From: Ye Li Date: Wed, 9 Mar 2016 08:13:48 +0000 (+0800) Subject: imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask X-Git-Tag: v2016.05-rc2~66^2~20 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b777789ebd193587a8e4700dce656523df821370;p=u-boot imx: mx6: Fix incorrect clear mmdc_ch0 handshake mask Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register the bit[17] for mmdc_ch0 is reserved and its proper state should be 1. When clear this bit, the periph_clk_sel cannot be set and that CDHIPR[periph_clk_sel_busy] handshake never clears. Signed-off-by: Ye Li Signed-off-by: Peng Fan Acked-by: Stefano Babic --- diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 91a3debe91..bdd41b07f4 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -278,7 +278,10 @@ static void clear_mmdc_ch_mask(void) reg = readl(&mxc_ccm->ccdr); /* Clear MMDC channel mask */ - reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); + if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK); + else + reg &= ~(MXC_CCM_CCDR_MMDC_CH1_HS_MASK | MXC_CCM_CCDR_MMDC_CH0_HS_MASK); writel(reg, &mxc_ccm->ccdr); }