From: stroese Date: Tue, 9 Dec 2003 14:54:43 +0000 (+0000) Subject: BUBINGA405EP port fixed. X-Git-Tag: LABEL_2006_03_12_0025~694 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=b828dda657dd26b5580c4a85e5680a5d16352a4c;p=u-boot BUBINGA405EP port fixed. --- diff --git a/board/bubinga405ep/bubinga405ep.c b/board/bubinga405ep/bubinga405ep.c index eb9baf4a38..8694ebe904 100644 --- a/board/bubinga405ep/bubinga405ep.c +++ b/board/bubinga405ep/bubinga405ep.c @@ -23,7 +23,6 @@ long int spd_sdram (void); #include -#include "bubinga405ep.h" #include @@ -82,18 +81,11 @@ int checkboard (void) unsigned char *s = getenv ("serial#"); unsigned char *e; - puts ("Board: "); - - if (!s || strncmp (s, "BUBINGA405EP", 9)) { - puts ("### No HW ID - assuming WALNUT405"); - } else { - for (e = s; *e; ++e) { - if (*e == ' ') - break; - } - for (; s < e; ++s) { - putc (*s); - } + puts ("Board: IBM 405EP Eval Board"); + + if (s != NULL) { + puts (", serial# "); + puts (s); } putc ('\n'); diff --git a/board/bubinga405ep/flash.c b/board/bubinga405ep/flash.c index 6a9907c016..d4bd7eef7e 100644 --- a/board/bubinga405ep/flash.c +++ b/board/bubinga405ep/flash.c @@ -101,6 +101,11 @@ unsigned long flash_init (void) FLASH_BASE0_PRELIM, FLASH_BASE0_PRELIM+CFG_MONITOR_LEN-1, &flash_info[0]); + /* Also protect sector containing initial power-up instruction */ + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, + 0xFFFFFFFF, + &flash_info[0]); size_b1 = 0 ; flash_info[0].size = size_b0; } @@ -143,6 +148,16 @@ unsigned long flash_init (void) base_b0+size_b0-CFG_MONITOR_LEN, base_b0+size_b0-1, &flash_info[0]); + /* Also protect sector containing initial power-up instruction */ + /* (flash_protect() checks address range - other call ignored) */ + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, + 0xFFFFFFFF, + &flash_info[0]); + (void)flash_protect(FLAG_PROTECT_SET, + 0xFFFFFFFC, + 0xFFFFFFFF, + &flash_info[1]); if (size_b1) { /* Re-do sizing to get full correct info */ @@ -493,18 +508,18 @@ int wait_for_DQ7(flash_info_t *info, int sect) volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *)(info->start[sect]); start = get_timer (0); - last = start; - while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return -1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; + last = 0; + while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc ('.'); + last = now; + } } - } return 0; } diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 215a925b93..e25101adbd 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1384,14 +1384,94 @@ trap_reloc: /**************************************************************************/ #ifdef CONFIG_405EP ppc405ep_init: + +#ifdef CONFIG_BUBINGA405EP + /* + * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate + * function) to support FPGA and NVRAM accesses below. + */ + + lis r3,GPIO0_OSRH@h /* config GPIO output select */ + ori r3,r3,GPIO0_OSRH@l + lis r4,CFG_GPIO0_OSRH@h + ori r4,r4,CFG_GPIO0_OSRH@l + stw r4,0(r3) + lis r3,GPIO0_OSRL@h + ori r3,r3,GPIO0_OSRL@l + lis r4,CFG_GPIO0_OSRL@h + ori r4,r4,CFG_GPIO0_OSRL@l + stw r4,0(r3) + + lis r3,GPIO0_ISR1H@h /* config GPIO input select */ + ori r3,r3,GPIO0_ISR1H@l + lis r4,CFG_GPIO0_ISR1H@h + ori r4,r4,CFG_GPIO0_ISR1H@l + stw r4,0(r3) + lis r3,GPIO0_ISR1L@h + ori r3,r3,GPIO0_ISR1L@l + lis r4,CFG_GPIO0_ISR1L@h + ori r4,r4,CFG_GPIO0_ISR1L@l + stw r4,0(r3) + + lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ + ori r3,r3,GPIO0_TSRH@l + lis r4,CFG_GPIO0_TSRH@h + ori r4,r4,CFG_GPIO0_TSRH@l + stw r4,0(r3) + lis r3,GPIO0_TSRL@h + ori r3,r3,GPIO0_TSRL@l + lis r4,CFG_GPIO0_TSRL@h + ori r4,r4,CFG_GPIO0_TSRL@l + stw r4,0(r3) + + lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ + ori r3,r3,GPIO0_TCR@l + lis r4,CFG_GPIO0_TCR@h + ori r4,r4,CFG_GPIO0_TCR@l + stw r4,0(r3) + + li r3,pb1ap /* program EBC bank 1 for RTC access */ + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1AP@h + ori r3,r3,CFG_EBC_PB1AP@l + mtdcr ebccfgd,r3 + li r3,pb1cr + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1CR@h + ori r3,r3,CFG_EBC_PB1CR@l + mtdcr ebccfgd,r3 + + li r3,pb1ap /* program EBC bank 1 for RTC access */ + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1AP@h + ori r3,r3,CFG_EBC_PB1AP@l + mtdcr ebccfgd,r3 + li r3,pb1cr + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB1CR@h + ori r3,r3,CFG_EBC_PB1CR@l + mtdcr ebccfgd,r3 + + li r3,pb4ap /* program EBC bank 4 for FPGA access */ + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB4AP@h + ori r3,r3,CFG_EBC_PB4AP@l + mtdcr ebccfgd,r3 + li r3,pb4cr + mtdcr ebccfga,r3 + lis r3,CFG_EBC_PB4CR@h + ori r3,r3,CFG_EBC_PB4CR@l + mtdcr ebccfgd,r3 +#endif + + addi r3,0,CPC0_PCI_HOST_CFG_EN +#ifdef CONFIG_BUBINGA405EP /* !----------------------------------------------------------------------- ! Check FPGA for PCI internal/external arbitration ! If board is set to internal arbitration, update cpc0_pci !----------------------------------------------------------------------- */ - addi r3,0,CPC0_PCI_HOST_CFG_EN -#ifdef CONFIG_BUBINGA405EP addis r5,r0,FPGA_REG1@h /* set offset for FPGA_REG1 */ ori r5,r5,FPGA_REG1@l lbz r5,0x0(r5) /* read to get PCI arb selection */ diff --git a/include/configs/BUBINGA405EP.h b/include/configs/BUBINGA405EP.h index 99fcbae169..a485e4e80f 100644 --- a/include/configs/BUBINGA405EP.h +++ b/include/configs/BUBINGA405EP.h @@ -30,6 +30,7 @@ /* Debug options */ /*#define __DEBUG_START_FROM_SRAM__ */ +/*#define DEBUG 1*/ /* @@ -148,13 +149,21 @@ */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_PCI | \ + CFG_CMD_CACHE | \ + CFG_CMD_DATE | \ + CFG_CMD_DHCP | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_I2C | \ CFG_CMD_IRQ | \ CFG_CMD_KGDB | \ - CFG_CMD_DHCP | \ - CFG_CMD_DATE | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF ) + CFG_CMD_MII | \ + CFG_CMD_NET | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + 0 ) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -207,6 +216,14 @@ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ #define CFG_I2C_SLAVE 0x7F +#define CFG_I2C_NOPROBES { 0x69 } /* avoid iprobe hangup (why?) */ +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */ + +#if (CONFIG_COMMANDS & CFG_CMD_EEPROM) +#define CFG_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */ +#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ +#endif + /*----------------------------------------------------------------------- * PCI stuff @@ -220,9 +237,11 @@ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ #define CONFIG_PCI_PNP /* do pci plug-and-play */ /* resource configuration */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */ #define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CFG_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */ #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ @@ -291,7 +310,7 @@ #define CFG_NVRAM_SIZE 0x1ff8 /* NVRAM size */ #ifdef CFG_ENV_IS_IN_NVRAM -#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */ +#define CFG_ENV_SIZE 0x0ff8 /* Size of Environment vars */ #define CFG_ENV_ADDR \ (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) /* Env */ #endif @@ -314,9 +333,6 @@ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ -/* Configuration Port location */ -#define CONFIG_PORT_ADDR 0xF0000500 - /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in data cache) */