From: RichardBarry Date: Wed, 23 Jan 2008 08:35:47 +0000 (+0000) Subject: UpdUpdate IAR projects to use Embedded Workbench V5.11. X-Git-Tag: V4.7.1~17 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=baa9ed196e2945d39b1487fbd47e7f089a534ee5;p=freertos UpdUpdate IAR projects to use Embedded Workbench V5.11. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@131 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h index 42b361533..f54e5ebff 100644 --- a/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h +++ b/Demo/ARM7_AT91SAM7S64_IAR/FreeRTOSConfig.h @@ -37,7 +37,7 @@ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H -#include +#include #include "Board.h" /*----------------------------------------------------------- diff --git a/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s new file mode 100644 index 000000000..12842e137 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s @@ -0,0 +1,302 @@ +;* ---------------------------------------------------------------------------- +;* ATMEL Microcontroller Software Support - ROUSSET - +;* ---------------------------------------------------------------------------- +;* Copyright (c) 2006, Atmel Corporation +; +;* All rights reserved. +;* +;* Redistribution and use in source and binary forms, with or without +;* modification, are permitted provided that the following conditions are met: +;* +;* - Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the disclaimer below. +;* +;* - Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the disclaimer below in the documentation and/or +;* other materials provided with the distribution. +;* +;* Atmel's name may not be used to endorse or promote products derived from +;* this software without specific prior written permission. +;* +;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* ---------------------------------------------------------------------------- + +;------------------------------------------------------------------------------ +; Include your AT91 Library files +;------------------------------------------------------------------------------ +#include "AT91SAM7X256_inc.h" +;------------------------------------------------------------------------------ + +#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE) +#define IRQ_STACK_SIZE 200 + ; 3 words to be saved per interrupt priority level + +; Mode, correspords to bits 0-5 in CPSR +MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + +I_BIT DEFINE 0x80 +F_BIT DEFINE 0x40 + +;------------------------------------------------------------------------------ +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;------------------------------------------------------------------------------ + SECTION .intvec:CODE:NOROOT(2) + PUBLIC __vector + PUBLIC __iar_program_start + EXTERN vPortYieldProcessor + + ARM +__vector: + ldr pc,[pc,#+24] ;; Reset +__und_handler: + ldr pc,[pc,#+24] ;; Undefined instructions +__swi_handler: + ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC) +__prefetch_handler: + ldr pc,[pc,#+24] ;; Prefetch abort +__data_handler: + ldr pc,[pc,#+24] ;; Data abort + DC32 0xFFFFFFFF ;; RESERVED +__irq_handler: + LDR PC, [PC, #-0xF20] +__fiq_handler: + ldr pc,[pc,#+24] ;; FIQ + + DC32 __iar_program_start + DC32 __und_handler + DC32 vPortYieldProcessor + DC32 __prefetch_handler + DC32 __data_handler + B . + DC32 IRQ_Handler_Entry + DC32 FIQ_Handler_Entry + +;------------------------------------------------------------------------------ +;- Manage exception: The exception must be ensure in ARM mode +;------------------------------------------------------------------------------ + SECTION text:CODE:NOROOT(2) + ARM +;------------------------------------------------------------------------------ +;- Function : FIQ_Handler_Entry +;- Treatments : FIQ Controller Interrupt Handler. +;- R8 is initialize in Cstartup +;- Called Functions : None only by FIQ +;------------------------------------------------------------------------------ +FIQ_Handler_Entry: + +;- Switch in SVC/User Mode to allow User Stack access for C code +; because the FIQ is not yet acknowledged + +;- Save and r0 in FIQ_Register + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | SVC_MODE +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, lr} + +;- Branch to the routine pointed by the AIC_FVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, lr} + +;- Leave Interrupts disabled and switch back in FIQ mode + msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE + +;- Restore the R0 ARM_MODE_SVC register + mov r0,r9 + +;- Restore the Program Counter using the LR_fiq directly in the PC + subs pc,lr,#4 +;------------------------------------------------------------------------------ +;- Function : IRQ_Handler_Entry +;- Treatments : IRQ Controller Interrupt Handler. +;- Called Functions : AIC_IVR[interrupt] +;------------------------------------------------------------------------------ +IRQ_Handler_Entry: +;------------------------- +;- Manage Exception Entry +;------------------------- +;- Adjust and save LR_irq in IRQ stack + sub lr, lr, #4 + stmfd sp!, {lr} + +;- Save r0 and SPSR (need to be saved for nested interrupt) + mrs r14, SPSR + stmfd sp!, {r0,r14} + +;- Write in the IVR to support Protect Mode +;- No effect in Normal Mode +;- De-assert the NIRQ and clear the source in Protect Mode + ldr r14, =AT91C_BASE_AIC + ldr r0 , [r14, #AIC_IVR] + str r14, [r14, #AIC_IVR] + +;- Enable Interrupt and Switch in Supervisor Mode + msr CPSR_c, #SVC_MODE + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, r14} + +;---------------------------------------------- +;- Branch to the routine pointed by the AIC_IVR +;---------------------------------------------- + mov r14, pc + bx r0 + +;---------------------------------------------- +;- Manage Exception Exit +;---------------------------------------------- +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, r14} + +;- Disable Interrupt and switch back in IRQ mode + msr CPSR_c, #I_BIT | IRQ_MODE + +;- Mark the End of Interrupt on the AIC + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_EOICR] + +;- Restore SPSR_irq and r0 from IRQ stack + ldmia sp!, {r0,r14} + msr SPSR_cxsf, r14 + +;- Restore adjusted LR_irq from IRQ stack directly in the PC + ldmia sp!, {pc}^ + +;------------------------------------------------------------------------------ +;- Exception Vectors +;------------------------------------------------------------------------------ + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + + ARM ; Always ARM mode after exeption + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + +;------------------------------------------------------------------------------ +; ?INIT +; Program entry. +;------------------------------------------------------------------------------ + + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION text:CODE:NOROOT(2) + REQUIRE __vector + EXTERN ?main + PUBLIC __iar_program_start + EXTERN AT91F_LowLevelInit + + +__iar_program_start: + +;------------------------------------------------------------------------------ +;- Low level Init is performed in a C function: AT91F_LowLevelInit +;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit +;------------------------------------------------------------------------------ + +;- Retrieve end of RAM address + + ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution + ldr r0,=AT91F_LowLevelInit + mov lr, pc + bx r0 ;- Branch on C function (with interworking) + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. + + mrs r0,cpsr ; Original PSR value + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SVC_MODE ; Set SVC mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#UND_MODE ; Set UND mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(UND_STACK) ; End of UND_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#ABT_MODE ; Set ABT mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#FIQ_MODE ; Set FIQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + ;- Init the FIQ register + ldr r8, =AT91C_BASE_AIC + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#IRQ_MODE ; Set IRQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SYS_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(CSTACK) ; End of CSTACK + + +#ifdef __ARMVFP__ +; Enable the VFP coprocessor. + mov r0, #0x40000000 ; Set EN bit in VFP + fmxr fpexc, r0 ; FPEXC, clear others. + +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. + mov r0, #0x01000000 ; Set FZ bit in VFP + fmxr fpscr, r0 ; FPSCR, clear others. +#endif + +; Add more initialization here + msr CPSR_c,#I_BIT | F_BIT | SVC_MODE + + +; Continue to ?main for more IAR specific system startup + + ldr r0,=?main + bx r0 + + END ;- Terminates the assembly of the last module in a file diff --git a/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf new file mode 100644 index 000000000..def0cf0a1 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_FLASH.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000100; +define symbol __ICFEDIT_region_ROM_end__ = 0x0000FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x00200000; +define symbol __ICFEDIT_region_RAM_end__ = 0x00203FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x4; +define symbol __ICFEDIT_size_undstack__ = 0x4; +define symbol __ICFEDIT_size_abtstack__ = 0x4; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd index 44815edc8..de6ec3f62 100644 --- a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd +++ b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -161,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -200,21 +257,13 @@ JLINK_ID 2 - 2 + 9 1 1 - - - + + + + + + + + + + + + + + + - MACRAIGOR_ID + LMIFTDI_ID 2 1 1 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + @@ -422,23 +566,23 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 @@ -446,7 +590,23 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 @@ -461,7 +621,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -610,6 +790,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -649,21 +866,13 @@ JLINK_ID 2 - 2 + 9 1 1 - - - + + + + + + + + + + + + + + + - MACRAIGOR_ID + LMIFTDI_ID 2 1 1 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + @@ -871,23 +1175,23 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 @@ -895,7 +1199,23 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 diff --git a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp index 63e626910..0b69546f9 100644 --- a/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp +++ b/Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + @@ -353,7 +316,7 @@ AARM 2 - 6 + 7 1 1 - - - + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -553,275 +534,234 @@ - XLINK - 2 + ILINK + 0 - 17 + 5 1 1 - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -840,15 +780,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + @@ -1183,7 +1086,7 @@ AARM 2 - 6 + 7 1 1 - - - + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -1382,275 +1303,234 @@ - XLINK - 2 + ILINK + 0 - 17 + 5 1 1 - - - - - - - - - - + - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -1727,7 +1607,7 @@ System Files - $PROJ_DIR$\SrcIAR\Cstartup.s79 + $PROJ_DIR$\SrcIAR\Cstartup.s $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt index cfa227533..0df6a20f1 100644 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt @@ -8,7 +8,7 @@ - 1912727 + 204272727 @@ -42,20 +42,20 @@ - 0 + 0TabID-18517-20319Debug LogDebug-Log0 - TextEditorE:\Dev\FreeRTOS\source\portable\iar\AtmelSAM7S64\lib_AT91SAM7S64.h06152480624806TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\USB\USBSample.c02891049810498TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\main.c014164206420TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\port.c011754935493TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\serial\serial.c013255475547TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c08236503650TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7902722262226TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\integer.c07740244024TextEditorE:\Dev\FreeRTOS\Source\tasks.c08232928929289TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\portasm.s7900519519TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\portmacro.h05700TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h02400TextEditorE:\Dev\FreeRTOS\Demo\Common\Minimal\semtest.c016678567856120100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h02517261726TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7901915271527TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s052325032502TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\AtmelSAM7S64\port.c0217834583450100000010000001 - IarIdePM1DebuggerGui1-2-21072265-2-20000166875959785 + iaridepm.enu1debuggergui.enu1-2-2740278-2-20000166667755601-2-21981682-2-216842001002381203666119048203666 diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni index fc509a42a..78681fc3a 100644 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni @@ -9,6 +9,20 @@ Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 [Low Level] Pipeline mode=1 Initialized=0 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -20,3 +34,6 @@ LogFile=_ "" mode=0 [Breakpoints] Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt index 2910d9720..ca9ef47b3 100644 --- a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt @@ -3,7 +3,7 @@ - rtosdemo/Flash Debug + rtosdemo/Flash Bin @@ -11,7 +11,7 @@ - 221272727 + 236272727 18115530877 @@ -28,7 +28,7 @@ - + TabID-17425-14382 @@ -36,11 +36,11 @@ Workspace - rtosdemortosdemo/Demo Sourcertosdemo/Scheduler Sourcertosdemo/System Files + rtosdemo - 0 + 0 TabID-4084-16269 @@ -56,20 +56,20 @@ - 0 + 0 - TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\FreeRTOSConfig.h01800TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Board.h00952969TextEditorE:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\SrcIAR\Cstartup.s7901426503651720100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\main.c000000100000010000001 - iaridepm1-2-2659295-2-230301875026809185625590705-2-24131602-2-2160441510025003708661875026809 + iaridepm.enu1-2-2576310-2-232261904826477185714588595-2-23621682-2-2168436410023813706721904826477 diff --git a/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par new file mode 100644 index 000000000..dbc316aa7 --- /dev/null +++ b/Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo_lnk.par @@ -0,0 +1,17 @@ +// IAR XLINK Setup +// Autogenerated file - do not edit +% +setrangelist($evec_ADR,[0-3F]); +setrangelist($internal_ROM,[8000-FFFFF]); +setrangelist($external_ROM,[]); +setrangelist($internal_RAM,[100000-7FFFFF]); +setrangelist($external_RAM,[]); +$CSTACK_SIZE=200; +$IRQSTACK_SIZE=100; +$HEAP_SIZE=4; +$COMMANDS=""; +$STACK_LOCATION="Internal RAM"; +$IRQSTACK_LOCATION="Internal RAM"; +$HEAP_LOCATION="Internal RAM"; +$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_AT91SAM7S64_IAR\resource\at91SAM7S64_NoRemap.xcl"; +% \ No newline at end of file diff --git a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h index 778a2060b..0466957ea 100644 --- a/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h +++ b/Demo/ARM7_LPC2129_IAR/FreeRTOSConfig.h @@ -38,7 +38,7 @@ #define FREERTOS_CONFIG_H /* Hardware specifics. */ -#include +#include /*----------------------------------------------------------- * Application specific definitions. diff --git a/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s b/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s new file mode 100644 index 000000000..062d7dbf2 --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/SrcIAR/lpc2xxx_cstartup.s @@ -0,0 +1,189 @@ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Part one of the system initialization code, +;; contains low-level +;; initialization. +;; +;; Copyright 2006 IAR Systems. All rights reserved. +;; +;; $Revision: 10608 $ +;; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + +; +; The module in this file are included in the libraries, and may be +; replaced by any user-defined modules that define the PUBLIC symbol +; __iar_program_start or a user defined start symbol. +; +; To override the cstartup defined in the library, simply add your +; modified version to the workbench project. + + SECTION .intvec:CODE:NOROOT(2) + + PUBLIC __vector + PUBLIC __vector_0x14 + PUBLIC __iar_program_start + EXTERN vPortYieldProcessor + + ARM +__vector: + ;; + ldr pc,[pc,#+24] ;; Reset + ldr pc,[pc,#+24] ;; Undefined instructions +;; ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC) + b vPortYieldProcessor + ldr pc,[pc,#+24] ;; Prefetch abort + ldr pc,[pc,#+24] ;; Data abort +__vector_0x14 + DC32 0 ;; RESERVED + ldr pc, [PC, #-0xFF0] ;; IRQ + ldr pc,[pc,#+24] ;; FIQ + + DC32 __iar_program_start ;; Reset + DC32 undef_handler ;; Undefined instructions + DC32 0 ;; Software interrupt (SWI/SVC) + DC32 prefetch_handler ;; Prefetch abort + DC32 data_handler ;; Data abort + DC32 0 ;; RESERVED + DC32 0 ;; IRQ + DC32 fiq_handler ;; FIQ + +undef_handler + b undef_handler + +prefetch_handler + b prefetch_handler + +data_handler + b data_handler + +fiq_handler + b fiq_handler +; -------------------------------------------------- +; ?cstartup -- low-level system initialization code. +; +; After a reser execution starts here, the mode is ARM, supervisor +; with interrupts disabled. +; + + + + SECTION .text:CODE:NOROOT(2) + +; PUBLIC ?cstartup + EXTERN ?main + REQUIRE __vector + + ARM + +__iar_program_start: +?cstartup: + +; +; Add initialization needed before setup of stackpointers here. +; + +; Errata MAM.1Incorrect read of data from SRAM after Reset and MAM +; is not enabled or partially enabled. +; Work-around: User code should enable the MAM after Reset and before +; any RAM accesses +MAMCR DEFINE 0xE01FC000 ; MAM Control Register +MAMTIM DEFINE 0xE01FC004 ; MAM Timing register + + ldr r0,=MAMCR + ldr r1,=MAMTIM + ldr r2,=0 + str r2,[r0] + ldr r2,=3 ; 1 < 20 MHz; 20 MHz < 2 < 40 MHz; 40MHz > 3 + str r2,[r1] + ldr r2,=2 + str r2,[r0] + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. +; +; -------------------- +; Mode, correspords to bits 0-5 in CPSR +MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + + MRS r0, cpsr ; Original PSR value + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #ABT_MODE ; Set ABT mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(ABT_STACK) ; End of ABT_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #UND_MODE ; Set UND mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(UND_STACK) ; End of UND_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #FIQ_MODE ; Set FIQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK + + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK + + BIC r0 ,r0, #MODE_BITS ; Clear the mode bits + ORR r0 ,r0, #SYS_MODE ; Set System mode bits + MSR cpsr_c, r0 ; Change the mode + LDR sp, =SFE(CSTACK) ; End of CSTACK + +#ifdef __ARMVFP__ + ;; Enable the VFP coprocessor. + + MOV r0, #0x40000000 ; Set EN bit in VFP + FMXR fpexc, r0 ; FPEXC, clear others. + +; +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. +; + + MOV r0, #0x01000000 ; Set FZ bit in VFP + FMXR fpscr, r0 ; FPSCR, clear others. +#endif + +; +; Add more initialization here +; + BIC r0, r0, #MODE_BITS ; Clear the mode bits + ORR r0, r0, #SVC_MODE ; Set SVC mode bits + MSR cpsr_c, r0 ; Change the mode + +; Continue to ?main for C-level initialization. + + LDR r0, =?main + BX r0 + + END diff --git a/Demo/ARM7_LPC2129_IAR/main.c b/Demo/ARM7_LPC2129_IAR/main.c index a98655298..91821648e 100644 --- a/Demo/ARM7_LPC2129_IAR/main.c +++ b/Demo/ARM7_LPC2129_IAR/main.c @@ -35,9 +35,9 @@ */ -/* +/* NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is + The processor MUST be in supervisor mode when vTaskStartScheduler is called. The demo applications included in the FreeRTOS.org download switch to supervisor mode prior to main being called. If you are not using one of these demo application projects then ensure Supervisor mode is used. @@ -159,9 +159,9 @@ void main( void ) xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); /* Start the scheduler. - + NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode. - The processor MUST be in supervisor mode when vTaskStartScheduler is + The processor MUST be in supervisor mode when vTaskStartScheduler is called. The demo applications included in the FreeRTOS.org download switch to supervisor mode prior to main being called. If you are not using one of these demo application projects then ensure Supervisor mode is used here. diff --git a/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf b/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf new file mode 100644 index 000000000..4c0e3c8ed --- /dev/null +++ b/Demo/ARM7_LPC2129_IAR/resource/lpc212x.icf @@ -0,0 +1,47 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000044; +define symbol __ICFEDIT_region_ROM_end__ = 0x3FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x40000040; +define symbol __ICFEDIT_region_RAM_end__ = 0x40003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x00; +define symbol __ICFEDIT_size_undstack__ = 0x0; +define symbol __ICFEDIT_size_abtstack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x0; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; + + + + + diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd index 41a42a723..e75220176 100644 --- a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd +++ b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -161,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -200,21 +257,13 @@ JLINK_ID 2 - 2 + 9 1 1 - - - + + + + + + + + + + + + + + + - MACRAIGOR_ID + LMIFTDI_ID 2 1 1 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + @@ -422,35 +566,47 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 @@ -465,7 +621,7 @@ C-SPY 2 - 13 + 15 1 0 + + ARMSIM_ID 2 - 0 + 1 1 0 + + + @@ -614,6 +790,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + IARROM_ID 2 @@ -653,21 +866,13 @@ JLINK_ID 2 - 2 + 9 1 0 - - - + + + + + + + + + + + + + + + - MACRAIGOR_ID + LMIFTDI_ID 2 1 1 0 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 0 + + + @@ -875,37 +1175,49 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + diff --git a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp index 9d363c963..88b0f2936 100644 --- a/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp +++ b/Demo/ARM7_LPC2129_IAR/rtosdemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + AARM 2 - 6 + 7 1 1 - - - + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -554,275 +535,234 @@ - XLINK - 2 + ILINK + 0 - 17 + 5 1 1 - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -841,15 +781,11 @@ 0 General - 2 + 3 - 9 + 14 1 0 - - - - + + + ICCARM 2 - 13 + 19 1 0 - - - - - - - - - - - - - - + + + + + + AARM 2 - 6 + 7 1 0 - - - + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + CUSTOM 3 @@ -1385,275 +1306,234 @@ - XLINK - 2 + ILINK + 0 - 17 + 5 1 0 - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 0 @@ -1724,7 +1604,7 @@ System Files - $PROJ_DIR$\SrcIAR\cstartup.s79 + $PROJ_DIR$\SrcIAR\lpc2xxx_cstartup.s diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt index cee08cd82..74c9f8d5a 100644 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt +++ b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dbgdt @@ -8,13 +8,13 @@ - 138272727 + 181272727 - 200100 + 200010 300Build 300Debug-Log @@ -48,14 +48,14 @@ - TextEditorE:\Dev\FreeRTOS\Source\list.c015964866613TextEditorE:\Dev\FreeRTOS\Source\include\list.h0000TextEditorE:\Dev\FreeRTOS\Source\tasks.c017269426959TextEditorE:\Dev\FreeRTOS\Source\include\task.h05022822291TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s790000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h0000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h05225222531TextEditorE:\Dev\FreeRTOS\Source\queue.c014875937593TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c016671727172TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c0752927293890100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\FreeRTOSConfig.h02517461746TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h02517151715TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\LPC2000\port.c019782008200TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\SrcIAR\lpc2xxx_cstartup.s085286628663TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c014360366036TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c014064481144811TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portasm.s7902916891689TextEditorC:\E\Dev\FreeRTOS\Demo\Common\Minimal\flash.c011743784392TextEditorC:\E\Dev\FreeRTOS\Source\queue.c08693220732207TextEditorC:\E\Dev\FreeRTOS\Demo\Common\Minimal\integer.c011354545454TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s7900307307TextEditorC:\E\Dev\FreeRTOS\Demo\Common\Minimal\comtest.c013868046804TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serial.c0131549754970100000010000001 - iaridepm1debuggergui1-2-2739212-2-20000133750662198-2-23331602-2-21604335100250029937492500132260 + iaridepm.enu1debuggergui.enu1-2-2646255-2-20000183571659878-2-22921402-2-21404294100285729938992857132383 diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni index b3fefed21..e14d72694 100644 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni +++ b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.dni @@ -9,6 +9,27 @@ Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 [Low Level] Pipeline mode=1 Initialized=0 +[Interrupts] +Enabled=1 +[MemoryMap] +Enabled=0 +TypeVolition=1 +UnspecRange=1 +ActionState=1 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -19,15 +40,7 @@ LogFile=_ "" [Disassemble mode] mode=0 [Breakpoints] -Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\queue.c}.179.3@1" 1 0 0 0 "" 0 "" -Count=1 -[Interrupts] -Enabled=1 -[MemoryMap] -Enabled=0 -TypeVolition=1 -UnspecRange=1 -ActionState=1 +Count=0 [TraceHelper] Enabled=0 ShowSource=1 diff --git a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt index 90d8027fe..b686eb5c1 100644 --- a/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt +++ b/Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt @@ -11,7 +11,7 @@ - 229272727 + 191272727 18115530877 @@ -28,7 +28,7 @@ - + TabID-17425-14382 @@ -36,24 +36,24 @@ Workspace - rtosdemortosdemo/Scheduler Sourcertosdemo/System Files + rtosdemortosdemo/Demo Sourcertosdemo/System Files - 0TabID-22109-27077BuildBuildTabID-12074-10873BreakpointsBreakpointsTabID-18349-15872Debug LogDebug-LogTabID-30013-18825Find in FilesFind-in-Files0 + 0TabID-22109-27077BuildBuildTabID-12074-10873BreakpointsBreakpointsTabID-18349-15872Debug LogDebug-LogTabID-30013-18825Find in FilesFind-in-Files0 - TextEditorE:\Dev\FreeRTOS\Source\list.c015964866613TextEditorE:\Dev\FreeRTOS\Source\include\list.h0000TextEditorE:\Dev\FreeRTOS\Source\tasks.c017269426959TextEditorE:\Dev\FreeRTOS\Source\include\task.h05022822291TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s790000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h0000TextEditorE:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h05225222531TextEditorE:\Dev\FreeRTOS\Source\queue.c014875937593TextEditorE:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c016671727172TextEditorE:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c0752927293890100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c01436036603600100000010000001 - iaridepm1-2-2944303-2-20000190625845397-2-21281602-2-2160413010025001161755500078641 + iaridepm.enu1-2-2605265-2-20000190714618126-2-23331402-2-2140433510028573411415500078411 diff --git a/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h b/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h index 43e2e4144..ac4a01586 100644 --- a/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h +++ b/Demo/ARM7_LPC2138_Rowley/FreeRTOSConfig.h @@ -72,7 +72,8 @@ the CPU frequency. */ #define configUSE_TRACE_FACILITY 1 #define configUSE_16_BIT_TICKS 0 #define configIDLE_SHOULD_YIELD 1 -#define configUSE_MUTEXES 0 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 diff --git a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp b/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp index 92c2bdc0f..175dd09b1 100644 --- a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp +++ b/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzp @@ -1,55 +1,56 @@ - - - - - - - - - - + + + + + + + + + + - - - - - + + + + + - + - - - - - - - - - - + + + + + + + + + + - + + - - - - - + + + + + - - + + - - diff --git a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs b/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs index 0d0ff0a1d..1ac46d239 100644 --- a/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs +++ b/Demo/ARM7_LPC2138_Rowley/RTOSDemo.hzs @@ -5,22 +5,21 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + @@ -35,28 +34,38 @@ + + + + + + + + + + - + - + - + - + - + @@ -67,8 +76,26 @@ - + + + + + - - + + + + + + + + + + + + + + + + diff --git a/Demo/ARM7_LPC2138_Rowley/main.c b/Demo/ARM7_LPC2138_Rowley/main.c index 4770321ed..4dae2144c 100644 --- a/Demo/ARM7_LPC2138_Rowley/main.c +++ b/Demo/ARM7_LPC2138_Rowley/main.c @@ -81,6 +81,7 @@ #include "integer.h" #include "PollQ.h" #include "blocktim.h" +#include "recmutex.h" /* Hardware configuration definitions. */ #define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 ) @@ -171,6 +172,7 @@ int main( void ) vStartDynamicPriorityTasks(); vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); vCreateBlockTimeTasks(); + vStartRecursiveMutexTasks(); /* Start the tasks defined within this file. */ xTaskCreate( vLEDTask, "LED", configMINIMAL_STACK_SIZE, NULL, mainLED_TASK_PRIORITY, NULL ); @@ -259,6 +261,11 @@ const portCHAR * const pcFailMessage = "FAIL\n"; xErrorOccurred = pdTRUE; } + if( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + /* Send either a pass or fail message. If an error is found it is never cleared again. */ if( xErrorOccurred == pdTRUE ) diff --git a/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h b/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h index c5c41912f..b620c45bc 100644 --- a/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h +++ b/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/FreeRTOSConfig.h @@ -48,7 +48,7 @@ #define configUSE_PREEMPTION 1 #define configUSE_IDLE_HOOK 0 #define configUSE_TICK_HOOK 1 -#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 57600000 ) /* =12Mhz xtal multiplied by 5 using the PLL. */ +#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 ) /* =12Mhz xtal multiplied by 5 using the PLL. */ #define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 ) #define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 104 ) diff --git a/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c b/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c index 16c6ec263..f81a99dc2 100644 --- a/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c +++ b/Demo/ARM7_LPC2368_Eclipse/RTOSDemo/main.c @@ -90,7 +90,7 @@ /* Constants to setup the PLL. */ #define mainPLL_MUL ( ( unsigned portLONG ) ( 12 - 1 ) ) #define mainPLL_DIV ( ( unsigned portLONG ) 0x0000 ) -#define mainCPU_CLK_DIV ( ( unsigned portLONG ) 0x0004 ) +#define mainCPU_CLK_DIV ( ( unsigned portLONG ) 0x0003 ) #define mainPLL_ENABLE ( ( unsigned portLONG ) 0x0001 ) #define mainPLL_CONNECT ( ( ( unsigned portLONG ) 0x0002 ) | mainPLL_ENABLE ) #define mainPLL_FEED_BYTE1 ( ( unsigned portLONG ) 0xaa ) @@ -266,12 +266,18 @@ static void prvSetupHardware( void ) PLLFEED = mainPLL_FEED_BYTE2; while( !( PLLSTAT & mainPLL_CONNECTED ) ); - /* Setup and turn on the MAM. Three cycle access is used due to the fast + /* + This code is commented out as the MAM does not work on the original revision + LPC2368 chips. If using Rev B chips then you can increase the speed though + the use of the MAM. + + Setup and turn on the MAM. Three cycle access is used due to the fast PLL used. It is possible faster overall performance could be obtained by - tuning the MAM and PLL settings. */ + tuning the MAM and PLL settings. MAMCR = 0; MAMTIM = mainMAM_TIM_3; MAMCR = mainMAM_MODE_FULL; + */ /* Setup the led's on the MCB2300 board */ vParTestInitialise(); diff --git a/Demo/ARM7_STR71x_IAR/71x_init.s b/Demo/ARM7_STR71x_IAR/71x_init.s new file mode 100644 index 000000000..b53e1e52b --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/71x_init.s @@ -0,0 +1,297 @@ +;******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +;* File Name : 71x_init.s +;* Author : MCD Application Team +;* Date First Issued : 06/23/2004 +;* Description : This is the first code executed after RESET. +;* This code used to initialize system stacks +;* and critical peripherals before entering the C code. +;******************************************************************************* +;* History: +;* 13/01/2006 : V3.1 +;* 24/05/2005 : V3.0 +;* 30/11/2004 : V2.0 +;* 14/07/2004 : V1.3 +;* 01/01/2004 : V1.2 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ + + +; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UNDEF EQU 0x1B +Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + +EIC_Base_addr EQU 0xFFFFF800; EIC base address +ICR_off_addr EQU 0x00 ; Interrupt Control register offset +CIPR_off_addr EQU 0x08 ; Current Interrupt Priority Register offset +IVR_off_addr EQU 0x18 ; Interrupt Vector Register offset +FIR_off_addr EQU 0x1C ; Fast Interrupt Register offset +IER_off_addr EQU 0x20 ; Interrupt Enable Register offset +IPR_off_addr EQU 0x40 ; Interrupt Pending Bit Register offset +SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0 + +EMI_Base_addr EQU 0x6C000000; EMI base address +BCON0_off_addr EQU 0x00 ; Bank 0 configuration register offset +BCON1_off_addr EQU 0x04 ; Bank 1 configuration register offset +BCON2_off_addr EQU 0x08 ; Bank 2 configuration register offset +BCON3_off_addr EQU 0x0C ; Bank 3 configuration register offset + +EMI_ENABLE EQU 0x8000 +EMI_SIZE_16 EQU 0x0001 + +GPIO2_Base_addr EQU 0xE0005000; GPIO2 base address +PC0_off_addr EQU 0x00 ; Port Configuration Register 0 offset +PC1_off_addr EQU 0x04 ; Port Configuration Register 1 offset +PC2_off_addr EQU 0x08 ; Port Configuration Register 2 offset +PD_off_addr EQU 0x0C ; Port Data Register offset + +CPM_Base_addr EQU 0xA0000040; CPM Base Address +BOOTCR_off_addr EQU 0x10 ; CPM - Boot Configuration Register +FLASH_mask EQU 0x0000 ; to remap FLASH at 0x0 +RAM_mask EQU 0x0002 ; to remap RAM at 0x0 + +;|----------------------------------------------------------------------------------| +;| - APB Bridge (System Peripheral) | +;|----------------------------------------------------------------------------------| +APB1_base_addr EQU 0xC0000000 ; APB Bridge1 Base Address +APB2_base_addr EQU 0xE0000000 ; APB Bridge2 Base Address +CKDIS_off_addr EQU 0x10 ; APB Bridge1 - Clock Disable Register +SWRES_off_addr EQU 0x14 ; APB Bridge1 - Software Reset Register +CKDIS1_config_all EQU 0x27FB ; To enable/disable clock of all APB1's peripherals +SWRES1_config_all EQU 0x27FB ; To reset all APB1's peripherals +CKDIS2_config_all EQU 0x7FDD ; To enable/disable clock of all APB2's peripherals +SWRES2_config_all EQU 0x7FDD ; To reset all APB2's peripherals + + + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .text:CODE(2) + PUBLIC __iar_program_start + EXTERN ?main + EXTERN ?main + CODE32 + + +;******************************************************************************* +;******* -- MACROS -- ******* +;******************************************************************************* +;******************************************************************************* +;* Macro Name : EMI_INIT +;* Description : This macro Initialize EMI bank 1: 16-bit 7 wait state +;* Input : None. +;* Output : None. +;******************************************************************************* +EMI_INIT MACRO + LDR r0, =GPIO2_Base_addr ; Configure P2.0 -> 3 in AF_PP mode + LDR r2, [r0, #PC0_off_addr] + ORR r2, r2,#0x0000000F + STR r2, [r0, #PC0_off_addr] + LDR r2, [r0, #PC1_off_addr] + ORR r2, r2,#0x0000000F + STR r2, [r0, #PC1_off_addr] + LDR r2, [r0, #PC2_off_addr] + ORR r2, r2,#0x0000000F + STR r2, [r0, #PC2_off_addr] + LDR r0, =EMI_Base_addr + LDR r1, =0x18|EMI_ENABLE|EMI_SIZE_16 + STR r1, [r0, #BCON1_off_addr] ; Enable bank 1 16-bit 7 wait state + ENDM +;******************************************************************************* +;* Macro Name : EIC_INIT +;* Description : This macro Initialize the EIC as following : +; - IRQ disabled +; - FIQ disabled +; - IVR contain the load PC opcode (0xE59FFXXX) +; - Current priority level equal to 0 +; - All channels are disabled +; - All channels priority equal to 0 +; - All SIR registers contain offset to the related IRQ +; table entry +;* Input : None. +;* Output : None. +;******************************************************************************* +EIC_INIT MACRO + + LDR r3, =EIC_Base_addr + LDR r4, =0xE59F0000 + STR r4, [r3, #IVR_off_addr]; Write the LDR pc,[pc,#offset] + ; instruction code in IVR[31:16] + LDR r2, =32 ; 32 Channel to initialize + LDR r0, =T0TIMI_Addr ; Read the address of the IRQs + ; address table + LDR r1, =0x00000FFF + AND r0,r0,r1 + LDR r5, =SIR0_off_addr ; Read SIR0 address + SUB r4,r0,#8 ; subtract 8 for prefetch + LDR r1, =0xF7E8 ; Add the offset from IVR to 0x00000000 + ; address(IVR address + 7E8 = 0x00000000) + ; 0xF7E8 used to complete the + ; LDR pc,[pc,#offset] opcode (0xE59FFXXX) + ADD r1,r4,r1 ; Compute the jump offset from IVR to the + ; IRQ table entry. +EIC_INI MOV r4, r1, LSL #16 ; Left shift the result + STR r4, [r3, r5] ; Store the result in SIRx register + ADD r1, r1, #4 ; Next IRQ address + ADD r5, r5, #4 ; Next SIR + SUBS r2, r2, #1 ; Decrement the number of SIR registers + ; to initialize + BNE EIC_INI ; If more then continue + ENDM +;******************************************************************************* +;* Macro Name : PERIPHERAL_INIT +;* Description : This macro reset all device peripherals. +;* Input : None. +;* Output : None. +;******************************************************************************* +PERIPHERAL_INIT MACRO + + LDR r1, =APB1_base_addr ; r0= APB1 base address + LDR r2, =APB2_base_addr ; r0= APB2 base address + LDR r0, =CKDIS1_config_all + STRH r0, [r1, #CKDIS_off_addr]; Clock Disabling for all APB1 peripherals + LDR r0, =CKDIS2_config_all + STRH r0, [r2, #CKDIS_off_addr]; Clock Disabling for all APB2 peripherals + LDR r0, =SWRES1_config_all + STRH r0, [r1, #SWRES_off_addr]; Keep all APB1 peripherals under reset + LDR r0, =SWRES2_config_all + STRH r0, [r2, #SWRES_off_addr]; Keep all APB2 peripherals under reset + MOV r7, #10 ; Wait that the selected macrocells exit from reset +loop1 SUBS r7, r7, #1 + BNE loop1 + MOV r0, #0 + STRH r0, [r1, #SWRES_off_addr]; Enable all all APB1 peripherals + STRH r0, [r2, #SWRES_off_addr]; Enable all all APB2 peripherals + STRH r0, [r1, #CKDIS_off_addr]; Clock Enabling for all APB1 peripherals + STRH r0, [r2, #CKDIS_off_addr]; Clock Enabling for all APB2 peripherals + MOV r7, #10 ; Wait that the selected macrocells exit from reset +loop2 SUBS r7, r7, #1 + BNE loop2 + ENDM +;******************************************************************************************** + +; define remapping +; If you need to remap memory before entring the main program +; uncomment next ligne +; #define remapping + +; Then define which memory to remap to address 0x00000000 +; Uncomment next line if you want to remap RAM +; #define remap_ram + +; Uncomment next line if you want to remap FLASH +; #define remap_flash + + + IMPORT T0TIMI_Addr +__iar_program_start + LDR pc, =NextInst +NextInst + NOP ; Wait for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + MSR CPSR_c, #Mode_ABT|F_Bit|I_Bit + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + MSR CPSR_c, #Mode_UNDEF|F_Bit|I_Bit + ldr sp,=SFE(UND_STACK) ; End of UNDEF_STACK + + MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + + +; Uncomment next ligne if you need to reset all device pripherals + ; PERIPHERAL_INIT ; Reset all device peripherals + +; Uncomment next ligne if you need to enable the EMI Bank 1 + ; EMI_INIT ; Initialize EIM Bank 1 + +;Uncomment next ligne if you need to initialize the EIC + EIC_INIT ; Initialize EIC + +;****************************************************************************** +;REMAPPING +;Description : Remapping memory whether RAM,FLASH +; at Address 0x0 after the application has started executing. +; Remapping is generally done to allow RAM to replace FLASH +; at 0x0. +; the remapping of RAM allow copying of vector table into RAM +; To enable the memory remapping uncomment: (see above) +; #define remapping to enable memory remapping +; AND +; #define remap_ram to remap RAM +; OR +; #define remap_flash to remap FLASH +;****************************************************************************** +#ifdef remapping + #ifdef remap_flash + MOV r0, #FLASH_mask + #endif + #ifdef remap_ram + MOV r0, #RAM_mask + #endif + + LDR r1, =CPM_Base_addr + LDRH r2, [r1, #BOOTCR_off_addr]; Read BOOTCR Register + BIC r2, r2, #0x03 ; Reset the two LSB bits of BOOTCR + ORR r2, r2, r0 ; change the two LSB bits of BOOTCR + STRH r2, [r1, #BOOTCR_off_addr]; Write BOOTCR Register +#endif + + MSR CPSR_c, #Mode_FIQ|I_Bit; Change to FIQ mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + + MSR CPSR_c, #Mode_IRQ|I_Bit; Change to IRQ mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + MSR CPSR_c, #Mode_SYS ; Change to system mode, Enable IRQ and FIQ + ldr sp,=SFE(CSTACK) ; End of CSTACK(user) + + + +; --- Now branches to a C lib function that copies RO data from their +; load region to their execute region, create the RW and ZI regions +; then jumps to user C main program. + + ; main() must be called from Supervisor mode + MSR CPSR_c, #Mode_SVC|F_Bit|I_Bit + + b ?main ; Note : use B not BL, because an application will + ; never return this way + + LTORG + + END +;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE**** diff --git a/Demo/ARM7_STR71x_IAR/71x_vect.s b/Demo/ARM7_STR71x_IAR/71x_vect.s new file mode 100644 index 000000000..da2dd6ab8 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/71x_vect.s @@ -0,0 +1,253 @@ +#include "FreeRTOSConfig.h" +;******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +;* File Name : 71x_vect.s +;* Author : MCD Application Team +;* Date First Issued : 16/05/2003 +;* Description : This file used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions handlers. +;******************************************************************************* +;* History: +;* 13/01/2006 : V3.1 +;* 24/05/2005 : V3.0 +;* 30/11/2004 : V2.0 +;* 14/07/2004 : V1.3 +;* 01/01/2004 : V1.2 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. +; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;*******************************************************************************/ + + MODULE ?RESET + SECTION .intvec:CODE(2) + CODE32 + +EIC_base_addr EQU 0xFFFFF800; EIC base address. +CICR_off_addr EQU 0x04 ; Current Interrupt Channel Register. +IVR_off_addr EQU 0x18 ; Interrupt Vector Register. +IPR_off_addr EQU 0x40 ; Interrupt Pending Register. + + +;******************************************************************************* +; Import the __iar_program_start address from 71x_init.s +;******************************************************************************* + + IMPORT __iar_program_start + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT Undefined_Handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT FIQ_Handler + +;******************************************************************************* +; Import IRQ handlers from 71x_it.c +;******************************************************************************* + + IMPORT Default_Handler + IMPORT vPortYieldProcessor + IMPORT vSerialISREntry + IMPORT vPortPreemptiveTickISR + IMPORT vPortNonPreemptiveTick + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + + EXPORT T0TIMI_Addr + +;******************************************************************************* +; Exception vectors +;******************************************************************************* +IVR_ADDR DEFINE 0xFFFFF818 + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, =IVR_ADDR + LDR PC, FIQ_Addr + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __iar_program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD 0 ; Direct vectors are used. See the STR75x demo for an alternative implementation +FIQ_Addr DCD FIQHandler + +;******************************************************************************* +; Peripherals IRQ handlers address table +;******************************************************************************* + +T0TIMI_Addr DCD Default_Handler +FLASH_Addr DCD Default_Handler +RCCU_Addr DCD Default_Handler +RTC_Addr DCD Default_Handler +#if configUSE_PREEMPTION == 0 +WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used. +#else +WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used. +#endif +XTI_Addr DCD Default_Handler +USBHP_Addr DCD Default_Handler +I2C0ITERR_Addr DCD Default_Handler +I2C1ITERR_ADDR DCD Default_Handler +UART0_Addr DCD vSerialISREntry +UART1_Addr DCD Default_Handler +UART2_ADDR DCD Default_Handler +UART3_ADDR DCD Default_Handler +BSPI0_ADDR DCD Default_Handler +BSPI1_Addr DCD Default_Handler +I2C0_Addr DCD Default_Handler +I2C1_Addr DCD Default_Handler +CAN_Addr DCD Default_Handler +ADC12_Addr DCD Default_Handler +T1TIMI_Addr DCD Default_Handler +T2TIMI_Addr DCD Default_Handler +T3TIMI_Addr DCD Default_Handler + DCD 0 ; reserved + DCD 0 ; reserved + DCD 0 ; reserved +HDLC_Addr DCD Default_Handler +USBLP_Addr DCD Default_Handler + DCD 0 ; reserved + DCD 0 ; reserved +T0TOI_Addr DCD Default_Handler +T0OC1_Addr DCD Default_Handler +T0OC2_Addr DCD Default_Handler + + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + +;******************************************************************************* +;* Macro Name : SaveContext +;* Description : This macro used to save the context before entering +; an exception handler. +;* Input : The range of registers to store. +;* Output : none +;******************************************************************************* + +SaveContext MACRO reg1,reg2 + + STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return + ; address lr_ mode into the stack. + MRS r1,spsr ; Save the spsr_mode into r1. + STMFD sp!,{r1} ; Save spsr. + ENDM + +;******************************************************************************* +;* Macro Name : RestoreContext +;* Description : This macro used to restore the context to return from +; an exception handler and continue the program execution. +;* Input : The range of registers to restore. +;* Output : none +;******************************************************************************* + +RestoreContext MACRO reg1,reg2 + + LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. + MSR spsr_cxsf,r1 ; Restore spsr_mode. + LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... + ; ...the exception interrupt. + ENDM + +;******************************************************************************* +;* Function Name : UndefinedHandler +;* Description : This function called when undefined instruction +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +UndefinedHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ und and spsr_und. + ldr r0,=Undefined_Handler + ldr lr,=Undefined_Handler_end + bx r0 ; Branch to Undefined_Handler +Undefined_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the undefined instruction. + + +;******************************************************************************* +;* Function Name : PrefetchAbortHandler +;* Description : This function called when Prefetch Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +PrefetchAbortHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_abt and spsr_abt. + ldr r0,=Prefetch_Handler + ldr lr,=Prefetch_Handler_end + + bx r0 ; Branch to Prefetch_Handler. +Prefetch_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the prefetch abort exception. + +;******************************************************************************* +;* Function Name : DataAbortHandler +;* Description : This function is called when Data Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +DataAbortHandler + SUB lr,lr,#8 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ abt and spsr_abt. + ldr r0,=Abort_Handler + ldr lr,=Abort_Handler_end + + bx r0 ; Branch to Abort_Handler. +Abort_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the data abort exception. + +;******************************************************************************* +;* Function Name : FIQHandler +;* Description : This function is called when FIQ +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +FIQHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r7 ; Save the workspace plus the current + ; return address lr_ fiq and spsr_fiq. + ldr r0,=FIQ_Handler + ldr lr,=FIQ_Handler_end + + bx r0 ; Branch to FIQ_Handler. +FIQ_Handler_end: + RestoreContext r0,r7 ; Restore the context and return to the... + ; ...program execution. + + + + LTORG + + END +;******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE**** \ No newline at end of file diff --git a/Demo/ARM7_STR71x_IAR/Library/71x_it.c b/Demo/ARM7_STR71x_IAR/Library/71x_it.c new file mode 100644 index 000000000..cc4b2b50a --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/Library/71x_it.c @@ -0,0 +1,78 @@ +/******************** (C) COPYRIGHT 2003 STMicroelectronics ******************** +* File Name : 71x_it.c +* Author : MCD Application Team +* Date First Issued : 16/05/2003 +* Description : Main Interrupt Service Routines +******************************************************************************* +* History: +* 24/05/05 : V3.0 +* 30/11/04 : V2.0 +* 16/05/03 : Created +******************************************************************************* + THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH + CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT + OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT + OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION + CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +*******************************************************************************/ +#include "71x_it.h" + + + u32 counter=1; +/******************************************************************************* +* Function Name : Undefined_Handler +* Description : This function handles Undefined instruction exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Undefined_Handler(void) +{ + for( ;; ); +} + +/******************************************************************************* +* Function Name : FIQ_Handler +* Description : This function handles FIQ exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void FIQ_Handler(void) +{ + for( ;; ); +} + +/******************************************************************************* +* Function Name : Prefetch_Handler +* Description : This function handles Prefetch Abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Prefetch_Handler(void) +{ + for( ;; ); +} + +/******************************************************************************* +* Function Name : Abort_Handler +* Description : This function handles Data Abort exception. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Abort_Handler(void) +{ + for( ;; ); +} + +void Default_Handler( void ); +void Default_Handler( void ) +{ + for( ;; ); +} + + +/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/ diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd index bf7182a47..55ff7b44e 100644 --- a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd +++ b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 12 + 15 1 1 - - - - + @@ -129,13 +117,25 @@ ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -181,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -220,7 +257,7 @@ JLINK_ID 2 - 1 + 9 1 1 + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + @@ -273,7 +401,7 @@ MACRAIGOR_ID 2 - 1 + 2 1 1 + + + @@ -426,23 +566,23 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 @@ -450,9 +590,25 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + @@ -465,7 +621,7 @@ C-SPY 2 - 12 + 15 1 0 - - - - + @@ -582,13 +726,25 @@ ARMSIM_ID 2 - 0 + 1 1 0 + + + @@ -634,6 +790,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + IARROM_ID 2 @@ -673,7 +866,7 @@ JLINK_ID 2 - 1 + 9 1 0 + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 0 + + @@ -726,7 +1010,7 @@ MACRAIGOR_ID 2 - 1 + 2 1 0 + + + @@ -879,23 +1175,23 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 @@ -903,7 +1199,23 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 diff --git a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp index b87cca4f9..4364c7b18 100644 --- a/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp +++ b/Demo/ARM7_STR71x_IAR/RTOSDemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 8 + 14 1 1 - - - - - + + + + ICCARM 2 - 11 + 19 1 1 - - - - - - - - - + + + + + AARM 2 - 5 + 7 1 1 - + + + + OBJCOPY + 0 + + 1 + 1 + 1 + @@ -542,275 +529,234 @@ - XLINK - 2 + ILINK + 0 - 17 + 5 1 1 - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -829,15 +775,11 @@ 0 General - 2 + 3 - 8 + 14 1 0 - - - - - + + + + ICCARM 2 - 11 + 19 1 0 - - - - - - - - - + + + + + AARM 2 - 5 + 7 1 0 - + + + + OBJCOPY + 0 + + 1 + 1 + 0 + @@ -1362,275 +1295,234 @@ - XLINK - 2 + ILINK + 0 - 17 + 5 1 0 - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 0 @@ -1719,13 +1611,13 @@ System Files - $PROJ_DIR$\cstartup.s79 + $PROJ_DIR$\71x_init.s - $PROJ_DIR$\lnkarm.xcl + $PROJ_DIR$\Library\71x_it.c - $PROJ_DIR$\vect.s79 + $PROJ_DIR$\71x_vect.s diff --git a/Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf b/Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf new file mode 100644 index 000000000..82356bda1 --- /dev/null +++ b/Demo/ARM7_STR71x_IAR/STR71x_FLASH.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x40000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x4000062C; +define symbol __ICFEDIT_region_ROM_end__ = 0x4003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x100; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x10; +define symbol __ICFEDIT_size_undstack__ = 0x10; +define symbol __ICFEDIT_size_abtstack__ = 0x10; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt index cd1e2ee2f..7e27d3f4d 100644 --- a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt +++ b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dbgdt @@ -9,7 +9,7 @@ - 129272727 + 273272727 @@ -21,7 +21,7 @@ - 100 + 010 @@ -33,7 +33,7 @@ - + TabID-24393-22702 @@ -45,7 +45,7 @@ - 0 + 0 TabID-13122-22708 @@ -61,20 +61,20 @@ TabID-19116-28152BreakpointsBreakpoints - 0TabID-10243-6871RegisterRegister0001CPSR0 + 0TabID-10802-25870DisassemblyDisassembly0 - 0100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c010449004900TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\Library\71x_it.c0482578257810100000010000001 - iaridepm1debuggergui1-2-2853203-2-212512578125111706128124764075-2-2853447-2-2200200125000178731280625764075-2-22191602-2-21604221100250019749778125111706 + iaridepm.enu1debuggergui.enu1-2-2746347-2-210911077857112016249286761711-2-2746198-2-2200200142857203666142857761711-2-21921402-2-21404194100285719755677857112016 diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni index e6db9e63b..3062e860f 100644 --- a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni +++ b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.dni @@ -4,16 +4,25 @@ State 1=_ 1 [JLinkDriver] WatchVectorCatch=_ 0 WatchCond=_ 0 -Watch0=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0 -Watch1=_ 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 "0x00000000" 0 0 0 0 +Watch0=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 +Watch1=_ 0 "" 0 "" 0 "" 0 "" 0 0 0 0 [Low Level] Pipeline mode=0 Initialized=0 -[Disassemble mode] -mode=0 -[Breakpoints] -Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\portable\IAR\STR71x\port.c}.240.4@1" 1 0 0 0 "" 0 "" -Count=1 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -21,3 +30,10 @@ Category=_ 0 [TermIOLog] LoggingEnabled=_ 0 LogFile=_ "" +[Disassemble mode] +mode=0 +[Breakpoints] +Count=0 +[TraceHelper] +Enabled=0 +ShowSource=1 diff --git a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt index 5acc21f72..f34de69b6 100644 --- a/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt +++ b/Demo/ARM7_STR71x_IAR/settings/RTOSDemo.wsdt @@ -3,7 +3,7 @@ - RTOSDemo/Debug + RTOSDemo/Release @@ -12,7 +12,7 @@ - 227272727 + 189272727 @@ -23,11 +23,11 @@ - + 10 - + TabID-14962-21036 @@ -39,7 +39,7 @@ - 0 + 0 TabID-24623-22493 @@ -55,20 +55,20 @@ TabID-25855-25419BreakpointsBreakpoints - 0 + 0 - TextEditorE:\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c0984693469300100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR71x_IAR\main.c01044900490000100000010000001 - iaridepm1debuggergui1-2-2675301-2-221211312518766189375605004-2-23971602-2-2160439910025003565681312518766 + iaridepm.enu1-2-2590263-2-218181285718330189286602851-2-23481402-2-2140435010028573564151285718330 diff --git a/Demo/ARM7_STR75x_IAR/75x_init.s b/Demo/ARM7_STR75x_IAR/75x_init.s index a4b018b67..850cf11a6 100644 --- a/Demo/ARM7_STR75x_IAR/75x_init.s +++ b/Demo/ARM7_STR75x_IAR/75x_init.s @@ -88,19 +88,19 @@ SIR0_off_addr EQU 0x60 ; Source Interrupt Register 0 ; ?program_start ;--------------------------------------------------------------- MODULE ?program_start - RSEG IRQ_STACK:DATA(2) - RSEG FIQ_STACK:DATA(2) - RSEG UND_STACK:DATA(2) - RSEG ABT_STACK:DATA(2) - RSEG SVC_STACK:DATA(2) - RSEG CSTACK:DATA(2) - RSEG ICODE:CODE(2) - PUBLIC __program_start + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .text:CODE(2) + PUBLIC __iar_program_start EXTERN ?main CODE32 -__program_start: +__iar_program_start: LDR pc, =NextInst NextInst @@ -134,19 +134,19 @@ NextInst MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(FIQ_STACK) & 0xFFFFFFF8 ; End of FIQ_STACK + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(ABT_STACK) & 0xFFFFFFF8 ; End of ABT_STACK + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(UND_STACK) & 0xFFFFFFF8 ; End of UND_STACK + ldr sp,=SFE(UND_STACK) ; End of UND_STACK MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts - ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of SVC_STACK + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK ; ------------------------------------------------------------------------------ ; Description : Enable SMI Bank0: enable GPIOs clock in MRCC_PCLKEN register, diff --git a/Demo/ARM7_STR75x_IAR/75x_vect.s b/Demo/ARM7_STR75x_IAR/75x_vect.s index 991bda794..aceda9657 100644 --- a/Demo/ARM7_STR75x_IAR/75x_vect.s +++ b/Demo/ARM7_STR75x_IAR/75x_vect.s @@ -22,7 +22,7 @@ PROGRAM ?RESET - COMMON INTVEC:CODE(2) + SECTION .intvec:CODE(2) CODE32 EIC_base_addr EQU 0xFFFFF800 ; EIC base address @@ -35,7 +35,7 @@ IPR_off_addr EQU 0x40 ; Interrupt Pending Register ; Import the __program_start address from 75x_init.s ;******************************************************************************* - IMPORT __program_start + IMPORT __iar_program_start @@ -113,7 +113,7 @@ IPR_off_addr EQU 0x40 ; Interrupt Pending Register ; Exception handlers address table ;******************************************************************************* -Reset_Addr DCD __program_start +Reset_Addr DCD __iar_program_start Undefined_Addr DCD UndefinedHandler SWI_Addr DCD vPortYieldProcessor Prefetch_Addr DCD PrefetchAbortHandler diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd index 77da49bb2..431b04239 100644 --- a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd +++ b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -161,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -200,7 +257,7 @@ JLINK_ID 2 - 6 + 9 1 1 - - + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + @@ -479,43 +566,47 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Stack\stack.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 @@ -530,7 +621,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -679,6 +790,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -718,7 +866,7 @@ JLINK_ID 2 - 6 + 9 1 1 - - + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + + + @@ -997,44 +1175,48 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Stack\stack.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 diff --git a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp index c078f2f2f..3ed41e775 100644 --- a/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp +++ b/Demo/ARM7_STR75x_IAR/RTOSDemo.ewp @@ -10,19 +10,15 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + @@ -479,7 +442,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -537,283 +530,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -832,19 +776,15 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + @@ -1337,6 +1244,36 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -1359,283 +1296,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 diff --git a/Demo/ARM7_STR75x_IAR/STR75x_FLASH.icf b/Demo/ARM7_STR75x_IAR/STR75x_FLASH.icf new file mode 100644 index 000000000..d44de43ba --- /dev/null +++ b/Demo/ARM7_STR75x_IAR/STR75x_FLASH.icf @@ -0,0 +1,49 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x20000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x200006F4; +define symbol __ICFEDIT_region_ROM_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x40000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x40003FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x00; +define symbol __ICFEDIT_size_undstack__ = 0x00; +define symbol __ICFEDIT_size_abtstack__ = 0x00; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define symbol __region_USB_PKG_RAM_start__ = 0xFFFFA000; +define symbol __region_USB_PKG_RAM_end__ = 0xFFFFA3FF; +define region USB_PKG_RAM_region = mem:[from __region_USB_PKG_RAM_start__ to __region_USB_PKG_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { section USB_PACKET_MEMORY }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; +place in USB_PKG_RAM_region + { readwrite data section USB_PACKET_MEMORY }; diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt index 1c29a21aa..25da3e89d 100644 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dbgdt @@ -22,7 +22,7 @@ - 100 + 010 20 1004 @@ -34,7 +34,7 @@ - + TabID-22366-21915 @@ -56,7 +56,7 @@ - 0 + 0 TabID-346-21918 @@ -68,20 +68,20 @@ - 0 + 0 - TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c01195333533300100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR75x\portmacro.h03220192019TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR75x\portasm.s7902519701970TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\75x_vect.s02591152811528TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c011123707137071TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR75x\port.c0123565156514TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\STLibrary\src\75x_it.c06539063906TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\75x_init.s021198149814TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c0144551855180100000010000001 - iaridepm1debuggergui1-2-2796232-2-20000167143820988-2-21301402-2-21404132100285713580200 + iaridepm.enu1debuggergui.enu1-2-2807232-2-20000167143823829-2-21311402-2-21404133100285713543800 diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni index 6b1ac8cf7..1dcb6aa9e 100644 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.dni @@ -24,6 +24,10 @@ UseAuto=0 TypeViolation=1 UnspecRange=1 ActionState=1 +[CodeCoverage] +Enabled=_ 0 +[Profiling] +Enabled=0 [Log file] LoggingEnabled=_ 0 LogFile=_ "" diff --git a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt index 9ecfb8432..f669e65af 100644 --- a/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt +++ b/Demo/ARM7_STR75x_IAR/settings/RTOSDemo.wsdt @@ -40,7 +40,7 @@ Workspace - RTOSDemoRTOSDemo/source + RTOSDemoRTOSDemo/sourceRTOSDemo/startup @@ -50,14 +50,14 @@ - TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c011953335333TextEditorC:\E\temp\rc\2\V4.1.2rc1\Demo\ARM7_STR75x_IAR\STLibrary\inc\75x_map.h0013451345TextEditorC:\E\temp\rc\2\V4.1.2rc1\Demo\ARM7_STR75x_IAR\STLibrary\src\75x_it.c02119391939TextEditorC:\E\temp\rc\2\V4.1.2rc1\Demo\ARM7_STR75x_IAR\STLibrary\src\lcd.c0212162211623930100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR75x\portmacro.h03220192019TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR75x\portasm.s7902519701970TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\75x_vect.s02591152811528TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c011123707137071TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\STR75x\port.c0123565156514TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\STLibrary\src\75x_it.c06539063906TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\75x_init.s021198149814TextEditorC:\E\Dev\FreeRTOS\Demo\ARM7_STR75x_IAR\main.c0144551855180100000010000001 - iaridepm1-2-2705298-2-20000214286727366-2-22211402-2-214042231002857229424142857205761 + iaridepm.enu1-2-2715298-2-20000214286730143-2-22231402-2-214042251002857229124142857205703 diff --git a/Demo/ARM9_STR91X_IAR/91x_init.s b/Demo/ARM9_STR91X_IAR/91x_init.s new file mode 100644 index 000000000..6c74e5272 --- /dev/null +++ b/Demo/ARM9_STR91X_IAR/91x_init.s @@ -0,0 +1,242 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 91x_init.s +;* Author : MCD Application Team +;* Date First Issued : 05/18/2006 : Version 1.0 +;* Description : This module performs: +;* - FLASH/RAM initialization, +;* - Stack pointer initialization for each mode , +;* - Branches to ?main in the C library (which eventually +;* calls main()). +;* +;* On reset, the ARM core starts up in Supervisor (SVC) mode, +;* in ARM state,with IRQ and FIQ disabled. +;******************************************************************************* +;* History: +;* 05/22/2007 : Version 1.2 +;* 05/24/2006 : Version 1.1 +;* 05/18/2006 : Version 1.0 +;******************************************************************************* +;* THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +;* CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +;* A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +;* OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +;* OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +;* CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +; At power up, the CPU defaults to run on the oscillator clock, so Depending +; of your Application, Disable or Enable the following Define + + #define PLL_Clock ; Use PLL as the default clock source @ 96 MHz only with + ; Bank 0 @ 0x0 and Bank 1 @ 0x80000 +; #define RTC_Clock ; Use RTC as the default clock source +; #define OSC_Clock ; Use OSC as the default clock source + + +; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs + +Mode_USR EQU 0x10 +Mode_FIQ EQU 0x11 +Mode_IRQ EQU 0x12 +Mode_SVC EQU 0x13 +Mode_ABT EQU 0x17 +Mode_UND EQU 0x1B +Mode_SYS EQU 0x1F ; available on ARM Arch 4 and later + +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + +; --- STR9X SCU specific definitions + +SCU_BASE_Address EQU 0x5C002000 ; SCU Base Address +SCU_CLKCNTR_OFST EQU 0x00000000 ; Clock Control register Offset +SCU_PLLCONF_OFST EQU 0x00000004 ; PLL Configuration register Offset +SCU_SYSSTATUS_OFST EQU 0x00000008 ; System Status Register Offset +SCU_SCR0_OFST EQU 0x00000034 ; System Configuration Register 0 Offset + +; --- STR9X FMI specific definitions + +FMI_BASE_Address EQU 0x54000000 ; FMI Base Address +FMI_BBSR_OFST EQU 0x00000000 ; Boot Bank Size Register +FMI_NBBSR_OFST EQU 0x00000004 ; Non-boot Bank Size Register +FMI_BBADR_OFST EQU 0x0000000C ; Boot Bank Base Address Register +FMI_NBBADR_OFST EQU 0x00000010 ; Non-boot Bank Base Address Register +FMI_CR_OFST EQU 0x00000018 ; Control Register + +;--------------------------------------------------------------- +; ?program_start +;--------------------------------------------------------------- + MODULE ?program_start + + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION .icode:CODE:NOROOT(2) + PUBLIC __iar_program_start + EXTERN ?main + CODE32 + +__iar_program_start: + LDR pc, =NextInst + + +NextInst + + + NOP ; execute some instructions to access CPU registers after wake + NOP ; up from Reset, while waiting for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + +; BUFFERED_Mode +; ------------------------------------------------------------------------------ +; Description : Enable the Buffered mode. +; Just enable the buffered define on the 91x_conf.h +; http://www.arm.com/pdfs/DDI0164A_966E_S.pdf +; ------------------------------------------------------------------------------ + + MRC p15, 0, r0, c1, c0, 0 ; Read CP15 register 1 into r0 + ORR r0, r0, #0x8 ; Enable Write Buffer on AHB + MCR p15, 0, r0, c1, c0, 0 ; Write CP15 register 1 + + + +; --- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, +; when the bank 0 is the boot bank, then enable the Bank 1. + + LDR R6, =FMI_BASE_Address + + LDR R7, = 0x4 ; BOOT BANK Size = 512KB + STR R7, [R6, #FMI_BBSR_OFST] ; (2^4) * 32 = 512KB + + LDR R7, = 0x2 ; NON BOOT BANK Size = 32KB + STR R7, [R6, #FMI_NBBSR_OFST] ; (2^2) * 8 = 32KB + + LDR R7, = 0x0 ; BOOT BANK Address = 0x0 + STR R7, [R6, #FMI_BBADR_OFST] + + LDR R7, = 0x20000 ; NON BOOT BANK Address = 0x80000 + STR R7, [R6, #FMI_NBBADR_OFST] ; need to put 0x20000 because FMI + ; bus on A[25:2] of CPU bus + + LDR R7, = 0x18 ; Enable CS on both banks + STR R7, [R6, #FMI_CR_OFST] ; LDR R7, = 0x19 ;in RevD + ; to enable 8 words PFQ deepth + +; --- Enable 96K RAM, PFQBC enabled, DTCM & AHB wait-states disabled + LDR R0, = SCU_BASE_Address + LDR R1, = 0x0191 + STR R1, [R0, #SCU_SCR0_OFST] + +; ------------------------------------------------------------------------------ +; --- System clock configuration +; ------------------------------------------------------------------------------ + +#ifdef PLL_Clock ; Use 96 MHZ PLL clock as the default frequency + +; --- wait states Flash confguration + + LDR R6, = 0x00080000 ;Write a Write Flash Configuration + LDR R7, =0x60 ;Register command (60h) to any word + STRH R7, [R6] ;address in Bank 1. + + LDR R6, = 0x00083040 ;Write a Write Flash Configuration + LDR R7, = 0x3 ;Register Confirm command (03h) + STRH R7, [R6] ;2Wstaites in read,PWD,LVD enabled, + ;High BUSCFG. +; --- PLL configuration + LDR R1, = 0x00020002 ;Set OSC as clock source + STR R1, [R0, #SCU_CLKCNTR_OFST ] + + + NOP ; Wait for OSC stabilization + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + NOP + + + + + LDR R1, = 0x000ac019 ;Set PLL ENABLE, to 96Mhz + STR R1, [R0, #SCU_PLLCONF_OFST] + +Wait_Loop + LDR R1,[R0, #SCU_SYSSTATUS_OFST] ;Wait until PLL is Locked + ANDS R1, R1, #0x01 + BEQ Wait_Loop + + LDR R1, = 0x00020080 ;Set PLL as clock source after pll + STR R1, [R0, #SCU_CLKCNTR_OFST ] ;is locked and FMICLK=RCLK, + ;PCLK=RCLK/2 +#endif + +#ifdef RTC_Clock ;Use RTC as the default clock source + LDR R1, = 0x00020001 ;Set RTC as clock source and + STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK +#endif + +#ifdef OSC_Clock ;Use Osc as the default clock source + LDR R1, = 0x00020002 ;Set OSC as clock source and + STR R1, [R0, #SCU_CLKCNTR_OFST ] ;FMICLK=RCLK, PCLK=RCLK +#endif + + +; --- Initialize Stack pointer registers + +; Enter each mode in turn and set up the stack pointer + + MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit ; No interrupts + LDR SP, =SFE(FIQ_STACK) + + MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(IRQ_STACK) + + MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(ABT_STACK) + + MSR CPSR_c, #Mode_UND|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(UND_STACK) + + MSR CPSR_c, #Mode_SYS ; IRQs & FIQs are now enabled + LDR SP, = SFE(CSTACK) + + MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit ; No interrupts + LDR SP, = SFE(SVC_STACK) + +; --- Set bits 17-18(DTCM/ITCM order bits)of the Core Configuration Control +; Register + MOV r0, #0x60000 + MCR p15,0x1,r0,c15,c1,0 + +; --- Now enter the C code + B ?main ; Note : use B not BL, because an application will + ; never return this way + + LTORG + + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE**** + + + + diff --git a/Demo/ARM9_STR91X_IAR/91x_vect.s b/Demo/ARM9_STR91X_IAR/91x_vect.s new file mode 100644 index 000000000..d1a4b0b2b --- /dev/null +++ b/Demo/ARM9_STR91X_IAR/91x_vect.s @@ -0,0 +1,228 @@ +;******************** (C) COPYRIGHT 2006 STMicroelectronics ******************** +;* File Name : 91x_vect.s +;* Author : MCD Application Team +;* Date First Issued : 05/18/2006 : Version 1.0 +;* Description : This File used to initialize the exception and IRQ +;* vectors, and to enter/return to/from exceptions +;* handlers. +;******************************************************************************* +* History: +* 05/22/2007 : Version 1.2 +* 05/24/2006 : Version 1.1 +* 05/18/2006 : Version 1.0 +;******************************************************************************* +; THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH +; CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS +; A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT +; OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT +; OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION +; CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. +;******************************************************************************/ + +#include "FreeRTOSConfig.h" +#include "ISR_Support.h" + + SECTION .intvec:CODE:ROOT(2) + CODE32 + + +VectorAddress EQU 0xFFFFF030 ; VIC Vector address register address. +VectorAddressDaisy EQU 0xFC000030 ; Daisy VIC Vector address register +I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled +F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled + + + + +;******************************************************************************* +; Import the __iar_program_start address from 91x_init.s +;******************************************************************************* + + IMPORT __iar_program_start + +;******************************************************************************* +; Import exception handlers +;******************************************************************************* + + IMPORT Undefined_Handler + IMPORT vPortYieldProcessor ; FreeRTOS SWI handler + IMPORT Prefetch_Handler + IMPORT Abort_Handler + IMPORT FIQ_Handler + + +;******************************************************************************* +; Export Peripherals IRQ handlers table address +;******************************************************************************* + +;******************************************************************************* +; Exception vectors +;******************************************************************************* + + LDR PC, Reset_Addr + LDR PC, Undefined_Addr + LDR PC, SWI_Addr + LDR PC, Prefetch_Addr + LDR PC, Abort_Addr + NOP ; Reserved vector + LDR PC, IRQ_Addr + +;******************************************************************************* +;* Function Name : FIQHandler +;* Description : This function is called when FIQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* +FIQHandler + SUB lr,lr,#4 ; Update the link register. + STMFD sp!,{r0-r7,lr} ; Save The workspace plus the current return + ; address lr_fiq into the FIQ stack. + ldr r0,=FIQ_Handler + ldr lr,=FIQ_Handler_end + bx r0 ;Branch to FIQ_Handler. +FIQ_Handler_end: + + LDMFD sp!,{r0-r7,pc}^; Return to the instruction following... + ; ...the exception interrupt. + + +;******************************************************************************* +; Exception handlers address table +;******************************************************************************* + +Reset_Addr DCD __iar_program_start +Undefined_Addr DCD UndefinedHandler +SWI_Addr DCD vPortYieldProcessor +Prefetch_Addr DCD PrefetchAbortHandler +Abort_Addr DCD DataAbortHandler + DCD 0 ; Reserved vector +IRQ_Addr DCD IRQHandler + + +;******************************************************************************* +; MACRO +;******************************************************************************* +;******************************************************************************* +;* Macro Name : SaveContext +;* Description : This macro is used to save the context before entering +; an exception handler. +;* Input : The range of registers to store. +;* Output : none +;******************************************************************************* + +SaveContext MACRO reg1,reg2 + STMFD sp!,{reg1-reg2,lr} ; Save The workspace plus the current return + ; address lr_ mode into the stack. + MRS r1,spsr ; Save the spsr_mode into r1. + STMFD sp!,{r1} ; Save spsr. + ENDM + +;******************************************************************************* +;* Macro Name : RestoreContext +;* Description : This macro is used to restore the context to return from +; an exception handler and continue the program execution. +;* Input : The range of registers to restore. +;* Output : none +;******************************************************************************* + +RestoreContext MACRO reg1,reg2 + LDMFD sp!,{r1} ; Restore the saved spsr_mode into r1. + MSR spsr_cxsf,r1 ; Restore spsr_mode. + LDMFD sp!,{reg1-reg2,pc}^; Return to the instruction following... + ; ...the exception interrupt. + ENDM + + +;******************************************************************************* +; Exception Handlers +;******************************************************************************* + + +;******************************************************************************* +;* Function Name : UndefinedHandler +;* Description : This function is called when undefined instruction +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +UndefinedHandler + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ und and spsr_und. + + ldr r0,=Undefined_Handler + ldr lr,=Undefined_Handler_end + bx r0 ; Branch to Undefined_Handler. + +Undefined_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following... + ; ...the undefined instruction. + +;******************************************************************************* +;* Function Name : PrefetchAbortHandler +;* Description : This function is called when Prefetch Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +PrefetchAbortHandler + SUB lr,lr,#4 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_abt and spsr_abt. + + ldr r0,=Prefetch_Handler + ldr lr,=Prefetch_Handler_end + bx r0 ; Branch to Prefetch_Handler. + +Prefetch_Handler_end: + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the prefetch abort exception. + +;******************************************************************************* +;* Function Name : DataAbortHandler +;* Description : This function is called when Data Abort +; exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +DataAbortHandler + SUB lr,lr,#8 ; Update the link register. + SaveContext r0,r12 ; Save the workspace plus the current + ; return address lr_ abt and spsr_abt. + ldr r0,=Abort_Handler + ldr lr,=Abort_Handler_end + bx r0 ; Branch to Abort_Handler. + +Abort_Handler_end: + + RestoreContext r0,r12 ; Return to the instruction following that... + ; ...has generated the data abort exception. +;******************************************************************************* +;* Function Name : IRQHandler +;* Description : This function is called when IRQ exception is entered. +;* Input : none +;* Output : none +;******************************************************************************* + +IRQHandler + portSAVE_CONTEXT ; Save the context of the current task. + + LDR r0, = VectorAddress + LDR r0, [r0] ; Read the routine address + LDR r1, = VectorAddressDaisy + LDR r1, [r1] + MOV lr, pc + bx r0 + LDR r0, = VectorAddress ; Write to the VectorAddress to clear the + STR r0, [r0] ; respective interrupt in the internal interrupt + LDR r1, = VectorAddressDaisy ; Write to the VectorAddressDaisy to clear the + STR r1,[r1] ; respective interrupt in the internal interrupt + + portRESTORE_CONTEXT ; Restore the context of the selected task. + + LTORG + + END +;******************* (C) COPYRIGHT 2006 STMicroelectronics *****END OF FILE**** diff --git a/Demo/ARM9_STR91X_IAR/RTOSDemo.dep b/Demo/ARM9_STR91X_IAR/RTOSDemo.dep deleted file mode 100644 index 9e4386916..000000000 --- a/Demo/ARM9_STR91X_IAR/RTOSDemo.dep +++ /dev/null @@ -1,7801 +0,0 @@ - - - - 2 - 2035077562 - - ARM - lwIP - D - - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\snmp.h - $PROJ_DIR$\ARM - lwIP - D\Obj\mem.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\def.h - $PROJ_DIR$\ARM - lwIP - D\Obj\stats.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\tcp.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\QPeek.pbi - $PROJ_DIR$\Library\include\91x_fmi.h - $PROJ_DIR$\ARM - lwIP - D\Obj\ip_frag.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\core\stats.c - $PROJ_DIR$\ARM - lwIP - D\Obj\ip.r79 - $PROJ_DIR$\..\Common\include\comtest2.h - $PROJ_DIR$\ARM - lwIP - D\Obj\udp.r79 - $PROJ_DIR$\..\..\Source\include\portable.h - $PROJ_DIR$\ARM - lwIP - D\Obj\ParTest.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\core\sys.c - $PROJ_DIR$\ARM - lwIP - D\Obj\port.pbi - $PROJ_DIR$\lwip\include\lwip\opt.h - $PROJ_DIR$\ARM - lwIP - D\List\RTOSDemo.html - $PROJ_DIR$\ARM - lwIP - D\Obj\mib2.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\BasicWEB.pbi - $PROJ_DIR$\lwip\include\lwIPWebServer\fs.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_vect_IAR.r79 - $PROJ_DIR$\Library\include\91x_vic.h - $PROJ_DIR$\ARM - lwIP - D\Obj\flash.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\api_msg.h - $PROJ_DIR$\ARM - lwIP - D\Obj\list.r79 - $PROJ_DIR$\Library\source\91x_scu.c - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\netif.h - $PROJ_DIR$\lwip\include\arch\lwip_errno.h - $PROJ_DIR$\Library\source\91x_gpio.c - $PROJ_DIR$\..\..\Source\include\FreeRTOS.h - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\tcpip.h - $TOOLKIT_DIR$\inc\stdio.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_scu.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\QPeek.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\ParTest.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\icmp.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_gpio.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\dynamic.pbi - $TOOLKIT_DIR$\inc\DLib_Threads.h - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\ARM - lwIP - D\Obj\tcpip.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\serial.pbi - $TOOLKIT_DIR$\inc\intrinsic.h - $PROJ_DIR$\ARM - lwIP - D\Obj\GenQTest.r79 - $TOOLKIT_DIR$\inc\stdlib.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_fmi.pbi - $PROJ_DIR$\Library\include\91x_scu.h - $PROJ_DIR$\ARM - lwIP - D\Obj\sys.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\api\api_msg.c - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_uart.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\dhcp.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_tim.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\netif.r79 - $PROJ_DIR$\..\Common\include\partest.h - $PROJ_DIR$\ARM - lwIP - D\Obj\mib_structs.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\msg_out.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_tim.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\msg_in.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_vic.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\tcpip.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_vic.pbi - $PROJ_DIR$\..\..\Source\include\projdefs.h - $PROJ_DIR$\ARM - lwIP - D\Obj\main.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\RTOSDemo.pbd - $PROJ_DIR$\ARM - lwIP - D\Obj\icmp.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_fmi.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\sockets.pbi - $PROJ_DIR$\lwip\lwipWebServer\fs.c - $PROJ_DIR$\ARM - lwIP - D\Obj\netif.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\main.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\api_lib.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\err.r79 - $PROJ_DIR$\Library\source\91x_vic.c - $PROJ_DIR$\Library\source\91x_tim.c - $PROJ_DIR$\ARM - lwIP - D\Obj\ethernetif.r79 - $PROJ_DIR$\Library\include\91x_lib.h - $PROJ_DIR$\ARM - lwIP - D\Obj\msg_out.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\memp.h - $PROJ_DIR$\ARM - lwIP - D\Obj\flop.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\sys_arch.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\lcd.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\asn1_dec.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\dynamic.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\ip_frag.c - $PROJ_DIR$\ARM - lwIP - D\Obj\BlockQ.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\ethernetif.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\debug.h - $PROJ_DIR$\..\Common\include\flop.h - $TOOLKIT_DIR$\inc\DLib_Defaults.h - $PROJ_DIR$\ARM - lwIP - D\Obj\tcp_in.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\mib2.c - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\pbuf.h - $PROJ_DIR$\..\..\Source\include\semphr.h - $PROJ_DIR$\ARM - lwIP - D\Obj\ip.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\comtest.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\PollQ.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\httpd.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\etharp.r79 - $TOOLKIT_DIR$\lib\dl5tpainl8n.h - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\asn1_dec.c - $PROJ_DIR$\ARM - lwIP - D\Obj\inet.pbi - $TOOLKIT_DIR$\inc\DLib_Product.h - $PROJ_DIR$\..\..\Source\include\task.h - $PROJ_DIR$\..\Common\Minimal\dynamic.c - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\err.h - $PROJ_DIR$\..\Common\ethernet\lwIP\include\ipv4\lwip\ip_frag.h - $PROJ_DIR$\lwip\lwipWebServer\BasicWEB.c - $PROJ_DIR$\ARM - lwIP - D\Obj\comtest.r79 - $PROJ_DIR$\..\Common\include\PollQ.h - $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\ISR_Support.h - $PROJ_DIR$\ARM - lwIP - D\Obj\BlockQ.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\arch.h - $PROJ_DIR$\ARM - lwIP - D\Obj\queue.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_it.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\fs.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\lcd.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\etharp.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\include\ipv4\lwip\ip.h - $PROJ_DIR$\ARM - lwIP - D\Obj\msg_in.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\serial.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\BasicWEB.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\tcp_out.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\ip.c - $PROJ_DIR$\ARM - lwIP - D\Obj\asn1_dec.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\raw.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\dhcp.h - $PROJ_DIR$\..\Common\ethernet\lwIP\core\raw.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\mem.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp.c - $PROJ_DIR$\..\..\Source\include\croutine.h - $TOOLKIT_DIR$\inc\stddef.h - $PROJ_DIR$\ARM - lwIP - D\Obj\mib_structs.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\dhcp.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\asn1_enc.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp_in.c - $PROJ_DIR$\..\Common\include\semtest.h - $PROJ_DIR$\ARM - lwIP - D\Obj\heap_2.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\ip_addr.c - $TOOLKIT_DIR$\inc\errno.h - $PROJ_DIR$\ARM - lwIP - D\Obj\api_lib.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\semtest.r79 - $PROJ_DIR$\lwip\include\arch\cc.h - $PROJ_DIR$\ARM - lwIP - D\Obj\asn1_enc.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\include\ipv4\lwip\icmp.h - $PROJ_DIR$\ARM - lwIP - D\Exe\RTOSDemo.d79 - $PROJ_DIR$\Library\source\91x_uart.c - $PROJ_DIR$\Library\source\91x_lib.c - $PROJ_DIR$\ARM - lwIP - D\Obj\tcp.pbi - $PROJ_DIR$\lwip\include\lwIPWebServer\fsdata.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_uart.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_init_IAR.r79 - $PROJ_DIR$\..\Common\Minimal\flash.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp_out.c - $TOOLKIT_DIR$\inc\xencoding_limits.h - $PROJ_DIR$\ARM - lwIP - D\Obj\mib2.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\netif\etharp.h - $TOOLKIT_DIR$\inc\yvals.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_it.r79 - $PROJ_DIR$\STCode\lcd.h - $PROJ_DIR$\ParTest\ParTest.c - $PROJ_DIR$\ARM - lwIP - D\Obj\sys.r79 - $PROJ_DIR$\Library\include\91x_tim.h - $PROJ_DIR$\..\Common\include\flash.h - $PROJ_DIR$\..\Common\ethernet\lwIP\api\tcpip.c - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\api.h - $PROJ_DIR$\ARM - lwIP - D\Obj\ip_addr.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\queue.r79 - $PROJ_DIR$\Library\include\91x_ahbapb.h - $PROJ_DIR$\..\Common\ethernet\lwIP\core\udp.c - $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\portmacro.h - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\mib_structs.c - $PROJ_DIR$\ARM - lwIP - D\Obj\tcp_out.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\GenQTest.pbi - $TOOLKIT_DIR$\inc\ymath.h - $PROJ_DIR$\ARM - lwIP - D\Exe\RTOSDemo.sim - $PROJ_DIR$\ARM - lwIP - D\Obj\list.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\pbuf.r79 - $PROJ_DIR$\main.c - $PROJ_DIR$\Library\include\91x_conf.h - $PROJ_DIR$\webserver\uIP_Task.c - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_gpio.r79 - $PROJ_DIR$\lwip\include\lwIPWebServer\BasicWEB.h - $PROJ_DIR$\ARM - lwIP - D\Obj\mem.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_lib.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\sys_arch.pbi - $TOOLKIT_DIR$\inc\intrinsics.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_wdg.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\sys.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_wdg.r79 - $PROJ_DIR$\..\Common\include\BlockQ.h - $PROJ_DIR$\ARM - lwIP - D\Obj\91x_enet.pbi - $PROJ_DIR$\ARM - lwIP - D\Obj\port.r79 - $PROJ_DIR$\..\..\Source\include\list.h - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\tcp.h - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\mem.h - $PROJ_DIR$\ARM - lwIP - D\Obj\ip_frag.r79 - $PROJ_DIR$\ARM - lwIP - D\Obj\tasks.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\ipv4\lwip\inet.h - $PROJ_DIR$\Library\source\91x_fmi.c - $PROJ_DIR$\ARM - lwIP - D\Obj\udp.pbi - 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$PROJ_DIR$\Library\source\91x_lib.c - $PROJ_DIR$\ARM - lwIP - R\Obj\91x_vic.pbi - $PROJ_DIR$\ARM - lwIP - R\Obj\port.r79 - $PROJ_DIR$\lwip\include\lwIPWebServer\fsdata.h - $PROJ_DIR$\..\Common\Minimal\flash.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\tcp_out.c - $TOOLKIT_DIR$\inc\xencoding_limits.h - $PROJ_DIR$\ARM - lwIP - R\Obj\91x_enet.pbi - $PROJ_DIR$\ARM - lwIP - R\Obj\flash.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\include\netif\etharp.h - $PROJ_DIR$\ARM - lwIP - R\Obj\fs.pbi - $TOOLKIT_DIR$\inc\yvals.h - $PROJ_DIR$\ARM - lwIP - R\Obj\mib2.pbi - $PROJ_DIR$\STCode\lcd.h - $PROJ_DIR$\ParTest\ParTest.c - $PROJ_DIR$\Library\include\91x_tim.h - $PROJ_DIR$\..\Common\include\flash.h - $PROJ_DIR$\ARM - lwIP - R\Obj\91x_wdg.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\api\tcpip.c - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\api.h - $PROJ_DIR$\ARM - lwIP - R\Obj\memp.r79 - $PROJ_DIR$\ARM - lwIP - R\Obj\ip.pbi - $PROJ_DIR$\Library\include\91x_ahbapb.h - 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$PROJ_DIR$\serial\serial.c - $PROJ_DIR$\Library\include\91x_wdg.h - $PROJ_DIR$\ARM - lwIP - R\Obj\integer.pbi - $PROJ_DIR$\lwip\include\lwip\lwipopts.h - $PROJ_DIR$\..\Common\ethernet\lwIP\netif\etharp.c - $TOOLKIT_DIR$\inc\math.h - $PROJ_DIR$\ARM - lwIP - R\Obj\91x_gpio.r79 - $PROJ_DIR$\..\Common\Minimal\comtest.c - $PROJ_DIR$\lwip\api\sys_arch.c - $PROJ_DIR$\..\Common\ethernet\lwIP\api\sockets.c - $PROJ_DIR$\STCode\lcd.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\pbuf.c - $PROJ_DIR$\Library\include\91x_map.h - $PROJ_DIR$\ARM - lwIP - R\Obj\91x_lib.pbi - $PROJ_DIR$\Library\include\91x_type.h - $PROJ_DIR$\lwip\include\arch\perf.h - $PROJ_DIR$\..\Common\Minimal\integer.c - $PROJ_DIR$\..\Common\ethernet\lwIP\api\api_lib.c - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\msg_in.c - $PROJ_DIR$\ARM - lwIP - R\Obj\GenQTest.r79 - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\stats.h - $PROJ_DIR$\..\Common\include\GenQTest.h - $PROJ_DIR$\ARM - lwIP - R\Obj\heap_2.r79 - $PROJ_DIR$\ARM - lwIP - R\Obj\serial.pbi - $PROJ_DIR$\Library\source\91x_enet.c - $PROJ_DIR$\..\Common\Minimal\semtest.c - $PROJ_DIR$\Library\source\91x_it.c - $PROJ_DIR$\ARM - lwIP - R\Obj\msg_out.pbi - $PROJ_DIR$\..\Common\ethernet\lwIP\core\dhcp.c - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\sockets.h - $PROJ_DIR$\ARM - lwIP - R\Obj\lcd.r79 - $PROJ_DIR$\..\Common\include\integer.h - $PROJ_DIR$\..\Common\include\comtest.h - $PROJ_DIR$\..\Common\ethernet\lwIP\include\lwip\raw.h - $PROJ_DIR$\ARM - lwIP - R\Obj\BlockQ.pbi - $PROJ_DIR$\lwip\lwipWebServer\httpd.c - $TOOLKIT_DIR$\inc\assert.h - $PROJ_DIR$\ARM - lwIP - R\Obj\main.pbi - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\ARM - lwIP - R\Obj\serial.r79 - $PROJ_DIR$\lwip\netif\ethernetif.c - $TOOLKIT_DIR$\inc\ysizet.h - $PROJ_DIR$\Library\include\91x_uart.h - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\msg_out.c - $PROJ_DIR$\ARM - lwIP - R\Obj\port.pbi - $PROJ_DIR$\lwip\include\lwIPWebServer\httpd.h - $PROJ_DIR$\lwip\include\arch\sys_arch.h - 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$PROJ_DIR$\Library\source\91x_enet.c - ICCARM - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - ICCARM - - - $PROJ_DIR$\Library\source\91x_it.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\core\dhcp.c - ICCARM - - - $PROJ_DIR$\lwip\lwipWebServer\httpd.c - ICCARM - - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - ICCARM - - - $PROJ_DIR$\lwip\netif\ethernetif.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\core\snmp\msg_out.c - ICCARM - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - ICCARM - - - $PROJ_DIR$\Library\source\91x_wdg.c - ICCARM - - - $PROJ_DIR$\..\Common\Minimal\GenQTest.c - ICCARM - - - $PROJ_DIR$\..\Common\Minimal\flop.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\core\inet.c - ICCARM - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\core\netif.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\core\memp.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\api\err.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\lwIP\core\ipv4\icmp.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c - ICCARM - - - $PROJ_DIR$\webserver\httpd.c - ICCARM - - - $PROJ_DIR$\webserver\httpd-fs.c - ICCARM - - - $PROJ_DIR$\webserver\httpd-cgi.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\apps\webserver\http-strings.c - ICCARM - - - $PROJ_DIR$\..\Common\Minimal\QPeek.c - ICCARM - - - $PROJ_DIR$\..\..\Source\tasks.c - ICCARM - - - $PROJ_DIR$\..\..\Source\queue.c - ICCARM - - - $PROJ_DIR$\..\..\Source\list.c - ICCARM - - - $PROJ_DIR$\..\..\Source\portable\IAR\STR91x\port.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c - ICCARM - - - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c - ICCARM - - - - - diff --git a/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd b/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd index 4fd4b8474..e00a0c08a 100644 --- a/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd +++ b/Demo/ARM9_STR91X_IAR/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + @@ -173,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -212,7 +257,7 @@ JLINK_ID 2 - 7 + 9 1 1 - - + + LMIFTDI_ID 2 - 0 + 1 1 1 - - - - @@ -536,11 +566,11 @@ - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 @@ -591,7 +621,7 @@ C-SPY 2 - 13 + 15 1 1 + + @@ -752,6 +790,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -791,7 +866,7 @@ JLINK_ID 2 - 7 + 9 1 1 - - + + LMIFTDI_ID 2 - 0 + 1 1 1 - - - - @@ -1115,11 +1175,11 @@ - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 @@ -1170,7 +1230,7 @@ C-SPY 2 - 13 + 15 1 1 + + @@ -1331,6 +1399,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -1370,7 +1475,7 @@ JLINK_ID 2 - 7 + 9 1 1 - - + + LMIFTDI_ID 2 - 0 + 1 1 1 - - - - @@ -1694,11 +1784,11 @@ - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 @@ -1740,7 +1830,7 @@ - ARM - lwIP - R + ARM - uIP - R ARM @@ -1749,7 +1839,7 @@ C-SPY 2 - 13 + 15 1 0 + + @@ -1910,6 +2008,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + IARROM_ID 2 @@ -1949,7 +2084,7 @@ JLINK_ID 2 - 7 + 9 1 0 - - - - - - LMIFTDI_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - - MACRAIGOR_ID - 2 - - 2 - 1 - 0 - - - - - - - - - - - - - - - - RDI_ID + LMIFTDI_ID 2 1 1 0 - - - - - - - - - - - - - - - - THIRDPARTY_ID - 2 - - 0 - 1 - 0 - - - - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin - 0 - - - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin - 0 - - - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin - 0 - - - $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin - 1 - - - $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin - 1 - - - - - ARM - uIP - R - - ARM - - 0 - - C-SPY - 2 - - 13 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - ARMSIM_ID - 2 - - 1 - 1 - 0 - - - - - - - - ANGEL_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - - - IARROM_ID - 2 - - 0 - 1 - 0 - - - - - - - - - - JLINK_ID - 2 - - 7 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - LMIFTDI_ID - 2 - - 0 - 1 - 0 - - - - - - - - @@ -2852,11 +2393,11 @@ - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 diff --git a/Demo/ARM9_STR91X_IAR/RTOSDemo.ewp b/Demo/ARM9_STR91X_IAR/RTOSDemo.ewp index 194a52cb4..496c3bc13 100644 --- a/Demo/ARM9_STR91X_IAR/RTOSDemo.ewp +++ b/Demo/ARM9_STR91X_IAR/RTOSDemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + @@ -132,7 +128,7 @@ ICCARM 2 - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + @@ -491,7 +449,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -549,283 +537,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -844,15 +783,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + @@ -966,7 +901,7 @@ ICCARM 2 - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + @@ -1326,7 +1223,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -1384,283 +1311,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -1679,15 +1557,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + @@ -1801,7 +1675,7 @@ ICCARM 2 - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + @@ -2164,7 +2000,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -2222,283 +2088,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -2510,51 +2327,39 @@ - ARM - lwIP - R + ARM - uIP - R ARM 0 General - 2 + 3 - 9 + 14 1 0 - - - - + + + @@ -2639,14 +2452,16 @@ ICCARM 2 - 14 + 19 1 0 - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 0 + + + + + + + AARM + 2 + + 7 + 1 + 0 + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + CUSTOM 3 @@ -3058,1117 +2861,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 0 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 0 - - - - BILINK - 0 - - - - - ARM - uIP - R - - ARM - - 0 - - General - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 14 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 7 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CUSTOM - 3 - - - - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - XLINK - 2 - - 18 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - XAR - 2 - - 0 - 1 - 0 - - - @@ -4230,7 +3150,6 @@ $PROJ_DIR$\webserver\uIP_Task.c ARM - lwIP - D - ARM - lwIP - R @@ -4246,248 +3165,13 @@ ICCARM - 14 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ARM - uIP - D - - ICCARM - - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + - ARM - lwIP - D + ARM - uIP - D ICCARM - 14 - 0 + 19 + 1 1 - - - - - - - - - - - - - - + + + + + - ARM - lwIP - R + ARM - lwIP - D ICCARM - 14 - 1 - 0 + 19 + 0 + 1 @@ -5016,36 +3622,15 @@ CCObjPrefix 1 - - - - - - - - - - - - - - + + + + + @@ -5188,7 +3756,7 @@ ICCARM - 14 + 19 1 0 - - - - - - - - - - - - - - + + + + + @@ -5595,23 +4125,16 @@ System Files - $PROJ_DIR$\91x_init_IAR.s - - - $PROJ_DIR$\91x_vect_IAR.s - - - $PROJ_DIR$\lnkarm_flash.xcl + $PROJ_DIR$\91x_init.s - $PROJ_DIR$\lnkarm_ram.xcl + $PROJ_DIR$\91x_vect.s uIP ARM - lwIP - D - ARM - lwIP - R $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\apps\webserver\http-strings.c diff --git a/Demo/ARM9_STR91X_IAR/STR91x_FLASH.icf b/Demo/ARM9_STR91X_IAR/STR91x_FLASH.icf new file mode 100644 index 000000000..cd6278e0d --- /dev/null +++ b/Demo/ARM9_STR91X_IAR/STR91x_FLASH.icf @@ -0,0 +1,42 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x00000178; +define symbol __ICFEDIT_region_ROM_end__ = 0x0007FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x04000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x04017FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x200; +define symbol __ICFEDIT_size_svcstack__ = 0x200; +define symbol __ICFEDIT_size_irqstack__ = 0x200; +define symbol __ICFEDIT_size_fiqstack__ = 0x10; +define symbol __ICFEDIT_size_undstack__ = 0x10; +define symbol __ICFEDIT_size_abtstack__ = 0x10; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { }; +define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { }; +define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { }; +define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { }; +define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { first block ICode{section .icode}, readonly }; +place in RAM_region { readwrite, + block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK, + block UND_STACK, block ABT_STACK, block HEAP }; \ No newline at end of file diff --git a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat index 05be14319..7259709f7 100644 --- a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat +++ b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.cspy.bat @@ -22,11 +22,11 @@ @REM but they are listed at the end of this file for reference. -"C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\bin\armjlink.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\bin\" --backend -B "--endian" "little" "--cpu" "ARM966E-S" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\CONFIG\iostr912.ddf" "--drv_verify_download" "all" "--proc_driver" "jlink" "--jlink_connection" "USB:0" "--jlink_initial_speed" "32" "--jlink_catch_exceptions" "0x000" +"C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armjlink.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\" --backend -B "--endian" "little" "--cpu" "ARM966E-S" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\CONFIG\debugger\ST\iostr912f.ddf" "--drv_verify_download" "all" "--proc_no_semihosting" "--proc_driver" "jlink" "--jlink_connection" "USB:0" "--jlink_initial_speed" "32" "--jlink_catch_exceptions" "0x000" @REM Loaded plugins: @REM armlibsupport.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\CodeCoverage\CodeCoverage.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\Profiling\Profiling.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\stack\stack.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\Profiling\Profiling.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\stack\stack.dll diff --git a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt index cdeee7d6a..985ff1079 100644 --- a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt +++ b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dbgdt @@ -16,7 +16,7 @@ - 252272727 + 268272727 @@ -28,12 +28,12 @@ - 100 + 010 20048268826 - + TabID-874-7293 @@ -49,7 +49,7 @@ TabID-4501-4793Find in FilesFind-in-FilesTabID-19328-10860BreakpointsBreakpoints - 0 + 0 TabID-11622-7296 @@ -57,24 +57,24 @@ Workspace - RTOSDemoRTOSDemo/Demo SourceRTOSDemo/Library SourceRTOSDemo/lwIPRTOSDemo/lwIP/WebServerRTOSDemo/lwIP/netif + RTOSDemo - 0TabID-21421-21055DisassemblyDisassembly0 + 0 - TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\lwip\lwipWebServer\BasicWEB.c010541734173TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\lwip\netif\ethernetif.c03921842184TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\91x_init_IAR.s06635333533TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\main.c0168689368933TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\Common\ethernet\lwIP\netif\etharp.c010343484348TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\Library\source\91x_gpio.c014954955495TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\Common\ethernet\lwIP\core\netif.c07536443644TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Source\portable\IAR\STR91x\port.c03931204912049TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\STCode\lcd.c03322008220082TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\Common\ethernet\lwIP\api\tcpip.c017448504867TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Source\tasks.c05161965219662TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\Library\source\91x_enet.c03971341713417TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\lwip\api\sys_arch.c031695029502TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\FreeRTOSConfig.h04526352635TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\lwip\include\lwip\lwipopts.h01817891789TextEditorC:\Temp\str9_test\FreeRTOS_v4.5.0_STR9_rc1\Demo\ARM9_STR91X_IAR\lwip\include\lwIPWebServer\BasicWEB.h021187818780100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_vect.s04527852785TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_init.s06537043704TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\main.c0170695269522TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\webserver\uIP_Task.c03600TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\lwip\include\lwIPWebServer\BasicWEB.h03420792079TextEditorC:\E\Dev\FreeRTOS\Demo\Common\ethernet\lwIP\core\tcp_in.c028410447104470100000010000001 - iaridepm.enu1debuggergui.enu1-2-2740342-2-2200200142857203666245714755601-2-2740198-2-2200200142857203666142857755601-2-21981402-2-214042001002857203666142857203666 + iaridepm.enu1debuggergui.enu1-2-2740342-2-2200200142857203666245714755601-2-21981402-2-214042001002857203666142857203666 diff --git a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni index 76d294bfd..c18ff2915 100644 --- a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni +++ b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.dni @@ -19,6 +19,8 @@ LimitSize=0 ByteLimit=50 [BreakpointUsageDialog] Placement=_ 144 186 919 647 +[CodeCoverage] +Enabled=_ 0 [Log file] LoggingEnabled=_ 0 LogFile=_ "" diff --git a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt index 17b495ffc..32b6915d1 100644 --- a/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt +++ b/Demo/ARM9_STR91X_IAR/settings/RTOSDemo.wsdt @@ -3,7 +3,7 @@ - RTOSDemo/ARM - lwIP - D + RTOSDemo/ARM - uIP - R @@ -34,7 +34,7 @@ Workspace - RTOSDemo + RTOSDemoRTOSDemo/System Files @@ -54,14 +54,14 @@ - TextEditorC:\Temp\STR9\str9_test\FreeRTOS_v4.5.0_STR9_rc2\Demo\ARM9_STR91X_IAR\main.c02010000100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_vect.s04527852785TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\91x_init.s06537043704TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\main.c0170695269522TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\webserver\uIP_Task.c03600TextEditorC:\E\Dev\FreeRTOS\Demo\ARM9_STR91X_IAR\lwip\include\lwIPWebServer\BasicWEB.h03420792079TextEditorC:\E\Dev\FreeRTOS\Demo\Common\ethernet\lwIP\core\tcp_in.c028410447104470100000010000001 - iaridepm.enu1-2-2606402-2-2200200142857203666288571619145-2-23321402-2-214043341002857340122142857203666 + iaridepm.enu1-2-2606402-2-2200200142857203666288571619145-2-23321402-2-214043341002857340122142857203666 diff --git a/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.dep b/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.dep deleted file mode 100644 index d63434224..000000000 --- a/Demo/AVR32_UC3/AT32UC3A/IAR/rtosdemo.dep +++ /dev/null @@ -1,1213 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\Debug\Obj\intc.r82 - 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$TOOLKIT_DIR$\inc\clib\sysmac.h - $TOOLKIT_DIR$\inc\clib\stdarg.h - $PROJ_DIR$\Output\Obj\regtest.pbi - $PROJ_DIR$\..\..\Source\include\FreeRTOS.h - $PROJ_DIR$\..\Common\include\PollQ.h - $TOOLKIT_DIR$\inc\clib\stddef.h - $TOOLKIT_DIR$\inc\iomacro.h - $PROJ_DIR$\Output\List\PollQ.lst - $PROJ_DIR$\..\Common\include\partest.h - $PROJ_DIR$\Output\Obj\queue.pbi - $PROJ_DIR$\..\Common\include\flash.h - $TOOLKIT_DIR$\inc\clib\string.h - $TOOLKIT_DIR$\inc\clib\stdlib.h - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\..\..\Source\include\croutine.h - $PROJ_DIR$\..\Common\include\print.h - $PROJ_DIR$\Output\Obj\ParTest.r90 - $PROJ_DIR$\..\Common\include\serial.h - $PROJ_DIR$\Output\Obj\main.r90 - $PROJ_DIR$\Output\Obj\PollQ.r90 - $PROJ_DIR$\FreeRTOSConfig.h - $PROJ_DIR$\Output\Obj\heap_1.r90 - $PROJ_DIR$\Output\Obj\integer.r90 - $TOOLKIT_DIR$\inc\clib\stdio.h - $PROJ_DIR$\Output\List\tasks.s90 - $PROJ_DIR$\Output\List\queue.lst - $PROJ_DIR$\..\Common\include\integer.h - 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$PROJ_DIR$\..\Common\include\comtest.h - $PROJ_DIR$\Output\List\main.s90 - $PROJ_DIR$\Output\List\serial.s90 - $PROJ_DIR$\Output\List\port.s90 - $PROJ_DIR$\Output\List\heap_1.lst - $PROJ_DIR$\Output\Exe\rtosdemo.cof - $PROJ_DIR$\Output\List\queue.s90 - $PROJ_DIR$\Output\List\PollQ.s90 - $PROJ_DIR$\Output\Obj\port.pbi - $PROJ_DIR$\Output\List\ParTest.s90 - $PROJ_DIR$\Output\List\integer.lst - $PROJ_DIR$\Output\Obj\port.r90 - $PROJ_DIR$\Output\Obj\comtest.pbi - $PROJ_DIR$\..\..\Source\include\task.h - $TOOLKIT_DIR$\src\template\cfg3soim.xcl - $PROJ_DIR$\Output\List\comtest.s90 - $PROJ_DIR$\Output\List\main.lst - $PROJ_DIR$\Output\List\flash.lst - $PROJ_DIR$\Output\List\flash.s90 - $PROJ_DIR$\Output\List\port.lst - $PROJ_DIR$\Output\List\heap_1.s90 - $PROJ_DIR$\Output\List\list.lst - $PROJ_DIR$\Output\List\rtosdemo.map - $PROJ_DIR$\Output\Obj\tasks.pbi - $PROJ_DIR$\Output\Obj\serial.pbi - $PROJ_DIR$\Output\List\list.s90 - $PROJ_DIR$\Output\Obj\PollQ.pbi - $PROJ_DIR$\Output\List\regtest.s90 - $PROJ_DIR$\Output\List\crflash.s90 - $PROJ_DIR$\..\..\Source\list.c - $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90 - $PROJ_DIR$\..\Common\Minimal\PollQ.c - $PROJ_DIR$\ParTest\ParTest.c - $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c - $PROJ_DIR$\..\..\Source\queue.c - $PROJ_DIR$\Output\Obj\portmacro.r90 - $PROJ_DIR$\..\..\Source\tasks.c - $PROJ_DIR$\serial\serial.c - $PROJ_DIR$\..\..\Source\include\portable.h - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - $PROJ_DIR$\main.c - $PROJ_DIR$\Output\Exe\rtosdemo.elf - $PROJ_DIR$\..\Common\Minimal\comtest.c - $PROJ_DIR$\Output\Exe\rtosdemo.dbg - $PROJ_DIR$\..\Common\include\crflash.h - $PROJ_DIR$\Output\Obj\queue.r90 - $PROJ_DIR$\Output\List\croutine.lst - $PROJ_DIR$\..\Common\Minimal\integer.c - $PROJ_DIR$\Output\Obj\croutine.r90 - $PROJ_DIR$\Output\List\croutine.s90 - $PROJ_DIR$\regtest.h - $PROJ_DIR$\..\..\Source\croutine.c - $PROJ_DIR$\Output\List\crflash.lst - $PROJ_DIR$\Output\Obj\croutine.pbi - $PROJ_DIR$\..\Common\Minimal\crflash.c - $PROJ_DIR$\Output\Obj\regtest.r90 - $PROJ_DIR$\Output\Obj\crflash.pbi - - - [ROOT_NODE] - - - XLINK - 47 78 - - - - - $PROJ_DIR$\..\Common\Minimal\flash.c - - - ICCAVR - 51 74 73 - - - BICOMP - 1 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 69 53 10 12 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 69 53 10 12 - - - - - $PROJ_DIR$\regtest.c - - - ICCAVR - 111 83 50 - - - BICOMP - 4 - - - - - ICCAVR - 5 7 2 49 22 33 8 94 37 69 53 106 - - - BICOMP - 5 7 2 49 22 33 8 94 37 69 53 106 - - - - - $PROJ_DIR$\Output\Obj\rtosdemo.pbd - - - BILINK - 55 82 68 112 109 41 46 35 48 64 11 4 80 79 - - - - - $PROJ_DIR$\Output\Exe\rtosdemo.d90 - - - XLINK - 29 70 18 21 34 51 23 24 52 20 67 91 101 36 54 43 - - - - - $PROJ_DIR$\Output\Exe\rtosdemo.a90 - - - XLINK - 78 - - - - - XLINK - 29 70 18 21 34 39 104 23 24 52 20 67 91 101 111 36 54 43 - - - - - $PROJ_DIR$\Output\Exe\rtosdemo.cof - - - XLINK - 29 70 18 21 34 51 23 24 52 20 67 91 101 36 54 43 - - - - - $PROJ_DIR$\..\..\Source\list.c - - - ICCAVR - 52 81 77 - - - BICOMP - 35 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 53 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 53 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\portmacro.s90 - - - AAVR - 91 - - - - - AAVR - 33 8 - - - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - ICCAVR - 21 63 9 - - - BICOMP - 82 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 69 53 15 6 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 69 53 15 6 - - - - - $PROJ_DIR$\ParTest\ParTest.c - - - ICCAVR - 18 65 30 - - - BICOMP - 55 - - - - - ICCAVR - 5 7 2 49 22 33 8 94 37 69 53 10 - - - BICOMP - 5 7 2 49 22 33 8 94 37 69 53 10 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\ATMega323\port.c - - - ICCAVR - 67 59 75 - - - BICOMP - 64 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 69 53 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 69 53 - - - - - $PROJ_DIR$\..\..\Source\queue.c - - - ICCAVR - 101 62 27 - - - BICOMP - 11 - - - - - ICCAVR - 14 2 13 5 7 49 22 33 8 94 37 69 53 16 - - - BICOMP - 14 2 13 5 7 49 22 33 8 94 37 69 53 16 - - - - - $PROJ_DIR$\..\..\Source\tasks.c - - - ICCAVR - 54 26 32 - - - BICOMP - 79 - - - - - ICCAVR - 25 3 2 14 13 5 7 49 22 33 8 94 37 69 53 - - - BICOMP - 25 3 2 14 13 5 7 49 22 33 8 94 37 69 53 - - - - - $PROJ_DIR$\serial\serial.c - - - ICCAVR - 36 58 45 - - - BICOMP - 80 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 15 69 53 19 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 15 69 53 19 - - - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - ICCAVR - 23 76 60 - - - BICOMP - 41 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 69 53 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 69 53 - - - - - $PROJ_DIR$\main.c - - - ICCAVR - 20 57 72 - - - BICOMP - 48 - - - - - ICCAVR - 14 2 13 5 7 49 22 33 8 94 37 69 53 16 6 28 19 56 100 17 10 106 - - - BICOMP - 14 2 13 5 7 49 22 33 8 94 37 69 53 16 6 28 19 56 100 17 10 106 - - - - - $PROJ_DIR$\Output\Exe\rtosdemo.elf - - - XLINK - 29 70 18 21 34 51 23 24 52 20 67 91 101 36 54 43 - - - - - $PROJ_DIR$\..\Common\Minimal\comtest.c - - - ICCAVR - 34 71 31 - - - BICOMP - 68 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 69 53 19 56 10 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 69 53 19 56 10 - - - - - $PROJ_DIR$\Output\Exe\rtosdemo.dbg - - - XLINK - 29 70 18 21 34 39 104 23 24 52 20 67 91 101 36 54 43 - - - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - ICCAVR - 24 44 66 - - - BICOMP - 46 - - - - - ICCAVR - 14 2 5 7 49 22 33 8 94 37 69 53 28 - - - BICOMP - 14 2 5 7 49 22 33 8 94 37 69 53 28 - - - - - $PROJ_DIR$\..\..\Source\croutine.c - - - ICCAVR - 104 105 102 - - - BICOMP - 109 - - - - - ICCAVR - 5 7 2 49 22 33 8 94 37 69 53 16 - - - BICOMP - 5 7 2 49 22 33 8 94 37 69 53 16 - - - - - $PROJ_DIR$\..\Common\Minimal\crflash.c - - - ICCAVR - 39 84 108 - - - BICOMP - 112 - - - - - ICCAVR - 5 7 2 49 22 33 8 94 37 16 53 15 10 100 - - - BICOMP - 5 7 2 49 22 33 8 94 37 16 53 15 10 100 - - - - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h index b4cecf7f1..0bd18bb8e 100644 --- a/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h +++ b/Demo/CORTEX_LM3S316_IAR/FreeRTOSConfig.h @@ -19,13 +19,13 @@ A special exception to the GPL can be applied should you wish to distribute a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section + the source code for any proprietary components. See the licensing section of http://www.FreeRTOS.org for full details of how and when the exception can be applied. *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant port sections of the online documentation. Also see http://www.SafeRTOS.com a version that has been certified for use @@ -44,7 +44,7 @@ * application requirements. * * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE - * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. *----------------------------------------------------------*/ #define configUSE_PREEMPTION 1 @@ -52,7 +52,7 @@ #define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 20000000 ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 ) -#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 70 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 ) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 3000 ) ) #define configMAX_TASK_NAME_LEN ( 3 ) #define configUSE_TRACE_FACILITY 0 @@ -74,7 +74,7 @@ to exclude the API function. */ #define INCLUDE_vTaskDelayUntil 0 #define INCLUDE_vTaskDelay 1 - +#define configKERNEL_INTERRUPT_PRIORITY 255 #endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S316_IAR/LM3S316.icf b/Demo/CORTEX_LM3S316_IAR/LM3S316.icf new file mode 100644 index 000000000..2c39cba27 --- /dev/null +++ b/Demo/CORTEX_LM3S316_IAR/LM3S316.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// boot_demo1.icf - Linker configuration file for boot_demo1. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x00003fff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20000fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep deleted file mode 100644 index 0e25ef46c..000000000 --- a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.dep +++ /dev/null @@ -1,535 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\..\..\Source\croutine.c - $PROJ_DIR$\ewarm\Obj\cspy.pbi - $PROJ_DIR$\ewarm\Exe\RTOSDemo.sim - $PROJ_DIR$\ewarm\Obj\commstest.r79 - $PROJ_DIR$\ewarm\Obj\pdc.r79 - $PROJ_DIR$\ewarm\Obj\list.r79 - $PROJ_DIR$\hw_include\hw_ssi.h - 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$PROJ_DIR$\..\..\Source\queue.c - $PROJ_DIR$\..\..\Source\tasks.c - $PROJ_DIR$\hw_include\driverlib.r79 - $PROJ_DIR$\ewarm\Obj\port.pbi - $PROJ_DIR$\hw_include\cspy.c - $PROJ_DIR$\hw_include\pdc.c - $PROJ_DIR$\hw_include\startup.c - - - $PROJ_DIR$\..\..\Source\croutine.c - - - ICCARM - 76 - - - BICOMP - 29 - - - - - ICCARM - 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 61 - - - BICOMP - 18 9 56 74 75 43 68 31 8 48 59 36 27 77 61 - - - - - $PROJ_DIR$\..\Common\Minimal\crflash.c - - - ICCARM - 47 - - - BICOMP - 24 - - - - - ICCARM - 18 9 56 74 86 75 43 68 31 8 48 59 36 61 77 35 49 78 - - - BICOMP - 18 9 56 74 75 43 68 31 8 48 59 36 61 77 35 49 78 - - - - - $PROJ_DIR$\ewarm\Exe\RTOSDemo.d79 - - - XLINK - 7 2 - - - - - XLINK - 11 53 3 47 76 39 70 5 57 4 40 37 41 15 26 38 97 32 - - - - - $PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd - - - BILINK - 21 16 24 29 1 73 60 81 65 98 64 23 22 - - - - - $PROJ_DIR$\qs_dk-lm3s316.c - - - ICCARM - 80 - - - BICOMP - 45 - - - - - $PROJ_DIR$\startup.c - - - ICCARM - 26 - - - BICOMP - 23 - - - - - $PROJ_DIR$\..\..\utils\cspy.c - - - ICCARM - 39 - - - BICOMP - 1 - - - - - $PROJ_DIR$\..\Common\Minimal\crhook.c - - - ICCARM - 44 - - - BICOMP - 17 - - - - - ICCARM - 18 9 56 74 86 75 43 68 31 8 48 59 36 61 77 35 20 - - - BICOMP - 18 9 56 74 75 43 68 31 8 48 59 36 61 77 35 20 - - - - - $PROJ_DIR$\..\..\utils\pdc.c - - - ICCARM - 4 - - - BICOMP - 65 - - - - - [ROOT_NODE] - - - XLINK - 46 7 2 - - - - - $PROJ_DIR$\commstest.c - - - ICCARM - 3 - - - BICOMP - 16 - - - - - ICCARM - 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 35 61 49 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34 - - - BICOMP - 18 9 56 74 75 43 68 31 8 48 59 36 27 77 35 61 49 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34 - - - - - $PROJ_DIR$\main.c - - - ICCARM - 57 - - - BICOMP - 81 - - - - - ICCARM - 28 56 74 86 75 43 68 31 18 9 8 48 59 36 27 77 35 61 49 78 72 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34 - - - BICOMP - 28 56 74 75 43 68 31 18 9 8 48 59 36 27 77 35 61 49 78 72 52 42 10 82 58 85 6 14 13 33 19 50 83 62 51 30 34 - - - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - ICCARM - 70 - - - BICOMP - 73 - - - - - ICCARM - 63 56 74 86 75 43 68 31 18 9 8 48 59 36 27 77 - - - BICOMP - 63 56 74 75 43 68 31 18 9 8 48 59 36 27 77 - - - - - $PROJ_DIR$\ParTest\ParTest.c - - - ICCARM - 53 - - - BICOMP - 21 - - - - - ICCARM - 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 49 51 - - - BICOMP - 18 9 56 74 75 43 68 31 8 48 59 36 27 77 49 51 - - - - - $PROJ_DIR$\registertest.s - - - AARM - 15 - - - - - $PROJ_DIR$\..\..\Source\list.c - - - ICCARM - 5 - - - BICOMP - 60 - - - - - ICCARM - 63 56 74 86 75 43 68 31 18 9 8 48 59 36 77 - - - BICOMP - 63 56 74 75 43 68 31 18 9 8 48 59 36 77 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - - - ICCARM - 40 - - - BICOMP - 98 - - - - - ICCARM - 18 9 56 74 86 75 43 68 31 8 48 59 36 27 77 - - - BICOMP - 18 9 56 74 75 43 68 31 8 48 59 36 27 77 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - AARM - 37 - - - - - AARM - 48 - - - - - $PROJ_DIR$\..\..\Source\queue.c - - - ICCARM - 41 - - - BICOMP - 64 - - - - - ICCARM - 63 56 74 86 75 43 68 31 66 18 9 8 48 59 36 27 77 61 - - - BICOMP - 63 56 74 75 43 68 31 66 18 9 8 48 59 36 27 77 61 - - - - - $PROJ_DIR$\..\..\Source\tasks.c - - - ICCARM - 38 - - - BICOMP - 22 - - - - - ICCARM - 28 56 74 86 75 43 68 31 63 66 18 9 8 48 59 36 27 77 - - - BICOMP - 28 56 74 75 43 68 31 63 66 18 9 8 48 59 36 27 77 - - - - - $PROJ_DIR$\hw_include\cspy.c - - - ICCARM - 39 - - - BICOMP - 1 - - - - - ICCARM - 79 - - - BICOMP - 79 - - - - - $PROJ_DIR$\hw_include\pdc.c - - - ICCARM - 4 - - - BICOMP - 65 - - - - - ICCARM - 82 58 12 33 62 50 51 - - - BICOMP - 82 58 12 33 62 50 51 - - - - - $PROJ_DIR$\hw_include\startup.c - - - ICCARM - 26 - - - BICOMP - 23 - - - - - - - diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd index 6ce3c335c..e68a6ffd2 100644 --- a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd +++ b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -161,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -200,7 +257,7 @@ JLINK_ID 2 - 6 + 9 1 1 - - + + + - MACRAIGOR_ID + LMIFTDI_ID 2 1 1 1 + + + + + + + + MACRAIGOR_ID + 2 + + 2 + 1 + 1 + + + @@ -467,39 +566,47 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Stack\stack.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 diff --git a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp index b63c9c75b..1a331cba4 100644 --- a/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp +++ b/Demo/CORTEX_LM3S316_IAR/RTOSDemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + @@ -481,7 +444,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -539,283 +532,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -868,12 +812,6 @@ $PROJ_DIR$\..\..\Source\tasks.c - - Libraries - - $PROJ_DIR$\hw_include\driverlib.r79 - - Luminary Code diff --git a/Demo/CORTEX_LM3S316_IAR/commstest.c b/Demo/CORTEX_LM3S316_IAR/commstest.c index 2fe1534ab..8e91e0cc6 100644 --- a/Demo/CORTEX_LM3S316_IAR/commstest.c +++ b/Demo/CORTEX_LM3S316_IAR/commstest.c @@ -19,13 +19,13 @@ A special exception to the GPL can be applied should you wish to distribute a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section + the source code for any proprietary components. See the licensing section of http://www.FreeRTOS.org for full details of how and when the exception can be applied. *************************************************************************** - See http://www.FreeRTOS.org for documentation, latest information, license - and contact details. Please ensure to read the configuration and relevant + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant port sections of the online documentation. Also see http://www.SafeRTOS.com a version that has been certified for use @@ -67,7 +67,7 @@ task. */ /* FIFO setting for the UART. The FIFO is not used to create a better test. */ #define commsFIFO_SET ( 0x10 ) -/* The string that is transmitted on the UART contains sequentially the +/* The string that is transmitted on the UART contains sequentially the characters from commsFIRST_TX_CHAR to commsLAST_TX_CHAR. */ #define commsFIRST_TX_CHAR '0' #define commsLAST_TX_CHAR 'z' @@ -114,7 +114,7 @@ void vSerialInit( void ) GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), commsBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); /* We dont want to use the fifo. This is for test purposes to generate as many interrupts as possible. */ @@ -122,6 +122,7 @@ void vSerialInit( void ) /* Enable both Rx and Tx interrupts. */ HWREG( UART0_BASE + UART_O_IM ) |= ( UART_INT_TX | UART_INT_RX ); + IntPrioritySet( INT_UART0, configKERNEL_INTERRUPT_PRIORITY ); IntEnable( INT_UART0 ); } /*-----------------------------------------------------------*/ @@ -209,7 +210,7 @@ portBASE_TYPE xTaskWokenByPost = pdFALSE; if( ( HWREG(UART0_BASE + UART_O_FR ) & UART_FR_RXFF ) ) { /* Get the char from the buffer and post it onto the queue of - Rxed chars. Posting the character should wake the task that is + Rxed chars. Posting the character should wake the task that is blocked on the queue waiting for characters. */ cRxedChar = ( portCHAR ) HWREG( UART0_BASE + UART_O_DR ); xTaskWokenByPost = xQueueSendFromISR( xCommsQueue, &cRxedChar, xTaskWokenByPost ); @@ -234,7 +235,7 @@ portBASE_TYPE xTaskWokenByPost = pdFALSE; { /* If a task was woken by the character being received then we force a context switch to occur in case the task is of higher priority than - the currently executing task (i.e. the task that this interrupt + the currently executing task (i.e. the task that this interrupt interrupted.) */ portEND_SWITCHING_ISR( xTaskWokenByPost ); } @@ -274,8 +275,8 @@ static portCHAR cRxedChar, cExpectedChar; { if( cExpectedChar == commsLAST_TX_CHAR ) { - /* We have reached the end of the string - we now expect to - receive the first character in the string again. The LED is + /* We have reached the end of the string - we now expect to + receive the first character in the string again. The LED is toggled to indicate that the entire string was received without error. */ vParTestToggleLED( commsRX_LED ); diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c index 65271d587..dfcf418bc 100644 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c +++ b/Demo/CORTEX_LM3S316_IAR/hw_include/pdc.c @@ -78,7 +78,8 @@ PDCInit(void) // // Configure the SSI port. // - SSIConfig(SSI_BASE, SSI_FRF_MOTO_MODE_0, SSI_MODE_MASTER, 1000000, 8); + SSIConfigSetExpClk(SSI_BASE, SysCtlClockGet(), SSI_FRF_MOTO_MODE_0, + SSI_MODE_MASTER, 1000000, 8); SSIEnable(SSI_BASE); // diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h b/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h index 26094b9e1..eb1374040 100644 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h +++ b/Demo/CORTEX_LM3S316_IAR/hw_include/ssi.h @@ -80,6 +80,10 @@ extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); extern void SSIIntUnregister(unsigned long ulBase); +extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, + unsigned long ulProtocol, unsigned long ulMode, + unsigned long ulBitRate, + unsigned long ulDataWidth); #ifdef __cplusplus } diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c b/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c index b07961b80..1fd39f5bf 100644 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c +++ b/Demo/CORTEX_LM3S316_IAR/hw_include/startup.c @@ -37,7 +37,6 @@ // Forward declaration of the default fault handlers. // //***************************************************************************** -void ResetISR(void); static void NmiSR(void); static void FaultISR(void); static void IntDefaultHandler(void); @@ -56,7 +55,7 @@ extern void vUART_ISR( void ); // The entry point for the application. // //***************************************************************************** -extern void main(void); +extern void __iar_program_start(void); //***************************************************************************** // @@ -66,57 +65,7 @@ extern void main(void); #ifndef STACK_SIZE #define STACK_SIZE 50 #endif -static unsigned long pulStack[STACK_SIZE] = { -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb, -0xbbbbbbbb }; +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; //***************************************************************************** // // A union that describes the entries of the vector table. The union is needed @@ -138,11 +87,11 @@ uVectorEntry; // 0x0000.0000. // //***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = +__root const uVectorEntry __vector_table[] @ ".intvec" = { { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, // The initial stack pointer - ResetISR, // The reset handler + __iar_program_start, // The reset handler NmiSR, // The NMI handler FaultISR, // The hard fault handler IntDefaultHandler, // The MPU fault handler @@ -189,58 +138,6 @@ __root const uVectorEntry g_pfnVectors[] @ "INTVEC" = IntDefaultHandler // FLASH Control }; -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} //***************************************************************************** // diff --git a/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h b/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h index d90fba8ff..6047d3a32 100644 --- a/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h +++ b/Demo/CORTEX_LM3S316_IAR/hw_include/uart.h @@ -94,6 +94,8 @@ extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); #ifdef __cplusplus } diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt index f583dfcf3..408229b41 100644 --- a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt +++ b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dbgdt @@ -22,7 +22,7 @@ - 100 + 010 20 1004 @@ -33,7 +33,7 @@ - + TabID-30594-29847 @@ -41,24 +41,24 @@ Workspace - RTOSDemoRTOSDemo/FreeRTOS SourceRTOSDemo/FreeRTOS Source/croutine.c + RTOSDemoRTOSDemo/Demo Source - 0TabID-30273-20034Debug LogDebug-Log0 + 0TabID-30273-20034Debug LogDebug-Log0 - TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c0182781778170TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h02119911991TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include\startup.c025496449644TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c073326424264240100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c0189797279720TextEditorC:\E\Dev\FreeRTOS\Source\portable\IAR\ARM_CM3\port.c015359365936TextEditorC:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\examples\Luminary\Stellaris\src\adc.c06702379023790TextEditorC:\E\Dev\FreeRTOS\Source\croutine.c02801150911509TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h039239723970100000010000001 - iaridepm1debuggergui1-2-2728348-2-2200200142857205761250000751029-2-21981402-2-214042001002857205761142857205761 + iaridepm.enu1debuggergui.enu1-2-2738348-2-2200202142857205703250000753564-2-22001402-2-214042021002857205703142857205703 diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni index 15689c4d4..8984f2a6b 100644 --- a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni +++ b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.dni @@ -15,6 +15,8 @@ UseTrigger=1 TriggerName=main LimitSize=0 ByteLimit=50 +[CodeCoverage] +Enabled=_ 0 [Log file] LoggingEnabled=_ 0 LogFile=_ "" @@ -25,8 +27,7 @@ LogFile=_ "" [Disassemble mode] mode=1 [Breakpoints] -Bp0=_ "Log" "Memory8:0x20000850" 0 0 0 0 "" 0 "" 0 -Count=1 +Count=0 [TraceHelper] Enabled=0 ShowSource=1 diff --git a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt index 0642cf610..f13f32b5b 100644 --- a/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt +++ b/Demo/CORTEX_LM3S316_IAR/settings/RTOSDemo.wsdt @@ -22,7 +22,7 @@ 30020100426766 - + 48268826 @@ -34,24 +34,24 @@ Workspace - RTOSDemoRTOSDemo/Demo Source + RTOSDemoRTOSDemo/Libraries - 0TabID-24894-24921BuildBuildTabID-10790-31422Debug LogDebug-Log0 + 0TabID-24894-24921BuildBuildTabID-10790-31422Debug LogDebug-LogTabID-27705-5723Find in FilesFind-in-Files0 - TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c0182781778170TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\FreeRTOSConfig.h02119911991TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\hw_include\startup.c025496449644TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c073326424264240100000010000001 + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3S316_IAR\main.c01897972797200100000010000001 - iaridepm1-2-2728260-2-2200200142857205761187143751029-2-21981402-2-214042001002857205761142857205761 + iaridepm.enu1-2-2738260-2-2200202142857205703187143753564-2-22001402-2-214042021002857205703142857205703 diff --git a/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h b/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h index 915e8cfe5..14215dadb 100644 --- a/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h +++ b/Demo/CORTEX_LM3S811_IAR/FreeRTOSConfig.h @@ -75,6 +75,6 @@ to exclude the API function. */ #define INCLUDE_vTaskDelay 1 - +#define configKERNEL_INTERRUPT_PRIORITY 255 #endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/CORTEX_LM3S811_IAR/LM3S811.icf b/Demo/CORTEX_LM3S811_IAR/LM3S811.icf new file mode 100644 index 000000000..5131af05e --- /dev/null +++ b/Demo/CORTEX_LM3S811_IAR/LM3S811.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// boot_demo1.icf - Linker configuration file for boot_demo1. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0000ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x20001fff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h index bfe8c8563..a9b4ad9e9 100644 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h +++ b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/i2c.h @@ -129,6 +129,8 @@ extern void I2CSlaveIntDisable(unsigned long ulBase); extern void I2CSlaveIntEnable(unsigned long ulBase); extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); extern unsigned long I2CSlaveStatus(unsigned long ulBase); +extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, + tBoolean bFast); #ifdef __cplusplus } diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c index 54f260d7a..1af1b6c2f 100644 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c +++ b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/osram96x16.c @@ -282,7 +282,7 @@ static void OSRAMDelay(unsigned long ulCount) { __asm(" subs r0, #1\n" - " bne OSRAMDelay\n" + " bne.n OSRAMDelay\n" " bx lr"); } #endif @@ -810,7 +810,7 @@ OSRAMInit(tBoolean bFast) // // Initialize the I2C master. // - I2CMasterInit(I2C_MASTER_BASE, bFast); + I2CMasterInitExpClk(I2C_MASTER_BASE, SysCtlClockGet(), bFast); // // Compute the inter-byte delay for the SSD0303 controller. This delay is diff --git a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h index b82f2eec5..ee8930861 100644 --- a/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h +++ b/Demo/CORTEX_LM3S811_IAR/LuminaryCode/uart.h @@ -94,6 +94,8 @@ extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); +extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, + unsigned long ulBaud, unsigned long ulConfig); #ifdef __cplusplus } diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep deleted file mode 100644 index 53577a423..000000000 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.dep +++ /dev/null @@ -1,430 +0,0 @@ - - - - 2 - - Debug - - $PROJ_DIR$\ewarm\Exe\RTOSDemo.sim - $PROJ_DIR$\LuminaryCode\osram96x16.h - $PROJ_DIR$\ewarm\Obj\main.pbi - $TOOLKIT_DIR$\lib\dl7mptnnl8f.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portmacro.h - $PROJ_DIR$\LuminaryCode\pwm.h - $PROJ_DIR$\ewarm\Obj\BlockQ.r79 - $PROJ_DIR$\ewarm\Obj\heap_1.pbi - $PROJ_DIR$\LuminaryCode\interrupt.h - $PROJ_DIR$\LuminaryCode\watchdog.h - $TOOLKIT_DIR$\inc\DLib_Threads.h - $PROJ_DIR$\..\..\Source\include\portable.h - $PROJ_DIR$\ewarm\Obj\list.r79 - $PROJ_DIR$\LuminaryCode\driverlib.r79 - $PROJ_DIR$\LuminaryCode\debug.h - $PROJ_DIR$\..\Common\include\semtest.h - $PROJ_DIR$\LuminaryCode\timer.h - $PROJ_DIR$\..\Common\include\PollQ.h - $PROJ_DIR$\ewarm\Obj\tasks.pbi - $PROJ_DIR$\ewarm\Obj\osram96x16.r79 - $PROJ_DIR$\..\..\Source\list.c - $PROJ_DIR$\ewarm\List\RTOSDemo.map - $PROJ_DIR$\LuminaryCode\hw_types.h - $PROJ_DIR$\LuminaryCode\hw_timer.h - $PROJ_DIR$\LuminaryCode\systick.h - $PROJ_DIR$\LuminaryCode\adc.h - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\LuminaryCode\ssi.h - $PROJ_DIR$\ewarm\Exe\RTOSDemo.d79 - $PROJ_DIR$\LuminaryCode\hw_watchdog.h - $PROJ_DIR$\LuminaryCode\hw_gpio.h - $PROJ_DIR$\ewarm\Obj\startup.r79 - $PROJ_DIR$\LuminaryCode\hw_ints.h - $PROJ_DIR$\startup.c - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - $PROJ_DIR$\..\Common\include\integer.h - $PROJ_DIR$\FreeRTOSConfig.h - $PROJ_DIR$\LuminaryCode\flash.h - $PROJ_DIR$\ewarm\Obj\startup.pbi - $PROJ_DIR$\..\..\Source\include\croutine.h - $PROJ_DIR$\ewarm\Obj\heap_1.r79 - $TOOLKIT_DIR$\lib\dl7mptnnl8f.r79 - $PROJ_DIR$\LuminaryCode\qei.h - $PROJ_DIR$\LuminaryCode\DriverLib.h - $PROJ_DIR$\..\..\Source\include\semphr.h - $PROJ_DIR$\LuminaryCode\osram96x16.c - $PROJ_DIR$\ewarm\Obj\PollQ.r79 - $PROJ_DIR$\LuminaryCode\hw_ssi.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - $PROJ_DIR$\ewarm\Obj\main.r79 - $PROJ_DIR$\..\..\Source\queue.c - $TOOLKIT_DIR$\inc\yvals.h - $TOOLKIT_DIR$\inc\stdlib.h - $PROJ_DIR$\LuminaryCode\hw_pwm.h - $PROJ_DIR$\..\..\Source\include\task.h - $PROJ_DIR$\LuminaryCode\hw_uart.h - $PROJ_DIR$\..\Common\Minimal\PollQ.c - $PROJ_DIR$\LuminaryCode\gpio.h - $PROJ_DIR$\LuminaryCode\hw_comp.h - $PROJ_DIR$\ewarm\Obj\port.r79 - $PROJ_DIR$\ewarm\Obj\tasks.r79 - $PROJ_DIR$\LuminaryCode\hw_i2c.h - $PROJ_DIR$\ewarm\Obj\PollQ.pbi - $PROJ_DIR$\ewarm\Obj\queue.pbi - $PROJ_DIR$\ewarm\Obj\integer.pbi - $TOOLKIT_DIR$\inc\string.h - $TOOLKIT_DIR$\inc\stddef.h - $TOOLKIT_DIR$\inc\DLib_Product.h - $PROJ_DIR$\LuminaryCode\cpu.h - $PROJ_DIR$\ewarm\Obj\semtest.pbi - $PROJ_DIR$\LuminaryCode\hw_memmap.h - $PROJ_DIR$\ewarm\Obj\BlockQ.pbi - $PROJ_DIR$\..\Common\Minimal\integer.c - $PROJ_DIR$\LuminaryCode\hw_qei.h - $PROJ_DIR$\LuminaryCode\hw_adc.h - $TOOLKIT_DIR$\inc\ysizet.h - $PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd - $TOOLKIT_DIR$\inc\DLib_Defaults.h - $TOOLKIT_DIR$\inc\xencoding_limits.h - $PROJ_DIR$\standalone.xcl - $PROJ_DIR$\main.c - $PROJ_DIR$\..\Common\Minimal\semtest.c - $PROJ_DIR$\LuminaryCode\comp.h - $PROJ_DIR$\..\..\Source\tasks.c - $PROJ_DIR$\LuminaryCode\hw_flash.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - $PROJ_DIR$\..\..\Source\include\list.h - $PROJ_DIR$\ewarm\Obj\queue.r79 - $PROJ_DIR$\..\..\Source\include\FreeRTOS.h - $PROJ_DIR$\LuminaryCode\hw_nvic.h - $PROJ_DIR$\ewarm\Obj\portasm.r79 - $PROJ_DIR$\ewarm\Obj\semtest.r79 - $TOOLKIT_DIR$\inc\stdio.h - $PROJ_DIR$\..\..\Source\include\projdefs.h - $PROJ_DIR$\LuminaryCode\i2c.h - $PROJ_DIR$\ewarm\Obj\list.pbi - $PROJ_DIR$\ewarm\Obj\osram96x16.pbi - $PROJ_DIR$\ewarm\Obj\integer.r79 - $PROJ_DIR$\LuminaryCode\uart.h - $PROJ_DIR$\ewarm\Obj\port.pbi - $PROJ_DIR$\..\..\Source\include\queue.h - $PROJ_DIR$\LuminaryCode\sysctl.h - $PROJ_DIR$\..\Common\include\BlockQ.h - $PROJ_DIR$\LuminaryCode\hw_sysctl.h - - - $PROJ_DIR$\..\..\Source\list.c - - - ICCARM - 12 - - - BICOMP - 95 - - - - - ICCARM - 52 51 77 3 67 78 10 75 88 66 93 36 11 4 86 - - - BICOMP - 52 51 77 67 78 10 75 88 66 93 36 11 4 86 - - - - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - ICCARM - 6 - - - BICOMP - 71 - - - - - ICCARM - 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 100 102 - - - BICOMP - 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 100 102 - - - - - $PROJ_DIR$\ewarm\Exe\RTOSDemo.d79 - - - XLINK - 21 0 - - - - - XLINK - 79 13 6 46 40 97 12 49 19 59 90 87 91 31 60 41 - - - - - $PROJ_DIR$\startup.c - - - ICCARM - 31 - - - BICOMP - 38 - - - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_1.c - - - ICCARM - 40 - - - BICOMP - 7 - - - - - ICCARM - 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 - - - BICOMP - 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 - - - - - $PROJ_DIR$\LuminaryCode\osram96x16.c - - - ICCARM - 19 - - - BICOMP - 96 - - - - - ICCARM - 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9 - - - BICOMP - 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - AARM - 90 - - - - - AARM - 36 - - - - - $PROJ_DIR$\..\..\Source\queue.c - - - ICCARM - 87 - - - BICOMP - 63 - - - - - ICCARM - 52 51 77 3 67 78 10 75 65 88 66 93 36 11 4 54 86 39 - - - BICOMP - 52 51 77 67 78 10 75 65 88 66 93 36 11 4 54 86 39 - - - - - $PROJ_DIR$\..\Common\Minimal\PollQ.c - - - ICCARM - 46 - - - BICOMP - 62 - - - - - ICCARM - 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 100 17 - - - BICOMP - 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 100 17 - - - - - [ROOT_NODE] - - - XLINK - 28 21 0 - - - - - $PROJ_DIR$\..\Common\Minimal\integer.c - - - ICCARM - 97 - - - BICOMP - 64 - - - - - ICCARM - 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 35 - - - BICOMP - 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 35 - - - - - $PROJ_DIR$\ewarm\Obj\RTOSDemo.pbd - - - BILINK - 71 62 7 64 95 2 96 99 63 69 38 18 - - - - - $PROJ_DIR$\main.c - - - ICCARM - 49 - - - BICOMP - 2 - - - - - ICCARM - 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9 88 66 51 77 3 67 78 10 75 93 36 11 4 54 86 100 44 35 17 15 102 - - - BICOMP - 43 74 58 84 30 61 32 70 89 53 73 47 103 23 22 55 29 1 25 82 68 14 37 57 94 8 5 42 27 101 24 16 98 9 88 66 51 77 67 78 10 75 93 36 11 4 54 86 100 44 35 17 15 102 - - - - - $PROJ_DIR$\..\Common\Minimal\semtest.c - - - ICCARM - 91 - - - BICOMP - 69 - - - - - ICCARM - 52 51 77 3 67 78 10 75 88 66 93 36 11 4 54 86 44 100 15 - - - BICOMP - 52 51 77 67 78 10 75 88 66 93 36 11 4 54 86 44 100 15 - - - - - $PROJ_DIR$\..\..\Source\tasks.c - - - ICCARM - 60 - - - BICOMP - 18 - - - - - ICCARM - 92 51 77 3 67 78 10 75 52 65 88 66 93 36 11 4 54 86 - - - BICOMP - 92 51 77 67 78 10 75 52 65 88 66 93 36 11 4 54 86 - - - - - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - - - ICCARM - 59 - - - BICOMP - 99 - - - - - ICCARM - 88 66 51 77 3 67 78 10 75 93 36 11 4 54 86 - - - BICOMP - 88 66 51 77 67 78 10 75 93 36 11 4 54 86 - - - - - - - diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd index 8e50f7c4c..cfdaf6ecc 100644 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd +++ b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -161,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -200,7 +257,7 @@ JLINK_ID 2 - 6 + 9 1 1 - - + + + LMIFTDI_ID 2 - 0 + 1 1 1 - - - - @@ -520,47 +566,47 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Stack\Stack.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 diff --git a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp index c4f6b76bd..b6d9faa4a 100644 --- a/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp +++ b/Demo/CORTEX_LM3S811_IAR/RTOSDemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + @@ -485,7 +443,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -543,283 +531,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -854,12 +793,6 @@ $PROJ_DIR$\startup.c - - Libraries - - $PROJ_DIR$\LuminaryCode\driverlib.r79 - - Scheduler Source diff --git a/Demo/CORTEX_LM3S811_IAR/main.c b/Demo/CORTEX_LM3S811_IAR/main.c index 4647f801f..7c435e993 100644 --- a/Demo/CORTEX_LM3S811_IAR/main.c +++ b/Demo/CORTEX_LM3S811_IAR/main.c @@ -254,7 +254,7 @@ static void prvSetupHardware( void ) GPIODirModeSet( GPIO_PORTA_BASE, GPIO_PIN_0 | GPIO_PIN_1, GPIO_DIR_MODE_HW ); /* Configure the UART for 8-N-1 operation. */ - UARTConfigSet( UART0_BASE, mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); + UARTConfigSetExpClk( UART0_BASE, SysCtlClockGet(), mainBAUD_RATE, UART_CONFIG_WLEN_8 | UART_CONFIG_PAR_NONE | UART_CONFIG_STOP_ONE ); /* We don't want to use the fifo. This is for test purposes to generate as many interrupts as possible. */ diff --git a/Demo/CORTEX_LM3S811_IAR/startup.c b/Demo/CORTEX_LM3S811_IAR/startup.c index 44bd7701c..d53376fd7 100644 --- a/Demo/CORTEX_LM3S811_IAR/startup.c +++ b/Demo/CORTEX_LM3S811_IAR/startup.c @@ -37,7 +37,6 @@ // Forward declaration of the default fault handlers. // //***************************************************************************** -void ResetISR(void); static void NmiSR(void); static void FaultISR(void); static void IntDefaultHandler(void); @@ -47,7 +46,7 @@ static void IntDefaultHandler(void); // The entry point for the application. // //***************************************************************************** -extern int main(void); +extern void __iar_program_start(void); //***************************************************************************** // @@ -67,7 +66,7 @@ extern void vUART_ISR(void); #ifndef STACK_SIZE #define STACK_SIZE 64 #endif -static unsigned long pulStack[STACK_SIZE]; +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; //***************************************************************************** // @@ -90,11 +89,11 @@ uVectorEntry; // 0x0000.0000. // //***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = +__root const uVectorEntry __vector_table[] @ ".intvec" = { { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, // The initial stack pointer - ResetISR, // The reset handler + __iar_program_start, // The reset handler NmiSR, // The NMI handler FaultISR, // The hard fault handler IntDefaultHandler, // The MPU fault handler @@ -141,58 +140,6 @@ __root const uVectorEntry g_pfnVectors[] @ "INTVEC" = IntDefaultHandler // FLASH Control }; -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} //***************************************************************************** // diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf new file mode 100644 index 000000000..575329d1f --- /dev/null +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/LM3Sxxxx.icf @@ -0,0 +1,58 @@ +//***************************************************************************** +// +// enet_lwip.icf - Linker configuration file for enet_lwip. +// +// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. +// Luminary Micro Confidential - For Use Under NDA Only +// +//***************************************************************************** + +// +// Define a memory region that covers the entire 4 GB addressible space of the +// processor. +// +define memory mem with size = 4G; + +// +// Define a region for the on-chip flash. +// +define region FLASH = mem:[from 0x00000000 to 0x0003ffff]; + +// +// Define a region for the on-chip SRAM. +// +define region SRAM = mem:[from 0x20000000 to 0x2000ffff]; + +// +// Define a block for the heap. The size should be set to something other +// than zero if things in the C library that require the heap are used. +// +define block HEAP with alignment = 8, size = 0x00000000 { }; + +// +// Indicate that the read/write values should be initialized by copying from +// flash. +// +initialize by copy { readwrite }; + +// +// Initicate that the noinit values should be left alone. This includes the +// stack, which if initialized will destroy the return address from the +// initialization code, causing the processor to branch to zero and fault. +// +do not initialize { section .noinit }; + +// +// Place the interrupt vectors at the start of flash. +// +place at start of FLASH { readonly section .intvec }; + +// +// Place the remainder of the read-only items into flash. +// +place in FLASH { readonly }; + +// +// Place all read/write items into SRAM. +// +place in SRAM { readwrite, block HEAP }; diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep index 30f1301f2..014fd12e6 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.dep @@ -2,495 +2,476 @@ 2 - 612718357 + 4157957474 Debug - $PROJ_DIR$\Debug\Obj\uip_arp.pbi + $TOOLKIT_DIR$\inc\DLib_Product.h + $PROJ_DIR$\Debug\Exe\RTOSDemo.out + $PROJ_DIR$\Debug\Obj\startup_ewarm.pbi + $PROJ_DIR$\Debug\Obj\death.pbi + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_ints.h + $PROJ_DIR$\..\..\Source\include\semphr.h + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_ssi.h + $PROJ_DIR$\Debug\Obj\psock.o + $PROJ_DIR$\Debug\Obj\GenQTest.o + $PROJ_DIR$\LuminaryDrivers\hw_ssi.h + $PROJ_DIR$\LuminaryDrivers\pdc.c + $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_ethernet.h + $PROJ_DIR$\..\Common\include\semtest.h + $PROJ_DIR$\webserver\httpd-cgi.h + $PROJ_DIR$\..\..\Source\include\portable.h $PROJ_DIR$\LuminaryDrivers\hw_types.h - $TOOLKIT_DIR$\inc\xencoding_limits.h + $PROJ_DIR$\LM3Sxxxx.icf + $PROJ_DIR$\lcd_message.h + $PROJ_DIR$\Debug\Obj\http-strings.o $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - $PROJ_DIR$\FreeRTOSConfig.h - $PROJ_DIR$\LuminaryDrivers\pdc.h - $PROJ_DIR$\webserver\httpd-fs.h - $PROJ_DIR$\startup_ewarm.c - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - $PROJ_DIR$\..\Common\drivers\LuminaryMicro\hw_sysctl.h - $PROJ_DIR$\Debug\Obj\tasks.pbi - $PROJ_DIR$\Debug\Obj\QPeek.pbi - $PROJ_DIR$\Debug\Obj\psock.pbi - $PROJ_DIR$\Debug\Obj\http-strings.r79 - $PROJ_DIR$\LuminaryDrivers\hw_sysctl.h - $PROJ_DIR$\..\Common\drivers\LuminaryMicro\debug.h - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\clock.h - $PROJ_DIR$\LuminaryDrivers\sysctl.h + $PROJ_DIR$\Debug\Obj\port.pbi + $PROJ_DIR$\LuminaryDrivers\osram128x64x4.c $PROJ_DIR$\webserver\httpd.h - $PROJ_DIR$\Debug\Obj\flash.r79 - $PROJ_DIR$\Debug\Obj\uIP_Task.pbi - $PROJ_DIR$\..\..\Source\list.c - $PROJ_DIR$\LuminaryDrivers\ssi.h - $PROJ_DIR$\webserver\httpd-fs.c - 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$TOOLKIT_DIR$\inc\string.h - $PROJ_DIR$\Debug\Obj\port.r79 - $TOOLKIT_DIR$\inc\stddef.h - $PROJ_DIR$\Debug\Obj\emac.pbi - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - $PROJ_DIR$\Debug\Obj\httpd-fs.pbi - $PROJ_DIR$\Debug\Obj\semtest.r79 + $PROJ_DIR$\..\Common\Minimal\QPeek.c + $PROJ_DIR$\timertest.c + $PROJ_DIR$\..\Common\Minimal\semtest.c + $PROJ_DIR$\webserver\httpd-fs.c $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c - $PROJ_DIR$\Debug\Obj\osram128x64x4.r79 - $PROJ_DIR$\..\Common\include\QPeek.h - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - $PROJ_DIR$\..\Common\Minimal\flash.c - $PROJ_DIR$\Debug\Obj\RTOSDemo.pbd - $PROJ_DIR$\Debug\Obj\rit128x96x4.r79 - $PROJ_DIR$\Debug\Obj\httpd.r79 - $PROJ_DIR$\Debug\Obj\pdc.r79 - $PROJ_DIR$\Debug\Obj\integer.r79 + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c + $PROJ_DIR$\webserver\httpd.c + $PROJ_DIR$\Debug\Obj\httpd-fs.pbi + $PROJ_DIR$\FreeRTOSConfig.h + $PROJ_DIR$\Debug\Obj\pdc.pbi + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\lc.h + $PROJ_DIR$\Debug\Obj\uIP_Task.o + $PROJ_DIR$\Debug\Obj\heap_2.pbi + $PROJ_DIR$\..\..\Source\include\queue.h + $PROJ_DIR$\Debug\Obj\psock.pbi + $PROJ_DIR$\Debug\Obj\tasks.o + $PROJ_DIR$\Debug\Obj\QPeek.pbi + $PROJ_DIR$\Debug\Obj\heap_2.o + $PROJ_DIR$\..\Common\include\GenQTest.h + $PROJ_DIR$\webserver\emac.h - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - - - AARM - 108 - - + $PROJ_DIR$\Debug\Exe\RTOSDemo.out - AARM - 4 + ILINK + 16 95 8 35 38 122 69 121 104 55 183 18 51 81 111 120 71 163 151 41 46 7 127 24 118 61 181 31 136 177 99 44 140 139 42 - $PROJ_DIR$\startup_ewarm.c + $PROJ_DIR$\LuminaryDrivers\pdc.c - - ICCARM - 33 - BICOMP - 101 + 175 - - - - $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - ICCARM - 38 - - - BICOMP - 60 + 114 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 + BICOMP + 39 15 129 34 101 157 106 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 + ICCARM + 39 15 129 34 101 157 106 - $PROJ_DIR$\..\..\Source\list.c + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\portasm.s - ICCARM - 98 - - - BICOMP - 133 + AARM + 46 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 144 - - - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 144 + AARM + 174 - $PROJ_DIR$\webserver\httpd-fs.c + $PROJ_DIR$\LuminaryDrivers\osram128x64x4.c - ICCARM - 135 + BICOMP + 98 - BICOMP - 171 + ICCARM + 63 ICCARM - 18 106 88 30 150 105 80 82 114 2 124 110 68 151 130 6 83 152 25 - - - BICOMP - 18 106 88 30 150 105 80 114 2 124 110 68 151 130 6 83 152 25 + 9 39 146 15 129 34 101 157 109 - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c + $PROJ_DIR$\..\Common\Minimal\integer.c - ICCARM - 96 + BICOMP + 142 - BICOMP - 12 + ICCARM + 120 - ICCARM - 111 105 80 82 114 2 124 132 166 88 30 150 110 18 106 68 151 130 6 152 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 28 - BICOMP - 111 105 80 114 2 124 132 166 88 30 150 110 18 106 68 151 130 6 152 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 28 - $PROJ_DIR$\..\Common\Minimal\semtest.c + $PROJ_DIR$\..\..\Source\portable\MemMang\heap_2.c - ICCARM - 172 + BICOMP + 178 - BICOMP - 52 + ICCARM + 183 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 165 136 39 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 165 136 39 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 - $PROJ_DIR$\webserver\httpd-cgi.c + $PROJ_DIR$\osram128x64x4.c - ICCARM - 40 + BICOMP + 98 - BICOMP - 78 + ICCARM + 151 - ICCARM - 152 88 30 150 105 80 82 114 2 124 110 18 106 68 151 130 6 137 111 132 166 + BICOMP + 6 123 102 90 89 50 143 153 152 - BICOMP - 152 88 30 150 105 80 114 2 124 110 18 106 68 151 130 6 137 111 132 166 + ICCARM + 6 123 102 90 89 50 143 153 152 - $PROJ_DIR$\..\Common\Minimal\GenQTest.c + $PROJ_DIR$\..\Common\Minimal\flash.c - ICCARM - 131 + BICOMP + 77 - BICOMP - 149 + ICCARM + 55 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 136 165 63 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 74 132 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 136 165 63 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 74 132 - $PROJ_DIR$\timertest.c + $PROJ_DIR$\webserver\httpd-cgi.c - ICCARM - 116 + BICOMP + 128 - BICOMP - 129 + ICCARM + 51 - ICCARM - 159 168 105 80 82 114 2 124 132 49 4 81 62 128 42 54 117 51 92 + BICOMP + 115 80 45 33 82 124 27 0 56 107 130 22 59 29 176 119 76 13 135 23 141 137 - BICOMP - 159 168 105 80 114 2 124 132 49 4 81 62 128 42 54 117 51 86 + ICCARM + 115 80 45 33 82 124 27 93 0 56 107 130 22 59 29 176 119 76 13 135 23 141 137 - $PROJ_DIR$\..\Common\Minimal\PollQ.c + $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c - ICCARM - 121 + BICOMP + 20 - BICOMP - 94 + ICCARM + 41 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 136 158 + BICOMP + 26 79 82 124 27 0 56 107 23 58 174 14 32 108 40 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 136 158 + ICCARM + 26 79 82 124 27 93 0 56 107 23 58 174 14 32 108 40 - $PROJ_DIR$\..\Common\Minimal\QPeek.c + $PROJ_DIR$\..\..\Source\queue.c - ICCARM - 44 + BICOMP + 43 - BICOMP - 11 + ICCARM + 127 + + BICOMP + 162 82 124 27 0 56 107 23 141 137 26 79 58 174 14 32 108 40 133 + ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 136 165 175 + 162 82 124 27 93 0 56 107 23 141 137 26 79 58 174 14 32 108 40 133 + + + + $PROJ_DIR$\Debug\Obj\RTOSDemo.pbd + - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 136 165 175 + BILINK + 105 78 85 145 182 117 3 30 77 178 49 128 173 125 142 84 164 98 20 180 43 64 87 2 72 134 73 91 62 110 - $PROJ_DIR$\webserver\uIP_Task.c + $PROJ_DIR$\ParTest\ParTest.c - ICCARM - 97 + BICOMP + 85 - BICOMP - 20 + ICCARM + 35 - ICCARM - 166 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 165 136 54 152 88 30 150 110 18 106 68 151 130 6 67 92 64 154 45 42 72 51 125 57 59 + BICOMP + 26 79 82 124 27 0 56 107 23 58 174 14 32 108 40 74 90 50 123 - BICOMP - 166 105 80 114 2 124 132 159 168 49 4 81 62 35 144 165 136 54 152 88 30 150 110 18 106 68 151 130 6 67 92 64 154 45 51 42 72 125 57 59 + ICCARM + 26 79 82 124 27 93 0 56 107 23 58 174 14 32 108 40 74 90 50 123 - $PROJ_DIR$\webserver\httpd.c + $PROJ_DIR$\main.c - ICCARM - 180 + BICOMP + 164 - BICOMP - 29 + ICCARM + 163 - ICCARM - 152 88 30 150 105 80 82 114 2 124 110 18 106 68 151 130 6 137 34 166 132 + BICOMP + 135 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 179 5 25 112 28 53 132 74 12 57 17 148 184 83 123 90 102 153 50 155 152 - BICOMP - 152 88 30 150 105 80 114 2 124 110 18 106 68 151 130 6 137 34 166 132 + ICCARM + 135 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 179 5 25 112 28 53 132 74 12 57 17 148 184 83 123 90 102 153 50 155 152 @@ -498,457 +479,473 @@ $PROJ_DIR$\rit128x96x4.c - ICCARM - 179 + BICOMP + 64 - BICOMP - 76 + ICCARM + 24 - ICCARM - 73 42 9 54 15 122 162 51 43 + BICOMP + 6 123 102 90 89 50 143 153 155 - BICOMP - 73 42 9 54 15 122 162 51 43 + ICCARM + 6 123 102 90 89 50 143 153 155 - $PROJ_DIR$\LuminaryDrivers\pdc.c + $PROJ_DIR$\webserver\uIP_Task.c - ICCARM - 181 + BICOMP + 91 - BICOMP - 90 + ICCARM + 177 - ICCARM - 66 1 119 71 22 17 5 + BICOMP + 141 82 124 27 0 56 107 23 137 26 79 58 174 14 32 108 40 5 179 90 115 80 45 33 130 22 59 29 176 119 76 70 126 75 11 154 153 123 68 185 74 17 - BICOMP - 66 1 119 71 22 17 5 + ICCARM + 141 82 124 27 93 0 56 107 23 137 26 79 58 174 14 32 108 40 5 179 90 115 80 45 33 130 22 59 29 176 119 76 70 126 75 11 154 153 123 68 185 74 17 - $PROJ_DIR$\main.c + $PROJ_DIR$\..\Common\Minimal\death.c - ICCARM - 84 + BICOMP + 3 - BICOMP - 164 + ICCARM + 121 - ICCARM - 111 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 136 165 160 75 79 85 102 57 39 158 59 70 63 175 42 54 9 51 122 43 157 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 112 - BICOMP - 111 105 80 114 2 124 132 159 168 49 4 81 62 35 144 136 165 160 75 79 85 102 57 39 158 59 70 63 175 42 54 9 51 122 43 157 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 112 - [ROOT_NODE] + $PROJ_DIR$\startup_ewarm.c - XLINK - 155 143 + BICOMP + 2 + + + ICCARM + 61 - $PROJ_DIR$\..\Common\Minimal\integer.c + $PROJ_DIR$\..\..\Source\list.c - ICCARM - 182 + BICOMP + 84 - BICOMP - 41 + ICCARM + 71 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 79 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 40 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 79 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 40 - $PROJ_DIR$\..\..\Source\tasks.c + $PROJ_DIR$\..\Common\Minimal\GenQTest.c - ICCARM - 146 + BICOMP + 78 - BICOMP - 10 + ICCARM + 8 - ICCARM - 111 105 80 82 114 2 124 132 99 166 159 168 49 4 81 62 35 144 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 179 5 184 - BICOMP - 111 105 80 114 2 124 132 99 166 159 168 49 4 81 62 35 144 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 179 5 184 - $PROJ_DIR$\LuminaryDrivers\osram128x64x4.c + $PROJ_DIR$\..\Common\Minimal\blocktim.c - ICCARM - 174 + BICOMP + 117 - BICOMP - 89 + ICCARM + 69 + + BICOMP + 26 79 82 124 27 0 56 107 23 58 174 14 32 108 40 179 53 + ICCARM - 153 66 14 1 119 71 22 17 127 + 26 79 82 124 27 93 0 56 107 23 58 174 14 32 108 40 179 53 - $PROJ_DIR$\ParTest\ParTest.c + $PROJ_DIR$\..\Common\Minimal\PollQ.c - ICCARM - 107 + BICOMP + 145 - BICOMP - 65 + ICCARM + 38 - ICCARM - 159 168 105 80 82 114 2 124 132 49 4 81 62 35 144 57 54 122 42 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 179 57 - BICOMP - 159 168 105 80 114 2 124 132 49 4 81 62 35 144 57 54 122 42 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 179 57 - $PROJ_DIR$\..\Common\Minimal\blocktim.c + $PROJ_DIR$\..\Common\Minimal\BlockQ.c - ICCARM - 120 + BICOMP + 105 - BICOMP - 147 + ICCARM + 95 - ICCARM - 159 168 105 80 82 114 2 124 132 49 4 81 62 35 144 136 85 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 179 25 - BICOMP - 159 168 105 80 114 2 124 132 49 4 81 62 35 144 136 85 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 179 25 - $PROJ_DIR$\osram128x64x4.c + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c - ICCARM - 174 + BICOMP + 110 - BICOMP - 89 + ICCARM + 44 - ICCARM - 73 42 9 54 15 122 162 51 157 + BICOMP + 70 115 80 45 33 82 124 27 0 56 107 130 22 59 29 176 119 76 141 23 137 - BICOMP - 73 42 9 54 15 122 162 51 157 + ICCARM + 70 115 80 45 33 82 124 27 93 0 56 107 130 22 59 29 176 119 76 141 23 137 - $PROJ_DIR$\..\..\Source\queue.c + $PROJ_DIR$\webserver\emac.c - ICCARM - 156 + BICOMP + 30 - BICOMP - 123 + ICCARM + 104 - ICCARM - 99 105 80 82 114 2 124 132 166 159 168 49 4 81 62 35 144 87 + BICOMP + 26 79 82 124 27 0 56 107 23 58 174 14 32 5 179 108 40 185 115 80 45 33 130 22 59 29 176 119 76 90 123 4 11 154 153 88 - BICOMP - 99 105 80 114 2 124 132 166 159 168 49 4 81 62 35 144 87 + ICCARM + 26 79 82 124 27 93 0 56 107 23 58 174 14 32 5 179 108 40 185 115 80 45 33 130 22 59 29 176 119 76 90 123 4 11 154 153 88 - $PROJ_DIR$\..\Common\Minimal\death.c + $PROJ_DIR$\..\..\Source\tasks.c - ICCARM - 37 + BICOMP + 72 - BICOMP - 46 + ICCARM + 181 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 75 + BICOMP + 135 82 124 27 0 56 107 23 162 141 137 26 79 58 174 14 32 108 40 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 75 + ICCARM + 135 82 124 27 93 0 56 107 23 162 141 137 26 79 58 174 14 32 108 40 - $PROJ_DIR$\webserver\emac.c + $PROJ_DIR$\webserver\http-strings.c - - ICCARM - 55 - BICOMP - 169 + 49 - - ICCARM - 159 168 105 80 82 114 2 124 132 49 4 81 62 165 136 35 144 125 152 88 30 150 110 18 106 68 151 130 6 54 42 128 154 45 117 - - - BICOMP - 159 168 105 80 114 2 124 132 49 4 81 62 165 136 35 144 125 152 88 30 150 110 18 106 68 151 130 6 54 42 128 154 45 51 117 + 18 - + - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip_arp.c + $PROJ_DIR$\..\Common\Minimal\QPeek.c - ICCARM - 93 + BICOMP + 182 - BICOMP - 0 + ICCARM + 122 - ICCARM - 67 152 88 30 150 105 80 82 114 2 124 110 18 106 68 151 130 6 166 132 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 179 5 83 - BICOMP - 67 152 88 30 150 105 80 114 2 124 110 18 106 68 151 130 6 166 132 + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 179 5 83 - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c + $PROJ_DIR$\timertest.c - ICCARM - 28 + BICOMP + 73 - BICOMP - 100 + ICCARM + 136 - ICCARM - 16 64 159 168 105 80 82 114 2 124 132 49 4 81 62 145 + BICOMP + 26 79 82 124 27 0 56 107 23 58 174 14 32 4 123 90 88 153 37 - BICOMP - 16 64 159 168 105 80 114 2 124 132 49 4 81 62 145 + ICCARM + 26 79 82 124 27 93 0 56 107 23 58 174 14 32 4 123 90 88 153 37 - $PROJ_DIR$\Debug\Exe\RTOSDemo.d79 + $PROJ_DIR$\..\Common\Minimal\semtest.c - XLINK - 143 + BICOMP + 87 + + + ICCARM + 118 - XLINK - 69 31 131 107 121 44 120 37 55 19 38 13 40 135 180 182 98 84 174 167 108 96 156 179 172 33 146 28 116 97 95 93 112 47 + BICOMP + 162 82 124 27 0 56 107 23 26 79 58 174 14 32 108 40 5 179 12 + + + ICCARM + 162 82 124 27 93 0 56 107 23 26 79 58 174 14 32 108 40 5 179 12 - $PROJ_DIR$\webserver\http-strings.c + $PROJ_DIR$\webserver\httpd-fs.c + + BICOMP + 173 + ICCARM - 13 + 81 + + BICOMP - 134 + 22 59 80 45 33 82 124 27 0 56 107 130 29 176 119 76 138 115 60 - + + ICCARM + 22 59 80 45 33 82 124 27 93 0 56 107 130 29 176 119 76 138 115 60 + + - $PROJ_DIR$\..\..\Source\portable\IAR\ARM_CM3\port.c + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c - ICCARM - 167 + BICOMP + 62 - BICOMP - 58 + ICCARM + 99 - ICCARM - 159 168 105 80 82 114 2 124 132 49 4 81 62 35 144 + BICOMP + 115 80 45 33 82 124 27 0 56 107 130 22 59 29 176 119 76 96 141 23 137 - BICOMP - 159 168 105 80 114 2 124 132 49 4 81 62 35 144 + ICCARM + 115 80 45 33 82 124 27 93 0 56 107 130 22 59 29 176 119 76 96 141 23 137 - $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\uip.c + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\timer.c - ICCARM - 95 + BICOMP + 134 - BICOMP - 104 + ICCARM + 31 - ICCARM - 152 88 30 150 105 80 82 114 2 124 110 18 106 68 151 130 6 141 166 132 + BICOMP + 147 75 26 79 82 124 27 0 56 107 23 58 174 14 32 54 - BICOMP - 152 88 30 150 105 80 114 2 124 110 18 106 68 151 130 6 141 166 132 + ICCARM + 147 75 26 79 82 124 27 93 0 56 107 23 58 174 14 32 54 - $PROJ_DIR$\..\Common\Minimal\BlockQ.c + $PROJ_DIR$\..\Common\ethernet\uIP\uip-1.0\uip\psock.c - ICCARM - 31 + BICOMP + 180 - BICOMP - 32 + ICCARM + 7 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 136 160 + BICOMP + 135 82 124 27 0 56 107 23 141 137 80 45 33 130 22 59 29 176 119 76 115 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 136 160 + ICCARM + 135 82 124 27 93 0 56 107 23 141 137 80 45 33 130 22 59 29 176 119 76 115 - $PROJ_DIR$\..\Common\Minimal\flash.c + $PROJ_DIR$\webserver\httpd.c - ICCARM - 19 + BICOMP + 125 - BICOMP - 161 + ICCARM + 111 - ICCARM - 99 105 80 82 114 2 124 132 159 168 49 4 81 62 35 144 57 102 + BICOMP + 115 80 45 33 82 124 27 0 56 107 130 22 59 29 176 119 76 13 86 141 23 137 - BICOMP - 99 105 80 114 2 124 132 159 168 49 4 81 62 35 144 57 102 + ICCARM + 115 80 45 33 82 124 27 93 0 56 107 130 22 59 29 176 119 76 13 86 141 23 137 - $PROJ_DIR$\Debug\Obj\RTOSDemo.pbd - + [ROOT_NODE] + - BILINK - 32 149 65 94 11 147 46 169 161 60 134 78 171 29 41 133 164 89 58 12 123 76 52 101 10 100 129 20 104 0 + ILINK + 1 - + $PROJ_DIR$\LuminaryDrivers\osram128x64x4.c diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd index 1d3a44298..a1f663560 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + @@ -173,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -212,7 +257,7 @@ JLINK_ID 2 - 7 + 9 1 1 - - + + LMIFTDI_ID 2 - 0 + 1 1 1 - - - - @@ -536,11 +566,11 @@ - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp index a0a8e3800..1f0f615c4 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/RTOSDemo.ewp @@ -10,19 +10,15 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + @@ -486,7 +444,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -544,283 +532,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat index ba9287cf8..ac49556d8 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.cspy.bat @@ -22,11 +22,11 @@ @REM but they are listed at the end of this file for reference. -"C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\bin\armlmiftdi.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\bin\" --backend -B "--endian" "little" "--cpu" "cortex-M3" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 4.0\ARM\CONFIG\iolm3sxxxx.ddf" "--drv_verify_download" "all" "--proc_driver" "lmiftdi" "--lmiftdi_speed" "500" +"C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\bin\cspybat" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armproc.dll" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\armlmiftdi.dll" %1 --plugin "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\bin\" --backend -B "--endian" "little" "--cpu" "Cortex-M3" "--fpu" "None" "--proc_device_desc_file" "C:\Devtools\IAR Systems\Embedded Workbench 5.0\ARM\CONFIG\debugger\Luminary\iolm3sxxxx.ddf" "--drv_verify_download" "all" "--proc_no_semihosting" "--proc_driver" "lmiftdi" "--lmiftdi_speed" "500" @REM Loaded plugins: @REM armlibsupport.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\CodeCoverage\CodeCoverage.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\Profiling\Profiling.dll -@REM C:\Devtools\IAR Systems\Embedded Workbench 4.0\common\plugins\stack\stack.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\CodeCoverage\CodeCoverage.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\Profiling\Profiling.dll +@REM C:\Devtools\IAR Systems\Embedded Workbench 5.0\common\plugins\stack\stack.dll diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt index 33f4649c2..e2af7d9ee 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dbgdt @@ -1,5 +1,80 @@ - + + + + + + 20 + 1006 + 268 + 67 + + + + + + + + 164272727 + + + + 2 + 0 + 0 + + + 1 + 0 + + + + + + + + + TabID-10465-12018 + Debug Log + Debug-Log + + + + TabID-9942-12028 + Build + Build + + + + + 0 + + + TabID-21213-12021 + Workspace + Workspace + + + RTOSDemoRTOSDemo/Demo files + + + + 0 + + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\main.c0161695669560TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\uIP_Task.c03900TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\timertest.c09639933993TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c010913621136211TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\FreeRTOSConfig.h036191519150100000010000001 + + + + + + + iaridepm.enu1debuggergui.enu1-2-2740238-2-2240200142857203666142857755601-2-21981682-2-216842001002381203666142857203666 + + diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni index 61d49c1b0..462defc70 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.dni @@ -1,3 +1,27 @@ +[CodeCoverage] +Enabled=_ 0 +[DisAssemblyWindow] +NumStates=_ 1 +State 1=_ 1 +[Profiling] +Enabled=0 +[StackPlugin] +Enabled=1 +OverflowWarningsEnabled=1 +WarningThreshold=90 +SpWarningsEnabled=1 +WarnHow=0 +UseTrigger=1 +TriggerName=main +LimitSize=0 +ByteLimit=50 +[Log file] +LoggingEnabled=_ 0 +LogFile=_ "" +Category=_ 0 +[TermIOLog] +LoggingEnabled=_ 0 +LogFile=_ "" [Disassemble mode] mode=1 [Breakpoints] diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt index c93053f8a..7913d1b96 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/settings/RTOSDemo.wsdt @@ -2,95 +2,47 @@ - - RTOSDemo/Debug - - + + RTOSDemo/Debug - 124 - 27 - 27 - 27 - + + + + + 304272727 - + 4826882619100726867 - + + TabID-18883-22024 Workspace Workspace - - RTOSDemo - - + + RTOSDemo - 0 - - + + 0TabID-29040-7360Find in FilesFind-in-FilesTabID-19024-10413BuildBuild1 - - 0 - - - 1000000 - 1000000 - - - 1 - + + + + + TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\main.c0161695669560TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\webserver\uIP_Task.c03900TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\timertest.c09639933993TextEditorC:\E\Dev\FreeRTOS\Source\tasks.c010913621136211TextEditorC:\E\Dev\FreeRTOS\Demo\CORTEX_LM3Sxxxx_IAR_Keil\FreeRTOSConfig.h036191519150100000010000001 - - - - - iaridepm.enu1 - - - - - - - - - - -2 - -2 - 938 - 198 - -2 - -2 - 200 - 200 - 142857 - 203666 - 142857 - 957230 - - - - - - - - - - - - - - - - - - - + + + + + + iaridepm.enu1-2-2613378-2-2240200142857203666226190626273-2-23251682-2-216843271002381332994142857203666 diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c index af1c8ac18..3279be441 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/startup_ewarm.c @@ -38,7 +38,6 @@ // Forward declaration of the default fault handlers. // //***************************************************************************** -void ResetISR(void); static void NmiSR(void); static void FaultISR(void); static void IntDefaultHandler(void); @@ -55,7 +54,7 @@ static void IntDefaultHandler(void); // The entry point for the application. // //***************************************************************************** -extern int main(void); +extern void __iar_program_start(void); extern void xPortPendSVHandler(void); extern void xPortSysTickHandler(void); extern void vEMAC_ISR( void ); @@ -69,7 +68,7 @@ extern Timer0IntHandler( void ); #ifndef STACK_SIZE #define STACK_SIZE 64 #endif -static unsigned long pulStack[STACK_SIZE]; +static unsigned long pulStack[STACK_SIZE] @ ".noinit"; //***************************************************************************** // @@ -92,11 +91,11 @@ uVectorEntry; // 0x0000.0000. // //***************************************************************************** -__root const uVectorEntry g_pfnVectors[] @ "INTVEC" = +__root const uVectorEntry __vector_table[] @ ".intvec" = { { .ulPtr = (unsigned long)pulStack + sizeof(pulStack) }, // The initial stack pointer - ResetISR, // The reset handler + __iar_program_start, // The reset handler NmiSR, // The NMI handler FaultISR, // The hard fault handler IntDefaultHandler, // The MPU fault handler @@ -157,58 +156,6 @@ __root const uVectorEntry g_pfnVectors[] @ "INTVEC" = IntDefaultHandler // Power Island }; -//***************************************************************************** -// -// The following are constructs created by the linker, indicating where the -// the "data" and "bss" segments reside in memory. The initializers for the -// for the "data" segment resides immediately following the "text" segment. -// -//***************************************************************************** -#pragma segment="DATA_ID" -#pragma segment="DATA_I" -#pragma segment="DATA_Z" - -//***************************************************************************** -// -// This is the code that gets called when the processor first starts execution -// following a reset event. Only the absolutely necessary set is performed, -// after which the application supplied entry() routine is called. Any fancy -// actions (such as making decisions based on the reset cause register, and -// resetting the bits in that register) are left solely in the hands of the -// application. -// -//***************************************************************************** -void -ResetISR(void) -{ - unsigned long *pulSrc, *pulDest, *pulEnd; - - // - // Copy the data segment initializers from flash to SRAM. - // - pulSrc = __segment_begin("DATA_ID"); - pulDest = __segment_begin("DATA_I"); - pulEnd = __segment_end("DATA_I"); - while(pulDest < pulEnd) - { - *pulDest++ = *pulSrc++; - } - - // - // Zero fill the bss segment. - // - pulDest = __segment_begin("DATA_Z"); - pulEnd = __segment_end("DATA_Z"); - while(pulDest < pulEnd) - { - *pulDest++ = 0; - } - - // - // Call the application's entry point. - // - main(); -} //***************************************************************************** // diff --git a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c index 1a88989d5..6e46bb4b7 100644 --- a/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c +++ b/Demo/CORTEX_LM3Sxxxx_IAR_Keil/timertest.c @@ -68,7 +68,7 @@ zero. */ void Timer0IntHandler( void ); /* Stores the value of the maximum recorded jitter between interrupts. */ -unsigned portLONG ulMaxJitter = 0; +volatile unsigned portLONG ulMaxJitter = 0; /*-----------------------------------------------------------*/ @@ -89,6 +89,9 @@ unsigned long ulFrequency; /* Just used to measure time. */ TimerLoadSet(TIMER1_BASE, TIMER_A, timerMAX_32BIT_VALUE ); + /* Ensure interrupts do not start until the scheduler is running. */ + portDISABLE_INTERRUPTS(); + /* The rate at which the timer will interrupt. */ ulFrequency = configCPU_CLOCK_HZ / timerINTERRUPT_FREQUENCY; TimerLoadSet( TIMER0_BASE, TIMER_A, ulFrequency ); @@ -103,7 +106,8 @@ unsigned long ulFrequency; void Timer0IntHandler( void ) { -unsigned portLONG ulDifference, ulCurrentCount; +unsigned portLONG ulDifference; +volatile unsigned portLONG ulCurrentCount; static portLONG ulMaxDifference = 0, ulLastCount = 0; /* We use the timer 1 counter value to measure the clock cycles between diff --git a/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd b/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd index c05a591f2..5b6128974 100644 --- a/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd +++ b/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 13 + 15 1 1 + + ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -161,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -200,7 +257,7 @@ JLINK_ID 2 - 6 + 9 1 1 - - + + + LMIFTDI_ID 2 - 0 + 1 1 1 - - - - @@ -520,47 +566,47 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Orti\Orti.ewplugin + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Stack\Stack.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 diff --git a/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp b/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp index 84635ff59..d9127ed12 100644 --- a/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp +++ b/Demo/CORTEX_STM32F103_IAR/RTOSDemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 14 + 19 1 1 - - - - - - - - - - - - - - + + + + + @@ -484,7 +442,7 @@ + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -542,283 +530,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 diff --git a/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s b/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s index e2b711955..cb20961e9 100644 --- a/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s +++ b/Demo/CORTEX_STM32F103_IAR/STM32F10xFWLib/src/cortexm3_macro.s @@ -16,7 +16,7 @@ ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. ;******************************************************************************* - RSEG CODE:CODE(2) + SECTION .text:CODE(2) ; Exported functions EXPORT __WFI @@ -28,6 +28,10 @@ EXPORT __SVC EXPORT __MRS_CONTROL EXPORT __MSR_CONTROL + EXPORT __MRS_PSP + EXPORT __MSR_PSP + EXPORT __MRS_MSP + EXPORT __MSR_MSP EXPORT __SETPRIMASK EXPORT __RESETPRIMASK EXPORT __SETFAULTMASK @@ -137,6 +141,50 @@ __MSR_CONTROL ISB BX r14 +;******************************************************************************* +; Function Name : __MRS_PSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Process Stack value. +;******************************************************************************* +__MRS_PSP + + MRS r0, PSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_PSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Process Stack new value. +; Return : None +;******************************************************************************* +__MSR_PSP + + MSR PSP, r0 ; set Process Stack value + BX r14 + +;******************************************************************************* +; Function Name : __MRS_MSP +; Description : Assembler function for the MRS instruction. +; Input : None +; Return : - r0 : Main Stack value. +;******************************************************************************* +__MRS_MSP + + MRS r0, MSP + BX r14 + +;******************************************************************************* +; Function Name : __MSR_MSP +; Description : Assembler function for the MSR instruction. +; Input : - r0 : Main Stack new value. +; Return : None +;******************************************************************************* +__MSR_MSP + + MSR MSP, r0 ; set Main Stack value + BX r14 + ;******************************************************************************* ; Function Name : __SETPRIMASK ; Description : Assembler function to set the PRIMASK. diff --git a/Demo/CORTEX_STM32F103_IAR/STM32F10x_FLASH.icf b/Demo/CORTEX_STM32F103_IAR/STM32F10x_FLASH.icf new file mode 100644 index 000000000..2f38805ab --- /dev/null +++ b/Demo/CORTEX_STM32F103_IAR/STM32F10x_FLASH.icf @@ -0,0 +1,31 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x080000EC; +define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x20004FFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x4; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c b/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c index ddb354eab..a30b73e81 100644 --- a/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c +++ b/Demo/CORTEX_STM32F103_IAR/stm32f10x_vector.c @@ -41,14 +41,14 @@ typedef union { intfunc __fun; void * __ptr; } intvec_elem; #pragma language=extended #pragma segment="CSTACK" -void __program_start( void ); +void __iar_program_start( void ); -#pragma location = "INTVEC" +#pragma location = ".intvec" /* STM32F10x Vector Table entries */ const intvec_elem __vector_table[] = { { .__ptr = __sfe( "CSTACK" ) }, - &__program_start, + &__iar_program_start, NMIException, HardFaultException, MemManageException, diff --git a/Demo/Common/Minimal/dynamic.c b/Demo/Common/Minimal/dynamic.c index f36938d51..43f08cb3e 100644 --- a/Demo/Common/Minimal/dynamic.c +++ b/Demo/Common/Minimal/dynamic.c @@ -351,6 +351,12 @@ portBASE_TYPE xGotValue; } xTaskResumeAll(); + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } while( xGotValue == pdFALSE ); if( ulReceivedValue != ulExpectedValue ) diff --git a/Demo/Common/Minimal/recmutex.c b/Demo/Common/Minimal/recmutex.c new file mode 100644 index 000000000..fea1d32c4 --- /dev/null +++ b/Demo/Common/Minimal/recmutex.c @@ -0,0 +1,335 @@ +/* + FreeRTOS.org V4.7.0 - Copyright (C) 2003-2007 Richard Barry. + + This file is part of the FreeRTOS.org distribution. + + FreeRTOS.org is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + FreeRTOS.org is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with FreeRTOS.org; if not, write to the Free Software + Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + + A special exception to the GPL can be applied should you wish to distribute + a combined work that includes FreeRTOS.org, without being obliged to provide + the source code for any proprietary components. See the licensing section + of http://www.FreeRTOS.org for full details of how and when the exception + can be applied. + + *************************************************************************** + See http://www.FreeRTOS.org for documentation, latest information, license + and contact details. Please ensure to read the configuration and relevant + port sections of the online documentation. + + Also see http://www.SafeRTOS.com a version that has been certified for use + in safety critical systems, plus commercial licensing, development and + support options. + *************************************************************************** +*/ + +/* + The tasks defined on this page demonstrate the use of recursive mutexes. + + All mutexes are created using a call to xSemaphoreCreateMutex(). For + recursive mutex functionality the created mutex should then be manipulated + using the xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() API + functions. Recursive mutexes must NOT be passed as a parameter to the + standard mutex API functions xSemaphoreTake() and xSemaphoreGive(). + + This demo creates three tasks all of which access the same recursive mutex: + + prvRecursiveMutexControllingTask() has the highest priority so executes + first and grabs the mutex. It then performs some recursive accesses - + between each of which it sleeps for a short period to let the lower + priority tasks execute. When it has completed its demo functionality + it gives the mutex back before suspending itself. + + prvRecursiveMutexBlockingTask() attempts to access the mutex by performing + a blocking 'take'. The blocking task has a lower priority than the + controlling task so by the time it executes the mutex has already been + taken by the controlling task, causing the blocking task to block. It + does not unblock until the controlling task has given the mutex back, + and it does not actually run until the controlling task has suspended + itself (due to the relative priorities). When it eventually does obtain + the mutex all it does is give the mutex back prior to also suspending + itself. At this point both the controlling task and the blocking task are + suspended. + + prvRecursiveMutexPollingTask() runs at the idle priority. It spins round + a tight loop attempting to obtain the mutex with a non-blocking call. As + the lowest priority task it will not successfully obtain the mutex until + both the controlling and blocking tasks are suspended. Once it eventually + does obtain the mutex it first unsuspends both the controlling task and + blocking task prior to giving the mutex back - resulting in the polling + task temporarily inheriting the controlling tasks priority. +*/ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Demo app include files. */ +#include "recmutex.h" + +/* Priorities assigned to the three tasks. */ +#define recmuCONTROLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define recmuBLOCKING_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) +#define recmuPOLLING_TASK_PRIORITY ( tskIDLE_PRIORITY + 0 ) + +/* The recursive call depth. */ +#define recmuMAX_COUNT ( 10 ) + +/* Misc. */ +#define recmuSHORT_DELAY ( 5 / portTICK_RATE_MS ) +#define recmuNO_DELAY ( ( portTickType ) 0 ) +#define recmuONE_TICK_DELAY ( ( portTickType ) 1 ) + +/* The three tasks as described at the top of this file. */ +static void prvRecursiveMutexControllingTask( void *pvParameters ); +static void prvRecursiveMutexBlockingTask( void *pvParameters ); +static void prvRecursiveMutexPollingTask( void *pvParameters ); + +/* The mutex used by the demo. */ +static xSemaphoreHandle xMutex; + +/* Variables used to detect and latch errors. */ +static portBASE_TYPE xErrorOccurred = pdFALSE, xControllingIsSuspended = pdFALSE, xBlockingIsSuspended = pdFALSE; +static unsigned portBASE_TYPE uxControllingCycles = 0, uxBlockingCycles, uxPollingCycles = 0; + +/* Handles of the two higher priority tasks, required so they can be resumed +(unsuspended). */ +static xTaskHandle xControllingTaskHandle, xBlockingTaskHandle; + +/*-----------------------------------------------------------*/ + +void vStartRecursiveMutexTasks( void ) +{ + /* Just creates the mutex and the three tasks. */ + + xMutex = xSemaphoreCreateMutex(); + + if( xMutex != NULL ) + { + xTaskCreate( prvRecursiveMutexControllingTask, "Rec1", configMINIMAL_STACK_SIZE, NULL, recmuCONTROLLING_TASK_PRIORITY, &xControllingTaskHandle ); + xTaskCreate( prvRecursiveMutexBlockingTask, "Rec2", configMINIMAL_STACK_SIZE, NULL, recmuBLOCKING_TASK_PRIORITY, &xBlockingTaskHandle ); + xTaskCreate( prvRecursiveMutexPollingTask, "Rec3", configMINIMAL_STACK_SIZE, NULL, recmuPOLLING_TASK_PRIORITY, NULL ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexControllingTask( void *pvParameters ) +{ +unsigned portBASE_TYPE ux; + + for( ;; ) + { + /* Should not be able to 'give' the mutex, as we have not yet 'taken' + it. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* We should now be able to take the mutex as many times as + we like. A one tick delay is used so the polling task will + inherit our priority on all but the first cycle of this task. + If we did not block attempting to receive the mutex then no + priority inheritance would occur. */ + if( xSemaphoreTakeRecursive( xMutex, recmuONE_TICK_DELAY ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Ensure the other task attempting to access the mutex (and the + other demo tasks) are able to execute. */ + vTaskDelay( recmuSHORT_DELAY ); + } + + /* For each time we took the mutex, give it back. */ + for( ux = 0; ux < recmuMAX_COUNT; ux++ ) + { + /* Ensure the other task attempting to access the mutex (and the + other demo tasks) are able to execute. */ + vTaskDelay( recmuSHORT_DELAY ); + + /* We should now be able to give the mutex as many times as we + took it. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + + /* Having given it back the same number of times as it was taken, we + should no longer be the mutex owner, so the next give should fail. */ + if( xSemaphoreGiveRecursive( xMutex ) == pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + /* Keep count of the number of cycles this task has performed so a + stall can be detected. */ + uxControllingCycles++; + + /* Suspend ourselves to the blocking task can execute. */ + xControllingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xControllingIsSuspended = pdFALSE; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexBlockingTask( void *pvParameters ) +{ + for( ;; ) + { + /* Attempt to obtain the mutex. We should block until the + controlling task has given up the mutex, and not actually execute + past this call until the controlling task is suspended. */ + if( xSemaphoreTakeRecursive( xMutex, portMAX_DELAY ) == pdPASS ) + { + if( xControllingIsSuspended != pdTRUE ) + { + /* Did not expect to execute until the controlling task was + suspended. */ + xErrorOccurred = pdTRUE; + } + else + { + /* Give the mutex back before suspending ourselves to allow + the polling task to obtain the mutex. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + + xBlockingIsSuspended = pdTRUE; + vTaskSuspend( NULL ); + xBlockingIsSuspended = pdFALSE; + } + } + else + { + /* We should not leave the xSemaphoreTakeRecursive() function + until the mutex was obtained. */ + xErrorOccurred = pdTRUE; + } + + /* The controlling and blocking tasks should be in lock step. */ + if( uxControllingCycles != ( uxBlockingCycles + 1 ) ) + { + xErrorOccurred = pdTRUE; + } + + /* Keep count of the number of cycles this task has performed so a + stall can be detected. */ + uxBlockingCycles++; + } +} +/*-----------------------------------------------------------*/ + +static void prvRecursiveMutexPollingTask( void *pvParameters ) +{ + for( ;; ) + { + /* Keep attempting to obtain the mutex. We should only obtain it when + the blocking task has suspended itself. */ + if( xSemaphoreTakeRecursive( xMutex, recmuNO_DELAY ) == pdPASS ) + { + /* Is the blocking task suspended? */ + if( xBlockingIsSuspended != pdTRUE ) + { + xErrorOccurred = pdTRUE; + } + else + { + /* Keep count of the number of cycles this task has performed so + a stall can be detected. */ + uxPollingCycles++; + + /* We can resume the other tasks here even though they have a + higher priority than the polling task. When they execute they + will attempt to obtain the mutex but fail because the polling + task is still the mutex holder. The polling task (this task) + will then inherit the higher priority. */ + vTaskResume( xBlockingTaskHandle ); + vTaskResume( xControllingTaskHandle ); + + /* Release the mutex, disinheriting the higher priority again. */ + if( xSemaphoreGiveRecursive( xMutex ) != pdPASS ) + { + xErrorOccurred = pdTRUE; + } + } + } + + #if configUSE_PREEMPTION == 0 + { + taskYIELD(); + } + #endif + } +} +/*-----------------------------------------------------------*/ + +/* This is called to check that all the created tasks are still running. */ +portBASE_TYPE xAreRecursiveMutexTasksStillRunning( void ) +{ +portBASE_TYPE xReturn; +static unsigned portBASE_TYPE uxLastControllingCycles = 0, uxLastBlockingCycles = 0, uxLastPollingCycles = 0; + + /* Is the controlling task still cycling? */ + if( uxLastControllingCycles == uxControllingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastControllingCycles = uxControllingCycles; + } + + /* Is the blocking task still cycling? */ + if( uxLastBlockingCycles == uxBlockingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastBlockingCycles = uxBlockingCycles; + } + + /* Is the polling task still cycling? */ + if( uxLastPollingCycles == uxPollingCycles ) + { + xErrorOccurred = pdTRUE; + } + else + { + uxLastPollingCycles = uxPollingCycles; + } + + if( xErrorOccurred == pdTRUE ) + { + xReturn = pdFAIL; + } + else + { + xReturn = pdTRUE; + } + + return xReturn; +} + + + + diff --git a/Demo/Common/drivers/LuminaryMicro/IAR/driverlib.a b/Demo/Common/drivers/LuminaryMicro/IAR/driverlib.a new file mode 100644 index 000000000..3f0508d57 Binary files /dev/null and b/Demo/Common/drivers/LuminaryMicro/IAR/driverlib.a differ diff --git a/Demo/Common/drivers/LuminaryMicro/Rowley/libdriver.a b/Demo/Common/drivers/LuminaryMicro/Rowley/libdriver.a new file mode 100644 index 000000000..d237b1375 Binary files /dev/null and b/Demo/Common/drivers/LuminaryMicro/Rowley/libdriver.a differ diff --git a/Demo/Common/drivers/LuminaryMicro/arm-stellaris-eabi-gcc/libdriver.a b/Demo/Common/drivers/LuminaryMicro/arm-stellaris-eabi-gcc/libdriver.a new file mode 100644 index 000000000..87d58081b Binary files /dev/null and b/Demo/Common/drivers/LuminaryMicro/arm-stellaris-eabi-gcc/libdriver.a differ diff --git a/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.dep b/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.dep deleted file mode 100644 index dcb8fe4f8..000000000 --- a/Demo/lwIP_AVR32_UC3/AT32UC3A/IAR/lwipdemo.dep +++ /dev/null @@ -1,1165 +0,0 @@ - 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- - - - - - - - - - - - - - + + + + + + + + + + + + + + + @@ -34,22 +34,27 @@ + + + + + - + - + - + - + @@ -57,10 +62,10 @@ + + - - diff --git a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h index 750913249..a059f90e7 100644 --- a/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h +++ b/Demo/uIP_Demo_IAR_ARM7/FreeRTOSConfig.h @@ -37,7 +37,7 @@ #ifndef FREERTOS_CONFIG_H #define FREERTOS_CONFIG_H -#include +#include #include "Board.h" /*----------------------------------------------------------- diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s new file mode 100644 index 000000000..12842e137 --- /dev/null +++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup.s @@ -0,0 +1,302 @@ +;* ---------------------------------------------------------------------------- +;* ATMEL Microcontroller Software Support - ROUSSET - +;* ---------------------------------------------------------------------------- +;* Copyright (c) 2006, Atmel Corporation +; +;* All rights reserved. +;* +;* Redistribution and use in source and binary forms, with or without +;* modification, are permitted provided that the following conditions are met: +;* +;* - Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the disclaimer below. +;* +;* - Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the disclaimer below in the documentation and/or +;* other materials provided with the distribution. +;* +;* Atmel's name may not be used to endorse or promote products derived from +;* this software without specific prior written permission. +;* +;* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +;* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +;* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +;* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +;* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +;* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +;* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +;* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +;* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* ---------------------------------------------------------------------------- + +;------------------------------------------------------------------------------ +; Include your AT91 Library files +;------------------------------------------------------------------------------ +#include "AT91SAM7X256_inc.h" +;------------------------------------------------------------------------------ + +#define TOP_OF_MEMORY (AT91C_ISRAM + AT91C_ISRAM_SIZE) +#define IRQ_STACK_SIZE 200 + ; 3 words to be saved per interrupt priority level + +; Mode, correspords to bits 0-5 in CPSR +MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR +USR_MODE DEFINE 0x10 ; User mode +FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode +IRQ_MODE DEFINE 0x12 ; Interrupt Request mode +SVC_MODE DEFINE 0x13 ; Supervisor mode +ABT_MODE DEFINE 0x17 ; Abort mode +UND_MODE DEFINE 0x1B ; Undefined Instruction mode +SYS_MODE DEFINE 0x1F ; System mode + +I_BIT DEFINE 0x80 +F_BIT DEFINE 0x40 + +;------------------------------------------------------------------------------ +; ?RESET +; Reset Vector. +; Normally, segment INTVEC is linked at address 0. +; For debugging purposes, INTVEC may be placed at other addresses. +; A debugger that honors the entry point will start the +; program in a normal way even if INTVEC is not at address 0. +;------------------------------------------------------------------------------ + SECTION .intvec:CODE:NOROOT(2) + PUBLIC __vector + PUBLIC __iar_program_start + EXTERN vPortYieldProcessor + + ARM +__vector: + ldr pc,[pc,#+24] ;; Reset +__und_handler: + ldr pc,[pc,#+24] ;; Undefined instructions +__swi_handler: + ldr pc,[pc,#+24] ;; Software interrupt (SWI/SVC) +__prefetch_handler: + ldr pc,[pc,#+24] ;; Prefetch abort +__data_handler: + ldr pc,[pc,#+24] ;; Data abort + DC32 0xFFFFFFFF ;; RESERVED +__irq_handler: + LDR PC, [PC, #-0xF20] +__fiq_handler: + ldr pc,[pc,#+24] ;; FIQ + + DC32 __iar_program_start + DC32 __und_handler + DC32 vPortYieldProcessor + DC32 __prefetch_handler + DC32 __data_handler + B . + DC32 IRQ_Handler_Entry + DC32 FIQ_Handler_Entry + +;------------------------------------------------------------------------------ +;- Manage exception: The exception must be ensure in ARM mode +;------------------------------------------------------------------------------ + SECTION text:CODE:NOROOT(2) + ARM +;------------------------------------------------------------------------------ +;- Function : FIQ_Handler_Entry +;- Treatments : FIQ Controller Interrupt Handler. +;- R8 is initialize in Cstartup +;- Called Functions : None only by FIQ +;------------------------------------------------------------------------------ +FIQ_Handler_Entry: + +;- Switch in SVC/User Mode to allow User Stack access for C code +; because the FIQ is not yet acknowledged + +;- Save and r0 in FIQ_Register + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | SVC_MODE +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, lr} + +;- Branch to the routine pointed by the AIC_FVR + mov r14, pc + bx r0 + +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, lr} + +;- Leave Interrupts disabled and switch back in FIQ mode + msr CPSR_c, #I_BIT | F_BIT | FIQ_MODE + +;- Restore the R0 ARM_MODE_SVC register + mov r0,r9 + +;- Restore the Program Counter using the LR_fiq directly in the PC + subs pc,lr,#4 +;------------------------------------------------------------------------------ +;- Function : IRQ_Handler_Entry +;- Treatments : IRQ Controller Interrupt Handler. +;- Called Functions : AIC_IVR[interrupt] +;------------------------------------------------------------------------------ +IRQ_Handler_Entry: +;------------------------- +;- Manage Exception Entry +;------------------------- +;- Adjust and save LR_irq in IRQ stack + sub lr, lr, #4 + stmfd sp!, {lr} + +;- Save r0 and SPSR (need to be saved for nested interrupt) + mrs r14, SPSR + stmfd sp!, {r0,r14} + +;- Write in the IVR to support Protect Mode +;- No effect in Normal Mode +;- De-assert the NIRQ and clear the source in Protect Mode + ldr r14, =AT91C_BASE_AIC + ldr r0 , [r14, #AIC_IVR] + str r14, [r14, #AIC_IVR] + +;- Enable Interrupt and Switch in Supervisor Mode + msr CPSR_c, #SVC_MODE + +;- Save scratch/used registers and LR in User Stack + stmfd sp!, { r1-r3, r12, r14} + +;---------------------------------------------- +;- Branch to the routine pointed by the AIC_IVR +;---------------------------------------------- + mov r14, pc + bx r0 + +;---------------------------------------------- +;- Manage Exception Exit +;---------------------------------------------- +;- Restore scratch/used registers and LR from User Stack + ldmia sp!, { r1-r3, r12, r14} + +;- Disable Interrupt and switch back in IRQ mode + msr CPSR_c, #I_BIT | IRQ_MODE + +;- Mark the End of Interrupt on the AIC + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_EOICR] + +;- Restore SPSR_irq and r0 from IRQ stack + ldmia sp!, {r0,r14} + msr SPSR_cxsf, r14 + +;- Restore adjusted LR_irq from IRQ stack directly in the PC + ldmia sp!, {pc}^ + +;------------------------------------------------------------------------------ +;- Exception Vectors +;------------------------------------------------------------------------------ + PUBLIC AT91F_Default_FIQ_handler + PUBLIC AT91F_Default_IRQ_handler + PUBLIC AT91F_Spurious_handler + + ARM ; Always ARM mode after exeption + +AT91F_Default_FIQ_handler + b AT91F_Default_FIQ_handler + +AT91F_Default_IRQ_handler + b AT91F_Default_IRQ_handler + +AT91F_Spurious_handler + b AT91F_Spurious_handler + + +;------------------------------------------------------------------------------ +; ?INIT +; Program entry. +;------------------------------------------------------------------------------ + + SECTION FIQ_STACK:DATA:NOROOT(3) + SECTION IRQ_STACK:DATA:NOROOT(3) + SECTION SVC_STACK:DATA:NOROOT(3) + SECTION ABT_STACK:DATA:NOROOT(3) + SECTION UND_STACK:DATA:NOROOT(3) + SECTION CSTACK:DATA:NOROOT(3) + SECTION text:CODE:NOROOT(2) + REQUIRE __vector + EXTERN ?main + PUBLIC __iar_program_start + EXTERN AT91F_LowLevelInit + + +__iar_program_start: + +;------------------------------------------------------------------------------ +;- Low level Init is performed in a C function: AT91F_LowLevelInit +;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit +;------------------------------------------------------------------------------ + +;- Retrieve end of RAM address + + ldr r13,=TOP_OF_MEMORY ;- Temporary stack in internal RAM for Low Level Init execution + ldr r0,=AT91F_LowLevelInit + mov lr, pc + bx r0 ;- Branch on C function (with interworking) + +; Initialize the stack pointers. +; The pattern below can be used for any of the exception stacks: +; FIQ, IRQ, SVC, ABT, UND, SYS. +; The USR mode uses the same stack as SYS. +; The stack segments must be defined in the linker command file, +; and be declared above. + + mrs r0,cpsr ; Original PSR value + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SVC_MODE ; Set SVC mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(SVC_STACK) ; End of SVC_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#UND_MODE ; Set UND mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(UND_STACK) ; End of UND_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#ABT_MODE ; Set ABT mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(ABT_STACK) ; End of ABT_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#FIQ_MODE ; Set FIQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(FIQ_STACK) ; End of FIQ_STACK + ;- Init the FIQ register + ldr r8, =AT91C_BASE_AIC + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#IRQ_MODE ; Set IRQ mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(IRQ_STACK) ; End of IRQ_STACK + + bic r0,r0,#MODE_BITS ; Clear the mode bits + orr r0,r0,#SYS_MODE ; Set System mode bits + msr cpsr_c,r0 ; Change the mode + ldr sp,=SFE(CSTACK) ; End of CSTACK + + +#ifdef __ARMVFP__ +; Enable the VFP coprocessor. + mov r0, #0x40000000 ; Set EN bit in VFP + fmxr fpexc, r0 ; FPEXC, clear others. + +; Disable underflow exceptions by setting flush to zero mode. +; For full IEEE 754 underflow compliance this code should be removed +; and the appropriate exception handler installed. + mov r0, #0x01000000 ; Set FZ bit in VFP + fmxr fpscr, r0 ; FPSCR, clear others. +#endif + +; Add more initialization here + msr CPSR_c,#I_BIT | F_BIT | SVC_MODE + + +; Continue to ?main for more IAR specific system startup + + ldr r0,=?main + bx r0 + + END ;- Terminates the assembly of the last module in a file diff --git a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c index a7d50f692..0b48391b3 100644 --- a/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c +++ b/Demo/uIP_Demo_IAR_ARM7/SrcIAR/Cstartup_SAM7.c @@ -1,94 +1,97 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : Cstartup_SAM7.c -//* Object : Low level initializations written in C for IAR -//* tools -//* 1.0 08/Sep/04 JPP : Creation -//* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed -//*---------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// ATMEL Microcontroller Software Support - ROUSSET - +//----------------------------------------------------------------------------- +// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR +// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE +// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, +// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, +// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +//----------------------------------------------------------------------------- +// File Name : Cstartup_SAM7.c +// Object : Low level initialisations written in C for Tools +// For AT91SAM7X256 with 2 flash plane +// Creation : JPP 14-Sep-2006 +//----------------------------------------------------------------------------- -// Include the board file description #include "Board.h" -//#include "init.h" -#include - -// The following functions must be write in ARM mode this function called directly -// by exception vector +// The following functions must be write in ARM mode this function called +// directly by exception vector extern void AT91F_Spurious_handler(void); extern void AT91F_Default_IRQ_handler(void); extern void AT91F_Default_FIQ_handler(void); - //*---------------------------------------------------------------------------- //* \fn AT91F_LowLevelInit //* \brief This function performs very low level HW initialization -//* this function can be use a Stack, depending the compilation +//* this function can use a Stack, depending the compilation //* optimization mode //*---------------------------------------------------------------------------- -void AT91F_LowLevelInit( void); -void AT91F_LowLevelInit( void ) @ "ICODE" +void AT91F_LowLevelInit(void) @ "ICODE" { - int i; - AT91PS_PMC pPMC = AT91C_BASE_PMC; + unsigned char i; + /////////////////////////////////////////////////////////////////////////// + // EFC Init + /////////////////////////////////////////////////////////////////////////// + AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ; - //* Set Flash Waite sate - // Single Cycle Access at Up to 30 MHz, or 40 - // if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN - AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ; + /////////////////////////////////////////////////////////////////////////// + // Init PMC Step 1. Enable Main Oscillator + // Main Oscillator startup time is board specific: + // Main Oscillator Startup Time worst case (3MHz) corresponds to 15ms + // (0x40 for AT91C_CKGR_OSCOUNT field) + /////////////////////////////////////////////////////////////////////////// + AT91C_BASE_PMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x40 <<8) | AT91C_CKGR_MOSCEN )); + // Wait Main Oscillator stabilization + while(!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); - //* Watchdog Disable - AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS; + /////////////////////////////////////////////////////////////////////////// + // Init PMC Step 2. + // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz + // PLL Startup time depends on PLL RC filter: worst case is choosen + // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus + // Specification (+/- 0.25% for full speed) + /////////////////////////////////////////////////////////////////////////// + AT91C_BASE_PMC->PMC_PLLR = AT91C_CKGR_USBDIV_1 | + (16 << 8) | + (AT91C_CKGR_MUL & (72 << 16)) | + (AT91C_CKGR_DIV & 14); + // Wait for PLL stabilization + while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) ); + // Wait until the master clock is established for the case we already + // turn on the PLL + while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); - - // If we are running off a j-link then the PLL will have already been setup. - if( !( pPMC->PMC_MCKR & AT91C_PMC_CSS_PLL_CLK ) ) - { - //* Set MCK at 47 923 200 - // 1 Enabling the Main Oscillator: - // SCK = 1/32768 = 30.51 uSeconde - // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms - pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN )); - // Wait the startup time - while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS)); - // 2 Checking the Main Oscillator Frequency (Optional) - // 3 Setting PLL and divider: - // - div by 5 Fin = 3,6864 =(18,432 / 5) - // - Mul 25+1: Fout = 95,8464 =(3,6864 *26) - // for 96 MHz the erroe is 0.16% - //eld out NOT USED = 0 Fi - pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) | - (AT91C_CKGR_PLLCOUNT & (28<<8)) | - (AT91C_CKGR_MUL & (25<<16))); + /////////////////////////////////////////////////////////////////////////// + // Init PMC Step 3. + // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz + // The PMC_MCKR register must not be programmed in a single write operation + // (see. Product Errata Sheet) + /////////////////////////////////////////////////////////////////////////// + AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; + // Wait until the master clock is established + while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); - // Wait the startup time - while(!(pPMC->PMC_SR & AT91C_PMC_LOCK)); - // 4. Selection of Master Clock and Processor Clock - // select the PLL clock divided by 2 + AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + // Wait until the master clock is established + while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); - pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ; - while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); + /////////////////////////////////////////////////////////////////////////// + // Disable Watchdog (write once register) + /////////////////////////////////////////////////////////////////////////// + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; - - pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ; - while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)); - } - - // Set up the default interrupts handler vectors - AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; - for (i=1;i < 31; i++) - { - AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; - } - AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ; + /////////////////////////////////////////////////////////////////////////// + // Init AIC: assign corresponding handler for each interrupt source + /////////////////////////////////////////////////////////////////////////// + AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; + } + AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler; } - - - diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep deleted file mode 100644 index 04b6ad8ff..000000000 --- a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.dep +++ /dev/null @@ -1,1590 +0,0 @@ - - - - 2 - - Flash Debug - - $PROJ_DIR$\uip\uipopt.h - $PROJ_DIR$\uip\fsdata.h - $TOOLKIT_DIR$\inc\intrinsic.h - $PROJ_DIR$\Flash_Debug\Obj\uip_arp.r79 - $PROJ_DIR$\Flash_Debug\Obj\queue.r79 - $PROJ_DIR$\Flash_Debug\Obj\ParTest.r79 - $PROJ_DIR$\Flash_Debug\Obj\list.r79 - $PROJ_DIR$\Flash_Debug\Obj\PollQ.r79 - $PROJ_DIR$\..\..\Source\portable\IAR\AtmelSAM7S64\lib_AT91SAM7X256.h - $PROJ_DIR$\uip\uip.c - $PROJ_DIR$\..\..\Source\tasks.c - $PROJ_DIR$\..\..\Source\include\semphr.h - $PROJ_DIR$\uip\cgi.c - $PROJ_DIR$\uip\fs.c - $PROJ_DIR$\uip\httpd.c - $PROJ_DIR$\Flash_Debug\Obj\death.r79 - $PROJ_DIR$\SrcIAR\Board.h - $PROJ_DIR$\..\Common\include\BlockQ.h - $PROJ_DIR$\..\..\Source\include\portable.h - $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c - $PROJ_DIR$\SrcIAR\Cstartup.s79 - $PROJ_DIR$\uip\uip_arp.c - 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- - BICOMP - 44 75 71 68 46 30 76 36 67 32 86 74 5 93 14 26 6 16 48 45 43 42 47 79 39 65 35 64 15 31 70 - - - - - [ROOT_NODE] - - - XLINK - 91 124 60 - - - - - $PROJ_DIR$\..\..\Source\list.c - - - ICCARM - 130 - - - BICOMP - 129 - - - - - ICCARM - 44 75 71 49 68 46 30 76 67 32 86 74 5 14 26 6 16 48 43 - - - - - $PROJ_DIR$\..\Common\Minimal\BlockQ.c - - - ICCARM - 135 - - - BICOMP - 13 - - - - - ICCARM - 44 75 71 49 68 46 30 76 67 32 86 74 5 14 26 6 16 48 45 43 127 15 - - - BICOMP - 44 75 71 68 46 30 76 67 32 86 74 5 93 14 26 6 16 48 45 43 127 15 - - - - - - - diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd index 88dde96a3..8515ff40d 100644 --- a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd +++ b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewd @@ -12,7 +12,7 @@ C-SPY 2 - 12 + 15 1 1 - - - - + @@ -129,13 +117,25 @@ ARMSIM_ID 2 - 0 + 1 1 1 + + + @@ -181,6 +181,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 1 + + + + + + + + + IARROM_ID 2 @@ -220,7 +257,7 @@ JLINK_ID 2 - 1 + 9 1 1 + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 1 + + @@ -273,7 +401,7 @@ MACRAIGOR_ID 2 - 1 + 2 1 1 + + + @@ -426,23 +566,23 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 @@ -450,7 +590,23 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin 0 @@ -465,7 +621,7 @@ C-SPY 2 - 12 + 15 1 0 - - - - + @@ -582,13 +726,25 @@ ARMSIM_ID 2 - 0 + 1 1 0 + + + @@ -634,6 +790,43 @@ + + GDBSERVER_ID + 2 + + 0 + 1 + 0 + + + + + + + + + IARROM_ID 2 @@ -673,7 +866,7 @@ JLINK_ID 2 - 1 + 9 1 0 + + + + + + + + + + + + + + + + + + + + + + LMIFTDI_ID + 2 + + 1 + 1 + 0 + + @@ -726,7 +1010,7 @@ MACRAIGOR_ID 2 - 1 + 2 1 0 + + + @@ -879,23 +1175,23 @@ - $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Profiling\Profiling.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ewplugin + 0 - $EW_DIR$\common\plugins\Trace\Trace.ewplugin - 1 + $TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin 0 - $TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\PowerPac\PowerPacRTOS.ewplugin 0 @@ -903,9 +1199,25 @@ 0 - $TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin 0 + + $EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin + 0 + + + $EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin + 1 + + + $EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin + 1 + diff --git a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp index 5d133f4b6..eac930951 100644 --- a/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp +++ b/Demo/uIP_Demo_IAR_ARM7/rtosdemo.ewp @@ -10,15 +10,11 @@ 1 General - 2 + 3 - 9 + 14 1 1 - - - - + + + ICCARM 2 - 13 + 19 1 1 - - - - - - - - - - - - - - + + + + + + AARM 2 - 6 + 7 1 1 - - - + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + CUSTOM 3 @@ -555,283 +536,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 1 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 1 @@ -850,15 +782,11 @@ 0 General - 2 + 3 - 9 + 14 1 0 - - - - + + + ICCARM 2 - 13 + 19 1 0 - - - - - - - - - - - - - - + + + + + + AARM 2 - 6 + 7 1 0 - - - + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + CUSTOM 3 @@ -1395,283 +1308,234 @@ - XLINK - 2 + ILINK + 0 - 18 + 5 1 0 - - - - - - - - - - - - XAR - 2 + IARCHIVE + 0 0 1 0 @@ -1770,7 +1634,7 @@ - $PROJ_DIR$\SrcIAR\Cstartup.s79 + $PROJ_DIR$\SrcIAR\Cstartup.s $PROJ_DIR$\SrcIAR\Cstartup_SAM7.c