From: richardbarry Date: Sun, 1 Apr 2007 19:37:01 +0000 (+0000) Subject: Add AVR32 port and demo files. X-Git-Tag: V4.2.1~6 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=bab0e0b61bd94ef1b36bf5e7ba2444466fe621a3;p=freertos Add AVR32 port and demo files. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@71 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/Makefile b/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/Makefile new file mode 100644 index 000000000..c529c5cca --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/Makefile @@ -0,0 +1,464 @@ +# Hey Emacs, this is a -*- makefile -*- + +# Goals available on make command line: +# +# [all] Default goal: build the project. +# clean Clean up the project. +# rebuild Rebuild the project. +# ccversion Display CC version information. +# cppfiles file.i Generate preprocessed files from C source files. +# asfiles file.x Generate preprocessed assembler files from C and assembler source files. +# objfiles file.o Generate object files from C and assembler source files. +# a file.a Archive: create A output file from object files. +# elf file.elf Link: create ELF output file from object files. +# lss file.lss Create extended listing from target output file. +# sym file.sym Create symbol table from target output file. +# bin file.bin Create binary image from ELF output file. +# sizes Display target size information. +# cpuinfo Get CPU information. +# halt Stop CPU execution. +# program Program MCU memory from ELF output file. +# reset Reset CPU. +# debug Open a debug connection with the MCU. +# run Start CPU execution. +# readregs Read CPU registers. +# doc Build the documentation. +# cleandoc Clean up the documentation. +# rebuilddoc Rebuild the documentation. +# verbose Display main executed commands. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# ENVIRONMENT SETTINGS +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +FirstWord = $(if $(1),$(word 1,$(1))) +LastWord = $(if $(1),$(word $(words $(1)),$(1))) + +MAKE = make +MAKECFG = config.mk +TGTTYPE = $(suffix $(TARGET)) +TGTFILE = $(PART)-$(TARGET) + +RM = rm -Rf + +AR = avr32-ar +ARFLAGS = rcs + +CPP = $(CC) -E +CPPFLAGS = -march=$(ARCH) -mpart=$(PART) $(WARNINGS) $(DEFS) \ + $(PLATFORM_INC_PATH:%=-I%) $(INC_PATH:%=-I%) $(CPP_EXTRA_FLAGS) +DPNDFILES = $(CSRCS:.c=.d) $(ASSRCS:.S=.d) +CPPFILES = $(CSRCS:.c=.i) + +CC = avr32-gcc +CFLAGS = $(DEBUG) $(OPTIMIZATION) $(C_EXTRA_FLAGS) +ASFILES = $(CSRCS:.c=.x) $(ASSRCS:.S=.x) + +AS = avr32-as +ASFLAGS = $(DEBUG) $(AS_EXTRA_FLAGS) +OBJFILES = $(CSRCS:.c=.o) $(ASSRCS:.S=.o) + +LD = avr32-ld +LDFLAGS = -march=$(ARCH) -mpart=$(PART) \ + $(LIB_PATH:%=-L%) $(LINKER_SCRIPT:%=-T%) $(LD_EXTRA_FLAGS) +LOADLIBES = +LDLIBS = $(LIBS:%=-l%) + +OBJDUMP = avr32-objdump +LSS = $(TGTFILE:$(TGTTYPE)=.lss) + +NM = avr32-nm +SYM = $(TGTFILE:$(TGTTYPE)=.sym) + +OBJCOPY = avr32-objcopy +BIN = $(TGTFILE:$(TGTTYPE)=.bin) + +SIZE = avr32-size + +SUDO = $(shell if [ -x /usr/bin/sudo ]; then echo sudo; fi) + +SLEEP = sleep +SLEEPUSB = 9 + +PROGRAM = avr32program + +DBGPROXY = avr32gdbproxy + +DOCGEN = doxygen + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MESSAGES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +ERR_TARGET_TYPE = Target type not supported: `$(TGTTYPE)' +MSG_CLEANING = Cleaning project. +MSG_PREPROCESSING = Preprocessing \`$<\' to \`$@\'. +MSG_COMPILING = Compiling \`$<\' to \`$@\'. +MSG_ASSEMBLING = Assembling \`$<\' to \`$@\'. +MSG_ARCHIVING = Archiving to \`$@\'. +MSG_LINKING = Linking to \`$@\'. +MSG_EXTENDED_LISTING = Creating extended listing to \`$@\'. +MSG_SYMBOL_TABLE = Creating symbol table to \`$@\'. +MSG_BINARY_IMAGE = Creating binary image to \`$@\'. +MSG_GETTING_CPU_INFO = Getting CPU information. +MSG_HALTING = Stopping CPU execution. +MSG_PROGRAMMING = Programming MCU memory from \`$<\'. +MSG_RESETTING = Resetting CPU. +MSG_DEBUGGING = Opening debug connection with MCU. +MSG_RUNNING = Starting CPU execution. +MSG_READING_CPU_REGS = Reading CPU registers. +MSG_CLEANING_DOC = Cleaning documentation. +MSG_GENERATING_DOC = Generating documentation to \`$(DOC_PATH)\'. + + +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** +# MAKE RULES +# ** ** ** *** ** ** ** ** ** ** ** ** ** ** ** + +# Include the make configuration file. +include $(MAKECFG) + +# ** ** TOP-LEVEL RULES ** ** + +# Default goal: build the project. +ifeq ($(TGTTYPE),.a) +.PHONY: all +all: ccversion a lss sym +else +ifeq ($(TGTTYPE),.elf) +.PHONY: all +all: ccversion elf lss sym bin sizes +else +$(error $(ERR_TARGET_TYPE)) +endif +endif + +# Clean up the project. +.PHONY: clean +clean: + @echo $(MSG_CLEANING) + -$(VERBOSE_CMD)$(RM) $(BIN) + -$(VERBOSE_CMD)$(RM) $(SYM) + -$(VERBOSE_CMD)$(RM) $(LSS) + -$(VERBOSE_CMD)$(RM) $(TGTFILE) + -$(VERBOSE_CMD)$(RM) $(OBJFILES) + -$(VERBOSE_CMD)$(RM) $(ASFILES) + -$(VERBOSE_CMD)$(RM) $(CPPFILES) + -$(VERBOSE_CMD)$(RM) $(DPNDFILES) + $(VERBOSE_NL) + +# Rebuild the project. +.PHONY: rebuild +rebuild: clean all + +# Display CC version information. +.PHONY: ccversion +ccversion: + @echo + @echo + @$(CC) --version + +# Generate preprocessed files from C source files. +.PHONY: cppfiles +cppfiles: $(CPPFILES) + +# Generate preprocessed assembler files from C and assembler source files. +.PHONY: asfiles +asfiles: $(ASFILES) + +# Generate object files from C and assembler source files. +.PHONY: objfiles +objfiles: $(OBJFILES) + +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.PHONY: a +a: $(TGTFILE) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.PHONY: elf +elf: $(TGTFILE) +endif +endif + +# Create extended listing from target output file. +.PHONY: lss +lss: $(LSS) + +# Create symbol table from target output file. +.PHONY: sym +sym: $(SYM) + +ifeq ($(TGTTYPE),.elf) +# Create binary image from ELF output file. +.PHONY: bin +bin: $(BIN) +endif + +# Display target size information. +.PHONY: sizes +sizes: $(TGTFILE) + @echo + @echo + @$(SIZE) -Ax $< + +ifeq ($(TGTTYPE),.elf) + +# Get CPU information. +.PHONY: cpuinfo +cpuinfo: + @echo + @echo $(MSG_GETTING_CPU_INFO) + $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB cpuinfo +ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),cpuinfo) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Stop CPU execution. +.PHONY: halt +halt: +ifeq ($(filter cpuinfo program reset run readregs,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_HALTING) + $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB halt +ifneq ($(call LastWord,$(filter halt debug,$(MAKECMDGOALS))),halt) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @echo > /dev/null +endif + +# Program MCU memory from ELF output file. +.PHONY: program +program: $(TGTFILE) + @echo + @echo $(MSG_PROGRAMMING) + $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB program $(FLASH:%=-f%) -e -v -R $(if $(findstring run,$(MAKECMDGOALS)),-r) $< +ifneq ($(call LastWord,$(filter cpuinfo program debug readregs,$(MAKECMDGOALS))),program) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Reset CPU. +.PHONY: reset +reset: +ifeq ($(filter program run,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RESETTING) + $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB reset +ifneq ($(call LastWord,$(filter cpuinfo reset debug readregs,$(MAKECMDGOALS))),reset) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @echo > /dev/null +endif + +# Open a debug connection with the MCU. +.PHONY: debug +debug: + @echo + @echo $(MSG_DEBUGGING) + $(VERBOSE_CMD)$(SUDO) $(DBGPROXY) -cUSB $(patsubst cfi@%,-f%,$(FLASH:internal@%=-f%)) +ifneq ($(call LastWord,$(filter cpuinfo halt program reset debug run readregs,$(MAKECMDGOALS))),debug) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +# Start CPU execution. +.PHONY: run +run: +ifeq ($(findstring program,$(MAKECMDGOALS)),) + @echo + @echo $(MSG_RUNNING) + $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB run $(if $(findstring reset,$(MAKECMDGOALS)),-R) +ifneq ($(call LastWord,$(filter cpuinfo debug run readregs,$(MAKECMDGOALS))),run) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif +else + @echo > /dev/null +endif + +# Read CPU registers. +.PHONY: readregs +readregs: + @echo + @echo $(MSG_READING_CPU_REGS) + $(VERBOSE_CMD)$(SUDO) $(PROGRAM) -cUSB readregs +ifneq ($(call LastWord,$(filter cpuinfo program reset debug run readregs,$(MAKECMDGOALS))),readregs) + @$(SLEEP) $(SLEEPUSB) +else + @echo +endif + +endif + +# Build the documentation. +.PHONY: doc +doc: + @echo + @echo $(MSG_GENERATING_DOC) + $(VERBOSE_CMD)cd $(dir $(DOC_CFG)) && $(DOCGEN) $(notdir $(DOC_CFG)) + @echo + +# Clean up the documentation. +.PHONY: cleandoc +cleandoc: + @echo $(MSG_CLEANING_DOC) + -$(VERBOSE_CMD)$(RM) $(DOC_PATH) + $(VERBOSE_NL) + +# Rebuild the documentation. +.PHONY: rebuilddoc +rebuilddoc: cleandoc doc + +# Display main executed commands. +.PHONY: verbose +ifeq ($(MAKECMDGOALS),verbose) +verbose: all +else +verbose: + @echo > /dev/null +endif +ifneq ($(findstring verbose,$(MAKECMDGOALS)),) +# Prefix displaying the following command if and only if verbose is a goal. +VERBOSE_CMD = +# New line displayed if and only if verbose is a goal. +VERBOSE_NL = @echo +else +VERBOSE_CMD = @ +VERBOSE_NL = +endif + +# ** ** COMPILATION RULES ** ** + +# Include silently the dependency files. +-include $(DPNDFILES) + +# The dependency files are not built alone but along with first generation files. +$(DPNDFILES): + +# First generation files depend on make files. +$(CPPFILES) $(ASFILES) $(OBJFILES): Makefile $(MAKECFG) + +ifeq ($(TGTTYPE),.elf) +# Files resulting from linking depend on linker script. +$(TGTFILE): $(LINKER_SCRIPT) +endif + +# Preprocess: create preprocessed files from C source files. +%.i: %.c %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.i $*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & compile: create assembler files from C source files. +%.x: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -S $(CPPFLAGS) -MD -MP -MT '$*.i $*.o' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess: create preprocessed files from assembler source files. +%.x: %.S %.d + @echo $(MSG_PREPROCESSING) + $(VERBOSE_CMD)$(CPP) $(CPPFLAGS) -MD -MP -MT '$*.x $*.o' -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess, compile & assemble: create object files from C source files. +%.o: %.c %.d + @echo $(MSG_COMPILING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.i $*.x' $(CFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +# Preprocess & assemble: create object files from assembler source files. +%.o: %.S %.d + @echo $(MSG_ASSEMBLING) + $(VERBOSE_CMD)$(CC) -c $(CPPFLAGS) -MD -MP -MT '$*.x' $(ASFLAGS) -o $@ $< + @touch $*.d + @touch $@ + $(VERBOSE_NL) + +.PRECIOUS: $(OBJFILES) +ifeq ($(TGTTYPE),.a) +# Archive: create A output file from object files. +.SECONDARY: $(TGTFILE) +$(TGTFILE): $(OBJFILES) + @echo $(MSG_ARCHIVING) + $(VERBOSE_CMD)$(AR) $(ARFLAGS) $@ $(filter %.o,$+) + $(VERBOSE_NL) +else +ifeq ($(TGTTYPE),.elf) +# Link: create ELF output file from object files. +.SECONDARY: $(TGTFILE) +$(TGTFILE): $(OBJFILES) + @echo $(MSG_LINKING) + $(VERBOSE_CMD)$(CC) $(LDFLAGS) $(filter %.o,$+) $(LOADLIBES) $(LDLIBS) -o $@ + $(VERBOSE_NL) +endif +endif + +# Create extended listing from target output file. +$(LSS): $(TGTFILE) + @echo $(MSG_EXTENDED_LISTING) + $(VERBOSE_CMD)$(OBJDUMP) -h -S $< > $@ + $(VERBOSE_NL) + +# Create symbol table from target output file. +$(SYM): $(TGTFILE) + @echo $(MSG_SYMBOL_TABLE) + $(VERBOSE_CMD)$(NM) -n $< > $@ + $(VERBOSE_NL) + +ifeq ($(TGTTYPE),.elf) +# Create binary image from ELF output file. +$(BIN): $(TGTFILE) + @echo $(MSG_BINARY_IMAGE) + $(VERBOSE_CMD)$(OBJCOPY) -O binary $< $@ + $(VERBOSE_NL) +endif diff --git a/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/config.mk b/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/config.mk new file mode 100644 index 000000000..a81384a24 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/config.mk @@ -0,0 +1,194 @@ +# Hey Emacs, this is a -*- makefile -*- + +# The purpose of this file is to define the build configuration variables used +# by the generic Makefile. See Makefile header for further information. + +# Copyright (c) 2007, Atmel Corporation All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation and/ +# or other materials provided with the distribution. +# +# 3. The name of ATMEL may not be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND +# SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, +# INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, +# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +# Base paths +PRJ_PATH = ../.. +APPS_PATH = $(PRJ_PATH)/APPLICATIONS +BRDS_PATH = $(PRJ_PATH)/BOARDS +COMP_PATH = $(PRJ_PATH)/COMPONENTS +DRVR_PATH = $(PRJ_PATH)/DRIVERS +SERV_PATH = $(PRJ_PATH)/SERVICES +UTIL_PATH = $(PRJ_PATH)/UTILS + +# Demo paths +FREERTOS_PATH = ../../../.. +FREERTOS_PORT_PATH = $(FREERTOS_PATH)/Source/portable/GCC/AVR32_UC3 +FREERTOS_MEM_PATH = $(FREERTOS_PATH)/Source/portable/MemMang +DEMO_PATH = ../.. +ETH_PATH = $(DEMO_PATH)/NETWORK +WEB_PATH = $(ETH_PATH)/BasicWEB +TFTP_PATH = $(ETH_PATH)/BasicTFTP +SMTP_PATH = $(ETH_PATH)/BasicSMTP +EMAC_PATH = $(ETH_PATH)/EMAC +LWIP_PATH = $(FREERTOS_PATH)/Demo/Common/ethernet/lwIP +LWIP_PORT_PATH = $(ETH_PATH)/lwip-port/AT32UC3A + +# CPU architecture: {ap|uc} +ARCH = uc + +# Part: {none|ap7000|ap7010|ap7020|uc3a0256|uc3a0512|uc3a1128|uc3a1256|uc3a1512} +PART = uc3a0512 + +# Flash memories: [type@address,size]... +FLASH = internal@0x80000000,512Kb + +# Device/Platform/Board include path +PLATFORM_INC_PATH = \ + $(BRDS_PATH)/ + +# Target name: {*.a|*.elf} +TARGET = lwipdemo.elf + +# Definitions: [-D name[=definition]...] [-U name...] +# Things that might be added to DEFS: +# BOARD Board used: {EVK1100} +DEFS = -D BOARD=EVK1100 -D FREERTOS_USED -D HTTP_USED=1 -D TFTP_USED=1 -D SMTP_USED=0 + +# Include path +INC_PATH = \ + $(UTIL_PATH)/ \ + $(UTIL_PATH)/PREPROCESSOR/ \ + $(DRVR_PATH)/INTC/ \ + $(DRVR_PATH)/TC/ \ + $(DRVR_PATH)/PM/ \ + $(DRVR_PATH)/GPIO/ \ + $(DRVR_PATH)/FLASHC/ \ + $(DEMO_PATH)/ \ + $(FREERTOS_PATH)/Source/include/ \ + $(FREERTOS_PATH)/Demo/Common/include/ \ + $(FREERTOS_PORT_PATH)/ \ + $(FREERTOS_MEM_PATH)/ \ + $(ETH_PATH)/ \ + $(EMAC_PATH)/ \ + $(LWIP_PATH)/include/ \ + $(LWIP_PATH)/include/ipv4/ \ + $(LWIP_PORT_PATH)/ \ + $(WEB_PATH)/ \ + $(TFTP_PATH)/ \ + $(SMTP_PATH)/ + +# C source files + +LWIP_SRC = \ + $(LWIP_PATH)/core/inet.c \ + $(LWIP_PATH)/core/mem.c \ + $(LWIP_PATH)/core/memp.c \ + $(LWIP_PATH)/core/netif.c \ + $(LWIP_PATH)/core/pbuf.c \ + $(LWIP_PATH)/core/raw.c \ + $(LWIP_PATH)/core/stats.c \ + $(LWIP_PATH)/core/sys.c \ + $(LWIP_PATH)/core/tcp.c \ + $(LWIP_PATH)/core/tcp_in.c \ + $(LWIP_PATH)/core/tcp_out.c \ + $(LWIP_PATH)/core/ipv4/ip.c \ + $(LWIP_PATH)/core/ipv4/ip_addr.c \ + $(LWIP_PATH)/core/ipv4/icmp.c \ + $(LWIP_PATH)/api/sockets.c \ + $(LWIP_PATH)/api/tcpip.c \ + $(LWIP_PATH)/api/api_msg.c \ + $(LWIP_PATH)/api/err.c \ + $(LWIP_PATH)/api/api_lib.c \ + $(LWIP_PATH)/netif/etharp.c \ + $(LWIP_PATH)/core/udp.c \ + $(LWIP_PATH)/core/ipv4/ip_frag.c + +CSRCS = \ + $(BRDS_PATH)/EVK1100/led.c \ + $(DRVR_PATH)/INTC/intc.c \ + $(DRVR_PATH)/TC/tc.c \ + $(DRVR_PATH)/PM/pm.c \ + $(DRVR_PATH)/GPIO/gpio.c \ + $(DRVR_PATH)/FLASHC/flashc.c \ + $(DEMO_PATH)/main.c \ + $(DEMO_PATH)/PARTEST/ParTest.c \ + $(DEMO_PATH)/SERIAL/serial.c \ + $(FREERTOS_PATH)/Source/tasks.c \ + $(FREERTOS_PATH)/Source/queue.c \ + $(FREERTOS_PATH)/Source/list.c \ + $(FREERTOS_PATH)/Source/croutine.c \ + $(FREERTOS_PATH)/Demo/Common/Minimal/flash.c \ + $(FREERTOS_PORT_PATH)/port.c \ + $(FREERTOS_MEM_PATH)/heap_3.c \ + $(LWIP_SRC) \ + $(LWIP_PORT_PATH)/sys_arch.c \ + $(LWIP_PORT_PATH)/ethernetif.c \ + $(WEB_PATH)/BasicWEB.c \ + $(TFTP_PATH)/BasicTFTP.c \ + $(SMTP_PATH)/BasicSMTP.c \ + $(ETH_PATH)/ethernet.c \ + $(EMAC_PATH)/AVR32_EMAC.c \ + $(EMAC_PATH)/AVR32_EMAC_ISR.c \ + $(DEMO_PATH)/printf-stdarg.c + +# Assembler source files +ASSRCS = \ + $(FREERTOS_PORT_PATH)/exception.S + +# Library path +LIB_PATH = + +# Libraries to link with the project +LIBS = + +# Linker script file if any +LINKER_SCRIPT = + +# Options to request or suppress warnings: [-fsyntax-only] [-pedantic[-errors]] [-w] [-Wwarning...] +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +WARNINGS = -Wall + +# Options for debugging: [-g]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +DEBUG = -g + +# Options that control optimization: [-O[0|1|2|3|s]]... +# For further details, refer to the chapter "GCC Command Options" of the GCC manual. +OPTIMIZATION = -O0 -ffunction-sections -fdata-sections + +# Extra flags to use when preprocessing +CPP_EXTRA_FLAGS = + +# Extra flags to use when compiling +C_EXTRA_FLAGS = + +# Extra flags to use when assembling +AS_EXTRA_FLAGS = + +# Extra flags to use when linking +LD_EXTRA_FLAGS = -Wl,--gc-sections + +# Documentation path +DOC_PATH = ./DOC/ + +# Documentation configuration file +DOC_CFG = ./doxyfile.doxygen diff --git a/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb.ini b/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb.ini new file mode 100644 index 000000000..3e2d67002 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/AT32UC3A/GCC/gdb.ini @@ -0,0 +1,8 @@ +target extended-remote 127.0.0.1:1024 +symbol uc3a0512-demo.elf + + +define current_task +printf "Task name: %s\n", ((tskTCB *)pxCurrentTCB)->pcTaskName +printf "pxTopOfStack: %x\n", ((tskTCB *)pxCurrentTCB)->pxTopOfStack +end diff --git a/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/evk1100.h b/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/evk1100.h new file mode 100644 index 000000000..bec0ecd3f --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/evk1100.h @@ -0,0 +1,318 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board header file. + * + * This file contains definitions and services related to the features of the + * EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _EVK1100_H_ +#define _EVK1100_H_ + +#include "compiler.h" + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. +# include "led.h" +#endif // __AVR32_ABI_COMPILER__ + + +/*! \name Oscillator Definitions + */ +//! @{ + +// RCOsc has no custom calibration by default. Set the following definition to +// the appropriate value if a custom RCOsc calibration has been applied to your +// part. +//#define FRCOSC 115200 //!< RCOsc frequency: Hz. + +#define FOSC32 32000 //!< Osc32 frequency: Hz. +#define OSC32_STARTUP 3 //!< Osc32 startup time: RCOsc periods. + +#define FOSC0 12000000 //!< Osc0 frequency: Hz. +#define OSC0_STARTUP 3 //!< Osc0 startup time: RCOsc periods. + +// Osc1 crystal is not mounted by default. Set the following definitions to the +// appropriate values if a custom Osc1 crystal is mounted on your board. +//#define FOSC1 12000000 //!< Osc1 frequency: Hz. +//#define OSC1_STARTUP 3 //!< Osc1 startup time: RCOsc periods. + +//! @} + + +/*! \name SDRAM Definitions + */ +//! @{ + +//! Part header file of used SDRAM(s). +#define SDRAM_PART_HDR "MT48LC16M16A2TG7E/mt48lc16m16a2tg7e.h" + +//! Data bus width to use the SDRAM(s) with (16 or 32 bits; always 16 bits on +//! UC3). +#define SDRAM_DBW 16 + +//! @} + + +/*! \name USB Definitions + */ +//! @{ + +//! Multiplexed pin used for USB_ID: AVR32_USBB_USB_ID_x_x. +//! To be selected according to the AVR32_USBB_USB_ID_x_x_PIN and +//! AVR32_USBB_USB_ID_x_x_FUNCTION definitions from . +#define USB_ID AVR32_USBB_USB_ID_0_0 + +//! Multiplexed pin used for USB_VBOF: AVR32_USBB_USB_VBOF_x_x. +//! To be selected according to the AVR32_USBB_USB_VBOF_x_x_PIN and +//! AVR32_USBB_USB_VBOF_x_x_FUNCTION definitions from . +#ifdef EVK1100_REVA +# define USB_VBOF AVR32_USBB_USB_VBOF_0_0 +#else +# define USB_VBOF AVR32_USBB_USB_VBOF_0_1 +#endif + +//! Active level of the USB_VBOF output pin. +#ifdef EVK1100_REVA +# define USB_VBOF_ACTIVE_LEVEL HIGH +#else +# define USB_VBOF_ACTIVE_LEVEL LOW +#endif + +//! @} + + +//! GPIO connection of the MAC PHY PWR_DOWN/INT signal. +#ifdef EVK1100_REVA +# define MACB_INTERRUPT_PIN AVR32_PIN_PX12 +#else +# define MACB_INTERRUPT_PIN AVR32_PIN_PA24 +#endif + + +//! Number of LEDs. +#define LED_COUNT 8 + +/*! \name GPIO Connections of LEDs + */ +//! @{ +#ifdef EVK1100_REVA +# define LED0_GPIO AVR32_PIN_PX13 +# define LED1_GPIO AVR32_PIN_PX14 +# define LED2_GPIO AVR32_PIN_PX15 +# define LED3_GPIO AVR32_PIN_PX16 +# define LED4_GPIO AVR32_PIN_PB19 +# define LED5_GPIO AVR32_PIN_PB20 +# define LED6_GPIO AVR32_PIN_PB21 +# define LED7_GPIO AVR32_PIN_PB22 +#else +# define LED0_GPIO AVR32_PIN_PB27 +# define LED1_GPIO AVR32_PIN_PB28 +# define LED2_GPIO AVR32_PIN_PB29 +# define LED3_GPIO AVR32_PIN_PB30 +# define LED4_GPIO AVR32_PIN_PB19 +# define LED5_GPIO AVR32_PIN_PB20 +# define LED6_GPIO AVR32_PIN_PB21 +# define LED7_GPIO AVR32_PIN_PB22 +#endif +//! @} + +/*! \name PWM Channels of LEDs + */ +//! @{ +#define LED0_PWM (-1) +#define LED1_PWM (-1) +#define LED2_PWM (-1) +#define LED3_PWM (-1) +#define LED4_PWM 0 +#define LED5_PWM 1 +#define LED6_PWM 2 +#define LED7_PWM 3 +//! @} + +/*! \name PWM Functions of LEDs + */ +//! @{ +#define LED0_PWM_FUNCTION (-1) +#define LED1_PWM_FUNCTION (-1) +#define LED2_PWM_FUNCTION (-1) +#define LED3_PWM_FUNCTION (-1) +#define LED4_PWM_FUNCTION AVR32_PWM_PWM_0_FUNCTION +#define LED5_PWM_FUNCTION AVR32_PWM_PWM_1_FUNCTION +#define LED6_PWM_FUNCTION AVR32_PWM_PWM_2_FUNCTION +#define LED7_PWM_FUNCTION AVR32_PWM_PWM_3_FUNCTION +//! @} + +/*! \name Color Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#ifdef EVK1100_REVA +# define LED_MONO0_GREEN LED4 +# define LED_MONO1_GREEN LED5 +# define LED_MONO2_GREEN LED6 +# define LED_MONO3_GREEN LED7 +# define LED_BI0_GREEN LED1 +# define LED_BI0_RED LED0 +# define LED_BI1_GREEN LED3 +# define LED_BI1_RED LED2 +#else +# define LED_MONO0_GREEN LED0 +# define LED_MONO1_GREEN LED1 +# define LED_MONO2_GREEN LED2 +# define LED_MONO3_GREEN LED3 +# define LED_BI0_GREEN LED5 +# define LED_BI0_RED LED4 +# define LED_BI1_GREEN LED7 +# define LED_BI1_RED LED6 +#endif +//! @} + + +/*! \name GPIO Connections of Push Buttons + */ +//! @{ +#ifdef EVK1100_REVA +# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PB28 +# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PB29 +# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PB27 +#else +# define GPIO_PUSH_BUTTON_0 AVR32_PIN_PX16 +# define GPIO_PUSH_BUTTON_1 AVR32_PIN_PX19 +# define GPIO_PUSH_BUTTON_2 AVR32_PIN_PX22 +#endif +//! @} + + +/*! \name GPIO Connections of the Joystick + */ +//! @{ +#define GPIO_JOYSTICK_PUSH AVR32_PIN_PA20 +#define GPIO_JOYSTICK_LEFT AVR32_PIN_PA25 +#define GPIO_JOYSTICK_RIGHT AVR32_PIN_PA28 +#define GPIO_JOYSTICK_UP AVR32_PIN_PA26 +#define GPIO_JOYSTICK_DOWN AVR32_PIN_PA27 +//! @} + + +/*! \name ADC Connection of the Potentiometer + */ +//! @{ +#define ADC_POTENTIOMETER_CHANNEL 1 +#define ADC_POTENTIOMETER_PIN AVR32_ADC_AD_1_PIN +#define ADC_POTENTIOMETER_FUNCTION AVR32_ADC_AD_1_FUNCTION +//! @} + + +/*! \name ADC Connection of the Temperature Sensor + */ +//! @{ +#define ADC_TEMPERATURE_CHANNEL 0 +#define ADC_TEMPERATURE_PIN AVR32_ADC_AD_0_PIN +#define ADC_TEMPERATURE_FUNCTION AVR32_ADC_AD_0_FUNCTION +//! @} + + +/*! \name ADC Connection of the Light Sensor + */ +//! @{ +#define ADC_LIGHT_CHANNEL 2 +#define ADC_LIGHT_PIN AVR32_ADC_AD_2_PIN +#define ADC_LIGHT_FUNCTION AVR32_ADC_AD_2_FUNCTION +//! @} + + +/*! \name SPI Connections of the DIP204 LCD + */ +//! @{ +#define DIP204_SPI (&AVR32_SPI1) +#define DIP204_SPI_CS 2 +#define DIP204_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define DIP204_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define DIP204_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define DIP204_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define DIP204_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define DIP204_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define DIP204_SPI_NPCS_PIN AVR32_SPI1_NPCS_2_PIN +#define DIP204_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_2_FUNCTION +//! @} + +/*! \name GPIO and PWM Connections of the DIP204 LCD Backlight + */ +//! @{ +#define DIP204_BACKLIGHT_PIN AVR32_PIN_PB18 +#define DIP204_PWM_CHANNEL AVR32_PWM_CHID6 +#define DIP204_PWM_PIN AVR32_PWM_PWM_6_PIN +#define DIP204_PWM_FUNCTION AVR32_PWM_PWM_6_FUNCTION +//! @} + + +/*! \name SPI Connections of the AT45DBX Data Flash Memory + */ +//! @{ +#define AT45DBX_SPI (&AVR32_SPI1) +#define AT45DBX_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define AT45DBX_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define AT45DBX_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define AT45DBX_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define AT45DBX_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define AT45DBX_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define AT45DBX_SPI_NPCS0_PIN AVR32_SPI1_NPCS_0_PIN +#define AT45DBX_SPI_NPCS0_FUNCTION AVR32_SPI1_NPCS_0_FUNCTION +//! @} + + +/*! \name SPI Connections of the SD/MMC Connector + */ +//! @{ +#define SD_MMC_SPI (&AVR32_SPI1) +#define SD_MMC_SPI_CS 1 +#define SD_MMC_SPI_SCK_PIN AVR32_SPI1_SCK_0_PIN +#define SD_MMC_SPI_SCK_FUNCTION AVR32_SPI1_SCK_0_FUNCTION +#define SD_MMC_SPI_MISO_PIN AVR32_SPI1_MISO_0_PIN +#define SD_MMC_SPI_MISO_FUNCTION AVR32_SPI1_MISO_0_FUNCTION +#define SD_MMC_SPI_MOSI_PIN AVR32_SPI1_MOSI_0_PIN +#define SD_MMC_SPI_MOSI_FUNCTION AVR32_SPI1_MOSI_0_FUNCTION +#define SD_MMC_SPI_NPCS_PIN AVR32_SPI1_NPCS_1_PIN +#define SD_MMC_SPI_NPCS_FUNCTION AVR32_SPI1_NPCS_1_FUNCTION +//! @} + + +#endif // _EVK1100_H_ diff --git a/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.c b/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.c new file mode 100644 index 000000000..550b0c028 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.c @@ -0,0 +1,314 @@ +/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +#else +# error Unknown compiler +#endif + +#include "preprocessor.h" +#include "compiler.h" +#include "evk1100.h" +#include "led.h" + + +//! Structure describing LED hardware connections. +typedef const struct +{ + struct + { + U32 PORT; //!< LED GPIO port. + U32 PIN_MASK; //!< Bit-mask of LED pin in GPIO port. + } GPIO; //!< LED GPIO descriptor. + struct + { + S32 CHANNEL; //!< LED PWM channel (< 0 if N/A). + S32 FUNCTION; //!< LED pin PWM function (< 0 if N/A). + } PWM; //!< LED PWM descriptor. +} tLED_DESCRIPTOR; + + +//! Hardware descriptors of all LEDs. +static tLED_DESCRIPTOR LED_DESCRIPTOR[LED_COUNT] = +{ +#define INSERT_LED_DESCRIPTOR(LED_NO, unused) \ + { \ + {LED##LED_NO##_GPIO / 32, 1 << (LED##LED_NO##_GPIO % 32)},\ + {LED##LED_NO##_PWM, LED##LED_NO##_PWM_FUNCTION } \ + }, + MREPEAT(LED_COUNT, INSERT_LED_DESCRIPTOR, ~) +#undef INSERT_LED_DESCRIPTOR +}; + + +//! Saved state of all LEDs. +static U32 LED_State = (1 << LED_COUNT) - 1; + + +U32 LED_Read_Display(void) +{ + return LED_State; +} + + +void LED_Display(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor; + volatile avr32_gpio_port_t *led_gpio_port; + + leds &= (1 << LED_COUNT) - 1; + LED_State = leds; + for (led_descriptor = &LED_DESCRIPTOR[0]; + led_descriptor < LED_DESCRIPTOR + LED_COUNT; + led_descriptor++) + { + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + } +} + + +U32 LED_Read_Display_Mask(U32 mask) +{ + return Rd_bits(LED_State, mask); +} + + +void LED_Display_Mask(U32 mask, U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + mask &= (1 << LED_COUNT) - 1; + Wr_bits(LED_State, mask, leds); + while (mask) + { + led_shift = 1 + ctz(mask); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + leds >>= led_shift - 1; + if (leds & 1) + { + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= 1; + mask >>= led_shift; + } +} + + +Bool LED_Test(U32 leds) +{ + return Tst_bits(LED_State, leds); +} + + +void LED_Off(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Clr_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrs = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_On(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Set_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrc = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +void LED_Toggle(U32 leds) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + leds &= (1 << LED_COUNT) - 1; + Tgl_bits(LED_State, leds); + while (leds) + { + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + led_gpio_port->ovrt = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->oders = led_descriptor->GPIO.PIN_MASK; + led_gpio_port->gpers = led_descriptor->GPIO.PIN_MASK; + leds >>= led_shift; + } +} + + +U32 LED_Read_Display_Field(U32 field) +{ + return Rd_bitfield(LED_State, field); +} + + +void LED_Display_Field(U32 field, U32 leds) +{ + LED_Display_Mask(field, leds << ctz(field)); +} + + +U8 LED_Get_Intensity(U32 led) +{ + tLED_DESCRIPTOR *led_descriptor; + + // Check that the argument value is valid. + led = ctz(led); + led_descriptor = &LED_DESCRIPTOR[led]; + if (led >= LED_COUNT || led_descriptor->PWM.CHANNEL < 0) return 0; + + // Return the duty cycle value if the LED PWM channel is enabled, else 0. + return (AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL)) ? + AVR32_PWM.channel[led_descriptor->PWM.CHANNEL].cdty : 0; +} + + +void LED_Set_Intensity(U32 leds, U8 intensity) +{ + tLED_DESCRIPTOR *led_descriptor = &LED_DESCRIPTOR[0] - 1; + volatile avr32_pwm_channel_t *led_pwm_channel; + volatile avr32_gpio_port_t *led_gpio_port; + U8 led_shift; + + // For each specified LED... + for (leds &= (1 << LED_COUNT) - 1; leds; leds >>= led_shift) + { + // Select the next specified LED and check that it has a PWM channel. + led_shift = 1 + ctz(leds); + led_descriptor += led_shift; + if (led_descriptor->PWM.CHANNEL < 0) continue; + + // Initialize or update the LED PWM channel. + led_pwm_channel = &AVR32_PWM.channel[led_descriptor->PWM.CHANNEL]; + if (!(AVR32_PWM.sr & (1 << led_descriptor->PWM.CHANNEL))) + { + led_pwm_channel->cmr = (AVR32_PWM_CPRE_MCK << AVR32_PWM_CPRE_OFFSET) & + ~(AVR32_PWM_CALG_MASK | + AVR32_PWM_CPOL_MASK | + AVR32_PWM_CPD_MASK); + led_pwm_channel->cprd = 0x000000FF; + led_pwm_channel->cdty = intensity; + AVR32_PWM.ena = 1 << led_descriptor->PWM.CHANNEL; + } + else + { + AVR32_PWM.isr; + while (!(AVR32_PWM.isr & (1 << led_descriptor->PWM.CHANNEL))); + led_pwm_channel->cupd = intensity; + } + + // Switch the LED pin to its PWM function. + led_gpio_port = &AVR32_GPIO.port[led_descriptor->GPIO.PORT]; + if (led_descriptor->PWM.FUNCTION & 0x1) + { + led_gpio_port->pmr0s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr0c = led_descriptor->GPIO.PIN_MASK; + } + if (led_descriptor->PWM.FUNCTION & 0x2) + { + led_gpio_port->pmr1s = led_descriptor->GPIO.PIN_MASK; + } + else + { + led_gpio_port->pmr1c = led_descriptor->GPIO.PIN_MASK; + } + led_gpio_port->gperc = led_descriptor->GPIO.PIN_MASK; + } +} diff --git a/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.h b/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.h new file mode 100644 index 000000000..3b3afd808 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/BOARDS/EVK1100/led.h @@ -0,0 +1,188 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief AT32UC3A EVK1100 board LEDs support package. + * + * This file contains definitions and services related to the LED features of + * the EVK1100 board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 AT32UC3A devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _LED_H_ +#define _LED_H_ + +#include "compiler.h" + + +/*! \name Identifiers of LEDs to Use with LED Functions + */ +//! @{ +#define LED0 0x01 +#define LED1 0x02 +#define LED2 0x04 +#define LED3 0x08 +#define LED4 0x10 +#define LED5 0x20 +#define LED6 0x40 +#define LED7 0x80 +//! @} + + +/*! \brief Gets the last state of all LEDs set through the LED API. + * + * \return State of all LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display(void); + +/*! \brief Sets the state of all LEDs. + * + * \param leds New state of all LEDs (1 bit per LED). + * + * \note The pins of all LEDs are set to GPIO output mode. + */ +extern void LED_Display(U32 leds); + +/*! \brief Gets the last state of the specified LEDs set through the LED API. + * + * \param mask LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Mask(U32 mask); + +/*! \brief Sets the state of the specified LEDs. + * + * \param mask LEDs of which to set the state (1 bit per LED). + * + * \param leds New state of the specified LEDs (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Mask(U32 mask, U32 leds); + +/*! \brief Tests the last state of the specified LEDs set through the LED API. + * + * \param leds LEDs of which to test the state (1 bit per LED). + * + * \return \c TRUE if at least one of the specified LEDs has a state on, else + * \c FALSE. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern Bool LED_Test(U32 leds); + +/*! \brief Turns off the specified LEDs. + * + * \param leds LEDs to turn off (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Off(U32 leds); + +/*! \brief Turns on the specified LEDs. + * + * \param leds LEDs to turn on (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_On(U32 leds); + +/*! \brief Toggles the specified LEDs. + * + * \param leds LEDs to toggle (1 bit per LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Toggle(U32 leds); + +/*! \brief Gets as a bit-field the last state of the specified LEDs set through + * the LED API. + * + * \param field LEDs of which to get the state (1 bit per LED). + * + * \return State of the specified LEDs (1 bit per LED, beginning with the first + * specified LED). + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U32 LED_Read_Display_Field(U32 field); + +/*! \brief Sets as a bit-field the state of the specified LEDs. + * + * \param field LEDs of which to set the state (1 bit per LED). + * \param leds New state of the specified LEDs (1 bit per LED, beginning with + * the first specified LED). + * + * \note The pins of the specified LEDs are set to GPIO output mode. + */ +extern void LED_Display_Field(U32 field, U32 leds); + +/*! \brief Gets the intensity of the specified LED. + * + * \param led LED of which to get the intensity (1 bit per LED; only the least + * significant set bit is used). + * + * \return Intensity of the specified LED (0x00 to 0xFF). + * + * \warning The PWM channel of the specified LED is supposed to be used only by + * this module. + * + * \note The GPIO pin configuration of all LEDs is left unchanged. + */ +extern U8 LED_Get_Intensity(U32 led); + +/*! \brief Sets the intensity of the specified LEDs. + * + * \param leds LEDs of which to set the intensity (1 bit per LED). + * \param intensity New intensity of the specified LEDs (0x00 to 0xFF). + * + * \warning The PWM channels of the specified LEDs are supposed to be used only + * by this module. + * + * \note The pins of the specified LEDs are set to PWM output mode. + */ +extern void LED_Set_Intensity(U32 leds, U8 intensity); + + +#endif // _LED_H_ diff --git a/Demo/lwIP_AVR32_UC3/BOARDS/board.h b/Demo/lwIP_AVR32_UC3/BOARDS/board.h new file mode 100644 index 000000000..36484edcc --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/BOARDS/board.h @@ -0,0 +1,73 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Standard board header file. + * + * This file includes the appropriate board header file according to the + * defined board. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#if __GNUC__ +# include +#elif __ICCAVR32__ || __AAVR32__ +# include +#else +# error Unknown compiler +#endif + +#define EVK1100 1 //!< AT32UC3A EVK1100 board. + +#if BOARD == EVK1100 +# include "EVK1100/evk1100.h" +#else +# error No known AVR32 board defined +#endif + + +#ifndef FRCOSC +# define FRCOSC AVR32_PM_RCOSC_FREQUENCY //!< Default RCOsc frequency. +#endif + + +#endif // _BOARD_H_ diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.c b/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.c new file mode 100644 index 000000000..5b5d0c57e --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.c @@ -0,0 +1,283 @@ +/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Flash Controller driver. + * + * This file defines a useful set of functions for the flash controller + * on AVR32A devices. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32A devices. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "flashc.h" + +/*! Flash command key*/ +#define X_KEY 0xA5000000 + + +/*! Get locke error. + * \warning: Flash status register (FCR) is read, and Programmming error status may be automatically + * cleared when reading FCR. + */ +#define Flashc_get_lockerror() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_LOCKE_MASK)>>AVR32_FLASHC_FSR_LOCKE_OFFSET) + +/*! Get programming error. + * \warning: Flash status register (FCR) is read, and locke error status may be automatically + * cleared when reading FCR. + */ +#define Flashc_get_programming_error() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_PROGE_MASK)>>AVR32_FLASHC_FSR_PROGE_OFFSET) + +/*! Check if page is erased (used with the quick page read command result) + * \warning: Flash status register (FCR) is read, and error status may be automatically + * cleared when reading FCR. + */ +#define Flashc_is_page_erased() ((AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK)>>AVR32_FLASHC_FSR_QPRR_OFFSET) + +/*! Set: No erase is performed before programming. */ +#define Flashc_set_no_erase_before_programming() (AVR32_FLASHC.fcr |= AVR32_FLASHC_FCR_NEBP_MASK) + +/*! Set: Page erase is performed before programming. */ +#define Flashc_set_erase_before_programming() (AVR32_FLASHC.fcr &= ~AVR32_FLASHC_FCR_NEBP_MASK) + + +/*! + * Memcopy function + * \param *s1 destination + * \param *s2 source + * \param n word numbers to copy + */ +U32 *flashc_memcpy(U32 *s1, const U32 *s2, const U32 n) { + register U32 *u32pdst; + register U32 i; + u32pdst = s1; + for (i = n; i > 0; i--) *u32pdst++ = *s2++; + return s1; +} + +/*! + * Set number of wait state for flash controller. + */ +int flashc_set_wait_state(U16 ws) +{ + if (ws > 1 ) return FLASHC_INVALID_INPUT; + if (ws == 0) AVR32_FLASHC.fcr &= ~AVR32_FLASHC_FWS_MASK; // update flash control register FCR + if (ws == 1) AVR32_FLASHC.fcr |= AVR32_FLASHC_FWS_MASK; + return FLASHC_SUCCESS; +} + + +/*! + * Page write n + * \param n page number + * \warning Assuming the page address is already loaded + */ +void flashc_page_write_n(U16 page_n) { + register U32 u32Command; + u32Command = X_KEY | AVR32_FLASHC_FCMD_CMD_WP; // key and command + u32Command |= ((page_n<>AVR32_FLASHC_FSR_FRDY_OFFSET)); + + if (Flashc_is_page_erased() == 0) // check QPRR bit in FCR to have the result of the quick page read + return FLASHC_FAILURE; + return FLASHC_SUCCESS; +} + +/*! + * Page load and write + * \warning Dest is a FLASH address at a page size boundary + * (assuming the page is already erased) + */ +void flashc_page_copy_write(U32 *u32dest, const U32 *src) { + register U32 u32command,pagen; + flashc_memcpy(u32dest, src, AVR32_FLASHC_PAGE_SIZE / 4); // copy Src to Dest (Dest is a FLASH address at a page boundary) + pagen = (U32)(((U32)u32dest-AVR32_FLASH_ADDRESS)/AVR32_FLASHC_PAGE_SIZE); // memory page addr + u32command = X_KEY | ((pagen<= dst) //current address is inside the target range adr + { + u32Temp = * ((U32*)src); // load word from buffer src + src++; + n--; + } + else //current word addr out of dst target + { + u32Temp = flash_rd_word((U32 const*)u32Address); // load word from existing flash + } + } + else //complete page with words from existing flash + { + u32Temp = flash_rd_word((U32 const*)u32Address); + } + flash_fill_temp_buffer(u32Temp, u32Address); // fill page buffer + u32Address+=4; // one more word for u32Address + } + + // u32Address = u32SavePageAddr*AVR32_FLASHC_PAGE_SIZE+AVR32_FLASH_ADDRESS; + + /* + // Done with QPR + for(u32NbWord=0 ; u32NbWord>AVR32_FLASHC_FSR_FRDY_OFFSET)); + + if ( (AVR32_FLASHC.fsr & AVR32_FLASHC_FSR_QPRR_MASK)>> AVR32_FLASHC_FSR_QPRR_OFFSET == 0 ) // test QPR bit in FSR + { // erase page + AVR32_FLASHC.fcmd = X_KEY | ((u32SavePageAddr<>AVR32_FLASHC_FSR_FRDY_OFFSET)); + } + + flashc_page_write_n(u32SavePageAddr); // write the corresponding page number + flashc_clear_page_buffer(); + } // end while (n) + return FLASHC_SUCCESS; +} + +/* Erase all flash with pages access */ +void flash_erase(void) +{ + U32 u32NbPage = flashc_get_page_count(); + while (u32NbPage) flashc_erase_page(--u32NbPage); +} diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.h b/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.h new file mode 100644 index 000000000..d9d0e5f10 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/FLASHC/flashc.h @@ -0,0 +1,193 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Flash Controller driver .h file. + * + * This file defines a useful set of functions for the flash controller + * on AVR32A devices. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32A devices. + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _FLASHC_H_ +#define _FLASHC_H_ + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +# include +#else +# error Unknown compiler +#endif + +#include "compiler.h" + + +/*! Value returned by function when it completed successfully */ +#define FLASHC_SUCCESS 0 + +/*! Value returned by function when it was unable to complete successfully + for some unspecified reason */ +#define FLASHC_FAILURE -1 + +/*! Value returned by function when the input paramters are out of range */ +#define FLASHC_INVALID_INPUT 1 + + +/*! Get Flash size */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned int flashc_get_flash_size(void) +{ + static const unsigned int FLASHC_SIZE[1 << AVR32_FLASHC_FSR_FSZ_SIZE] = + { + 32 << 10, + 64 << 10, + 128 << 10, + 256 << 10, + 384 << 10, + 512 << 10, + 768 << 10, + 1024 << 10 + }; + + return FLASHC_SIZE[Rd_bitfield(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_FSZ_MASK)]; +} + +/*! Get Flash page count */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned int flashc_get_page_count(void) +{ + return flashc_get_flash_size() / AVR32_FLASHC_PAGE_SIZE; +} + +/*! Get Flash page count per region */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ unsigned int flashc_get_page_count_per_region(void) +{ + return flashc_get_page_count() / 16; +} + +/*! Wait flash ready status, the application must wait before running a new command. + * Warning: Flash status register (FCR) is read, and error status may be automatically + * cleared when reading FCR. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ void flashc_busy_wait(void) +{ + while (!Tst_bits(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_FRDY_MASK)); +} + +/*! Check if security bit is active. + * \warning: Flash status register (FCR) is read, and error status may be automatically + * cleared when reading FCR. + */ +#if __GNUC__ +__attribute__((__always_inline__)) +#endif +extern __inline__ Bool flashc_is_security_active(void) +{ + return Tst_bits(AVR32_FLASHC.fsr, AVR32_FLASHC_FSR_SECURITY_MASK); +} + +/*! \brief Memcopy function + * \param *s1 destination + * \param *s2 source + * \param n number of words to copy + */ +extern U32 *flashc_memcpy(U32 *s1, const U32 *s2, const U32 n); + +/*! \brief Set number of wait state + * \param ws 0 if for no-wait state, for 1 wait-state + * \return FLASHC_SUCCESS, FLASHC_INVALID_INPUT or FLASHC_FAILURE + */ +extern int flashc_set_wait_state(U16 ws); + +/*! \brief Page write number n. Assuming page bubuffer is already loaded. + * \param n Page number + */ +extern void flashc_page_write_n(U16 n); + +/*! \brief Page write + * Assuming the page address is already loaded + */ +extern void flashc_page_write(U16 page_n); + +/*! \brief Clear page buffer + */ +extern void flashc_clear_page_buffer(void); + +/*! \brief Page erase + * Assuming the page address is already loaded + */ +extern void flashc_erase_page(U16 page_n); + +/*! \brief Erase all Pages + */ +extern void flashc_erase_all(void); + +/*! \brief Erase a page and check if erase is OK + */ +extern int flashc_erase_page_and_check(U16 page_n); + +/*! \brief Page load and write + * \warning Dest is a FLASH address at a page boundary + * (assuming the page is already erased) + */ +extern void flashc_page_copy_write(U32 *Dest, const U32 *Src) ; + +/*! \brief This function allows to write up to 65535 bytes in the flash memory. + * This function manages alignement issue (byte and page alignements). + * + * \param *src Address of data to write. + * \param dst Start address in flash memory where write data + * \param n Number of word to write + * \return FLASHC_SUCCESS or FLASHC_FAILURE + */ +extern int flash_wr_block(U32 * src, U32 dst, U32 n); + + +#endif /* #ifndef _FLASHC_H_*/ diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.c b/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.c new file mode 100644 index 000000000..bbaf979f2 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.c @@ -0,0 +1,216 @@ +/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO driver for AVR32 UC3. + * + * This file defines a useful set of functions for the GPIO. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a PWM module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "gpio.h" + + +//! GPIO module instance. +#define GPIO AVR32_GPIO + + +int gpio_enable_module(avr32_gpiomap_t gpiomap, int size) +{ + int i,status=GPIO_SUCCESS; + + for(i=0; ipmr0c = (1<<(pin%32)); + gpio_port->pmr1c = (1<<(pin%32)); + break; + case 1: // B function + gpio_port->pmr0s = (1<<(pin%32)); + gpio_port->pmr1c = (1<<(pin%32)); + break; + case 2: // C function + gpio_port->pmr0c = (1<<(pin%32)); + gpio_port->pmr1s = (1<<(pin%32)); + break; + default: + return GPIO_INVALID_ARGUMENT; + } + + // Disable gpio control + gpio_port->gperc = (1<<(pin%32)); + + return GPIO_SUCCESS; +} + + +void gpio_enable_gpio(avr32_gpiomap_t gpiomap, int size) +{ + int i; + + for(i=0; igpers = 1<<(pin%32); +} + + +void gpio_enable_gpio_glitch_filter(int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; + gpio_port->gfers = 1<<(pin%32); +} + + +void gpio_disable_gpio_glitch_filter(int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; + gpio_port->gferc = 1<<(pin%32); +} + + +void gpio_disable_module(avr32_gpiomap_t gpiomap, int size) +{ + int i; + + for(i=0; igperc = 1<<(pin%32); +} + + +int gpio_pin_value(int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; + return (gpio_port->pvr >>(pin%32))&1; +} + + +void gpio_set_gpio_pin(int pin) +{ + // The port holding that pin. + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; + + gpio_port->ovrs = (1<<(pin%32)); // Value to be driven on the I/O line: 1 + gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin. +} + + +void gpio_clr_gpio_pin(int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin. + + gpio_port->ovrc = (1<<(pin%32)); // Value to be driven on the I/O line: 0 + gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin. +} + + +void gpio_tgl_gpio_pin(int pin) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin. + + gpio_port->ovrt = (1<<(pin%32)); // Toggle the I/O line. + gpio_port->oders = (1<<(pin%32)); // The GPIO output driver is enabled for that pin. + gpio_port->gpers = (1<<(pin%32)); // The GPIO module controls that pin. +} + + +void gpio_cfg_int_gpio_pin(int pin, int level) +{ + volatile avr32_gpio_port_t *gpio_port = &GPIO.port[pin/32]; // The port holding that pin. + + gpio_port->gpers = 1<<(pin%32); // GPIO controller enable + gpio_port->gfers = 1<<(pin%32); // GPIO glitch filter enable + switch (level) + { + case GPIO_RISING_EDGE: + { + // mode rising edge + gpio_port->imr0s = 1<<(pin%32); + gpio_port->imr1c = 1<<(pin%32); + break; + } + case GPIO_FALLING_EDGE: + { + // mode falling edge + gpio_port->imr0c = 1<<(pin%32); + gpio_port->imr1s = 1<<(pin%32); + break; + } + default : + { + // mode pin change + gpio_port->imr0c = 1<<(pin%32); + gpio_port->imr1c = 1<<(pin%32); + break; + } + } + gpio_port->iers = 1<<(pin%32); // GPIO interrupt enable +} diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.h b/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.h new file mode 100644 index 000000000..0faf006d1 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/GPIO/gpio.h @@ -0,0 +1,195 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief GPIO header for AVR32 UC3. + * + * This file contains basic GPIO driver functions. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a GPIO module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _GPIO_H_ +#define _GPIO_H_ + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +#else +# error Unknown compiler +#endif + + +/*! \name General GPIO API defines + * These values are returned by the GPIO API: + */ +//! @{ +#define GPIO_SUCCESS 0 //!< Function successfully completed +#define GPIO_FAILURE -1 //!< Function did not successfully complete for some unspecified reason +#define GPIO_INVALID_ARGUMENT 1 //!< Input paramters are out of range +//! @} + + +/*! \name Interrupt configuration defines + * Configure the method used to trigger the interrupt: + */ +//! @{ +#define GPIO_RISING_EDGE 1 //!< configure IT upon Rising Edge +#define GPIO_FALLING_EDGE 2 //!< configure IT upon Falling Edge +#define GPIO_INPUT_CHANGE 3 //!< configure IT upon Pin Change +//! @} + + +/*! + * A type definitions of pins and module connectivity. + * First column is the pin number, the second is gpio connectivity. + */ +typedef char avr32_gpiomap_t[][2]; + + +/*! + * \brief Enable a module pin for a given set of pins and respective modules. + * + * \param gpiomap A list of pins and pio connectivity + * \param size The number of pins in \a gpiomap + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT + */ +extern int gpio_enable_module(avr32_gpiomap_t gpiomap, int size); + +/*! + * \brief Enable a special module (function) for a pin (pin number). + * + * \param pin The pin number + * \param function The pin function + * \return \ref GPIO_SUCCESS or \ref GPIO_INVALID_ARGUMENT + */ +extern int gpio_enable_module_pin(int pin, int function); + +/*! + * \brief Enable pins of a module according gpiomap. + * + * \param gpiomap The pin map + * \param size The number of pins in \a gpiomap + */ +extern void gpio_enable_gpio(avr32_gpiomap_t gpiomap, int size); + +/*! + * \brief Enable the GPIO module to control the pin. + * + * \param pin The pin number + */ +extern void gpio_enable_gpio_pin(int pin); + +/*! + * \brief Enable the GPIO glitch filter. + * + * When the glitch filter is enabled, a + * glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with duration + * of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock + * cycles, the pulse may or may not be taken into account, depending on the precise timing of its + * occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for + * a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces + * 2 clock cycles latency. + * + * \param pin The pin number + * \return \ref GPIO_SUCCESS + */ +extern void gpio_enable_gpio_glitch_filter(int pin); + +/*! + * \brief Disable the GPIO glitch filter. + * + * \param pin The pin number + */ +extern void gpio_disable_gpio_glitch_filter(int pin); + +/*! + * \brief Return the pin value + * + * \param pin The pin number + * \return pin value + */ +extern int gpio_pin_value(int pin); + +/*! + * \brief Disable the GPIO module to control a set of pins according to gpiomap. + * + * \param gpiomap The pin map + * \param size The number of pins in \a gpiomap + */ +extern void gpio_disable_module(avr32_gpiomap_t gpiomap, int size); + +/*! + * \brief Disable the GPIO module to control the pin. + * + * \param pin The pin number + */ +extern void gpio_disable_gpio_pin(int pin); + +/*! + * \brief Configure a pin to generate IT + * + * \param pin GPIO pin number to configure. + * \param level level to configure (\ref GPIO_RISING_EDGE, \ref GPIO_FALLING_EDGE, \ref GPIO_INPUT_CHANGE). + */ +extern void gpio_cfg_int_gpio_pin(int pin, int level); + +/*! + * \brief Drive a gpio pin value to 1. + * + * \param pin The pin number + */ +extern void gpio_set_gpio_pin(int pin); + +/*! + * \brief Drive a gpio pin value to 0. + * + * \param pin The pin number + */ +extern void gpio_clr_gpio_pin(int pin); + +/*! + * \brief This function toggle a gpio pin value. + * + * \param pin The pin number + */ +extern void gpio_tgl_gpio_pin(int pin); + + +#endif // _GPIO_H_ diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.c b/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.c new file mode 100644 index 000000000..71f9c706c --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.c @@ -0,0 +1,201 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +#else +# error Unknown compiler +#endif + +#include "compiler.h" +#include "preprocessor.h" +#include "intc.h" + + +//! Values to store in the interrupt priority registers for the various interrupt priority levels. +extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS]; + +//! Creates a table of interrupt line handlers per interrupt group in order to optimize RAM space. +//! Each line handler table contains a set of pointers to interrupt handlers. +#define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \ +static volatile __int_handler _int_line_handler_table_##GRP[AVR32_INTC_NUM_IRQS_PER_GRP##GRP]; +MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~); +#undef DECL_INT_LINE_HANDLER_TABLE + +//! Table containing for each interrupt group the number of interrupt request +//! lines and a pointer to the table of interrupt line handlers. +static const struct +{ + unsigned int num_irqs; + volatile __int_handler *_int_line_handler_table; +} _int_handler_table[AVR32_INTC_NUM_INT_GRPS] = +{ +#define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \ + {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP}, + MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~) +#undef INSERT_INT_LINE_HANDLER_TABLE +}; + + +/*! \brief Default interrupt handler. + * + * \note Taken and adapted from Newlib. + */ +#if __GNUC__ +__attribute__((__interrupt__)) +#elif __ICCAVR32__ +__interrupt +#endif +static void _unhandled_interrupt(void) +{ + // Catch unregistered interrupts. + while (TRUE); +} + + +/*! \brief Gets the interrupt handler of the current event at the \a int_lev + * interrupt priority level (called from exception.S). + * + * \param int_lev Interrupt priority level to handle. + * + * \return Interrupt handler to execute. + * + * \note Taken and adapted from Newlib. + */ +__int_handler _get_interrupt_handler(unsigned int int_lev) +{ + // ICR3 is mapped first, ICR0 last. + // Code in exception.S puts int_lev in R12 which is used by AVR32-GCC to pass + // a single argument to a function. + unsigned int int_grp = (&AVR32_INTC.icr3)[INT3 - int_lev]; + unsigned int int_req = AVR32_INTC.irr[int_grp]; + + // As an interrupt may disappear while it is being fetched by the CPU + // (spurious interrupt caused by a delayed response from an MCU peripheral to + // an interrupt flag clear or interrupt disable instruction), check if there + // are remaining interrupt lines to process. + // If a spurious interrupt occurs, the status register (SR) contains an + // execution mode and interrupt level masks corresponding to a level 0 + // interrupt, whatever the interrupt priority level causing the spurious + // event. This behavior has been chosen because a spurious interrupt has not + // to be a priority one and because it may not cause any trouble to other + // interrupts. + // However, these spurious interrupts place the hardware in an unstable state + // and could give problems in other/future versions of the CPU, so the + // software has to be written so that they never occur. The only safe way of + // achieving this is to always clear or disable peripheral interrupts with the + // following sequence: + // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR. + // 2: Perform the bus access to the peripheral register that clears or + // disables the interrupt. + // 3: Wait until the interrupt has actually been cleared or disabled by the + // peripheral. This is usually performed by reading from a register in the + // same peripheral (it DOES NOT have to be the same register that was + // accessed in step 2, but it MUST be in the same peripheral), what takes + // bus system latencies into account, but peripheral internal latencies + // (generally 0 cycle) also have to be considered. + // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR. + // Note that steps 1 and 4 are useless inside interrupt handlers as the + // corresponding interrupt level is automatically masked by IxM (unless IxM is + // explicitly cleared by the software). + // + // Get the right IRQ handler. + // + // If several interrupt lines are active in the group, the interrupt line with + // the highest number is selected. This is to be coherent with the + // prioritization of interrupt groups performed by the hardware interrupt + // controller. + // + // If no handler has been registered for the pending interrupt, + // _unhandled_interrupt will be selected thanks to the initialization of + // _int_line_handler_table_x by INTC_init_interrupts. + // + // exception.S will provide the interrupt handler with a clean interrupt stack + // frame, with nothing more pushed onto the stack. The interrupt handler must + // manage the `rete' instruction, what can be done thanks to pure assembly, + // inline assembly or the `__attribute__((__interrupt__))' C function + // attribute. + return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL; +} + + +void INTC_init_interrupts(void) +{ + unsigned int int_grp, int_req; + + // For all interrupt groups, + for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++) + { + // For all interrupt request lines of each group, + for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++) + { + // Assign _unhandled_interrupt as default interrupt handler. + _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt; + } + + // Set the interrupt group priority register to its default value. + // By default, all interrupt groups are linked to the interrupt priority + // level 0 and to the interrupt vector _int0. + AVR32_INTC.ipr[int_grp] = ipr_val[INT0]; + } +} + + +void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev) +{ + unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP; + + // Store in _int_line_handler_table_x the pointer to the interrupt handler, so + // that _get_interrupt_handler can retrieve it when the interrupt is vectored. + _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler; + + // Program the corresponding IPRX register to set the interrupt priority level + // and the interrupt vector offset that will be fetched by the core interrupt + // system. + // NOTE: The _intx functions are intermediate assembly functions between the + // core interrupt system and the user interrupt handler. + AVR32_INTC.ipr[int_grp] = ipr_val[int_lev & (AVR32_INTC_IPR0_INTLEV_MASK >> AVR32_INTC_IPR0_INTLEV_OFFSET)]; +} diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.h b/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.h new file mode 100644 index 000000000..0772d9068 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/INTC/intc.h @@ -0,0 +1,104 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief INTC driver for AVR32 UC3. + * + * AVR32 Interrupt Controller driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with an INTC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _INTC_H_ +#define _INTC_H_ + +#include "compiler.h" + + +//! Maximal number of interrupt request lines per group. +#define AVR32_INTC_MAX_NUM_IRQS_PER_GRP 32 + +//! Number of interrupt priority levels. +#define AVR32_INTC_NUM_INT_LEVELS (1 << AVR32_INTC_IPR0_INTLEV_SIZE) + +/*! \name Interrupt Priority Levels + */ +//! @{ +#define INT0 0 //!< Lowest interrupt priority level. +#define INT1 1 +#define INT2 2 +#define INT3 3 //!< Highest interrupt priority level. +//! @} + + +#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling. + +//! Pointer to interrupt handler. +#if __GNUC__ +typedef void (*__int_handler)(void); +#elif __ICCAVR32__ +typedef void (__interrupt *__int_handler)(void); +#endif + + +/*! \brief Initializes the hardware interrupt controller driver. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_init_interrupts(void); + +/*! \brief Registers an interrupt handler. + * + * \param handler Interrupt handler to register. + * \param irq IRQ of the interrupt handler to register. + * \param int_lev Interrupt priority level to assign to the group of this IRQ. + * + * \warning The interrupt handler must manage the `rete' instruction, what can + * be done thanks to pure assembly, inline assembly or the + * `__attribute__((__interrupt__))' C function attribute. + * + * \warning If several interrupt handlers of a same group are registered with + * different priority levels, only the latest priority level set will + * be effective. + * + * \note Taken and adapted from Newlib. + */ +extern void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_lev); + +#endif // __AVR32_ABI_COMPILER__ + + +#endif // _INTC_H_ diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.c b/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.c new file mode 100644 index 000000000..671c3e22c --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.c @@ -0,0 +1,608 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#include "pm.h" + + +void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm) +{ + union { + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; + } oscctrl0 ; + // Read + oscctrl0.oscctrl0 = pm->oscctrl0; + // Modify + oscctrl0.OSCCTRL0.mode = AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK; + // Write + pm->oscctrl0 = oscctrl0.oscctrl0; +} + + +void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0) +{ + union { + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; + } oscctrl0 ; + // Read + oscctrl0.oscctrl0 = pm->oscctrl0; + // Modify + oscctrl0.OSCCTRL0.mode = (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3; + // Write + pm->oscctrl0 = oscctrl0.oscctrl0; +} + + +void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + union { + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; + } oscctrl0 ; + + // Read register + mcctrl.mcctrl = pm->mcctrl; + oscctrl0.oscctrl0 = pm->oscctrl0; + // Modify + mcctrl.MCCTRL.osc0en = 1; + oscctrl0.OSCCTRL0.startup = startup; + // Write back + pm->oscctrl0 = oscctrl0.oscctrl0; + pm->mcctrl = mcctrl.mcctrl; + + while(!pm->ISR.osc0rdy); //For osc output valid +} + + +void pm_disable_clk0(volatile avr32_pm_t *pm) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + + // Read register + mcctrl.mcctrl = pm->mcctrl; + + // Modify + mcctrl.MCCTRL.osc0en = 0; + + // Write back + pm->mcctrl = mcctrl.mcctrl; +} + + +void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + union { + unsigned long oscctrl0; + avr32_pm_oscctrl0_t OSCCTRL0; + } oscctrl0 ; + + // Read register + mcctrl.mcctrl = pm->mcctrl; + oscctrl0.oscctrl0 = pm->oscctrl0; + // Modify + mcctrl.MCCTRL.osc0en = 1; + oscctrl0.OSCCTRL0.startup=startup; + // Write back + pm->mcctrl = mcctrl.mcctrl; + pm->oscctrl0 = oscctrl0.oscctrl0; +} + + +void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm) +{ + while(!pm->ISR.osc0rdy); +} + + +void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm) +{ + union { + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; + } oscctrl1 ; + // Read + oscctrl1.oscctrl1= pm->oscctrl1; + // Modify + oscctrl1.OSCCTRL1.mode = AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK; + // Write + pm->oscctrl1 = oscctrl1.oscctrl1; +} + + +void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1) +{ + union { + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; + } oscctrl1 ; + // Read + oscctrl1.oscctrl1= pm->oscctrl1; + // Modify + oscctrl1.OSCCTRL1.mode = (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 : + AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3; + // Write + pm->oscctrl1 = oscctrl1.oscctrl1; +} + + +void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + union { + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; + } oscctrl1 ; + + // Read register + mcctrl.mcctrl = pm->mcctrl; + oscctrl1.oscctrl1 = pm->oscctrl1; + + mcctrl.MCCTRL.osc1en = 1; + oscctrl1.OSCCTRL1.startup=startup; + // Write back + pm->oscctrl1 = oscctrl1.oscctrl1; + pm->mcctrl = mcctrl.mcctrl; + + while(!pm->ISR.osc1rdy); +} + + +void pm_disable_clk1(volatile avr32_pm_t *pm) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + + + // Read register + mcctrl.mcctrl = pm->mcctrl; + + // Modify + mcctrl.MCCTRL.osc1en = 0; + + // Write back + pm->mcctrl = mcctrl.mcctrl; +} + + +void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + union { + unsigned long oscctrl1; + avr32_pm_oscctrl1_t OSCCTRL1; + } oscctrl1 ; + + // Read register + mcctrl.mcctrl = pm->mcctrl; + oscctrl1.oscctrl1 = pm->oscctrl1; + + mcctrl.MCCTRL.osc1en = 1; + oscctrl1.OSCCTRL1.startup=startup; + // Write back + pm->oscctrl1 = oscctrl1.oscctrl1; + pm->mcctrl = mcctrl.mcctrl; +} + + +void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm) +{ + while(!pm->ISR.osc1rdy); +} + + +void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm) +{ + union { + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; + } u_ctrl; + u_ctrl.oscctrl32 = pm->oscctrl32; + u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK; + pm->oscctrl32 = u_ctrl.oscctrl32; +} + + +void pm_enable_osc32_crystal(volatile avr32_pm_t *pm) +{ + union { + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; + } u_ctrl; + u_ctrl.oscctrl32 = pm->oscctrl32; + u_ctrl.OSCCTRL32.mode = AVR32_PM_OSCCTRL32_MODE_CRYSTAL; + pm->oscctrl32 = u_ctrl.oscctrl32; +} + + +void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup) +{ + union { + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; + } oscctrl32 ; + + // Read register + oscctrl32.oscctrl32 = pm->oscctrl32; + // Modify + oscctrl32.OSCCTRL32.osc32en = 1; + oscctrl32.OSCCTRL32.startup=startup; + // Write back + pm->oscctrl32 = oscctrl32.oscctrl32; + + while(!pm->ISR.osc32rdy); +} + + +void pm_disable_clk32(volatile avr32_pm_t *pm) +{ + // To get rid of a GCC bug + // This makes C code longer, but not ASM + union { + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; + } oscctrl32 ; + + // Read register + oscctrl32.oscctrl32 = pm->oscctrl32; + // Modify + oscctrl32.OSCCTRL32.osc32en = 0; + // Write back + pm->oscctrl32 = oscctrl32.oscctrl32; +} + + +void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup) +{ + union { + unsigned long oscctrl32; + avr32_pm_oscctrl32_t OSCCTRL32; + } oscctrl32 ; + + // Read register + oscctrl32.oscctrl32 = pm->oscctrl32; + // Modify + oscctrl32.OSCCTRL32.osc32en = 1; + oscctrl32.OSCCTRL32.startup=startup; + // Write back + pm->oscctrl32 = oscctrl32.oscctrl32; +} + + +void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm) +{ + // To get rid of a GCC bug + // This makes C code longer, but not ASM + + while(!pm->ISR.osc32rdy); +} + + +void pm_cksel(volatile avr32_pm_t *pm, + unsigned int pbadiv, + unsigned int pbasel, + unsigned int pbbdiv, + unsigned int pbbsel, + unsigned int hsbdiv, + unsigned int hsbsel) +{ + // Force the compiler to generate only one 32 bits access + union { + avr32_pm_cksel_t selval ; + unsigned long uword32; + } cksel; + + cksel.uword32 = 0; + + cksel.selval.cpudiv = hsbdiv; + cksel.selval.cpusel = hsbsel; + cksel.selval.hsbdiv = hsbdiv; + cksel.selval.hsbsel = hsbsel; + cksel.selval.pbbdiv = pbbdiv; + cksel.selval.pbbsel = pbbsel; + cksel.selval.pbadiv = pbadiv; + cksel.selval.pbasel = pbasel; + + pm->cksel = cksel.uword32; + + // Wait for ckrdy bit and then clear it + while(!(pm->ISR.ckrdy)); + + return; +} + + +void pm_gc_setup(volatile avr32_pm_t *pm, + unsigned int gc, + unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1) + unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1 + unsigned int diven, + unsigned int div) { + union { + unsigned long gcctrl; + avr32_pm_gcctrl_t GCCTRL; + } u_gc; + + u_gc.GCCTRL.oscsel = pll_osc; + u_gc.GCCTRL.pllsel = osc_or_pll; + u_gc.GCCTRL.diven = diven; + u_gc.GCCTRL.div = div; + u_gc.GCCTRL.cen = 0; // Disable GC first + pm->gcctrl[gc] = u_gc.gcctrl; +} + + +void pm_gc_enable(volatile avr32_pm_t *pm, + unsigned int gc) { + union { + unsigned long gcctrl; + avr32_pm_gcctrl_t GCCTRL; + } u_gc; + u_gc.gcctrl = pm->gcctrl[gc]; + u_gc.GCCTRL.cen = 1; + pm->gcctrl[gc] = u_gc.gcctrl; +} + + +void pm_gc_disable(volatile avr32_pm_t *pm, + unsigned int gc) { + union { + unsigned long gcctrl; + avr32_pm_gcctrl_t GCCTRL; + } u_gc; + u_gc.gcctrl = pm->gcctrl[gc]; + u_gc.GCCTRL.cen = 0; + pm->gcctrl[gc] = u_gc.gcctrl; +} + + +void pm_pll_setup(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int mul, + unsigned int div, + unsigned int osc, + unsigned int lockcount) { + + union { + unsigned long pll ; + avr32_pm_pll_t PLL ; + } u_pll; + + u_pll.pll=0; + + u_pll.PLL.pllmul = mul; + u_pll.PLL.plldiv = div; + u_pll.PLL.pllosc = osc; + u_pll.PLL.pllcount = lockcount; + + u_pll.PLL.pllopt = 0; + + u_pll.PLL.plltest = 0; + + (pm->pll)[pll] = u_pll.pll; +} + + +void pm_pll_set_option(volatile avr32_pm_t *pm, + unsigned int pll, + unsigned int pll_freq, + unsigned int pll_div2, + unsigned int pll_wbwdisable) { + union { + unsigned long pll ; + avr32_pm_pll_t PLL ; + } u_pll; + + u_pll.pll = (pm->pll)[pll]; + u_pll.PLL.pllopt = pll_freq | (pll_div2<<1) | (pll_wbwdisable<<2); + (pm->pll)[pll] = u_pll.pll; +} + + +unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, + unsigned int pll) { + return (pm->PLL)[pll].pllopt; +} + + +void pm_pll_enable(volatile avr32_pm_t *pm, + unsigned int pll) { + union { + unsigned long pll ; + avr32_pm_pll_t PLL ; + } u_pll; + + u_pll.pll = (pm->pll)[pll]; + u_pll.PLL.pllen = 1; + (pm->pll)[pll] = u_pll.pll; +} + + +void pm_pll_disable(volatile avr32_pm_t *pm, + unsigned int pll) { + union { + unsigned long pll ; + avr32_pm_pll_t PLL ; + } u_pll; + + u_pll.pll = (pm->pll)[pll]; + u_pll.PLL.pllen = 0; + (pm->pll)[pll] = u_pll.pll; +} + + +void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm) +{ + while(!pm->ISR.lock0); + + // Bypass the lock signal of the PLL + pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK; +} + + +void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm) +{ + while(!pm->ISR.lock1); + + // Bypass the lock signal of the PLL + pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK; +} + + +void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock) +{ + union { + avr32_pm_mcctrl_t MCCTRL; + unsigned long mcctrl; + } mcctrl; + // Read + mcctrl.mcctrl = pm->mcctrl; + // Modify + mcctrl.MCCTRL.mcsel = clock; + // Write Back + pm->MCCTRL.mcsel = mcctrl.mcctrl; +} + + +void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup) +{ + pm_enable_osc0_crystal(pm, fosc0); // Enable the Osc0 in crystal mode + pm_enable_clk0(pm, startup); // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal + pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0); // Then switch main clock to Osc0 +} + + +void pm_bod_enable_irq(volatile struct avr32_pm_t *pm) { + + union { + unsigned long ier ; + avr32_pm_ier_t IER ; + } u_ier; + u_ier.ier = 0; + u_ier.IER.boddet = 1; + + pm->ier = u_ier.ier; +} + + +void pm_bod_disable_irq(volatile struct avr32_pm_t *pm) { + + union { + unsigned long idr ; + avr32_pm_idr_t IDR ; + } u_idr; + u_idr.idr = 0; + u_idr.IDR.boddet = 1; + + pm->idr = u_idr.idr; +} + + +void pm_bod_clear_irq(volatile struct avr32_pm_t *pm) { + + union { + unsigned long icr ; + avr32_pm_idr_t ICR ; + } u_icr; + u_icr.icr = 0; + u_icr.ICR.boddet = 1; + + pm->icr = u_icr.icr; +} + + +unsigned long pm_bod_get_irq_status(volatile struct avr32_pm_t *pm) { + + return pm->ISR.boddet; +} + + +unsigned long pm_bod_get_irq_enable_bit(volatile struct avr32_pm_t *pm) { + + return pm->IMR.boddet; +} + + +unsigned long pm_bod_get_level(volatile avr32_pm_t *pm) { + union { + unsigned long bod ; + avr32_pm_bod_t BOD ; + } u_bod; + + u_bod.bod = pm->bod; + + return (unsigned long) u_bod.BOD.level; + +} + + +void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value) { + (pm->gplp)[gplp] = value; + +} + + +unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp) { + + return (pm->gplp)[gplp]; +} diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.h b/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.h new file mode 100644 index 000000000..5a3e6898a --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/PM/pm.h @@ -0,0 +1,331 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Power Manager driver. + * + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _PM_H_ +#define _PM_H_ + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +# include +#else +# error Unknown compiler +#endif + +#include "compiler.h" +#include "preprocessor.h" + + +/*! \brief Sets the MCU in the specified sleep mode. + * + * \param mode Sleep mode: + * \arg \c AVR32_PM_SMODE_IDLE: Idle; + * \arg \c AVR32_PM_SMODE_FROZEN: Frozen; + * \arg \c AVR32_PM_SMODE_STANDBY: Standby; + * \arg \c AVR32_PM_SMODE_STOP: Stop; + * \arg \c AVR32_PM_SMODE_SHUTDOWN: Shutdown (DeepStop); + * \arg \c AVR32_PM_SMODE_STATIC: Static. + */ +#define SLEEP(mode) {__asm__ __volatile__ ("sleep "STRINGZ(mode));} + + +/*! + * \brief This function will enable the external clock mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + */ +extern void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0); + + +/*! + * \brief This function will enable the oscillator 0 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 0. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk0(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 0 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc0 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc1 Oscillator 1 crystal frequency (Hz) + */ +extern void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1); + + +/*! + * \brief This function will enable the oscillator 1 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 1. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk1(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 1 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 1 startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the Osc1 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the external clock mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the crystal mode of the 32-kHz oscillator. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_enable_osc32_crystal(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with a startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will disable the oscillator 32. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_disable_clk32(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will enable the oscillator 32 to be used with no startup time. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param startup Clock 32 kHz startup time. Time is expressed in term of RCOsc periods (3-bit value) but not checked. + */ +extern void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup); + + +/*! + * \brief This function will wait until the osc32 clock is ready. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm); + + +//FIXME update this header -SM +/*! + * \brief This function will select all the power manager clocks. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pbadiv Peripheral Bus A clock divisor enable + * \param pbasel Peripheral Bus A select + * \param pbbdiv Peripheral Bus B clock divisor enable + * \param pbbsel Peripheral Bus B select + * \param hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock) + * \param hsbsel High Speed Bus select (CPU clock = HSB clock ) + */ +extern void pm_cksel(volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel); + + +/*! + * \brief This function will setup a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + * \param osc_or_pll Use OSC (=0) or PLL (=1) + * \param pll_osc Select Osc0/PLL0 or Osc1/PLL1 + * \param diven Generic clock divisor enable + * \param div Generic clock divisor + */ +extern void pm_gc_setup(volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div); + + +/*! + * \brief This function will enable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_enable(volatile avr32_pm_t *pm, unsigned int gc); + + +/*! + * \brief This function will disable a generic clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param gc generic clock number (0 for gc0...) + */ +extern void pm_gc_disable(volatile avr32_pm_t *pm, unsigned int gc); + + +//FIXME update this header -SM +/*! + * \brief This function will setup a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param mul + * \param div + * \param osc + * \param lockcount + */ +extern void pm_pll_setup(volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount); + + +//FIXME update this header -SM +/*! + * \brief This function will set a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \param pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. + * \param pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) + * \param pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. + */ +extern void pm_pll_set_option(volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable); + + +//FIXME update this header -SM +/*! + * \brief This function will get a PLL option. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + * \return Option + */ +extern unsigned int pm_pll_get_option(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will enable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_enable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will disable a PLL. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param pll PLL number(0 for PLL0, 1 for PLL1) + */ +extern void pm_pll_disable(volatile avr32_pm_t *pm, unsigned int pll); + + +/*! + * \brief This function will wait for PLL0 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will wait for PLL1 locked + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + */ +extern void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm); + + +/*! + * \brief This function will switch the power manager main clock. + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0. + */ +extern void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock); + + +/*! + * \brief Switch main clock to clock Osc0 (crystal mode) + * \param pm Base address of the Power Manager (i.e. &AVR32_PM) + * \param fosc0 Oscillator 0 crystal frequency (Hz) + * \param startup Crystal 0 startup time. Time is expressed in term of RCOsc periods (3-bit value) + */ +extern void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup); + + +#endif // _PM_H_ diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.c b/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.c new file mode 100644 index 000000000..20dfe4ee5 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.c @@ -0,0 +1,299 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief TC driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +#else +# error Unknown compiler +#endif + +#include "compiler.h" +#include "tc.h" + + +int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].imr; +} + + +int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable the appropriate interrupts. + tc->channel[channel].ier = bitfield->etrgs << AVR32_TC_ETRGS_OFFSET | + bitfield->ldrbs << AVR32_TC_LDRBS_OFFSET | + bitfield->ldras << AVR32_TC_LDRAS_OFFSET | + bitfield->cpcs << AVR32_TC_CPCS_OFFSET | + bitfield->cpbs << AVR32_TC_CPBS_OFFSET | + bitfield->cpas << AVR32_TC_CPAS_OFFSET | + bitfield->lovrs << AVR32_TC_LOVRS_OFFSET | + bitfield->covfs << AVR32_TC_COVFS_OFFSET; + + // Disable the appropriate interrupts. + tc->channel[channel].idr = (~bitfield->etrgs & 1) << AVR32_TC_ETRGS_OFFSET | + (~bitfield->ldrbs & 1) << AVR32_TC_LDRBS_OFFSET | + (~bitfield->ldras & 1) << AVR32_TC_LDRAS_OFFSET | + (~bitfield->cpcs & 1) << AVR32_TC_CPCS_OFFSET | + (~bitfield->cpbs & 1) << AVR32_TC_CPBS_OFFSET | + (~bitfield->cpas & 1) << AVR32_TC_CPAS_OFFSET | + (~bitfield->lovrs & 1) << AVR32_TC_LOVRS_OFFSET | + (~bitfield->covfs & 1) << AVR32_TC_COVFS_OFFSET; + + return 0; +} + + +int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS || ext_clk_sig_src >= 1 << AVR32_TC_BMR_TC0XC0S_SIZE) + return TC_INVALID_ARGUMENT; + + // Clear bit-field and set the correct behavior. + tc->bmr = (tc->bmr & ~(AVR32_TC_BMR_TC0XC0S_MASK << (channel * AVR32_TC_BMR_TC0XC0S_SIZE))) | + (ext_clk_sig_src << (channel * AVR32_TC_BMR_TC0XC0S_SIZE)); + + return 0; +} + + +int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // MEASURE SIGNALS: Capture operating mode. + tc->channel[opt->channel].cmr = opt->ldrb << AVR32_TC_LDRB_OFFSET | + opt->ldra << AVR32_TC_LDRA_OFFSET | + 0 << AVR32_TC_WAVE_OFFSET | + opt->cpctrg << AVR32_TC_CPCTRG_OFFSET | + opt->abetrg << AVR32_TC_ABETRG_OFFSET | + opt->etrgedg << AVR32_TC_ETRGEDG_OFFSET| + opt->ldbdis << AVR32_TC_LDBDIS_OFFSET | + opt->ldbstop << AVR32_TC_LDBSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt) +{ + // Check for valid input. + if (opt->channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // GENERATE SIGNALS: Waveform operating mode. + tc->channel[opt->channel].cmr = opt->bswtrg << AVR32_TC_BSWTRG_OFFSET | + opt->beevt << AVR32_TC_BEEVT_OFFSET | + opt->bcpc << AVR32_TC_BCPC_OFFSET | + opt->bcpb << AVR32_TC_BCPB_OFFSET | + opt->aswtrg << AVR32_TC_ASWTRG_OFFSET | + opt->aeevt << AVR32_TC_AEEVT_OFFSET | + opt->acpc << AVR32_TC_ACPC_OFFSET | + opt->acpa << AVR32_TC_ACPA_OFFSET | + 1 << AVR32_TC_WAVE_OFFSET | + opt->wavsel << AVR32_TC_WAVSEL_OFFSET | + opt->enetrg << AVR32_TC_ENETRG_OFFSET | + opt->eevt << AVR32_TC_EEVT_OFFSET | + opt->eevtedg << AVR32_TC_EEVTEDG_OFFSET | + opt->cpcdis << AVR32_TC_CPCDIS_OFFSET | + opt->cpcstop << AVR32_TC_CPCSTOP_OFFSET | + opt->burst << AVR32_TC_BURST_OFFSET | + opt->clki << AVR32_TC_CLKI_OFFSET | + opt->tcclks << AVR32_TC_TCCLKS_OFFSET; + + return 0; +} + + +int tc_start(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Enable, reset and start the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK | AVR32_TC_CLKEN_MASK; + + return 0; +} + + +int tc_stop(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Disable the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_CLKDIS_MASK; + + return 0; +} + + +int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // Reset the selected timer/counter channel. + tc->channel[channel].ccr = AVR32_TC_SWTRG_MASK; + + return 0; +} + + +void tc_sync_trigger(volatile avr32_tc_t *tc) +{ + // Reset all channels of the selected timer/counter. + tc->bcr = AVR32_TC_BCR_SYNC_MASK; +} + + +int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return tc->channel[channel].sr; +} + + +int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].cv, AVR32_TC_CV_MASK); +} + + +int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK); +} + + +int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK); +} + + +int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + return Rd_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK); +} + + +int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].ra, AVR32_TC_RA_MASK, value); + + return value; +} + + +int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rb, AVR32_TC_RB_MASK, value); + + return value; +} + + +int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value) +{ + // Check for valid input. + if (channel >= TC_NUMBER_OF_CHANNELS) + return TC_INVALID_ARGUMENT; + + // This function is only available in WAVEFORM mode. + if (Tst_bits(tc->channel[channel].cmr, AVR32_TC_WAVE_MASK)) + Wr_bitfield(tc->channel[channel].rc, AVR32_TC_RC_MASK, value); + + return value; +} diff --git a/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.h b/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.h new file mode 100644 index 000000000..f76586d70 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/DRIVERS/TC/tc.h @@ -0,0 +1,586 @@ +/*This file is prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Timer/Counter driver for AVR32 UC3. + * + * AVR32 Timer/Counter driver module. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices with a TC module can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + ******************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef _TC_H_ +#define _TC_H_ + +#if __GNUC__ +# include +#elif __ICCAVR32__ +# include +#else +# error Unknown compiler +#endif + + +//! TC driver functions return value in case of invalid argument(s). +#define TC_INVALID_ARGUMENT -1 + +//! Number of timer/counter channels. +#define TC_NUMBER_OF_CHANNELS (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t)) + +/*! \name External Clock Signal 0 Selection + */ +//! @{ +#define TC_CH0_EXT_CLK0_SRC_TCLK0 AVR32_TC_TC0XC0S_TCLK0 +#define TC_CH0_EXT_CLK0_SRC_NO_CLK AVR32_TC_TC0XC0S_NO_CLK +#define TC_CH0_EXT_CLK0_SRC_TIOA1 AVR32_TC_TC0XC0S_TIOA1 +#define TC_CH0_EXT_CLK0_SRC_TIOA2 AVR32_TC_TC0XC0S_TIOA2 +//! @} + +/*! \name External Clock Signal 1 Selection + */ +//! @{ +#define TC_CH1_EXT_CLK1_SRC_TCLK1 AVR32_TC_TC1XC1S_TCLK1 +#define TC_CH1_EXT_CLK1_SRC_NO_CLK AVR32_TC_TC1XC1S_NO_CLK +#define TC_CH1_EXT_CLK1_SRC_TIOA0 AVR32_TC_TC1XC1S_TIOA0 +#define TC_CH1_EXT_CLK1_SRC_TIOA2 AVR32_TC_TC1XC1S_TIOA2 +//! @} + +/*! \name External Clock Signal 2 Selection + */ +//! @{ +#define TC_CH2_EXT_CLK2_SRC_TCLK2 AVR32_TC_TC2XC2S_TCLK2 +#define TC_CH2_EXT_CLK2_SRC_NO_CLK AVR32_TC_TC2XC2S_NO_CLK +#define TC_CH2_EXT_CLK2_SRC_TIOA0 AVR32_TC_TC2XC2S_TIOA0 +#define TC_CH2_EXT_CLK2_SRC_TIOA1 AVR32_TC_TC2XC2S_TIOA1 +//! @} + +/*! \name Event/Trigger Actions on Output + */ +//! @{ +#define TC_EVT_EFFECT_NOOP AVR32_TC_NONE +#define TC_EVT_EFFECT_SET AVR32_TC_SET +#define TC_EVT_EFFECT_CLEAR AVR32_TC_CLEAR +#define TC_EVT_EFFECT_TOGGLE AVR32_TC_TOGGLE +//! @} + +/*! \name RC Compare Trigger Enable + */ +//! @{ +#define TC_NO_TRIGGER_COMPARE_RC 0 +#define TC_TRIGGER_COMPARE_RC 1 +//! @} + +/*! \name Waveform Selection + */ +//! @{ +#define TC_WAVEFORM_SEL_UP_MODE AVR32_TC_WAVSEL_UP_NO_AUTO +#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UP_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE AVR32_TC_WAVSEL_UPDOWN_NO_AUTO +#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER AVR32_TC_WAVSEL_UPDOWN_AUTO +//! @} + +/*! \name TIOA or TIOB External Trigger Selection + */ +//! @{ +#define TC_EXT_TRIG_SEL_TIOA 1 +#define TC_EXT_TRIG_SEL_TIOB 0 +//! @} + +/*! \name External Event Selection + */ +//! @{ +#define TC_EXT_EVENT_SEL_TIOB_INPUT AVR32_TC_EEVT_TIOB_INPUT +#define TC_EXT_EVENT_SEL_XC0_OUTPUT AVR32_TC_EEVT_XC0_OUTPUT +#define TC_EXT_EVENT_SEL_XC1_OUTPUT AVR32_TC_EEVT_XC1_OUTPUT +#define TC_EXT_EVENT_SEL_XC2_OUTPUT AVR32_TC_EEVT_XC2_OUTPUT +//! @} + +/*! \name Edge Selection + */ +//! @{ +#define TC_SEL_NO_EDGE AVR32_TC_EEVTEDG_NO_EDGE +#define TC_SEL_RISING_EDGE AVR32_TC_EEVTEDG_POS_EDGE +#define TC_SEL_FALLING_EDGE AVR32_TC_EEVTEDG_NEG_EDGE +#define TC_SEL_EACH_EDGE AVR32_TC_EEVTEDG_BOTH_EDGES +//! @} + +/*! \name Burst Signal Selection + */ +//! @{ +#define TC_BURST_NOT_GATED AVR32_TC_BURST_NOT_GATED +#define TC_BURST_CLK_AND_XC0 AVR32_TC_BURST_CLK_AND_XC0 +#define TC_BURST_CLK_AND_XC1 AVR32_TC_BURST_CLK_AND_XC1 +#define TC_BURST_CLK_AND_XC2 AVR32_TC_BURST_CLK_AND_XC2 +//! @} + +/*! \name Clock Invert + */ +//! @{ +#define TC_CLOCK_RISING_EDGE 0 +#define TC_CLOCK_FALLING_EDGE 1 +//! @} + +/*! \name Clock Selection + */ +//! @{ +#define TC_CLOCK_SOURCE_TC1 AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK +#define TC_CLOCK_SOURCE_TC2 AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK +#define TC_CLOCK_SOURCE_TC3 AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK +#define TC_CLOCK_SOURCE_TC4 AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK +#define TC_CLOCK_SOURCE_TC5 AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK +#define TC_CLOCK_SOURCE_XC0 AVR32_TC_TCCLKS_XC0 +#define TC_CLOCK_SOURCE_XC1 AVR32_TC_TCCLKS_XC1 +#define TC_CLOCK_SOURCE_XC2 AVR32_TC_TCCLKS_XC2 +//! @} + + +//! Timer/counter interrupts. +typedef struct +{ + unsigned int :24; + + //! External trigger interrupt. + unsigned int etrgs : 1; + + //! RB load interrupt. + unsigned int ldrbs : 1; + + //! RA load interrupt. + unsigned int ldras : 1; + + //! RC compare interrupt. + unsigned int cpcs : 1; + + //! RB compare interrupt. + unsigned int cpbs : 1; + + //! RA compare interrupt. + unsigned int cpas : 1; + + //! Load overrun interrupt. + unsigned int lovrs : 1; + + //! Counter overflow interrupt. + unsigned int covfs : 1; +} tc_interrupt_t; + +//! Parameters when initializing a timer/counter in capture mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + unsigned int :12; + + //! RB loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldrb : 2; + + //! RA loading selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int ldra : 2; + + unsigned int : 1; + + //! RC compare trigger enable:\n + //! - \ref TC_NO_TRIGGER_COMPARE_RC;\n + //! - \ref TC_TRIGGER_COMPARE_RC. + unsigned int cpctrg : 1; + + unsigned int : 3; + + //! TIOA or TIOB external trigger selection:\n + //! - \ref TC_EXT_TRIG_SEL_TIOA;\n + //! - \ref TC_EXT_TRIG_SEL_TIOB. + unsigned int abetrg : 1; + + //! External trigger edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int etrgedg : 2; + + //! Counter clock disable with RB loading:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int ldbdis : 1; + + //! Counter clock stopped with RB loading:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int ldbstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_capture_opt_t; + +//! Parameters when initializing a timer/counter in waveform mode. +typedef struct +{ + //! Channel to initialize. + unsigned int channel ; + + //! Software trigger effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bswtrg : 2; + + //! External event effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int beevt : 2; + + //! RC compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpc : 2; + + //! RB compare effect on TIOB:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int bcpb : 2; + + //! Software trigger effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aswtrg : 2; + + //! External event effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int aeevt : 2; + + //! RC compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpc : 2; + + //! RA compare effect on TIOA:\n + //! - \ref TC_EVT_EFFECT_NOOP;\n + //! - \ref TC_EVT_EFFECT_SET;\n + //! - \ref TC_EVT_EFFECT_CLEAR;\n + //! - \ref TC_EVT_EFFECT_TOGGLE. + unsigned int acpa : 2; + + unsigned int : 1; + + //! Waveform selection:\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n + //! - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER. + unsigned int wavsel : 2; + + //! External event trigger enable:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int enetrg : 1; + + //! External event selection:\n + //! - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n + //! - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT. + unsigned int eevt : 2; + + //! External event edge selection:\n + //! - \ref TC_SEL_NO_EDGE;\n + //! - \ref TC_SEL_RISING_EDGE;\n + //! - \ref TC_SEL_FALLING_EDGE;\n + //! - \ref TC_SEL_EACH_EDGE. + unsigned int eevtedg : 2; + + //! Counter clock disable with RC compare:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int cpcdis : 1; + + //! Counter clock stopped with RC compare:\n + //! - \c FALSE;\n + //! - \c TRUE. + unsigned int cpcstop : 1; + + //! Burst signal selection:\n + //! - \ref TC_BURST_NOT_GATED;\n + //! - \ref TC_BURST_CLK_AND_XC0;\n + //! - \ref TC_BURST_CLK_AND_XC1;\n + //! - \ref TC_BURST_CLK_AND_XC2. + unsigned int burst : 2; + + //! Clock invert:\n + //! - \ref TC_CLOCK_RISING_EDGE;\n + //! - \ref TC_CLOCK_FALLING_EDGE. + unsigned int clki : 1; + + //! Clock selection:\n + //! - \ref TC_CLOCK_SOURCE_TC1;\n + //! - \ref TC_CLOCK_SOURCE_TC2;\n + //! - \ref TC_CLOCK_SOURCE_TC3;\n + //! - \ref TC_CLOCK_SOURCE_TC4;\n + //! - \ref TC_CLOCK_SOURCE_TC5;\n + //! - \ref TC_CLOCK_SOURCE_XC0;\n + //! - \ref TC_CLOCK_SOURCE_XC1;\n + //! - \ref TC_CLOCK_SOURCE_XC2. + unsigned int tcclks : 3; +} tc_waveform_opt_t; + + +/*! \brief Reads timer/counter interrupt settings. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Enables various timer/counter interrupts. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param bitfield The interrupt enable configuration. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield); + +/*! \brief Selects which external clock to use and how to configure it. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param ext_clk_sig_src External clock signal selection: + * \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0; + * \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1; + * \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2; + * \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1; + * \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0; + * \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2; + * \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2; + * \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0; + * \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src); + +/*! \brief Sets options for timer/counter capture initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for capture mode. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt); + +/*! \brief Sets options for timer/counter waveform initialization. + * + * \param tc Pointer to the TC instance to access. + * \param opt Options for waveform generation. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt); + +/*! \brief Starts a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Stops a timer/counter. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Performs a software trigger: the counter is reset and the clock is started. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval 0 Success. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels. + * + * \param tc Pointer to the TC instance to access. + */ +extern void tc_sync_trigger(volatile avr32_tc_t *tc); + +/*! \brief Reads the status register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 Status register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's TC counter and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 TC counter value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RA register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RA register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RB register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RB register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Reads the channel's RC register and returns the value. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * + * \retval >=0 RC register value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel); + +/*! \brief Writes a value to the channel's RA register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RA register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RB register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RB register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + +/*! \brief Writes a value to the channel's RC register. + * + * \param tc Pointer to the TC instance to access. + * \param channel The TC instance channel to access. + * \param value Value to write to the RC register. + * + * \retval >=0 Written value. + * \retval TC_INVALID_ARGUMENT Invalid argument(s). + */ +extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value); + + +#endif // _TC_H_ diff --git a/Demo/lwIP_AVR32_UC3/FreeRTOSConfig.h b/Demo/lwIP_AVR32_UC3/FreeRTOSConfig.h new file mode 100644 index 000000000..3d1d37f04 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/FreeRTOSConfig.h @@ -0,0 +1,95 @@ +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief FreeRTOS and lwIP example for AVR32 UC3. + * + * - Compiler: IAR EWAVR32 and GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "board.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + *----------------------------------------------------------*/ + +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configCPU_CLOCK_HZ ( 48000000 ) /* Hz clk gen */ +#define configPBA_CLOCK_HZ ( 24000000 ) +#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) +#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 8 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 256 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 0 ) ) +#define configMAX_TASK_NAME_LEN ( 20 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 0 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ + +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 0 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 + +/* configTICK_USE_TC is a boolean indicating whether to use a Timer Counter + for the tick generation. Timer Counter will generate an accurate Tick; + otherwise the CPU will generate a tick but with time drift + configTICK_TC_CHANNEL is the TC channel.*/ +#define configTICK_USE_TC 1 +#define configTICK_TC_CHANNEL 2 + +#endif /* FREERTOS_CONFIG_H */ diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.c b/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.c new file mode 100644 index 000000000..0442eccd8 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.c @@ -0,0 +1,252 @@ +/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic SMTP Host for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + Implements a simplistic SMTP client. +*/ + +#if (SMTP_USED == 1) + +#include + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "BasicSMTP.h" + + +/* Demo includes. */ +#include "AVR32_EMAC.h" +#include "portmacro.h" +#include "partest.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/arch.h" +#include "lwip/sys.h" +#include "lwip/sockets.h" +#include "netif/loopif.h" + +/*! SMTP default port */ +#define SMTP_PORT 25 +/*! SMTP EHLO code answer */ +#define SMTP_EHLO_STRING "220" +/*! SMTP end of transmission code answer */ +#define SMTP_END_OF_TRANSMISSION_STRING "221" +/*! SMTP OK code answer */ +#define SMTP_OK_STRING "250" +/*! SMTP start of transmission code answer */ +#define SMTP_START_OF_TRANSMISSION_STRING "354" +/*! SMTP DATA */ +#define SMTP_DATA_STRING "DATA\r\n" +/*! SMTP . */ +#define SMTP_MAIL_END_STRING "\r\n.\r\n" +/*! SMTP QUIT */ +#define SMTP_QUIT_STRING "QUIT\r\n\r\n" + + +/*! Server address */ +portCHAR cServer[] = "192.168.0.1"; + +/*! Fill here the ehlo with your SMTP server name */ +#error configure SMTP server +char ehlo[] = "EHLO smtp.domain.com\r\n"; + +/*! Fill here the mailfrom with your mail address */ +#error configure mail sender +char mailfrom[] = "MAIL FROM: \r\n"; + +/*! Fill here the mailto with your contact mail address */ +#error configure mail receiver +char mailto[] = "RCPT TO: \r\n"; + +/*! Fill here the mailcontent with the mail you want to send */ +#error configure mail content +char mailcontent[] ="Subject: *** SPAM ***\r\nFROM: \"Your Name here\" \r\nTO: \"Your Contact here\" \r\n\r\nSay what you want here."; + +Bool bSendMail = pdTRUE; +portCHAR cTempBuffer[200]; + +/*! Basic SMTP Host task definition */ +portTASK_FUNCTION( vBasicSMTPHost, pvParameters ) +{ + struct sockaddr_in stServeurSockAddr; + portLONG lRetval; + portLONG lSocket = -1; + + + for (;;) + { + // wait for a signal to send a mail + while (bSendMail != pdTRUE) vTaskDelay(200); + + // Set up port + memset(&stServeurSockAddr, 0, sizeof(stServeurSockAddr)); + stServeurSockAddr.sin_len = sizeof(stServeurSockAddr); + stServeurSockAddr.sin_addr.s_addr = inet_addr(cServer); + stServeurSockAddr.sin_port = htons(SMTP_PORT); + stServeurSockAddr.sin_family = AF_INET; + + // clear the flag + bSendMail = pdFALSE; + + // socket as a stream + if ( (lSocket = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + // socket failed, blink a LED and stay here + for (;;) { + vParTestToggleLED( 0 ); + vTaskDelay( 200 ); + } + } + // connect to the server + if(connect(lSocket,(struct sockaddr *)&stServeurSockAddr, sizeof(stServeurSockAddr)) < 0) + { + // connect failed, blink a LED and stay here + for (;;) { + vParTestToggleLED( 1 ); + vTaskDelay( 200 ); + } + } + else + { +//Server: 220 SMTP Ready + /* wait for SMTP Server answer */ + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_EHLO_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: EHLO smtp.domain.com + /* send ehlo */ + send(lSocket, cEhlo, strlen(cEhlo), 0); +//Server: 250 + /* wait for SMTP Server answer */ + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Server: 250 HELP + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); +//Client: MAIL FROM: + /* send MAIL FROM */ + send(lSocket, cMailfrom, strlen(cMailfrom), 0); +//Server: 250 OK + /* wait for SMTP Server answer */ + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: RCPT TO: + /* send RCPT TO */ + send(lSocket, cMailto, strlen(cMailto), 0); +//Server: 250 OK + /* wait for SMTP Server answer */ + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: DATA + /* send DATA */ + send(lSocket, SMTP_DATA_STRING, 6, 0); +//Server: 354 Start mail input; end with . + /* wait for SMTP Server answer */ + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_START_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0) + { + /* send content */ + send(lSocket, cMailcontent, strlen(cMailcontent), 0); +//Client: . + /* send "." */ + send(lSocket, SMTP_MAIL_END_STRING, 5, 0); +//Server: 250 OK + /* wait for SMTP Server answer */ + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_OK_STRING, sizeof(cTempBuffer)) >= 0) + { +//Client: QUIT + /* send QUIT */ + send(lSocket, SMTP_QUIT_STRING, 8, 0); +//Server: 221 smtp.domain.com closing transmission + do + { + lRetval = recv(lSocket, cTempBuffer, sizeof(cTempBuffer), 0); + }while (lRetval <= 0); + if (strncmp(cTempBuffer, SMTP_END_OF_TRANSMISSION_STRING, sizeof(cTempBuffer)) >= 0) + { + vParTestSetLED( 3 , pdTRUE ); + } + } + } + } + } + } + /* close socket */ + close(lSocket); + } + } + } +} +#endif diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.h b/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.h new file mode 100644 index 000000000..ca9895886 --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/NETWORK/BasicSMTP/BasicSMTP.h @@ -0,0 +1,57 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic SMTP Host for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef BASIC_SMTP_SERVER_H +#define BASIC_SMTP_SERVER_H + +#include "portmacro.h" + + +/* The function that implements the SMTP host task. */ +portTASK_FUNCTION_PROTO( vBasicSMTPHost, pvParameters ); + + + +#endif + diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.c b/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.c new file mode 100644 index 000000000..5b2c405ac --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.c @@ -0,0 +1,473 @@ +/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic TFTP Server for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + Implements a simplistic TFTP server. + + In order to put data on the TFTP server (not over 2048 bytes) + tftp 192.168.0.2 PUT + this will copy file from your hard drive to the RAM buffer of the application + + tftp 192.168.0.2 GET + this will copy file from the RAM buffer of the application to your hard drive + You can then check that src_filename and dst_filename are identical +*/ + +#if (TFTP_USED == 1) + +#include + + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "partest.h" +#include "BasicTFTP.h" + + +/* Demo includes. */ +#include "AVR32_EMAC.h" +#include "portmacro.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "lwip/opt.h" +#include "lwip/api.h" +#include "lwip/arch.h" +#include "lwip/sys.h" +#include "netif/loopif.h" +#include "lwip/sockets.h" + +#define O_WRONLY 1 +#define O_RDONLY 2 + + +/* The port on which we listen. */ +#define TFTP_PORT ( 69 ) + +/* Delay on close error. */ +#define TFTP_DELAY ( 10 ) + +/* Delay on bind error. */ +#define TFTP_ERROR_DELAY ( 40 ) + +#define TFTP_LED ( 4 ) + +char data_out[SEGSIZE+sizeof(struct tftphdr)]; +char data_in[SEGSIZE+sizeof(struct tftphdr)]; + +//struct tftp_server *server; + +/*------------------------------------------------------------*/ +static char * errmsg[] = { + "Undefined error code", // 0 nothing defined + "File not found", // 1 TFTP_ENOTFOUND + "Access violation", // 2 TFTP_EACCESS + "Disk full or allocation exceeded", // 3 TFTP_ENOSPACE + "Illegal TFTP operation", // 4 TFTP_EBADOP + "Unknown transfer ID", // 5 TFTP_EBADID + "File already exists", // 6 TFTP_EEXISTS + "No such user", // 7 TFTP_ENOUSER +}; + + +/* Send an error packet to the client */ +static void +tftpd_send_error(int s, struct tftphdr * reply, int err, + struct sockaddr_in *from_addr, int from_len) +{ + if ( ( 0 <= err ) && ( sizeof(errmsg)/sizeof(errmsg[0]) > err) ) { + reply->th_opcode = htons(ERROR); + reply->th_code = htons(err); + if ( (0 > err) || (sizeof(errmsg)/sizeof(errmsg[0]) <= err) ) + err = 0; // Do not copy a random string from hyperspace + strcpy(reply->th_msg, errmsg[err]); + sendto(s, reply, 4+strlen(reply->th_msg)+1, 0, + (struct sockaddr *)from_addr, from_len); + } +} + +portCHAR cRamBuffer[2048]; +int lCurrentBlock = 0; +int lTotalLength = 0; + + +int tftpd_close_data_file(int fd) +{ + lCurrentBlock = 0; + return (5); +} + +int tftpd_open_data_file(int fd, int mode) +{ + lCurrentBlock = 0; + return (5); +} + +int tftpd_read_data_file(int fd, portCHAR * buffer, int length) +{ +int lReturnValue; + + if ((lTotalLength -= length) >= 0) { + lReturnValue = length; + } + else + { + lReturnValue = lTotalLength + length; + lTotalLength = 0; + } + memcpy(buffer, &cRamBuffer[lCurrentBlock * SEGSIZE], lReturnValue); + lCurrentBlock++; + return (lReturnValue); +} + +// +// callback to store data to the RAM buffer +// +int tftpd_write_data_file(int fd, portCHAR * buffer, int length) +{ + lTotalLength += length; + memcpy(&cRamBuffer[lCurrentBlock * SEGSIZE], buffer, length); + lCurrentBlock++; + return (length); +} + +// +// Receive a file from the client +// +static void +tftpd_write_file(struct tftphdr *hdr, + struct sockaddr_in *from_addr, int from_len) +{ + + struct tftphdr *reply = (struct tftphdr *)data_out; + struct tftphdr *response = (struct tftphdr *)data_in; + int fd, len, ok, tries, closed, data_len, s; + unsigned short block; + struct timeval timeout; + fd_set fds; + int total_timeouts = 0; + struct sockaddr_in client_addr, local_addr; + int client_len; + + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) { + return; + } + + memset((char *)&local_addr, 0, sizeof(local_addr)); + local_addr.sin_family = AF_INET; + local_addr.sin_len = sizeof(local_addr); + local_addr.sin_addr.s_addr = htonl(INADDR_ANY); + local_addr.sin_port = htons(INADDR_ANY); + + if (bind(s, (struct sockaddr *)&local_addr, sizeof(local_addr)) < 0) { + // Problem setting up my end + close(s); + return; + } + + if ((fd = tftpd_open_data_file((int)hdr->th_stuff, O_WRONLY)) < 0) { + tftpd_send_error(s,reply,TFTP_ENOTFOUND,from_addr, from_len); + close(s); + return; + } + + ok = pdTRUE; + closed = pdFALSE; + block = 0; + while (ok) { + // Send ACK telling client he can send data + reply->th_opcode = htons(ACK); + reply->th_block = htons(block++); // postincrement + for (tries = 0; tries < TFTP_RETRIES_MAX; tries++) { + sendto(s, reply, 4, 0, (struct sockaddr *)from_addr, from_len); + repeat_select: + timeout.tv_sec = TFTP_TIMEOUT_PERIOD; + timeout.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(s, &fds); + vParTestToggleLED( TFTP_LED ); + if (lwip_select(s+1, &fds, 0, 0, &timeout) <= 0) { + if (++total_timeouts > TFTP_TIMEOUT_MAX) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + break; + } + continue; // retry the send, using up one retry. + } + vParTestToggleLED( TFTP_LED ); + // Some data has arrived + data_len = sizeof(data_in); + client_len = sizeof(client_addr); + if ((data_len = recvfrom(s, data_in, data_len, 0, + (struct sockaddr *)&client_addr, &client_len)) < 0) { + // What happened? No data here! + continue; // retry the send, using up one retry. + } + if (ntohs(response->th_opcode) == DATA && + ntohs(response->th_block) < block) { + // Then it is repeat DATA with an old block; listen again, + // but do not repeat sending the current ack, and do not + // use up a retry count. (we do re-send the ack if + // subsequently we time out) + goto repeat_select; + } + if (ntohs(response->th_opcode) == DATA && + ntohs(response->th_block) == block) { + // Good data - write to file + len = tftpd_write_data_file(fd, response->th_data, data_len-4); + if (len < (data_len-4)) { + // File is "full" + tftpd_send_error(s,reply,TFTP_ENOSPACE, + from_addr, from_len); + ok = pdFALSE; // Give up + break; // out of the retries loop + } + if (data_len < (SEGSIZE+4)) { + // End of file + closed = pdTRUE; + ok = pdFALSE; + vParTestSetLED( 0 , 0 ); + + if (tftpd_close_data_file(fd) == -1) { + tftpd_send_error(s,reply,TFTP_EACCESS, + from_addr, from_len); + + break; // out of the retries loop + } + // Exception to the loop structure: we must ACK the last + // packet, the one that implied EOF: + reply->th_opcode = htons(ACK); + reply->th_block = htons(block++); // postincrement + sendto(s, reply, 4, 0, (struct sockaddr *)from_addr, from_len); + break; // out of the retries loop + } + // Happy! Break out of the retries loop. + break; + } + } // End of the retries loop. + if (TFTP_RETRIES_MAX <= tries) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + } + } + close(s); + if (!closed) { + tftpd_close_data_file(fd); + } +} + + +// +// Send a file to the client +// +static void +tftpd_read_file(struct tftphdr *hdr, + struct sockaddr_in *from_addr, int from_len) +{ + struct tftphdr *reply = (struct tftphdr *)data_out; + struct tftphdr *response = (struct tftphdr *)data_in; + int fd, len, tries, ok, data_len, s; + unsigned short block; + struct timeval timeout; + fd_set fds; + int total_timeouts = 0; + struct sockaddr_in client_addr, local_addr; + int client_len; + + s = socket(AF_INET, SOCK_DGRAM, 0); + if (s < 0) { + return; + } + memset((char *)&local_addr, 0, sizeof(local_addr)); + local_addr.sin_family = AF_INET; + local_addr.sin_len = sizeof(local_addr); + local_addr.sin_addr.s_addr = htonl(INADDR_ANY); + local_addr.sin_port = htons(INADDR_ANY); + if (bind(s, (struct sockaddr *)&local_addr, sizeof(local_addr)) < 0) { + // Problem setting up my end + close(s); + return; + } + if ((fd = tftpd_open_data_file((int)hdr->th_stuff, O_RDONLY)) < 0) { + tftpd_send_error(s,reply,TFTP_ENOTFOUND,from_addr, from_len); + close(s); + return; + } + block = 0; + ok = pdTRUE; + while (ok) { + // Read next chunk of file + len = tftpd_read_data_file(fd, reply->th_data, SEGSIZE); + reply->th_block = htons(++block); // preincrement + reply->th_opcode = htons(DATA); + for (tries = 0; tries < TFTP_RETRIES_MAX; tries++) { + if (sendto(s, reply, 4+len, 0, + (struct sockaddr *)from_addr, from_len) < 0) { + // Something went wrong with the network! + ok = pdFALSE; + break; + } + repeat_select: + timeout.tv_sec = TFTP_TIMEOUT_PERIOD; + timeout.tv_usec = 0; + FD_ZERO(&fds); + FD_SET(s, &fds); + vParTestToggleLED( TFTP_LED ); + if (select(s+1, &fds, 0, 0, &timeout) <= 0) { + if (++total_timeouts > TFTP_TIMEOUT_MAX) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + break; + } + continue; // retry the send, using up one retry. + } + vParTestToggleLED( TFTP_LED ); + data_len = sizeof(data_in); + client_len = sizeof(client_addr); + if ((data_len = recvfrom(s, data_in, data_len, 0, + (struct sockaddr *)&client_addr, + &client_len)) < 0) { + // What happened? Maybe someone lied to us... + continue; // retry the send, using up one retry. + } + if ((ntohs(response->th_opcode) == ACK) && + (ntohs(response->th_block) < block)) { + // Then it is a repeat ACK for an old block; listen again, + // but do not repeat sending the current block, and do not + // use up a retry count. (we do re-send the data if + // subsequently we time out) + goto repeat_select; + } + if ((ntohs(response->th_opcode) == ACK) && + (ntohs(response->th_block) == block)) { + // Happy! Break out of the retries loop. + break; + } + } // End of the retries loop. + if (TFTP_RETRIES_MAX <= tries) { + tftpd_send_error(s,reply,TFTP_EBADOP,from_addr, from_len); + ok = pdFALSE; + } + if (len < SEGSIZE) { + break; // That's end of file then. + } + } + close(s); + tftpd_close_data_file(fd); +} + + + +portTASK_FUNCTION( vBasicTFTPServer, pvParameters ) +{ + int lSocket; + int lDataLen, lRecvLen, lFromLen; + struct sockaddr_in sLocalAddr, sFromAddr; + portCHAR cData[SEGSIZE+sizeof(struct tftphdr)]; + struct tftphdr *sHdr = (struct tftphdr *)cData; + + // Set up port + // Network order in info; host order in server: + + for (;;) { + // Create socket + lSocket = socket(AF_INET, SOCK_DGRAM, 0); + if (lSocket < 0) { + return; + } + memset((char *)&sLocalAddr, 0, sizeof(sLocalAddr)); + sLocalAddr.sin_family = AF_INET; + sLocalAddr.sin_len = sizeof(sLocalAddr); + sLocalAddr.sin_addr.s_addr = htonl(INADDR_ANY); + sLocalAddr.sin_port = TFTP_PORT; + + if (bind(lSocket, (struct sockaddr *)&sLocalAddr, sizeof(sLocalAddr)) < 0) { + // Problem setting up my end + close(lSocket); + return; + } + + + lRecvLen = sizeof(cData); + lFromLen = sizeof(sFromAddr); + lDataLen = recvfrom(lSocket, sHdr, lRecvLen, 0, + (struct sockaddr *)&sFromAddr, &lFromLen); + vParTestSetLED( TFTP_LED , pdTRUE ); + close(lSocket); // so that other servers can bind to the TFTP socket + + if ( lDataLen < 0) { + + } else { + switch (ntohs(sHdr->th_opcode)) { + case WRQ: + tftpd_write_file(sHdr, &sFromAddr, lFromLen); + vParTestSetLED( TFTP_LED , pdFALSE ); + break; + case RRQ: + tftpd_read_file(sHdr, &sFromAddr, lFromLen); + vParTestSetLED( TFTP_LED , pdFALSE ); + break; + case ACK: + case DATA: + case ERROR: + vParTestSetLED( TFTP_LED , pdFALSE ); + // Ignore + break; + default: + for(;;) + { + vParTestToggleLED( TFTP_LED ); + vTaskDelay(200); + } + } + } + } +} +#endif diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.h b/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.h new file mode 100644 index 000000000..92fdf4f9f --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/NETWORK/BasicTFTP/BasicTFTP.h @@ -0,0 +1,143 @@ +/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic TFTP Server for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +#ifndef BASIC_TFTP_SERVER_H +#define BASIC_TFTP_SERVER_H + +#include "portmacro.h" + +/* tftp_support.h */ + +/* + * File transfer modes + */ +#define TFTP_NETASCII 0 // Text files +#define TFTP_OCTET 1 // Binary files + +/* + * Errors + */ + +// These initial 7 are passed across the net in "ERROR" packets. +#define TFTP_ENOTFOUND 1 /* file not found */ +#define TFTP_EACCESS 2 /* access violation */ +#define TFTP_ENOSPACE 3 /* disk full or allocation exceeded */ +#define TFTP_EBADOP 4 /* illegal TFTP operation */ +#define TFTP_EBADID 5 /* unknown transfer ID */ +#define TFTP_EEXISTS 6 /* file already exists */ +#define TFTP_ENOUSER 7 /* no such user */ +// These extensions are return codes in our API, *never* passed on the net. +#define TFTP_TIMEOUT 8 /* operation timed out */ +#define TFTP_NETERR 9 /* some sort of network error */ +#define TFTP_INVALID 10 /* invalid parameter */ +#define TFTP_PROTOCOL 11 /* protocol violation */ +#define TFTP_TOOLARGE 12 /* file is larger than buffer */ + +#define TFTP_TIMEOUT_PERIOD 5 // Seconds between retries +#define TFTP_TIMEOUT_MAX 50 // Max timeouts over all blocks +#define TFTP_RETRIES_MAX 5 // retries per block before giving up + +/* netdb.h */ +// Internet services +struct servent { +char *s_name; /* official service name */ +char **s_aliases; /* alias list */ +int s_port; /* port number */ +char *s_proto; /* protocol to use */ +}; + +/* arpa/tftp.h */ + +/* + * Trivial File Transfer Protocol (IEN-133) + */ +#define SEGSIZE 512 /* data segment size */ + +/* + * Packet types. + */ + +#define th_block th_u.tu_block +#define th_code th_u.tu_code +#define th_stuff th_u.tu_stuff +#define th_msg th_data + +/* + * Error codes. + */ +#define EUNDEF 0 /* not defined */ +#define ENOTFOUND 1 /* file not found */ +#define EACCESS 2 /* access violation */ +#define ENOSPACE 3 /* disk full or allocation exceeded */ +#define EBADOP 4 /* illegal TFTP operation */ +#define EBADID 5 /* unknown transfer ID */ +#define EEXISTS 6 /* file already exists */ +#define ENOUSER 7 /* no such user */ + + + +#define RRQ 01 /* read request */ +#define WRQ 02 /* write request */ +#define DATA 03 /* data packet */ +#define ACK 04 /* acknowledgement */ +#define ERROR 05 /* error code */ + +struct tftphdr { + short th_opcode; /* packet type */ + union { + unsigned short tu_block; /* block # */ + short tu_code; /* error code */ + char tu_stuff[1]; /* request packet stuff */ + } __attribute__ ((packed)) th_u; + char th_data[1]; /* data or error string */ +} __attribute__ ((packed)); + + +/* The function that implements the TFTP server task. */ +portTASK_FUNCTION_PROTO( vBasicTFTPServer, pvParameters ); + + + +#endif + diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.c b/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.c new file mode 100644 index 000000000..a54f214bd --- /dev/null +++ b/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.c @@ -0,0 +1,209 @@ +/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */ + +/*This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ********************************************************************* + * + * \brief Basic WEB Server for AVR32 UC3. + * + * - Compiler: GNU GCC for AVR32 + * - Supported devices: All AVR32 devices can be used. + * - AppNote: + * + * \author Atmel Corporation: http://www.atmel.com \n + * Support email: avr32@atmel.com + * + *****************************************************************************/ + +/* Copyright (c) 2007, Atmel Corporation All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of ATMEL may not be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND + * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + + +/* + Implements a simplistic WEB server. Every time a connection is made and + data is received a dynamic page that shows the current FreeRTOS.org kernel + statistics is generated and returned. The connection is then closed. + + This file was adapted from a FreeRTOS lwIP slip demo supplied by a third + party. +*/ + +#if (HTTP_USED == 1) + + +/* Standard includes. */ +#include +#include +#include + +#include "conf_eth.h" + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "partest.h" +#include "serial.h" + +/* Demo includes. */ +/* Demo app includes. */ +#include "AVR32_EMAC.h" +#include "portmacro.h" + +/* lwIP includes. */ +#include "lwip/api.h" +#include "lwip/tcpip.h" +#include "lwip/memp.h" +#include "lwip/stats.h" +#include "netif/loopif.h" + +/* ethernet includes */ +#include "ethernet.h" + +/*! The size of the buffer in which the dynamic WEB page is created. */ +#define webMAX_PAGE_SIZE 512 + +/*! Standard GET response. */ +#define webHTTP_OK "HTTP/1.0 200 OK\r\nContent-type: text/html\r\n\r\n" + +/*! The port on which we listen. */ +#define webHTTP_PORT ( 80 ) + +/*! Delay on close error. */ +#define webSHORT_DELAY ( 10 ) + +/*! Format of the dynamic page that is returned on each connection. */ +#define webHTML_START \ +"\ +\ +\ +\ +\r\nPage Hits = " + +#define webHTML_END \ +"\r\n\ +\r\n\ +" + +portCHAR cDynamicPage[ webMAX_PAGE_SIZE ]; +portCHAR cPageHits[ 11 ]; + + +/*! Function to process the current connection */ +static void prvweb_ParseHTMLRequest( struct netconn *pxNetCon ); + + +/*! \brief WEB server main task + * check for incoming connection and process it + * + * \param pvParameters Input. Not Used. + * + */ +portTASK_FUNCTION( vBasicWEBServer, pvParameters ) +{ +struct netconn *pxHTTPListener, *pxNewConnection; + + /* Create a new tcp connection handle */ + pxHTTPListener = netconn_new( NETCONN_TCP ); + netconn_bind(pxHTTPListener, NULL, webHTTP_PORT ); + netconn_listen( pxHTTPListener ); + + /* Loop forever */ + for( ;; ) + { + /* Wait for a first connection. */ + pxNewConnection = netconn_accept(pxHTTPListener); + vParTestSetLED(webCONN_LED, pdTRUE); + + if(pxNewConnection != NULL) + { + prvweb_ParseHTMLRequest(pxNewConnection); + }/* end if new connection */ + + vParTestSetLED(webCONN_LED, pdFALSE); + + } /* end infinite loop */ +} + + +/*! \brief parse the incoming request + * parse the HTML request and send file + * + * \param pxNetCon Input. The netconn to use to send and receive data. + * + */ +static void prvweb_ParseHTMLRequest( struct netconn *pxNetCon ) +{ +struct netbuf *pxRxBuffer; +portCHAR *pcRxString; +unsigned portSHORT usLength; +static unsigned portLONG ulPageHits = 0; + + /* We expect to immediately get data. */ + pxRxBuffer = netconn_recv( pxNetCon ); + + if( pxRxBuffer != NULL ) + { + /* Where is the data? */ + netbuf_data( pxRxBuffer, ( void * ) &pcRxString, &usLength ); + + /* Is this a GET? We don't handle anything else. */ + if( !strncmp( pcRxString, "GET", 3 ) ) + { + pcRxString = cDynamicPage; + + /* Update the hit count. */ + ulPageHits++; + sprintf( cPageHits, "%d", (int)ulPageHits ); + + /* Write out the HTTP OK header. */ + netconn_write( pxNetCon, webHTTP_OK, (u16_t) strlen( webHTTP_OK ), NETCONN_COPY ); + + /* Generate the dynamic page... First the page header. */ + strcpy( cDynamicPage, webHTML_START ); + + /* ... Then the hit count... */ + strcat( cDynamicPage, cPageHits ); + strcat( cDynamicPage, "

Task          State  Priority  Stack	#
************************************************
" );
+
+			/* ... Then the list of tasks and their status... */
+			vTaskList( ( signed portCHAR * ) cDynamicPage + strlen( cDynamicPage ) );
+
+			/* ... Finally the page footer. */
+			strcat( cDynamicPage, webHTML_END );
+
+			/* Write out the dynamically generated page. */
+			netconn_write( pxNetCon, cDynamicPage, (u16_t) strlen( cDynamicPage ), NETCONN_COPY );
+		}
+		netbuf_delete( pxRxBuffer );
+	}
+
+	netconn_close( pxNetCon );
+	netconn_delete( pxNetCon );
+}
+
+#endif
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.h b/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.h
new file mode 100644
index 000000000..70722d5c2
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/BasicWEB/BasicWEB.h
@@ -0,0 +1,59 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Basic WEB Server for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef BASIC_WEB_SERVER_H
+#define BASIC_WEB_SERVER_H
+
+#include "portmacro.h"
+
+
+/*! \brief WEB server main task
+ *
+ *  \param pvParameters   Input. Not Used.
+ *
+ */
+portTASK_FUNCTION_PROTO( vBasicWEBServer, pvParameters );
+
+#endif
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_CONF_EMAC.h b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_CONF_EMAC.h
new file mode 100644
index 000000000..aff683a49
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_CONF_EMAC.h
@@ -0,0 +1,62 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief EMAC abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef AVR32_CONF_EMAC_H
+#define AVR32_CONF_EMAC_H
+
+#include "lwip/opt.h"
+
+/*! Number of receive buffers */
+#define NB_RX_BUFFERS     20
+
+/*! USE_RMII_INTERFACE must be defined as 1 to use an RMII interface, or 0
+to use an MII interface. */
+#define USE_RMII_INTERFACE 1
+
+/*! Number of Transmit buffers */
+#define NB_TX_BUFFERS     ( MEMP_NUM_PBUF / 2 )
+
+/*! Size of each Transmit buffer. */
+#define ETH_TX_BUFFER_SIZE    1024 //( PBUF_POOL_BUFSIZE  )
+
+#endif //* AVR32_CONF_EMAC_H
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_EMAC.c b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_EMAC.c
new file mode 100644
index 000000000..a5ee1b89e
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_EMAC.c
@@ -0,0 +1,785 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief EMAC abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices with a MACB can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+ * Interrupt driven driver for the EMAC peripheral.  This driver is not
+ * reentrant, re-entrancy is handled by a semaphore at the network interface
+ * level. 
+ */
+
+
+/* Standard includes. */
+#include 
+#include 
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "task.h"
+
+/* Demo app includes. */
+#include "AVR32_EMAC.h"
+#include "AVR32_CONF_EMAC.h"
+#include "DP83848.h"
+#include "intc.h"
+
+/* Hardware specific includes. */
+#include "gpio.h"
+
+/* Size of each receive buffer - DO NOT CHANGE. */
+#define ETH_RX_BUFFER_SIZE    128
+
+/* The buffer addresses written into the descriptors must be aligned so the
+last few bits are zero.  These bits have special meaning for the EMAC
+peripheral and cannot be used as part of the address. */
+#define emacADDRESS_MASK      ( ( unsigned portLONG ) 0xFFFFFFFC )
+
+/* Bit used within the address stored in the descriptor to mark the last
+descriptor in the array. */
+#define emacRX_WRAP_BIT       ( ( unsigned portLONG ) 0x02 )
+
+
+/* A short delay is used to wait for a buffer to become available, should
+one not be immediately available when trying to transmit a frame. */
+#define emacBUFFER_WAIT_DELAY   ( 2 )
+#define emacMAX_WAIT_CYCLES     ( ( portBASE_TYPE ) ( configTICK_RATE_HZ / 40 ) )
+
+/* The time to block waiting for input. */
+#define emacBLOCK_TIME_WAITING_FOR_INPUT   ( ( portTickType ) 100 )
+
+/* Misc defines. */
+#define emacNO_DELAY        ( 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Buffer written to by the EMAC DMA.  Must be aligned as described by the
+comment above the emacADDRESS_MASK definition. */
+static volatile portCHAR pcRxBuffer[ NB_RX_BUFFERS * ETH_RX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
+
+/* Buffer read by the EMAC DMA.  Must be aligned as described by the comment
+above the emacADDRESS_MASK definition. */
+static portCHAR pcTxBuffer[ NB_TX_BUFFERS * ETH_TX_BUFFER_SIZE ] __attribute__ ((aligned (8)));
+
+/* Descriptors used to communicate between the program and the EMAC peripheral.
+These descriptors hold the locations and state of the Rx and Tx buffers. */
+static volatile AVR32_TxTdDescriptor xTxDescriptors[ NB_TX_BUFFERS ];
+static volatile AVR32_RxTdDescriptor xRxDescriptors[ NB_RX_BUFFERS ];
+
+/* The IP and Ethernet addresses are read from the header files. */
+portCHAR cMACAddress[ 6 ] = { emacETHADDR0, emacETHADDR1, emacETHADDR2, emacETHADDR3, emacETHADDR4, emacETHADDR5 };
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+
+/*
+ * Prototype for the EMAC interrupt function - called by the asm wrapper.
+ */
+void vEMAC_ISR( void ) __attribute__ ((naked));
+
+/*
+ * Initialise both the Tx and Rx descriptors used by the EMAC.
+ */
+static void prvSetupDescriptors(void);
+
+/*
+ * Write our MAC address into the EMAC.  
+ */
+static void prvSetupMACAddress( void );
+
+/*
+ * Configure the EMAC and AIC for EMAC interrupts.
+ */
+static void prvSetupEMACInterrupt( void );
+
+/*
+ * Some initialisation functions taken from the Atmel EMAC sample code.
+ */
+static unsigned portLONG vReadPHY( unsigned portCHAR ucAddress );
+
+static void vWritePHY( unsigned portCHAR ucAddress, unsigned portLONG ulValue);
+
+static portBASE_TYPE prvProbePHY( void );
+
+/* The semaphore used by the EMAC ISR to wake the EMAC task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+/* Holds the index to the next buffer from which data will be read. */
+static volatile unsigned portLONG ulNextRxBuffer = 0;
+
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame )
+{
+static unsigned portBASE_TYPE uxTxBufferIndex = 0;
+//portBASE_TYPE xWaitCycles = 0;
+portLONG lReturn = pdPASS;
+portCHAR *pcBuffer;
+unsigned portLONG ulLastBuffer, ulDataBuffered = 0, ulDataRemainingToSend, ulLengthToSend;
+
+  /* If the length of data to be transmitted is greater than each individual
+  transmit buffer then the data will be split into more than one buffer.
+  Loop until the entire length has been buffered. */
+  while( ulDataBuffered < ulLength )
+  {
+    /* Is a buffer available? */
+    while( !( xTxDescriptors[ uxTxBufferIndex ].U_Status.status & AVR32_TRANSMIT_OK ) )
+    {
+      /* There is no room to write the Tx data to the Tx buffer.  Wait a
+      short while, then try again. */
+        vTaskDelay( emacBUFFER_WAIT_DELAY );
+    }
+  
+    /* lReturn will only be pdPASS if a buffer is available. */
+    if( lReturn == pdPASS )
+    {
+      portENTER_CRITICAL();
+      {
+        /* Get the address of the buffer from the descriptor, then copy
+        the data into the buffer. */
+        pcBuffer = ( portCHAR * ) xTxDescriptors[ uxTxBufferIndex ].addr;
+
+        /* How much can we write to the buffer? */
+        ulDataRemainingToSend = ulLength - ulDataBuffered;
+        if( ulDataRemainingToSend <= ETH_TX_BUFFER_SIZE )
+        {
+          /* We can write all the remaining bytes. */
+          ulLengthToSend = ulDataRemainingToSend;
+        }
+        else
+        {
+          /* We can not write more than ETH_TX_BUFFER_SIZE in one go. */
+          ulLengthToSend = ETH_TX_BUFFER_SIZE;
+        }
+
+        /* Copy the data into the buffer. */
+        memcpy( ( void * ) pcBuffer, ( void * ) &( pcFrom[ ulDataBuffered ] ), ulLengthToSend );
+        ulDataBuffered += ulLengthToSend;
+
+        /* Is this the last data for the frame? */
+        if( lEndOfFrame && ( ulDataBuffered >= ulLength ) )
+        {
+          /* No more data remains for this frame so we can start the
+          transmission. */
+          ulLastBuffer = AVR32_LAST_BUFFER;
+        }
+        else
+        {
+          /* More data to come for this frame. */
+          ulLastBuffer = 0;
+        }
+  
+        /* Fill out the necessary in the descriptor to get the data sent,
+        then move to the next descriptor, wrapping if necessary. */
+        if( uxTxBufferIndex >= ( NB_TX_BUFFERS - 1 ) )
+        {
+          xTxDescriptors[ uxTxBufferIndex ].U_Status.status =   ( ulLengthToSend & ( unsigned portLONG ) AVR32_LENGTH_FRAME )
+                                      | ulLastBuffer
+                                      | AVR32_TRANSMIT_WRAP;
+          uxTxBufferIndex = 0;
+        }
+        else
+        {
+          xTxDescriptors[ uxTxBufferIndex ].U_Status.status =   ( ulLengthToSend & ( unsigned portLONG ) AVR32_LENGTH_FRAME )
+                                      | ulLastBuffer;
+          uxTxBufferIndex++;
+        }
+  
+        /* If this is the last buffer to be sent for this frame we can
+        start the transmission. */
+        if( ulLastBuffer )
+        {
+          AVR32_MACB.ncr |=  AVR32_MACB_TSTART_MASK;
+        }
+      }
+      portEXIT_CRITICAL();
+    }
+    else
+    {
+      break;
+    }
+  }
+
+  return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+unsigned portLONG ulEMACInputLength( void )
+{
+register unsigned portLONG ulIndex , ulLength = 0;
+
+  /* Skip any fragments.  We are looking for the first buffer that contains
+  data and has the SOF (start of frame) bit set. */
+  while( ( xRxDescriptors[ ulNextRxBuffer ].addr & AVR32_OWNERSHIP_BIT ) && !( xRxDescriptors[ ulNextRxBuffer ].U_Status.status & AVR32_SOF ) )
+  {
+    /* Ignoring this buffer.  Mark it as free again. */
+    xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );
+    ulNextRxBuffer++;
+    if( ulNextRxBuffer >= NB_RX_BUFFERS )
+    {
+      ulNextRxBuffer = 0;
+    }
+  }
+
+  /* We are going to walk through the descriptors that make up this frame,
+  but don't want to alter ulNextRxBuffer as this would prevent vEMACRead()
+  from finding the data.  Therefore use a copy of ulNextRxBuffer instead. */
+  ulIndex = ulNextRxBuffer;
+  /* Walk through the descriptors until we find the last buffer for this
+  frame.  The last buffer will give us the length of the entire frame. */
+  while( ( xRxDescriptors[ ulIndex ].addr & AVR32_OWNERSHIP_BIT ) && !ulLength )
+  {
+    ulLength = xRxDescriptors[ ulIndex ].U_Status.status & AVR32_LENGTH_FRAME;
+    /* Increment to the next buffer, wrapping if necessary. */
+    ulIndex++;
+    if( ulIndex >= NB_RX_BUFFERS )
+    {
+      ulIndex = 0;
+    }
+  }
+  return ulLength;
+}
+/*-----------------------------------------------------------*/
+
+/* See the header file for descriptions of public functions. */
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength )
+{
+static unsigned portLONG ulSectionBytesReadSoFar = 0, ulBufferPosition = 0, ulFameBytesReadSoFar = 0;
+static portCHAR *pcSource;
+register unsigned portLONG ulBytesRemainingInBuffer, ulRemainingSectionBytes;
+
+  /* Read ulSectionLength bytes from the Rx buffers.  This is not necessarily any
+  correspondence between the length of our Rx buffers, and the length of the
+  data we are returning or the length of the data being requested.  Therefore,
+  between calls  we have to remember not only which buffer we are currently
+  processing, but our position within that buffer.  This would be greatly
+  simplified if PBUF_POOL_BUFSIZE could be guaranteed to be greater than
+  the size of each Rx buffer, and that memory fragmentation did not occur.
+  
+  This function should only be called after a call to ulEMACInputLength().
+  This will ensure ulNextRxBuffer is set to the correct buffer. */
+
+
+  /* vEMACRead is called with pcTo set to NULL to indicate that we are about
+  to read a new frame.  Any fragments remaining in the frame we were
+  processing during the last call should be dropped. */
+  if( pcTo == NULL )
+  {
+    /* How many bytes are indicated as being in this buffer?  If none then
+    the buffer is completely full and the frame is contained within more
+    than one buffer. */
+    /* Reset our state variables ready for the next read from this buffer. */
+        pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+        ulFameBytesReadSoFar = ( unsigned portLONG ) 0;
+    ulBufferPosition = ( unsigned portLONG ) 0;
+  }
+  else
+  {
+    /* Loop until we have obtained the required amount of data. */
+    ulSectionBytesReadSoFar = 0;
+    while( ulSectionBytesReadSoFar < ulSectionLength )
+    {
+      /* We may have already read some data from this buffer.  How much
+      data remains in the buffer? */
+      ulBytesRemainingInBuffer = ( ETH_RX_BUFFER_SIZE - ulBufferPosition );
+
+      /* How many more bytes do we need to read before we have the
+      required amount of data? */
+      ulRemainingSectionBytes = ulSectionLength - ulSectionBytesReadSoFar;
+
+      /* Do we want more data than remains in the buffer? */
+      if( ulRemainingSectionBytes > ulBytesRemainingInBuffer )
+      {
+        /* We want more data than remains in the buffer so we can
+        write the remains of the buffer to the destination, then move
+        onto the next buffer to get the rest. */
+        memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulBytesRemainingInBuffer );
+        ulSectionBytesReadSoFar += ulBytesRemainingInBuffer;
+        ulFameBytesReadSoFar += ulBytesRemainingInBuffer;
+
+        /* Mark the buffer as free again. */
+        xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );
+        /* Move onto the next buffer. */
+        ulNextRxBuffer++;
+        if( ulNextRxBuffer >= NB_RX_BUFFERS )
+        {
+          ulNextRxBuffer = ( unsigned portLONG ) 0;
+        }
+
+        /* Reset the variables for the new buffer. */
+        pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+        ulBufferPosition = ( unsigned portLONG ) 0;
+      }
+      else
+      {
+        /* We have enough data in this buffer to send back.  Read out
+        enough data and remember how far we read up to. */
+        memcpy( &( pcTo[ ulSectionBytesReadSoFar ] ), &( pcSource[ ulBufferPosition ] ), ulRemainingSectionBytes );
+
+        /* There may be more data in this buffer yet.  Increment our
+        position in this buffer past the data we have just read. */
+        ulBufferPosition += ulRemainingSectionBytes;
+        ulSectionBytesReadSoFar += ulRemainingSectionBytes;
+        ulFameBytesReadSoFar += ulRemainingSectionBytes;
+
+        /* Have we now finished with this buffer? */
+        if( ( ulBufferPosition >= ETH_RX_BUFFER_SIZE ) || ( ulFameBytesReadSoFar >= ulTotalFrameLength ) )
+        {
+          /* Mark the buffer as free again. */
+          xRxDescriptors[ ulNextRxBuffer ].addr &= ~( AVR32_OWNERSHIP_BIT );
+          /* Move onto the next buffer. */
+          ulNextRxBuffer++;
+          if( ulNextRxBuffer >= NB_RX_BUFFERS )
+          {
+            ulNextRxBuffer = 0;
+          }
+          pcSource = ( portCHAR * )( xRxDescriptors[ ulNextRxBuffer ].addr & emacADDRESS_MASK );
+          ulBufferPosition = 0;
+        }
+      }
+    }
+  }
+}
+/*-----------------------------------------------------------*/
+void vEMACSetMACAddress(const portCHAR * EMACAddress)
+{
+  memcpy(cMACAddress, EMACAddress, sizeof(cMACAddress));
+}
+
+/* See the header file for descriptions of public functions. */
+xSemaphoreHandle xEMACInit( void )
+{
+unsigned long status;
+
+  /* enable GPIO's */
+  gpio_enable_module_pin(AVR32_MACB_TX_CLK_0_PIN, AVR32_MACB_TX_CLK_0_FUNCTION); //PB0
+  gpio_enable_module_pin(AVR32_MACB_TX_EN_0_PIN, AVR32_MACB_TX_EN_0_FUNCTION);   //PB1
+  gpio_enable_module_pin(AVR32_MACB_TXD_0_PIN, AVR32_MACB_TXD_0_FUNCTION);       //PB2
+  gpio_enable_module_pin(AVR32_MACB_TXD_1_PIN, AVR32_MACB_TXD_1_FUNCTION);       //PB3
+
+  gpio_enable_module_pin(AVR32_MACB_RXD_0_PIN, AVR32_MACB_RXD_0_FUNCTION);       //PB5
+  gpio_enable_module_pin(AVR32_MACB_RXD_1_PIN, AVR32_MACB_RXD_1_FUNCTION);       //PB6
+  gpio_enable_module_pin(AVR32_MACB_RX_ER_0_PIN, AVR32_MACB_RX_ER_0_FUNCTION);   //PB7
+  gpio_enable_module_pin(AVR32_MACB_MDC_0_PIN, AVR32_MACB_MDC_0_FUNCTION);       //PB8
+  gpio_enable_module_pin(AVR32_MACB_MDIO_0_PIN, AVR32_MACB_MDIO_0_FUNCTION);     //PB9
+
+  gpio_enable_module_pin(AVR32_MACB_RX_DV_0_PIN, AVR32_MACB_RX_DV_0_FUNCTION);   //PB15
+
+
+  /* set up registers */
+  AVR32_MACB.ncr = 0;
+  AVR32_MACB.tsr = ~0UL;
+  AVR32_MACB.rsr = ~0UL;
+  AVR32_MACB.idr = ~0UL;
+  status = AVR32_MACB.isr;
+
+
+#ifndef USE_RMII_INTERFACE
+  // RMII not used, set 1 to the USRIO Register
+  AVR32_MACB.usrio |= AVR32_MACB_RMII_MASK;
+#else
+  // RMII used, set 0 to the USRIO Register
+  AVR32_MACB.usrio &= ~AVR32_MACB_RMII_MASK;
+#endif
+
+  /* Load our MAC address into the EMAC. */
+  prvSetupMACAddress();
+
+  /* Setup the buffers and descriptors. */
+  prvSetupDescriptors();
+
+#if configCPU_CLOCK_HZ <= 20000000
+  AVR32_MACB.ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV8 << AVR32_MACB_NCFGR_CLK_OFFSET);
+#elif configCPU_CLOCK_HZ <= 40000000
+  AVR32_MACB.ncfgr |= (AVR32_MACB_NCFGR_CLK_DIV16 << AVR32_MACB_NCFGR_CLK_OFFSET);
+#elif configCPU_CLOCK_HZ <= 80000000
+  AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_CLK_DIV32 << AVR32_MACB_NCFGR_CLK_OFFSET;
+#elif configCPU_CLOCK_HZ <= 160000000
+  AVR32_MACB.ncfgr |= AVR32_MACB_NCFGR_CLK_DIV64 << AVR32_MACB_NCFGR_CLK_OFFSET;
+#else
+# error System clock too fast
+#endif
+
+  /* Are we connected? */
+  if( prvProbePHY() )
+  {
+    /* Enable the interrupt! */
+    portENTER_CRITICAL();
+    {
+      prvSetupEMACInterrupt();
+      vPassEMACSemaphore( xSemaphore );
+    }
+    portEXIT_CRITICAL();
+    /* Enable Rx and Tx, plus the stats register. */
+    AVR32_MACB.ncr = AVR32_MACB_NCR_TE_MASK | AVR32_MACB_NCR_RE_MASK;
+  }
+  return xSemaphore;
+}
+
+/* See the header file for descriptions of public functions. */
+void vClearEMACTxBuffer( void )
+{
+static unsigned portBASE_TYPE uxNextBufferToClear = 0;
+
+  /* Called on Tx interrupt events to set the AT91C_TRANSMIT_OK bit in each
+  Tx buffer within the frame just transmitted.  This marks all the buffers
+  as available again.
+
+  The first buffer in the frame should have the bit set automatically. */
+  if( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_TRANSMIT_OK )
+  {
+    /* Loop through the other buffers in the frame. */
+    while( !( xTxDescriptors[ uxNextBufferToClear ].U_Status.status & AVR32_LAST_BUFFER ) )
+    {
+      uxNextBufferToClear++;
+
+      if( uxNextBufferToClear >= NB_TX_BUFFERS )
+      {
+        uxNextBufferToClear = 0;
+      }
+
+      xTxDescriptors[ uxNextBufferToClear ].U_Status.status |= AVR32_TRANSMIT_OK;
+    }
+
+    /* Start with the next buffer the next time a Tx interrupt is called. */
+    uxNextBufferToClear++;
+
+    /* Do we need to wrap back to the first buffer? */
+    if( uxNextBufferToClear >= NB_TX_BUFFERS )
+    {
+      uxNextBufferToClear = 0;
+    }
+  }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupDescriptors(void)
+{
+unsigned portBASE_TYPE xIndex;
+unsigned portLONG ulAddress;
+
+  /* Initialise xRxDescriptors descriptor. */
+  for( xIndex = 0; xIndex < NB_RX_BUFFERS; ++xIndex )
+  {
+    /* Calculate the address of the nth buffer within the array. */
+    ulAddress = ( unsigned portLONG )( pcRxBuffer + ( xIndex * ETH_RX_BUFFER_SIZE ) );
+
+    /* Write the buffer address into the descriptor.  The DMA will place
+    the data at this address when this descriptor is being used.  Mask off
+    the bottom bits of the address as these have special meaning. */
+    xRxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+  }
+
+  /* The last buffer has the wrap bit set so the EMAC knows to wrap back
+  to the first buffer. */
+  xRxDescriptors[ NB_RX_BUFFERS - 1 ].addr |= emacRX_WRAP_BIT;
+
+  /* Initialise xTxDescriptors. */
+  for( xIndex = 0; xIndex < NB_TX_BUFFERS; ++xIndex )
+  {
+    /* Calculate the address of the nth buffer within the array. */
+    ulAddress = ( unsigned portLONG )( pcTxBuffer + ( xIndex * ETH_TX_BUFFER_SIZE ) );
+
+    /* Write the buffer address into the descriptor.  The DMA will read
+    data from here when the descriptor is being used. */
+    xTxDescriptors[ xIndex ].addr = ulAddress & emacADDRESS_MASK;
+    xTxDescriptors[ xIndex ].U_Status.status = AVR32_TRANSMIT_OK;
+  }
+
+  /* The last buffer has the wrap bit set so the EMAC knows to wrap back
+  to the first buffer. */
+  xTxDescriptors[ NB_TX_BUFFERS - 1 ].U_Status.status = AVR32_TRANSMIT_WRAP | AVR32_TRANSMIT_OK;
+
+  /* Tell the EMAC where to find the descriptors. */
+  AVR32_MACB.rbqp =   ( unsigned portLONG )xRxDescriptors;
+  AVR32_MACB.tbqp =   ( unsigned portLONG )xTxDescriptors;
+
+  /* Enable the copy of data into the buffers, ignore broadcasts,
+  and don't copy FCS. */
+  AVR32_MACB.ncfgr |= (AVR32_MACB_CAF_MASK |  AVR32_MACB_NBC_MASK | AVR32_MACB_NCFGR_DRFCS_MASK);
+
+} 
+/*-----------------------------------------------------------*/
+
+static void prvSetupMACAddress( void )
+{
+  /* Must be written SA1L then SA1H. */
+  AVR32_MACB.sa1b =  ( ( unsigned portLONG ) cMACAddress[ 3 ] << 24 ) |
+                     ( ( unsigned portLONG ) cMACAddress[ 2 ] << 16 ) |
+                     ( ( unsigned portLONG ) cMACAddress[ 1 ] << 8  ) |
+                                             cMACAddress[ 0 ];
+
+  AVR32_MACB.sa1t =  ( ( unsigned portLONG ) cMACAddress[ 5 ] << 8 ) |
+                                             cMACAddress[ 4 ];
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupEMACInterrupt( void )
+{
+  /* Create the semaphore used to trigger the EMAC task. */
+  if (xSemaphore == NULL)
+  {
+    vSemaphoreCreateBinary( xSemaphore );
+  }
+
+  if( xSemaphore )
+  {
+    /* We start by 'taking' the semaphore so the ISR can 'give' it when the
+    first interrupt occurs. */
+    xSemaphoreTake( xSemaphore, emacNO_DELAY );
+    portENTER_CRITICAL();
+    {
+    /* Setup the interrupt for USART0.
+       Register the USART0 interrupt handler to the interrupt controller
+       at interrupt level 2. */
+    INTC_register_interrupt(&vEMAC_ISR, AVR32_MACB_IRQ, INT2);
+
+    /* We want to interrupt on Rx and Tx events. */
+    AVR32_MACB.ier = AVR32_MACB_IER_RCOMP_MASK | AVR32_MACB_IER_TCOMP_MASK;
+    }
+    portEXIT_CRITICAL();
+  }
+}
+
+/*
+ * The following functions are initialisation functions taken from the Atmel
+ * EMAC sample code.
+ */
+static portBASE_TYPE prvProbePHY( void )
+{
+unsigned long mii_status, advertise, lpa, phy_ctrl;
+unsigned long config;
+unsigned long upper, lower,mode;
+unsigned long physID;
+
+  /* Read Phy Identifier register 1 & 2 */
+  lower = vReadPHY(PHY_PHYSID2);
+  upper = vReadPHY(PHY_PHYSID1);
+  /* get Phy ID, ignore Revision */
+  physID = ((upper << 16) & 0xFFFF0000) | (lower & 0xFFF0);
+  /* check if it match config */
+  if (physID == MII_DP83848_ID)
+  {
+    /* read RBR */
+    mode = vReadPHY(PHY_RBR);
+    /* set RMII mode if not done */
+    if ((mode & RBR_RMII) != RBR_RMII)
+    {
+      /* force RMII flag if strap options are wrong */
+      mode |= RBR_RMII;
+    vWritePHY(PHY_RBR,mode);
+    }
+
+    /* set advertise register */
+#if ETHERNET_CONF_AN_ENABLE == 1
+    advertise = ADVERTISE_CSMA | ADVERTISE_ALL;
+#else
+    advertise = ADVERTISE_CSMA;
+    #if ETHERNET_CONF_USE_100MB
+      #if ETHERNET_CONF_USE_FULL_DUPLEX
+        advertise |= ADVERTISE_100FULL;
+      #else
+        advertise |= ADVERTISE_100HALF;
+      #endif
+    #else
+      #if ETHERNET_CONF_USE_FULL_DUPLEX
+        advertise |= ADVERTISE_10FULL;
+      #else
+        advertise |= ADVERTISE_10HALF;
+      #endif
+    #endif
+#endif
+    /* write advertise register */
+    vWritePHY(PHY_ADVERTISE, advertise);
+    /* read Control register */
+    config = vReadPHY(PHY_BMCR);
+    /* read Phy Control register */
+    phy_ctrl = vReadPHY(PHY_PHYCR);
+#if ETHERNET_CONF_AN_ENABLE
+  #if ETHERNET_CONF_AUTO_CROSS_ENABLE
+    /* enable Auto MDIX */
+    phy_ctrl |= PHYCR_MDIX_EN;
+  #else
+    /* disable Auto MDIX */
+    phy_ctrl &= ~PHYCR_MDIX_EN;
+    #if ETHERNET_CONF_CROSSED_LINK
+      /* force direct link = Use crossed RJ45 cable */
+      phy_ctrl &= ~PHYCR_MDIX_FORCE;
+    #else
+      /* force crossed link = Use direct RJ45 cable */
+      phy_ctrl |= PHYCR_MDIX_FORCE;
+    #endif
+  #endif
+  /* reset auto-negociation capability */
+  config |= (BMCR_ANRESTART | BMCR_ANENABLE);
+#else
+  /* disable Auto MDIX */
+  phy_ctrl &= ~PHYCR_MDIX_EN;
+  #if ETHERNET_CONF_CROSSED_LINK
+    /* force direct link = Use crossed RJ45 cable */
+    phy_ctrl &= ~PHYCR_MDIX_FORCE;
+  #else
+    /* force crossed link = Use direct RJ45 cable */
+    phy_ctrl |= PHYCR_MDIX_FORCE;
+  #endif
+  /* clear AN bit */
+  config &= ~BMCR_ANENABLE;
+
+  #if ETHERNET_CONF_USE_100MB
+    config |= BMCR_SPEED100;
+  #else
+    config &= ~BMCR_SPEED100;
+  #endif
+  #if ETHERNET_CONF_USE_FULL_DUPLEX
+    config |= BMCR_FULLDPLX;
+  #else
+    config &= ~BMCR_FULLDPLX;
+  #endif
+#endif
+    /* update Phy ctrl register */
+    vWritePHY(PHY_PHYCR, phy_ctrl);
+
+    /* update ctrl register */
+    vWritePHY(PHY_BMCR, config);
+
+    /* loop while link status isn't OK */
+    do {
+      mii_status = vReadPHY(PHY_BMSR);
+    } while (!(mii_status & BMSR_LSTATUS));
+
+    /* read the LPA configuration of the PHY */
+    lpa = vReadPHY(PHY_LPA);
+
+    /* read the MACB config register */
+    config = AVR32_MACB.ncfgr;
+
+    /* if 100MB needed */
+    if ((lpa & advertise) & (LPA_100HALF | LPA_100FULL))
+    {
+      config |= AVR32_MACB_SPD_MASK;
+    }
+    else
+    {
+      config &= ~(AVR32_MACB_SPD_MASK);
+    }
+
+    /* if FULL DUPLEX needed */
+    if ((lpa & advertise) & (LPA_10FULL | LPA_100FULL))
+    {
+      config |= AVR32_MACB_FD_MASK;
+    }
+    else
+    {
+      config &= ~(AVR32_MACB_FD_MASK);
+    }
+
+    /* write the MACB config register */
+    AVR32_MACB.ncfgr = config;
+
+    return pdPASS;
+  }
+  return pdFAIL;
+}
+
+static unsigned portLONG vReadPHY( unsigned portCHAR ucAddress )
+{
+ unsigned portLONG pulValue;
+
+  /* Enable management port */
+  AVR32_MACB.ncr |= AVR32_MACB_NCR_MPE_MASK;
+
+  /* configure MDIO frame in MAN register */
+  AVR32_MACB.man =  (AVR32_MACB_SOF_MASK & (0x01<
+#elif __ICCAVR32__
+#  include 
+#else
+#  error Unknown compiler
+#endif
+
+#include 
+
+#include "conf_eth.h"
+
+
+/* Receive Transfer descriptor structure */
+typedef struct  _AVR32_RxTdDescriptor {
+  unsigned int addr;
+  union
+  {
+    unsigned int status;
+    struct {
+      unsigned int BroadCast:1;
+      unsigned int MultiCast:1;
+      unsigned int UniCast:1;
+      unsigned int ExternalAdd:1;
+      unsigned int Res1:1;
+      unsigned int Sa1Match:1;
+      unsigned int Sa2Match:1;
+      unsigned int Sa3Match:1;
+      unsigned int Sa4Match:1;
+      unsigned int TypeID:1;
+      unsigned int VlanTag:1;
+      unsigned int PriorityTag:1;
+      unsigned int VlanPriority:3;
+      unsigned int Cfi:1;
+      unsigned int EndOfFrame:1;
+      unsigned int StartOfFrame:1;
+      unsigned int Rxbuf_off:2;
+      unsigned int Res0:1;
+      unsigned int Length:11;
+    }S_Status;
+  }U_Status;
+}AVR32_RxTdDescriptor, *AVR32P_RxTdDescriptor;
+
+
+/* Transmit Transfer descriptor structure */
+typedef struct _AVR32_TxTdDescriptor {
+  unsigned int addr;
+  union
+  {
+    unsigned int status;
+    struct {
+      unsigned int BuffUsed:1;
+      unsigned int Wrap:1;
+      unsigned int TransmitError:1;
+      unsigned int TransmitUnderrun:1;
+      unsigned int BufExhausted:1;
+      unsigned int Res1:10;
+      unsigned int NoCrc:1;
+      unsigned int LastBuff:1;
+      unsigned int Res0:4;
+      unsigned int Length:11;
+    }S_Status;
+  }U_Status;
+}AVR32_TxTdDescriptor, *AVR32P_TxTdDescriptor;
+
+#define AVR32_OWNERSHIP_BIT   0x00000001
+
+/* Receive status defintion */
+#define AVR32_BROADCAST_ADDR  ((unsigned int) (1 << 31))  //* Broadcat address detected
+#define AVR32_MULTICAST_HASH  ((unsigned int) (1 << 30))  //* MultiCast hash match
+#define AVR32_UNICAST_HASH    ((unsigned int) (1 << 29))  //* UniCast hash match
+#define AVR32_EXTERNAL_ADDR   ((unsigned int) (1 << 28))  //* External Address match
+#define AVR32_SA1_ADDR        ((unsigned int) (1 << 26))  //* Specific address 1 match
+#define AVR32_SA2_ADDR        ((unsigned int) (1 << 25))  //* Specific address 2 match
+#define AVR32_SA3_ADDR        ((unsigned int) (1 << 24))  //* Specific address 3 match
+#define AVR32_SA4_ADDR        ((unsigned int) (1 << 23))  //* Specific address 4 match
+#define AVR32_TYPE_ID         ((unsigned int) (1 << 22))  //* Type ID match
+#define AVR32_VLAN_TAG        ((unsigned int) (1 << 21))  //* VLAN tag detected
+#define AVR32_PRIORITY_TAG    ((unsigned int) (1 << 20))  //* PRIORITY tag detected
+#define AVR32_VLAN_PRIORITY   ((unsigned int) (7 << 17))  //* PRIORITY Mask
+#define AVR32_CFI_IND         ((unsigned int) (1 << 16))  //* CFI indicator
+#define AVR32_EOF             ((unsigned int) (1 << 15))  //* EOF
+#define AVR32_SOF             ((unsigned int) (1 << 14))  //* SOF
+#define AVR32_RBF_OFFSET      ((unsigned int) (3 << 12))  //* Receive Buffer Offset Mask
+#define AVR32_LENGTH_FRAME    ((unsigned int) 0x0FFF)     //* Length of frame
+
+/* Transmit Status definition */
+#define AVR32_TRANSMIT_OK     ((unsigned int) (1 << 31))  //*
+#define AVR32_TRANSMIT_WRAP   ((unsigned int) (1 << 30))  //* Wrap bit: mark the last descriptor
+#define AVR32_TRANSMIT_ERR    ((unsigned int) (1 << 29))  //* RLE:transmit error
+#define AVR32_TRANSMIT_UND    ((unsigned int) (1 << 28))  //* Transmit Underrun
+#define AVR32_BUF_EX          ((unsigned int) (1 << 27))  //* Buffers exhausted in mid frame
+#define AVR32_TRANSMIT_NO_CRC ((unsigned int) (1 << 16))  //* No CRC will be appended to the current frame
+#define AVR32_LAST_BUFFER     ((unsigned int) (1 << 15))  //*
+
+#define AVR32_EMAC_CLKEN      0x2
+
+/*
+ * Initialise the EMAC driver.  If successful a semaphore is returned that
+ * is used by the EMAC ISR to indicate that Rx packets have been received.
+ * If the initialisation fails then NULL is returned.
+ */
+xSemaphoreHandle xEMACInit( void );
+
+/*
+ * Send ulLength bytes from pcFrom.  This copies the buffer to one of the
+ * EMAC Tx buffers, then indicates to the EMAC that the buffer is ready.
+ * If lEndOfFrame is true then the data being copied is the end of the frame
+ * and the frame can be transmitted.
+ */
+portLONG lEMACSend( portCHAR *pcFrom, unsigned portLONG ulLength, portLONG lEndOfFrame );
+
+/*
+ * Frames can be read from the EMAC in multiple sections.
+ * Read ulSectionLength bytes from the EMAC receive buffers to pcTo.
+ * ulTotalFrameLength is the size of the entire frame.  Generally vEMACRead
+ * will be repetedly called until the sum of all the ulSectionLenths totals
+ * the value of ulTotalFrameLength.
+ */
+void vEMACRead( portCHAR *pcTo, unsigned portLONG ulSectionLength, unsigned portLONG ulTotalFrameLength );
+
+/*
+ * The EMAC driver and interrupt service routines are defined in different
+ * files as the driver is compiled to THUMB, and the ISR to ARM.  This function
+ * simply passes the semaphore used to communicate between the two.
+ */
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore );
+
+/*
+ * Called by the Tx interrupt, this function traverses the buffers used to
+ * hold the frame that has just completed transmission and marks each as
+ * free again.
+ */
+void vClearEMACTxBuffer( void );
+
+/*
+ * Suspend on a semaphore waiting either for the semaphore to be obtained
+ * or a timeout.  The semaphore is used by the EMAC ISR to indicate that
+ * data has been received and is ready for processing.
+ */
+void vEMACWaitForInput( void );
+
+/*
+ * Return the length of the next frame in the receive buffers.
+ */
+unsigned portLONG ulEMACInputLength( void );
+
+/*
+ * Set the MACB Physical address (SA1B & SA1T registers).
+ */
+void vEMACSetMACAddress(const portCHAR * EMACAddress);
+
+/*
+ * Get the MACB Physical address (SA1B & SA1T registers).
+ */
+void vEMACGetMACAddress(portCHAR * EMACAddress);
+
+#endif
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_EMAC_ISR.c b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_EMAC_ISR.c
new file mode 100644
index 000000000..aaf4b89a9
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/AVR32_EMAC_ISR.c
@@ -0,0 +1,129 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief EMAC abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "semphr.h"
+
+#include "AVR32_EMAC.h"
+#include "AVR32_CONF_EMAC.h"
+
+#include "lwipopts.h"
+
+
+
+
+/*-----------------------------------------------------------*/
+
+/* The semaphore used to signal the arrival of new data to the interface
+task. */
+static xSemaphoreHandle xSemaphore = NULL;
+
+static __attribute__((__noinline__)) portBASE_TYPE prvEMAC_ISR_NonNakedBehaviour( void );
+
+
+/*
+ * The EMAC ISR.  Handles both Tx and Rx complete interrupts.
+ */
+//__attribute__((naked,section (".handlers"))) void vEMAC_ISR( void )
+__attribute__((naked)) void vEMAC_ISR( void )
+{
+ /* This ISR can cause a context switch, so the first statement must be a
+     call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
+     variable declarations. */
+  portENTER_SWITCHING_ISR();
+
+  prvEMAC_ISR_NonNakedBehaviour();
+ /* Exit the ISR.  If a task was woken by either a character being received
+     or transmitted then a context switch will occur. */
+
+  portEXIT_SWITCHING_ISR();
+}
+/*-----------------------------------------------------------*/
+
+static __attribute__((__noinline__)) portBASE_TYPE prvEMAC_ISR_NonNakedBehaviour( void )
+{
+
+  /* Variable definitions can be made now. */
+  volatile unsigned portLONG ulIntStatus, ulEventStatus;
+  portBASE_TYPE xSwitchRequired = pdFALSE;
+  extern void vClearEMACTxBuffer( void );
+
+  /* Find the cause of the interrupt. */
+  ulIntStatus = AVR32_MACB.isr;
+  ulEventStatus = AVR32_MACB.rsr;
+
+  if( ( ulIntStatus & AVR32_MACB_IDR_RCOMP_MASK ) || ( ulEventStatus & AVR32_MACB_REC_MASK ) )
+  {
+    /* A frame has been received, signal the lwIP task so it can process
+    the Rx descriptors. */
+    portENTER_CRITICAL();
+    xSwitchRequired = xSemaphoreGiveFromISR( xSemaphore, pdFALSE );
+    portEXIT_CRITICAL();
+    AVR32_MACB.rsr =  AVR32_MACB_REC_MASK;
+    AVR32_MACB.rsr;
+  }
+
+  if( ulIntStatus & AVR32_MACB_TCOMP_MASK )
+  {
+   /* A frame has been transmitted.  Mark all the buffers used by the
+    frame just transmitted as free again. */
+    vClearEMACTxBuffer();
+    AVR32_MACB.tsr =  AVR32_MACB_TSR_COMP_MASK;
+    AVR32_MACB.tsr;
+  }
+
+  return ( xSwitchRequired );
+}
+
+/*-----------------------------------------------------------*/
+
+void vPassEMACSemaphore( xSemaphoreHandle xCreatedSemaphore )
+{
+  /* Simply store the semaphore that should be used by the ISR. */
+  xSemaphore = xCreatedSemaphore;
+}
+
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/DP83848.h b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/DP83848.h
new file mode 100644
index 000000000..3e9e139b7
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/EMAC/DP83848.h
@@ -0,0 +1,166 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief PHY abstraction layer for AVR32 UC3 on EVK1100.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* DP83848 registers. */
+/*! Generic MII registers. */
+#define PHY_BMCR            0x00        /* Basic mode control register */
+#define PHY_BMSR            0x01        /* Basic mode status register  */
+#define PHY_PHYSID1         0x02        /* PHYS ID 1                   */
+#define PHY_PHYSID2         0x03        /* PHYS ID 2                   */
+#define PHY_ADVERTISE       0x04        /* Advertisement control reg   */
+#define PHY_LPA             0x05        /* Link partner ability reg    */
+
+#if BOARD == EVK1100
+/*! Extended registers for DP83848 */
+#define PHY_RBR             0x17        /* RMII Bypass reg             */
+#define PHY_MICR            0x11        /* Interrupt Control reg       */
+#define PHY_MISR            0x12        /* Interrupt Status reg        */
+#define PHY_PHYCR           0x19        /* Phy CTRL reg                */
+#endif
+
+
+/*! Basic mode control register. */
+#define BMCR_RESV               0x007f  /* Unused...                   */
+#define BMCR_CTST               0x0080  /* Collision test              */
+#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
+#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
+#define BMCR_ISOLATE            0x0400  /* Disconnect PHY from MII     */
+#define BMCR_PDOWN              0x0800  /* Powerdown the PHY           */
+#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
+#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
+#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
+#define BMCR_RESET              0x8000  /* Reset the PHY               */
+
+/*! Basic mode status register. */
+#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
+#define BMSR_JCD                0x0002  /* Jabber detected             */
+#define BMSR_LSTATUS            0x0004  /* Link status                 */
+#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
+#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
+#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
+#define BMSR_RESV               0x00c0  /* Unused...                   */
+#define BMSR_ESTATEN            0x0100  /* Extended Status in R15 */
+#define BMSR_100FULL2           0x0200  /* Can do 100BASE-T2 HDX */
+#define BMSR_100HALF2           0x0400  /* Can do 100BASE-T2 FDX */
+#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
+#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
+#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
+#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
+#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
+
+/*! Advertisement control register. */
+#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
+#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
+#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
+#define ADVERTISE_1000XFULL     0x0020  /* Try for 1000BASE-X full-duplex */
+#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
+#define ADVERTISE_1000XHALF     0x0040  /* Try for 1000BASE-X half-duplex */
+#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
+#define ADVERTISE_1000XPAUSE    0x0080  /* Try for 1000BASE-X pause    */
+#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
+#define ADVERTISE_1000XPSE_ASYM 0x0100  /* Try for 1000BASE-X asym pause */
+#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
+#define ADVERTISE_PAUSE_CAP     0x0400  /* Try for pause               */
+#define ADVERTISE_PAUSE_ASYM    0x0800  /* Try for asymetric pause     */
+#define ADVERTISE_RESV          0x1000  /* Unused...                   */
+#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
+#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
+#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
+
+#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | ADVERTISE_CSMA)
+#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
+                       ADVERTISE_100HALF | ADVERTISE_100FULL)
+
+/*! Link partner ability register. */
+#define LPA_SLCT                0x001f  /* Same as advertise selector  */
+#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
+#define LPA_1000XFULL           0x0020  /* Can do 1000BASE-X full-duplex */
+#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
+#define LPA_1000XHALF           0x0040  /* Can do 1000BASE-X half-duplex */
+#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
+#define LPA_1000XPAUSE          0x0080  /* Can do 1000BASE-X pause     */
+#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
+#define LPA_1000XPAUSE_ASYM     0x0100  /* Can do 1000BASE-X pause asym*/
+#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
+#define LPA_PAUSE_CAP           0x0400  /* Can pause                   */
+#define LPA_PAUSE_ASYM          0x0800  /* Can pause asymetrically     */
+#define LPA_RESV                0x1000  /* Unused...                   */
+#define LPA_RFAULT              0x2000  /* Link partner faulted        */
+#define LPA_LPACK               0x4000  /* Link partner acked us       */
+#define LPA_NPAGE               0x8000  /* Next page bit               */
+
+#define LPA_DUPLEX    (LPA_10FULL | LPA_100FULL)
+#define LPA_100       (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+
+#if BOARD == EVK1100
+/*! RMII Bypass Register */
+#define RBR_RMII                 0x0020  /* RMII Mode          */
+/*! Interrupt Ctrl Register */
+#define MICR_INTEN               0x0002  /* Enable interrupts  */
+#define MICR_INTOE               0x0001  /* Enable INT output  */
+/*! Interrupt Status Register */
+#define MISR_ED_INT_EN           0x0040  /* Energy Detect enabled      */
+#define MISR_LINK_INT_EN         0x0020  /* Link status change enabled */
+#define MISR_SPD_INT_EN          0x0010  /* Speed change enabled       */
+#define MISR_DP_INT_EN           0x0008  /* Duplex mode change enabled */
+#define MISR_ANC_INT_EN          0x0004  /* Auto-Neg complete enabled  */
+#define MISR_FHF_INT_EN          0x0002  /* False Carrier enabled      */
+#define MISR_RHF_INT_EN          0x0001  /* Receive Error enabled      */
+#define MISR_ED_INT              0x4000  /* Energy Detect      */
+#define MISR_LINK_INT            0x2000  /* Link status change */
+#define MISR_SPD_INT             0x1000  /* Speed change       */
+#define MISR_DP_INT              0x0800  /* Duplex mode change */
+#define MISR_ANC_INT             0x0400  /* Auto-Neg complete  */
+#define MISR_FHF_INT             0x0200  /* False Carrier      */
+#define MISR_RHF_INT             0x0100  /* Receive Error      */
+/*! Phy Ctrl Register */
+#define PHYCR_MDIX_EN            0x8000  /* Enable Auto MDIX   */
+#define PHYCR_MDIX_FORCE         0x4000  /* Force MDIX crossed */
+#endif
+
+/*! PHY ID */
+#define MII_DP83848_ID           0x20005C90	/* 0x00225541 */
+
+/*! PHY Address */
+#define DP83848_PHY_ADDR         0x01
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.c b/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.c
new file mode 100644
index 000000000..f97902025
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.c
@@ -0,0 +1,195 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief ethernet management for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+
+#include 
+
+#include "conf_eth.h"
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo program include files. */
+#include "partest.h"
+#include "serial.h"
+
+
+/* ethernet includes */
+#include "ethernet.h"
+#include "AVR32_EMAC.h"
+
+#if (HTTP_USED == 1)
+  #include "BasicWEB.h"
+#endif
+
+#if (TFTP_USED == 1)
+  #include "BasicTFTP.h"
+#endif
+
+#if (SMTP_USED == 1)
+  #include "BasicSMTP.h"
+#endif
+
+/* lwIP includes */
+#include "lwip/sys.h"
+#include "lwip/api.h" 
+#include "lwip/tcpip.h"
+#include "lwip/memp.h" 
+#include "lwip/stats.h"
+#include "netif/loopif.h"
+
+
+//_____ M A C R O S ________________________________________________________
+
+
+//_____ D E F I N I T I O N S ______________________________________________
+
+/* global variable containing MAC Config (hw addr, IP, GW, ...) */
+struct netif EMAC_if;
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+/* Initialisation required by lwIP. */
+static void prvlwIPInit( void );
+
+/* Initialisation of ethernet interfaces by reading config file */
+static void prvEthernetConfigureInterface(void * param);
+
+
+/*! \brief create ethernet task, for ethernet management.
+ *
+ *  \param uxPriority   Input. priority for the task, it should be low
+ *
+ */
+void vStartEthernetTask( unsigned portBASE_TYPE uxPriority )
+{
+  /* Setup lwIP. */
+  prvlwIPInit();
+
+#if (HTTP_USED == 1)
+  /* Create the WEB server task.  This uses the lwIP RTOS abstraction layer.*/
+  sys_thread_new( vBasicWEBServer, ( void * ) NULL, ethWEBSERVER_PRIORITY );
+#endif
+
+#if (TFTP_USED == 1)
+  /* Create the TFTP server task.  This uses the lwIP RTOS abstraction layer.*/
+  sys_thread_new( vBasicTFTPServer, ( void * ) NULL, ethTFTPSERVER_PRIORITY );
+#endif
+
+#if (SMTP_USED == 1)
+  /* Create the SMTP Host task.  This uses the lwIP RTOS abstraction layer.*/
+  sys_thread_new( vBasicSMTPHost, ( void * ) NULL, ethSMTPHOST_PRIORITY );
+#endif
+
+}
+
+
+/*!
+ *  \brief start lwIP layer.
+ */
+static void prvlwIPInit( void )
+{
+	/* Initialize lwIP and its interface layer. */
+	#if LWIP_STATS
+		stats_init();
+	#endif
+
+	sys_init();
+	mem_init();
+	memp_init();
+	pbuf_init();
+	netif_init();
+	
+	/* once TCP stack has been initalized, set hw and IP parameters, initialize MACB too */
+	tcpip_init( prvEthernetConfigureInterface, NULL );
+}
+
+/*!
+ *  \brief set ethernet config 
+ */
+static void prvEthernetConfigureInterface(void * param)
+{
+struct ip_addr xIpAddr, xNetMask, xGateway;
+extern err_t ethernetif_init( struct netif *netif );
+portCHAR MacAddress[6];
+
+   /* Default MAC addr. */
+   MacAddress[0] = emacETHADDR0;
+   MacAddress[1] = emacETHADDR1;
+   MacAddress[2] = emacETHADDR2;
+   MacAddress[3] = emacETHADDR3;
+   MacAddress[4] = emacETHADDR4;
+   MacAddress[5] = emacETHADDR5;
+   
+   /* pass the EMAC address to AVR32_EMAC module */
+   vEMACSetMACAddress( MacAddress );
+   
+   /* set MAC hardware address length to be used by lwIP */
+   EMAC_if.hwaddr_len = 6;
+   
+   /* set MAC hardware address to be used by lwIP */
+   memcpy( EMAC_if.hwaddr, MacAddress, EMAC_if.hwaddr_len );
+   
+   /* Default ip addr. */
+   IP4_ADDR( &xIpAddr,emacIPADDR0,emacIPADDR1,emacIPADDR2,emacIPADDR3 );
+   
+   /* Default Subnet mask. */
+   IP4_ADDR( &xNetMask,emacNET_MASK0,emacNET_MASK1,emacNET_MASK2,emacNET_MASK3 );
+   
+   /* Default Gw addr. */
+   IP4_ADDR( &xGateway,emacGATEWAY_ADDR0,emacGATEWAY_ADDR1,emacGATEWAY_ADDR2,emacGATEWAY_ADDR3 );
+   
+   /* add data to netif */
+   netif_add( &EMAC_if, &xIpAddr, &xNetMask, &xGateway, NULL, ethernetif_init, tcpip_input );
+   
+   /* make it the default interface */
+   netif_set_default( &EMAC_if );
+   
+   /* bring it up */
+   netif_set_up( &EMAC_if );
+}
+
+
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.h b/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.h
new file mode 100644
index 000000000..06d111164
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/ethernet.h
@@ -0,0 +1,59 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief ethernet headers for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef ETHERNET_H
+#define ETHERNET_H
+
+/*! \brief create ethernet task, for ethernet management.
+ *
+ *  \param uxPriority   Input. priority for the task, it should be low
+ *
+ */
+void vStartEthernetTask( unsigned portBASE_TYPE uxPriority );
+
+
+
+#endif
+
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cc.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cc.h
new file mode 100644
index 000000000..36e220534
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cc.h
@@ -0,0 +1,75 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CC_H__
+#define __CC_H__
+
+#include "cpu.h"
+
+typedef unsigned   char    u8_t;
+typedef signed     char    s8_t;
+typedef unsigned   short   u16_t;
+typedef signed     short   s16_t;
+typedef unsigned   long    u32_t;
+typedef signed     long    s32_t;
+typedef u32_t mem_ptr_t;
+typedef int sys_prot_t;
+
+/*! Defines for the LWIP_STATS feature. */
+#define S16_F   "d"
+#define U16_F   "d"
+#define X16_F   "d"
+#define X32_F   "d"
+#define U32_F   "d"
+#define S32_F   "d"
+
+#define LWIP_PLATFORM_DIAG(x)   
+#define LWIP_PLATFORM_ASSERT(x)   
+
+/* */
+#define PACK_STRUCT_BEGIN
+#define PACK_STRUCT_STRUCT __attribute__ ((__packed__))
+#define PACK_STRUCT_END
+#define PACK_STRUCT_FIELD(x) x
+
+#endif /* __CC_H__ */
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cpu.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cpu.h
new file mode 100644
index 000000000..81aa3374a
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/cpu.h
@@ -0,0 +1,50 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __CPU_H__
+#define __CPU_H__
+
+#define BYTE_ORDER BIG_ENDIAN
+
+#endif /* __CPU_H__ */
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/init.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/init.h
new file mode 100644
index 000000000..068ee7622
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/init.h
@@ -0,0 +1,57 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef __ARCH_INIT_H__
+#define __ARCH_INIT_H__
+
+#define TCPIP_INIT_DONE(arg)  tcpip_init_done(arg)
+
+void tcpip_init_done(void *);
+int wait_for_tcpip_init(void);
+
+#endif /* __ARCH_INIT_H__ */
+
+
+
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/lib.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/lib.h
new file mode 100644
index 000000000..23dc3f8ee
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/lib.h
@@ -0,0 +1,50 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __LIB_H__
+#define __LIB_H__
+
+#include 
+
+
+#endif /* __LIB_H__ */
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/perf.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/perf.h
new file mode 100644
index 000000000..4e5055a03
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/perf.h
@@ -0,0 +1,50 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PERF_H__
+#define __PERF_H__
+
+#define PERF_START    /* null definition */
+#define PERF_STOP(x)  /* null definition */
+
+#endif /* __PERF_H__ */
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/sys_arch.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/sys_arch.h
new file mode 100644
index 000000000..81b300241
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/arch/sys_arch.h
@@ -0,0 +1,60 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SYS_RTXC_H__
+#define __SYS_RTXC_H__
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+#define SYS_MBOX_NULL (xQueueHandle)0
+#define SYS_SEM_NULL  (xSemaphoreHandle)0
+
+typedef xSemaphoreHandle sys_sem_t;
+typedef xQueueHandle sys_mbox_t;
+typedef xTaskHandle sys_thread_t;
+
+#endif /* __SYS_RTXC_H__ */
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/ethernetif.c b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/ethernetif.c
new file mode 100644
index 000000000..17d5acf34
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/ethernetif.c
@@ -0,0 +1,384 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+
+/*
+ * This file is a skeleton for developing Ethernet network interface
+ * drivers for lwIP. Add code to the low_level functions and do a
+ * search-and-replace for the word "ethernetif" to replace it with
+ * something that better describes your network interface.
+ */
+
+#include "lwip/opt.h"
+#include "lwip/def.h"
+#include "lwip/mem.h"
+#include "lwip/pbuf.h"
+#include "lwip/sys.h"
+#include 
+
+#include "conf_eth.h"
+
+#include "netif/etharp.h"
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "AVR32_EMAC.h"
+#include "AVR32_CONF_EMAC.h"
+
+#define netifMTU              ( 1500 )
+#define netifGUARD_BLOCK_TIME       ( 250 )
+#define IFNAME0 'e'
+#define IFNAME1 'm'
+
+
+struct ethernetif {
+  struct eth_addr *ethaddr;
+  /* Add whatever per-interface state that is needed here. */
+};
+
+static const struct eth_addr ethbroadcast = {{0xff,0xff,0xff,0xff,0xff,0xff}};
+
+/* Forward declarations. */
+void  ethernetif_input(void * );
+static err_t ethernetif_output(struct netif *netif, struct pbuf *p,
+             struct ip_addr *ipaddr);
+static struct netif *xNetIf = NULL;
+
+
+static void
+low_level_init(struct netif *netif)
+{
+//  struct ethernetif *ethernetif = netif->state;
+  unsigned portBASE_TYPE uxPriority;
+
+  /* maximum transfer unit */
+  netif->mtu = netifMTU;
+  
+  /* broadcast capability */
+  netif->flags = NETIF_FLAG_BROADCAST;
+ 
+  /* Do whatever else is needed to initialize interface. */  
+  xNetIf = netif;
+
+  /* Initialise the EMAC.  This routine contains code that polls status bits.
+  If the Ethernet cable is not plugged in then this can take a considerable
+  time.  To prevent this starving lower priority tasks of processing time we
+  lower our priority prior to the call, then raise it back again once the
+  initialisation is complete. */
+  uxPriority = uxTaskPriorityGet( NULL );
+  vTaskPrioritySet( NULL, tskIDLE_PRIORITY );
+  while( xEMACInit() == NULL )
+  {
+    __asm( "NOP" );
+  }
+  vTaskPrioritySet( NULL, uxPriority );
+
+  /* Create the task that handles the EMAC. */
+  // xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", netifINTERFACE_TASK_STACK_SIZE, NULL, netifINTERFACE_TASK_PRIORITY, NULL );
+  sys_thread_new( ethernetif_input, NULL, netifINTERFACE_TASK_PRIORITY );
+}
+
+/*
+ * low_level_output():
+ *
+ * Should do the actual transmission of the packet. The packet is
+ * contained in the pbuf that is passed to the function. This pbuf
+ * might be chained.
+ *
+ */
+
+static err_t
+low_level_output(struct netif *netif, struct pbuf *p)
+{
+struct pbuf *q;
+static xSemaphoreHandle xTxSemaphore = NULL;
+err_t xReturn = ERR_OK;
+
+  /* Parameter not used. */
+  ( void ) netif;
+
+  if( xTxSemaphore == NULL )
+  {
+    vSemaphoreCreateBinary( xTxSemaphore );
+  }
+
+  #if ETH_PAD_SIZE
+    pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+  #endif
+
+  /* Access to the EMAC is guarded using a semaphore. */
+  if( xSemaphoreTake( xTxSemaphore, netifGUARD_BLOCK_TIME ) )
+  {
+    for( q = p; q != NULL; q = q->next )
+    {
+      /* Send the data from the pbuf to the interface, one pbuf at a
+      time. The size of the data in each pbuf is kept in the ->len
+      variable.  if q->next == NULL then this is the last pbuf in the
+      chain. */
+      if( !lEMACSend( q->payload, q->len, ( q->next == NULL ) ) )
+      {
+        xReturn = ~ERR_OK;
+      }
+    }
+
+        xSemaphoreGive( xTxSemaphore );
+  }
+  
+
+  #if ETH_PAD_SIZE
+    pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+  #endif
+
+  #if LINK_STATS
+    lwip_stats.link.xmit++;
+  #endif /* LINK_STATS */
+
+    return xReturn;
+}
+
+/*
+ * low_level_input():
+ *
+ * Should allocate a pbuf and transfer the bytes of the incoming
+ * packet from the interface into the pbuf.
+ *
+ */
+
+static struct pbuf *
+low_level_input(struct netif *netif) {
+struct pbuf         *p = NULL;
+struct pbuf         *q;
+u16_t               len = 0;
+static xSemaphoreHandle xRxSemaphore = NULL;
+
+  /* Parameter not used. */
+  ( void ) netif;
+
+  if( xRxSemaphore == NULL )
+  {
+    vSemaphoreCreateBinary( xRxSemaphore );
+  }
+
+  /* Access to the emac is guarded using a semaphore. */
+  if( xSemaphoreTake( xRxSemaphore, netifGUARD_BLOCK_TIME ) )
+  {
+    /* Obtain the size of the packet. */
+    len = ulEMACInputLength();
+
+    if( len )
+    {
+      #if ETH_PAD_SIZE
+        len += ETH_PAD_SIZE;    /* allow room for Ethernet padding */
+      #endif
+  
+      /* We allocate a pbuf chain of pbufs from the pool. */
+      p = pbuf_alloc( PBUF_RAW, len, PBUF_POOL );
+  
+      if( p != NULL )
+      {
+        #if ETH_PAD_SIZE
+          pbuf_header( p, -ETH_PAD_SIZE );    /* drop the padding word */
+        #endif
+  
+        /* Let the driver know we are going to read a new packet. */
+        vEMACRead( NULL, 0, len );
+  
+        /* We iterate over the pbuf chain until we have read the entire
+        packet into the pbuf. */
+        for( q = p; q != NULL; q = q->next )
+        {
+          /* Read enough bytes to fill this pbuf in the chain. The
+          available data in the pbuf is given by the q->len variable. */
+          vEMACRead( q->payload, q->len, len );
+        }
+  
+        #if ETH_PAD_SIZE
+          pbuf_header( p, ETH_PAD_SIZE );     /* reclaim the padding word */
+        #endif
+        #if LINK_STATS
+          lwip_stats.link.recv++;
+        #endif /* LINK_STATS */
+      }
+      else
+      {
+        #if LINK_STATS
+          lwip_stats.link.memerr++;
+          lwip_stats.link.drop++;
+        #endif /* LINK_STATS */
+      }
+    }
+    xSemaphoreGive( xRxSemaphore );
+  }
+
+  return p;
+}
+
+/*
+ * ethernetif_output():
+ *
+ * This function is called by the TCP/IP stack when an IP packet
+ * should be sent. It calls the function called low_level_output() to
+ * do the actual transmission of the packet.
+ *
+ */
+
+static err_t
+ethernetif_output(struct netif *netif, struct pbuf *p,
+      struct ip_addr *ipaddr)
+{
+  
+ /* resolve hardware address, then send (or queue) packet */
+  return etharp_output(netif, ipaddr, p);
+ 
+}
+
+/*
+ * ethernetif_input():
+ *
+ * This function should be called when a packet is ready to be read
+ * from the interface. It uses the function low_level_input() that
+ * should handle the actual reception of bytes from the network
+ * interface.
+ *
+ */
+
+void ethernetif_input( void * pvParameters )
+{
+struct ethernetif   *ethernetif;
+struct eth_hdr      *ethhdr;
+struct pbuf         *p;
+
+  ( void ) pvParameters;
+
+  for( ;; )  {
+   
+    ethernetif = xNetIf->state;
+    do
+    {
+      ethernetif = xNetIf->state;
+
+      /* move received packet into a new pbuf */
+      p = low_level_input( xNetIf );
+
+      if( p == NULL )
+      {
+        /* No packet could be read.  Wait a for an interrupt to tell us
+        there is more data available. */
+        vEMACWaitForInput();
+      }
+
+    } while( p == NULL );
+
+    /* points to packet payload, which starts with an Ethernet header */
+    ethhdr = p->payload;
+  
+    #if LINK_STATS
+      lwip_stats.link.recv++;
+    #endif /* LINK_STATS */
+  
+    ethhdr = p->payload;
+  
+    switch( htons( ethhdr->type ) )
+    {
+      /* IP packet? */
+      case ETHTYPE_IP:
+        /* update ARP table */
+        etharp_ip_input( xNetIf, p );
+  
+        /* skip Ethernet header */
+        pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) );
+  
+        /* pass to network layer */
+        xNetIf->input( p, xNetIf );
+        break;
+  
+      case ETHTYPE_ARP:
+        /* pass p to ARP module */
+        etharp_arp_input( xNetIf, ethernetif->ethaddr, p );
+        break;
+  
+      default:
+        pbuf_free( p );
+        p = NULL;
+        break;
+    }
+  }
+}
+
+static void
+arp_timer(void *arg)
+{
+  etharp_tmr();
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+}
+
+/*
+ * ethernetif_init():
+ *
+ * Should be called at the beginning of the program to set up the
+ * network interface. It calls the function low_level_init() to do the
+ * actual setup of the hardware.
+ *
+ */
+extern struct netif EMAC_if;
+err_t
+ethernetif_init(struct netif *netif)
+{
+  struct ethernetif *ethernetif;
+  int i;
+    
+  ethernetif = (struct ethernetif *)mem_malloc(sizeof(struct ethernetif));
+  
+  if (ethernetif == NULL)
+  {
+    LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
+    return ERR_MEM;
+  }
+  
+  netif->state = ethernetif;
+  netif->name[0] = IFNAME0;
+  netif->name[1] = IFNAME1;
+  netif->output = ethernetif_output;
+  netif->linkoutput = low_level_output;
+  
+  for(i = 0; i < 6; i++) netif->hwaddr[i] = EMAC_if.hwaddr[i];
+  
+  low_level_init(netif);
+
+  etharp_init();
+
+  sys_timeout(ARP_TMR_INTERVAL, arp_timer, NULL);
+
+  return ERR_OK;
+}
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwip/opt.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwip/opt.h
new file mode 100644
index 000000000..2d84d6a56
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwip/opt.h
@@ -0,0 +1,724 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved. 
+ * 
+ * Redistribution and use in source and binary forms, with or without modification, 
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *    derived from this software without specific prior written permission. 
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED 
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT 
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ * 
+ * Author: Adam Dunkels 
+ *
+ */
+#ifndef __LWIP_OPT_H__
+#define __LWIP_OPT_H__
+
+/* Include user defined options first */
+#include "lwipopts.h"
+#include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT            0
+#endif
+
+#ifndef NO_SYS
+#define NO_SYS                          0
+#endif
+/* ---------- Memory options ---------- */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC                 0
+#endif
+
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT                   1
+#endif
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#ifndef MEM_SIZE
+#define MEM_SIZE                        1600
+#endif
+
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK       0
+#endif
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF                   16
+#endif
+
+/* Number of raw connection PCBs */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB                4
+#endif
+
+/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+   per active UDP "connection". */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB                4
+#endif
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB                5
+#endif
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN         8
+#endif
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG                16
+#endif
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT            3
+#endif
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF                 2
+#endif
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN                4
+#endif
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#ifndef MEMP_NUM_API_MSG
+#define MEMP_NUM_API_MSG                8
+#endif
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#ifndef MEMP_NUM_TCPIP_MSG
+#define MEMP_NUM_TCPIP_MSG              8
+#endif
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE                  16
+#endif
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE               128
+#endif
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. Defaults to 14 for Ethernet. */
+
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN                  14
+#endif
+
+
+
+/* ---------- ARP options ---------- */
+
+/** Number of active hardware address, IP address pairs cached */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE                  10
+#endif
+
+/**
+ * If enabled, outgoing packets are queued during hardware address
+ * resolution.
+ *
+ * This feature has not stabilized yet. Single-packet queueing is
+ * believed to be stable, multi-packet queueing is believed to
+ * clash with the TCP segment queueing.
+ * 
+ * As multi-packet-queueing is currently disabled, enabling this
+ * _should_ work, but we need your testing feedback on lwip-users.
+ *
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING                    1
+#endif
+
+/* This option is deprecated */
+#ifdef ETHARP_QUEUE_FIRST
+#error ETHARP_QUEUE_FIRST option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* This option is removed to comply with the ARP standard */
+#ifdef ETHARP_ALWAYS_INSERT
+#error ETHARP_ALWAYS_INSERT option is deprecated. Remove it from your lwipopts.h.
+#endif
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#ifndef IP_FORWARD
+#define IP_FORWARD                      0
+#endif
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#ifndef IP_OPTIONS
+#define IP_OPTIONS                      1
+#endif
+
+/** IP reassembly and segmentation. Even if they both deal with IP
+ *  fragments, note that these are orthogonal, one dealing with incoming
+ *  packets, the other with outgoing packets
+ */
+
+/** Reassemble incoming fragmented IP packets */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY                   1
+#endif
+
+/** Fragment outgoing IP packets if their size exceeds MTU */
+#ifndef IP_FRAG
+#define IP_FRAG                         1
+#endif
+
+/* IP reassemly default age in seconds */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE 3
+#endif
+
+/* IP reassembly buffer size (minus IP header) */
+#ifndef IP_REASS_BUFSIZE
+#define IP_REASS_BUFSIZE 5760
+#endif
+
+/* Assumed max MTU on any interface for IP frag buffer */
+#ifndef IP_FRAG_MAX_MTU
+#define IP_FRAG_MAX_MTU 1500
+#endif
+
+/** Global default value for Time To Live used by transport layers. */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL                  255
+#endif
+
+/* ---------- ICMP options ---------- */
+
+#ifndef ICMP_TTL
+#define ICMP_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/* ---------- RAW options ---------- */
+
+#ifndef LWIP_RAW
+#define LWIP_RAW                        1
+#endif
+
+#ifndef RAW_TTL
+#define RAW_TTL                        (IP_DEFAULT_TTL)
+#endif
+
+/* ---------- DHCP options ---------- */
+
+#ifndef LWIP_DHCP
+#define LWIP_DHCP                       0
+#endif
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK             1
+#endif
+
+/* ---------- SNMP options ---------- */
+/** @note UDP must be available for SNMP transport */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP                       0
+#endif
+
+/** @note At least one request buffer is required.  */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS        1
+#endif
+
+/** @note At least one trap destination is required */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS          1
+#endif
+
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB                0
+#endif
+
+/* ---------- UDP options ---------- */
+#ifndef LWIP_UDP
+#define LWIP_UDP                        1
+#endif
+
+#ifndef UDP_TTL
+#define UDP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+/* ---------- TCP options ---------- */
+#ifndef LWIP_TCP
+#define LWIP_TCP                        1
+#endif
+
+#ifndef TCP_TTL
+#define TCP_TTL                         (IP_DEFAULT_TTL)
+#endif
+
+#ifndef TCP_WND
+#define TCP_WND                         2048
+#endif 
+
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX                      12
+#endif
+
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX                   6
+#endif
+
+
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ                 1
+#endif
+
+/* TCP Maximum segment size. */
+#ifndef TCP_MSS
+#define TCP_MSS                         128 /* A *very* conservative default. */
+#endif
+
+/* TCP sender buffer space (bytes). */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF                     256
+#endif
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN                4 * TCP_SND_BUF/TCP_MSS
+#endif
+
+
+/* Maximum number of retransmissions of data segments. */
+
+/* Maximum number of retransmissions of SYN segments. */
+
+/* TCP writable space (bytes). This must be less than or equal
+   to TCP_SND_BUF. It is the amount of space which must be
+   available in the tcp snd_buf for select to return writable */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT                    TCP_SND_BUF/2
+#endif
+
+/* Support loop interface (127.0.0.1) */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF                0
+#endif
+
+#ifndef LWIP_EVENT_API
+#define LWIP_EVENT_API                  0
+#define LWIP_CALLBACK_API               1
+#else 
+#define LWIP_EVENT_API                  1
+#define LWIP_CALLBACK_API               0
+#endif 
+
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS             1
+#endif
+
+
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO               1
+#endif
+
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO              1
+#endif
+
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO                 1
+#endif
+
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO             1
+#endif
+
+
+/* ---------- Socket Options ---------- */
+/* Enable SO_REUSEADDR and SO_REUSEPORT options */ 
+#ifdef SO_REUSE
+/* I removed the lot since this was an ugly hack. It broke the raw-API.
+   It also came with many ugly goto's, Christiaan Simons. */
+#error "SO_REUSE currently unavailable, this was a hack"
+#endif                                                                        
+
+
+/* ---------- Statistics options ---------- */
+#ifndef LWIP_STATS
+#define LWIP_STATS                      1
+#endif
+
+#if LWIP_STATS
+
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+#ifndef LINK_STATS
+#define LINK_STATS  1
+#endif
+
+#ifndef IP_STATS
+#define IP_STATS    1
+#endif
+
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS    1
+#endif
+
+#ifndef ICMP_STATS
+#define ICMP_STATS  1
+#endif
+
+#ifndef UDP_STATS
+#define UDP_STATS   1
+#endif
+
+#ifndef TCP_STATS
+#define TCP_STATS   1
+#endif
+
+#ifndef MEM_STATS
+#define MEM_STATS   1
+#endif
+
+#ifndef MEMP_STATS
+#define MEMP_STATS  1
+#endif
+
+#ifndef PBUF_STATS
+#define PBUF_STATS  1
+#endif
+
+#ifndef SYS_STATS
+#define SYS_STATS   1
+#endif
+
+#ifndef RAW_STATS
+#define RAW_STATS   0
+#endif
+
+#else
+
+#define LINK_STATS  0
+#define IP_STATS    0
+#define IPFRAG_STATS    0
+#define ICMP_STATS  0
+#define UDP_STATS   0
+#define TCP_STATS   0
+#define MEM_STATS   0
+#define MEMP_STATS  0
+#define PBUF_STATS  0
+#define SYS_STATS   0
+#define RAW_STATS   0
+#define LWIP_STATS_DISPLAY  0
+
+#endif /* LWIP_STATS */
+
+/* ---------- PPP options ---------- */
+
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT                     0      /* Set for PPP */
+#endif
+
+#if PPP_SUPPORT 
+
+#define NUM_PPP                         1      /* Max PPP sessions. */
+
+
+
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT                     0      /* Set for PAP. */
+#endif
+
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT                    0      /* Set for CHAP. */
+#endif
+
+#define MSCHAP_SUPPORT                  0      /* Set for MSCHAP (NOT FUNCTIONAL!) */
+#define CBCP_SUPPORT                    0      /* Set for CBCP (NOT FUNCTIONAL!) */
+#define CCP_SUPPORT                     0      /* Set for CCP (NOT FUNCTIONAL!) */
+
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT                      0      /* Set for VJ header compression. */
+#endif
+
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT                     0      /* Set for MD5 (see also CHAP) */
+#endif
+
+
+/*
+ * Timeouts.
+ */
+#define FSM_DEFTIMEOUT                  6       /* Timeout time in seconds */
+#define FSM_DEFMAXTERMREQS              2       /* Maximum Terminate-Request transmissions */
+#define FSM_DEFMAXCONFREQS              10      /* Maximum Configure-Request transmissions */
+#define FSM_DEFMAXNAKLOOPS              5       /* Maximum number of nak loops */
+
+#define UPAP_DEFTIMEOUT                 6       /* Timeout (seconds) for retransmitting req */
+#define UPAP_DEFREQTIME                 30      /* Time to wait for auth-req from peer */
+
+#define CHAP_DEFTIMEOUT                 6       /* Timeout time in seconds */
+#define CHAP_DEFTRANSMITS               10      /* max # times to send challenge */
+
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#if 1
+#define LCP_ECHOINTERVAL                0
+#else
+#define LCP_ECHOINTERVAL                10
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#define LCP_MAXECHOFAILS                3
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#define PPP_MAXIDLEFLAG                 100
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ *    limits.  See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ *    of living in lcp.h)
+ */
+#define PPP_MTU                         1500     /* Default MTU (size of Info field) */
+#if 0
+#define PPP_MAXMTU  65535 - (PPP_HDRLEN + PPP_FCSLEN)
+#else
+#define PPP_MAXMTU                      1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU                      64
+#define PPP_MRU                         1500     /* default MRU = max length of info field */
+#define PPP_MAXMRU                      1500     /* Largest MRU we allow */
+#define PPP_DEFMRU                      296             /* Try for this */
+#define PPP_MINMRU                      128             /* No MRUs below this */
+
+
+#define MAXNAMELEN                      256     /* max length of hostname or name for auth */
+#define MAXSECRETLEN                    256     /* max length of password or secret */
+
+#endif /* PPP_SUPPORT */
+
+/* checksum options - set to zero for hardware checksum support */
+
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP                 1
+#endif
+ 
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP                1
+#endif
+ 
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP                1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP               1
+#endif
+ 
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP              1
+#endif
+
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP              1
+#endif
+
+/* Debugging options all default to off */
+
+#ifndef DBG_TYPES_ON
+#define DBG_TYPES_ON                    0
+#endif
+
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG                    DBG_OFF
+#endif
+
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG                      DBG_OFF
+#endif
+
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG                   DBG_OFF
+#endif
+
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG                   DBG_OFF
+#endif
+
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG                   DBG_OFF
+#endif
+
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef INET_DEBUG
+#define INET_DEBUG                      DBG_OFF
+#endif
+
+#ifndef IP_DEBUG
+#define IP_DEBUG                        DBG_OFF
+#endif
+
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG                  DBG_OFF
+#endif
+
+#ifndef RAW_DEBUG
+#define RAW_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEM_DEBUG
+#define MEM_DEBUG                       DBG_OFF
+#endif
+
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SYS_DEBUG
+#define SYS_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_DEBUG
+#define TCP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG                 DBG_OFF
+#endif
+
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG                    DBG_OFF
+#endif
+
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_REXMIT_DEBUG
+#define TCP_REXMIT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG                  DBG_OFF
+#endif
+
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG                DBG_OFF
+#endif
+
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG                   DBG_OFF
+#endif
+
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG                  DBG_OFF
+#endif
+
+#ifndef UDP_DEBUG
+#define UDP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG                     DBG_OFF
+#endif
+
+#ifndef PPP_DEBUG 
+#define PPP_DEBUG                       DBG_OFF
+#endif
+
+#ifndef SLIP_DEBUG 
+#define SLIP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef DHCP_DEBUG 
+#define DHCP_DEBUG                      DBG_OFF
+#endif
+
+#ifndef SNMP_MSG_DEBUG 
+#define SNMP_MSG_DEBUG                  DBG_OFF
+#endif
+
+#ifndef SNMP_MIB_DEBUG 
+#define SNMP_MIB_DEBUG                  DBG_OFF
+#endif
+
+#ifndef DBG_MIN_LEVEL
+#define DBG_MIN_LEVEL                   DBG_LEVEL_OFF
+#endif
+
+#endif /* __LWIP_OPT_H__ */
+
+
+
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwipopts.h b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwipopts.h
new file mode 100644
index 000000000..d8d22e766
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/lwipopts.h
@@ -0,0 +1,228 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP configuration for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+
+#ifndef __LWIPOPTS_H__
+#define __LWIPOPTS_H__
+
+/* Include user defined options first */
+#include "conf_eth.h"
+// #include "lwip/debug.h"
+
+/* Define default values for unconfigured parameters. */
+#define LWIP_NOASSERT 1 // To suppress some errors for now (no debug output)
+
+/* These two control is reclaimer functions should be compiled
+   in. Should always be turned on (1). */
+#define MEM_RECLAIM             1
+#define MEMP_RECLAIM            1
+
+
+/* Platform specific locking */
+
+/*
+ * enable SYS_LIGHTWEIGHT_PROT in lwipopts.h if you want inter-task protection
+ * for certain critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#define SYS_LIGHTWEIGHT_PROT            1
+
+/* ---------- Memory options ---------- */
+// #define MEM_LIBC_MALLOC                 0
+
+/* MEM_ALIGNMENT: should be set to the alignment of the CPU for which
+   lwIP is compiled. 4 byte alignment -> define MEM_ALIGNMENT to 4, 2
+   byte alignment -> define MEM_ALIGNMENT to 2. */
+#define MEM_ALIGNMENT           4
+
+/* MEM_SIZE: the size of the heap memory. If the application will send
+a lot of data that needs to be copied, this should be set high. */
+#define MEM_SIZE                3 * 1024
+
+// #define MEMP_SANITY_CHECK       1
+
+/* MEMP_NUM_PBUF: the number of memp struct pbufs. If the application
+   sends a lot of data out of ROM (or other static memory), this
+   should be set high. */
+#define MEMP_NUM_PBUF           6
+
+/* Number of raw connection PCBs */
+#define MEMP_NUM_RAW_PCB                1
+
+#if (TFTP_USED == 1)
+  /* ---------- UDP options ---------- */
+  #define LWIP_UDP                1
+  #define UDP_TTL                 255
+  /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+     per active UDP "connection". */
+
+  #define MEMP_NUM_UDP_PCB        1
+#else
+  /* ---------- UDP options ---------- */
+  #define LWIP_UDP                0
+  #define UDP_TTL                 0
+  /* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+     per active UDP "connection". */
+
+  #define MEMP_NUM_UDP_PCB        0
+#endif
+
+/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB        14
+/* MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP
+   connections. */
+#define MEMP_NUM_TCP_PCB_LISTEN 2
+/* MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP
+   segments. */
+#define MEMP_NUM_TCP_SEG        6
+/* MEMP_NUM_SYS_TIMEOUT: the number of simulateously active
+   timeouts. */
+#define MEMP_NUM_SYS_TIMEOUT    6
+
+/* The following four are used only with the sequential API and can be
+   set to 0 if the application only will use the raw API. */
+/* MEMP_NUM_NETBUF: the number of struct netbufs. */
+#define MEMP_NUM_NETBUF         3
+/* MEMP_NUM_NETCONN: the number of struct netconns. */
+#define MEMP_NUM_NETCONN        6
+/* MEMP_NUM_APIMSG: the number of struct api_msg, used for
+   communication between the TCP/IP stack and the sequential
+   programs. */
+#define MEMP_NUM_API_MSG        4
+/* MEMP_NUM_TCPIPMSG: the number of struct tcpip_msg, which is used
+   for sequential API communication and incoming packets. Used in
+   src/api/tcpip.c. */
+#define MEMP_NUM_TCPIP_MSG      4
+
+
+/* ---------- Pbuf options ---------- */
+/* PBUF_POOL_SIZE: the number of buffers in the pbuf pool. */
+
+#define PBUF_POOL_SIZE          6
+
+/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
+
+#define PBUF_POOL_BUFSIZE       500
+
+/* PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+   link level header. */
+#define PBUF_LINK_HLEN          16
+
+/* ---------- TCP options ---------- */
+#define LWIP_TCP                1
+#define TCP_TTL                 255
+/* TCP receive window. */
+#define TCP_WND                 1500
+/* Controls if TCP should queue segments that arrive out of
+   order. Define to 0 if your device is low on memory. */
+#define TCP_QUEUE_OOSEQ         1
+
+/* TCP Maximum segment size. */
+#define TCP_MSS                 1500
+
+/* TCP sender buffer space (bytes). */
+#define TCP_SND_BUF             2150
+
+/* TCP sender buffer space (pbufs). This must be at least = 2 *
+   TCP_SND_BUF/TCP_MSS for things to work. */
+#define TCP_SND_QUEUELEN        6 * TCP_SND_BUF/TCP_MSS
+
+
+
+/* Maximum number of retransmissions of data segments. */
+#define TCP_MAXRTX              12
+
+/* Maximum number of retransmissions of SYN segments. */
+#define TCP_SYNMAXRTX           4
+
+/* ---------- ARP options ---------- */
+#define ARP_TABLE_SIZE 10
+#define ARP_QUEUEING 0
+
+/* ---------- IP options ---------- */
+/* Define IP_FORWARD to 1 if you wish to have the ability to forward
+   IP packets across network interfaces. If you are going to run lwIP
+   on a device with only one network interface, define this to 0. */
+#define IP_FORWARD              0
+
+/* If defined to 1, IP options are allowed (but not parsed). If
+   defined to 0, all packets with IP options are dropped. */
+#define IP_OPTIONS              1
+
+/* ---------- ICMP options ---------- */
+#define ICMP_TTL                255
+
+
+/* ---------- DHCP options ---------- */
+/* Define LWIP_DHCP to 1 if you want DHCP configuration of
+   interfaces. DHCP is not implemented in lwIP 0.5.1, however, so
+   turning this on does currently not work. */
+#define LWIP_DHCP               0
+
+/* 1 if you want to do an ARP check on the offered address
+   (recommended). */
+#define DHCP_DOES_ARP_CHECK     1
+
+#define TCPIP_THREAD_PRIO               lwipINTERFACE_TASK_PRIORITY
+
+/* ---------- Statistics options ---------- */
+#define LWIP_STATS 1
+
+#define LWIP_STATS_DISPLAY 1
+
+#if LWIP_STATS
+#define LINK_STATS 1
+#define IP_STATS   1
+#define ICMP_STATS 1
+#define UDP_STATS  1
+#define TCP_STATS  1
+#define MEM_STATS  1
+#define MEMP_STATS 1
+#define PBUF_STATS 1
+#define SYS_STATS  1
+#endif /* STATS */
+
+
+#endif /* __LWIPOPTS_H__ */
diff --git a/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/sys_arch.c b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/sys_arch.c
new file mode 100644
index 000000000..5d9ee7a7f
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/NETWORK/lwip-port/AT32UC3A/sys_arch.c
@@ -0,0 +1,431 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief lwIP abstraction layer for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "conf_eth.h"
+
+#if (HTTP_USED == 1)
+  #include "BasicWEB.h"
+#endif
+
+#if (TFTP_USED == 1)
+  #include "BasicTFTP.h"
+#endif
+
+#if (SMTP_USED == 1)
+  #include "BasicSMTP.h"
+#endif
+
+/* lwIP includes. */
+#include "lwip/debug.h"
+#include "lwip/def.h"
+#include "lwip/sys.h"
+#include "lwip/mem.h"
+
+/* Message queue constants. */
+#define archMESG_QUEUE_LENGTH ( 6 )
+#define archPOST_BLOCK_TIME_MS  ( ( unsigned portLONG ) 10000 )
+
+struct timeoutlist 
+{
+  struct sys_timeouts timeouts;
+  xTaskHandle pid;
+};
+
+static struct timeoutlist timeoutlist[SYS_THREAD_MAX];
+static u16_t nextthread = 0;
+int intlevel = 0;
+
+extern void ethernetif_input( void * pvParameters );
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates an empty mailbox.
+sys_mbox_t
+sys_mbox_new(void)
+{
+  xQueueHandle mbox;
+
+  mbox = xQueueCreate( archMESG_QUEUE_LENGTH, sizeof( void * ) );
+
+  return mbox;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Deallocates a mailbox. If there are messages still present in the
+  mailbox when the mailbox is deallocated, it is an indication of a
+  programming error in lwIP and the developer should be notified.
+*/
+void
+sys_mbox_free(sys_mbox_t mbox)
+{
+  if( uxQueueMessagesWaiting( mbox ) )
+  {
+    /* Line for breakpoint.  Should never break here! */
+    __asm volatile ( "NOP" );
+  }
+
+  vQueueDelete( mbox );
+}
+
+/*-----------------------------------------------------------------------------------*/
+//   Posts the "msg" to the mailbox.
+void
+sys_mbox_post(sys_mbox_t mbox, void *data)
+{   
+  xQueueSend( mbox, &data, ( portTickType ) ( archPOST_BLOCK_TIME_MS / portTICK_RATE_MS ) );
+}
+
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread until a message arrives in the mailbox, but does
+  not block the thread longer than "timeout" milliseconds (similar to
+  the sys_arch_sem_wait() function). The "msg" argument is a result
+  parameter that is set by the function (i.e., by doing "*msg =
+  ptr"). The "msg" parameter maybe NULL to indicate that the message
+  should be dropped.
+
+  The return values are the same as for the sys_arch_sem_wait() function:
+  Number of milliseconds spent waiting or SYS_ARCH_TIMEOUT if there was a
+  timeout.
+
+  Note that a function with a similar name, sys_mbox_fetch(), is
+  implemented by lwIP. 
+*/
+u32_t sys_arch_mbox_fetch(sys_mbox_t mbox, void **msg, u32_t timeout)
+{
+void *dummyptr;
+portTickType StartTime, EndTime, Elapsed;
+
+  StartTime = xTaskGetTickCount();
+
+  if( msg == NULL )
+  {
+    msg = &dummyptr;
+  }
+  
+  if( timeout != 0 )
+  {
+    if(pdTRUE == xQueueReceive( mbox, &(*msg), timeout ) )
+    {
+      EndTime = xTaskGetTickCount();
+      Elapsed = EndTime - StartTime;
+      if( Elapsed == 0 )
+      {
+        Elapsed = 1;
+      }
+      return ( Elapsed );
+    }
+    else // timed out blocking for message
+    {
+      *msg = NULL;
+      return SYS_ARCH_TIMEOUT;
+    }
+  }
+  else // block forever for a message.
+  {
+    while( pdTRUE != xQueueReceive( mbox, &(*msg), 10000 ) ) // time is arbitrary
+    {
+      ;
+    }
+    EndTime = xTaskGetTickCount();
+    Elapsed = EndTime - StartTime;
+    if( Elapsed == 0 )
+    {
+      Elapsed = 1;
+    }
+    return ( Elapsed ); // return time blocked TBD test
+  }
+}
+
+/*-----------------------------------------------------------------------------------*/
+//  Creates and returns a new semaphore. The "count" argument specifies
+//  the initial state of the semaphore. TBD finish and test
+sys_sem_t
+sys_sem_new(u8_t count)
+{
+  xSemaphoreHandle  xSemaphore = NULL;
+
+  portENTER_CRITICAL();
+  vSemaphoreCreateBinary( xSemaphore );
+  if( xSemaphore == NULL )
+  {
+    return NULL;  // TBD need assert
+  }
+  if(count == 0)  // Means we want the sem to be unavailable at init state.
+  {
+    xSemaphoreTake(xSemaphore,1);
+  }
+  portEXIT_CRITICAL();
+
+  return xSemaphore;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Blocks the thread while waiting for the semaphore to be
+  signaled. If the "timeout" argument is non-zero, the thread should
+  only be blocked for the specified time (measured in
+  milliseconds).
+
+  If the timeout argument is non-zero, the return value is the number of
+  milliseconds spent waiting for the semaphore to be signaled. If the
+  semaphore wasn't signaled within the specified time, the return value is
+  SYS_ARCH_TIMEOUT. If the thread didn't have to wait for the semaphore
+  (i.e., it was already signaled), the function may return zero.
+
+  Notice that lwIP implements a function with a similar name,
+  sys_sem_wait(), that uses the sys_arch_sem_wait() function.
+*/
+u32_t
+sys_arch_sem_wait(sys_sem_t sem, u32_t timeout)
+{
+portTickType StartTime, EndTime, Elapsed;
+
+  StartTime = xTaskGetTickCount();
+
+  if( timeout != 0)
+  {
+    if( xSemaphoreTake( sem, timeout ) == pdTRUE )
+    {
+      EndTime = xTaskGetTickCount();
+      Elapsed = EndTime - StartTime;
+      if( Elapsed == 0 )
+      {
+        Elapsed = 1;
+      }
+      return (Elapsed); // return time blocked TBD test
+    }
+    else
+    {
+      return SYS_ARCH_TIMEOUT;
+    }
+  }
+  else // must block without a timeout
+  {
+    while( xSemaphoreTake( sem, 10000 ) != pdTRUE )
+    {
+      ;
+    }
+    EndTime = xTaskGetTickCount();
+    Elapsed = EndTime - StartTime;
+    if( Elapsed == 0 )
+    {
+      Elapsed = 1;
+    }
+
+    return ( Elapsed ); // return time blocked
+  
+  }
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Signals a semaphore
+void
+sys_sem_signal(sys_sem_t sem)
+{
+  xSemaphoreGive( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Deallocates a semaphore
+void
+sys_sem_free(sys_sem_t sem)
+{
+  vQueueDelete( sem );
+}
+
+/*-----------------------------------------------------------------------------------*/
+// Initialize sys arch
+void
+sys_init(void)
+{
+
+  int i;
+
+  // Initialize the the per-thread sys_timeouts structures
+  // make sure there are no valid pids in the list
+  for(i = 0; i < SYS_THREAD_MAX; i++)
+  {
+    timeoutlist[i].pid = 0;
+    timeoutlist[i].timeouts.next = NULL;
+  }
+
+  // keep track of how many threads have been created
+  nextthread = 0;
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*
+  Returns a pointer to the per-thread sys_timeouts structure. In lwIP,
+  each thread has a list of timeouts which is represented as a linked
+  list of sys_timeout structures. The sys_timeouts structure holds a
+  pointer to a linked list of timeouts. This function is called by
+  the lwIP timeout scheduler and must not return a NULL value. 
+
+  In a single threaded sys_arch implementation, this function will
+  simply return a pointer to a global sys_timeouts variable stored in
+  the sys_arch module.
+*/
+struct sys_timeouts *
+sys_arch_timeouts(void)
+{
+int i;
+xTaskHandle pid;
+struct timeoutlist *tl;  
+
+  pid = xTaskGetCurrentTaskHandle( );
+
+  for(i = 0; i < nextthread; i++)
+  {
+    tl = &(timeoutlist[i]);
+    if(tl->pid == pid)
+    {
+      return &(tl->timeouts);
+    }
+  }
+
+
+  // If we're here, this means the scheduler gave the focus to the task as it was
+  // being created(because of a higher priority). Since timeoutlist[] update is
+  // done just after the task creation, the array is not up-to-date.
+  // => the last array entry must be the one of the current task.
+  return( &( timeoutlist[nextthread].timeouts ) );
+/*
+  // Error
+  return NULL;
+*/
+}
+
+/*-----------------------------------------------------------------------------------*/
+/*-----------------------------------------------------------------------------------*/
+// TBD 
+/*-----------------------------------------------------------------------------------*/
+/*
+  Starts a new thread with priority "prio" that will begin its execution in the
+  function "thread()". The "arg" argument will be passed as an argument to the
+  thread() function. The id of the new thread is returned. Both the id and
+  the priority are system dependent.
+*/
+sys_thread_t sys_thread_new(void (* thread)(void *arg), void *arg, int prio)
+{
+xTaskHandle CreatedTask;
+int result = pdFAIL;
+static int iCall = 0;
+
+  if( thread == ethernetif_input )
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "ETHINT", netifINTERFACE_TASK_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+  else if( iCall == 0 )
+  {
+    /* The first time this is called we are creating the lwIP handler. */
+    result = xTaskCreate( thread, ( signed portCHAR * ) "lwIP", lwipINTERFACE_STACK_SIZE, arg, prio, &CreatedTask );
+    iCall++;
+  }
+#if (HTTP_USED == 1)
+  else if (thread == vBasicWEBServer)
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "WEB", lwipBASIC_WEB_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+#endif
+#if (TFTP_USED == 1)
+  else if (thread == vBasicTFTPServer)
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "TFTP", lwipBASIC_TFTP_SERVER_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+#endif
+#if (SMTP_USED == 1)
+  else if (thread == vBasicSMTPHost)
+  {
+    result = xTaskCreate( thread, ( signed portCHAR * ) "SMTP", lwipBASIC_SMTP_HOST_STACK_SIZE, arg, prio, &CreatedTask );
+  }
+#endif
+
+
+  // For each task created, store the task handle (pid) in the timers array.
+  // This scheme doesn't allow for threads to be deleted
+  timeoutlist[nextthread++].pid = CreatedTask;
+
+  if(result == pdPASS)
+  {
+    return CreatedTask;
+  }
+  else
+  {
+    return NULL;
+  }
+}
+
+/*
+  This optional function does a "fast" critical region protection and returns
+  the previous protection level. This function is only called during very short
+  critical regions. An embedded system which supports ISR-based drivers might
+  want to implement this function by disabling interrupts. Task-based systems
+  might want to implement this by using a mutex or disabling tasking. This
+  function should support recursive calls from the same task or interrupt. In
+  other words, sys_arch_protect() could be called while already protected. In
+  that case the return value indicates that it is already protected.
+
+  sys_arch_protect() is only required if your port is supporting an operating
+  system.
+*/
+sys_prot_t sys_arch_protect(void)
+{
+  vPortEnterCritical();
+  return 1;
+}
+
+/*
+  This optional function does a "fast" set of critical region protection to the
+  value specified by pval. See the documentation for sys_arch_protect() for
+  more information. This function is only required if your port is supporting
+  an operating system.
+*/
+void sys_arch_unprotect(sys_prot_t pval)
+{ 
+  ( void ) pval;
+  vPortExitCritical();
+}
+
diff --git a/Demo/lwIP_AVR32_UC3/PARTEST/ParTest.c b/Demo/lwIP_AVR32_UC3/PARTEST/ParTest.c
new file mode 100644
index 000000000..d7a3ca3af
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/PARTEST/ParTest.c
@@ -0,0 +1,121 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS Led Driver example for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#if __GNUC__
+#  include 
+#elif __ICCAVR32__
+#  include 
+#else
+#  error Unknown compiler
+#endif
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "partest.h"
+
+
+/*-----------------------------------------------------------
+ * Simple parallel port IO routines.
+ *-----------------------------------------------------------*/
+
+#define partstALL_OUTPUTS_OFF     ( ( unsigned portCHAR ) 0x00 )
+#define partstMAX_OUTPUT_LED      ( ( unsigned portCHAR ) 8 )
+
+static volatile unsigned portCHAR ucCurrentOutputValue = partstALL_OUTPUTS_OFF; /*lint !e956 File scope parameters okay here. */
+
+/*-----------------------------------------------------------*/
+
+void vParTestInitialise( void )
+{
+	LED_Display(partstALL_OUTPUTS_OFF); /* Start with all LEDs off. */
+}
+/*-----------------------------------------------------------*/
+
+void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
+{
+unsigned portCHAR ucBit;
+
+	if( uxLED >= partstMAX_OUTPUT_LED )
+	{
+		return;
+	}
+
+	ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;
+
+	vTaskSuspendAll();
+	{
+		if( xValue == pdTRUE )
+		{
+		  ucCurrentOutputValue |= ucBit;
+		}
+		else
+		{
+		  ucCurrentOutputValue &= ~ucBit;
+		}
+
+		LED_Display(ucCurrentOutputValue);
+	}
+	xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
+{
+	unsigned portCHAR ucBit;
+
+	if( uxLED >= partstMAX_OUTPUT_LED )
+	{
+		return;
+	}
+
+	ucBit = ( ( unsigned portCHAR ) 1 ) << uxLED;
+
+	vTaskSuspendAll();
+	{
+		ucCurrentOutputValue ^= ucBit;
+		LED_Display(ucCurrentOutputValue);
+	}
+	xTaskResumeAll();
+}
+
diff --git a/Demo/lwIP_AVR32_UC3/SERIAL/serial.c b/Demo/lwIP_AVR32_UC3/SERIAL/serial.c
new file mode 100644
index 000000000..b93bbf752
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/SERIAL/serial.c
@@ -0,0 +1,372 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS serial port for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/*
+  BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "queue.h"
+#include "task.h"
+
+/* Demo application includes. */
+#include "serial.h"
+#if __GNUC__
+#  include 
+#elif __ICCAVR32__
+#  include 
+#else
+#  error Unknown compiler
+#endif
+#include "board.h"
+#include "gpio.h"
+
+/*-----------------------------------------------------------*/
+
+/* Constants to setup and access the USART. */
+#define serINVALID_COMPORT_HANDLER        ( ( xComPortHandle ) 0 )
+#define serINVALID_QUEUE                  ( ( xQueueHandle ) 0 )
+#define serHANDLE                         ( ( xComPortHandle ) 1 )
+#define serNO_BLOCK                       ( ( portTickType ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* Queues used to hold received characters, and characters waiting to be
+transmitted. */
+static xQueueHandle xRxedChars;
+static xQueueHandle xCharsForTx;
+
+/*-----------------------------------------------------------*/
+
+/* Forward declaration. */
+static void vprvSerialCreateQueues( unsigned portBASE_TYPE uxQueueLength,
+        xQueueHandle *pxRxedChars,
+        xQueueHandle *pxCharsForTx );
+
+/*-----------------------------------------------------------*/
+
+#if __GNUC__
+__attribute__((__noinline__))
+#elif __ICCAVR32__
+#pragma optimize = no_inline
+#endif
+static portBASE_TYPE prvUSART0_ISR_NonNakedBehaviour( void )
+{
+  /* Now we can declare the local variables. */
+  signed portCHAR     cChar;
+  portBASE_TYPE     xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
+  unsigned portLONG     ulStatus;
+  volatile avr32_usart_t  *usart0 = &AVR32_USART0;
+  portBASE_TYPE retstatus;
+
+  /* What caused the interrupt? */
+  ulStatus = usart0->csr & usart0->imr;
+
+  if (ulStatus & AVR32_USART_CSR_TXRDY_MASK)
+  {
+    /* The interrupt was caused by the THR becoming empty.  Are there any
+       more characters to transmit? */
+    /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+      calls in a critical section . */
+    portENTER_CRITICAL();
+    retstatus = xQueueReceiveFromISR(xCharsForTx, &cChar, &xTaskWokenByTx);
+    portEXIT_CRITICAL();
+    if (retstatus == pdTRUE)
+    {
+      /* A character was retrieved from the queue so can be sent to the
+         THR now. */
+      usart0->thr = cChar;
+    }
+    else
+    {
+      /* Queue empty, nothing to send so turn off the Tx interrupt. */
+      usart0->idr = AVR32_USART_IDR_TXRDY_MASK;
+    }
+  }
+
+  if (ulStatus & AVR32_USART_CSR_RXRDY_MASK)
+  {
+    /* The interrupt was caused by the receiver getting data. */
+    cChar = usart0->rhr; //TODO
+
+    /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+      calls in a critical section . */
+    portENTER_CRITICAL();
+    retstatus = xQueueSendFromISR(xRxedChars, &cChar, pdFALSE);
+    portEXIT_CRITICAL();
+    if (retstatus)
+    {
+      xTaskWokenByRx = pdTRUE;
+    }
+  }
+
+  /* The return value will be used by portEXIT_SWITCHING_ISR() to know if it
+  should perform a vTaskSwitchContext(). */
+  return ( xTaskWokenByTx || xTaskWokenByRx );
+}
+
+
+/*
+ * USART0 interrupt service routine.
+ */
+#if __GNUC__
+__attribute__((__naked__))
+#elif __ICCAVR32__
+#pragma shadow_registers = full  // All registers shadowed
+#pragma handler = AVR32_USART0_IRQ_GROUP, 0
+__interrupt
+#endif
+static void vUSART0_ISR( void )
+{
+
+ /* This ISR can cause a context switch, so the first statement must be a
+  call to the portENTER_SWITCHING_ISR() macro.  This must be BEFORE any
+  variable declarations. */
+  portENTER_SWITCHING_ISR();
+  prvUSART0_ISR_NonNakedBehaviour();
+ /* Exit the ISR.  If a task was woken by either a character being received
+  or transmitted then a context switch will occur. */
+  portEXIT_SWITCHING_ISR();
+}
+/*-----------------------------------------------------------*/
+
+
+
+/*
+ * Init the serial port for the Minimal implementation.
+ */
+xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
+{
+  xComPortHandle    xReturn = serHANDLE;
+  volatile avr32_usart_t  *usart0 = &AVR32_USART0;
+  int                           cd; /* USART0 Clock Divider. */
+
+  /* Create the rx and tx queues. */
+  vprvSerialCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );
+
+  /* Configure USART0. */
+  if( ( xRxedChars != serINVALID_QUEUE ) &&
+      ( xCharsForTx != serINVALID_QUEUE ) &&
+      ( ulWantedBaud != ( unsigned portLONG ) 0 ) )
+  {
+    portENTER_CRITICAL();
+    {
+      /**
+       ** Reset USART0.
+       **/
+      /* Disable all USART0 interrupt sources to begin... */
+      usart0->idr = 0xFFFFFFFF;
+
+      /* Reset mode and other registers that could cause unpredictable
+         behaviour after reset */
+      usart0->mr = 0; /* Reset Mode register. */
+      usart0->rtor = 0; /* Reset Receiver Time-out register. */
+      usart0->ttgr = 0; /* Reset Transmitter Timeguard register. */
+
+      /* Shutdown RX and TX, reset status bits, reset iterations in CSR, reset NACK
+         and turn off DTR and RTS */
+      usart0->cr = AVR32_USART_CR_RSTRX_MASK   |
+                   AVR32_USART_CR_RSTTX_MASK   |
+                   AVR32_USART_CR_RXDIS_MASK   |
+                   AVR32_USART_CR_TXDIS_MASK   |
+                   AVR32_USART_CR_RSTSTA_MASK  |
+                   AVR32_USART_CR_RSTIT_MASK   |
+                   AVR32_USART_CR_RSTNACK_MASK |
+                   AVR32_USART_CR_DTRDIS_MASK  |
+                   AVR32_USART_CR_RTSDIS_MASK;
+
+      /**
+       ** Configure USART0.
+       **/
+      /* Enable USART0 RXD & TXD pins. */
+      gpio_enable_module_pin(AVR32_USART0_RXD_0_PIN, AVR32_USART0_RXD_0_FUNCTION);
+      gpio_enable_module_pin(AVR32_USART0_TXD_0_PIN, AVR32_USART0_TXD_0_FUNCTION);
+
+      /* Set the USART0 baudrate to be as close as possible to the wanted baudrate. */
+      /*
+       *             ** BAUDRATE CALCULATION **
+       *
+       *                 Selected Clock                       Selected Clock
+       *     baudrate = ----------------   or     baudrate = ----------------
+       *                    16 x CD                              8 x CD
+       *
+       *       (with 16x oversampling)              (with 8x oversampling)
+       */
+      if ( ulWantedBaud < (configCPU_CLOCK_HZ/16)  ){
+        /* Use 8x oversampling */
+        usart0->mr |= (1<brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);
+      } else {
+        /* Use 16x oversampling */
+        usart0->mr &= ~(1< 65535) {
+          /* Baudrate is too low */
+          return serINVALID_COMPORT_HANDLER;
+        }
+      }
+      usart0->brgr = (cd << AVR32_USART_BRGR_CD_OFFSET);
+
+      /* Set the USART0 Mode register: Mode=Normal(0), Clk selection=MCK(0),
+         CHRL=8,  SYNC=0(asynchronous), PAR=None, NBSTOP=1, CHMODE=0, MSBF=0,
+         MODE9=0, CKLO=0, OVER(previously done when setting the baudrate),
+         other fields not used in this mode. */
+      usart0->mr |= ((8-5) << AVR32_USART_MR_CHRL_OFFSET  ) |
+                    (   4  << AVR32_USART_MR_PAR_OFFSET   ) |
+                    (   1  << AVR32_USART_MR_NBSTOP_OFFSET);
+
+      /* Write the Transmit Timeguard Register */
+      usart0->ttgr = 0;
+
+#if __GNUC__
+      // Register the USART0 interrupt handler to the interrupt controller and
+      // enable the USART0 interrupt.
+      INTC_register_interrupt(&vUSART0_ISR, AVR32_USART0_IRQ, INT1);
+#endif
+
+      /* Enable USART0 interrupt sources (but not Tx for now)... */
+      usart0->ier = AVR32_USART_IER_RXRDY_MASK;
+
+      /* Enable receiver and transmitter... */
+      usart0->cr |= AVR32_USART_CR_TXEN_MASK | AVR32_USART_CR_RXEN_MASK;
+    }
+    portEXIT_CRITICAL();
+  }
+  else
+  {
+    xReturn = serINVALID_COMPORT_HANDLER;
+  }
+
+  return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
+{
+  /* The port handle is not required as this driver only supports UART0. */
+  ( void ) pxPort;
+
+  /* Get the next character from the buffer.  Return false if no characters
+  are available, or arrive before xBlockTime expires. */
+  if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
+  {
+    return pdTRUE;
+  }
+  else
+  {
+    return pdFALSE;
+  }
+}
+/*-----------------------------------------------------------*/
+
+void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
+{
+signed portCHAR *pxNext;
+
+  /* NOTE: This implementation does not handle the queue being full as no
+  block time is used! */
+
+  /* The port handle is not required as this driver only supports UART0. */
+  ( void ) pxPort;
+
+  /* Send each character in the string, one at a time. */
+  pxNext = ( signed portCHAR * ) pcString;
+  while( *pxNext )
+  {
+    xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
+    pxNext++;
+  }
+}
+/*-----------------------------------------------------------*/
+
+signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
+{
+volatile avr32_usart_t  *usart0 = &AVR32_USART0;
+
+  /* Place the character in the queue of characters to be transmitted. */
+  if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
+  {
+    return pdFAIL;
+  }
+
+  /* Turn on the Tx interrupt so the ISR will remove the character from the
+  queue and send it.   This does not need to be in a critical section as
+  if the interrupt has already removed the character the next interrupt
+  will simply turn off the Tx interrupt again. */
+  usart0->ier = (1 << AVR32_USART_IER_TXRDY_OFFSET);
+
+  return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+void vSerialClose( xComPortHandle xPort )
+{
+  /* Not supported as not required by the demo application. */
+}
+/*-----------------------------------------------------------*/
+
+/*###########################################################*/
+
+/*
+ * Create the rx and tx queues.
+ */
+static void vprvSerialCreateQueues(  unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )
+{
+  /* Create the queues used to hold Rx and Tx characters. */
+  xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+  xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
+
+  /* Pass back a reference to the queues so the serial API file can
+  post/receive characters. */
+  *pxRxedChars = xRxedChars;
+  *pxCharsForTx = xCharsForTx;
+}
+/*-----------------------------------------------------------*/
diff --git a/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h
new file mode 100644
index 000000000..3457d20f8
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/mrepeat.h
@@ -0,0 +1,325 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor macro repeating utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _MREPEAT_H_
+#define _MREPEAT_H_
+
+#include "preprocessor.h"
+
+
+//! Maximal number of repetitions supported by MREPEAT.
+#define MREPEAT_LIMIT   256
+
+/*! \brief Macro repeat.
+ *
+ * This macro represents a horizontal repetition construct.
+ *
+ * \param count  The number of repetitious calls to macro. Valid values range from 0 to MREPEAT_LIMIT.
+ * \param macro  A binary operation of the form macro(n, data). This macro is expanded by MREPEAT with
+ *               the current repetition number and the auxiliary data argument.
+ * \param data   Auxiliary data passed to macro.
+ *
+ * \return       macro(0, data) macro(1, data) ... macro(count - 1, data)
+ */
+#define MREPEAT(count, macro, data)         TPASTE2(MREPEAT, count)(macro, data)
+
+#define MREPEAT0(  macro, data)
+#define MREPEAT1(  macro, data)       MREPEAT0(  macro, data)   macro(  0, data)
+#define MREPEAT2(  macro, data)       MREPEAT1(  macro, data)   macro(  1, data)
+#define MREPEAT3(  macro, data)       MREPEAT2(  macro, data)   macro(  2, data)
+#define MREPEAT4(  macro, data)       MREPEAT3(  macro, data)   macro(  3, data)
+#define MREPEAT5(  macro, data)       MREPEAT4(  macro, data)   macro(  4, data)
+#define MREPEAT6(  macro, data)       MREPEAT5(  macro, data)   macro(  5, data)
+#define MREPEAT7(  macro, data)       MREPEAT6(  macro, data)   macro(  6, data)
+#define MREPEAT8(  macro, data)       MREPEAT7(  macro, data)   macro(  7, data)
+#define MREPEAT9(  macro, data)       MREPEAT8(  macro, data)   macro(  8, data)
+#define MREPEAT10( macro, data)       MREPEAT9(  macro, data)   macro(  9, data)
+#define MREPEAT11( macro, data)       MREPEAT10( macro, data)   macro( 10, data)
+#define MREPEAT12( macro, data)       MREPEAT11( macro, data)   macro( 11, data)
+#define MREPEAT13( macro, data)       MREPEAT12( macro, data)   macro( 12, data)
+#define MREPEAT14( macro, data)       MREPEAT13( macro, data)   macro( 13, data)
+#define MREPEAT15( macro, data)       MREPEAT14( macro, data)   macro( 14, data)
+#define MREPEAT16( macro, data)       MREPEAT15( macro, data)   macro( 15, data)
+#define MREPEAT17( macro, data)       MREPEAT16( macro, data)   macro( 16, data)
+#define MREPEAT18( macro, data)       MREPEAT17( macro, data)   macro( 17, data)
+#define MREPEAT19( macro, data)       MREPEAT18( macro, data)   macro( 18, data)
+#define MREPEAT20( macro, data)       MREPEAT19( macro, data)   macro( 19, data)
+#define MREPEAT21( macro, data)       MREPEAT20( macro, data)   macro( 20, data)
+#define MREPEAT22( macro, data)       MREPEAT21( macro, data)   macro( 21, data)
+#define MREPEAT23( macro, data)       MREPEAT22( macro, data)   macro( 22, data)
+#define MREPEAT24( macro, data)       MREPEAT23( macro, data)   macro( 23, data)
+#define MREPEAT25( macro, data)       MREPEAT24( macro, data)   macro( 24, data)
+#define MREPEAT26( macro, data)       MREPEAT25( macro, data)   macro( 25, data)
+#define MREPEAT27( macro, data)       MREPEAT26( macro, data)   macro( 26, data)
+#define MREPEAT28( macro, data)       MREPEAT27( macro, data)   macro( 27, data)
+#define MREPEAT29( macro, data)       MREPEAT28( macro, data)   macro( 28, data)
+#define MREPEAT30( macro, data)       MREPEAT29( macro, data)   macro( 29, data)
+#define MREPEAT31( macro, data)       MREPEAT30( macro, data)   macro( 30, data)
+#define MREPEAT32( macro, data)       MREPEAT31( macro, data)   macro( 31, data)
+#define MREPEAT33( macro, data)       MREPEAT32( macro, data)   macro( 32, data)
+#define MREPEAT34( macro, data)       MREPEAT33( macro, data)   macro( 33, data)
+#define MREPEAT35( macro, data)       MREPEAT34( macro, data)   macro( 34, data)
+#define MREPEAT36( macro, data)       MREPEAT35( macro, data)   macro( 35, data)
+#define MREPEAT37( macro, data)       MREPEAT36( macro, data)   macro( 36, data)
+#define MREPEAT38( macro, data)       MREPEAT37( macro, data)   macro( 37, data)
+#define MREPEAT39( macro, data)       MREPEAT38( macro, data)   macro( 38, data)
+#define MREPEAT40( macro, data)       MREPEAT39( macro, data)   macro( 39, data)
+#define MREPEAT41( macro, data)       MREPEAT40( macro, data)   macro( 40, data)
+#define MREPEAT42( macro, data)       MREPEAT41( macro, data)   macro( 41, data)
+#define MREPEAT43( macro, data)       MREPEAT42( macro, data)   macro( 42, data)
+#define MREPEAT44( macro, data)       MREPEAT43( macro, data)   macro( 43, data)
+#define MREPEAT45( macro, data)       MREPEAT44( macro, data)   macro( 44, data)
+#define MREPEAT46( macro, data)       MREPEAT45( macro, data)   macro( 45, data)
+#define MREPEAT47( macro, data)       MREPEAT46( macro, data)   macro( 46, data)
+#define MREPEAT48( macro, data)       MREPEAT47( macro, data)   macro( 47, data)
+#define MREPEAT49( macro, data)       MREPEAT48( macro, data)   macro( 48, data)
+#define MREPEAT50( macro, data)       MREPEAT49( macro, data)   macro( 49, data)
+#define MREPEAT51( macro, data)       MREPEAT50( macro, data)   macro( 50, data)
+#define MREPEAT52( macro, data)       MREPEAT51( macro, data)   macro( 51, data)
+#define MREPEAT53( macro, data)       MREPEAT52( macro, data)   macro( 52, data)
+#define MREPEAT54( macro, data)       MREPEAT53( macro, data)   macro( 53, data)
+#define MREPEAT55( macro, data)       MREPEAT54( macro, data)   macro( 54, data)
+#define MREPEAT56( macro, data)       MREPEAT55( macro, data)   macro( 55, data)
+#define MREPEAT57( macro, data)       MREPEAT56( macro, data)   macro( 56, data)
+#define MREPEAT58( macro, data)       MREPEAT57( macro, data)   macro( 57, data)
+#define MREPEAT59( macro, data)       MREPEAT58( macro, data)   macro( 58, data)
+#define MREPEAT60( macro, data)       MREPEAT59( macro, data)   macro( 59, data)
+#define MREPEAT61( macro, data)       MREPEAT60( macro, data)   macro( 60, data)
+#define MREPEAT62( macro, data)       MREPEAT61( macro, data)   macro( 61, data)
+#define MREPEAT63( macro, data)       MREPEAT62( macro, data)   macro( 62, data)
+#define MREPEAT64( macro, data)       MREPEAT63( macro, data)   macro( 63, data)
+#define MREPEAT65( macro, data)       MREPEAT64( macro, data)   macro( 64, data)
+#define MREPEAT66( macro, data)       MREPEAT65( macro, data)   macro( 65, data)
+#define MREPEAT67( macro, data)       MREPEAT66( macro, data)   macro( 66, data)
+#define MREPEAT68( macro, data)       MREPEAT67( macro, data)   macro( 67, data)
+#define MREPEAT69( macro, data)       MREPEAT68( macro, data)   macro( 68, data)
+#define MREPEAT70( macro, data)       MREPEAT69( macro, data)   macro( 69, data)
+#define MREPEAT71( macro, data)       MREPEAT70( macro, data)   macro( 70, data)
+#define MREPEAT72( macro, data)       MREPEAT71( macro, data)   macro( 71, data)
+#define MREPEAT73( macro, data)       MREPEAT72( macro, data)   macro( 72, data)
+#define MREPEAT74( macro, data)       MREPEAT73( macro, data)   macro( 73, data)
+#define MREPEAT75( macro, data)       MREPEAT74( macro, data)   macro( 74, data)
+#define MREPEAT76( macro, data)       MREPEAT75( macro, data)   macro( 75, data)
+#define MREPEAT77( macro, data)       MREPEAT76( macro, data)   macro( 76, data)
+#define MREPEAT78( macro, data)       MREPEAT77( macro, data)   macro( 77, data)
+#define MREPEAT79( macro, data)       MREPEAT78( macro, data)   macro( 78, data)
+#define MREPEAT80( macro, data)       MREPEAT79( macro, data)   macro( 79, data)
+#define MREPEAT81( macro, data)       MREPEAT80( macro, data)   macro( 80, data)
+#define MREPEAT82( macro, data)       MREPEAT81( macro, data)   macro( 81, data)
+#define MREPEAT83( macro, data)       MREPEAT82( macro, data)   macro( 82, data)
+#define MREPEAT84( macro, data)       MREPEAT83( macro, data)   macro( 83, data)
+#define MREPEAT85( macro, data)       MREPEAT84( macro, data)   macro( 84, data)
+#define MREPEAT86( macro, data)       MREPEAT85( macro, data)   macro( 85, data)
+#define MREPEAT87( macro, data)       MREPEAT86( macro, data)   macro( 86, data)
+#define MREPEAT88( macro, data)       MREPEAT87( macro, data)   macro( 87, data)
+#define MREPEAT89( macro, data)       MREPEAT88( macro, data)   macro( 88, data)
+#define MREPEAT90( macro, data)       MREPEAT89( macro, data)   macro( 89, data)
+#define MREPEAT91( macro, data)       MREPEAT90( macro, data)   macro( 90, data)
+#define MREPEAT92( macro, data)       MREPEAT91( macro, data)   macro( 91, data)
+#define MREPEAT93( macro, data)       MREPEAT92( macro, data)   macro( 92, data)
+#define MREPEAT94( macro, data)       MREPEAT93( macro, data)   macro( 93, data)
+#define MREPEAT95( macro, data)       MREPEAT94( macro, data)   macro( 94, data)
+#define MREPEAT96( macro, data)       MREPEAT95( macro, data)   macro( 95, data)
+#define MREPEAT97( macro, data)       MREPEAT96( macro, data)   macro( 96, data)
+#define MREPEAT98( macro, data)       MREPEAT97( macro, data)   macro( 97, data)
+#define MREPEAT99( macro, data)       MREPEAT98( macro, data)   macro( 98, data)
+#define MREPEAT100(macro, data)       MREPEAT99( macro, data)   macro( 99, data)
+#define MREPEAT101(macro, data)       MREPEAT100(macro, data)   macro(100, data)
+#define MREPEAT102(macro, data)       MREPEAT101(macro, data)   macro(101, data)
+#define MREPEAT103(macro, data)       MREPEAT102(macro, data)   macro(102, data)
+#define MREPEAT104(macro, data)       MREPEAT103(macro, data)   macro(103, data)
+#define MREPEAT105(macro, data)       MREPEAT104(macro, data)   macro(104, data)
+#define MREPEAT106(macro, data)       MREPEAT105(macro, data)   macro(105, data)
+#define MREPEAT107(macro, data)       MREPEAT106(macro, data)   macro(106, data)
+#define MREPEAT108(macro, data)       MREPEAT107(macro, data)   macro(107, data)
+#define MREPEAT109(macro, data)       MREPEAT108(macro, data)   macro(108, data)
+#define MREPEAT110(macro, data)       MREPEAT109(macro, data)   macro(109, data)
+#define MREPEAT111(macro, data)       MREPEAT110(macro, data)   macro(110, data)
+#define MREPEAT112(macro, data)       MREPEAT111(macro, data)   macro(111, data)
+#define MREPEAT113(macro, data)       MREPEAT112(macro, data)   macro(112, data)
+#define MREPEAT114(macro, data)       MREPEAT113(macro, data)   macro(113, data)
+#define MREPEAT115(macro, data)       MREPEAT114(macro, data)   macro(114, data)
+#define MREPEAT116(macro, data)       MREPEAT115(macro, data)   macro(115, data)
+#define MREPEAT117(macro, data)       MREPEAT116(macro, data)   macro(116, data)
+#define MREPEAT118(macro, data)       MREPEAT117(macro, data)   macro(117, data)
+#define MREPEAT119(macro, data)       MREPEAT118(macro, data)   macro(118, data)
+#define MREPEAT120(macro, data)       MREPEAT119(macro, data)   macro(119, data)
+#define MREPEAT121(macro, data)       MREPEAT120(macro, data)   macro(120, data)
+#define MREPEAT122(macro, data)       MREPEAT121(macro, data)   macro(121, data)
+#define MREPEAT123(macro, data)       MREPEAT122(macro, data)   macro(122, data)
+#define MREPEAT124(macro, data)       MREPEAT123(macro, data)   macro(123, data)
+#define MREPEAT125(macro, data)       MREPEAT124(macro, data)   macro(124, data)
+#define MREPEAT126(macro, data)       MREPEAT125(macro, data)   macro(125, data)
+#define MREPEAT127(macro, data)       MREPEAT126(macro, data)   macro(126, data)
+#define MREPEAT128(macro, data)       MREPEAT127(macro, data)   macro(127, data)
+#define MREPEAT129(macro, data)       MREPEAT128(macro, data)   macro(128, data)
+#define MREPEAT130(macro, data)       MREPEAT129(macro, data)   macro(129, data)
+#define MREPEAT131(macro, data)       MREPEAT130(macro, data)   macro(130, data)
+#define MREPEAT132(macro, data)       MREPEAT131(macro, data)   macro(131, data)
+#define MREPEAT133(macro, data)       MREPEAT132(macro, data)   macro(132, data)
+#define MREPEAT134(macro, data)       MREPEAT133(macro, data)   macro(133, data)
+#define MREPEAT135(macro, data)       MREPEAT134(macro, data)   macro(134, data)
+#define MREPEAT136(macro, data)       MREPEAT135(macro, data)   macro(135, data)
+#define MREPEAT137(macro, data)       MREPEAT136(macro, data)   macro(136, data)
+#define MREPEAT138(macro, data)       MREPEAT137(macro, data)   macro(137, data)
+#define MREPEAT139(macro, data)       MREPEAT138(macro, data)   macro(138, data)
+#define MREPEAT140(macro, data)       MREPEAT139(macro, data)   macro(139, data)
+#define MREPEAT141(macro, data)       MREPEAT140(macro, data)   macro(140, data)
+#define MREPEAT142(macro, data)       MREPEAT141(macro, data)   macro(141, data)
+#define MREPEAT143(macro, data)       MREPEAT142(macro, data)   macro(142, data)
+#define MREPEAT144(macro, data)       MREPEAT143(macro, data)   macro(143, data)
+#define MREPEAT145(macro, data)       MREPEAT144(macro, data)   macro(144, data)
+#define MREPEAT146(macro, data)       MREPEAT145(macro, data)   macro(145, data)
+#define MREPEAT147(macro, data)       MREPEAT146(macro, data)   macro(146, data)
+#define MREPEAT148(macro, data)       MREPEAT147(macro, data)   macro(147, data)
+#define MREPEAT149(macro, data)       MREPEAT148(macro, data)   macro(148, data)
+#define MREPEAT150(macro, data)       MREPEAT149(macro, data)   macro(149, data)
+#define MREPEAT151(macro, data)       MREPEAT150(macro, data)   macro(150, data)
+#define MREPEAT152(macro, data)       MREPEAT151(macro, data)   macro(151, data)
+#define MREPEAT153(macro, data)       MREPEAT152(macro, data)   macro(152, data)
+#define MREPEAT154(macro, data)       MREPEAT153(macro, data)   macro(153, data)
+#define MREPEAT155(macro, data)       MREPEAT154(macro, data)   macro(154, data)
+#define MREPEAT156(macro, data)       MREPEAT155(macro, data)   macro(155, data)
+#define MREPEAT157(macro, data)       MREPEAT156(macro, data)   macro(156, data)
+#define MREPEAT158(macro, data)       MREPEAT157(macro, data)   macro(157, data)
+#define MREPEAT159(macro, data)       MREPEAT158(macro, data)   macro(158, data)
+#define MREPEAT160(macro, data)       MREPEAT159(macro, data)   macro(159, data)
+#define MREPEAT161(macro, data)       MREPEAT160(macro, data)   macro(160, data)
+#define MREPEAT162(macro, data)       MREPEAT161(macro, data)   macro(161, data)
+#define MREPEAT163(macro, data)       MREPEAT162(macro, data)   macro(162, data)
+#define MREPEAT164(macro, data)       MREPEAT163(macro, data)   macro(163, data)
+#define MREPEAT165(macro, data)       MREPEAT164(macro, data)   macro(164, data)
+#define MREPEAT166(macro, data)       MREPEAT165(macro, data)   macro(165, data)
+#define MREPEAT167(macro, data)       MREPEAT166(macro, data)   macro(166, data)
+#define MREPEAT168(macro, data)       MREPEAT167(macro, data)   macro(167, data)
+#define MREPEAT169(macro, data)       MREPEAT168(macro, data)   macro(168, data)
+#define MREPEAT170(macro, data)       MREPEAT169(macro, data)   macro(169, data)
+#define MREPEAT171(macro, data)       MREPEAT170(macro, data)   macro(170, data)
+#define MREPEAT172(macro, data)       MREPEAT171(macro, data)   macro(171, data)
+#define MREPEAT173(macro, data)       MREPEAT172(macro, data)   macro(172, data)
+#define MREPEAT174(macro, data)       MREPEAT173(macro, data)   macro(173, data)
+#define MREPEAT175(macro, data)       MREPEAT174(macro, data)   macro(174, data)
+#define MREPEAT176(macro, data)       MREPEAT175(macro, data)   macro(175, data)
+#define MREPEAT177(macro, data)       MREPEAT176(macro, data)   macro(176, data)
+#define MREPEAT178(macro, data)       MREPEAT177(macro, data)   macro(177, data)
+#define MREPEAT179(macro, data)       MREPEAT178(macro, data)   macro(178, data)
+#define MREPEAT180(macro, data)       MREPEAT179(macro, data)   macro(179, data)
+#define MREPEAT181(macro, data)       MREPEAT180(macro, data)   macro(180, data)
+#define MREPEAT182(macro, data)       MREPEAT181(macro, data)   macro(181, data)
+#define MREPEAT183(macro, data)       MREPEAT182(macro, data)   macro(182, data)
+#define MREPEAT184(macro, data)       MREPEAT183(macro, data)   macro(183, data)
+#define MREPEAT185(macro, data)       MREPEAT184(macro, data)   macro(184, data)
+#define MREPEAT186(macro, data)       MREPEAT185(macro, data)   macro(185, data)
+#define MREPEAT187(macro, data)       MREPEAT186(macro, data)   macro(186, data)
+#define MREPEAT188(macro, data)       MREPEAT187(macro, data)   macro(187, data)
+#define MREPEAT189(macro, data)       MREPEAT188(macro, data)   macro(188, data)
+#define MREPEAT190(macro, data)       MREPEAT189(macro, data)   macro(189, data)
+#define MREPEAT191(macro, data)       MREPEAT190(macro, data)   macro(190, data)
+#define MREPEAT192(macro, data)       MREPEAT191(macro, data)   macro(191, data)
+#define MREPEAT193(macro, data)       MREPEAT192(macro, data)   macro(192, data)
+#define MREPEAT194(macro, data)       MREPEAT193(macro, data)   macro(193, data)
+#define MREPEAT195(macro, data)       MREPEAT194(macro, data)   macro(194, data)
+#define MREPEAT196(macro, data)       MREPEAT195(macro, data)   macro(195, data)
+#define MREPEAT197(macro, data)       MREPEAT196(macro, data)   macro(196, data)
+#define MREPEAT198(macro, data)       MREPEAT197(macro, data)   macro(197, data)
+#define MREPEAT199(macro, data)       MREPEAT198(macro, data)   macro(198, data)
+#define MREPEAT200(macro, data)       MREPEAT199(macro, data)   macro(199, data)
+#define MREPEAT201(macro, data)       MREPEAT200(macro, data)   macro(200, data)
+#define MREPEAT202(macro, data)       MREPEAT201(macro, data)   macro(201, data)
+#define MREPEAT203(macro, data)       MREPEAT202(macro, data)   macro(202, data)
+#define MREPEAT204(macro, data)       MREPEAT203(macro, data)   macro(203, data)
+#define MREPEAT205(macro, data)       MREPEAT204(macro, data)   macro(204, data)
+#define MREPEAT206(macro, data)       MREPEAT205(macro, data)   macro(205, data)
+#define MREPEAT207(macro, data)       MREPEAT206(macro, data)   macro(206, data)
+#define MREPEAT208(macro, data)       MREPEAT207(macro, data)   macro(207, data)
+#define MREPEAT209(macro, data)       MREPEAT208(macro, data)   macro(208, data)
+#define MREPEAT210(macro, data)       MREPEAT209(macro, data)   macro(209, data)
+#define MREPEAT211(macro, data)       MREPEAT210(macro, data)   macro(210, data)
+#define MREPEAT212(macro, data)       MREPEAT211(macro, data)   macro(211, data)
+#define MREPEAT213(macro, data)       MREPEAT212(macro, data)   macro(212, data)
+#define MREPEAT214(macro, data)       MREPEAT213(macro, data)   macro(213, data)
+#define MREPEAT215(macro, data)       MREPEAT214(macro, data)   macro(214, data)
+#define MREPEAT216(macro, data)       MREPEAT215(macro, data)   macro(215, data)
+#define MREPEAT217(macro, data)       MREPEAT216(macro, data)   macro(216, data)
+#define MREPEAT218(macro, data)       MREPEAT217(macro, data)   macro(217, data)
+#define MREPEAT219(macro, data)       MREPEAT218(macro, data)   macro(218, data)
+#define MREPEAT220(macro, data)       MREPEAT219(macro, data)   macro(219, data)
+#define MREPEAT221(macro, data)       MREPEAT220(macro, data)   macro(220, data)
+#define MREPEAT222(macro, data)       MREPEAT221(macro, data)   macro(221, data)
+#define MREPEAT223(macro, data)       MREPEAT222(macro, data)   macro(222, data)
+#define MREPEAT224(macro, data)       MREPEAT223(macro, data)   macro(223, data)
+#define MREPEAT225(macro, data)       MREPEAT224(macro, data)   macro(224, data)
+#define MREPEAT226(macro, data)       MREPEAT225(macro, data)   macro(225, data)
+#define MREPEAT227(macro, data)       MREPEAT226(macro, data)   macro(226, data)
+#define MREPEAT228(macro, data)       MREPEAT227(macro, data)   macro(227, data)
+#define MREPEAT229(macro, data)       MREPEAT228(macro, data)   macro(228, data)
+#define MREPEAT230(macro, data)       MREPEAT229(macro, data)   macro(229, data)
+#define MREPEAT231(macro, data)       MREPEAT230(macro, data)   macro(230, data)
+#define MREPEAT232(macro, data)       MREPEAT231(macro, data)   macro(231, data)
+#define MREPEAT233(macro, data)       MREPEAT232(macro, data)   macro(232, data)
+#define MREPEAT234(macro, data)       MREPEAT233(macro, data)   macro(233, data)
+#define MREPEAT235(macro, data)       MREPEAT234(macro, data)   macro(234, data)
+#define MREPEAT236(macro, data)       MREPEAT235(macro, data)   macro(235, data)
+#define MREPEAT237(macro, data)       MREPEAT236(macro, data)   macro(236, data)
+#define MREPEAT238(macro, data)       MREPEAT237(macro, data)   macro(237, data)
+#define MREPEAT239(macro, data)       MREPEAT238(macro, data)   macro(238, data)
+#define MREPEAT240(macro, data)       MREPEAT239(macro, data)   macro(239, data)
+#define MREPEAT241(macro, data)       MREPEAT240(macro, data)   macro(240, data)
+#define MREPEAT242(macro, data)       MREPEAT241(macro, data)   macro(241, data)
+#define MREPEAT243(macro, data)       MREPEAT242(macro, data)   macro(242, data)
+#define MREPEAT244(macro, data)       MREPEAT243(macro, data)   macro(243, data)
+#define MREPEAT245(macro, data)       MREPEAT244(macro, data)   macro(244, data)
+#define MREPEAT246(macro, data)       MREPEAT245(macro, data)   macro(245, data)
+#define MREPEAT247(macro, data)       MREPEAT246(macro, data)   macro(246, data)
+#define MREPEAT248(macro, data)       MREPEAT247(macro, data)   macro(247, data)
+#define MREPEAT249(macro, data)       MREPEAT248(macro, data)   macro(248, data)
+#define MREPEAT250(macro, data)       MREPEAT249(macro, data)   macro(249, data)
+#define MREPEAT251(macro, data)       MREPEAT250(macro, data)   macro(250, data)
+#define MREPEAT252(macro, data)       MREPEAT251(macro, data)   macro(251, data)
+#define MREPEAT253(macro, data)       MREPEAT252(macro, data)   macro(252, data)
+#define MREPEAT254(macro, data)       MREPEAT253(macro, data)   macro(253, data)
+#define MREPEAT255(macro, data)       MREPEAT254(macro, data)   macro(254, data)
+#define MREPEAT256(macro, data)       MREPEAT255(macro, data)   macro(255, data)
+
+
+#endif  // _MREPEAT_H_
diff --git a/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h
new file mode 100644
index 000000000..47e4cd2e8
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/preprocessor.h
@@ -0,0 +1,52 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _PREPROCESSOR_H_
+#define _PREPROCESSOR_H_
+
+#include "tpaste.h"
+#include "stringz.h"
+#include "mrepeat.h"
+
+
+#endif  // _PREPROCESSOR_H_
diff --git a/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/stringz.h b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/stringz.h
new file mode 100644
index 000000000..fbeb5156c
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/stringz.h
@@ -0,0 +1,72 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor stringizing utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _STRINGZ_H_
+#define _STRINGZ_H_
+
+
+/*! \brief Stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be #defined.
+ *
+ * May be used only within macros with the token passed as an argument if the token is #defined.
+ *
+ * For example, writing STRINGZ(PIN) within a macro #defined by PIN_NAME(PIN)
+ * and invoked as PIN_NAME(PIN0) with PIN0 #defined as A0 is equivalent to
+ * writing "A0".
+ */
+#define STRINGZ(x)                                #x
+
+/*! \brief Absolute stringize.
+ *
+ * Stringize a preprocessing token, this token being allowed to be #defined.
+ *
+ * No restriction of use if the token is #defined.
+ *
+ * For example, writing ASTRINGZ(PIN0) anywhere with PIN0 #defined as A0 is
+ * equivalent to writing "A0".
+ */
+#define ASTRINGZ(x)                               STRINGZ(x)
+
+
+#endif  // _STRINGZ_H_
diff --git a/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h
new file mode 100644
index 000000000..bcedcd01d
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/UTILS/PREPROCESSOR/tpaste.h
@@ -0,0 +1,92 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Preprocessor token pasting utils.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _TPASTE_H_
+#define _TPASTE_H_
+
+
+/*! \name Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be #defined.
+ *
+ * May be used only within macros with the tokens passed as arguments if the tokens are #defined.
+ *
+ * For example, writing TPASTE2(U, WIDTH) within a macro #defined by
+ * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH #defined as 32 is
+ * equivalent to writing U32.
+ */
+//! @{
+#define TPASTE2( a, b)                            a##b
+#define TPASTE3( a, b, c)                         a##b##c
+#define TPASTE4( a, b, c, d)                      a##b##c##d
+#define TPASTE5( a, b, c, d, e)                   a##b##c##d##e
+#define TPASTE6( a, b, c, d, e, f)                a##b##c##d##e##f
+#define TPASTE7( a, b, c, d, e, f, g)             a##b##c##d##e##f##g
+#define TPASTE8( a, b, c, d, e, f, g, h)          a##b##c##d##e##f##g##h
+#define TPASTE9( a, b, c, d, e, f, g, h, i)       a##b##c##d##e##f##g##h##i
+#define TPASTE10(a, b, c, d, e, f, g, h, i, j)    a##b##c##d##e##f##g##h##i##j
+//! @}
+
+/*! \name Absolute Token Paste
+ *
+ * Paste N preprocessing tokens together, these tokens being allowed to be #defined.
+ *
+ * No restriction of use if the tokens are #defined.
+ *
+ * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH #defined
+ * as 32 is equivalent to writing U32.
+ */
+//! @{
+#define ATPASTE2( a, b)                           TPASTE2( a, b)
+#define ATPASTE3( a, b, c)                        TPASTE3( a, b, c)
+#define ATPASTE4( a, b, c, d)                     TPASTE4( a, b, c, d)
+#define ATPASTE5( a, b, c, d, e)                  TPASTE5( a, b, c, d, e)
+#define ATPASTE6( a, b, c, d, e, f)               TPASTE6( a, b, c, d, e, f)
+#define ATPASTE7( a, b, c, d, e, f, g)            TPASTE7( a, b, c, d, e, f, g)
+#define ATPASTE8( a, b, c, d, e, f, g, h)         TPASTE8( a, b, c, d, e, f, g, h)
+#define ATPASTE9( a, b, c, d, e, f, g, h, i)      TPASTE9( a, b, c, d, e, f, g, h, i)
+#define ATPASTE10(a, b, c, d, e, f, g, h, i, j)   TPASTE10(a, b, c, d, e, f, g, h, i, j)
+//! @}
+
+
+#endif  // _TPASTE_H_
diff --git a/Demo/lwIP_AVR32_UC3/UTILS/compiler.h b/Demo/lwIP_AVR32_UC3/UTILS/compiler.h
new file mode 100644
index 000000000..77483303b
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/UTILS/compiler.h
@@ -0,0 +1,880 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Compiler file for AVR32.
+ *
+ * This file defines commonly used types and macros.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _COMPILER_H_
+#define _COMPILER_H_
+
+#if __GNUC__
+#  include 
+#elif __ICCAVR32__ || __AAVR32__
+#  include 
+#  include 
+#  if __ICCAVR32__
+#    include 
+#  endif
+#else
+#  error Unknown compiler
+#endif
+
+#include "preprocessor.h"
+
+
+//_____ D E C L A R A T I O N S ____________________________________________
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+#include 
+#include 
+
+/*! \name Usual Types
+ */
+//! @{
+typedef unsigned char           Bool; //!< Boolean.
+typedef unsigned char           U8 ;  //!< 8-bit unsigned integer.
+typedef unsigned short int      U16;  //!< 16-bit unsigned integer.
+typedef unsigned long int       U32;  //!< 32-bit unsigned integer.
+typedef unsigned long long int  U64;  //!< 64-bit unsigned integer.
+typedef signed char             S8 ;  //!< 8-bit signed integer.
+typedef signed short int        S16;  //!< 16-bit signed integer.
+typedef signed long int         S32;  //!< 32-bit signed integer.
+typedef signed long long int    S64;  //!< 64-bit signed integer.
+typedef float                   F32;  //!< 32-bit floating-point number.
+typedef double                  F64;  //!< 64-bit floating-point number.
+//! @}
+
+/*! \name Status Types
+ */
+//! @{
+typedef Bool                Status_bool_t;  //!< Boolean status.
+typedef U8                  Status_t;       //!< 8-bit-coded status.
+//! @}
+
+#if __ICCAVR32__
+
+/*! \name Compiler Keywords
+ *
+ * Translation of some keywords from GNU GCC for AVR32 to IAR Embedded Workbench for Atmel AVR32.
+ */
+//! @{
+#define __asm__             asm
+#define __inline__          inline
+#define __volatile__
+//! @}
+
+#endif
+
+/*! \name Aliasing Aggregate Types
+ */
+//! @{
+
+//! 16-bit union.
+typedef union
+{
+  U16 u16   ;
+  U8  u8 [2];
+} Union16;
+
+//! 32-bit union.
+typedef union
+{
+  U32 u32   ;
+  U16 u16[2];
+  U8  u8 [4];
+} Union32;
+
+//! 64-bit union.
+typedef union
+{
+  U64 u64   ;
+  U32 u32[2];
+  U16 u16[4];
+  U8  u8 [8];
+} Union64;
+
+//! Union of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  U64 *u64ptr;
+  U32 *u32ptr;
+  U16 *u16ptr;
+  U8  *u8ptr ;
+} UnionPtr;
+
+//! Union of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  volatile U64 *u64ptr;
+  volatile U32 *u32ptr;
+  volatile U16 *u16ptr;
+  volatile U8  *u8ptr ;
+} UnionVPtr;
+
+//! Union of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  const U64 *u64ptr;
+  const U32 *u32ptr;
+  const U16 *u16ptr;
+  const U8  *u8ptr ;
+} UnionCPtr;
+
+//! Union of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef union
+{
+  const volatile U64 *u64ptr;
+  const volatile U32 *u32ptr;
+  const volatile U16 *u16ptr;
+  const volatile U8  *u8ptr ;
+} UnionCVPtr;
+
+//! Structure of pointers to 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  U64 *u64ptr;
+  U32 *u32ptr;
+  U16 *u16ptr;
+  U8  *u8ptr ;
+} StructPtr;
+
+//! Structure of pointers to volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  volatile U64 *u64ptr;
+  volatile U32 *u32ptr;
+  volatile U16 *u16ptr;
+  volatile U8  *u8ptr ;
+} StructVPtr;
+
+//! Structure of pointers to constant 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  const U64 *u64ptr;
+  const U32 *u32ptr;
+  const U16 *u16ptr;
+  const U8  *u8ptr ;
+} StructCPtr;
+
+//! Structure of pointers to constant volatile 64-, 32-, 16- and 8-bit unsigned integers.
+typedef struct
+{
+  const volatile U64 *u64ptr;
+  const volatile U32 *u32ptr;
+  const volatile U16 *u16ptr;
+  const volatile U8  *u8ptr ;
+} StructCVPtr;
+
+//! @}
+
+#endif  // __AVR32_ABI_COMPILER__
+
+//_____ M A C R O S ________________________________________________________
+
+/*! \name Usual Constants
+ */
+//! @{
+#define DISABLE   0
+#define ENABLE    1
+#define DISABLED  0
+#define ENABLED   1
+#define OFF       0
+#define ON        1
+#define FALSE     0
+#define TRUE      1
+#define KO        0
+#define OK        1
+#define PASS      0
+#define FAIL      1
+#define LOW       0
+#define HIGH      1
+#define CLR       0
+#define SET       1
+//! @}
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \name Bit-Field Handling Macros
+ */
+//! @{
+
+/*! \brief Reads the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value to read bits from.
+ * \param mask  Bit-mask indicating bits to read.
+ *
+ * \return Read bits.
+ */
+#define Rd_bits( value, mask)        ((value) & (mask))
+
+/*! \brief Writes the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue to write bits to.
+ * \param mask    Bit-mask indicating bits to write.
+ * \param bits    Bits to write.
+ *
+ * \return Resulting value with written bits.
+ */
+#define Wr_bits(lvalue, mask, bits)  ((lvalue) = ((lvalue) & ~(mask)) |\
+                                                 ((bits  ) &  (mask)))
+
+/*! \brief Tests the bits of a value specified by a given bit-mask.
+ *
+ * \param value Value of which to test bits.
+ * \param mask  Bit-mask indicating bits to test.
+ *
+ * \return \c 1 if at least one of the tested bits is set, else \c 0.
+ */
+#define Tst_bits( value, mask)  (Rd_bits(value, mask) != 0)
+
+/*! \brief Clears the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to clear bits.
+ * \param mask    Bit-mask indicating bits to clear.
+ *
+ * \return Resulting value with cleared bits.
+ */
+#define Clr_bits(lvalue, mask)  ((lvalue) &= ~(mask))
+
+/*! \brief Sets the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to set bits.
+ * \param mask    Bit-mask indicating bits to set.
+ *
+ * \return Resulting value with set bits.
+ */
+#define Set_bits(lvalue, mask)  ((lvalue) |=  (mask))
+
+/*! \brief Toggles the bits of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue  C lvalue of which to toggle bits.
+ * \param mask    Bit-mask indicating bits to toggle.
+ *
+ * \return Resulting value with toggled bits.
+ */
+#define Tgl_bits(lvalue, mask)  ((lvalue) ^=  (mask))
+
+/*! \brief Reads the bit-field of a value specified by a given bit-mask.
+ *
+ * \param value Value to read a bit-field from.
+ * \param mask  Bit-mask indicating the bit-field to read.
+ *
+ * \return Read bit-field.
+ */
+#define Rd_bitfield( value, mask)           (Rd_bits( value, mask) >> ctz(mask))
+
+/*! \brief Writes the bit-field of a C lvalue specified by a given bit-mask.
+ *
+ * \param lvalue    C lvalue to write a bit-field to.
+ * \param mask      Bit-mask indicating the bit-field to write.
+ * \param bitfield  Bit-field to write.
+ *
+ * \return Resulting value with written bit-field.
+ */
+#define Wr_bitfield(lvalue, mask, bitfield) (Wr_bits(lvalue, mask, (U32)(bitfield) << ctz(mask)))
+
+//! @}
+
+/*! \brief This macro is used to test fatal errors.
+ *
+ * The macro tests if the expression is FALSE. If it is, a fatal error is
+ * detected and the application hangs up.
+ *
+ * \param expr  Expression to evaluate and supposed to be nonzero.
+ */
+#ifdef _ASSERT_ENABLE_
+  #define Assert(expr) \
+  {\
+    if (!(expr)) while (TRUE);\
+  }
+#else
+  #define Assert(expr)
+#endif
+
+/*! \name Zero-Bit Counting Macros
+ *
+ * Under AVR32-GCC, __builtin_clz and __builtin_ctz behave like macros when
+ * applied to constant expressions (values known at compile time), so they are
+ * more optimized than the use of the corresponding assembly instructions and
+ * they can be used as constant expressions e.g. to initialize objects having
+ * static storage duration, and like the corresponding assembly instructions
+ * when applied to non-constant expressions (values unknown at compile time), so
+ * they are more optimized than an assembly periphrasis. Hence, clz and ctz
+ * ensure a possible and optimized behavior for both constant and non-constant
+ * expressions.
+ */
+//! @{
+
+/*! \brief Counts the leading zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the leading zero bits.
+ *
+ * \return The count of leading zero bits in \a u.
+ */
+#if __GNUC__
+  #define clz(u)              __builtin_clz(u)
+#elif __ICCAVR32__
+  #define clz(u)              __count_leading_zeros(u)
+#endif
+
+/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer.
+ *
+ * \param u Value of which to count the trailing zero bits.
+ *
+ * \return The count of trailing zero bits in \a u.
+ */
+#if __GNUC__
+  #define ctz(u)              __builtin_ctz(u)
+#elif __ICCAVR32__
+  #define ctz(u)              __count_trailing_zeros(u)
+#endif
+
+//! @}
+
+/*! \name Alignment Macros
+ */
+//! @{
+
+/*! \brief Tests alignment of the number \a val with the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return \c 1 if the number \a val is aligned with the \a n boundary, else \c 0.
+ */
+#define Test_align(val, n     ) (!Tst_bits( val, (n) - 1     )   )
+
+/*! \brief Gets alignment of the number \a val with respect to the \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return Alignment of the number \a val with respect to the \a n boundary.
+ */
+#define Get_align( val, n     ) (  Rd_bits( val, (n) - 1     )   )
+
+/*! \brief Sets alignment of the lvalue number \a lval to \a alg with respect to the \a n boundary.
+ *
+ * \param lval  Input/output lvalue.
+ * \param n     Boundary.
+ * \param alg   Alignment.
+ *
+ * \return New value of \a lval resulting from its alignment set to \a alg with respect to the \a n boundary.
+ */
+#define Set_align(lval, n, alg) (  Wr_bits(lval, (n) - 1, alg)   )
+
+/*! \brief Aligns the number \a val with the upper \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the upper \a n boundary.
+ */
+#define Align_up(  val, n     ) (((val) + ((n) - 1)) & ~((n) - 1))
+
+/*! \brief Aligns the number \a val with the lower \a n boundary.
+ *
+ * \param val Input value.
+ * \param n   Boundary.
+ *
+ * \return Value resulting from the number \a val aligned with the lower \a n boundary.
+ */
+#define Align_down(val, n     ) ( (val)              & ~((n) - 1))
+
+//! @}
+
+/*! \name Mathematics Macros
+ *
+ * The same considerations as for clz and ctz apply here but AVR32-GCC does not
+ * provide built-in functions to access the assembly instructions abs, min and
+ * max and it does not produce them by itself in most cases, so two sets of
+ * macros are defined here:
+ *   - Abs, Min and Max to apply to constant expressions (values known at
+ *     compile time);
+ *   - abs, min and max to apply to non-constant expressions (values unknown at
+ *     compile time).
+ */
+//! @{
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Abs(a)              (((a) <  0 ) ? -(a) : (a))
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Min(a, b)           (((a) < (b)) ?  (a) : (b))
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Max(a, b)           (((a) > (b)) ?  (a) : (b))
+
+/*! \brief Takes the absolute value of \a a.
+ *
+ * \param a Input value.
+ *
+ * \return Absolute value of \a a.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define abs(a) \
+  (\
+    {\
+      int __value = (a);\
+      __asm__ ("abs\t%0" : "+r" (__value) :  : "cc");\
+      __value;\
+    }\
+  )
+#elif __ICCAVR32__
+  #define abs(a)      Abs(a)
+#endif
+
+/*! \brief Takes the minimal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Minimal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define min(a, b) \
+  (\
+    {\
+      int __value, __arg_a = (a), __arg_b = (b);\
+      __asm__ ("min\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
+      __value;\
+    }\
+  )
+#elif __ICCAVR32__
+  #define min(a, b)   Min(a, b)
+#endif
+
+/*! \brief Takes the maximal value of \a a and \a b.
+ *
+ * \param a Input value.
+ * \param b Input value.
+ *
+ * \return Maximal value of \a a and \a b.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define max(a, b) \
+  (\
+    {\
+      int __value, __arg_a = (a), __arg_b = (b);\
+      __asm__ ("max\t%0, %1, %2" : "=r" (__value) : "r" (__arg_a), "r" (__arg_b));\
+      __value;\
+    }\
+  )
+#elif __ICCAVR32__
+  #define max(a, b)   Max(a, b)
+#endif
+
+//! @}
+
+/*! \brief Calls the routine at address \a addr.
+ *
+ * It generates a long call opcode.
+ *
+ * For example, `Long_call(0x80000000)' generates a software reset on a UC3 if
+ * it is invoked from the CPU supervisor mode.
+ *
+ * \param addr  Address of the routine to call.
+ *
+ * \note It may be used as a long jump opcode in some special cases.
+ */
+#define Long_call(addr)                   ((*(void (*)(void))(addr))())
+
+/*! \brief Resets the CPU by software.
+ *
+ * \warning It shall not be called from the CPU application mode.
+ */
+#if __GNUC__
+  #define Reset_CPU() \
+  (\
+    {\
+      __asm__ __volatile__ (\
+        "lda.w   r8, _start\n\t"\
+        "lddpc   r9, 1f\n\t"\
+        "stm     --sp, r8-r9\n\t"\
+        "mfsr    r8, %[SR]\n\t"\
+        "bfextu  r8, r8, %[SR_MX_OFFSET], %[SR_MX_SIZE]\n\t"\
+        "cp.w    r8, 0b001\n\t"\
+        "breq    0f\n\t"\
+        "rete\n"\
+        "0:\n\t"\
+        "rets\n\t"\
+        ".balign 4\n"\
+        "1:\n\t"\
+        ".word   %[RESET_SR]"\
+        :\
+        : [SR] "i" (AVR32_SR),\
+          [SR_MX_OFFSET] "i" (AVR32_SR_M0_OFFSET),\
+          [SR_MX_SIZE] "i" (AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE),\
+          [RESET_SR] "i" (AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)\
+      );\
+    }\
+  )
+#elif __ICCAVR32__
+  #define Reset_CPU() \
+  {\
+    extern void *volatile __program_start;\
+    __asm__ __volatile__ (\
+      "mov     r8, LWRD(__program_start)\n\t"\
+      "orh     r8, HWRD(__program_start)\n\t"\
+      "mov     r9, LWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\
+      "orh     r9, HWRD("ASTRINGZ(AVR32_SR_GM_MASK | AVR32_SR_EM_MASK | AVR32_SR_M0_MASK)")\n\t"\
+      "stm     --sp, r8-r9\n\t"\
+      "mfsr    r8, "ASTRINGZ(AVR32_SR)"\n\t"\
+      "bfextu  r8, r8, "ASTRINGZ(AVR32_SR_M0_OFFSET)", "ASTRINGZ(AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE)"\n\t"\
+      "cp.w    r8, 001b\n\t"\
+      "breq    $ + 4\n\t"\
+      "rete\n\t"\
+      "rets"\
+    );\
+    __program_start;\
+}
+#endif
+
+/*! \name CPU Status Register Macros
+ */
+//! @{
+
+/*! \brief Disables all exceptions.
+ */
+#if __GNUC__
+  #define Disable_global_exception()        ({__asm__ __volatile__ ("ssrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})
+#elif __ICCAVR32__
+  #define Disable_global_exception()        (__set_status_flag(AVR32_SR_EM_OFFSET))
+#endif
+
+/*! \brief Enables all exceptions.
+ */
+#if __GNUC__
+  #define Enable_global_exception()         ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_EM_OFFSET));})
+#elif __ICCAVR32__
+  #define Enable_global_exception()         (__clear_status_flag(AVR32_SR_EM_OFFSET))
+#endif
+
+/*! \brief Disables all interrupts.
+ */
+#if __GNUC__
+  #define Disable_global_interrupt()        ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" :  : "i" (AVR32_SR_GM_OFFSET));})
+#elif __ICCAVR32__
+  #define Disable_global_interrupt()        {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(AVR32_SR_GM_OFFSET)"\n\tnop\n\tnop");}
+#endif
+
+/*! \brief Enables all interrupts.
+ */
+#if __GNUC__
+  #define Enable_global_interrupt()         ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (AVR32_SR_GM_OFFSET));})
+#elif __ICCAVR32__
+  #define Enable_global_interrupt()         (__enable_interrupt())
+#endif
+
+/*! \brief Disables interrupt level \a int_lev.
+ *
+ * \param int_lev Interrupt level to disable (0 to 3).
+ */
+#if __GNUC__
+  #define Disable_interrupt_level(int_lev)  ({__asm__ __volatile__ ("ssrf\t%0\n\tnop\n\tnop" :  : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
+#elif __ICCAVR32__
+  #define Disable_interrupt_level(int_lev)  {__asm__ __volatile__ ("ssrf\t"ASTRINGZ(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET))"\n\tnop\n\tnop");}
+#endif
+
+/*! \brief Enables interrupt level \a int_lev.
+ *
+ * \param int_lev Interrupt level to enable (0 to 3).
+ */
+#if __GNUC__
+  #define Enable_interrupt_level(int_lev)   ({__asm__ __volatile__ ("csrf\t%0" :  : "i" (TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)));})
+#elif __ICCAVR32__
+  #define Enable_interrupt_level(int_lev)   (__clear_status_flag(TPASTE3(AVR32_SR_I, int_lev, M_OFFSET)))
+#endif
+
+//! @}
+
+/*! \name System Register Access Macros
+ */
+//! @{
+
+/*! \brief Gets the value of the \a sysreg system register.
+ *
+ * \param sysreg  Address of the system register of which to get the value.
+ *
+ * \return Value of the \a sysreg system register.
+ */
+#if __GNUC__
+  #define Get_system_register(sysreg)         __builtin_mfsr(sysreg)
+#elif __ICCAVR32__
+  #define Get_system_register(sysreg)         __get_system_register(sysreg)
+#endif
+
+/*! \brief Sets the value of the \a sysreg system register to \a value.
+ *
+ * \param sysreg  Address of the system register of which to set the value.
+ * \param value   Value to set the \a sysreg system register to.
+ */
+#if __GNUC__
+  #define Set_system_register(sysreg, value)  __builtin_mtsr(sysreg, value)
+#elif __ICCAVR32__
+  #define Set_system_register(sysreg, value)  __set_system_register(sysreg, value)
+#endif
+
+//! @}
+
+#endif  // __AVR32_ABI_COMPILER__
+
+//! Boolean evaluating MCU little endianism.
+#if (__GNUC__ && __AVR32__) || (__ICCAVR32__ || __AAVR32__)
+  #define LITTLE_ENDIAN_MCU     FALSE
+#endif
+
+// Check that MCU endianism is correctly defined.
+#ifndef LITTLE_ENDIAN_MCU
+  #error YOU MUST define the MCU endianism with LITTLE_ENDIAN_MCU: either FALSE or TRUE
+#endif
+
+//! Boolean evaluating MCU big endianism.
+#define BIG_ENDIAN_MCU        (!LITTLE_ENDIAN_MCU)
+
+#ifdef __AVR32_ABI_COMPILER__ // Automatically defined when compiling for AVR32, not when assembling.
+
+/*! \name U16/U32/U64 MCU Endianism Handling Macros
+ */
+//! @{
+#if LITTLE_ENDIAN_MCU
+  #define LSB(u16)        (((U8  *)&(u16))[0])  //!< Least significant byte of \a u16.
+  #define MSB(u16)        (((U8  *)&(u16))[1])  //!< Most significant byte of \a u16.
+  #define LSH(u32)        (((U16 *)&(u32))[0])  //!< Least significant half-word of \a u32.
+  #define MSH(u32)        (((U16 *)&(u32))[1])  //!< Most significant half-word of \a u32.
+  #define LSB0W(u32)      (((U8  *)&(u32))[0])  //!< Least significant byte of 1st rank of \a u32.
+  #define LSB1W(u32)      (((U8  *)&(u32))[1])  //!< Least significant byte of 2nd rank of \a u32.
+  #define LSB2W(u32)      (((U8  *)&(u32))[2])  //!< Least significant byte of 3rd rank of \a u32.
+  #define LSB3W(u32)      (((U8  *)&(u32))[3])  //!< Least significant byte of 4th rank of \a u32.
+  #define MSB3W(u32)      LSB0W(u32)            //!< Most significant byte of 1st rank of \a u32.
+  #define MSB2W(u32)      LSB1W(u32)            //!< Most significant byte of 2nd rank of \a u32.
+  #define MSB1W(u32)      LSB2W(u32)            //!< Most significant byte of 3rd rank of \a u32.
+  #define MSB0W(u32)      LSB3W(u32)            //!< Most significant byte of 4th rank of \a u32.
+  #define LSW(u64)        (((U32 *)&(u64))[0])  //!< Least significant word of \a u64.
+  #define MSW(u64)        (((U32 *)&(u64))[1])  //!< Most significant word of \a u64.
+  #define LSH0(u64)       (((U16 *)&(u64))[0])  //!< Least significant half-word of 1st rank of \a u64.
+  #define LSH1(u64)       (((U16 *)&(u64))[1])  //!< Least significant half-word of 2nd rank of \a u64.
+  #define LSH2(u64)       (((U16 *)&(u64))[2])  //!< Least significant half-word of 3rd rank of \a u64.
+  #define LSH3(u64)       (((U16 *)&(u64))[3])  //!< Least significant half-word of 4th rank of \a u64.
+  #define MSH3(u64)       LSH0(u64)             //!< Most significant half-word of 1st rank of \a u64.
+  #define MSH2(u64)       LSH1(u64)             //!< Most significant half-word of 2nd rank of \a u64.
+  #define MSH1(u64)       LSH2(u64)             //!< Most significant half-word of 3rd rank of \a u64.
+  #define MSH0(u64)       LSH3(u64)             //!< Most significant half-word of 4th rank of \a u64.
+  #define LSB0D(u64)      (((U8  *)&(u64))[0])  //!< Least significant byte of 1st rank of \a u64.
+  #define LSB1D(u64)      (((U8  *)&(u64))[1])  //!< Least significant byte of 2nd rank of \a u64.
+  #define LSB2D(u64)      (((U8  *)&(u64))[2])  //!< Least significant byte of 3rd rank of \a u64.
+  #define LSB3D(u64)      (((U8  *)&(u64))[3])  //!< Least significant byte of 4th rank of \a u64.
+  #define LSB4D(u64)      (((U8  *)&(u64))[4])  //!< Least significant byte of 5th rank of \a u64.
+  #define LSB5D(u64)      (((U8  *)&(u64))[5])  //!< Least significant byte of 6th rank of \a u64.
+  #define LSB6D(u64)      (((U8  *)&(u64))[6])  //!< Least significant byte of 7th rank of \a u64.
+  #define LSB7D(u64)      (((U8  *)&(u64))[7])  //!< Least significant byte of 8th rank of \a u64.
+  #define MSB7D(u64)      LSB0D(u64)            //!< Most significant byte of 1st rank of \a u64.
+  #define MSB6D(u64)      LSB1D(u64)            //!< Most significant byte of 2nd rank of \a u64.
+  #define MSB5D(u64)      LSB2D(u64)            //!< Most significant byte of 3rd rank of \a u64.
+  #define MSB4D(u64)      LSB3D(u64)            //!< Most significant byte of 4th rank of \a u64.
+  #define MSB3D(u64)      LSB4D(u64)            //!< Most significant byte of 5th rank of \a u64.
+  #define MSB2D(u64)      LSB5D(u64)            //!< Most significant byte of 6th rank of \a u64.
+  #define MSB1D(u64)      LSB6D(u64)            //!< Most significant byte of 7th rank of \a u64.
+  #define MSB0D(u64)      LSB7D(u64)            //!< Most significant byte of 8th rank of \a u64.
+#else // BIG_ENDIAN_MCU
+  #define MSB(u16)        (((U8  *)&(u16))[0])  //!< Most significant byte of \a u16.
+  #define LSB(u16)        (((U8  *)&(u16))[1])  //!< Least significant byte of \a u16.
+  #define MSH(u32)        (((U16 *)&(u32))[0])  //!< Most significant half-word of \a u32.
+  #define LSH(u32)        (((U16 *)&(u32))[1])  //!< Least significant half-word of \a u32.
+  #define MSB0W(u32)      (((U8  *)&(u32))[0])  //!< Most significant byte of 1st rank of \a u32.
+  #define MSB1W(u32)      (((U8  *)&(u32))[1])  //!< Most significant byte of 2nd rank of \a u32.
+  #define MSB2W(u32)      (((U8  *)&(u32))[2])  //!< Most significant byte of 3rd rank of \a u32.
+  #define MSB3W(u32)      (((U8  *)&(u32))[3])  //!< Most significant byte of 4th rank of \a u32.
+  #define LSB3W(u32)      MSB0W(u32)            //!< Least significant byte of 1st rank of \a u32.
+  #define LSB2W(u32)      MSB1W(u32)            //!< Least significant byte of 2nd rank of \a u32.
+  #define LSB1W(u32)      MSB2W(u32)            //!< Least significant byte of 3rd rank of \a u32.
+  #define LSB0W(u32)      MSB3W(u32)            //!< Least significant byte of 4th rank of \a u32.
+  #define MSW(u64)        (((U32 *)&(u64))[0])  //!< Most significant word of \a u64.
+  #define LSW(u64)        (((U32 *)&(u64))[1])  //!< Least significant word of \a u64.
+  #define MSH0(u64)       (((U16 *)&(u64))[0])  //!< Most significant half-word of 1st rank of \a u64.
+  #define MSH1(u64)       (((U16 *)&(u64))[1])  //!< Most significant half-word of 2nd rank of \a u64.
+  #define MSH2(u64)       (((U16 *)&(u64))[2])  //!< Most significant half-word of 3rd rank of \a u64.
+  #define MSH3(u64)       (((U16 *)&(u64))[3])  //!< Most significant half-word of 4th rank of \a u64.
+  #define LSH3(u64)       MSH0(u64)             //!< Least significant half-word of 1st rank of \a u64.
+  #define LSH2(u64)       MSH1(u64)             //!< Least significant half-word of 2nd rank of \a u64.
+  #define LSH1(u64)       MSH2(u64)             //!< Least significant half-word of 3rd rank of \a u64.
+  #define LSH0(u64)       MSH3(u64)             //!< Least significant half-word of 4th rank of \a u64.
+  #define MSB0D(u64)      (((U8  *)&(u64))[0])  //!< Most significant byte of 1st rank of \a u64.
+  #define MSB1D(u64)      (((U8  *)&(u64))[1])  //!< Most significant byte of 2nd rank of \a u64.
+  #define MSB2D(u64)      (((U8  *)&(u64))[2])  //!< Most significant byte of 3rd rank of \a u64.
+  #define MSB3D(u64)      (((U8  *)&(u64))[3])  //!< Most significant byte of 4th rank of \a u64.
+  #define MSB4D(u64)      (((U8  *)&(u64))[4])  //!< Most significant byte of 5th rank of \a u64.
+  #define MSB5D(u64)      (((U8  *)&(u64))[5])  //!< Most significant byte of 6th rank of \a u64.
+  #define MSB6D(u64)      (((U8  *)&(u64))[6])  //!< Most significant byte of 7th rank of \a u64.
+  #define MSB7D(u64)      (((U8  *)&(u64))[7])  //!< Most significant byte of 8th rank of \a u64.
+  #define LSB7D(u64)      MSB0D(u64)            //!< Least significant byte of 1st rank of \a u64.
+  #define LSB6D(u64)      MSB1D(u64)            //!< Least significant byte of 2nd rank of \a u64.
+  #define LSB5D(u64)      MSB2D(u64)            //!< Least significant byte of 3rd rank of \a u64.
+  #define LSB4D(u64)      MSB3D(u64)            //!< Least significant byte of 4th rank of \a u64.
+  #define LSB3D(u64)      MSB4D(u64)            //!< Least significant byte of 5th rank of \a u64.
+  #define LSB2D(u64)      MSB5D(u64)            //!< Least significant byte of 6th rank of \a u64.
+  #define LSB1D(u64)      MSB6D(u64)            //!< Least significant byte of 7th rank of \a u64.
+  #define LSB0D(u64)      MSB7D(u64)            //!< Least significant byte of 8th rank of \a u64.
+#endif
+//! @}
+
+/*! \name Endianism Conversion Macros
+ *
+ * The same considerations as for clz and ctz apply here but AVR32-GCC's
+ * __builtin_bswap_16 and __builtin_bswap_32 do not behave like macros when
+ * applied to constant expressions, so two sets of macros are defined here:
+ *   - Swap16, Swap32 and Swap64 to apply to constant expressions (values known
+ *     at compile time);
+ *   - swap16, swap32 and swap64 to apply to non-constant expressions (values
+ *     unknown at compile time).
+ */
+//! @{
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap16(u16) ((U16)(((U16)(u16) >> 8) |\
+                           ((U16)(u16) << 8)))
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap32(u32) ((U32)(((U32)Swap16((U32)(u32) >> 16)) |\
+                           ((U32)Swap16((U32)(u32)) << 16)))
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values known at compile time.
+ */
+#define Swap64(u64) ((U64)(((U64)Swap32((U64)(u64) >> 32)) |\
+                           ((U64)Swap32((U64)(u64)) << 32)))
+
+/*! \brief Toggles the endianism of \a u16 (by swapping its bytes).
+ *
+ * \param u16 U16 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u16 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define swap16(u16) __builtin_bswap_16(u16)
+#elif __ICCAVR32__
+  #define swap16(u16) Swap16(u16)
+#endif
+
+/*! \brief Toggles the endianism of \a u32 (by swapping its bytes).
+ *
+ * \param u32 U32 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u32 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#if __GNUC__
+  #define swap32(u32) __builtin_bswap_32(u32)
+#elif __ICCAVR32__
+  #define swap32(u32) Swap32(u32)
+#endif
+
+/*! \brief Toggles the endianism of \a u64 (by swapping its bytes).
+ *
+ * \param u64 U64 of which to toggle the endianism.
+ *
+ * \return Value resulting from \a u64 with toggled endianism.
+ *
+ * \note More optimized if only used with values unknown at compile time.
+ */
+#define swap64(u64) ((U64)(((U64)swap32((U64)(u64) >> 32)) |\
+                           ((U64)swap32((U64)(u64)) << 32)))
+
+//! @}
+
+#endif  // __AVR32_ABI_COMPILER__
+
+
+#endif  // _COMPILER_H_
diff --git a/Demo/lwIP_AVR32_UC3/conf_eth.h b/Demo/lwIP_AVR32_UC3/conf_eth.h
new file mode 100644
index 000000000..bc19a9e2b
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/conf_eth.h
@@ -0,0 +1,143 @@
+/* This header file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file ******************************************************************
+ *
+ * \brief Ethernet module configuration file.
+ *
+ * This file contains the possible external configuration of the Ethernet module.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ ***************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef _CONF_ETH_H_
+#define _CONF_ETH_H_
+
+/*! define stack size for WEB server task */
+#define lwipBASIC_WEB_SERVER_STACK_SIZE   256
+
+/*! define stack size for TFTP server task */
+#define lwipBASIC_TFTP_SERVER_STACK_SIZE  1024
+
+/*! define stack size for SMTP host task */
+#define lwipBASIC_SMTP_HOST_STACK_SIZE    256
+
+/*! define stack size for lwIP task */
+#define lwipINTERFACE_STACK_SIZE          512
+
+/*! define stack size for netif task */
+#define netifINTERFACE_TASK_STACK_SIZE    256
+
+/*! define WEB server priority */
+#define ethWEBSERVER_PRIORITY             ( tskIDLE_PRIORITY + 2 )
+
+/*! define TFTP server priority */
+#define ethTFTPSERVER_PRIORITY            ( tskIDLE_PRIORITY + 3 )
+
+/*! define SMTP host priority */
+#define ethSMTPHOST_PRIORITY              ( tskIDLE_PRIORITY + 5 )
+
+/*! define lwIP task priority */
+#define lwipINTERFACE_TASK_PRIORITY       ( configMAX_PRIORITIES - 1 )
+
+/*! define netif task priority */
+#define netifINTERFACE_TASK_PRIORITY      ( configMAX_PRIORITIES - 1 )
+
+/*! Number of threads that can be started with sys_thread_new() */
+#define SYS_THREAD_MAX                      6
+
+/*! LED used by the ethernet task, toggled on each activation */
+#define webCONN_LED                         7
+
+/*! Use Auto Negociation to get speed and duplex */
+#define ETHERNET_CONF_AN_ENABLE                      1
+
+/*! Do not use auto cross capability */
+#define ETHERNET_CONF_AUTO_CROSS_ENABLE              0
+/*! use direct cable */
+#define ETHERNET_CONF_CROSSED_LINK                   0
+
+
+/* ethernet default parameters */
+/*! MAC address definition.  The MAC address must be unique on the network. */
+#define emacETHADDR0                        0x00
+#define emacETHADDR1                        0x04
+#define emacETHADDR2                        0x25
+#define emacETHADDR3                        0x40
+#define emacETHADDR4                        0x40
+#define emacETHADDR5                        0x40
+
+#if 0
+/*! The IP address being used. */
+#define emacIPADDR0           10
+#define emacIPADDR1           172
+#define emacIPADDR2           214
+#define emacIPADDR3           40
+
+/*! The gateway address being used. */
+#define emacGATEWAY_ADDR0     10
+#define emacGATEWAY_ADDR1     172
+#define emacGATEWAY_ADDR2     250
+#define emacGATEWAY_ADDR3     1
+
+/*! The network mask being used. */
+#define emacNET_MASK0         255
+#define emacNET_MASK1         255
+#define emacNET_MASK2         0
+#define emacNET_MASK3         0
+
+#else
+/*! The IP address being used. */
+#define emacIPADDR0                         192
+#define emacIPADDR1                         168
+#define emacIPADDR2                         0
+#define emacIPADDR3                         2
+
+/*! The gateway address being used. */
+#define emacGATEWAY_ADDR0                   192
+#define emacGATEWAY_ADDR1                   168
+#define emacGATEWAY_ADDR2                   0
+#define emacGATEWAY_ADDR3                   1
+
+/*! The network mask being used. */
+#define emacNET_MASK0                       255
+#define emacNET_MASK1                       255
+#define emacNET_MASK2                       255
+#define emacNET_MASK3                       0
+#endif
+
+#endif
diff --git a/Demo/lwIP_AVR32_UC3/main.c b/Demo/lwIP_AVR32_UC3/main.c
new file mode 100644
index 000000000..9a398313b
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/main.c
@@ -0,0 +1,147 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS and lwIP example for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Environment include files. */
+#include 
+#include 
+#include "pm.h"
+#include "flashc.h"
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Demo file headers. */
+#include "partest.h"
+#include "serial.h"
+#include "ethernet.h"
+#include "netif/etharp.h"
+#include "flash.h"
+
+/* Priority definitions for most of the tasks in the demo application. */
+#define mainLED_TASK_PRIORITY     ( tskIDLE_PRIORITY + 1 )
+#define mainETH_TASK_PRIORITY     ( tskIDLE_PRIORITY + 1 )
+
+/* Baud rate used by the serial port tasks. */
+#define mainCOM_BAUD_RATE      ( ( unsigned portLONG ) 57600 )
+#define mainCOM_BUFFER_LEN     ( ( unsigned portLONG ) 70 )
+
+/* An address in the internal Flash used to count resets.  This is used to check that
+the demo application is not unexpectedly resetting. */
+#define mainRESET_COUNT_ADDRESS     ( ( void * ) 0xC0000000 )
+
+
+//!
+//! \fn     main
+//! \brief  start the software here
+//!         1) Initialize the microcontroller and the shared hardware resources
+//!         of the board.
+//!         2) Launch the IP modules.
+//!         3) Start FreeRTOS.
+//! \return 42, which should never occur.
+//! \note
+//!
+int main( void )
+{
+volatile avr32_pm_t* pm = &AVR32_PM;
+
+	/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
+
+	/* Switch to external oscillator 0 */
+	pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
+
+	/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
+	   Extra div by 2 => 96MHz */
+	pm_pll_setup(pm,	/* volatile avr32_pm_t* pm */
+				0,		/* unsigned int pll */
+				15,		/* unsigned int mul */
+				1,		/* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
+				0,		/* unsigned int osc */
+				16);		/* unsigned int lockcount */
+
+	pm_pll_set_option( pm, 0,   // pll0
+	                       0,   // Choose the range 160-240MHz.
+	                       1,   // div2
+	                       0 ); // wbwdisable
+
+	/* Enable PLL0 */
+	pm_pll_enable(pm,0);
+
+	/* Wait for PLL0 locked */
+	pm_wait_for_pll0_locked(pm) ;
+
+	/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
+	pm_gc_setup(pm,
+				0,
+				1, /* Use Osc (=0) or PLL (=1) */
+				0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
+				0,
+				1);
+
+	/* Enable Generic clock 0*/
+	pm_gc_enable(pm, 0);
+
+	/* switch to clock */
+	pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
+	flashc_set_wait_state( 1 );
+	pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
+
+	/* Setup the LED's for output. */
+	vParTestInitialise();
+
+	/* Start the flash tasks just to provide visual feedback that the demo is
+	executing. */
+	vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
+
+	/* 2) Start ethernet task. */
+	vStartEthernetTask( mainETH_TASK_PRIORITY );
+
+	/* 3) Start FreeRTOS. */
+	vTaskStartScheduler();
+
+	/* Will only reach here if there was insufficient memory to create the idle task. */
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
diff --git a/Demo/lwIP_AVR32_UC3/printf-stdarg.c b/Demo/lwIP_AVR32_UC3/printf-stdarg.c
new file mode 100644
index 000000000..75dfab73d
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/printf-stdarg.c
@@ -0,0 +1,315 @@
+/* This source file is part of the ATMEL FREERTOS-0.9.0 Release */
+
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief sprintf functions to replace newlib for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation: http://www.atmel.com \n
+ *                       Support email: avr32@atmel.com
+ *
+ *****************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+	Copyright 2001, 2002 Georges Menie (www.menie.org)
+	stdarg version contributed by Christian Ettinger
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU Lesser General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU Lesser General Public License for more details.
+
+    You should have received a copy of the GNU Lesser General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+/*
+	putchar is the only external dependency for this file,
+	if you have a working putchar, leave it commented out.
+	If not, uncomment the define below and
+	replace outbyte(c) by your own function call.
+
+#define putchar(c) outbyte(c)
+*/
+
+#include 
+#include 
+
+
+static void printchar(char **str, int c)
+{
+	extern int putchar(int c);
+	
+	if (str) {
+		**str = c;
+		++(*str);
+	}
+	else (void)putchar(c);
+}
+
+#define PAD_RIGHT 1
+#define PAD_ZERO 2
+
+static int prints(char **out, const char *string, int width, int pad)
+{
+	register int pc = 0, padchar = ' ';
+
+	if (width > 0) {
+		register int len = 0;
+		register const char *ptr;
+		for (ptr = string; *ptr; ++ptr) ++len;
+		if (len >= width) width = 0;
+		else width -= len;
+		if (pad & PAD_ZERO) padchar = '0';
+	}
+	if (!(pad & PAD_RIGHT)) {
+		for ( ; width > 0; --width) {
+			printchar (out, padchar);
+			++pc;
+		}
+	}
+	for ( ; *string ; ++string) {
+		printchar (out, *string);
+		++pc;
+	}
+	for ( ; width > 0; --width) {
+		printchar (out, padchar);
+		++pc;
+	}
+
+	return pc;
+}
+
+/* the following should be enough for 32 bit int */
+#define PRINT_BUF_LEN 12
+
+static int printi(char **out, int i, int b, int sg, int width, int pad, int letbase)
+{
+	char print_buf[PRINT_BUF_LEN];
+	register char *s;
+	register int t, neg = 0, pc = 0;
+	register unsigned int u = i;
+
+	if (i == 0) {
+		print_buf[0] = '0';
+		print_buf[1] = '\0';
+		return prints (out, print_buf, width, pad);
+	}
+
+	if (sg && b == 10 && i < 0) {
+		neg = 1;
+		u = -i;
+	}
+
+	s = print_buf + PRINT_BUF_LEN-1;
+	*s = '\0';
+
+	while (u) {
+		t = u % b;
+		if( t >= 10 )
+			t += letbase - '0' - 10;
+		*--s = t + '0';
+		u /= b;
+	}
+
+	if (neg) {
+		if( width && (pad & PAD_ZERO) ) {
+			printchar (out, '-');
+			++pc;
+			--width;
+		}
+		else {
+			*--s = '-';
+		}
+	}
+
+	return pc + prints (out, s, width, pad);
+}
+
+int fprintf(__FILE *stream, const char *format, ...)
+{
+return 0;
+}
+static int print(char **out, const char *format, va_list args )
+{
+	register int width, pad;
+	register int pc = 0;
+	char scr[2];
+
+	for (; *format != 0; ++format) {
+		if (*format == '%') {
+			++format;
+			width = pad = 0;
+			if (*format == '\0') break;
+			if (*format == '%') goto out;
+			if (*format == '-') {
+				++format;
+				pad = PAD_RIGHT;
+			}
+			while (*format == '0') {
+				++format;
+				pad |= PAD_ZERO;
+			}
+			for ( ; *format >= '0' && *format <= '9'; ++format) {
+				width *= 10;
+				width += *format - '0';
+			}
+			if( *format == 's' ) {
+				register char *s = (char *)va_arg( args, int );
+				pc += prints (out, s?s:"(null)", width, pad);
+				continue;
+			}
+			if( *format == 'd' ) {
+				pc += printi (out, va_arg( args, int ), 10, 1, width, pad, 'a');
+				continue;
+			}
+			if( *format == 'x' ) {
+				pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'a');
+				continue;
+			}
+			if( *format == 'X' ) {
+				pc += printi (out, va_arg( args, int ), 16, 0, width, pad, 'A');
+				continue;
+			}
+			if( *format == 'u' ) {
+				pc += printi (out, va_arg( args, int ), 10, 0, width, pad, 'a');
+				continue;
+			}
+			if( *format == 'c' ) {
+				/* char are converted to int then pushed on the stack */
+				scr[0] = (char)va_arg( args, int );
+				scr[1] = '\0';
+				pc += prints (out, scr, width, pad);
+				continue;
+			}
+		}
+		else {
+		out:
+			printchar (out, *format);
+			++pc;
+		}
+	}
+	if (out) **out = '\0';
+	va_end( args );
+	return pc;
+}
+
+int printk(const char *format, ...)
+{
+        va_list args;
+        
+        va_start( args, format );
+        return print( 0, format, args );
+}
+
+int sprintf(char *out, const char *format, ...)
+{
+        va_list args;
+        
+        va_start( args, format );
+        return print( &out, format, args );
+}
+
+#ifdef TEST_PRINTF
+int main(void)
+{
+	char *ptr = "Hello world!";
+	char *np = 0;
+	int i = 5;
+	unsigned int bs = sizeof(int)*8;
+	int mi;
+	char buf[80];
+
+	mi = (1 << (bs-1)) + 1;
+	printf("%s\n", ptr);
+	printf("printf test\n");
+	printf("%s is null pointer\n", np);
+	printf("%d = 5\n", i);
+	printf("%d = - max int\n", mi);
+	printf("char %c = 'a'\n", 'a');
+	printf("hex %x = ff\n", 0xff);
+	printf("hex %02x = 00\n", 0);
+	printf("signed %d = unsigned %u = hex %x\n", -3, -3, -3);
+	printf("%d %s(s)%", 0, "message");
+	printf("\n");
+	printf("%d %s(s) with %%\n", 0, "message");
+	sprintf(buf, "justif: \"%-10s\"\n", "left"); printf("%s", buf);
+	sprintf(buf, "justif: \"%10s\"\n", "right"); printf("%s", buf);
+	sprintf(buf, " 3: %04d zero padded\n", 3); printf("%s", buf);
+	sprintf(buf, " 3: %-4d left justif.\n", 3); printf("%s", buf);
+	sprintf(buf, " 3: %4d right justif.\n", 3); printf("%s", buf);
+	sprintf(buf, "-3: %04d zero padded\n", -3); printf("%s", buf);
+	sprintf(buf, "-3: %-4d left justif.\n", -3); printf("%s", buf);
+	sprintf(buf, "-3: %4d right justif.\n", -3); printf("%s", buf);
+
+	return 0;
+}
+
+/*
+ * if you compile this file with
+ *   gcc -Wall $(YOUR_C_OPTIONS) -DTEST_PRINTF -c printf.c
+ * you will get a normal warning:
+ *   printf.c:214: warning: spurious trailing `%' in format
+ * this line is testing an invalid % at the end of the format string.
+ *
+ * this should display (on 32bit int machine) :
+ *
+ * Hello world!
+ * printf test
+ * (null) is null pointer
+ * 5 = 5
+ * -2147483647 = - max int
+ * char a = 'a'
+ * hex ff = ff
+ * hex 00 = 00
+ * signed -3 = unsigned 4294967293 = hex fffffffd
+ * 0 message(s)
+ * 0 message(s) with %
+ * justif: "left      "
+ * justif: "     right"
+ *  3: 0003 zero padded
+ *  3: 3    left justif.
+ *  3:    3 right justif.
+ * -3: -003 zero padded
+ * -3: -3   left justif.
+ * -3:   -3 right justif.
+ */
+
+#endif
diff --git a/Demo/lwIP_AVR32_UC3/readme.html b/Demo/lwIP_AVR32_UC3/readme.html
new file mode 100644
index 000000000..9fbee43b3
--- /dev/null
+++ b/Demo/lwIP_AVR32_UC3/readme.html
@@ -0,0 +1,101 @@
+
+
+   
+      
+   
+   
+
Back to main page

+
AVR®32 AT32UC3 Series Software Library: Basic Web server and TFTP server example.

+

+
+
Copyright © 2007 Atmel Corporation

+
+
Introduction

+    
This example implements a basic Web server and a basic TFTP server.
+    It is running on top of the lwIP TCP/IP stack and the AVR32 UC3 freeRTOS.org port.

+    
This example thus contains a port of the lwIP TCP/IP stack. This port is using both the AVR32 UC3 freeRTOS.org port and the AVR32 UC3A MACB interface for the Ethernet access.
  
+
+
 

+
+
lwIP TCP/IP stack

+    
lwIP is an implementation of the TCP/IP protocol suite. The focus of the lwIP TCP/IP implementation is to reduce resource usage while still having a full scale TCP.

+    
lwIP features:
+    
  • IP (Internet Protocol) including packet forwarding over multiple network interfaces
    • 
+    
  • ICMP (Internet Control Message Protocol) for network maintenance and debugging
    • 
+    
  • UDP (User Datagram Protocol) including experimental UDP-lite extensions
    • 
+    
  • TCP (Transmission Control Protocol) with congestion control, RTT estimation and fast recovery/fast retransmit
    • 
+    
  • Specialized raw API for enhanced performance
    • 
+    
  • Optional Berkeley-alike socket API
    • 
+    
  • DHCP (Dynamic Host Configuration Protocol)
    • 
+    
  • PPP (Point-to-Point Protocol)
    • 
+    
  • ARP (Address Resolution Protocol) for Ethernet
    • 
+
+
     
    
+
+
    The Basic Web server
    
+    
    Implements a simplistic WEB server.
    
+    Demo description: Every time a connection is made and data is received, a dynamic page that shows the current FreeRTOS.org kernel statistics is generated and returned. The connection is then closed.
    
+    Note: The WEB server is reachable at the IP address 192.168.0.2.
+
+
     
    
+
+
    The Basic TFTP server
    
+    
    Implements a simplistic TFTP server.
    
+    
    Demo description: 
+    
  • To put a file onto the TFTP server (Supported file size < 2048 bytes), on a PC command line type tftp 192.168.0.2 PUT "a_file": this will copy a_file from your hard drive to a RAM buffer of the demo.
    • 
+    
  • To get a file from the TFTP server, on a PC command line type tftp 192.168.0.2 GET "a_file": this will copy a_file from the RAM buffer of the application to the PC's hard drive.
    • 
+    Note 1: only one file at a time is supported on this TFTP server. This is because the TFTP server being a simplistic example, it does not use a file system to store files but a predefined RAM area of 2048 Bytes.
+    
    Note 2: The TFTP server is reachable at the IP address 192.168.0.2.
     
+
+
     
    
+
+
    Device Info
    
+    All AVR32 UC3A devices with a MACB module can be used. This example has been tested with the following setup(s):
+    
  • AT32UC3A0512 on the EVK1100 evaluation kit.
    • 
+    
+
     
    
+
+
    Contact Info
    
+For more info about Atmel AVR32 visit Atmel AVR32 
    
+ AVR32 Application Notes
    
+ Support mail: avr32@atmel.com
+
+
     
    
+
+
    License
    
+
+Copyright (c) 2007, Atmel Corporation All rights reserved.
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
      
+
    1. Redistributions of source code must retain the above copyright notice,
+this list of conditions and the following disclaimer.
+
    2. Redistributions in binary form must reproduce the above copyright notice,
+this list of conditions and the following disclaimer in the documentation
+and/or other materials provided with the distribution.
+
    3. The name of ATMEL may not be used to endorse or promote products derived
+from this software without specific prior written permission.
+
    
+
     
    
+THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+
     
    
+
+
+
    
+
+    
    AVR is a registered trademark of
+    Atmel Corporation.
    
+
+   
+