From: Michal Simek Date: Thu, 20 Jul 2017 10:38:27 +0000 (+0200) Subject: arm64: zynqmp: Move dts zcu102 to zcu102-revA X-Git-Tag: v2017.09-rc2~129^2~4 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=be4634511a55c52a68131cf7114c97f5c2b608d6;p=u-boot arm64: zynqmp: Move dts zcu102 to zcu102-revA Not using board revision is causing confusion about which board is supported and tested. Mark dts files exactly with board revision which was tested. When new board revision arives it can be symlink if SW view is the same. Also add -revX suffix to compatible string because user space tools are parsing this string and can change behavior depends of board revision. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e4d118d51c..175c706e7a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -139,7 +139,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ zynq-zc770-xm013.dtb dtb-$(CONFIG_ARCH_ZYNQMP) += \ zynqmp-ep108.dtb \ - zynqmp-zcu102.dtb \ + zynqmp-zcu102-revA.dtb \ zynqmp-zcu102-revB.dtb \ zynqmp-zc1751-xm015-dc1.dtb \ zynqmp-zc1751-xm016-dc2.dtb \ diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts new file mode 100644 index 0000000000..d8ac008f2b --- /dev/null +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -0,0 +1,661 @@ +/* + * dts file for Xilinx ZynqMP ZCU102 + * + * (C) Copyright 2015, Xilinx, Inc. + * + * Michal Simek + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk.dtsi" +#include + +/ { + model = "ZynqMP ZCU102 RevA"; + compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; + + aliases { + ethernet0 = &gem3; + gpio0 = &gpio; + i2c0 = &i2c0; + i2c1 = &i2c1; + mmc0 = &sdhci1; + rtc0 = &rtc; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &dcc; + spi0 = &qspi; + usb0 = &usb0; + }; + + chosen { + bootargs = "earlycon"; + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + sw19 { + label = "sw19"; + gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; + linux,code = <108>; /* down */ + gpio-key,wakeup; + autorepeat; + }; + }; + + leds { + compatible = "gpio-leds"; + heartbeat_led { + label = "heartbeat"; + gpios = <&gpio 23 0>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + status = "okay"; +}; + +&dcc { + status = "okay"; +}; + +/* fpd_dma clk 667MHz, lpd_dma 500MHz */ +&fpd_dma_chan1 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ + xlnx,overfetch; /* for testing purpose */ + xlnx,ratectrl = <0>; /* for testing purpose */ + xlnx,src-issue = <31>; +}; + +&fpd_dma_chan2 { + status = "okay"; + xlnx,ratectrl = <100>; /* for testing purpose */ + xlnx,src-issue = <4>; /* for testing purpose */ +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; + xlnx,include-sg; /* for testing purpose */ +}; + +&gem3 { + status = "okay"; + local-mac-address = [00 0a 35 00 02 90]; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + phy0: phy@21 { + reg = <21>; + ti,rx-internal-delay = <0x8>; + ti,tx-internal-delay = <0xa>; + ti,fifo-depth = <0x1>; + }; +}; + +&gpio { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <400000>; + + tca6416_u97: gpio@20 { + /* + * Enable all GTs to out from U-Boot + * i2c mw 20 6 0 - setup IO to output + * i2c mw 20 2 ef - setup output values on pins 0-7 + * i2c mw 20 3 ff - setup output values on pins 10-17 + */ + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - PS_GTR_LAN_SEL0 + * 1 - PS_GTR_LAN_SEL1 + * 2 - PS_GTR_LAN_SEL2 + * 3 - PS_GTR_LAN_SEL3 + * 4 - PCI_CLK_DIR_SEL + * 5 - IIC_MUX_RESET_B + * 6 - GEM3_EXP_RESET_B + * 7, 10 - 17 - not connected + */ + + gtr_sel0 { + gpio-hog; + gpios = <0 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel0"; + }; + gtr_sel1 { + gpio-hog; + gpios = <1 0>; + output-high; /* PCIE = 0, DP = 1 */ + line-name = "sel1"; + }; + gtr_sel2 { + gpio-hog; + gpios = <2 0>; + output-high; /* PCIE = 0, USB0 = 1 */ + line-name = "sel2"; + }; + gtr_sel3 { + gpio-hog; + gpios = <3 0>; + output-high; /* PCIE = 0, SATA = 1 */ + line-name = "sel3"; + }; + }; + + tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + /* + * IRQ not connected + * Lines: + * 0 - VCCPSPLL_EN + * 1 - MGTRAVCC_EN + * 2 - MGTRAVTT_EN + * 3 - VCCPSDDRPLL_EN + * 4 - MIO26_PMU_INPUT_LS + * 5 - PL_PMBUS_ALERT + * 6 - PS_PMBUS_ALERT + * 7 - MAXIM_PMBUS_ALERT + * 10 - PL_DDR4_VTERM_EN + * 11 - PL_DDR4_VPP_2V5_EN + * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON + * 13 - PS_DIMM_SUSPEND_EN + * 14 - PS_DDR4_VTERM_EN + * 15 - PS_DDR4_VPP_2V5_EN + * 16 - 17 - not connected + */ + }; + + i2cswitch@75 { /* u60 */ + compatible = "nxp,pca9544"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + i2c@0 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* PS_PMBUS */ + ina226@40 { /* u76 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + ina226@41 { /* u77 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u78 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u87 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u85 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u86 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u93 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u88 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + ina226@4a { /* u15 */ + compatible = "ti,ina226"; + reg = <0x4a>; + shunt-resistor = <5000>; + }; + ina226@4b { /* u92 */ + compatible = "ti,ina226"; + reg = <0x4b>; + shunt-resistor = <5000>; + }; + }; + i2c@1 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* PL_PMBUS */ + ina226@40 { /* u79 */ + compatible = "ti,ina226"; + reg = <0x40>; + shunt-resistor = <2000>; + }; + ina226@41 { /* u81 */ + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + ina226@42 { /* u80 */ + compatible = "ti,ina226"; + reg = <0x42>; + shunt-resistor = <5000>; + }; + ina226@43 { /* u84 */ + compatible = "ti,ina226"; + reg = <0x43>; + shunt-resistor = <5000>; + }; + ina226@44 { /* u16 */ + compatible = "ti,ina226"; + reg = <0x44>; + shunt-resistor = <5000>; + }; + ina226@45 { /* u65 */ + compatible = "ti,ina226"; + reg = <0x45>; + shunt-resistor = <5000>; + }; + ina226@46 { /* u74 */ + compatible = "ti,ina226"; + reg = <0x46>; + shunt-resistor = <5000>; + }; + ina226@47 { /* u75 */ + compatible = "ti,ina226"; + reg = <0x47>; + shunt-resistor = <5000>; + }; + }; + i2c@2 { /* i2c mw 75 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* MAXIM_PMBUS - 00 */ + max15301@a { /* u46 */ + compatible = "max15301"; + reg = <0xa>; + }; + max15303@b { /* u4 */ + compatible = "max15303"; + reg = <0xb>; + }; + max15303@10 { /* u13 */ + compatible = "max15303"; + reg = <0x10>; + }; + max15301@13 { /* u47 */ + compatible = "max15301"; + reg = <0x13>; + }; + max15303@14 { /* u7 */ + compatible = "max15303"; + reg = <0x14>; + }; + max15303@15 { /* u6 */ + compatible = "max15303"; + reg = <0x15>; + }; + max15303@16 { /* u10 */ + compatible = "max15303"; + reg = <0x16>; + }; + max15303@17 { /* u9 */ + compatible = "max15303"; + reg = <0x17>; + }; + max15301@18 { /* u63 */ + compatible = "max15301"; + reg = <0x18>; + }; + max15303@1a { /* u49 */ + compatible = "max15303"; + reg = <0x1a>; + }; + max15303@1d { /* u18 */ + compatible = "max15303"; + reg = <0x1d>; + }; + max15303@20 { /* u8 */ + compatible = "max15303"; + status = "disabled"; /* unreachable */ + reg = <0x20>; + }; + +/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. +drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o +*/ + max20751@72 { /* u95 FIXME - not detected */ + compatible = "max20751"; + reg = <0x72>; + }; + max20751@73 { /* u96 FIXME - not detected */ + compatible = "max20751"; + reg = <0x73>; + }; + }; + /* Bus 3 is not connected */ + }; + + /* FIXME PMOD - j160 */ + /* FIXME MSP430F - u41 - not detected */ +}; + +&i2c1 { + status = "okay"; + clock-frequency = <400000>; + /* FIXME PL i2c via PCA9306 - u45 */ + /* FIXME MSP430 - u41 - not detected */ + i2cswitch@74 { /* u34 */ + compatible = "nxp,pca9548"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x74>; + i2c@0 { /* i2c mw 74 0 1 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* + * IIC_EEPROM 1kB memory which uses 256B blocks + * where every block has different address. + * 0 - 256B address 0x54 + * 256B - 512B address 0x55 + * 512B - 768B address 0x56 + * 768B - 1024B address 0x57 + */ + eeprom@54 { /* u23 */ + compatible = "at,24c08"; + reg = <0x54>; + }; + }; + i2c@1 { /* i2c mw 74 0 2 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + si5341: clock-generator1@36 { /* SI5341 - u69 */ + compatible = "si5341"; + reg = <0x36>; + }; + + }; + i2c@2 { /* i2c mw 74 0 4 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + si570_1: clock-generator2@5d { /* USER SI570 - u42 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; + factory-fout = <300000000>; + clock-frequency = <300000000>; + }; + }; + i2c@3 { /* i2c mw 74 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ + #clock-cells = <0>; + compatible = "silabs,si570"; + reg = <0x5d>; + temperature-stability = <50>; /* copy from zc702 */ + factory-fout = <156250000>; + clock-frequency = <148500000>; + }; + }; + i2c@4 { /* i2c mw 74 0 10 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + si5328: clock-generator4@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + }; + }; + /* 5 - 7 unconnected */ + }; + + i2cswitch@75 { + compatible = "nxp,pca9548"; /* u135 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <0x75>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + /* HPC0_IIC */ + }; + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + /* HPC1_IIC */ + }; + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + /* SYSMON */ + }; + i2c@3 { /* i2c mw 75 0 8 */ + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + /* DDR4 SODIMM */ + dev@19 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x19>; + }; + dev@30 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x30>; + }; + dev@35 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x35>; + }; + dev@36 { /* u-boot detection */ + compatible = "xxx"; + reg = <0x36>; + }; + dev@51 { /* u-boot detection - maybe SPD */ + compatible = "xxx"; + reg = <0x51>; + }; + }; + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <4>; + /* SEP 3 */ + }; + i2c@5 { + #address-cells = <1>; + #size-cells = <0>; + reg = <5>; + /* SEP 2 */ + }; + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <6>; + /* SEP 1 */ + }; + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <7>; + /* SEP 0 */ + }; + }; +}; + +&pcie { +/* status = "okay"; */ +}; + +&qspi { + status = "okay"; + is-dual = <1>; + flash@0 { + compatible = "m25p80"; /* 32MB */ + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ + spi-max-frequency = <108000000>; /* Based on DC1 spec */ + partition@qspi-fsbl-uboot { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@qspi-linux { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@qspi-device-tree { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@qspi-rootfs { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5E0000>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sata { + status = "okay"; + /* SATA OOB timing settings */ + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; +}; + +/* SD1 with level shifter */ +&sdhci1 { + status = "okay"; + no-1-8-v; /* for 1.0 silicon */ + xlnx,mio_bank = <1>; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +/* ULPI SMSC USB3320 */ +&usb0 { + status = "okay"; +}; + +&dwc3_0 { + status = "okay"; + dr_mode = "host"; +}; + +&xilinx_drm { + status = "okay"; + clocks = <&si570_1>; +}; + +&xlnx_dp { + status = "okay"; +}; + +&xlnx_dp_sub { + status = "okay"; + xlnx,vid-clk-pl; +}; + +&xlnx_dp_snd_pcm0 { + status = "okay"; +}; + +&xlnx_dp_snd_pcm1 { + status = "okay"; +}; + +&xlnx_dp_snd_card { + status = "okay"; +}; + +&xlnx_dp_snd_codec0 { + status = "okay"; +}; + +&xlnx_dpdma { + status = "okay"; +}; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 765108e437..82337332f9 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -8,7 +8,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "zynqmp-zcu102.dts" +#include "zynqmp-zcu102-revA.dts" / { model = "ZynqMP ZCU102 RevB"; diff --git a/arch/arm/dts/zynqmp-zcu102.dts b/arch/arm/dts/zynqmp-zcu102.dts deleted file mode 100644 index 0e9150e6b1..0000000000 --- a/arch/arm/dts/zynqmp-zcu102.dts +++ /dev/null @@ -1,661 +0,0 @@ -/* - * dts file for Xilinx ZynqMP ZCU102 - * - * (C) Copyright 2015, Xilinx, Inc. - * - * Michal Simek - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/dts-v1/; - -#include "zynqmp.dtsi" -#include "zynqmp-clk.dtsi" -#include - -/ { - model = "ZynqMP ZCU102 RevA"; - compatible = "xlnx,zynqmp-zcu102", "xlnx,zynqmp"; - - aliases { - ethernet0 = &gem3; - gpio0 = &gpio; - i2c0 = &i2c0; - i2c1 = &i2c1; - mmc0 = &sdhci1; - rtc0 = &rtc; - serial0 = &uart0; - serial1 = &uart1; - serial2 = &dcc; - spi0 = &qspi; - usb0 = &usb0; - }; - - chosen { - bootargs = "earlycon"; - stdout-path = "serial0:115200n8"; - }; - - memory@0 { - device_type = "memory"; - reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; - }; - - gpio-keys { - compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - autorepeat; - sw19 { - label = "sw19"; - gpios = <&gpio 22 GPIO_ACTIVE_HIGH>; - linux,code = <108>; /* down */ - gpio-key,wakeup; - autorepeat; - }; - }; - - leds { - compatible = "gpio-leds"; - heartbeat_led { - label = "heartbeat"; - gpios = <&gpio 23 0>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&can1 { - status = "okay"; -}; - -&dcc { - status = "okay"; -}; - -/* fpd_dma clk 667MHz, lpd_dma 500MHz */ -&fpd_dma_chan1 { - status = "okay"; - xlnx,include-sg; /* for testing purpose */ - xlnx,overfetch; /* for testing purpose */ - xlnx,ratectrl = <0>; /* for testing purpose */ - xlnx,src-issue = <31>; -}; - -&fpd_dma_chan2 { - status = "okay"; - xlnx,ratectrl = <100>; /* for testing purpose */ - xlnx,src-issue = <4>; /* for testing purpose */ -}; - -&fpd_dma_chan3 { - status = "okay"; -}; - -&fpd_dma_chan4 { - status = "okay"; - xlnx,include-sg; /* for testing purpose */ -}; - -&fpd_dma_chan5 { - status = "okay"; -}; - -&fpd_dma_chan6 { - status = "okay"; - xlnx,include-sg; /* for testing purpose */ -}; - -&fpd_dma_chan7 { - status = "okay"; -}; - -&fpd_dma_chan8 { - status = "okay"; - xlnx,include-sg; /* for testing purpose */ -}; - -&gem3 { - status = "okay"; - local-mac-address = [00 0a 35 00 02 90]; - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - phy0: phy@21 { - reg = <21>; - ti,rx-internal-delay = <0x8>; - ti,tx-internal-delay = <0xa>; - ti,fifo-depth = <0x1>; - }; -}; - -&gpio { - status = "okay"; -}; - -&gpu { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - clock-frequency = <400000>; - - tca6416_u97: gpio@20 { - /* - * Enable all GTs to out from U-Boot - * i2c mw 20 6 0 - setup IO to output - * i2c mw 20 2 ef - setup output values on pins 0-7 - * i2c mw 20 3 ff - setup output values on pins 10-17 - */ - compatible = "ti,tca6416"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - PS_GTR_LAN_SEL0 - * 1 - PS_GTR_LAN_SEL1 - * 2 - PS_GTR_LAN_SEL2 - * 3 - PS_GTR_LAN_SEL3 - * 4 - PCI_CLK_DIR_SEL - * 5 - IIC_MUX_RESET_B - * 6 - GEM3_EXP_RESET_B - * 7, 10 - 17 - not connected - */ - - gtr_sel0 { - gpio-hog; - gpios = <0 0>; - output-high; /* PCIE = 0, DP = 1 */ - line-name = "sel0"; - }; - gtr_sel1 { - gpio-hog; - gpios = <1 0>; - output-high; /* PCIE = 0, DP = 1 */ - line-name = "sel1"; - }; - gtr_sel2 { - gpio-hog; - gpios = <2 0>; - output-high; /* PCIE = 0, USB0 = 1 */ - line-name = "sel2"; - }; - gtr_sel3 { - gpio-hog; - gpios = <3 0>; - output-high; /* PCIE = 0, SATA = 1 */ - line-name = "sel3"; - }; - }; - - tca6416_u61: gpio@21 { /* FIXME enable it by i2c mw 21 6 0 */ - compatible = "ti,tca6416"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - /* - * IRQ not connected - * Lines: - * 0 - VCCPSPLL_EN - * 1 - MGTRAVCC_EN - * 2 - MGTRAVTT_EN - * 3 - VCCPSDDRPLL_EN - * 4 - MIO26_PMU_INPUT_LS - * 5 - PL_PMBUS_ALERT - * 6 - PS_PMBUS_ALERT - * 7 - MAXIM_PMBUS_ALERT - * 10 - PL_DDR4_VTERM_EN - * 11 - PL_DDR4_VPP_2V5_EN - * 12 - PS_DIMM_VDDQ_TO_PSVCCO_ON - * 13 - PS_DIMM_SUSPEND_EN - * 14 - PS_DDR4_VTERM_EN - * 15 - PS_DDR4_VPP_2V5_EN - * 16 - 17 - not connected - */ - }; - - i2cswitch@75 { /* u60 */ - compatible = "nxp,pca9544"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - i2c@0 { /* i2c mw 75 0 1 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* PS_PMBUS */ - ina226@40 { /* u76 */ - compatible = "ti,ina226"; - reg = <0x40>; - shunt-resistor = <5000>; - }; - ina226@41 { /* u77 */ - compatible = "ti,ina226"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - ina226@42 { /* u78 */ - compatible = "ti,ina226"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - ina226@43 { /* u87 */ - compatible = "ti,ina226"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - ina226@44 { /* u85 */ - compatible = "ti,ina226"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - ina226@45 { /* u86 */ - compatible = "ti,ina226"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - ina226@46 { /* u93 */ - compatible = "ti,ina226"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - ina226@47 { /* u88 */ - compatible = "ti,ina226"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - ina226@4a { /* u15 */ - compatible = "ti,ina226"; - reg = <0x4a>; - shunt-resistor = <5000>; - }; - ina226@4b { /* u92 */ - compatible = "ti,ina226"; - reg = <0x4b>; - shunt-resistor = <5000>; - }; - }; - i2c@1 { /* i2c mw 75 0 1 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* PL_PMBUS */ - ina226@40 { /* u79 */ - compatible = "ti,ina226"; - reg = <0x40>; - shunt-resistor = <2000>; - }; - ina226@41 { /* u81 */ - compatible = "ti,ina226"; - reg = <0x41>; - shunt-resistor = <5000>; - }; - ina226@42 { /* u80 */ - compatible = "ti,ina226"; - reg = <0x42>; - shunt-resistor = <5000>; - }; - ina226@43 { /* u84 */ - compatible = "ti,ina226"; - reg = <0x43>; - shunt-resistor = <5000>; - }; - ina226@44 { /* u16 */ - compatible = "ti,ina226"; - reg = <0x44>; - shunt-resistor = <5000>; - }; - ina226@45 { /* u65 */ - compatible = "ti,ina226"; - reg = <0x45>; - shunt-resistor = <5000>; - }; - ina226@46 { /* u74 */ - compatible = "ti,ina226"; - reg = <0x46>; - shunt-resistor = <5000>; - }; - ina226@47 { /* u75 */ - compatible = "ti,ina226"; - reg = <0x47>; - shunt-resistor = <5000>; - }; - }; - i2c@2 { /* i2c mw 75 0 1 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* MAXIM_PMBUS - 00 */ - max15301@a { /* u46 */ - compatible = "max15301"; - reg = <0xa>; - }; - max15303@b { /* u4 */ - compatible = "max15303"; - reg = <0xb>; - }; - max15303@10 { /* u13 */ - compatible = "max15303"; - reg = <0x10>; - }; - max15301@13 { /* u47 */ - compatible = "max15301"; - reg = <0x13>; - }; - max15303@14 { /* u7 */ - compatible = "max15303"; - reg = <0x14>; - }; - max15303@15 { /* u6 */ - compatible = "max15303"; - reg = <0x15>; - }; - max15303@16 { /* u10 */ - compatible = "max15303"; - reg = <0x16>; - }; - max15303@17 { /* u9 */ - compatible = "max15303"; - reg = <0x17>; - }; - max15301@18 { /* u63 */ - compatible = "max15301"; - reg = <0x18>; - }; - max15303@1a { /* u49 */ - compatible = "max15303"; - reg = <0x1a>; - }; - max15303@1d { /* u18 */ - compatible = "max15303"; - reg = <0x1d>; - }; - max15303@20 { /* u8 */ - compatible = "max15303"; - status = "disabled"; /* unreachable */ - reg = <0x20>; - }; - -/* drivers/hwmon/pmbus/Kconfig:86: be called max20751. -drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751) += max20751.o -*/ - max20751@72 { /* u95 FIXME - not detected */ - compatible = "max20751"; - reg = <0x72>; - }; - max20751@73 { /* u96 FIXME - not detected */ - compatible = "max20751"; - reg = <0x73>; - }; - }; - /* Bus 3 is not connected */ - }; - - /* FIXME PMOD - j160 */ - /* FIXME MSP430F - u41 - not detected */ -}; - -&i2c1 { - status = "okay"; - clock-frequency = <400000>; - /* FIXME PL i2c via PCA9306 - u45 */ - /* FIXME MSP430 - u41 - not detected */ - i2cswitch@74 { /* u34 */ - compatible = "nxp,pca9548"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x74>; - i2c@0 { /* i2c mw 74 0 1 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* - * IIC_EEPROM 1kB memory which uses 256B blocks - * where every block has different address. - * 0 - 256B address 0x54 - * 256B - 512B address 0x55 - * 512B - 768B address 0x56 - * 768B - 1024B address 0x57 - */ - eeprom@54 { /* u23 */ - compatible = "at,24c08"; - reg = <0x54>; - }; - }; - i2c@1 { /* i2c mw 74 0 2 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - si5341: clock-generator1@36 { /* SI5341 - u69 */ - compatible = "si5341"; - reg = <0x36>; - }; - - }; - i2c@2 { /* i2c mw 74 0 4 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - si570_1: clock-generator2@5d { /* USER SI570 - u42 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; - factory-fout = <300000000>; - clock-frequency = <300000000>; - }; - }; - i2c@3 { /* i2c mw 74 0 8 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - si570_2: clock-generator3@5d { /* USER MGT SI570 - u56 */ - #clock-cells = <0>; - compatible = "silabs,si570"; - reg = <0x5d>; - temperature-stability = <50>; /* copy from zc702 */ - factory-fout = <156250000>; - clock-frequency = <148500000>; - }; - }; - i2c@4 { /* i2c mw 74 0 10 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - si5328: clock-generator4@69 {/* SI5328 - u20 */ - compatible = "silabs,si5328"; - reg = <0x69>; - }; - }; - /* 5 - 7 unconnected */ - }; - - i2cswitch@75 { - compatible = "nxp,pca9548"; /* u135 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <0x75>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - /* HPC0_IIC */ - }; - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - /* HPC1_IIC */ - }; - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - /* SYSMON */ - }; - i2c@3 { /* i2c mw 75 0 8 */ - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - /* DDR4 SODIMM */ - dev@19 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x19>; - }; - dev@30 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x30>; - }; - dev@35 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x35>; - }; - dev@36 { /* u-boot detection */ - compatible = "xxx"; - reg = <0x36>; - }; - dev@51 { /* u-boot detection - maybe SPD */ - compatible = "xxx"; - reg = <0x51>; - }; - }; - i2c@4 { - #address-cells = <1>; - #size-cells = <0>; - reg = <4>; - /* SEP 3 */ - }; - i2c@5 { - #address-cells = <1>; - #size-cells = <0>; - reg = <5>; - /* SEP 2 */ - }; - i2c@6 { - #address-cells = <1>; - #size-cells = <0>; - reg = <6>; - /* SEP 1 */ - }; - i2c@7 { - #address-cells = <1>; - #size-cells = <0>; - reg = <7>; - /* SEP 0 */ - }; - }; -}; - -&pcie { -/* status = "okay"; */ -}; - -&qspi { - status = "okay"; - is-dual = <1>; - flash@0 { - compatible = "m25p80"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; - reg = <0x0>; - spi-tx-bus-width = <1>; - spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ - spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@qspi-fsbl-uboot { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@qspi-linux { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@qspi-device-tree { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@qspi-rootfs { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5E0000>; - }; - }; -}; - -&rtc { - status = "okay"; -}; - -&sata { - status = "okay"; - /* SATA OOB timing settings */ - ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>; - ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>; - ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>; - ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>; - ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>; -}; - -/* SD1 with level shifter */ -&sdhci1 { - status = "okay"; - no-1-8-v; /* for 1.0 silicon */ - xlnx,mio_bank = <1>; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -/* ULPI SMSC USB3320 */ -&usb0 { - status = "okay"; -}; - -&dwc3_0 { - status = "okay"; - dr_mode = "host"; -}; - -&xilinx_drm { - status = "okay"; - clocks = <&si570_1>; -}; - -&xlnx_dp { - status = "okay"; -}; - -&xlnx_dp_sub { - status = "okay"; - xlnx,vid-clk-pl; -}; - -&xlnx_dp_snd_pcm0 { - status = "okay"; -}; - -&xlnx_dp_snd_pcm1 { - status = "okay"; -}; - -&xlnx_dp_snd_card { - status = "okay"; -}; - -&xlnx_dp_snd_codec0 { - status = "okay"; -}; - -&xlnx_dpdma { - status = "okay"; -}; diff --git a/configs/xilinx_zynqmp_zcu102_defconfig b/configs/xilinx_zynqmp_zcu102_defconfig deleted file mode 100644 index 4d0f73f782..0000000000 --- a/configs/xilinx_zynqmp_zcu102_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_ARM=y -CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" -CONFIG_ARCH_ZYNQMP=y -CONFIG_SYS_TEXT_BASE=0x8000000 -CONFIG_SYS_MALLOC_F_LEN=0x8000 -CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102" -CONFIG_ZYNQMP_USB=y -CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102" -CONFIG_DEBUG_UART=y -CONFIG_AHCI=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_ENV_IS_IN_FAT=y -# CONFIG_DISPLAY_CPUINFO is not set -# CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL=y -CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_OS_BOOT=y -CONFIG_SYS_PROMPT="ZynqMP> " -# CONFIG_CMD_IMLS is not set -CONFIG_CMD_EEPROM=y -CONFIG_CMD_MEMTEST=y -CONFIG_CMD_UNZIP=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPT=y -CONFIG_CMD_MMC=y -CONFIG_CMD_I2C=y -CONFIG_CMD_USB=y -CONFIG_CMD_DFU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TIME=y -CONFIG_CMD_TIMER=y -CONFIG_CMD_EXT4_WRITE=y -# CONFIG_SPL_ISO_PARTITION is not set -CONFIG_SPL_OF_CONTROL=y -CONFIG_OF_EMBED=y -CONFIG_NET_RANDOM_ETHADDR=y -CONFIG_SPL_DM=y -CONFIG_SPL_DM_SEQ_ALIAS=y -CONFIG_SCSI=y -CONFIG_DM_SCSI=y -CONFIG_SATA_CEVA=y -CONFIG_DFU_RAM=y -CONFIG_FPGA_XILINX=y -CONFIG_FPGA_ZYNQMPPL=y -CONFIG_DM_GPIO=y -CONFIG_DM_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_ZYNQ=y -CONFIG_SPI_FLASH=y -CONFIG_SPI_FLASH_BAR=y -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_DM_ETH=y -CONFIG_ZYNQ_GEM=y -CONFIG_DEBUG_UART_ZYNQ=y -CONFIG_DEBUG_UART_BASE=0xff000000 -CONFIG_DEBUG_UART_CLOCK=100000000 -CONFIG_DEBUG_UART_ANNOUNCE=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_XHCI_ZYNQMP=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_ULPI_VIEWPORT=y -CONFIG_USB_ULPI=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_G_DNL_MANUFACTURER="Xilinx" -CONFIG_G_DNL_VENDOR_NUM=0x03FD -CONFIG_G_DNL_PRODUCT_NUM=0x0300 -CONFIG_EFI_LOADER_BOUNCE_BUFFER=y diff --git a/configs/xilinx_zynqmp_zcu102_revA_defconfig b/configs/xilinx_zynqmp_zcu102_revA_defconfig new file mode 100644 index 0000000000..fc14459d3c --- /dev/null +++ b/configs/xilinx_zynqmp_zcu102_revA_defconfig @@ -0,0 +1,78 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zcu102" +CONFIG_ARCH_ZYNQMP=y +CONFIG_SYS_TEXT_BASE=0x8000000 +CONFIG_SYS_MALLOC_F_LEN=0x8000 +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZCU102" +CONFIG_ZYNQMP_USB=y +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zcu102-revA" +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_ENV_IS_IN_FAT=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_OS_BOOT=y +CONFIG_SYS_PROMPT="ZynqMP> " +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_UNZIP=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_SPL_ISO_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_EMBED=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_SATA_CEVA=y +CONFIG_DFU_RAM=y +CONFIG_FPGA_XILINX=y +CONFIG_FPGA_ZYNQMPPL=y +CONFIG_DM_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ZYNQ=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y +CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xff000000 +CONFIG_DEBUG_UART_CLOCK=100000000 +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_ZYNQMP=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_G_DNL_MANUFACTURER="Xilinx" +CONFIG_G_DNL_VENDOR_NUM=0x03FD +CONFIG_G_DNL_PRODUCT_NUM=0x0300 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y