From: Axel Beierlein <belatronix@web.de>
Date: Fri, 15 Aug 2008 22:30:48 +0000 (+0200)
Subject: Adding bootlimit/bootcount feature for MPC5XXX on TQM5200 Boards
X-Git-Tag: v2008.10-rc1~142
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=bef92e215d945cc574399c1a1b00a3a76d35aa03;p=u-boot

Adding bootlimit/bootcount feature for MPC5XXX on TQM5200 Boards

Tested with TQM5200S on STK52XX.200 Board

Signed-off-by: Axel Beierlein <belatronix@web.de>
---

diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c
index ace16535ff..d87f42ca29 100644
--- a/cpu/mpc5xxx/cpu.c
+++ b/cpu/mpc5xxx/cpu.c
@@ -135,3 +135,23 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #endif
 }
 #endif
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+
+void bootcount_store (ulong a)
+{
+     volatile ulong *save_addr = (volatile ulong *)(MPC5XXX_CDM_BRDCRMB);
+
+     *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a;
+}
+
+ulong bootcount_load (void)
+{
+     volatile ulong *save_addr = (volatile ulong *)(MPC5XXX_CDM_BRDCRMB);
+
+     if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000))
+             return 0;
+     else
+             return (*save_addr & 0x0000ffff);
+}
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index 992439f3b3..0ba7455896 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -55,6 +55,7 @@
 #define CONFIG_PSC_CONSOLE	1	/* console is on PSC1			*/
 #define CONFIG_BAUDRATE		115200	/* ... at 115200 bps			*/
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_BOOTCOUNT_LIMIT	1
 
 #ifdef CONFIG_FO300
 #define CFG_DEVICE_NULLDEV		1	/* enable null device */
diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h
index 5d11ef0f48..0f5bee574e 100644
--- a/include/mpc5xxx.h
+++ b/include/mpc5xxx.h
@@ -137,6 +137,7 @@
 /* Clock Distribution Module */
 #define MPC5XXX_CDM_JTAGID	(MPC5XXX_CDM + 0x0000)
 #define MPC5XXX_CDM_PORCFG	(MPC5XXX_CDM + 0x0004)
+#define MPC5XXX_CDM_BRDCRMB  	(MPC5XXX_CDM + 0x0008)
 #define MPC5XXX_CDM_CFG		(MPC5XXX_CDM + 0x000c)
 #define MPC5XXX_CDM_48_FDC	(MPC5XXX_CDM + 0x0010)
 #define MPC5XXX_CDM_SRESET	(MPC5XXX_CDM + 0x0020)