From: Becky Bruce Date: Wed, 5 Nov 2008 20:55:34 +0000 (-0600) Subject: mpc86xx: Use SRR0/1/rfi to enable address translation, not blr X-Git-Tag: v2009.01-rc1~72^2~7 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c1e1cf69547b138173f87a7f81c42a5d8dbfde3d;p=u-boot mpc86xx: Use SRR0/1/rfi to enable address translation, not blr Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method. Signed-off-by: Becky Bruce --- diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 0d30e91b61..7e36801741 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -244,9 +244,15 @@ in_flash: */ /* enable address translation */ - bl enable_addr_trans - sync + mfmsr r5 + ori r5, r5, (MSR_IR | MSR_DR) + lis r3,addr_trans_enabled@h + ori r3, r3, addr_trans_enabled@l + mtspr SPRN_SRR0,r3 + mtspr SPRN_SRR1,r5 + rfi +addr_trans_enabled: /* enable and invalidate the data cache */ /* bl l1dcache_enable */ bl dcache_enable @@ -423,15 +429,6 @@ tlblp: blt tlblp blr - .globl enable_addr_trans -enable_addr_trans: - /* enable address translation */ - mfmsr r5 - ori r5, r5, (MSR_IR | MSR_DR) - mtmsr r5 - isync - blr - .globl disable_addr_trans disable_addr_trans: /* disable address translation */