From: Paul Fertser <fercerpav@gmail.com>
Date: Fri, 2 Dec 2016 17:03:07 +0000 (+0300)
Subject: target: arm: disassembler: decode v6T2 ARM DSB instruction
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c26bbf7a1b2a11e9cc369536332bff2faa223da8;p=openocd

target: arm: disassembler: decode v6T2 ARM DSB instruction

Change-Id: Id91b1a87d34982c72f2a8ab46564c961d1fef9dc
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/3894
Tested-by: jenkins
---

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index f0266d02..15366793 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -129,6 +129,47 @@ static int evaluate_pld(uint32_t opcode,
 
 		return ERROR_OK;
 	}
+	/* DSB */
+	if ((opcode & 0x07f000f0) == 0x05700040) {
+		instruction->type = ARM_DSB;
+
+		char *opt;
+		switch (opcode & 0x0000000f) {
+		case 0xf:
+			opt = "SY";
+			break;
+		case 0xe:
+			opt = "ST";
+			break;
+		case 0xb:
+			opt = "ISH";
+			break;
+		case 0xa:
+			opt = "ISHST";
+			break;
+		case 0x7:
+			opt = "NSH";
+			break;
+		case 0x6:
+			opt = "NSHST";
+			break;
+		case 0x3:
+			opt = "OSH";
+			break;
+		case 0x2:
+			opt = "OSHST";
+			break;
+		default:
+			opt = "UNK";
+		}
+
+		snprintf(instruction->text,
+				128,
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tDSB %s",
+				address, opcode, opt);
+
+		return ERROR_OK;
+	}
 	return evaluate_unknown(opcode, address, instruction);
 }
 
diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 6f8f65d4..b73f24a8 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -106,6 +106,7 @@ enum arm_instruction_type {
 	ARM_MCRR,
 	ARM_MRRC,
 	ARM_PLD,
+	ARM_DSB,
 	ARM_QADD,
 	ARM_QDADD,
 	ARM_QSUB,