+Device +	+7z020 +
+SpeedGrade +	+-1 +
+Part +	+7z020clg484-1 +
+Description +	+Zynq PS Configuration Report with register details +
+Vendor +	+Xilinx +

MIO Table View

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+MIO Pin +	+Peripheral +	+Signal +	+IO Type +	+Speed +	+Pullup +	+Direction +
+MIO 0 +	+SD 0 +	+cd +	+LVCMOS 1.8V +	+slow +	+enabled +	+in +
+MIO 1 +	+Quad SPI Flash +	+qspi0_ss_b +	+LVCMOS 1.8V +	+slow +	+enabled +	+out +
+MIO 2 +	+Quad SPI Flash +	+qspi0_io[0] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 3 +	+Quad SPI Flash +	+qspi0_io[1] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 4 +	+Quad SPI Flash +	+qspi0_io[2] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 5 +	+Quad SPI Flash +	+qspi0_io[3] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 6 +	+Quad SPI Flash +	+qspi0_sclk +	+LVCMOS 1.8V +	+slow +	+disabled +	+out +
+MIO 7 +	+USB Reset +	+reset +	+LVCMOS 1.8V +	+slow +	+disabled +	+out +
+MIO 8 +	+Quad SPI Flash +	+qspi_fbclk +	+LVCMOS 1.8V +	+slow +	+disabled +	+out +
+MIO 9 +	+GPIO +	+gpio[9] +	+LVCMOS 1.8V +	+slow +	+enabled +	+inout +
+MIO 10 +	+GPIO +	+gpio[10] +	+LVCMOS 1.8V +	+slow +	+enabled +	+inout +
+MIO 11 +	+ENET Reset +	+reset +	+LVCMOS 1.8V +	+slow +	+enabled +	+out +
+MIO 12 +	+GPIO +	+gpio[12] +	+LVCMOS 1.8V +	+slow +	+enabled +	+inout +
+MIO 13 +	+I2C Reset +	+reset +	+LVCMOS 1.8V +	+slow +	+enabled +	+out +
+MIO 14 +	+GPIO +	+gpio[14] +	+LVCMOS 1.8V +	+slow +	+enabled +	+inout +
+MIO 15 +	+SD 0 +	+wp +	+LVCMOS 1.8V +	+slow +	+enabled +	+in +
+MIO 16 +	+Enet 0 +	+tx_clk +	+HSTL 1.8V +	+slow +	+disabled +	+out +
+MIO 17 +	+Enet 0 +	+txd[0] +	+HSTL 1.8V +	+slow +	+disabled +	+out +
+MIO 18 +	+Enet 0 +	+txd[1] +	+HSTL 1.8V +	+slow +	+disabled +	+out +
+MIO 19 +	+Enet 0 +	+txd[2] +	+HSTL 1.8V +	+slow +	+disabled +	+out +
+MIO 20 +	+Enet 0 +	+txd[3] +	+HSTL 1.8V +	+slow +	+disabled +	+out +
+MIO 21 +	+Enet 0 +	+tx_ctl +	+HSTL 1.8V +	+slow +	+disabled +	+out +
+MIO 22 +	+Enet 0 +	+rx_clk +	+HSTL 1.8V +	+slow +	+disabled +	+in +
+MIO 23 +	+Enet 0 +	+rxd[0] +	+HSTL 1.8V +	+slow +	+disabled +	+in +
+MIO 24 +	+Enet 0 +	+rxd[1] +	+HSTL 1.8V +	+slow +	+disabled +	+in +
+MIO 25 +	+Enet 0 +	+rxd[2] +	+HSTL 1.8V +	+slow +	+disabled +	+in +
+MIO 26 +	+Enet 0 +	+rxd[3] +	+HSTL 1.8V +	+slow +	+disabled +	+in +
+MIO 27 +	+Enet 0 +	+rx_ctl +	+HSTL 1.8V +	+slow +	+disabled +	+in +
+MIO 28 +	+USB 0 +	+data[4] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 29 +	+USB 0 +	+dir +	+LVCMOS 1.8V +	+slow +	+disabled +	+in +
+MIO 30 +	+USB 0 +	+stp +	+LVCMOS 1.8V +	+slow +	+disabled +	+out +
+MIO 31 +	+USB 0 +	+nxt +	+LVCMOS 1.8V +	+slow +	+disabled +	+in +
+MIO 32 +	+USB 0 +	+data[0] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 33 +	+USB 0 +	+data[1] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 34 +	+USB 0 +	+data[2] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 35 +	+USB 0 +	+data[3] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 36 +	+USB 0 +	+clk +	+LVCMOS 1.8V +	+slow +	+disabled +	+in +
+MIO 37 +	+USB 0 +	+data[5] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 38 +	+USB 0 +	+data[6] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 39 +	+USB 0 +	+data[7] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 40 +	+SD 0 +	+clk +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 41 +	+SD 0 +	+cmd +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 42 +	+SD 0 +	+data[0] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 43 +	+SD 0 +	+data[1] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 44 +	+SD 0 +	+data[2] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 45 +	+SD 0 +	+data[3] +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +
+MIO 46 +	+CAN 0 +	+rx +	+LVCMOS 1.8V +	+slow +	+enabled +	+in +
+MIO 47 +	+CAN 0 +	+tx +	+LVCMOS 1.8V +	+slow +	+enabled +	+out +
+MIO 48 +	+UART 1 +	+tx +	+LVCMOS 1.8V +	+slow +	+disabled +	+out +
+MIO 49 +	+UART 1 +	+rx +	+LVCMOS 1.8V +	+slow +	+disabled +	+in +
+MIO 50 +	+I2C 0 +	+scl +	+LVCMOS 1.8V +	+slow +	+enabled +	+inout +
+MIO 51 +	+I2C 0 +	+sda +	+LVCMOS 1.8V +	+slow +	+enabled +	+inout +
+MIO 52 +	+Enet 0 +	+mdc +	+LVCMOS 1.8V +	+slow +	+disabled +	+out +
+MIO 53 +	+Enet 0 +	+mdio +	+LVCMOS 1.8V +	+slow +	+disabled +	+inout +

DDR Memory information

+Parameter name +	+Value +	+Description +
+Enable DDR +	+1 +	+Enable DDR Controller of Zynq PS +
+Enable DDR +	+1 +	+Enable DDR Controller of Zynq PS +
+Memory Part +	+MT41J256M8 HX-15E +	+ +
+DRAM bus width +	+32 Bit +	+Select the desired data width. Refer to the Thechnical Reference Manual(TRM) for a detailed list of supported DDR data widths +
+ECC +	+Disabled +	+ECC is supported only for data width of 16-bit +
+BURST Length (lppdr only) +	+8 +	+Select the burst Length. It refers to the amount of data read/written after a read/write command is presented to the controller +
+Internal Vref +	+1 +	+ +
+Operating Frequency (MHz) +	+533.333333 +	+Chose the clock period for the desired frequency. The allowed freq range (200 - 667 MHz) is a function of FPGA part and FPGA speed grade +
+HIGH temperature +	+Normal (0-85) +	+Select the operating temparature +
+DRAM IC bus width +	+8 Bits +	+Provide the width of the DRAM chip +
+DRAM Device Capacity +	+2048 MBits +	+ +
+Speed Bin +	+DDR3_1066F +	+Provide the Speed Bin +
+BANK Address Count +	+3 +	+Defines the bank to which an active an ACTIVE, READ, WRITE, or Precharge Command is being applied +
+ROW Address Count +	+15 +	+Provide the Row address for ACTIVE commands +
+COLUMN Address Count +	+10 +	+Provide the Row address for READ/WRITE commands +
+CAS Latency +	+7 +	+Select the Column Access Strobe (CAS) Latency. It refers to the amount of time it takes for data to appear on the pins of the memory module +
+CAS Write Latency +	+6 +	+Select the CAS Write Latency +
+RAS to CAS Delay +	+7 +	+Provide the row address to column address delay time. tRCD is t he time required between the memory controller asserting a row address strobe (RAS), and then asserting the column address strobe (CAS) +
+RECHARGE Time +	+7 +	+Precharge Time (tRP) is the number of clock cycles needed o terminate acces s to an open row of memory, and open access to the next row +
+tRC (ns ) +	+49.5 +	+Provide the Row cycle time tRC (ns) +
+tRASmin ( ns ) +	+36.0 +	+tRASmin (ns) is the minimum number of clock cycles required between an Active command and issuing the Precharge command +
+tFAW +	+30.0 +	+It restricts the number of activates that can be done within a certain window of time +
+ADDITIVE Latency +	+0 +	+Provide the Additive Latency (ns). Increases the efficiency of the command and data bus for sustainable bandwidths +
+Write levelling +	+1 +	+ +
+Read gate +	+1 +	+ +
+Read gate +	+1 +	+ +
+DQS to Clock delay [0] (ns) +	+0.217 +	+The daly difference of each DQS path delay subtracted from the clock path delay +
+DQS to Clock delay [1] (ns) +	+0.133 +	+The daly difference of each DQS path delay subtracted from the clock path delay +
+DQS to Clock delay [2] (ns) +	+0.089 +	+The daly difference of each DQS path delay subtracted from the clock path delay +
+DQS to Clock delay [3] (ns) +	+0.248 +	+The daly difference of each DQS path delay subtracted from the clock path delay +
+Board delay [0] (ns) +	+0.537 +	+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+Board delay [1] (ns) +	+0.442 +	+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+Board delay [2] (ns) +	+0.464 +	+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +
+Board delay [3] (ns) +	+0.521 +	+The average of the data midpoint delay, of the data delays associated with a byte lane (DDR_DQ, DDR_DM) averaged with the midpoint of the cloc kdelays (DDR_CK, DR_CK_N) +

PS Clocks information

PS Reference Clock : 33.333333

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Peripheral +	+PLL source +	+Frequency (MHz) +
+CPU 6x Freq (MHz) +	+ARM PLL +	+666.666687 +
+QSPI Flash Freq (MHz) +	+IO PLL +	+200.000000 +
+ENET0 Freq (MHz) +	+IO PLL +	+25.000000 +
+SDIO Freq (MHz) +	+IO PLL +	+50.000000 +
+UART Freq (MHz) +	+IO PLL +	+50.000000 +
+CAN Freq (MHz) +	+IO PLL +	+23.809523 +
+TTC0 CLK0 Freq (MHz) +	+CPU_1X +	+111.111115 +
+TTC0 CLK1 Freq (MHz) +	+CPU_1X +	+111.111115 +
+TTC0 CLK2 Freq (MHz) +	+CPU_1X +	+111.111115 +
+FPGA0 Freq (MHz) +	+IO PLL +	+50.000000 +
+FPGA1 Freq (MHz) +	+IO PLL +	+50.000000 +
+FPGA2 Freq (MHz) +	+IO PLL +	+50.000000 +
+FPGA3 Freq (MHz) +	+IO PLL +	+50.000000 +

ps7_pll_init_data_3_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +ARM_PLL_CFG + +	+0XF8000110 +	+32 +	+RW +	+0x000000 +	+ARM PLL Configuration +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_CLK_CTRL + +	+0XF8000120 +	+32 +	+RW +	+0x000000 +	+CPU Clock Control +
+ +DDR_PLL_CFG + +	+0XF8000114 +	+32 +	+RW +	+0x000000 +	+DDR PLL Configuration +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_CLK_CTRL + +	+0XF8000124 +	+32 +	+RW +	+0x000000 +	+DDR Clock Control +
+ +IO_PLL_CFG + +	+0XF8000118 +	+32 +	+RW +	+0x000000 +	+IO PLL Configuration +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_pll_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CFG +	+0XF8000110 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before syaing locked. +
+ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
+

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
+

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
+

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value): 0: PLL mode is set based on pin strap setting. 1: PLL bypassed regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
+

Register ( slcr )ARM_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_CLK_CTRL +	+0XF8000120 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: ARM PLL 10: DDR PLL 11: IO PLL This field is reset by POR only. +
+DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
+CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
+CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
+CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
+CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
+CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
+

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CFG +	+0XF8000114 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
+DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for the PLL. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
+

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
+

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
+

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +DDR PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
+

Register ( slcr )DDR_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_CLK_CTRL +	+0XF8000124 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +DDR_3x Clock control: 0: disable, 1: enable +
+DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +DDR_2x Clock control: 0: disable, 1: enable +
+DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Frequency divisor for the ddr_3x clock +
+DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Frequency divisor for the ddr_2x clock +
+DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
+

IO PLL INIT

Register ( slcr )IO_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CFG +	+0XF8000118 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned with a certain window before staying locked. +
+IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into reset mode. Refer to the Zynq-7000 TRM, UG585, Clocks chapter for CP/RES/CNT values for programming the PLL. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
+

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
+

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
+

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +PLL Reset control: 0: de-assert (PLL operating) 1: assert (PLL held in reset) +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +IO PLL Bypass override control: PLL_BYPASS_QUAL = 0 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL = 1 (QUAL bit default value) 0: PLL mode is set based on pin strap setting. 1: PLL bypass is enabled regardless of the pin strapping. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +Write the lock key, 0x767B, to write protect the slcr registers: all slcr registers, 0xF800_0000 to 0xF800_0B74, are write protected until the unlock key is written to the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_clock_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +DCI_CLK_CTRL + +	+0XF8000128 +	+32 +	+RW +	+0x000000 +	+DCI clock control +
+ +GEM0_RCLK_CTRL + +	+0XF8000138 +	+32 +	+RW +	+0x000000 +	+GigE 0 Rx Clock and Rx Signals Select +
+ +GEM0_CLK_CTRL + +	+0XF8000140 +	+32 +	+RW +	+0x000000 +	+GigE 0 Ref Clock Control +
+ +LQSPI_CLK_CTRL + +	+0XF800014C +	+32 +	+RW +	+0x000000 +	+Quad SPI Ref Clock Control +
+ +SDIO_CLK_CTRL + +	+0XF8000150 +	+32 +	+RW +	+0x000000 +	+SDIO Ref Clock Control +
+ +UART_CLK_CTRL + +	+0XF8000154 +	+32 +	+RW +	+0x000000 +	+UART Ref Clock Control +
+ +CAN_CLK_CTRL + +	+0XF800015C +	+32 +	+RW +	+0x000000 +	+CAN Ref Clock Control +
+ +CAN_MIOCLK_CTRL + +	+0XF8000160 +	+32 +	+RW +	+0x000000 +	+CAN MIO Clock Control +
+ +PCAP_CLK_CTRL + +	+0XF8000168 +	+32 +	+RW +	+0x000000 +	+PCAP Clock Control +
+ +FPGA0_CLK_CTRL + +	+0XF8000170 +	+32 +	+RW +	+0x000000 +	+PL Clock 0 Output control +
+ +FPGA1_CLK_CTRL + +	+0XF8000180 +	+32 +	+RW +	+0x000000 +	+PL Clock 1 Output control +
+ +FPGA2_CLK_CTRL + +	+0XF8000190 +	+32 +	+RW +	+0x000000 +	+PL Clock 2 output control +
+ +FPGA3_CLK_CTRL + +	+0XF80001A0 +	+32 +	+RW +	+0x000000 +	+PL Clock 3 output control +
+ +CLK_621_TRUE + +	+0XF80001C4 +	+32 +	+RW +	+0x000000 +	+CPU Clock Ratio Mode select +
+ +APER_CLK_CTRL + +	+0XF800012C +	+32 +	+RW +	+0x000000 +	+AMBA Peripheral Clock Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_clock_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DCI_CLK_CTRL +	+0XF8000128 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +DCI clock control - 0: disable, 1: enable +
+DIVISOR0 + +13:8 + +3f00 + +23 + +2300 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +302301 + +DCI clock control +
+

Register ( slcr )GEM0_RCLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GEM0_RCLK_CTRL +	+0XF8000138 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
+SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source of the Rx clock, control and data signals: 0: MIO 1: EMIO +
+GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock and Rx Signals Select +
+

Register ( slcr )GEM0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GEM0_CLK_CTRL +	+0XF8000140 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controller 0 Reference Clock control 0: disable, 1: enable +
+SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source to generate the reference clock 00x: IO PLL. 010: ARM PLL. 011: DDR PLL 1xx: Ethernet controller 0 EMIO clock +
+DIVISOR + +13:8 + +3f00 + +8 + +800 + +First divisor for Ethernet controller 0 source clock. +
+DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Second divisor for Ethernet controller 0 source clock. +
+GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +500801 + +GigE 0 Ref Clock Control +
+

Register ( slcr )LQSPI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LQSPI_CLK_CTRL +	+0XF800014C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
+LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
+

Register ( slcr )SDIO_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SDIO_CLK_CTRL +	+0XF8000150 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO Controller 0 Clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO Controller 1 Clock control. 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock. 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +1401 + +SDIO Ref Clock Control +
+

Register ( slcr )UART_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+UART_CLK_CTRL +	+0XF8000154 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +14 + +1400 + +Divisor for UART Controller source clock. +
+UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +1402 + +UART Ref Clock Control +
+

Register ( slcr )CAN_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CAN_CLK_CTRL +	+0XF800015C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +CAN 0 Reference Clock active: 0: Clock is disabled 1: Clock is enabled +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +CAN 1 Reference Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +e + +e00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider. +
+CAN_CLK_CTRL@0XF800015C + +31:0 + +3f03f33 + + + +300e01 + +CAN Ref Clock Control +
+

Register ( slcr )CAN_MIOCLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CAN_MIOCLK_CTRL +	+0XF8000160 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CAN0_MUX + +5:0 + +3f + +0 + +0 + +CAN 0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN0_REF_SEL + +6:6 + +40 + +0 + +0 + +CAN 0 Reference Clock selection: 0: From internal PLL 1: From MIO based on the next field +
+CAN1_MUX + +21:16 + +3f0000 + +0 + +0 + +CAN 1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN1_REF_SEL + +22:22 + +400000 + +0 + +0 + +CAN 1 Reference Clock selection: 0: From internal PLL. 1: From MIO based on the next field +
+CAN_MIOCLK_CTRL@0XF8000160 + +31:0 + +7f007f + + + +0 + +CAN MIO Clock Control +
+

Register ( slcr )PCAP_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PCAP_CLK_CTRL +	+0XF8000168 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
+

Register ( slcr )FPGA0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA0_CLK_CTRL +	+0XF8000170 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 0 Output control +
+

Register ( slcr )FPGA1_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA1_CLK_CTRL +	+0XF8000180 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 1 Output control +
+

Register ( slcr )FPGA2_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA2_CLK_CTRL +	+0XF8000190 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 2 output control +
+

Register ( slcr )FPGA3_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA3_CLK_CTRL +	+0XF80001A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 3 output control +
+

Register ( slcr )CLK_621_TRUE

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CLK_621_TRUE +	+0XF80001C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ratio: (When this register changes, no access are allowed to OCM.) 0: 4:2:1 1: 6:2:1 +
+CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
+

Register ( slcr )APER_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+APER_CLK_CTRL +	+0XF800012C +	+32 +	+rw +	+0x00000000 +	+-- +

THIS SHOULD BE BLANK

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ +

ps7_ddr_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +ddrc_ctrl + +	+0XF8006000 +	+32 +	+RW +	+0x000000 +	+DDRC Control +
+ +Two_rank_cfg + +	+0XF8006004 +	+32 +	+RW +	+0x000000 +	+Two Rank Configuration +
+ +HPR_reg + +	+0XF8006008 +	+32 +	+RW +	+0x000000 +	+HPR Queue control +
+ +LPR_reg + +	+0XF800600C +	+32 +	+RW +	+0x000000 +	+LPR Queue control +
+ +WR_reg + +	+0XF8006010 +	+32 +	+RW +	+0x000000 +	+WR Queue control +
+ +DRAM_param_reg0 + +	+0XF8006014 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 0 +
+ +DRAM_param_reg1 + +	+0XF8006018 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 1 +
+ +DRAM_param_reg2 + +	+0XF800601C +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 2 +
+ +DRAM_param_reg3 + +	+0XF8006020 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 3 +
+ +DRAM_param_reg4 + +	+0XF8006024 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 4 +
+ +DRAM_init_param + +	+0XF8006028 +	+32 +	+RW +	+0x000000 +	+DRAM Initialization Parameters +
+ +DRAM_EMR_reg + +	+0XF800602C +	+32 +	+RW +	+0x000000 +	+DRAM EMR2, EMR3 access +
+ +DRAM_EMR_MR_reg + +	+0XF8006030 +	+32 +	+RW +	+0x000000 +	+DRAM EMR, MR access +
+ +DRAM_burst8_rdwr + +	+0XF8006034 +	+32 +	+RW +	+0x000000 +	+DRAM Burst 8 read/write +
+ +DRAM_disable_DQ + +	+0XF8006038 +	+32 +	+RW +	+0x000000 +	+DRAM Disable DQ +
+ +DRAM_addr_map_bank + +	+0XF800603C +	+32 +	+RW +	+0x000000 +	+Row/Column address bits +
+ +DRAM_addr_map_col + +	+0XF8006040 +	+32 +	+RW +	+0x000000 +	+Column address bits +
+ +DRAM_addr_map_row + +	+0XF8006044 +	+32 +	+RW +	+0x000000 +	+Select DRAM row address bits +
+ +DRAM_ODT_reg + +	+0XF8006048 +	+32 +	+RW +	+0x000000 +	+DRAM ODT control +
+ +phy_cmd_timeout_rddata_cpt + +	+0XF8006050 +	+32 +	+RW +	+0x000000 +	+PHY command time out and read data capture FIFO +
+ +DLL_calib + +	+0XF8006058 +	+32 +	+RW +	+0x000000 +	+DLL calibration +
+ +ODT_delay_hold + +	+0XF800605C +	+32 +	+RW +	+0x000000 +	+ODT delay and ODT hold +
+ +ctrl_reg1 + +	+0XF8006060 +	+32 +	+RW +	+0x000000 +	+Controller 1 +
+ +ctrl_reg2 + +	+0XF8006064 +	+32 +	+RW +	+0x000000 +	+Controller 2 +
+ +ctrl_reg3 + +	+0XF8006068 +	+32 +	+RW +	+0x000000 +	+Controller 3 +
+ +ctrl_reg4 + +	+0XF800606C +	+32 +	+RW +	+0x000000 +	+Controller 4 +
+ +ctrl_reg5 + +	+0XF8006078 +	+32 +	+RW +	+0x000000 +	+Controller register 5 +
+ +ctrl_reg6 + +	+0XF800607C +	+32 +	+RW +	+0x000000 +	+Controller register 6 +
+ +CHE_T_ZQ + +	+0XF80060A4 +	+32 +	+RW +	+0x000000 +	+ZQ parameters +
+ +CHE_T_ZQ_Short_Interval_Reg + +	+0XF80060A8 +	+32 +	+RW +	+0x000000 +	+Misc parameters +
+ +deep_pwrdwn_reg + +	+0XF80060AC +	+32 +	+RW +	+0x000000 +	+Deep powerdown (LPDDR2) +
+ +reg_2c + +	+0XF80060B0 +	+32 +	+RW +	+0x000000 +	+Training control +
+ +reg_2d + +	+0XF80060B4 +	+32 +	+RW +	+0x000000 +	+Misc Debug +
+ +dfi_timing + +	+0XF80060B8 +	+32 +	+RW +	+0x000000 +	+DFI timing +
+ +CHE_ECC_CONTROL_REG_OFFSET + +	+0XF80060C4 +	+32 +	+RW +	+0x000000 +	+ECC error clear +
+ +CHE_ECC_CONTROL_REG_OFFSET + +	+0XF80060C4 +	+32 +	+RW +	+0x000000 +	+ECC error clear +
+ +CHE_CORR_ECC_LOG_REG_OFFSET + +	+0XF80060C8 +	+32 +	+RW +	+0x000000 +	+ECC error correction +
+ +CHE_UNCORR_ECC_LOG_REG_OFFSET + +	+0XF80060DC +	+32 +	+RW +	+0x000000 +	+ECC unrecoverable error status +
+ +CHE_ECC_STATS_REG_OFFSET + +	+0XF80060F0 +	+32 +	+RW +	+0x000000 +	+ECC error count +
+ +ECC_scrub + +	+0XF80060F4 +	+32 +	+RW +	+0x000000 +	+ECC mode/scrub +
+ +phy_rcvr_enable + +	+0XF8006114 +	+32 +	+RW +	+0x000000 +	+Phy receiver enable register +
+ +PHY_Config + +	+0XF8006118 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config + +	+0XF800611C +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config + +	+0XF8006120 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config + +	+0XF8006124 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +phy_init_ratio + +	+0XF800612C +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio + +	+0XF8006130 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio + +	+0XF8006134 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio + +	+0XF8006138 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF8006140 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF8006144 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF8006148 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF800614C +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF8006154 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF8006158 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF800615C +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF8006160 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_we_cfg + +	+0XF8006168 +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg + +	+0XF800616C +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg + +	+0XF8006170 +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg + +	+0XF8006174 +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 0. +
+ +wr_data_slv + +	+0XF800617C +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv + +	+0XF8006180 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv + +	+0XF8006184 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv + +	+0XF8006188 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 0. +
+ +reg_64 + +	+0XF8006190 +	+32 +	+RW +	+0x000000 +	+Training control 2 +
+ +reg_65 + +	+0XF8006194 +	+32 +	+RW +	+0x000000 +	+Training control 3 +
+ +page_mask + +	+0XF8006204 +	+32 +	+RW +	+0x000000 +	+Page mask +
+ +axi_priority_wr_port + +	+0XF8006208 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port + +	+0XF800620C +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port + +	+0XF8006210 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port + +	+0XF8006214 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_rd_port + +	+0XF8006218 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port + +	+0XF800621C +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port + +	+0XF8006220 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port + +	+0XF8006224 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +lpddr_ctrl0 + +	+0XF80062A8 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 0 +
+ +lpddr_ctrl1 + +	+0XF80062AC +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 1 +
+ +lpddr_ctrl2 + +	+0XF80062B0 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 2 +
+ +lpddr_ctrl3 + +	+0XF80062B4 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 3 +
+ +ddrc_ctrl + +	+0XF8006000 +	+32 +	+RW +	+0x000000 +	+DDRC Control +

ps7_ddr_init_data_3_0

+ + + + + + + + + +

DDR INITIALIZATION

LOCK DDR

Register ( slcr )ddrc_ctrl

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ddrc_ctrl +	+0XF8006000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
+

Register ( slcr )Two_rank_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Two_rank_cfg +	+0XF8006004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
+reserved_reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Reserved. Do not modify. +
+reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
+Two_rank_cfg@0XF8006004 + +31:0 + +7ffff + + + +1081 + +Two Rank Configuration +
+

Register ( slcr )HPR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+HPR_reg +	+0XF8006008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of counts that the HPR queue is guaranteed to be non-critical (1 count = 32 DDR clocks). +
+reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
+HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control +
+

Register ( slcr )LPR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LPR_reg +	+0XF800600C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpr_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clocks that the LPR queue is guaranteed to be non-critical. Unit: 32 clocks +
+reg_ddrc_lpr_max_starve_x32 + +21:11 + +3ff800 + +2 + +1000 + +Number of clocks that the LPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_lpr_xact_run_length + +25:22 + +3c00000 + +8 + +2000000 + +Number of transactions that will be serviced once the LPR queue goes critical is the smaller of this number and the number of transactions available +
+LPR_reg@0XF800600C + +31:0 + +3ffffff + + + +2001001 + +LPR Queue control +
+

Register ( slcr )WR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+WR_reg +	+0XF8006010 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_w_min_non_critical_x32 + +10:0 + +7ff + +1 + +1 + +Number of clock cycles that the WR queue is guaranteed to be non-critical. +
+reg_ddrc_w_xact_run_length + +14:11 + +7800 + +8 + +4000 + +Number of transactions that will be serviced once the WR queue goes critical is the smaller of this number and the number of transactions available +
+reg_ddrc_w_max_starve_x32 + +25:15 + +3ff8000 + +2 + +10000 + +Number of clocks that the Write queue can be starved before it goes critical. Unit: 32 clocks. FOR PERFORMANCE ONLY. +
+WR_reg@0XF8006010 + +31:0 + +3ffffff + + + +14001 + +WR Queue control +
+

Register ( slcr )DRAM_param_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg0 +	+0XF8006014 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM Related. Default value is set for DDR3. +
+reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +56 + +1580 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75nS to 195nS). DRAM Related. Default value is set for DDR3. Dynamic Bit Field. +
+reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks. DRAM Related +
+DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4159b + +DRAM Parameters 0 +
+

Register ( slcr )DRAM_param_reg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg1 +	+0XF8006018 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank DDR and DDR3: WL + BL/2 + tWR LPDDR2: WL + BL/2 + tWR + 1 Unit: Clocks where, WL: write latency. BL: burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR: write recovery time. This comes directly from the DRAM specs. +
+reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
+reg_ddrc_t_faw + +15:10 + +fc00 + +10 + +4000 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks. DRAM Related. +
+reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec is 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM related. +
+reg_ddrc_t_ras_min + +26:22 + +7c00000 + +14 + +5000000 + +tRAS(min) - Minimum time between activate and precharge to the same bank (spec is 45 ns). Unit: clocks DRAM related. Default value is set for DDR3. +
+reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. DDR2 and DDR3: Set this to tCKE value. LPDDR2: Set this to the larger of tCKE or tCKESR. Unit: clocks. +
+DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +452440d2 + +DRAM Parameters 1 +
+

Register ( slcr )DRAM_param_reg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg2 +	+0XF800601C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. In non-LPDDR mode, the minimum DRAM Write Latency (DDR2) supported is 3. In LPDDR mode, the required DRAM Write Latency of 1 is supported. Since write latency (CWL) min is 3, and DDR2 CWL is CL-1, the min (DDR2) CL supported is 4 +
+reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
+reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
+reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
+reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
+reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
+reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
+DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
+

Register ( slcr )DRAM_param_reg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg3 +	+0XF8006020 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
+reg_ddrc_t_rrd + +7:5 + +e0 + +4 + +80 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
+reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
+reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
+reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
+reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
+reg_ddrc_en_dfi_dram_clk_disable + +23:23 + +800000 + +0 + +0 + +Enables the assertion of ddrc_dfi_dram_clk_disable. In DDR2/DDR3, only asserted in Self Refresh. In mDDR/LPDDR2, can be asserted in following: - during normal operation (Clock Stop), - in Power Down - in Self Refresh - In Deep Power Down +
+reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
+reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
+reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
+DRAM_param_reg3@0XF8006020 + +31:0 + +7fdffffc + + + +27087290 + +DRAM Parameters 3 +
+

Register ( slcr )DRAM_param_reg4

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg4 +	+0XF8006024 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
+reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
+reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
+reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
+reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
+ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
+reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
+reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
+DRAM_param_reg4@0XF8006024 + +31:0 + +fffffc3 + + + +0 + +DRAM Parameters 4 +
+

Register ( slcr )DRAM_init_param

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_init_param +	+0XF8006028 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
+reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
+reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands. DRAM related. Default value is set for DDR3. +
+DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM Initialization Parameters +
+

Register ( slcr )DRAM_EMR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_EMR_reg +	+0XF800602C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2: Value loaded into EMR2 register DDR3: Value loaded into MR2 register LPDDR2: Value loaded into MR3 register +
+reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2: Value loaded into EMR3 register DDR3: Value loaded into MR3 register. Set Bit[2:0] to 3'b000. These bits are set appropriately by the Controller during Read Data eye training and Read DQS gate leveling. LPDDR2: Unused +
+DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
+

Register ( slcr )DRAM_EMR_MR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_EMR_MR_reg +	+0XF8006030 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2: Value loaded into MR register. (Bit[8] is for DLL and the setting here is ignored. Controller sets this bit appropriately DDR3: Value loaded into MR0 register. LPDDR2: Value loaded into MR1 register +
+reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2: Value loaded into EMR1register. (Bits[9:7] are for OCD and the setting in this reg is ignored. Controller sets this bits appropriately during initialization DDR3: Value loaded into MR1 register. Set Bit[7] to 0. This bit is set appropriately by the Controller during Write Leveling LPDDR2: Value loaded into MR2 register +
+DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
+

Register ( slcr )DRAM_burst8_rdwr

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_burst8_rdwr +	+0XF8006034 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +Controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. 0010: Burst length of 4 0100: Burst length of 8 1000: Burst length of 16 (LPDDR2 with ___-bit data) All other values are reserved +
+reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +105 + +1050 + +Clock cycles to wait after a DDR software reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 uS. LPDDR2 - tINIT0 of 20 mS (max) + tINIT1 of 100 nS (min) +
+reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Clock cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
+reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
+DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +11054 + +DRAM Burst 8 read/write +
+

Register ( slcr )DRAM_disable_DQ

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_disable_DQ +	+0XF8006038 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
+reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
+DRAM_disable_DQ@0XF8006038 + +31:0 + +3 + + + +0 + +DRAM Disable DQ +
+

Register ( slcr )DRAM_addr_map_bank

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_bank +	+0XF800603C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
+reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
+

Register ( slcr )DRAM_addr_map_col

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_col +	+0XF8006040 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
+

Register ( slcr )DRAM_addr_map_row

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_row +	+0XF8006044 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
+reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 8, Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
+reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 7, Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
+reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 6, Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
+reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 5, Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
+DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
+

Register ( slcr )DRAM_ODT_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_ODT_reg +	+0XF8006048 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
+reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
+reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
+DRAM_ODT_reg@0XF8006048 + +31:0 + +3f000 + + + +3c000 + +DRAM ODT control +
+

Register ( slcr )phy_cmd_timeout_rddata_cpt

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_cmd_timeout_rddata_cpt +	+0XF8006050 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
+reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
+reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
+reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
+reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
+reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
+reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
+

Register ( slcr )DLL_calib

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DLL_calib +	+0XF8006058 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
+DLL_calib@0XF8006058 + +31:0 + +10000 + + + +0 + +DLL calibration +
+

Register ( slcr )ODT_delay_hold

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ODT_delay_hold +	+0XF800605C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
+reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable to LPDDR2. +
+reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
+reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
+ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold +
+

Register ( slcr )ctrl_reg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg1 +	+0XF8006060 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
+reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
+reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
+reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
+reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
+reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
+reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
+ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
+

Register ( slcr )ctrl_reg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg2 +	+0XF8006064 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
+reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +0: Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 0. 1: Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on Urgent input coming from AXI master. +
+ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller 2 +
+

Register ( slcr )ctrl_reg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg3 +	+0XF8006068 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +DDR2: not applicable. LPDDR2 and DDR3: Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) +
+reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +DDR2 and LPDDR2: not applicable. DDR3: Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHYs operating in PHY RdLvl Evaluation mode. +
+reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +DDR2 and LPDDR2: not applicable. DDR3: First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. +
+ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller 3 +
+

Register ( slcr )ctrl_reg4

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg4 +	+0XF800606C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_t_ctrlupd_interval_min_x1024 + +7:0 + +ff + +10 + +10 + +This is the minimum amount of time between Controller initiated DFI update requests (which will be executed whenever the controller is idle). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the first read request when the controller is idle. Units: 1024 clocks +
+dfi_t_ctrlupd_interval_max_x1024 + +15:8 + +ff00 + +16 + +1600 + +This is the maximum amount of time between Controller initiated DFI update requests. This timer resets with each update request; when the timer expires, traffic is blocked for a few cycles. PHY can use this idle time to recalibrate the delay lines to the DLLs. The DLL calibration is also used to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance. Units: 1024 clocks +
+ctrl_reg4@0XF800606C + +31:0 + +ffff + + + +1610 + +Controller 4 +
+

Register ( slcr )ctrl_reg5

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg5 +	+0XF8006078 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
+reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
+reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
+ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
+

Register ( slcr )ctrl_reg6

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg6 +	+0XF800607C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
+ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
+

Register ( slcr )CHE_T_ZQ

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_T_ZQ +	+0XF80060A4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
+reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum d'128) +
+reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
+reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
+CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
+

Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_T_ZQ_Short_Interval_Reg +	+0XF80060A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +DDR2: not used. LPDDR2 and DDR3: Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. +
+dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters +
+

Register ( slcr )deep_pwrdwn_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+deep_pwrdwn_reg +	+0XF80060AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+deeppowerdown_en + +0:0 + +1 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: Brings Controller out of Deep Powerdown mode. 1: Puts DRAM into Deep Powerdown mode when the transaction store is empty. For performance only. Dynamic Bit Field. +
+deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +DDR2 and DDR3: not sued. LPDDR2: Minimum deep power down time. DDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. Value from the spec is 500us. Units are in 1024 clock cycles. For performance only. +
+deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown (LPDDR2) +
+

Register ( slcr )reg_2c

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_2c +	+0XF80060B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
+ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
+reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
+reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
+

Register ( slcr )reg_2d

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_2d +	+0XF80060B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
+reg_2d@0XF80060B4 + +31:0 + +200 + + + +200 + +Misc Debug +
+

Register ( slcr )dfi_timing

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+dfi_timing +	+0XF80060B8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. DDR2 and DDR3: RL - 1 LPDDR: RL Where RL is read latency of DRAM. +
+reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
+reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
+dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing +
+

RESET ECC ERROR

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_CONTROL_REG_OFFSET +	+0XF80060C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +1 + +1 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +1 + +2 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +3 + +ECC error clear +
+

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_CONTROL_REG_OFFSET +	+0XF80060C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
+

Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_CORR_ECC_LOG_REG_OFFSET +	+0XF80060C8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when a correctable ECC error is captured. As long as this is 1 no further ECC errors will be captured. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
+ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction +
+

Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_UNCORR_ECC_LOG_REG_OFFSET +	+0XF80060DC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to 1 when an uncorrectable ECC error is captured. As long as this is a 1, no further ECC errors will be captured. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status +
+

Register ( slcr )CHE_ECC_STATS_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_STATS_REG_OFFSET +	+0XF80060F0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
+STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of uncorrectable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
+

Register ( slcr )ECC_scrub

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ECC_scrub +	+0XF80060F4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 000 (No ECC) and 100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 : No ECC, 001: Reserved 010: Parity 011: Reserved 100: SEC/DED over 1-beat 101: SEC/DED over multiple beats 110: Device Correction 111: Reserved +
+reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +0: Enable ECC scrubs (valid only when reg_ddrc_ecc_mode = 100). 1: Disable ECC scrubs +
+ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub +
+

Register ( slcr )phy_rcvr_enable

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rcvr_enable +	+0XF8006114 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_dif_on + +3:0 + +f + +0 + +0 + +Value to drive to IO receiver enable pins when turning it ON. When NOT in powerdown or self-refresh (when CKE=1) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. +
+reg_phy_dif_off + +7:4 + +f0 + +0 + +0 + +Value to drive to IO receiver enable pins when turning it OFF. When in powerdown or self-refresh (CKE=0) this value will be sent to the IOs to control receiver on/off. IOD is the size specified by the IO_DIFEN_SIZE parameter. Depending on the IO, one of these signals dif_on or dif_off can be used. +
+phy_rcvr_enable@0XF8006114 + +31:0 + +ff + + + +0 + +Phy receiver enable register +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF8006118 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006118 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF800611C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF800611C + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF8006120 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006120 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF8006124 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006124 + +31:0 + +7fffffcf + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF800612C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +1d + +1d + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +f2 + +3c800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF800612C + +31:0 + +fffff + + + +3c81d + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF8006130 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +12 + +12 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +d8 + +36000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +36012 + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF8006134 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +c + +c + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +de + +37800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +3780c + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF8006138 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +21 + +21 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +ee + +3b800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +3b821 + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF8006140 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF8006144 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF8006148 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF800614C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_rd_dqs_slave_ratio for the read DQS slave DLL 1: overwrite the delay/tap value for read DQS slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF8006154 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +9d + +9d + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +9d + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF8006158 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +92 + +92 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +92 + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF800615C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +8c + +8c + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +8c + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF8006160 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +a1 + +a1 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. (Used to program the manual training ratio value) +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: Use reg_phy_wr_dqs_slave_ratio for the write DQS slave DLL 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +a1 + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF8006168 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +147 + +147 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +147 + +PHY FIFO write enable configuration for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF800616C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +12d + +12d + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +12d + +PHY FIFO write enable configuration for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF8006170 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +133 + +133 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +133 + +PHY FIFO write enable configuration for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF8006174 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +143 + +143 + +Ratio value to be used when reg_phy_fifo_we_in_force is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +0: Use reg_phy_fifo_we_slave_ratio as ratio value for fifo_we_X slave DLL 1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the reg_phy_fifo_we_in_delay bus. i.e. The 'force' bit selects between specifying the delay in 'ratio' units or tap delay units +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when reg_phy_fifo_we_in_force is set to 1. +
+phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +143 + +PHY FIFO write enable configuration for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF800617C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +dd + +dd + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF800617C + +31:0 + +fffff + + + +dd + +PHY write data slave ratio config for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF8006180 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +d2 + +d2 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +d2 + +PHY write data slave ratio config for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF8006184 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +cc + +cc + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +cc + +PHY write data slave ratio config for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF8006188 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +e1 + +e1 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: Selects reg_phy_wr_data_slave_ratio for write data slave DLL 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +e1 + +PHY write data slave ratio config for data slice 0. +
+

Register ( slcr )reg_64

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_64 +	+0XF8006190 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
+reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
+reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
+reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
+reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
+reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on board topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
+reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
+reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +0: Use reg_phy_ctrl_slave_ratio for address/command timing slave DLL 1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
+reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
+reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
+reg_64@0XF8006190 + +31:0 + +6ffffefe + + + +40080 + +Training control 2 +
+

Register ( slcr )reg_65

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_65 +	+0XF8006194 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
+reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
+reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
+reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
+reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
+reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
+reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
+

Register ( slcr )page_mask

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+page_mask +	+0XF8006204 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +Set this register based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
+page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF8006208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF8006208 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF800620C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF800620C + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF8006210 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF8006210 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF8006214 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+axi_priority_wr_port@0XF8006214 + +31:0 + +703ff + + + +3ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF8006218 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF800621C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF8006220 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF8006224 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )lpddr_ctrl0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl0 +	+0XF80062A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
+reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. This feature should only be enabled after LPDDR2 initialization is completed +
+reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
+lpddr_ctrl0@0XF80062A8 + +31:0 + +ff5 + + + +0 + +LPDDR2 Control 0 +
+

Register ( slcr )lpddr_ctrl1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl1 +	+0XF80062AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. +
+lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 +
+

Register ( slcr )lpddr_ctrl2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl2 +	+0XF80062B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
+reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Units: 32 clock cycles. +
+reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
+lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 +
+

Register ( slcr )lpddr_ctrl3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl3 +	+0XF80062B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
+reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
+lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 +
+

POLL ON DCI STATUS

Register ( slcr )DDRIOB_DCI_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_STATUS +	+0XF8000B74 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DONE + +13:13 + +2000 + +1 + +2000 + +DCI done signal +
+DDRIOB_DCI_STATUS@0XF8000B74 + +31:0 + +2000 + + + +2000 + +tobe +
+

UNLOCK DDR

Register ( slcr )ddrc_ctrl

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ddrc_ctrl +	+0XF8006000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
+

CHECK DDR STATUS

Register ( slcr )mode_sts_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+mode_sts_reg +	+0XF8006054 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Powerdown mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
+mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
+

+ +

ps7_mio_init_data_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +GPIOB_CTRL + +	+0XF8000B00 +	+32 +	+RW +	+0x000000 +	+PS IO Buffer Control +
+ +DDRIOB_ADDR0 + +	+0XF8000B40 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for A[14:0], CKE and DRST_B +
+ +DDRIOB_ADDR1 + +	+0XF8000B44 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
+ +DDRIOB_DATA0 + +	+0XF8000B48 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + +	+0XF8000B4C +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + +	+0XF8000B50 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + +	+0XF8000B54 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 3:2 +
+ +DDRIOB_CLOCK + +	+0XF8000B58 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Clock Output +
+ +DDRIOB_DRIVE_SLEW_ADDR + +	+0XF8000B5C +	+32 +	+RW +	+0x000000 +	+Drive and Slew controls for Address and Command pins of the DDR Interface +
+ +DDRIOB_DRIVE_SLEW_DATA + +	+0XF8000B60 +	+32 +	+RW +	+0x000000 +	+Drive and Slew controls for DQ pins of the DDR Interface +
+ +DDRIOB_DRIVE_SLEW_DIFF + +	+0XF8000B64 +	+32 +	+RW +	+0x000000 +	+Drive and Slew controls for DQS pins of the DDR Interface +
+ +DDRIOB_DRIVE_SLEW_CLOCK + +	+0XF8000B68 +	+32 +	+RW +	+0x000000 +	+Drive and Slew controls for Clock pins of the DDR Interface +
+ +DDRIOB_DDR_CTRL + +	+0XF8000B6C +	+32 +	+RW +	+0x000000 +	+DDR IOB Buffer Control +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDR IOB DCI Config +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDR IOB DCI Config +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDR IOB DCI Config +
+ +MIO_PIN_00 + +	+0XF8000700 +	+32 +	+RW +	+0x000000 +	+MIO Pin 0 Control +
+ +MIO_PIN_01 + +	+0XF8000704 +	+32 +	+RW +	+0x000000 +	+MIO Pin 1 Control +
+ +MIO_PIN_02 + +	+0XF8000708 +	+32 +	+RW +	+0x000000 +	+MIO Pin 2 Control +
+ +MIO_PIN_03 + +	+0XF800070C +	+32 +	+RW +	+0x000000 +	+MIO Pin 3 Control +
+ +MIO_PIN_04 + +	+0XF8000710 +	+32 +	+RW +	+0x000000 +	+MIO Pin 4 Control +
+ +MIO_PIN_05 + +	+0XF8000714 +	+32 +	+RW +	+0x000000 +	+MIO Pin 5 Control +
+ +MIO_PIN_06 + +	+0XF8000718 +	+32 +	+RW +	+0x000000 +	+MIO Pin 6 Control +
+ +MIO_PIN_07 + +	+0XF800071C +	+32 +	+RW +	+0x000000 +	+MIO Pin 7 Control +
+ +MIO_PIN_08 + +	+0XF8000720 +	+32 +	+RW +	+0x000000 +	+MIO Pin 8 Control +
+ +MIO_PIN_09 + +	+0XF8000724 +	+32 +	+RW +	+0x000000 +	+MIO Pin 9 Control +
+ +MIO_PIN_10 + +	+0XF8000728 +	+32 +	+RW +	+0x000000 +	+MIO Pin 10 Control +
+ +MIO_PIN_11 + +	+0XF800072C +	+32 +	+RW +	+0x000000 +	+MIO Pin 11 Control +
+ +MIO_PIN_12 + +	+0XF8000730 +	+32 +	+RW +	+0x000000 +	+MIO Pin 12 Control +
+ +MIO_PIN_13 + +	+0XF8000734 +	+32 +	+RW +	+0x000000 +	+MIO Pin 13 Control +
+ +MIO_PIN_14 + +	+0XF8000738 +	+32 +	+RW +	+0x000000 +	+MIO Pin 14 Control +
+ +MIO_PIN_15 + +	+0XF800073C +	+32 +	+RW +	+0x000000 +	+MIO Pin 15 Control +
+ +MIO_PIN_16 + +	+0XF8000740 +	+32 +	+RW +	+0x000000 +	+MIO Pin 16 Control +
+ +MIO_PIN_17 + +	+0XF8000744 +	+32 +	+RW +	+0x000000 +	+MIO Pin 17 Control +
+ +MIO_PIN_18 + +	+0XF8000748 +	+32 +	+RW +	+0x000000 +	+MIO Pin 18 Control +
+ +MIO_PIN_19 + +	+0XF800074C +	+32 +	+RW +	+0x000000 +	+MIO Pin 19 Control +
+ +MIO_PIN_20 + +	+0XF8000750 +	+32 +	+RW +	+0x000000 +	+MIO Pin 20 Control +
+ +MIO_PIN_21 + +	+0XF8000754 +	+32 +	+RW +	+0x000000 +	+MIO Pin 21 Control +
+ +MIO_PIN_22 + +	+0XF8000758 +	+32 +	+RW +	+0x000000 +	+MIO Pin 22 Control +
+ +MIO_PIN_23 + +	+0XF800075C +	+32 +	+RW +	+0x000000 +	+MIO Pin 23 Control +
+ +MIO_PIN_24 + +	+0XF8000760 +	+32 +	+RW +	+0x000000 +	+MIO Pin 24 Control +
+ +MIO_PIN_25 + +	+0XF8000764 +	+32 +	+RW +	+0x000000 +	+MIO Pin 25 Control +
+ +MIO_PIN_26 + +	+0XF8000768 +	+32 +	+RW +	+0x000000 +	+MIO Pin 26 Control +
+ +MIO_PIN_27 + +	+0XF800076C +	+32 +	+RW +	+0x000000 +	+MIO Pin 27 Control +
+ +MIO_PIN_28 + +	+0XF8000770 +	+32 +	+RW +	+0x000000 +	+MIO Pin 28 Control +
+ +MIO_PIN_29 + +	+0XF8000774 +	+32 +	+RW +	+0x000000 +	+MIO Pin 29 Control +
+ +MIO_PIN_30 + +	+0XF8000778 +	+32 +	+RW +	+0x000000 +	+MIO Pin 30 Control +
+ +MIO_PIN_31 + +	+0XF800077C +	+32 +	+RW +	+0x000000 +	+MIO Pin 31 Control +
+ +MIO_PIN_32 + +	+0XF8000780 +	+32 +	+RW +	+0x000000 +	+MIO Pin 32 Control +
+ +MIO_PIN_33 + +	+0XF8000784 +	+32 +	+RW +	+0x000000 +	+MIO Pin 33 Control +
+ +MIO_PIN_34 + +	+0XF8000788 +	+32 +	+RW +	+0x000000 +	+MIO Pin 34 Control +
+ +MIO_PIN_35 + +	+0XF800078C +	+32 +	+RW +	+0x000000 +	+MIO Pin 35 Control +
+ +MIO_PIN_36 + +	+0XF8000790 +	+32 +	+RW +	+0x000000 +	+MIO Pin 36 Control +
+ +MIO_PIN_37 + +	+0XF8000794 +	+32 +	+RW +	+0x000000 +	+MIO Pin 37 Control +
+ +MIO_PIN_38 + +	+0XF8000798 +	+32 +	+RW +	+0x000000 +	+MIO Pin 38 Control +
+ +MIO_PIN_39 + +	+0XF800079C +	+32 +	+RW +	+0x000000 +	+MIO Pin 39 Control +
+ +MIO_PIN_40 + +	+0XF80007A0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 40 Control +
+ +MIO_PIN_41 + +	+0XF80007A4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 41 Control +
+ +MIO_PIN_42 + +	+0XF80007A8 +	+32 +	+RW +	+0x000000 +	+MIO Pin 42 Control +
+ +MIO_PIN_43 + +	+0XF80007AC +	+32 +	+RW +	+0x000000 +	+MIO Pin 43 Control +
+ +MIO_PIN_44 + +	+0XF80007B0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 44 Control +
+ +MIO_PIN_45 + +	+0XF80007B4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 45 Control +
+ +MIO_PIN_46 + +	+0XF80007B8 +	+32 +	+RW +	+0x000000 +	+MIO Pin 46 Control +
+ +MIO_PIN_47 + +	+0XF80007BC +	+32 +	+RW +	+0x000000 +	+MIO Pin 47 Control +
+ +MIO_PIN_48 + +	+0XF80007C0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 48 Control +
+ +MIO_PIN_49 + +	+0XF80007C4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 49 Control +
+ +MIO_PIN_50 + +	+0XF80007C8 +	+32 +	+RW +	+0x000000 +	+MIO Pin 50 Control +
+ +MIO_PIN_51 + +	+0XF80007CC +	+32 +	+RW +	+0x000000 +	+MIO Pin 51 Control +
+ +MIO_PIN_52 + +	+0XF80007D0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 52 Control +
+ +MIO_PIN_53 + +	+0XF80007D4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 53 Control +
+ +SD0_WP_CD_SEL + +	+0XF8000830 +	+32 +	+RW +	+0x000000 +	+SDIO 0 WP CD select +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_mio_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

OCM REMAPPING

Register ( slcr )GPIOB_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GPIOB_CTRL +	+0XF8000B00 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_EN + +0:0 + +1 + +1 + +1 + +Enables VREF internal generator +
+VREF_SEL + +6:4 + +70 + +0 + +0 + +Specifies GPIO VREF Selection 000 - VREF = Disabled 001 - VREF = 0.9V 010 - VREF = test only - 1.8V 100 - VREF = test only - 1.25V Other values reserved +
+GPIOB_CTRL@0XF8000B00 + +31:0 + +71 + + + +1 + +PS IO Buffer Control +
+

DDRIOB SETTINGS

Register ( slcr )DDRIOB_ADDR0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_ADDR0 +	+0XF8000B40 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for A[14:0], CKE and DRST_B +
+

Register ( slcr )DDRIOB_ADDR1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_ADDR1 +	+0XF8000B44 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for BA[2:0], ODT, CS_B, WE_B, RAS_B and CAS_B +
+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA0 +	+0XF8000B48 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA1 +	+0XF8000B4C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF0 +	+0XF8000B50 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF1 +	+0XF8000B54 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +3 + +60 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
+

Register ( slcr )DDRIOB_CLOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_CLOCK +	+0XF8000B58 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_INP_POWER + +0:0 + +1 + +0 + +0 + +Reserved. Do not modify. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer control: 00: Input off (input signal to selected controller is driven Low). 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE_B + +3:3 + +8 + +0 + +0 + +DCI Update Enable: 0: disable 1: enable +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enable: 0: disable 1: enable +
+DCI_TYPE + +6:5 + +60 + +0 + +0 + +DCI Mode Selection: 00: DCI Disabled (DDR2/3 ADDR and CLOCK) 01: DCI Drive (LPDDR2) 10: reserved 11: DCI Termination (DDR2/3 DATA and DIFF) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_ADDR +	+0XF8000B5C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +Drive and Slew controls for Address and Command pins of the DDR Interface +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_DATA +	+0XF8000B60 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQ pins of the DDR Interface +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_DIFF +	+0XF8000B64 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for DQS pins of the DDR Interface +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_CLOCK +	+0XF8000B68 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_DRIVE_P + +6:0 + +7f + +1c + +1c + +Reserved. Do not modify. +
+reserved_DRIVE_N + +13:7 + +3f80 + +c + +600 + +Reserved. Do not modify. +
+reserved_SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Reserved. Do not modify. +
+reserved_SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Reserved. Do not modify. +
+reserved_GTL + +26:24 + +7000000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_RTERM + +31:27 + +f8000000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +Drive and Slew controls for Clock pins of the DDR Interface +
+

Register ( slcr )DDRIOB_DDR_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DDR_CTRL +	+0XF8000B6C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_INT_EN + +0:0 + +1 + +1 + +1 + +Enables VREF internal generator +
+VREF_SEL + +4:1 + +1e + +4 + +8 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
+VREF_EXT_EN + +6:5 + +60 + +0 + +0 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1x: Enable External VREF for upper 16 bits +
+reserved_VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Reserved. Do not modify. +
+REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
+reserved_REFIO_TEST + +11:10 + +c00 + +3 + +c00 + +Reserved. Do not modify. +
+reserved_REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Reserved. Do not modify. +
+reserved_CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Reserved. Do not modify. +
+DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +e09 + +DDR IOB Buffer Control +
+

ASSERT RESET

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialize flops in DCI system +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +1 + + + +1 + +DDR IOB DCI Config +
+

DEASSERT RESET

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialize flops in DCI system +
+reserved_VRN_OUT + +5:5 + +20 + +1 + +20 + +Reserved. Do not modify. +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDR IOB DCI Config +
+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

MIO PROGRAMMING

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_00 +	+0XF8000700 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type is LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Select the IO Buffer Type. 000: Reserved 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables Pullup on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1201 + +MIO Pin 0 Control +
+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_01 +	+0XF8000704 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25, Output 10: SRAM/NOR Chip Select 1, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1202 + +MIO Pin 1 Control +
+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_02 +	+0XF8000708 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +202 + +MIO Pin 2 Control +
+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_03 +	+0XF800070C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0, Input/Output 10: NAND WE_B, Output 11: SDIO 1 Card Power, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +202 + +MIO Pin 3 Control +
+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_04 +	+0XF8000710 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1, Input/Output 10: NAND Flash IO Bit 2, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +202 + +MIO Pin 4 Control +
+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_05 +	+0XF8000714 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2, Input/Output 10: NAND Flash IO Bit 0, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +202 + +MIO Pin 5 Control +
+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_06 +	+0XF8000718 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3, Input/Output 10: NAND Flash IO Bit 1, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0), Input/Output others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +202 + +MIO Pin 6 Control +
+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_07 +	+0XF800071C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B, Output 10: NAND Flash CLE_B, Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 (bank 0), Output-only others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +200 + +MIO Pin 7 Control +
+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_08 +	+0XF8000720 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash RD_B, Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 (bank 0), Output-only 001: CAN 1 Tx, Output 010: SRAM/NOR BLS_B, Output 011 to 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +202 + +MIO Pin 8 Control +
+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_09 +	+0XF8000724 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6, Input/Output 10: NAND Flash IO Bit 4, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0), Input/Output 001: CAN 1 Rx, Input 010 to 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1200 + +MIO Pin 9 Control +
+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_10 +	+0XF8000728 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7, Input/Output 10: NAND Flash IO Bit 5, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1200 + +MIO Pin 10 Control +
+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_11 +	+0XF800072C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4, Input/Output 10: NAND Flash IO Bit 6, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1200 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_12 +	+0XF8000730 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait, Input 10: NAND Flash IO Bit 7, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1200 + +MIO Pin 12 Control +
+

Register ( slcr )MIO_PIN_13

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_13 +	+0XF8000734 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3, Input/Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5, Input/Output 10: NAND Flash IO Bit 3, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1200 + +MIO Pin 13 Control +
+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_14 +	+0XF8000738 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy, Input 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 slave select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1200 + +MIO Pin 14 Control +
+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_15 +	+0XF800073C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3f01 + + + +1201 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_16 +	+0XF8000740 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1, Output 10: NAND Flash IO Bit 8, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +2802 + +MIO Pin 16 Control +
+

Register ( slcr )MIO_PIN_17

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_17 +	+0XF8000744 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2, Output 10: NAND Flash IO Bit 9, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110 TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +2802 + +MIO Pin 17 Control +
+

Register ( slcr )MIO_PIN_18

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_18 +	+0XF8000748 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3, Output 10: NAND Flash IO Bit 10, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +2802 + +MIO Pin 18 Control +
+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_19 +	+0XF800074C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4, Output 10: NAND Flash IO Bit 11, Input/Output 111: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +2802 + +MIO Pin 19 Control +
+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_20 +	+0XF8000750 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5, Output 10: NAND Flash IO Bit 12, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +2802 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_21 +	+0XF8000754 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6, Output 10: NAND Flash IO Bit 13, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +2802 + +MIO Pin 21 Control +
+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_22 +	+0XF8000758 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7, Output 10: NAND Flash IO Bit 14, Input/Output 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +803 + +MIO Pin 22 Control +
+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_23 +	+0XF800075C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8, Output 10: NAND Flash IO Bit 15, Input/Output 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +803 + +MIO Pin 23 Control +
+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_24 +	+0XF8000760 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +803 + +MIO Pin 24 Control +
+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_25 +	+0XF8000764 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +803 + +MIO Pin 25 Control +
+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_26 +	+0XF8000768 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +803 + +MIO Pin 26 Control +
+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_27 +	+0XF800076C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +803 + +MIO Pin 27 Control +
+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_28 +	+0XF8000770 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +204 + +MIO Pin 28 Control +
+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_29 +	+0XF8000774 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +205 + +MIO Pin 29 Control +
+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_30 +	+0XF8000778 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +204 + +MIO Pin 30 Control +
+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_31 +	+0XF800077C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +205 + +MIO Pin 31 Control +
+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_32 +	+0XF8000780 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +204 + +MIO Pin 32 Control +
+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_33 +	+0XF8000784 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control, Output +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +204 + +MIO Pin 33 Control +
+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_34 +	+0XF8000788 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +204 + +MIO Pin 34 Control +
+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_35 +	+0XF800078C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +204 + +MIO Pin 35 Control +
+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_36 +	+0XF8000790 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +205 + +MIO Pin 36 Control +
+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_37 +	+0XF8000794 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 2, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Slave Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +204 + +MIO Pin 37 Control +
+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_38 +	+0XF8000798 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23, Output 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +204 + +MIO Pin 38 Control +
+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_39 +	+0XF800079C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control, Input +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24, Output 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +204 + +MIO Pin 39 Control +
+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_40 +	+0XF80007A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 Clock, Input/Output 101: SPI 0 Serial Clock, Input/Output 110: TTC 1 Wave, Output 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +280 + +MIO Pin 40 Control +
+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_41 +	+0XF80007A4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 Command, Input/Output 101: SPI 0 MISO, Input/Output 110: TTC 1 Clock, Input 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +280 + +MIO Pin 41 Control +
+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_42 +	+0XF80007A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop, Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: reserved 100: SDIO 0 IO Bit 0, Input/Output 101: SPI 0 Slave Select 0, Input/Output 110: TTC 0 Wave, Output 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +280 + +MIO Pin 42 Control +
+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_43 +	+0XF80007AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next, Input +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 1, Input/Output 101: SPI 0 Slave Select 1, Output 110: TTC 0 Clock, Input 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +280 + +MIO Pin 43 Control +
+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_44 +	+0XF80007B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: reserved 100: SDIO 0 IO Bit 2, Input/Output 101: SPI 0 Slave Select 2, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +280 + +MIO Pin 44 Control +
+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_45 +	+0XF80007B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: reserved 100: SDIO 0 IO Bit 3, Input/Output 101: SPI 0 MOSI, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +280 + +MIO Pin 45 Control +
+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_46 +	+0XF80007B8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 46 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: PJTAG TDI, Input 100: SDIO 1 IO Bit 0, Input/Output 101: SPI 1 MOSI, Input/Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1221 + +MIO Pin 46 Control +
+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_47 +	+0XF80007BC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 47 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: PJTAG TDO, Output 100: SDIO 1 Command, Input/Output 101: SPI 1 MISO, Input/Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1220 + +MIO Pin 47 Control +
+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_48 +	+0XF80007C0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: PJTAG TCK, Input 100: SDIO 1 Clock, Input/Output 101: SPI 1 Serial Clock, Input/Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +2e0 + +MIO Pin 48 Control +
+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_49 +	+0XF80007C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: PJTAG TMS, Input 100: SDIO 1 IO Bit 1, Input/Output 101: SPI 1 Select 0, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +2e1 + +MIO Pin 49 Control +
+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_50 +	+0XF80007C8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 50 (bank 1), Input/Output 001: CAN 0 Rx, Input 010: I2C 0 Serial Clock, Input/Ouput 011: SWDT Clock, Input 100: SDIO 1 IO Bit 2, Input/Output 101: SPI 1 Slave Select 1, Output 110: reserved 111: UART 0 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1240 + +MIO Pin 50 Control +
+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_51 +	+0XF80007CC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7, Input/Output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 51 (bank 1), Input/Output 001: CAN 0 Tx, Output 010: I2C 0 Serial Data, Input/Output 011: SWDT Reset, Output 100: SDIO 1 IO Bit 3, Input/Output 101: SPI 1 Slave Select 2, Output 110: reserved 111: UART 0 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1240 + +MIO Pin 51 Control +
+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_52 +	+0XF80007D0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1), Input/Output 001: CAN 1 Tx, Output 010: I2C 1 Serial Clock, Input/Output 011: SWDT Clock, Input 100: MDIO 0 Clock, Output 101: MDIO 1 Clock, Output 110: reserved 111: UART 1 TxD, Output +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +280 + +MIO Pin 52 Control +
+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_53 +	+0XF80007D4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control, Output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1), Input/Output 001: CAN 1 Rx, Input 010: I2C 1 Serial Data, Input/Output 011: SWDT Reset, Output 100: MDIO 0 Data, Input/Output 101: MDIO 1 Data, Input/Output 110: reserved 111: UART 1 RxD, Input +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULLUP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +280 + +MIO Pin 53 Control +
+

Register ( slcr )SD0_WP_CD_SEL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SD0_WP_CD_SEL +	+0XF8000830 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SDIO0_WP_SEL + +5:0 + +3f + +f + +f + +SDIO 0 WP Select. Values 53:0 select MIO input (any pin except 7 and 8) Values 63:54 select EMIO input +
+SDIO0_CD_SEL + +21:16 + +3f0000 + +0 + +0 + +SDIO 0 CD Select. Values 53:0 select MIO input (any pin except bits 7 and 8) Values 63:54 select EMIO input +
+SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +f + +SDIO 0 WP CD select +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ +

ps7_peripherals_init_data_3_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +DDRIOB_DATA0 + +	+0XF8000B48 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + +	+0XF8000B4C +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + +	+0XF8000B50 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + +	+0XF8000B54 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 3:2 +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +
+ +Baud_rate_divider_reg0 + +	+0XE0001034 +	+32 +	+RW +	+0x000000 +	+Baud Rate Divider Register +
+ +Baud_rate_gen_reg0 + +	+0XE0001018 +	+32 +	+RW +	+0x000000 +	+Baud Rate Generator Register. +
+ +Control_reg0 + +	+0XE0001000 +	+32 +	+RW +	+0x000000 +	+UART Control Register +
+ +mode_reg0 + +	+0XE0001004 +	+32 +	+RW +	+0x000000 +	+UART Mode Register +
+ +Config_reg + +	+0XE000D000 +	+32 +	+RW +	+0x000000 +	+SPI configuration register +
+ +CTRL + +	+0XF8007000 +	+32 +	+RW +	+0x000000 +	+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +

ps7_peripherals_init_data_3_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

DDR TERM/IBUF_DISABLE_MODE SETTINGS

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA0 +	+0XF8000B48 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 15:0 +
+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA1 +	+0XF8000B4C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +180 + + + +180 + +DDR IOB Config for Data 31:16 +
+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF0 +	+0XF8000B50 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 1:0 +
+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF1 +	+0XF8000B54 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IBUF_DISABLE_MODE + +7:7 + +80 + +1 + +80 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable NOTE: This must be 0 during DRAM init/training and can only be set to 1 after init/training completes. +
+TERM_DISABLE_MODE + +8:8 + +100 + +1 + +100 + +Termination is used during read transactions and may be disabled (automatically by hardware) when there are no reads taking place through the DDR Interface. Disabling termination reduces power consumption. 0: termination always enabled 1: use 'dynamic_dci_ts' to disable termination when not in use NOTE: This bit must be 0 during DRAM init/training. It may be set to 1 after init/training completes. +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +180 + + + +180 + +DDR IOB Config for DQS 3:2 +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

SRAM/NOR SET OPMODE

TRACE CURRENT PORT SIZE

UART REGISTERS

Register ( slcr )Baud_rate_divider_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Baud_rate_divider_reg0 +	+0XE0001034 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate +
+Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +Baud Rate Divider Register +
+

Register ( slcr )Baud_rate_gen_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Baud_rate_gen_reg0 +	+0XE0001018 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CD + +15:0 + +ffff + +3e + +3e + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample +
+Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +3e + +Baud Rate Generator Register. +
+

Register ( slcr )Control_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Control_reg0 +	+0XE0001000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a high level during 12 bit periods. It can be set regardless of the value of STTBRK. +
+STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high. +
+RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has completed. +
+TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter 1: disable transmitter +
+TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0. +
+RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: enable 1: disable, regardless of the value of RXEN +
+RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
+TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded This bit is self clearing once the reset has completed. +
+RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit is self clearing once the reset has completed. +
+Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control Register +
+

Register ( slcr )mode_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+mode_reg0 +	+0XE0001004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback +
+NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
+PAR + +5:3 + +38 + +4 + +20 + +Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
+CHRL + +2:1 + +6 + +0 + +0 + +Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits +
+CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock source is uart_ref_clk 1: clock source is uart_ref_clk/8 +
+mode_reg0@0XE0001004 + +31:0 + +3ff + + + +20 + +UART Mode Register +
+

QSPI REGISTERS

Register ( slcr )Config_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Config_reg +	+0XE000D000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Holdb_dr + +19:19 + +80000 + +1 + +80000 + +If set, Holdb and WPn pins are actively driven by the qspi controller in 1-bit and 2-bit modes . If not set, then external pull up is required on HOLDb and WPn pins . Note that this bit doesn't affect the quad(4-bit) mode as Controller always drives these pins in quad mode. It is highly recommended to set this bit always(irrespective of mode of operation) while using QSPI +
+Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
+

PL POWER ON RESET REGISTERS

Register ( slcr )CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CTRL +	+0XF8007000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This register controls which POR timer the PL will use for power-up. 0 - Use 64k timer 1 - Use 4k timer +
+CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

DIR MODE BANK 0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_0 + +31:0 + +ffffffff + +2880 + +2880 + +Direction mode 0: input 1: output Each bit configures the corresponding pin within the 32-bit bank NOTE: bits[8:7] of bank0 cannot be used as inputs. The DIRM bits can be set to 0, but reading DATA_RO does not reflect the input value. See the GPIO chapter for more information. +
+DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +2880 + +Direction mode (GPIO Bank0, MIO) +
+

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +ff7f + +ff7f0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +80 + +80 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +ff7f0080 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_0 + +31:0 + +ffffffff + +2880 + +2880 + +Output enables 0: disabled 1: enabled Each bit configures the corresponding pin within the 32-bit bank +
+OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +2880 + +Output enable (GPIO Bank0, MIO) +
+

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +ff7f + +ff7f0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +ff7f0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ENET RESET

DIR MODE BANK 0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +800 + +800 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0800 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +800 + +800 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0800 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

I2C RESET

DIR MODE GPIO BANK0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

DIR MODE GPIO BANK1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +2000 + +2000 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff2000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

OUTPUT ENABLE

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +2000 + +2000 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff2000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

+ +

ps7_post_config_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +LVL_SHFTR_EN + +	+0XF8000900 +	+32 +	+RW +	+0x000000 +	+Level Shifters Enable +
+ +FPGA_RST_CTRL + +	+0XF8000240 +	+32 +	+RW +	+0x000000 +	+FPGA Software Reset Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_post_config_3_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

ENABLING LEVEL SHIFTER

Register ( slcr )LVL_SHFTR_EN

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LVL_SHFTR_EN +	+0XF8000900 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+USER_LVL_INP_EN_0 + +3:3 + +8 + +1 + +8 + +Level shifter enable to drive signals from PL to PS +
+USER_LVL_OUT_EN_0 + +2:2 + +4 + +1 + +4 + +Level shifter enable to drive signals from PS to PL +
+USER_LVL_INP_EN_1 + +1:1 + +2 + +1 + +2 + +Level shifter enable to drive signals from PL to PS +
+USER_LVL_OUT_EN_1 + +0:0 + +1 + +1 + +1 + +Level shifter enable to drive signals from PS to PL +
+LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
+

FPGA RESETS TO 0

Register ( slcr )FPGA_RST_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA_RST_CTRL +	+0XF8000240 +	+32 +	+rw +	+0x00000000 +	+-- +

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ +

ps7_debug_3_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +LAR + +	+0XF8898FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +
+ +LAR + +	+0XF8899FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +
+ +LAR + +	+0XF8809FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +

ps7_debug_3_0

+ + + + + + + + + +

CROSS TRIGGER CONFIGURATIONS

UNLOCKING CTI REGISTERS

Register ( slcr )LAR

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8898FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8898FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8899FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8809FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

ENABLING CTI MODULES AND CHANNELS

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

+ +

+ + + + +

ps7_pll_init_data_2_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +ARM_PLL_CFG + +	+0XF8000110 +	+32 +	+RW +	+0x000000 +	+ARM PLL Configuration +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_CLK_CTRL + +	+0XF8000120 +	+32 +	+RW +	+0x000000 +	+CPU Clock Control +
+ +DDR_PLL_CFG + +	+0XF8000114 +	+32 +	+RW +	+0x000000 +	+DDR PLL Configuration +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_CLK_CTRL + +	+0XF8000124 +	+32 +	+RW +	+0x000000 +	+DDR Clock Control +
+ +IO_PLL_CFG + +	+0XF8000118 +	+32 +	+RW +	+0x000000 +	+IO PLL Configuration +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_pll_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CFG +	+0XF8000110 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
+

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
+

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
+

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset. After reset, program the PLLs and ensure that the serviced bit is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +ARM PLL Bypass override control: PLL_BYPASS_QUAL = 0: 0: enabled, not bypassed. 1: bypassed. PLL_BYPASS_QUAL =1: 0: 1: bypass mode regardless of the pin strapping. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
+

Register ( slcr )ARM_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_CLK_CTRL +	+0XF8000120 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the CPU clock: 0x: CPU PLL 10: divided DDR PLL 11: IO PLL +
+DIVISOR + +13:8 + +3f00 + +2 + +200 + +Frequency divisor for the CPU clock source. +
+CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +CPU_6x4x Clock control: 0: disable, 1: enable +
+CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +CPU_3x2x Clock control: 0: disable, 1: enable +
+CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +CPU_2x Clock control: 0: disable, 1: enable +
+CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +CPU_1x Clock control: 0: disable, 1: enable +
+CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CPU Clock Control +
+

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CFG +	+0XF8000114 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
+DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
+

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
+

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
+

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset 1: PLL held in reset Remember that after reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
+

Register ( slcr )DDR_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_CLK_CTRL +	+0XF8000124 +	+32 +	+rw +	+0x00000000 +	+-- +

IO PLL INIT

Register ( slcr )IO_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CFG +	+0XF8000118 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +c + +c0 + +Drive the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control. +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drive the PLL_CP[3:0] input of the PLL to set the PLL charge pump control. +
+LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drive the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before staying locked. +
+IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provide the feedback divisor for the PLL. Note: Before changing this value, the PLL must first be bypassed and then put into powerdown or reset state. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
+

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
+

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
+

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drive the RESET input of the PLL: 0: PLL out of reset. 1: PLL held in reset. Remember that after a reset, program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overide control of the PLL bypass function within the clock controller to force into bypass state: 0: PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1: PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_clock_init_data_2_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +DCI_CLK_CTRL + +	+0XF8000128 +	+32 +	+RW +	+0x000000 +	+DCI clock control +
+ +GEM0_RCLK_CTRL + +	+0XF8000138 +	+32 +	+RW +	+0x000000 +	+GigE 0 Rx Clock Control +
+ +GEM0_CLK_CTRL + +	+0XF8000140 +	+32 +	+RW +	+0x000000 +	+GigE 0 Ref Clock Control +
+ +LQSPI_CLK_CTRL + +	+0XF800014C +	+32 +	+RW +	+0x000000 +	+Quad SPI Ref Clock Control +
+ +SDIO_CLK_CTRL + +	+0XF8000150 +	+32 +	+RW +	+0x000000 +	+SDIO Ref Clock Control +
+ +UART_CLK_CTRL + +	+0XF8000154 +	+32 +	+RW +	+0x000000 +	+UART Ref Clock Control +
+ +CAN_CLK_CTRL + +	+0XF800015C +	+32 +	+RW +	+0x000000 +	+CAN Ref Clock Control +
+ +CAN_MIOCLK_CTRL + +	+0XF8000160 +	+32 +	+RW +	+0x000000 +	+CAN MIO Clock Control +
+ +PCAP_CLK_CTRL + +	+0XF8000168 +	+32 +	+RW +	+0x000000 +	+PCAP Clock Control +
+ +FPGA0_CLK_CTRL + +	+0XF8000170 +	+32 +	+RW +	+0x000000 +	+PL Clock 0 Output control +
+ +FPGA1_CLK_CTRL + +	+0XF8000180 +	+32 +	+RW +	+0x000000 +	+PL Clock 1 Output control +
+ +FPGA2_CLK_CTRL + +	+0XF8000190 +	+32 +	+RW +	+0x000000 +	+PL Clock 2 output control +
+ +FPGA3_CLK_CTRL + +	+0XF80001A0 +	+32 +	+RW +	+0x000000 +	+PL Clock 3 output control +
+ +CLK_621_TRUE + +	+0XF80001C4 +	+32 +	+RW +	+0x000000 +	+CPU Clock Ratio Mode select +
+ +APER_CLK_CTRL + +	+0XF800012C +	+32 +	+RW +	+0x000000 +	+AMBA Peripheral Clock Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_clock_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DCI_CLK_CTRL +	+0XF8000128 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )GEM0_RCLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GEM0_RCLK_CTRL +	+0XF8000138 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Ethernet Controler 0 Rx Clock control 0: disable, 1: enable +
+SRCSEL + +4:4 + +10 + +0 + +0 + +Select the source to generate the Rx clock: 0: MIO Rx clock, 1: EMIO Rx clock +
+GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +GigE 0 Rx Clock Control +
+

Register ( slcr )GEM0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GEM0_CLK_CTRL +	+0XF8000140 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )LQSPI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LQSPI_CLK_CTRL +	+0XF800014C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Quad SPI Controller Reference Clock control 0: disable, 1: enable +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select clock source generate Quad SPI clock: 0x: IO PLL, 10: ARM PLL, 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Divisor for Quad SPI Controller source clock. +
+LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Quad SPI Ref Clock Control +
+

Register ( slcr )SDIO_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SDIO_CLK_CTRL +	+0XF8000150 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )UART_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+UART_CLK_CTRL +	+0XF8000154 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 Reference clock control. 0: disable, 1: enable +
+CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the PLL source to generate the clock. 0x: IO PLL 10: ARM PLL 11: DDR PLL +
+DIVISOR + +13:8 + +3f00 + +14 + +1400 + +Divisor for UART Controller source clock. +
+UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +1402 + +UART Ref Clock Control +
+

Register ( slcr )CAN_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CAN_CLK_CTRL +	+0XF800015C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CAN_MIOCLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CAN_MIOCLK_CTRL +	+0XF8000160 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )PCAP_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PCAP_CLK_CTRL +	+0XF8000168 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active: 0: Clock is disabled 1: Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP Clock Control +
+

Register ( slcr )FPGA0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA0_CLK_CTRL +	+0XF8000170 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )FPGA1_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA1_CLK_CTRL +	+0XF8000180 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 1 Output control +
+

Register ( slcr )FPGA2_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA2_CLK_CTRL +	+0XF8000190 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 2 output control +
+

Register ( slcr )FPGA3_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA3_CLK_CTRL +	+0XF80001A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Select the source used to generate the clock: 0x: Source for generated clock is IO PLL. 10: Source for generated clock is ARM PLL. 11: Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider. +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divide +
+FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +101400 + +PL Clock 3 output control +
+

Register ( slcr )CLK_621_TRUE

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CLK_621_TRUE +	+0XF80001C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Select the CPU clock ration: 0: 4:2:1 1: 6:2:1 +
+CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +CPU Clock Ratio Mode select +
+

Register ( slcr )APER_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+APER_CLK_CTRL +	+0XF800012C +	+32 +	+rw +	+0x00000000 +	+-- +

THIS SHOULD BE BLANK

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_ddr_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +ddrc_ctrl + +	+0XF8006000 +	+32 +	+RW +	+0x000000 +	+DDRC Control +
+ +Two_rank_cfg + +	+0XF8006004 +	+32 +	+RW +	+0x000000 +	+Two Rank Configuration +
+ +HPR_reg + +	+0XF8006008 +	+32 +	+RW +	+0x000000 +	+HPR Queue control +
+ +LPR_reg + +	+0XF800600C +	+32 +	+RW +	+0x000000 +	+LPR Queue control +
+ +WR_reg + +	+0XF8006010 +	+32 +	+RW +	+0x000000 +	+WR Queue control +
+ +DRAM_param_reg0 + +	+0XF8006014 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 0 +
+ +DRAM_param_reg1 + +	+0XF8006018 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 1 +
+ +DRAM_param_reg2 + +	+0XF800601C +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 2 +
+ +DRAM_param_reg3 + +	+0XF8006020 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 3 +
+ +DRAM_param_reg4 + +	+0XF8006024 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters 4 +
+ +DRAM_init_param + +	+0XF8006028 +	+32 +	+RW +	+0x000000 +	+DRAM Initialization Parameters +
+ +DRAM_EMR_reg + +	+0XF800602C +	+32 +	+RW +	+0x000000 +	+DRAM EMR2, EMR3 access +
+ +DRAM_EMR_MR_reg + +	+0XF8006030 +	+32 +	+RW +	+0x000000 +	+DRAM EMR, MR access +
+ +DRAM_burst8_rdwr + +	+0XF8006034 +	+32 +	+RW +	+0x000000 +	+DRAM Burst 8 read/write +
+ +DRAM_disable_DQ + +	+0XF8006038 +	+32 +	+RW +	+0x000000 +	+DRAM Disable DQ +
+ +DRAM_addr_map_bank + +	+0XF800603C +	+32 +	+RW +	+0x000000 +	+Row/Column address bits +
+ +DRAM_addr_map_col + +	+0XF8006040 +	+32 +	+RW +	+0x000000 +	+Column address bits +
+ +DRAM_addr_map_row + +	+0XF8006044 +	+32 +	+RW +	+0x000000 +	+Select DRAM row address bits +
+ +DRAM_ODT_reg + +	+0XF8006048 +	+32 +	+RW +	+0x000000 +	+DRAM ODT control +
+ +phy_cmd_timeout_rddata_cpt + +	+0XF8006050 +	+32 +	+RW +	+0x000000 +	+PHY command time out and read data capture FIFO +
+ +DLL_calib + +	+0XF8006058 +	+32 +	+RW +	+0x000000 +	+DLL calibration +
+ +ODT_delay_hold + +	+0XF800605C +	+32 +	+RW +	+0x000000 +	+ODT delay and ODT hold +
+ +ctrl_reg1 + +	+0XF8006060 +	+32 +	+RW +	+0x000000 +	+Controller 1 +
+ +ctrl_reg2 + +	+0XF8006064 +	+32 +	+RW +	+0x000000 +	+Controller 2 +
+ +ctrl_reg3 + +	+0XF8006068 +	+32 +	+RW +	+0x000000 +	+Controller 3 +
+ +ctrl_reg4 + +	+0XF800606C +	+32 +	+RW +	+0x000000 +	+Controller 4 +
+ +ctrl_reg5 + +	+0XF8006078 +	+32 +	+RW +	+0x000000 +	+Controller register 5 +
+ +ctrl_reg6 + +	+0XF800607C +	+32 +	+RW +	+0x000000 +	+Controller register 6 +
+ +CHE_REFRESH_TIMER01 + +	+0XF80060A0 +	+32 +	+RW +	+0x000000 +	+CHE_REFRESH_TIMER01 +
+ +CHE_T_ZQ + +	+0XF80060A4 +	+32 +	+RW +	+0x000000 +	+ZQ parameters +
+ +CHE_T_ZQ_Short_Interval_Reg + +	+0XF80060A8 +	+32 +	+RW +	+0x000000 +	+Misc parameters +
+ +deep_pwrdwn_reg + +	+0XF80060AC +	+32 +	+RW +	+0x000000 +	+Deep powerdown (LPDDR2) +
+ +reg_2c + +	+0XF80060B0 +	+32 +	+RW +	+0x000000 +	+Training control +
+ +reg_2d + +	+0XF80060B4 +	+32 +	+RW +	+0x000000 +	+Misc Debug +
+ +dfi_timing + +	+0XF80060B8 +	+32 +	+RW +	+0x000000 +	+DFI timing +
+ +CHE_ECC_CONTROL_REG_OFFSET + +	+0XF80060C4 +	+32 +	+RW +	+0x000000 +	+ECC error clear +
+ +CHE_ECC_CONTROL_REG_OFFSET + +	+0XF80060C4 +	+32 +	+RW +	+0x000000 +	+ECC error clear +
+ +CHE_CORR_ECC_LOG_REG_OFFSET + +	+0XF80060C8 +	+32 +	+RW +	+0x000000 +	+ECC error correction +
+ +CHE_UNCORR_ECC_LOG_REG_OFFSET + +	+0XF80060DC +	+32 +	+RW +	+0x000000 +	+ECC unrecoverable error status +
+ +CHE_ECC_STATS_REG_OFFSET + +	+0XF80060F0 +	+32 +	+RW +	+0x000000 +	+ECC error count +
+ +ECC_scrub + +	+0XF80060F4 +	+32 +	+RW +	+0x000000 +	+ECC mode/scrub +
+ +phy_rcvr_enable + +	+0XF8006114 +	+32 +	+RW +	+0x000000 +	+Phy receiver enable register +
+ +PHY_Config0 + +	+0XF8006118 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config1 + +	+0XF800611C +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 1. +
+ +PHY_Config2 + +	+0XF8006120 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 2. +
+ +PHY_Config3 + +	+0XF8006124 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 3. +
+ +phy_init_ratio0 + +	+0XF800612C +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio1 + +	+0XF8006130 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 1. +
+ +phy_init_ratio2 + +	+0XF8006134 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 2. +
+ +phy_init_ratio3 + +	+0XF8006138 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 3. +
+ +phy_rd_dqs_cfg0 + +	+0XF8006140 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg1 + +	+0XF8006144 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 1. +
+ +phy_rd_dqs_cfg2 + +	+0XF8006148 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 2. +
+ +phy_rd_dqs_cfg3 + +	+0XF800614C +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 3. +
+ +phy_wr_dqs_cfg0 + +	+0XF8006154 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg1 + +	+0XF8006158 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 1. +
+ +phy_wr_dqs_cfg2 + +	+0XF800615C +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 2. +
+ +phy_wr_dqs_cfg3 + +	+0XF8006160 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 3. +
+ +phy_we_cfg0 + +	+0XF8006168 +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 0. +
+ +phy_we_cfg1 + +	+0XF800616C +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 1. +
+ +phy_we_cfg2 + +	+0XF8006170 +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 2. +
+ +phy_we_cfg3 + +	+0XF8006174 +	+32 +	+RW +	+0x000000 +	+PHY FIFO write enable configuration for data slice 3. +
+ +wr_data_slv0 + +	+0XF800617C +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 0. +
+ +wr_data_slv1 + +	+0XF8006180 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 1. +
+ +wr_data_slv2 + +	+0XF8006184 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 2. +
+ +wr_data_slv3 + +	+0XF8006188 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio config for data slice 3. +
+ +reg_64 + +	+0XF8006190 +	+32 +	+RW +	+0x000000 +	+Training control 2 +
+ +reg_65 + +	+0XF8006194 +	+32 +	+RW +	+0x000000 +	+Training control 3 +
+ +page_mask + +	+0XF8006204 +	+32 +	+RW +	+0x000000 +	+Page mask +
+ +axi_priority_wr_port0 + +	+0XF8006208 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port1 + +	+0XF800620C +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 1. +
+ +axi_priority_wr_port2 + +	+0XF8006210 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 2. +
+ +axi_priority_wr_port3 + +	+0XF8006214 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 3. +
+ +axi_priority_rd_port0 + +	+0XF8006218 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port1 + +	+0XF800621C +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 1. +
+ +axi_priority_rd_port2 + +	+0XF8006220 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 2. +
+ +axi_priority_rd_port3 + +	+0XF8006224 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 3. +
+ +lpddr_ctrl0 + +	+0XF80062A8 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 0 +
+ +lpddr_ctrl1 + +	+0XF80062AC +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 1 +
+ +lpddr_ctrl2 + +	+0XF80062B0 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 2 +
+ +lpddr_ctrl3 + +	+0XF80062B4 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 3 +
+ +ddrc_ctrl + +	+0XF8006000 +	+32 +	+RW +	+0x000000 +	+DDRC Control +

ps7_ddr_init_data_2_0

+ + + + + + + + + +

DDR INITIALIZATION

LOCK DDR

Register ( slcr )ddrc_ctrl

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ddrc_ctrl +	+0XF8006000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control +
+

Register ( slcr )Two_rank_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Two_rank_cfg +	+0XF8006004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM related. Default value is set for DDR3. Dynamic Bit Field. +
+reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Rank configuration: 01: One Rank of DDR 11: Two Ranks of DDR Others: reserved +
+reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
+reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +Block read/write scheduling cycle count when Write requires changing ODT settings 00: 1 cycle 01: 2 cycles 10: 3 cycles others: reserved +
+reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0: schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1: schedule 2 cycle gap for the same +
+reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
+reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map to Open Bank mode +
+reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1: Set the address map for 4 Bank RAMs +
+Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two Rank Configuration +
+

Register ( slcr )HPR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+HPR_reg +	+0XF8006008 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )LPR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LPR_reg +	+0XF800600C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )WR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+WR_reg +	+0XF8006010 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DRAM_param_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg0 +	+0XF8006014 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DRAM_param_reg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg1 +	+0XF8006018 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DRAM_param_reg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg2 +	+0XF800601C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2 and DDR3: WL -1 LPDDR2: WL Where WL: Write Latency of DRAM DRAM related. +
+reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. DDR2 and DDR3: RL + BL/2 + 2 - WL LPDDR2: RL + BL/2 + RU (tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
+reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. DDR2 and DDR3: WL + tWTR + BL/2 LPDDR2: WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL: Write latency, BL: burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR: internal WRITE to READ command delay. This comes directly from the DRAM specs. +
+reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM related. +
+reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
+reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2: AL + BL/2 + max(tRTP, 2) - 2 DDR3: AL + max (tRTP, 4) LPDDR2: BL/2 + tRTP - 1 AL: Additive Latency; BL: DRAM Burst Length; tRTP: value from spec. DRAM related. +
+reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency. DRAM Related. +
+DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters 2 +
+

Register ( slcr )DRAM_param_reg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg3 +	+0XF8006020 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1. DRAM related. +
+reg_ddrc_t_rrd + +7:5 + +e0 + +4 + +80 + +tRRD - Minimum time between activates from bank A to bank B. (spec: 10ns or less) DRAM RELATED +
+reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
+reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
+reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. Dynamic Bit Field. +
+reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1: sdram device 0: non-sdram device +
+reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +0: DDR2 or DDR3 device. 1: LPDDR2 device. +
+reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +DDR2 and DDR3: not used. LPDDR2: 0: stop_clk will never be asserted. 1: enable the assertion of stop_clk to the PHY whenever a clock is not required +
+reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Non-LPDDR2: not used. DDR2 and DDR3: Set to Read Latency, RL. Time from Read command to Read data on DRAM interface. It is used to calculate when DRAM clock may be stopped. Unit: DDR clock. +
+reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
+reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1: disable the pad power down feature 0: Enable the pad power down feature. +
+reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
+DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +27287290 + +DRAM Parameters 3 +
+

Register ( slcr )DRAM_param_reg4

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg4 +	+0XF8006024 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1: DDRC will use 2T timing 0: DDRC will use 1T timing +
+reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1: Bank selector prefers writes over reads +
+reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
+reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and "ddrc_reg_mr_wr_busy" is detected low. +
+reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +DDR2 and DDR3: Mode register address. LPDDR2: not used. 00: MR0 01: MR1 10: MR2 11: MR3 +
+reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +DDR2 and DDR3: Mode register write data. LPDDR2: The 16 bits are interpreted for reads and writes: Reads: MR Addr[7:0], Don't Care[7:0]. Writes: MR Addf[7:0], MR Data[7:0]. +
+ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 0: Indicates that the core can initiate a mode register write / read operation. 1: Indicates that mode register write / read operation is in progress. +
+reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 0: write 1: read +
+reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 0 by default. This bit will be cleared (0), whenever a Mode Register Read command is issued. This bit will be set to 1, when the Mode Register Read Data is written to register 0xA9. +
+DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters 4 +
+

Register ( slcr )DRAM_init_param

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_init_param +	+0XF8006028 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DRAM_EMR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_EMR_reg +	+0XF800602C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +DDR2 and DDR3: Value written into the DRAM EMR2 register. LPDDR2: Value written into the DRAM MR3 register. +
+reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +DDR2 and DDR3: Value written into the DRAM EMR3 register. LPDDR2: not used. +
+DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access +
+

Register ( slcr )DRAM_EMR_MR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_EMR_MR_reg +	+0XF8006030 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +DDR2 and DDR3: Value written into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. LPDDR2: Value written into the DRAM MR1 register +
+reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +DDR2 and DDR3: Value written into the DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. LPDDR2: Value written into the DRAM MR2 register. +
+DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access +
+

Register ( slcr )DRAM_burst8_rdwr

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_burst8_rdwr +	+0XF8006034 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DRAM_disable_DQ

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_disable_DQ +	+0XF8006038 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Read Transaction Priority disable. 0: read transactions forced to low priority (turns off Bypass). 1: HPR reads allowed if enabled in the AXI priority read registers. +
+reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. Dynamic Bit Field. +
+reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
+DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ +
+

Register ( slcr )DRAM_addr_map_bank

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_bank +	+0XF800603C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14. Internal Base: 5. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
+reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Row/Column address bits +
+

Register ( slcr )DRAM_addr_map_col

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_col +	+0XF8006040 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Column address bits +
+

Register ( slcr )DRAM_addr_map_row

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_row +	+0XF8006044 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
+reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
+reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
+reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
+reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
+DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Select DRAM row address bits +
+

Register ( slcr )DRAM_ODT_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_ODT_reg +	+0XF8006048 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODTs must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during reads to rank 0. +
+reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2]: If 1 then local ODT is enabled during writes to rank 0. +
+reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
+reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
+reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
+reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
+reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
+reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
+reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
+DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT control +
+

Register ( slcr )phy_cmd_timeout_rddata_cpt

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_cmd_timeout_rddata_cpt +	+0XF8006050 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
+reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
+reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
+reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
+reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
+reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1: stall clock, for DLL aging control +
+reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO +
+

Register ( slcr )DLL_calib

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DLL_calib +	+0XF8006058 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dll_calib_to_min_x1024 + +7:0 + +ff + +1 + +1 + +Unused in DFI Controller. +
+reg_ddrc_dll_calib_to_max_x1024 + +15:8 + +ff00 + +1 + +100 + +Unused in DFI Controller. +
+reg_ddrc_dis_dll_calib + +16:16 + +10000 + +0 + +0 + +When 1, disable dll_calib generated by the controller. The core should issue the dll_calib signal using co_gs_dll_calib input. This input is changeable on the fly. When 0, controller will issue dll_calib periodically +
+DLL_calib@0XF8006058 + +31:0 + +1ffff + + + +101 + +DLL calibration +
+

Register ( slcr )ODT_delay_hold

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ODT_delay_hold +	+0XF800605C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )ctrl_reg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg1 +	+0XF8006060 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
+reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
+reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
+reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. Dynamic Bit Field. +
+reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +Disable Write Combine: 0: enable 1: disable +
+reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to 0, auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
+reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. Dynamic Bit Field. +
+ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller 1 +
+

Register ( slcr )ctrl_reg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg2 +	+0XF8006064 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )ctrl_reg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg3 +	+0XF8006068 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )ctrl_reg4

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg4 +	+0XF800606C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )ctrl_reg5

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg5 +	+0XF8006078 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_ctrl_delay + +3:0 + +f + +1 + +1 + +Specifies the number of DFI clock cycles after an assertion or deassertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_disable + +7:4 + +f0 + +1 + +10 + +Specifies the number of DFI clock cycles from the assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_dfi_t_dram_clk_enable + +11:8 + +f00 + +1 + +100 + +Specifies the number of DFI clock cycles from the de-assertion of the ddrc_dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and the memory clock are not phase aligned, this timing parameter should be rounded up to the next integer value. +
+reg_ddrc_t_cksre + +15:12 + +f000 + +6 + +6000 + +This is the time after Self Refresh Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRE +
+reg_ddrc_t_cksrx + +19:16 + +f0000 + +6 + +60000 + +This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: LPDDR2: 2 DDR2: 1 DDR3: tCKSRX +
+reg_ddrc_t_ckesr + +25:20 + +3f00000 + +4 + +400000 + +Minimum CKE low width for Self Refresh entry to exit Timing in memory clock cycles. Recommended settings: LPDDR2: tCKESR DDR2: tCKE DDR3: tCKE+1 +
+ctrl_reg5@0XF8006078 + +31:0 + +3ffffff + + + +466111 + +Controller register 5 +
+

Register ( slcr )ctrl_reg6

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg6 +	+0XF800607C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ckpde + +3:0 + +f + +2 + +2 + +This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckpdx + +7:4 + +f0 + +2 + +20 + +This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpde + +11:8 + +f00 + +2 + +200 + +This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckdpdx + +15:12 + +f000 + +2 + +2000 + +This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended setting for LPDDR2: 2. +
+reg_ddrc_t_ckcsx + +19:16 + +f0000 + +3 + +30000 + +This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before next command after Clock Stop Exit. Recommended setting for LPDDR2: tXP + 2. +
+ctrl_reg6@0XF800607C + +31:0 + +fffff + + + +32222 + +Controller register 6 +
+

Register ( slcr )CHE_REFRESH_TIMER01

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_REFRESH_TIMER01 +	+0XF80060A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+refresh_timer0_start_value_x32 + +11:0 + +fff + +0 + +0 + +Refresh Timer for Rank 1. Unit: in multiples of 32 clocks. (Only present in multi-rank configurations). FOR PERFORMANCE ONLY. +
+refresh_timer1_start_value_x32 + +23:12 + +fff000 + +8 + +8000 + +Refresh Timer for Rank 0. (Only present in multi-rank configurations). Unit: in multiples of 32 clocks. FOR PERFORMANCE ONLY. +
+CHE_REFRESH_TIMER01@0XF80060A0 + +31:0 + +ffffff + + + +8000 + +CHE_REFRESH_TIMER01 +
+

Register ( slcr )CHE_T_ZQ

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_T_ZQ +	+0XF80060A4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
+reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
+reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles. +
+reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles. +
+CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters +
+

Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_T_ZQ_Short_Interval_Reg +	+0XF80060A8 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )deep_pwrdwn_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+deep_pwrdwn_reg +	+0XF80060AC +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )reg_2c

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_2c +	+0XF80060B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
+ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +DDR2: not applicable. LPDDR2 and DDR3: When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. +
+reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +0: Write leveling disabled. 1: Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +0: Read DQS gate leveling is disabled. 1: Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs +
+reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +DDR2: not applicable. LPDDR2 and DDR3: 0: 1: Read Data Eye training mode has been enabled as part of init sequence. +
+reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control +
+

Register ( slcr )reg_2d

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_2d +	+0XF80060B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
+reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1: Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0: Not supported. +
+reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
+reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug +
+

Register ( slcr )dfi_timing

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+dfi_timing +	+0XF80060B8 +	+32 +	+rw +	+0x00000000 +	+-- +

RESET ECC ERROR

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_CONTROL_REG_OFFSET +	+0XF80060C4 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_CONTROL_REG_OFFSET +	+0XF80060C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear +
+

Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_CORR_ECC_LOG_REG_OFFSET +	+0XF80060C8 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_UNCORR_ECC_LOG_REG_OFFSET +	+0XF80060DC +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CHE_ECC_STATS_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_STATS_REG_OFFSET +	+0XF80060F0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
+STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a 1 is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count +
+

Register ( slcr )ECC_scrub

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ECC_scrub +	+0XF80060F4 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )phy_rcvr_enable

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rcvr_enable +	+0XF8006114 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )PHY_Config0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config0 +	+0XF8006118 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config0@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config1 +	+0XF800611C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config1@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 1. +
+

Register ( slcr )PHY_Config2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config2 +	+0XF8006120 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config2@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 2. +
+

Register ( slcr )PHY_Config3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config3 +	+0XF8006124 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 0: read data responses are ignored. 1: data slice is valid. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +reserved +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +reserved +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +reserved +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Transmitter for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 0: disable 1: This Slice behaves as Receiver for board loopback. This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 10. 0: PRBS pattern without any shift. 1: PRBS pattern shifted early by 1 bit. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 0: No effect 1: sticky error flag is cleared +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config3@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 3. +
+

Register ( slcr )phy_init_ratio0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio0 +	+0XF800612C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +1d + +1d + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +f2 + +3c800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio0@0XF800612C + +31:0 + +fffff + + + +3c81d + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_init_ratio1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio1 +	+0XF8006130 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +12 + +12 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +d8 + +36000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio1@0XF8006130 + +31:0 + +fffff + + + +36012 + +PHY init ratio register for data slice 1. +
+

Register ( slcr )phy_init_ratio2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio2 +	+0XF8006134 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +c + +c + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +de + +37800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio2@0XF8006134 + +31:0 + +fffff + + + +3780c + +PHY init ratio register for data slice 2. +
+

Register ( slcr )phy_init_ratio3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio3 +	+0XF8006138 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +21 + +21 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +ee + +3b800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio3@0XF8006138 + +31:0 + +fffff + + + +3b821 + +PHY init ratio register for data slice 3. +
+

Register ( slcr )phy_rd_dqs_cfg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg0 +	+0XF8006140 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg0@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg1 +	+0XF8006144 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg1@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 1. +
+

Register ( slcr )phy_rd_dqs_cfg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg2 +	+0XF8006148 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg2@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 2. +
+

Register ( slcr )phy_rd_dqs_cfg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg3 +	+0XF800614C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg3@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 3. +
+

Register ( slcr )phy_wr_dqs_cfg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg0 +	+0XF8006154 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +9d + +9d + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg0@0XF8006154 + +31:0 + +fffff + + + +9d + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg1 +	+0XF8006158 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +92 + +92 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg1@0XF8006158 + +31:0 + +fffff + + + +92 + +PHY write DQS configuration register for data slice 1. +
+

Register ( slcr )phy_wr_dqs_cfg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg2 +	+0XF800615C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +8c + +8c + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg2@0XF800615C + +31:0 + +fffff + + + +8c + +PHY write DQS configuration register for data slice 2. +
+

Register ( slcr )phy_wr_dqs_cfg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg3 +	+0XF8006160 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +a1 + +a1 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg3@0XF8006160 + +31:0 + +fffff + + + +a1 + +PHY write DQS configuration register for data slice 3. +
+

Register ( slcr )phy_we_cfg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg0 +	+0XF8006168 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +147 + +147 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg0@0XF8006168 + +31:0 + +1fffff + + + +147 + +PHY FIFO write enable configuration for data slice 0. +
+

Register ( slcr )phy_we_cfg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg1 +	+0XF800616C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +12d + +12d + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg1@0XF800616C + +31:0 + +1fffff + + + +12d + +PHY FIFO write enable configuration for data slice 1. +
+

Register ( slcr )phy_we_cfg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg2 +	+0XF8006170 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +133 + +133 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg2@0XF8006170 + +31:0 + +1fffff + + + +133 + +PHY FIFO write enable configuration for data slice 2. +
+

Register ( slcr )phy_we_cfg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg3 +	+0XF8006174 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +143 + +143 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg3@0XF8006174 + +31:0 + +1fffff + + + +143 + +PHY FIFO write enable configuration for data slice 3. +
+

Register ( slcr )wr_data_slv0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv0 +	+0XF800617C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +dd + +dd + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv0@0XF800617C + +31:0 + +fffff + + + +dd + +PHY write data slave ratio config for data slice 0. +
+

Register ( slcr )wr_data_slv1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv1 +	+0XF8006180 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +d2 + +d2 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv1@0XF8006180 + +31:0 + +fffff + + + +d2 + +PHY write data slave ratio config for data slice 1. +
+

Register ( slcr )wr_data_slv2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv2 +	+0XF8006184 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +cc + +cc + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv2@0XF8006184 + +31:0 + +fffff + + + +cc + +PHY write data slave ratio config for data slice 2. +
+

Register ( slcr )wr_data_slv3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv3 +	+0XF8006188 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +e1 + +e1 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +0: 1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv3@0XF8006188 + +31:0 + +fffff + + + +e1 + +PHY write data slave ratio config for data slice 3. +
+

Register ( slcr )reg_64

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_64 +	+0XF8006190 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
+reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
+reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +0: run scan test at slow clock speed but with high coverage 1: run scan test at full clock speed but with less coverage During normal function mode, this port must be set 0. +
+reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
+reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
+reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 00: constant pattern (0 repeated on each DQ bit) 01: low freq pattern (00001111 repeated on each DQ bit) 10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested 11: reserved +
+reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
+reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +0: (default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) 1: assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) +
+reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0: Select algorithm # 1'b1: Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
+reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
+reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 0: Each Rank uses its own delay 1: Rank 0 delays are used for all ranks +
+reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +0: DDR2 or DDR3. 1: LPDDR2. +
+reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
+reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1: enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
+reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control 2 +
+

Register ( slcr )reg_65

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_65 +	+0XF8006194 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
+reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
+reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
+reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
+reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
+reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
+reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control 3 +
+

Register ( slcr )page_mask

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+page_mask +	+0XF8006204 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )axi_priority_wr_port0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port0 +	+0XF8006208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port0@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port1 +	+0XF800620C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port1@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 1. +
+

Register ( slcr )axi_priority_wr_port2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port2 +	+0XF8006210 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port2@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 2. +
+

Register ( slcr )axi_priority_wr_port3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port3 +	+0XF8006214 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port3@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 3. +
+

Register ( slcr )axi_priority_rd_port0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port0 +	+0XF8006218 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port0@0XF8006218 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )axi_priority_rd_port1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port1 +	+0XF800621C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port1@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 1. +
+

Register ( slcr )axi_priority_rd_port2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port2 +	+0XF8006220 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port2@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 2. +
+

Register ( slcr )axi_priority_rd_port3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port3 +	+0XF8006224 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port3@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 3. +
+

Register ( slcr )lpddr_ctrl0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl0 +	+0XF80062A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +0: DDR2 or DDR3 in use. 1: LPDDR2 in Use. +
+reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +0:All bank refresh Per bank refresh allows traffic to flow to other banks. 1:Per bank refresh Per bank refresh is not supported on all LPDDR2 devices. +
+reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. +
+reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
+lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 +
+

Register ( slcr )lpddr_ctrl1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl1 +	+0XF80062AC +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )lpddr_ctrl2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl2 +	+0XF80062B0 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )lpddr_ctrl3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl3 +	+0XF80062B4 +	+32 +	+rw +	+0x00000000 +	+-- +

POLL ON DCI STATUS

Register ( slcr )DDRIOB_DCI_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_STATUS +	+0XF8000B74 +	+32 +	+rw +	+0x00000000 +	+-- +

UNLOCK DDR

Register ( slcr )ddrc_ctrl

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ddrc_ctrl +	+0XF8006000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. Update during normal operation. 0: Resets the controller 1: Takes the controller out of reset. Dynamic Bit Field. Note: Software changes DRAM controller register values only when the controller is in the reset state, except for bit fields that can be dymanically updated. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. Update during normal operation. Enable the controller to powerdown after it becomes idle. Dynamic Bit Field. 0: disable 1: enable +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00: 32-bit 01: 16-bit 1x: reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0: single refresh 1: burst-of-2 ... 7: burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0: Do not disable bypass path for high priority read page hits. 1: disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0: Do not disable bypass path for high priority read activates. 1: disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0: do not disable auto-refresh. 1: disable auto-refresh. Dynamic Bit Field. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control +
+

CHECK DDR STATUS

Register ( slcr )mode_sts_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+mode_sts_reg +	+0XF8006054 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0: DDRC Init 1: Normal operation 2: Power-down mode 3: Self-refresh mode 4 and above: deep power down mode (LPDDR2 only) +
+mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
+

+ +

ps7_mio_init_data_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +GPIOB_CTRL + +	+0XF8000B00 +	+32 +	+RW +	+0x000000 +	+PS IO Buffer Control +
+ +DDRIOB_ADDR0 + +	+0XF8000B40 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Address 0 +
+ +DDRIOB_ADDR1 + +	+0XF8000B44 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Address 1 +
+ +DDRIOB_DATA0 + +	+0XF8000B48 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + +	+0XF8000B4C +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + +	+0XF8000B50 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + +	+0XF8000B54 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 3:2 +
+ +DDRIOB_CLOCK + +	+0XF8000B58 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Clock Output +
+ +DDRIOB_DRIVE_SLEW_ADDR + +	+0XF8000B5C +	+32 +	+RW +	+0x000000 +	+DDR IOB Slew for Address +
+ +DDRIOB_DRIVE_SLEW_DATA + +	+0XF8000B60 +	+32 +	+RW +	+0x000000 +	+DDR IOB Slew for Data +
+ +DDRIOB_DRIVE_SLEW_DIFF + +	+0XF8000B64 +	+32 +	+RW +	+0x000000 +	+DDR IOB Slew for Diff +
+ +DDRIOB_DRIVE_SLEW_CLOCK + +	+0XF8000B68 +	+32 +	+RW +	+0x000000 +	+DDR IOB Slew for Clock +
+ +DDRIOB_DDR_CTRL + +	+0XF8000B6C +	+32 +	+RW +	+0x000000 +	+DDR IOB Buffer Control +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDRIOB DCI configuration +
+ +MIO_PIN_00 + +	+0XF8000700 +	+32 +	+RW +	+0x000000 +	+MIO Pin 0 Control +
+ +MIO_PIN_01 + +	+0XF8000704 +	+32 +	+RW +	+0x000000 +	+MIO Pin 1 Control +
+ +MIO_PIN_02 + +	+0XF8000708 +	+32 +	+RW +	+0x000000 +	+MIO Pin 2 Control +
+ +MIO_PIN_03 + +	+0XF800070C +	+32 +	+RW +	+0x000000 +	+MIO Pin 3 Control +
+ +MIO_PIN_04 + +	+0XF8000710 +	+32 +	+RW +	+0x000000 +	+MIO Pin 4 Control +
+ +MIO_PIN_05 + +	+0XF8000714 +	+32 +	+RW +	+0x000000 +	+MIO Pin 5 Control +
+ +MIO_PIN_06 + +	+0XF8000718 +	+32 +	+RW +	+0x000000 +	+MIO Pin 6 Control +
+ +MIO_PIN_07 + +	+0XF800071C +	+32 +	+RW +	+0x000000 +	+MIO Pin 7 Control +
+ +MIO_PIN_08 + +	+0XF8000720 +	+32 +	+RW +	+0x000000 +	+MIO Pin 8 Control +
+ +MIO_PIN_09 + +	+0XF8000724 +	+32 +	+RW +	+0x000000 +	+MIO Pin 9 Control +
+ +MIO_PIN_10 + +	+0XF8000728 +	+32 +	+RW +	+0x000000 +	+MIO Pin 10 Control +
+ +MIO_PIN_11 + +	+0XF800072C +	+32 +	+RW +	+0x000000 +	+MIO Pin 11 Control +
+ +MIO_PIN_12 + +	+0XF8000730 +	+32 +	+RW +	+0x000000 +	+MIO Pin 12 Control +
+ +MIO_PIN_13 + +	+0XF8000734 +	+32 +	+RW +	+0x000000 +	+MIO Pin 13 Control +
+ +MIO_PIN_14 + +	+0XF8000738 +	+32 +	+RW +	+0x000000 +	+MIO Pin 14 Control +
+ +MIO_PIN_15 + +	+0XF800073C +	+32 +	+RW +	+0x000000 +	+MIO Pin 15 Control +
+ +MIO_PIN_16 + +	+0XF8000740 +	+32 +	+RW +	+0x000000 +	+MIO Pin 16 Control +
+ +MIO_PIN_17 + +	+0XF8000744 +	+32 +	+RW +	+0x000000 +	+MIO Pin 17 Control +
+ +MIO_PIN_18 + +	+0XF8000748 +	+32 +	+RW +	+0x000000 +	+MIO Pin 18 Control +
+ +MIO_PIN_19 + +	+0XF800074C +	+32 +	+RW +	+0x000000 +	+MIO Pin 19 Control +
+ +MIO_PIN_20 + +	+0XF8000750 +	+32 +	+RW +	+0x000000 +	+MIO Pin 20 Control +
+ +MIO_PIN_21 + +	+0XF8000754 +	+32 +	+RW +	+0x000000 +	+MIO Pin 21 Control +
+ +MIO_PIN_22 + +	+0XF8000758 +	+32 +	+RW +	+0x000000 +	+MIO Pin 22 Control +
+ +MIO_PIN_23 + +	+0XF800075C +	+32 +	+RW +	+0x000000 +	+MIO Pin 23 Control +
+ +MIO_PIN_24 + +	+0XF8000760 +	+32 +	+RW +	+0x000000 +	+MIO Pin 24 Control +
+ +MIO_PIN_25 + +	+0XF8000764 +	+32 +	+RW +	+0x000000 +	+MIO Pin 25 Control +
+ +MIO_PIN_26 + +	+0XF8000768 +	+32 +	+RW +	+0x000000 +	+MIO Pin 26 Control +
+ +MIO_PIN_27 + +	+0XF800076C +	+32 +	+RW +	+0x000000 +	+MIO Pin 27 Control +
+ +MIO_PIN_28 + +	+0XF8000770 +	+32 +	+RW +	+0x000000 +	+MIO Pin 28 Control +
+ +MIO_PIN_29 + +	+0XF8000774 +	+32 +	+RW +	+0x000000 +	+MIO Pin 29 Control +
+ +MIO_PIN_30 + +	+0XF8000778 +	+32 +	+RW +	+0x000000 +	+MIO Pin 30 Control +
+ +MIO_PIN_31 + +	+0XF800077C +	+32 +	+RW +	+0x000000 +	+MIO Pin 31 Control +
+ +MIO_PIN_32 + +	+0XF8000780 +	+32 +	+RW +	+0x000000 +	+MIO Pin 32 Control +
+ +MIO_PIN_33 + +	+0XF8000784 +	+32 +	+RW +	+0x000000 +	+MIO Pin 33 Control +
+ +MIO_PIN_34 + +	+0XF8000788 +	+32 +	+RW +	+0x000000 +	+MIO Pin 34 Control +
+ +MIO_PIN_35 + +	+0XF800078C +	+32 +	+RW +	+0x000000 +	+MIO Pin 35 Control +
+ +MIO_PIN_36 + +	+0XF8000790 +	+32 +	+RW +	+0x000000 +	+MIO Pin 36 Control +
+ +MIO_PIN_37 + +	+0XF8000794 +	+32 +	+RW +	+0x000000 +	+MIO Pin 37 Control +
+ +MIO_PIN_38 + +	+0XF8000798 +	+32 +	+RW +	+0x000000 +	+MIO Pin 38 Control +
+ +MIO_PIN_39 + +	+0XF800079C +	+32 +	+RW +	+0x000000 +	+MIO Pin 39 Control +
+ +MIO_PIN_40 + +	+0XF80007A0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 40 Control +
+ +MIO_PIN_41 + +	+0XF80007A4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 41 Control +
+ +MIO_PIN_42 + +	+0XF80007A8 +	+32 +	+RW +	+0x000000 +	+MIO Pin 42 Control +
+ +MIO_PIN_43 + +	+0XF80007AC +	+32 +	+RW +	+0x000000 +	+MIO Pin 43 Control +
+ +MIO_PIN_44 + +	+0XF80007B0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 44 Control +
+ +MIO_PIN_45 + +	+0XF80007B4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 45 Control +
+ +MIO_PIN_46 + +	+0XF80007B8 +	+32 +	+RW +	+0x000000 +	+MIO Pin 46 Control +
+ +MIO_PIN_47 + +	+0XF80007BC +	+32 +	+RW +	+0x000000 +	+MIO Pin 47 Control +
+ +MIO_PIN_48 + +	+0XF80007C0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 48 Control +
+ +MIO_PIN_49 + +	+0XF80007C4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 49 Control +
+ +MIO_PIN_50 + +	+0XF80007C8 +	+32 +	+RW +	+0x000000 +	+MIO Pin 50 Control +
+ +MIO_PIN_51 + +	+0XF80007CC +	+32 +	+RW +	+0x000000 +	+MIO Pin 51 Control +
+ +MIO_PIN_52 + +	+0XF80007D0 +	+32 +	+RW +	+0x000000 +	+MIO Pin 52 Control +
+ +MIO_PIN_53 + +	+0XF80007D4 +	+32 +	+RW +	+0x000000 +	+MIO Pin 53 Control +
+ +SD0_WP_CD_SEL + +	+0XF8000830 +	+32 +	+RW +	+0x000000 +	+SDIO 0 WP CD select +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_mio_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

OCM REMAPPING

Register ( slcr )GPIOB_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GPIOB_CTRL +	+0XF8000B00 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_EN + +0:0 + +1 + +1 + +1 + +Enables VREF internal generator +
+VREF_PULLUP_EN + +1:1 + +2 + +0 + +0 + +Enables internal pullup. 0 - no pullup. 1 - pullup. +
+CLK_PULLUP_EN + +8:8 + +100 + +0 + +0 + +Enables internal pullup. 0: no pullup. 1: pullup. +
+SRSTN_PULLUP_EN + +9:9 + +200 + +0 + +0 + +Enables internal pullup. 0: no pullup. 1: pullup. +
+GPIOB_CTRL@0XF8000B00 + +31:0 + +303 + + + +1 + +PS IO Buffer Control +
+

DDRIOB SETTINGS

Register ( slcr )DDRIOB_ADDR0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_ADDR0 +	+0XF8000B40 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 0 +
+

Register ( slcr )DDRIOB_ADDR1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_ADDR1 +	+0XF8000B44 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDR IOB Config for Address 1 +
+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA0 +	+0XF8000B48 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 15:0 +
+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA1 +	+0XF8000B4C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDR IOB Config for Data 31:16 +
+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF0 +	+0XF8000B50 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 1:0 +
+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF1 +	+0XF8000B54 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDR IOB Config for DQS 3:2 +
+

Register ( slcr )DDRIOB_CLOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_CLOCK +	+0XF8000B58 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0: low power mode. 1: high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00: Input off, reads 0. 01: Vref based differential receiver for SSTL, HSTL. 10: Differential input receiver. 11: LVCMOS receiver. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00: DCI Disabled 01: DCI Drive (HSTL12_DCI) 10: reserved 11: DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0: ibuf is enabled 1: use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0: termination enabled 1: use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00: ibuf 01 and 10: reserved 11: obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0: no pullup 1: pullup enabled +
+DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDR IOB Config for Clock Output +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_ADDR +	+0XF8000B5C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +3 + +c000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +3 + +180000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDR IOB Slew for Address +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_DATA +	+0XF8000B60 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Data +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_DIFF +	+0XF8000B64 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Diff +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_CLOCK +	+0XF8000B68 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000: Normal Operation 001 to 111: Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDR IOB Slew for Clock +
+

Register ( slcr )DDRIOB_DDR_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DDR_CTRL +	+0XF8000B6C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_INT_EN + +0:0 + +1 + +1 + +1 + +Enables VREF internal generator +
+VREF_SEL + +4:1 + +1e + +4 + +8 + +Specifies DDR IOB Vref generator output: 0001: VREF = 0.6V for LPDDR2 with 1.2V IO 0100: VREF = 0.75V for DDR3 with 1.5V IO 1000: VREF = 0.90V for DDR2 with 1.8V IO +
+VREF_EXT_EN + +6:5 + +60 + +0 + +0 + +Enables External VREF input x0: Disable External VREF for lower 16 bits x1: Enable External VREF for lower 16 bits 0x: Disable External VREF for upper 16 bits 1X: Enable External VREF for upper 16 bits +
+VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors x0: Disable VREF pull-up for lower 16 bits x1: Enable VREF pull-up for lower 16 bits 0x: Disable VREF pull-up for upper 16 bits 1x: Enable VREF pull-up for upper 16 bits +
+REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0: VRP/VRN not used 1: VRP/VRN used as refio +
+REFIO_TEST + +11:10 + +c00 + +3 + +c00 + +Enable test mode for VRP and VRN: 00: VRP/VRN test mode not used 11: VRP/VRN test mode enabled using vref based receiver. VRP/VRN control is set using the VRN_OUT, VRP_OUT, VRN_TRI, VRP_TRI fields in the DDRIOB_DCI_CTRL register +
+REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0: no pull-up 1: enable pull-up +
+DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
+CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0: no pull-up 1: enable pull-up +
+DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +7fff + + + +e09 + +DDR IOB Buffer Control +
+

ASSERT RESET

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +1 + +1 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +21 + +DDRIOB DCI configuration +
+

DEASSERT RESET

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

MIO PROGRAMMING

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_00 +	+0XF8000700 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. 0: disable 1: enable +
+Speed + +8:8 + +100 + +0 + +0 + +Select IO Buffer Edge Rate, applicable when IO_Type= LVCMOS18, LVCMOS25 or LVCMOS33. 0: Slow CMOS edge 1: Fast CMOS edge +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Select the IO Buffer Type. 000: LVTTL 001: LVCMOS18 010: LVCMOS25 011, 101, 110, 111: LVCMOS33 100: HSTL +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Enables pull-up on IO Buffer pin 0: disable 1: enable +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Disable HSTL Input Buffer to save power when it is an output-only (IO_Type must be HSTL). 0: enable 1: disable +
+MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1201 + +MIO Pin 0 Control +
+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_01 +	+0XF8000704 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Chip Select +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM Address Bit 25 10: SRAM/NOR Chip Select 1 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 1 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1202 + +MIO Pin 1 Control +
+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_02 +	+0XF8000708 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 8 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash ALEn 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 2 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +202 + +MIO Pin 2 Control +
+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_03 +	+0XF800070C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 9 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data bit 0 10: NAND WE_B output 11: SDIO 1 Card Power output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 3 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +202 + +MIO Pin 3 Control +
+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_04 +	+0XF8000710 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 10 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 1 10: NAND Flash IO Bit 2 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 4 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +202 + +MIO Pin 4 Control +
+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_05 +	+0XF8000714 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 11 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 2 10: NAND Flash IO Bit 0 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 5 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +202 + +MIO Pin 5 Control +
+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_06 +	+0XF8000718 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 0 Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 12 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 3 10: NAND Flash IO Bit 1 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 6 (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +202 + +MIO Pin 6 Control +
+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_07 +	+0XF800071C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 13 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR OE_B 10: NAND Flash CLE_B 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 7 Output-only (bank 0) others: reserved +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +200 + +MIO Pin 7 Control +
+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_08 +	+0XF8000720 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI Feedback Output Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 14 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR WE_B 10: NAND Flash RD_B 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 8 Output-only (bank 0) 001: CAN 1 Tx 010: sram, Output, smc_sram_bls_b 011 to 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +202 + +MIO Pin 8 Control +
+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_09 +	+0XF8000724 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 Flash Memory Clock Output +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 15 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 6 10: NAND Flash IO Bit 4 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 9 (bank 0) 001: CAN 1 Rx 010 to 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1200 + +MIO Pin 9 Control +
+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_10 +	+0XF8000728 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 7 10: NAND Flash IO Bit 5 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 10 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1200 + +MIO Pin 10 Control +
+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_11 +	+0XF800072C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 4 10: NAND Flash IO Bit 6 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 11 (bank 0) 001: CAN 0 Tx 010: I2C Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1200 + +MIO Pin 11 Control +
+

Register ( slcr )MIO_PIN_12

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_12 +	+0XF8000730 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Wait 10: NAND Flash IO Bit 7 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 12 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1200 + +MIO Pin 12 Control +
+

Register ( slcr )MIO_PIN_13

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_13 +	+0XF8000734 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Quad SPI 1 IO Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Data Bit 5 10: NAND Flash IO Bit 3 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 13 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1200 + +MIO Pin 13 Control +
+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_14 +	+0XF8000738 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: NAND Flash Busy 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 14 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 slave select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1200 + +MIO Pin 14 Control +
+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_15 +	+0XF800073C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_15@0XF800073C + +31:0 + +3f01 + + + +1201 + +MIO Pin 15 Control +
+

Register ( slcr )MIO_PIN_16

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_16 +	+0XF8000740 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 1 10: NAND Flash IO Bit 8 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 16 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Output 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +2802 + +MIO Pin 16 Control +
+

Register ( slcr )MIO_PIN_17

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_17 +	+0XF8000744 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 2 10: NAND Flash IO Bit 9 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 17 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110 TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +2802 + +MIO Pin 17 Control +
+

Register ( slcr )MIO_PIN_18

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_18 +	+0XF8000748 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 3 10: NAND Flash IO Bit 10 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 18 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +2802 + +MIO Pin 18 Control +
+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_19 +	+0XF800074C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 4 10: NAND Flash IO Bit 11 111: SDIO 1 Power Control Output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 19 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 Output 110: TTC 0 Clock Input 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +2802 + +MIO Pin 19 Control +
+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_20 +	+0XF8000750 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 5 10: NAND Flash IO Bit 12 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 20 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +2802 + +MIO Pin 20 Control +
+

Register ( slcr )MIO_PIN_21

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_21 +	+0XF8000754 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 6 10: NAND Flash IO Bit 13 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 21 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +2802 + +MIO Pin 21 Control +
+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_22 +	+0XF8000758 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 7 10: NAND Flash IO Bit 14 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 22 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +803 + +MIO Pin 22 Control +
+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_23 +	+0XF800075C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD 0 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 8 10: NAND Flash IO Bit 15 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 23 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +803 + +MIO Pin 23 Control +
+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_24 +	+0XF8000760 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 1 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Clock output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 9 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 24 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 serial clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +803 + +MIO Pin 24 Control +
+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_25 +	+0XF8000764 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit2 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Control Signal output +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 10 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 25 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +803 + +MIO Pin 25 Control +
+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_26 +	+0XF8000768 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII RxD Bit 3 +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 11 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 26 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +803 + +MIO Pin 26 Control +
+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_27 +	+0XF800076C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 0 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: Trace Port Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 12 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 27 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +803 + +MIO Pin 27 Control +
+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_28 +	+0XF8000770 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Clock +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 13 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 28 (bank 0) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +204 + +MIO Pin 28 Control +
+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_29 +	+0XF8000774 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 0 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 14 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 29 (bank 0) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +205 + +MIO Pin 29 Control +
+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_30 +	+0XF8000778 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 1 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 15 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 30 (bank 0) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Slave Select 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +204 + +MIO Pin 30 Control +
+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_31 +	+0XF800077C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 2 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 16 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 31 (bank 0) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +205 + +MIO Pin 31 Control +
+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_32 +	+0XF8000780 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII TxD Bit 3 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 17 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 32 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +204 + +MIO Pin 32 Control +
+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_33 +	+0XF8000784 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Tx Control +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 18 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 33 (Bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 MOSI 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +204 + +MIO Pin 33 Control +
+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_34 +	+0XF8000788 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Clock +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 19 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 34 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +204 + +MIO Pin 34 Control +
+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_35 +	+0XF800078C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD data Bit 0 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 20 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 35 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 Command 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +204 + +MIO Pin 35 Control +
+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_36 +	+0XF8000790 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Data Bit 1 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 21 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 36 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +205 + +MIO Pin 36 Control +
+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_37 +	+0XF8000794 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 22 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 37 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: PJTAG TMS+H2129 100: SDIO 1 IO Bit 1 101: SPI 1 Slave Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +204 + +MIO Pin 37 Control +
+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_38 +	+0XF8000798 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII RxD Data Bit 3 +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 23 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 38 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock In 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +204 + +MIO Pin 38 Control +
+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_39 +	+0XF800079C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: Ethernet 1 RGMII Rx Control +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 0 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: SRAM/NOR Address Bit 24 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 000: GPIO 39 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Out 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 2 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +204 + +MIO Pin 39 Control +
+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_40 +	+0XF80007A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 4 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 40 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: reserved 100: SDIO 0 Clock 101: SPI 0 Serial Clock 110: TTC 1 Wave Out 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +280 + +MIO Pin 40 Control +
+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_41 +	+0XF80007A4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Direction +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 41 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 Command 101: SPI 0 MISO 110: TTC 1 Clock Input 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +280 + +MIO Pin 41 Control +
+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_42 +	+0XF80007A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Stop +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 42 (bank 1) 001: CAN 0 Rx 010: I2C0 Serial Clock 011: reserved 100: SDIO 0 IO Bit 0 101: SPI 0 Data Bit 0 110: TTC 0 Wave Out 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +280 + +MIO Pin 42 Control +
+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_43 +	+0XF80007AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Next +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 43 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: reserved 100: SDIO 0 IO Bit 1 101: SPI 0 Slave Select 1 110: TTC 0 Clock Intput 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +280 + +MIO Pin 43 Control +
+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_44 +	+0XF80007B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 0 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 44 (bank 1) 001: CAN 1 Tx 010: I2C Serial Clock 011: reserved 100 SDIO 0 IO Bit 2 101: SPI 0 Slave Select 2 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +280 + +MIO Pin 44 Control +
+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_45 +	+0XF80007B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 1 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 45 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: reserved 100: SDIO 0 IO Bit 3 101: SPI 0 Data Bit 3 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +280 + +MIO Pin 45 Control +
+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_46 +	+0XF80007B8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 2 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 46 (bank 1) 001: CAN 0 Rx 010: I2C 0 Serial Clock 011: PJTAG TDI 100: SDIO 1 IO Bit 0 101: SPI 1 MOSI 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1221 + +MIO Pin 46 Control +
+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_47 +	+0XF80007BC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 3 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 000: GPIO 47 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: PJTAG TDO 100: SDIO 1 Command 101: SPI 1 MISO 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1220 + +MIO Pin 47 Control +
+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_48 +	+0XF80007C0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Clock +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 48 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: PJTAG TCK 100: SDIO 1 Clock 101: SPI 1 Serial Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +2e0 + +MIO Pin 48 Control +
+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_49 +	+0XF80007C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 5 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 000: GPIO 49 (bank 1) 001: CAN 1 Rx 010: I2C Serial Data 011: PJTAG TMS 100: SDIO 1 IO Bit 1 101: SPI 1 Select 0 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +2e1 + +MIO Pin 49 Control +
+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_50 +	+0XF80007C8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 6 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 50 (bank 1) 001: Can 0 Rx 010: I2C 0 Serial Clock 011: SWDT Clock Input 100: SDIO 1 IO Bit 2 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1240 + +MIO Pin 50 Control +
+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_51 +	+0XF80007CC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: USB 1 ULPI Data Bit 7 +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 000: GPIO 51 (bank 1) 001: CAN 0 Tx 010: I2C 0 Serial Data 011: SWDT Reset Output 100: SDIO 1 IO Bit 3 101: SPI 1 Slave Select 1 110: reserved 111: UART 0 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1240 + +MIO Pin 51 Control +
+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_52 +	+0XF80007D0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 0 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 52 (bank 1) 001: CAN 1 Tx 010: I2C 1 Serial Clock 011: SWDT Clock Input 100: MDIO 0 Clock 101: MDIO 1 Clock 110: reserved 111: UART 1 TxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +280 + +MIO Pin 52 Control +
+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_53 +	+0XF80007D4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Operates the same as MIO_PIN_00[TRI_ENABLE] +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0: Level 1 Mux 1: reserved +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0: Level 2 Mux 1: reserved +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 00: Level 3 Mux 01: reserved 10: reserved 11: SDIO 1 Power Control output +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 000: GPIO 53 (bank 1) 001: CAN 1 Rx 010: I2C 1 Serial Data 011: SWDT Reset Output 100: MDIO 0 Data 101: MDIO 1 Data 110: reserved 111: UART 1 RxD +
+Speed + +8:8 + +100 + +0 + +0 + +Operates the same as MIO_PIN_00[Speed] +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Operates the same as MIO_PIN_00[IO_Type] +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Operates the same as MIO_PIN_00[PULL_UP] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Operates the same as MIO_PIN_00[DisableRcvr] +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +280 + +MIO Pin 53 Control +
+

Register ( slcr )SD0_WP_CD_SEL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SD0_WP_CD_SEL +	+0XF8000830 +	+32 +	+rw +	+0x00000000 +	+-- +

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_peripherals_init_data_2_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +DDRIOB_DATA0 + +	+0XF8000B48 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 15:0 +
+ +DDRIOB_DATA1 + +	+0XF8000B4C +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for Data 31:16 +
+ +DDRIOB_DIFF0 + +	+0XF8000B50 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 1:0 +
+ +DDRIOB_DIFF1 + +	+0XF8000B54 +	+32 +	+RW +	+0x000000 +	+DDR IOB Config for DQS 3:2 +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +
+ +Baud_rate_divider_reg0 + +	+0XE0001034 +	+32 +	+RW +	+0x000000 +	+baud rate divider register +
+ +Baud_rate_gen_reg0 + +	+0XE0001018 +	+32 +	+RW +	+0x000000 +	+Baud rate divider register. +
+ +Control_reg0 + +	+0XE0001000 +	+32 +	+RW +	+0x000000 +	+UART Control register +
+ +mode_reg0 + +	+0XE0001004 +	+32 +	+RW +	+0x000000 +	+UART Mode register +
+ +Config_reg + +	+0XE000D000 +	+32 +	+RW +	+0x000000 +	+SPI configuration register +
+ +CTRL + +	+0XF8007000 +	+32 +	+RW +	+0x000000 +	+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable (GPIO Bank0, MIO) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +

ps7_peripherals_init_data_2_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

DDR TERM/IBUF_DISABLE_MODE SETTINGS

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA0 +	+0XF8000B48 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA1 +	+0XF8000B4C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF0 +	+0XF8000B50 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF1 +	+0XF8000B54 +	+32 +	+rw +	+0x00000000 +	+-- +

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

SRAM/NOR SET OPMODE

TRACE CURRENT PORT SIZE

UART REGISTERS

Register ( slcr )Baud_rate_divider_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Baud_rate_divider_reg0 +	+0XE0001034 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )Baud_rate_gen_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Baud_rate_gen_reg0 +	+0XE0001018 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CD + +15:0 + +ffff + +3e + +3e + +Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass 2 - 65535: baud_sample value +
+Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +3e + +Baud rate divider register. +
+

Register ( slcr )Control_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Control_reg0 +	+0XE0001000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break: 0: start break transmission, 1: stop break transmission. +
+STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break: 0: 1: start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
+RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter: 0: receiver timeout counter disabled, 1: receiver timeout counter is restarted. +
+TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable: 0: enable transmitter, 0: disable transmitter +
+TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable: 0: disable transmitter, 1: enable transmitter, provided the TXDIS field is set to 0. +
+RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable: 0: disable, 1: enable +
+RXEN + +2:2 + +4 + +1 + +4 + +Receive enable: 0: disable, 1: enable. When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero. +
+TXRES + +1:1 + +2 + +1 + +2 + +Software reset for Tx data path: 0: 1: transmitter logic is reset and all pending transmitter data is discarded self clear +
+RXRES + +0:0 + +1 + +1 + +1 + +Software reset for Rx data path: 0: 1: receiver logic is reset and all pending receiver data is discarded self clear +
+Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
+

Register ( slcr )mode_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+mode_reg0 +	+0XE0001004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode: 0: Default UART mode 1: Enable IrDA mode +
+UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select: 0: APB clock, pclk 1: a user-defined clock +
+CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode: 00: normal 01: automatic cho 10: local loopback 11: remote loopback +
+NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits: 00: 1 stop bit 01: 1.5 stop bits 10: 2 stop bits 11: reserved +
+PAR + +5:3 + +38 + +4 + +20 + +Parity type select: 000: even parity 001: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity +
+CHRL + +2:1 + +6 + +0 + +0 + +Character length select: 11: 6 bits 10: 7 bits 0x: 8 bits +
+CLKS + +0:0 + +1 + +0 + +0 + +Clock source select: 0: clock source is uart_clk 1: clock source is uart_clk/8 +
+mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
+

QSPI REGISTERS

Register ( slcr )Config_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Config_reg +	+0XE000D000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
+Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
+

PL POWER ON RESET REGISTERS

Register ( slcr )CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CTRL +	+0XF8007000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
+CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

DIR MODE BANK 0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +ff7f + +ff7f0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +ff7f0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ENET RESET

DIR MODE BANK 0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +800 + +800 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0800 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +800 + +800 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0800 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

I2C RESET

DIR MODE GPIO BANK0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

DIR MODE GPIO BANK1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +2000 + +2000 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff2000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

OUTPUT ENABLE

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff0000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +On a write, only bits with a corresponding deasserted mask will change the output value. 0: pin value is updated 1: pin is masked Each bit controls the corresponding pin within the 16-bit half-bank. Reads return 0's. +
+DATA_0_LSW + +15:0 + +ffff + +2000 + +2000 + +On a write, these are the data values for the corresponding GPIO output bits. Each bit controls the corresponding pin within the 16-bit half-bank. Reads return the previous value written to this register or DATA_0[15:0]. Reads do not return the value on the GPIO pin. +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff2000 + +Maskable Output Data (GPIO Bank0, MIO, Lower 16bits) +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

+ +

ps7_post_config_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +LVL_SHFTR_EN + +	+0XF8000900 +	+32 +	+RW +	+0x000000 +	+Level Shifters Enable +
+ +FPGA_RST_CTRL + +	+0XF8000240 +	+32 +	+RW +	+0x000000 +	+FPGA Software Reset Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_post_config_2_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

ENABLING LEVEL SHIFTER

Register ( slcr )LVL_SHFTR_EN

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LVL_SHFTR_EN +	+0XF8000900 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+USER_INP_ICT_EN_0 + +1:0 + +3 + +3 + +3 + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 0, drives slcr_fpga_if_ctrl0[1:0]. +
+USER_INP_ICT_EN_1 + +3:2 + +c + +3 + +c + +Enable level shifters for PSS user inputs to FPGA in FPGA tile 1, drives slcr_fpga_if_ctrl1[1:0]. +
+LVL_SHFTR_EN@0XF8000900 + +31:0 + +f + + + +f + +Level Shifters Enable +
+

FPGA RESETS TO 0

Register ( slcr )FPGA_RST_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA_RST_CTRL +	+0XF8000240 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset: 0: No reset 1: ACP AXI interface reset output asserted +
+FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0: No reset 1: AXDS3AXI interface reset output asserted +
+FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0: No reset 1: AXDS2 AXI interface reset output asserted +
+FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0: No reset 1: AXDS1 AXI interface reset output asserted +
+FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0: No reset 1: AXDS0 AXI interface reset output asserted +
+reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0: No reset 1: FPGA slave interface 1 reset is asserted +
+FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0: No reset 1: FPGA slave interface 0 reset is asserted +
+reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface: 1: soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0: No reset 1: FPGA master interface 1 reset is asserted +
+FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0: No reset 1: FPGA master interface 0 reset is asserted. +
+FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 3 peripheral request reset output asserted +
+FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 2 peripheral request reset output asserted +
+FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 1 peripheral request reset output asserted +
+FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0: No reset 1: FPGA DMA 0 peripheral request reset output asserted +
+reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is zero. +
+FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0: No reset 1: FPGA 3 top level reset output asserted +
+FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0: No reset 1: FPGA 2 top level reset output asserted +
+FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0: No reset 1: FPGA 1 top level reset output asserted +
+FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0: No reset 1: FPGA 0 top level reset output asserted +
+FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
+

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_debug_2_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +LAR + +	+0XF8898FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +
+ +LAR + +	+0XF8899FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +
+ +LAR + +	+0XF8809FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +

ps7_debug_2_0

+ + + + + + + + + +

CROSS TRIGGER CONFIGURATIONS

UNLOCKING CTI REGISTERS

Register ( slcr )LAR

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8898FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8899FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8809FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

ENABLING CTI MODULES AND CHANNELS

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

+ +

+ + + + +

ps7_pll_init_data_1_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +ARM_PLL_CFG + +	+0XF8000110 +	+32 +	+RW +	+0x000000 +	+ARM PLL Configuration +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_PLL_CTRL + +	+0XF8000100 +	+32 +	+RW +	+0x000000 +	+ARM PLL Control +
+ +ARM_CLK_CTRL + +	+0XF8000120 +	+32 +	+RW +	+0x000000 +	+CORTEX A9 Clock Control +
+ +DDR_PLL_CFG + +	+0XF8000114 +	+32 +	+RW +	+0x000000 +	+DDR PLL Configuration +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_PLL_CTRL + +	+0XF8000104 +	+32 +	+RW +	+0x000000 +	+DDR PLL Control +
+ +DDR_CLK_CTRL + +	+0XF8000124 +	+32 +	+RW +	+0x000000 +	+DDR Clock Control +
+ +IO_PLL_CFG + +	+0XF8000118 +	+32 +	+RW +	+0x000000 +	+IO PLL Configuration +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +IO_PLL_CTRL + +	+0XF8000108 +	+32 +	+RW +	+0x000000 +	+IO PLL Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_pll_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CFG +	+0XF8000110 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +fa + +fa000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+ARM_PLL_CFG@0XF8000110 + +31:0 + +3ffff0 + + + +fa220 + +ARM PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +28 + +28000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +7f000 + + + +28000 + +ARM PLL Control +
+

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +10 + +ARM PLL Control +
+

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +1 + +ARM PLL Control +
+

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset; 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +1 + + + +0 + +ARM PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ARM_PLL_LOCK + +0:0 + +1 + +1 + +1 + +ARM PLL lock status. 0 - ARM PLL out of lock. 1 - ARM PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
+PLL_STATUS@0XF800010C + +31:0 + +1 + + + +1 + +tobe +
+

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_PLL_CTRL +	+0XF8000100 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed. +
+ARM_PLL_CTRL@0XF8000100 + +31:0 + +10 + + + +0 + +ARM PLL Control +
+

Register ( slcr )ARM_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ARM_CLK_CTRL +	+0XF8000120 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is CPU PLL. 10 - Source for generated clock is DDR divided clock. 11 - Source for generated clock is IO PLL +
+DIVISOR + +13:8 + +3f00 + +2 + +200 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+CPU_6OR4XCLKACT + +24:24 + +1000000 + +1 + +1000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_3OR2XCLKACT + +25:25 + +2000000 + +1 + +2000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_2XCLKACT + +26:26 + +4000000 + +1 + +4000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_1XCLKACT + +27:27 + +8000000 + +1 + +8000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CPU_PERI_CLKACT + +28:28 + +10000000 + +1 + +10000000 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+ARM_CLK_CTRL@0XF8000120 + +31:0 + +1f003f30 + + + +1f000200 + +CORTEX A9 Clock Control +
+

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CFG +	+0XF8000114 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +2 + +20 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +12c + +12c000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+DDR_PLL_CFG@0XF8000114 + +31:0 + +3ffff0 + + + +12c220 + +DDR PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +20 + +20000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +7f000 + + + +20000 + +DDR PLL Control +
+

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +10 + +DDR PLL Control +
+

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +1 + +DDR PLL Control +
+

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +1 + + + +0 + +DDR PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_PLL_LOCK + +1:1 + +2 + +1 + +2 + +DDR PLL lock status. 0 - DDR PLL out of lock. 1 - DDR PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
+PLL_STATUS@0XF800010C + +31:0 + +2 + + + +2 + +tobe +
+

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_PLL_CTRL +	+0XF8000104 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+DDR_PLL_CTRL@0XF8000104 + +31:0 + +10 + + + +0 + +DDR PLL Control +
+

Register ( slcr )DDR_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDR_CLK_CTRL +	+0XF8000124 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DDR_3XCLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+DDR_2XCLKACT + +1:1 + +2 + +1 + +2 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+DDR_3XCLK_DIVISOR + +25:20 + +3f00000 + +2 + +200000 + +Divisor value for the ddr_3xclk +
+DDR_2XCLK_DIVISOR + +31:26 + +fc000000 + +3 + +c000000 + +Divisor value for the ddr_2xclk (does not have to be 2/3 speed of ddr_3xclk) +
+DDR_CLK_CTRL@0XF8000124 + +31:0 + +fff00003 + + + +c200003 + +DDR Clock Control +
+

IO PLL INIT

Register ( slcr )IO_PLL_CFG

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CFG +	+0XF8000118 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RES + +7:4 + +f0 + +c + +c0 + +Drives the PLL_RES[3:0] input of the PLL to set the PLL loop filter resistor control +
+PLL_CP + +11:8 + +f00 + +2 + +200 + +Drives the PLL_CP[3:0] input of the PLL to set the PLL charge pump control +
+LOCK_CNT + +21:12 + +3ff000 + +145 + +145000 + +Drives the LOCK_CNT[9:0] input of the PLL to set the number of clock cycles the PLL needs to have clkref and clkfb aligned withth a certain window before syaing locked. +
+IO_PLL_CFG@0XF8000118 + +31:0 + +3ffff0 + + + +1452c0 + +IO PLL Configuration +
+

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_FDIV + +18:12 + +7f000 + +1e + +1e000 + +Provides the feedback divisor for the PLL. NOTE: Before changing this value the PLL must first be bypassed and then put into powerdown or reset state. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +7f000 + + + +1e000 + +IO PLL Control +
+

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +1 + +10 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +10 + +IO PLL Control +
+

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +1 + +1 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +1 + +IO PLL Control +
+

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_RESET + +0:0 + +1 + +0 + +0 + +Drives the RESET input of the PLL. 0 - PLL out of reset. 1 - PLL held in reset. Remember that after reset, the user should program the PLLs and ensure that the serviced bit below is asserted before using. +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +1 + + + +0 + +IO PLL Control +
+

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PLL_STATUS +	+0XF800010C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IO_PLL_LOCK + +2:2 + +4 + +1 + +4 + +IO PLL lock status. 0 - IO PLL out of lock. 1 - IO PLL in lock. Note: Reset condition is actually 0, but will always be 1 by the time this register can be read if PLL's are being used. +
+PLL_STATUS@0XF800010C + +31:0 + +4 + + + +4 + +tobe +
+

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+IO_PLL_CTRL +	+0XF8000108 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PLL_BYPASS_FORCE + +4:4 + +10 + +0 + +0 + +Overides control of the PLL bypass function within the clock controller to force into bypass state. 0 - PLL not forced to be bypassed (may still be bypassed through bootstrap pin). 1 - PLL forced to be bypassed +
+IO_PLL_CTRL@0XF8000108 + +31:0 + +10 + + + +0 + +IO PLL Control +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_clock_init_data_1_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +DCI_CLK_CTRL + +	+0XF8000128 +	+32 +	+RW +	+0x000000 +	+DCI clock control +
+ +GEM0_RCLK_CTRL + +	+0XF8000138 +	+32 +	+RW +	+0x000000 +	+Gigabit Ethernet MAC 0 RX Clock Control +
+ +GEM0_CLK_CTRL + +	+0XF8000140 +	+32 +	+RW +	+0x000000 +	+Gigabit Ethernet MAC 0 Ref Clock Control +
+ +LQSPI_CLK_CTRL + +	+0XF800014C +	+32 +	+RW +	+0x000000 +	+Linear Quad-SPI Reference Clock Control +
+ +SDIO_CLK_CTRL + +	+0XF8000150 +	+32 +	+RW +	+0x000000 +	+SDIO Reference Clock Control +
+ +UART_CLK_CTRL + +	+0XF8000154 +	+32 +	+RW +	+0x000000 +	+UART Reference Clock Control +
+ +CAN_CLK_CTRL + +	+0XF800015C +	+32 +	+RW +	+0x000000 +	+CAN Reference Clock Control +
+ +CAN_MIOCLK_CTRL + +	+0XF8000160 +	+32 +	+RW +	+0x000000 +	+CAN MIO Clock Control +
+ +PCAP_CLK_CTRL + +	+0XF8000168 +	+32 +	+RW +	+0x000000 +	+PCAP 2X Clock Contol +
+ +FPGA0_CLK_CTRL + +	+0XF8000170 +	+32 +	+RW +	+0x000000 +	+FPGA 0 Output Clock Control +
+ +FPGA1_CLK_CTRL + +	+0XF8000180 +	+32 +	+RW +	+0x000000 +	+FPGA 1 Output Clock Control +
+ +FPGA2_CLK_CTRL + +	+0XF8000190 +	+32 +	+RW +	+0x000000 +	+FPGA 2 Output Clock Control +
+ +FPGA3_CLK_CTRL + +	+0XF80001A0 +	+32 +	+RW +	+0x000000 +	+FPGA 3 Output Clock Control +
+ +CLK_621_TRUE + +	+0XF80001C4 +	+32 +	+RW +	+0x000000 +	+6:2:1 ratio clock, if set +
+ +APER_CLK_CTRL + +	+0XF800012C +	+32 +	+RW +	+0x000000 +	+AMBA Peripheral Clock Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_clock_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DCI_CLK_CTRL +	+0XF8000128 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+DIVISOR0 + +13:8 + +3f00 + +23 + +2300 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+DCI_CLK_CTRL@0XF8000128 + +31:0 + +3f03f01 + + + +302301 + +DCI clock control +
+

Register ( slcr )GEM0_RCLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GEM0_RCLK_CTRL +	+0XF8000138 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +4:4 + +10 + +0 + +0 + +Selects the source used to generate the clock. 0 - Source for generated clock is GEM 0 MIO RX clock. 1 - Source for generated clock is GEM 0 FMIO RX clock. +
+GEM0_RCLK_CTRL@0XF8000138 + +31:0 + +11 + + + +1 + +Gigabit Ethernet MAC 0 RX Clock Control +
+

Register ( slcr )GEM0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GEM0_CLK_CTRL +	+0XF8000140 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +6:4 + +70 + +0 + +0 + +Selects the source used to generate the clock. 1xx - Source for generated clock is Ethernet 0 FMIO clock. 00x - Source for generated clock is IO PLL. 010 - Source for generated clock is ARM PLL. 011 - Source for generated clock is DDR PLL +
+DIVISOR + +13:8 + +3f00 + +8 + +800 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +5 + +500000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+GEM0_CLK_CTRL@0XF8000140 + +31:0 + +3f03f71 + + + +500801 + +Gigabit Ethernet MAC 0 Ref Clock Control +
+

Register ( slcr )LQSPI_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LQSPI_CLK_CTRL +	+0XF800014C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+LQSPI_CLK_CTRL@0XF800014C + +31:0 + +3f31 + + + +501 + +Linear Quad-SPI Reference Clock Control +
+

Register ( slcr )SDIO_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SDIO_CLK_CTRL +	+0XF8000150 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +SDIO 0 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +SDIO 1 Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+SDIO_CLK_CTRL@0XF8000150 + +31:0 + +3f33 + + + +1401 + +SDIO Reference Clock Control +
+

Register ( slcr )UART_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+UART_CLK_CTRL +	+0XF8000154 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +0 + +0 + +UART 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CLKACT1 + +1:1 + +2 + +1 + +2 + +UART 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+UART_CLK_CTRL@0XF8000154 + +31:0 + +3f33 + + + +1402 + +UART Reference Clock Control +
+

Register ( slcr )CAN_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CAN_CLK_CTRL +	+0XF800015C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT0 + +0:0 + +1 + +1 + +1 + +CAN 0 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+CLKACT1 + +1:1 + +2 + +0 + +0 + +CAN 1 Reference Clock active. 0 - Clock is disabled. 1 - Clock is enabled. +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +e + +e00 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +3 + +300000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+CAN_CLK_CTRL@0XF800015C + +31:0 + +3f03f33 + + + +300e01 + +CAN Reference Clock Control +
+

Register ( slcr )CAN_MIOCLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CAN_MIOCLK_CTRL +	+0XF8000160 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CAN0_MUX + +5:0 + +3f + +0 + +0 + +CAN0 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN0_REF_SEL + +6:6 + +40 + +0 + +0 + +CAN 0 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field +
+CAN1_MUX + +21:16 + +3f0000 + +0 + +0 + +CAN1 mux selection for MIO. Setting this to zero will select MIO[0] as the clock source. Only values 0-53 are valid. +
+CAN1_REF_SEL + +22:22 + +400000 + +0 + +0 + +CAN1 Reference Clock selection. 0 - From internal PLL. 1 - From MIO based on the next field +
+CAN_MIOCLK_CTRL@0XF8000160 + +31:0 + +7f007f + + + +0 + +CAN MIO Clock Control +
+

Register ( slcr )PCAP_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PCAP_CLK_CTRL +	+0XF8000168 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLKACT + +0:0 + +1 + +1 + +1 + +Clock active 0 - Clock is disabled 1 - Clock is enabled +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL +
+DIVISOR + +13:8 + +3f00 + +5 + +500 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. +
+PCAP_CLK_CTRL@0XF8000168 + +31:0 + +3f31 + + + +501 + +PCAP 2X Clock Contol +
+

Register ( slcr )FPGA0_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA0_CLK_CTRL +	+0XF8000170 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA0_CLK_CTRL@0XF8000170 + +31:0 + +3f03f30 + + + +101400 + +FPGA 0 Output Clock Control +
+

Register ( slcr )FPGA1_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA1_CLK_CTRL +	+0XF8000180 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA1_CLK_CTRL@0XF8000180 + +31:0 + +3f03f30 + + + +101400 + +FPGA 1 Output Clock Control +
+

Register ( slcr )FPGA2_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA2_CLK_CTRL +	+0XF8000190 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA2_CLK_CTRL@0XF8000190 + +31:0 + +3f03f30 + + + +101400 + +FPGA 2 Output Clock Control +
+

Register ( slcr )FPGA3_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA3_CLK_CTRL +	+0XF80001A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SRCSEL + +5:4 + +30 + +0 + +0 + +Selects the source used to generate the clock. 0x - Source for generated clock is IO PLL. 10 - Source for generated clock is ARM PLL. 11 - Source for generated clock is DDR PLL. +
+DIVISOR0 + +13:8 + +3f00 + +14 + +1400 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. First cascade divider +
+DIVISOR1 + +25:20 + +3f00000 + +1 + +100000 + +Provides the divisor used to divide the source clock to generate the required generated clock frequency. Second cascade divider +
+FPGA3_CLK_CTRL@0XF80001A0 + +31:0 + +3f03f30 + + + +101400 + +FPGA 3 Output Clock Control +
+

Register ( slcr )CLK_621_TRUE

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CLK_621_TRUE +	+0XF80001C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CLK_621_TRUE + +0:0 + +1 + +1 + +1 + +Enable the 6:2:1 mode. 1 for 6:3:2:1. 0 for 4:2:2:1. +
+CLK_621_TRUE@0XF80001C4 + +31:0 + +1 + + + +1 + +6:2:1 ratio clock, if set +
+

Register ( slcr )APER_CLK_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+APER_CLK_CTRL +	+0XF800012C +	+32 +	+rw +	+0x00000000 +	+-- +

THIS SHOULD BE BLANK

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_ddr_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +ddrc_ctrl + +	+0XF8006000 +	+32 +	+RW +	+0x000000 +	+DDRC Control Register +
+ +Two_rank_cfg + +	+0XF8006004 +	+32 +	+RW +	+0x000000 +	+Two rank configuration register +
+ +HPR_reg + +	+0XF8006008 +	+32 +	+RW +	+0x000000 +	+HPR Queue control register +
+ +LPR_reg + +	+0XF800600C +	+32 +	+RW +	+0x000000 +	+LPR Queue control register +
+ +WR_reg + +	+0XF8006010 +	+32 +	+RW +	+0x000000 +	+WR Queue control register +
+ +DRAM_param_reg0 + +	+0XF8006014 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters register 0 +
+ +DRAM_param_reg1 + +	+0XF8006018 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters register 1 +
+ +DRAM_param_reg2 + +	+0XF800601C +	+32 +	+RW +	+0x000000 +	+DRAM Parameters register 2 +
+ +DRAM_param_reg3 + +	+0XF8006020 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters register 3 +
+ +DRAM_param_reg4 + +	+0XF8006024 +	+32 +	+RW +	+0x000000 +	+DRAM Parameters register 4 +
+ +DRAM_init_param + +	+0XF8006028 +	+32 +	+RW +	+0x000000 +	+DRAM initialization parameters register +
+ +DRAM_EMR_reg + +	+0XF800602C +	+32 +	+RW +	+0x000000 +	+DRAM EMR2, EMR3 access register +
+ +DRAM_EMR_MR_reg + +	+0XF8006030 +	+32 +	+RW +	+0x000000 +	+DRAM EMR, MR access register +
+ +DRAM_burst8_rdwr + +	+0XF8006034 +	+32 +	+RW +	+0x000000 +	+DRAM burst 8 read/write register +
+ +DRAM_disable_DQ + +	+0XF8006038 +	+32 +	+RW +	+0x000000 +	+DRAM Disable DQ register +
+ +DRAM_addr_map_bank + +	+0XF800603C +	+32 +	+RW +	+0x000000 +	+Selects the address bits used as DRAM bank address bits +
+ +DRAM_addr_map_col + +	+0XF8006040 +	+32 +	+RW +	+0x000000 +	+Selects the address bits used as DRAM column address bits +
+ +DRAM_addr_map_row + +	+0XF8006044 +	+32 +	+RW +	+0x000000 +	+Selects the address bits used as DRAM row address bits +
+ +DRAM_ODT_reg + +	+0XF8006048 +	+32 +	+RW +	+0x000000 +	+DRAM ODT register +
+ +phy_cmd_timeout_rddata_cpt + +	+0XF8006050 +	+32 +	+RW +	+0x000000 +	+PHY command time out and read data capture FIFO register +
+ +DLL_calib + +	+0XF8006058 +	+32 +	+RW +	+0x000000 +	+DLL calibration register +
+ +ODT_delay_hold + +	+0XF800605C +	+32 +	+RW +	+0x000000 +	+ODT delay and ODT hold register +
+ +ctrl_reg1 + +	+0XF8006060 +	+32 +	+RW +	+0x000000 +	+Controller register 1 +
+ +ctrl_reg2 + +	+0XF8006064 +	+32 +	+RW +	+0x000000 +	+Controller register 2 +
+ +ctrl_reg3 + +	+0XF8006068 +	+32 +	+RW +	+0x000000 +	+Controller register 3 +
+ +ctrl_reg4 + +	+0XF800606C +	+32 +	+RW +	+0x000000 +	+Controller register 4 +
+ +CHE_REFRESH_TIMER01 + +	+0XF80060A0 +	+32 +	+RW +	+0x000000 +	+CHE_REFRESH_TIMER01 +
+ +CHE_T_ZQ + +	+0XF80060A4 +	+32 +	+RW +	+0x000000 +	+ZQ parameters register +
+ +CHE_T_ZQ_Short_Interval_Reg + +	+0XF80060A8 +	+32 +	+RW +	+0x000000 +	+Misc parameters register +
+ +deep_pwrdwn_reg + +	+0XF80060AC +	+32 +	+RW +	+0x000000 +	+Deep powerdown register +
+ +reg_2c + +	+0XF80060B0 +	+32 +	+RW +	+0x000000 +	+Training control register +
+ +reg_2d + +	+0XF80060B4 +	+32 +	+RW +	+0x000000 +	+Misc Debug register +
+ +dfi_timing + +	+0XF80060B8 +	+32 +	+RW +	+0x000000 +	+DFI timing register +
+ +CHE_ECC_CONTROL_REG_OFFSET + +	+0XF80060C4 +	+32 +	+RW +	+0x000000 +	+ECC error clear register +
+ +CHE_ECC_CONTROL_REG_OFFSET + +	+0XF80060C4 +	+32 +	+RW +	+0x000000 +	+ECC error clear register +
+ +CHE_CORR_ECC_LOG_REG_OFFSET + +	+0XF80060C8 +	+32 +	+RW +	+0x000000 +	+ECC error correction register +
+ +CHE_UNCORR_ECC_LOG_REG_OFFSET + +	+0XF80060DC +	+32 +	+RW +	+0x000000 +	+ECC unrecoverable error status register +
+ +CHE_ECC_STATS_REG_OFFSET + +	+0XF80060F0 +	+32 +	+RW +	+0x000000 +	+ECC error count register +
+ +ECC_scrub + +	+0XF80060F4 +	+32 +	+RW +	+0x000000 +	+ECC mode/scrub register +
+ +phy_rcvr_enable + +	+0XF8006114 +	+32 +	+RW +	+0x000000 +	+Phy receiver enable register +
+ +PHY_Config + +	+0XF8006118 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config + +	+0XF800611C +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config + +	+0XF8006120 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +PHY_Config + +	+0XF8006124 +	+32 +	+RW +	+0x000000 +	+PHY configuration register for data slice 0. +
+ +phy_init_ratio + +	+0XF800612C +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio + +	+0XF8006130 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio + +	+0XF8006134 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_init_ratio + +	+0XF8006138 +	+32 +	+RW +	+0x000000 +	+PHY init ratio register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF8006140 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF8006144 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF8006148 +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_rd_dqs_cfg + +	+0XF800614C +	+32 +	+RW +	+0x000000 +	+PHY read DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF8006154 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF8006158 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF800615C +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_wr_dqs_cfg + +	+0XF8006160 +	+32 +	+RW +	+0x000000 +	+PHY write DQS configuration register for data slice 0. +
+ +phy_we_cfg + +	+0XF8006168 +	+32 +	+RW +	+0x000000 +	+PHY fifo write enable configuration register for data slice 0. +
+ +phy_we_cfg + +	+0XF800616C +	+32 +	+RW +	+0x000000 +	+PHY fifo write enable configuration register for data slice 0. +
+ +phy_we_cfg + +	+0XF8006170 +	+32 +	+RW +	+0x000000 +	+PHY fifo write enable configuration register for data slice 0. +
+ +phy_we_cfg + +	+0XF8006174 +	+32 +	+RW +	+0x000000 +	+PHY fifo write enable configuration register for data slice 0. +
+ +wr_data_slv + +	+0XF800617C +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio configuration register for data slice 0. +
+ +wr_data_slv + +	+0XF8006180 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio configuration register for data slice 0. +
+ +wr_data_slv + +	+0XF8006184 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio configuration register for data slice 0. +
+ +wr_data_slv + +	+0XF8006188 +	+32 +	+RW +	+0x000000 +	+PHY write data slave ratio configuration register for data slice 0. +
+ +reg_64 + +	+0XF8006190 +	+32 +	+RW +	+0x000000 +	+Training control register (2) +
+ +reg_65 + +	+0XF8006194 +	+32 +	+RW +	+0x000000 +	+Training control register (3) +
+ +page_mask + +	+0XF8006204 +	+32 +	+RW +	+0x000000 +	+Page mask register +
+ +axi_priority_wr_port + +	+0XF8006208 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port + +	+0XF800620C +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port + +	+0XF8006210 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_wr_port + +	+0XF8006214 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for write port 0. +
+ +axi_priority_rd_port + +	+0XF8006218 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port + +	+0XF800621C +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port + +	+0XF8006220 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +axi_priority_rd_port + +	+0XF8006224 +	+32 +	+RW +	+0x000000 +	+AXI Priority control for read port 0. +
+ +lpddr_ctrl0 + +	+0XF80062A8 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 0 Register +
+ +lpddr_ctrl1 + +	+0XF80062AC +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 1 Register +
+ +lpddr_ctrl2 + +	+0XF80062B0 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 2 Register +
+ +lpddr_ctrl3 + +	+0XF80062B4 +	+32 +	+RW +	+0x000000 +	+LPDDR2 Control 3 Register +
+ +ddrc_ctrl + +	+0XF8006000 +	+32 +	+RW +	+0x000000 +	+DDRC Control Register +

ps7_ddr_init_data_1_0

+ + + + + + + + + +

DDR INITIALIZATION

LOCK DDR

Register ( slcr )ddrc_ctrl

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ddrc_ctrl +	+0XF8006000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +0 + +0 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +80 + +DDRC Control Register +
+

Register ( slcr )Two_rank_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Two_rank_cfg +	+0XF8006004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rfc_nom_x32 + +11:0 + +fff + +81 + +81 + +tREFI - Average time between refreshes. Unit: in multiples of 32 clocks. DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_active_ranks + +13:12 + +3000 + +1 + +1000 + +Only present for multi-rank configurations. Each bit represents one rank. 1=populated; 0=unpopulated 01 = One Rank 11 = Two Ranks Others = Reserved +
+reg_ddrc_addrmap_cs_bit0 + +18:14 + +7c000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 0. Valid Range: 0 to 25, and 31 Internal Base: 9. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 0 is set to 0. +
+reg_ddrc_wr_odt_block + +20:19 + +180000 + +1 + +80000 + +00 = block read/write scheduling for 1-cycle when Write requires changing ODT settings 01 = block read/write scheduling for 2 cycles when Write requires changing ODT settings 10 = block read/write scheduling for 3 cycles when Write requires changing ODT settings 11 = Reserved +
+reg_ddrc_diff_rank_rd_2cycle_gap + +21:21 + +200000 + +0 + +0 + +Only present for multi-rank configurations. The two cycle gap is required for mDDR only, due to the large variance in tDQSCK in mDDR. 0 = schedule a 1-cycle gap in data responses when performing consecutive reads to different ranks 1 = schedule 2 cycle gap for the same +
+reg_ddrc_addrmap_cs_bit1 + +26:22 + +7c00000 + +0 + +0 + +Only present for multi-rank configurations. Selects the address bit used as rank address bit 1. Valid Range: 0 to 25, and 31 Internal Base: 10 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 31, rank address bit 1 is set to 0. +
+reg_ddrc_addrmap_open_bank + +27:27 + +8000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map to Open Bank mode +
+reg_ddrc_addrmap_4bank_ram + +28:28 + +10000000 + +0 + +0 + +Only present if MEMC_SIMPLE_ADDR_MAP is defined. Since MEMC_SIMPLE_ADDR_MAP is not defined, Reserved 1 = Set the address map for 4 Bank RAMs +
+Two_rank_cfg@0XF8006004 + +31:0 + +1fffffff + + + +81081 + +Two rank configuration register +
+

Register ( slcr )HPR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+HPR_reg +	+0XF8006008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_hpr_min_non_critical_x32 + +10:0 + +7ff + +f + +f + +Number of clocks that the HPR queue is guaranteed to be non-critical. Unit: 32 clocks +
+reg_ddrc_hpr_max_starve_x32 + +21:11 + +3ff800 + +f + +7800 + +Number of clocks that the HPR queue can be starved before it goes critical. Unit: 32 clocks +
+reg_ddrc_hpr_xact_run_length + +25:22 + +3c00000 + +f + +3c00000 + +Number of transactions that will be serviced once the HPR queue goes critical is the smaller of this number and the number of transactions available. +
+HPR_reg@0XF8006008 + +31:0 + +3ffffff + + + +3c0780f + +HPR Queue control register +
+

Register ( slcr )LPR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LPR_reg +	+0XF800600C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )WR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+WR_reg +	+0XF8006010 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DRAM_param_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg0 +	+0XF8006014 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_rc + +5:0 + +3f + +1b + +1b + +tRC - Min time between activates to same bank (spec: 65 ns for DDR2-400 and smaller for faster parts). DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_t_rfc_min + +13:6 + +3fc0 + +56 + +1580 + +tRFC(min) - Minimum time from refresh to refresh or activate (spec: 75ns to 195ns). DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_post_selfref_gap_x32 + +20:14 + +1fc000 + +10 + +40000 + +Minimum time to wait after coming out of self refresh before doing anything. This must be bigger than all the constraints that exist. (spec: Maximum of tXSNR and tXSRD and tXSDLL which is 512 clocks). Unit: in multiples of 32 clocks DRAM RELATED +
+DRAM_param_reg0@0XF8006014 + +31:0 + +1fffff + + + +4159b + +DRAM Parameters register 0 +
+

Register ( slcr )DRAM_param_reg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg1 +	+0XF8006018 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wr2pre + +4:0 + +1f + +12 + +12 + +Minimum time between write and precharge to same bank Non-LPDDR2 -> WL + BL/2 + tWR LPDDR2 -> WL + BL/2 + tWR + 1 Unit: Clocks where, WL = write latency. BL = burst length. This must match the value programmed in the BL bit of the mode register to the DRAM. BST is not supported at present. tWR = write recovery time. This comes directly from the DRAM specs. +
+reg_ddrc_powerdown_to_x32 + +9:5 + +3e0 + +6 + +c0 + +After this many clocks of NOP or DESELECT the controller will put the DRAM into power down. This must be enabled in the Master Control Register. Unit: Multiples of 32 clocks. +
+reg_ddrc_t_faw + +15:10 + +fc00 + +10 + +4000 + +tFAW - At most 4 banks must be activated in a rolling window of tFAW cycles. Unit: clocks DRAM RELATED. +
+reg_ddrc_t_ras_max + +21:16 + +3f0000 + +24 + +240000 + +tRAS(max) - Maximum time between activate and precharge to same bank. Maximum time that a page can be kept open (spec: 70 us). If this is zero. The page is closed after each transaction. Unit: Multiples of 1024 clocks DRAM RELATED. +
+reg_ddrc_t_ras_min + +26:22 + +7c00000 + +14 + +5000000 + +tRAS(min) - Minimum time between activate and precharge to the same bank(spec: 45 ns). Unit: clocks DRAM RELATED. Default value is set for DDR3. +
+reg_ddrc_t_cke + +31:28 + +f0000000 + +4 + +40000000 + +Minimum number of cycles of CKE HIGH/LOW during power down and self refresh. LPDDR2 mode: Set this to the larger of tCKE or tCKESR. Non-LPDDR2 designs: Set this to tCKE value. Unit: clocks. +
+DRAM_param_reg1@0XF8006018 + +31:0 + +f7ffffff + + + +452440d2 + +DRAM Parameters register 1 +
+

Register ( slcr )DRAM_param_reg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg2 +	+0XF800601C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_write_latency + +4:0 + +1f + +5 + +5 + +Time from write command to write data on DDRC to PHY Interface. (PHY adds an extra flop delay on the write data path; hence this value is one less than the write latency of the DRAM device itself). DDR2/3 -> WL -1 LPDDR -> 1 LPDDR2 ->WL Where WL = Write Latency of DRAM DRAM RELATED. +
+reg_ddrc_rd2wr + +9:5 + +3e0 + +7 + +e0 + +Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints. non-LPDDR2 -> RL + BL/2 + 2 - WL LPDDR2 -> RL + BL/2 + RU(tDQSCKmax / tCK) + 1 - WL Write Pre-amble and DQ/DQS jitter timer is included in the above equation. DRAM RELATED. +
+reg_ddrc_wr2rd + +14:10 + +7c00 + +e + +3800 + +Minimum time from write command to read command. Includes time for bus turnaround and recovery times and all per-bank, per-rank, and global constraints. non-LPDDR2 -> WL + tWTR + BL/2 LPDDR2 -> WL + tWTR + BL/2 + 1 Unit: clocks. Where, WL = Write latency, BL = burst length. This should match the value. Programmed in the BL bit of the mode register to the DRAM. tWTR = internal WRITE to READ command delay. This comes directly from the DRAM specs. +
+reg_ddrc_t_xp + +19:15 + +f8000 + +4 + +20000 + +tXP: Minimum time after power down exit to any operation. DRAM RELATED. +
+reg_ddrc_pad_pd + +22:20 + +700000 + +0 + +0 + +If pads have a power-saving mode, this is the greater of the time for the pads to enter power down or the time for the pads to exit power down. Used only in non-DFI designs. Unit: clocks. +
+reg_ddrc_rd2pre + +27:23 + +f800000 + +4 + +2000000 + +Minimum time from read to precharge of same bank DDR2 -> AL + BL/2 + max(tRTP, 2) - 2 DDR3 -> AL + max (tRTP, 4) mDDR -> BL/2 LPDDR2 -> BL/2 + tRTP - 1 AL = Additive Latency BL = DRAM Burst Length tRTP = value from spec DRAM RELATED +
+reg_ddrc_t_rcd + +31:28 + +f0000000 + +7 + +70000000 + +tRCD - AL Minimum time from activate to read or write command to same bank Min value for this is 1. AL = Additive Latency DRAM RELATED +
+DRAM_param_reg2@0XF800601C + +31:0 + +ffffffff + + + +720238e5 + +DRAM Parameters register 2 +
+

Register ( slcr )DRAM_param_reg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg3 +	+0XF8006020 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_t_ccd + +4:2 + +1c + +4 + +10 + +tCCD - Minimum time between two reads or two writes (from bank a to bank b) is this value + 1 DRAM RELATED +
+reg_ddrc_t_rrd + +7:5 + +e0 + +4 + +80 + +tRRD - Minimum time between activates from bank a to bank b. (spec: 10ns or less) DRAM RELATED +
+reg_ddrc_refresh_margin + +11:8 + +f00 + +2 + +200 + +Issue critical refresh or page close this many cycles before the critical refresh or page timer expires. It is recommended that this not be changed from the default value. +
+reg_ddrc_t_rp + +15:12 + +f000 + +7 + +7000 + +tRP - Minimum time from precharge to activate of same bank. DRAM RELATED +
+reg_ddrc_refresh_to_x32 + +20:16 + +1f0000 + +8 + +80000 + +If the refresh timer (tRFC_nom, as known as tREFI) has expired at least once, but it has not expired burst_of_N_refresh times yet, then a 'speculative refresh' may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful, but before it is absolutely required. When the DRAM bus is idle for a period of time determined by this refresh idle timeout and the refresh timer has expired at least once since the last refresh, then a 'speculative refresh' will be performed. Speculative refreshes will continue successively until there are no refreshes pending or until new reads or writes are issued to the controller. +
+reg_ddrc_sdram + +21:21 + +200000 + +1 + +200000 + +1 = sdram device 0 = non-sdram device +
+reg_ddrc_mobile + +22:22 + +400000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-mobile DRAM device in use. +
+reg_ddrc_clock_stop_en + +23:23 + +800000 + +0 + +0 + +1=enable the assertion of stop_clk to the PHY whenever a clock is not required by LPDDR/ LPDDR2. 0=stop_clk will never be asserted. Note: This is only present for implementations supporting LPDDR/LPDDR2 devices. +
+reg_ddrc_read_latency + +28:24 + +1f000000 + +7 + +7000000 + +Set to RL. Time from Read command to Read data on DRAM interface. Unit: clocks This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. RL = Read Latency of DRAM Note: This signal is present for designs supporting LPDDR/LPDDR2 DRAM only. It is used to calculate when DRAM clock may be stopped. +
+reg_phy_mode_ddr1_ddr2 + +29:29 + +20000000 + +1 + +20000000 + +unused +
+reg_ddrc_dis_pad_pd + +30:30 + +40000000 + +0 + +0 + +1 = disable the pad power down feature 0 = Enable the pad power down feature. +
+reg_ddrc_loopback + +31:31 + +80000000 + +0 + +0 + +unused +
+DRAM_param_reg3@0XF8006020 + +31:0 + +fffffffc + + + +27287290 + +DRAM Parameters register 3 +
+

Register ( slcr )DRAM_param_reg4

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_param_reg4 +	+0XF8006024 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_en_2t_timing_mode + +0:0 + +1 + +0 + +0 + +1 = DDRC will use 2T timing 0 = DDRC will use 1T timing +
+reg_ddrc_prefer_write + +1:1 + +2 + +0 + +0 + +1 = Bank selector prefers writes over reads +
+reg_ddrc_max_rank_rd + +5:2 + +3c + +f + +3c + +Only present for multi-rank configurations Background: Reads to the same rank can be performed back-to-back. Reads from different ranks require additional 1-cycle latency in between (to avoid possible data bus contention). The controller arbitrates for bus access on a cycle-by-cycle basis; therefore after a read is scheduled, there is a clock cycle in which only reads from the same bank are eligible to be scheduled. This prevents reads from other ranks from having fair access to the data bus. This parameter represents the maximum number of 64-byte reads (or 32B reads in some short read cases) that can be scheduled consecutively to the same rank. After this number is reached, a 1-cycle delay is inserted by the scheduler to allow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness (and hence worst-case latency). FOR PERFORMANCE ONLY. +
+reg_ddrc_mr_wr + +6:6 + +40 + +0 + +0 + +A low to high signal on this signal will do a mode register write or read. Controller will accept this command, if this signal is detected high and 'ddrc_reg_mr_wr_busy' is detected low. +
+reg_ddrc_mr_addr + +8:7 + +180 + +0 + +0 + +Mode register address - for non-LPDDR2 modes. This register is don't care in LPDDR2 mode 00 = MR0 01 = MR1 10 = MR2 11 = MR3 +
+reg_ddrc_mr_data + +24:9 + +1fffe00 + +0 + +0 + +Mode register write data - for non-LPDDR2 modes. For LPDDR2, these 16-bits are interpreted as Writes: \'7bMR Addr[7:0], MR Data[7:0]\'7d. Reads: \'7bMR Addr[7:0], Don't Care[7:0]\'7d +
+ddrc_reg_mr_wr_busy + +25:25 + +2000000 + +0 + +0 + +Core must initiate a MR write / read operation only if this signal is low. This signal goes high in the clock after the controller accepts the write / read request. It goes low when (i) MR write command has been issued to the DRAM (ii) MR Read data has been returned to Controller. Any MR write / read command that is received when 'ddrc_reg_mr_wr_busy' is high is not accepted. 1 = Indicates that mode register write / read operation is in progress. 0 = Indicates that the core can initiate a mode register write / read operation. +
+reg_ddrc_mr_type + +26:26 + +4000000 + +0 + +0 + +Indicates whether the Mode register operation is read or write 1 = read 0 = write +
+reg_ddrc_mr_rdata_valid + +27:27 + +8000000 + +0 + +0 + +This bit indicates whether the Mode Register Read Data present at address 0xA9 is valid or not. This bit is 1'b0 by default. This bit will be cleared (1'b0), whenever a Mode Register Read command is issued. This bit will be set to 1'b1, when the Mode Register Read Data is written to register 0xA9. +
+DRAM_param_reg4@0XF8006024 + +31:0 + +fffffff + + + +3c + +DRAM Parameters register 4 +
+

Register ( slcr )DRAM_init_param

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_init_param +	+0XF8006028 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_final_wait_x32 + +6:0 + +7f + +7 + +7 + +Cycles to wait after completing the DRAM init sequence before starting the dynamic scheduler. Units are in counts of a global timer that pulses every 32 clock cycles. Default value is set for DDR3. +
+reg_ddrc_pre_ocd_x32 + +10:7 + +780 + +0 + +0 + +Wait period before driving the 'OCD Complete' command to DRAM. Units are in counts of a global timer that pulses every 32 clock cycles. There is no known spec requirement for this. It may be set to zero. +
+reg_ddrc_t_mrd + +13:11 + +3800 + +4 + +2000 + +tMRD - Cycles between Load Mode commands DRAM RELATED Default value is set for DDR3. +
+DRAM_init_param@0XF8006028 + +31:0 + +3fff + + + +2007 + +DRAM initialization parameters register +
+

Register ( slcr )DRAM_EMR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_EMR_reg +	+0XF800602C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_emr2 + +15:0 + +ffff + +8 + +8 + +Non LPDDR2- Value to be loaded into DRAM EMR2 registers. For LPDDR2 - Value to Write to the MR3 register +
+reg_ddrc_emr3 + +31:16 + +ffff0000 + +0 + +0 + +Non LPDDR2- Value to be loaded into DRAM EMR3 registers. Used in non-LPDDR2 designs only. +
+DRAM_EMR_reg@0XF800602C + +31:0 + +ffffffff + + + +8 + +DRAM EMR2, EMR3 access register +
+

Register ( slcr )DRAM_EMR_MR_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_EMR_MR_reg +	+0XF8006030 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr + +15:0 + +ffff + +930 + +930 + +Non LPDDR2-Value to be loaded into the DRAM Mode register. Bit 8 is for DLL and the setting here is ignored. The controller sets appropriately. For LPDDR2 - Value to Write to the MR1 register +
+reg_ddrc_emr + +31:16 + +ffff0000 + +4 + +40000 + +Non LPDDR2-Value to be loaded into DRAM EMR registers. Bits [9:7] are for OCD and the setting in this register is ignored. The controller sets those bits appropriately. For LPDDR2 - Value to Write to the MR2 register +
+DRAM_EMR_MR_reg@0XF8006030 + +31:0 + +ffffffff + + + +40930 + +DRAM EMR, MR access register +
+

Register ( slcr )DRAM_burst8_rdwr

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_burst8_rdwr +	+0XF8006034 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_burst_rdwr + +3:0 + +f + +4 + +4 + +This controls the burst size used to access the DRAM. This must match the BL mode register setting in the DRAM. In LPDDR and LPDDR2, Burst length of 16 is supported only in Half Bus Width mode. Every input read/write command has 4 cycles of data associated with it and that is not enough data for doing Burst Length16 in Full Bus Width mode. 0010 - Burst length of 4 0100 - Burst length of 8 1000 - Burst length of 16 (only supported for LPDDR AND LPDDR2) All other values are reserved +
+reg_ddrc_pre_cke_x1024 + +13:4 + +3ff0 + +105 + +1050 + +Cycles to wait after reset before driving CKE high to start the DRAM initialization sequence. Units: 1024 clock cycles. DDR2 Specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2 - tINIT0 of 20 ms (max) + tINIT1 of 100 ns (min) +
+reg_ddrc_post_cke_x1024 + +25:16 + +3ff0000 + +1 + +10000 + +Cycles to wait after driving CKE high to start the DRAM initialization sequence. Units: 1024 clocks. DDR2 typically require a 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2 - Typically require this to be programmed for a delay of 200 us. +
+reg_ddrc_burstchop + +28:28 + +10000000 + +0 + +0 + +Feature not supported. When 1, Controller is out in burstchop mode. +
+DRAM_burst8_rdwr@0XF8006034 + +31:0 + +13ff3fff + + + +11054 + +DRAM burst 8 read/write register +
+

Register ( slcr )DRAM_disable_DQ

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_disable_DQ +	+0XF8006038 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_force_low_pri_n + +0:0 + +1 + +0 + +0 + +Active Low signal. When asserted (0), all incoming transactions will be forced to low priority. Forcing the incoming transactions to low priority implicitly turns OFF Bypass. Otherwise, HPR is allowed if enabled in the AXI priority read registers. +
+reg_ddrc_dis_dq + +1:1 + +2 + +0 + +0 + +When 1, DDRC will not de-queue any transactions from the CAM. Bypass will also be disabled. All transactions will be queued in the CAM. This is for debug only; no reads or writes are issued to DRAM as long as this is asserted. This bit is intended to be switched on-the-fly +
+reg_phy_debug_mode + +6:6 + +40 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_wr_level_start + +7:7 + +80 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_rd_level_start + +8:8 + +100 + +0 + +0 + +Not Applicable in this PHY. +
+reg_phy_dq0_wait_t + +12:9 + +1e00 + +0 + +0 + +Not Applicable in this PHY. +
+DRAM_disable_DQ@0XF8006038 + +31:0 + +1fc3 + + + +0 + +DRAM Disable DQ register +
+

Register ( slcr )DRAM_addr_map_bank

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_bank +	+0XF800603C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_bank_b0 + +3:0 + +f + +7 + +7 + +Selects the address bits used as bank address bit 0. Valid Range: 0 to 14 Internal Base: 5 The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b1 + +7:4 + +f0 + +7 + +70 + +Selects the address bits used as bank address bit 1. Valid Range: 0 to 14; Internal Base: 6. The selected address bit for each of the bank address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_bank_b2 + +11:8 + +f00 + +7 + +700 + +Selects the AXI address bit used as bank address bit 2. Valid range 0 to 14, and 15. Internal Base: 7. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, bank address bit 2 is set to 0. +
+reg_ddrc_addrmap_col_b5 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 6. Half bus width mode: Selects the address bits used as column address bits 7. Valid range is 0-7. Internal Base 8. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+reg_ddrc_addrmap_col_b6 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bits used as column address bits 7. Half bus width mode: Selects the address bits used as column address bits 8. Valid range is 0-7. Internal Base 9. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. Internal base: 9 +
+DRAM_addr_map_bank@0XF800603C + +31:0 + +fffff + + + +777 + +Selects the address bits used as DRAM bank address bits +
+

Register ( slcr )DRAM_addr_map_col

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_col +	+0XF8006040 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_col_b2 + +3:0 + +f + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 3. Half bus width mode: Selects the address bit used as column address bit 4. Valid Range: 0 to 7. Internal Base: 5 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b3 + +7:4 + +f0 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 4. Half bus width mode: Selects the address bit used as column address bit 5. Valid Range: 0 to 7 Internal Base: 6 The selected address bit is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b4 + +11:8 + +f00 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 5. Half bus width mode: Selects the address bit used as column address bits 6. Valid Range: 0 to 7. Internal Base: 7. The selected address bit for each of the column address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_col_b7 + +15:12 + +f000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 8. Half bus width mode: Selects the address bit used as column address bit 9. Valid Range: 0 to 7, and 15. Internal Base: 10. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10.In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b8 + +19:16 + +f0000 + +0 + +0 + +Full bus width mode: Selects the address bit used as column address bit 9. Half bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 11 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b9 + +23:20 + +f00000 + +f + +f00000 + +Full bus width mode: Selects the address bit used as column address bit 11. (Column address bit 10 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Valid Range: 0 to 7, and 15 Internal Base: 12 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b10 + +27:24 + +f000000 + +f + +f000000 + +Full bus width mode: Selects the address bit used as column address bit 12. (Column address bit 11 in LPDDR2 mode) Half bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 13 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+reg_ddrc_addrmap_col_b11 + +31:28 + +f0000000 + +f + +f0000000 + +Full bus width mode: Selects the address bit used as column address bit 13. (Column address bit 12 in LPDDR2 mode) Half bus width mode: Unused. To make it unused, this should be set to 15. (Column address bit 13 in LPDDR2 mode) Valid Range: 0 to 7, and 15. Internal Base: 14. The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2 spec, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column address bit 10. In LPDDR2, there is a dedicated bit for auto-precharge in the CA bus, and hence column bit 10 is used. +
+DRAM_addr_map_col@0XF8006040 + +31:0 + +ffffffff + + + +fff00000 + +Selects the address bits used as DRAM column address bits +
+

Register ( slcr )DRAM_addr_map_row

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_addr_map_row +	+0XF8006044 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_addrmap_row_b0 + +3:0 + +f + +6 + +6 + +Selects the AXI address bits used as row address bit 0. Valid Range: 0 to 11. Internal Base: 9 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field +
+reg_ddrc_addrmap_row_b1 + +7:4 + +f0 + +6 + +60 + +Selects the AXI address bits used as row address bit 1. Valid Range: 0 to 11. Internal Base: 10 The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b2_11 + +11:8 + +f00 + +6 + +600 + +Selects the AXI address bits used as row address bits 2 to 11. Valid Range: 0 to 11. Internal Base: 11 (for row address bit 2) to 20 (for row address bit 11) The selected address bit for each of the row address bits is determined by adding the Internal Base to the value of this field. +
+reg_ddrc_addrmap_row_b12 + +15:12 + +f000 + +6 + +6000 + +Selects the AXI address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 12 is set to 0. +
+reg_ddrc_addrmap_row_b13 + +19:16 + +f0000 + +6 + +60000 + +Selects the AXI address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 13 is set to 0. +
+reg_ddrc_addrmap_row_b14 + +23:20 + +f00000 + +6 + +600000 + +Selects theAXI address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 23 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 14 is set to 0. +
+reg_ddrc_addrmap_row_b15 + +27:24 + +f000000 + +f + +f000000 + +Selects the AXI address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 24 The selected address bit is determined by adding the Internal Base to the value of this field. If set to 15, row address bit 15 is set to 0. +
+DRAM_addr_map_row@0XF8006044 + +31:0 + +fffffff + + + +f666666 + +Selects the address bits used as DRAM row address bits +
+

Register ( slcr )DRAM_ODT_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DRAM_ODT_reg +	+0XF8006048 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rank0_rd_odt + +2:0 + +7 + +0 + +0 + +Unused. [1:0] - Indicates which remote ODT's must be turned ON during a read to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during reads to rank 0. +
+reg_ddrc_rank0_wr_odt + +5:3 + +38 + +1 + +8 + +[1:0] - Indicates which remote ODT's must be turned on during a write to rank 0. Each of the 2 ranks has a remote ODT (in the DRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; Rank 1 is controlled by bit next to the LSB. For each rank, set its bit to 1 to enable its ODT. [2] - If 1 then local ODT is enabled during writes to rank 0. +
+reg_ddrc_rank1_rd_odt + +8:6 + +1c0 + +1 + +40 + +Unused +
+reg_ddrc_rank1_wr_odt + +11:9 + +e00 + +1 + +200 + +Unused +
+reg_phy_rd_local_odt + +13:12 + +3000 + +0 + +0 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is in progress (where 'in progress' is defined as after a read command is issued and until all read data has been returned all the way to the controller.) Typically this is set to the value required to enable termination at the desired strength for read usage. +
+reg_phy_wr_local_odt + +15:14 + +c000 + +3 + +c000 + +Value to drive on the 2-bit local_odt PHY outputs when write levelling is enabled for DQS. +
+reg_phy_idle_local_odt + +17:16 + +30000 + +3 + +30000 + +Value to drive on the 2-bit local_odt PHY outputs when output enable is not asserted and a read is not in progress. Typically this is the value required to disable termination to save power when idle. +
+reg_ddrc_rank2_rd_odt + +20:18 + +1c0000 + +0 + +0 + +Unused +
+reg_ddrc_rank2_wr_odt + +23:21 + +e00000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_rd_odt + +26:24 + +7000000 + +0 + +0 + +Unused +
+reg_ddrc_rank3_wr_odt + +29:27 + +38000000 + +0 + +0 + +Unused +
+DRAM_ODT_reg@0XF8006048 + +31:0 + +3fffffff + + + +3c248 + +DRAM ODT register +
+

Register ( slcr )phy_cmd_timeout_rddata_cpt

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_cmd_timeout_rddata_cpt +	+0XF8006050 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_cmd_to_data + +3:0 + +f + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_wr_cmd_to_data + +7:4 + +f0 + +0 + +0 + +Not used in DFI PHY. +
+reg_phy_rdc_we_to_re_delay + +11:8 + +f00 + +8 + +800 + +This register value + 1 give the number of clock cycles between writing into the Read Capture FIFO and the read operation. The setting of this register determines the read data timing and depends upon total delay in the system for read operation which include fly-by delays, trace delay, clkout_invert etc. This is used only if reg_phy_use_fixed_re=1. +
+reg_phy_rdc_fifo_rst_disable + +15:15 + +8000 + +0 + +0 + +When 1, disable counting the number of times the Read Data Capture FIFO has been reset when the FIFO was not empty. +
+reg_phy_use_fixed_re + +16:16 + +10000 + +1 + +10000 + +When 1: PHY generates FIFO read enable after fixed number of clock cycles as defined by reg_phy_rdc_we_to_re_delay[3:0]. When 0: PHY uses the not_empty method to do the read enable generation. Note: This port must be set HIGH during training/leveling process i.e. when ddrc_dfi_wrlvl_en/ ddrc_dfi_rdlvl_en/ ddrc_dfi_rdlvl_gate_en port is set HIGH. +
+reg_phy_rdc_fifo_rst_err_cnt_clr + +17:17 + +20000 + +0 + +0 + +Clear/reset for counter rdc_fifo_rst_err_cnt[3:0]. 0: no clear, 1: clear. Note: This is a synchronous dynamic signal that must have timing closed. +
+reg_phy_dis_phy_ctrl_rstn + +18:18 + +40000 + +0 + +0 + +Disable the reset from Phy Ctrl macro. 1: PHY Ctrl macro reset port is always HIGH 0: PHY Ctrl macro gets power on reset. +
+reg_phy_clk_stall_level + +19:19 + +80000 + +0 + +0 + +1 = stall clock, for DLL aging control +
+reg_phy_gatelvl_num_of_dq0 + +27:24 + +f000000 + +7 + +7000000 + +This register value determines register determines the number of samples used for each ratio increment during Gate Training. Num_of_iteration = reg_phy_gatelvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+reg_phy_wrlvl_num_of_dq0 + +31:28 + +f0000000 + +7 + +70000000 + +This register value determines register determines the number of samples used for each ratio increment during Write Leveling. Num_of_iteration = reg_phy_wrlvl_num_of_dq0 + 1 The recommended value for this register is 8. Accuracy is better with higher value, but this will cause leveling to run longer. +
+phy_cmd_timeout_rddata_cpt@0XF8006050 + +31:0 + +ff0f8fff + + + +77010800 + +PHY command time out and read data capture FIFO register +
+

Register ( slcr )DLL_calib

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DLL_calib +	+0XF8006058 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )ODT_delay_hold

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ODT_delay_hold +	+0XF800605C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_rd_odt_delay + +3:0 + +f + +3 + +3 + +UNUSED +
+reg_ddrc_wr_odt_delay + +7:4 + +f0 + +0 + +0 + +The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting should remain constant for the entire time that DQS is driven by the controller. The suggested value for DDR2 is WL - 5 and for DDR3 is 0. WL is Write latency. DDR2 ODT has a 2-cycle on-time delay and a 2.5-cycle off-time delay. ODT is not applicable for LPDDR and LPDDR2 modes. +
+reg_ddrc_rd_odt_hold + +11:8 + +f00 + +0 + +0 + +Unused +
+reg_ddrc_wr_odt_hold + +15:12 + +f000 + +5 + +5000 + +Cycles to hold ODT for a Write Command. When 0x0, ODT signal is ON for 1 cycle. When 0x1, it is ON for 2 cycles, etc. The values to program in different modes are : DRAM Burst of 4 -2, DRAM Burst of 8 -4 +
+ODT_delay_hold@0XF800605C + +31:0 + +ffff + + + +5003 + +ODT delay and ODT hold register +
+

Register ( slcr )ctrl_reg1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg1 +	+0XF8006060 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_pageclose + +0:0 + +1 + +0 + +0 + +If true, bank will be closed and kept closed if no transactions are available for it. If false, bank will remain open until there is a need to close it (to open a different page, or for page timeout or refresh timeout.) This does not apply when auto-refresh is used. +
+reg_ddrc_lpr_num_entries + +6:1 + +7e + +1f + +3e + +Number of entries in the low priority transaction store is this value plus 1. In this design, by default all read ports are treated as low priority and hence the value of 0x1F. The hpr_num_entries is 32 minus this value. Bit [6] is ignored. +
+reg_ddrc_auto_pre_en + +7:7 + +80 + +0 + +0 + +When set, most reads and writes will be issued with auto-precharge. (Exceptions can be made for collision cases.) +
+reg_ddrc_refresh_update_level + +8:8 + +100 + +0 + +0 + +Toggle this signal to indicate that refresh register(s) have been updated. The value will be automatically updated when exiting soft reset. So it does not need to be toggled initially. +
+reg_ddrc_dis_wc + +9:9 + +200 + +0 + +0 + +When 1, disable Write Combine +
+reg_ddrc_dis_collision_page_opt + +10:10 + +400 + +0 + +0 + +When this is set to '0', auto-precharge will be disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DIS_WC bit = 1 (where 'same address' comparisons exclude the two address bits representing critical word). +
+reg_ddrc_selfref_en + +12:12 + +1000 + +0 + +0 + +If 1, then the controller will put the DRAM into self refresh when the transaction store is empty. +
+ctrl_reg1@0XF8006060 + +31:0 + +17ff + + + +3e + +Controller register 1 +
+

Register ( slcr )ctrl_reg2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg2 +	+0XF8006064 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_go2critical_hysteresis + +12:5 + +1fe0 + +0 + +0 + +Describes the number of cycles that co_gs_go2critical_rd or co_gs_go2critical_wr must be asserted before the corresponding queue moves to the 'critical' state in the DDRC. The arbiter controls the co_gs_go2critical_* signals; it is designed for use with this hysteresis field set to 0. +
+reg_arb_go2critical_en + +17:17 + +20000 + +1 + +20000 + +1 - Set reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC based on 'urgent' input coming from AXI master. 0 - Keep reg_ddrc_go2critical_wr and reg_ddrc_go2critical_rd signals going to DDRC at 1'b0. +
+ctrl_reg2@0XF8006064 + +31:0 + +21fe0 + + + +20000 + +Controller register 2 +
+

Register ( slcr )ctrl_reg3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg3 +	+0XF8006068 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_wrlvl_ww + +7:0 + +ff + +41 + +41 + +Write leveling write-to-write delay. Specifies the minimum number of clock cycles from the assertion of a ddrc_dfi_wrlvl_strobe signal to the next ddrc_dfi_wrlvl_strobe signal. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Recommended value is: (RL + reg_phy_rdc_we_to_re_delay + 50) Only present in designs that support DDR3 and LPDDR2 devices. +
+reg_ddrc_rdlvl_rr + +15:8 + +ff00 + +41 + +4100 + +Read leveling read-to-read delay. Specifies the minimum number of clock cycles from the assertion of a read command to the next read command. Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Only present in designs that support DDR3 devices +
+reg_ddrc_dfi_t_wlmrd + +25:16 + +3ff0000 + +28 + +280000 + +First DQS/DQS# rising edge after write leveling mode is programmed. This is same as the tMLRD value from the DRAM spec. Only present in designs that support DDR3 devices. +
+ctrl_reg3@0XF8006068 + +31:0 + +3ffffff + + + +284141 + +Controller register 3 +
+

Register ( slcr )ctrl_reg4

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ctrl_reg4 +	+0XF800606C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CHE_REFRESH_TIMER01

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_REFRESH_TIMER01 +	+0XF80060A0 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CHE_T_ZQ

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_T_ZQ +	+0XF80060A4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dis_auto_zq + +0:0 + +1 + +0 + +0 + +1=disable controller generation of ZQCS command. Co_gs_zq_calib_short can be used instead to control ZQ calibration commands. 0=internally generate ZQCS commands based on reg_ddrc_t_zq_short_interval_x1024 This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_ddr3 + +1:1 + +2 + +1 + +2 + +Indicates operating in DDR2/DDR3 mode. Default value is set for DDR3. +
+reg_ddrc_t_mod + +11:2 + +ffc + +200 + +800 + +Mode register set command update delay (minimum the larger of 12 clock cycles or 15ns) +
+reg_ddrc_t_zq_long_nop + +21:12 + +3ff000 + +200 + +200000 + +Number of cycles of NOP required after a ZQCL (ZQ calibration long) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+reg_ddrc_t_zq_short_nop + +31:22 + +ffc00000 + +40 + +10000000 + +Number of cycles of NOP required after a ZQCS (ZQ calibration short) command is issued to DRAM. Units: Clock cycles This is only present for implementations supporting DDR3 and LPDDR2 devices. +
+CHE_T_ZQ@0XF80060A4 + +31:0 + +ffffffff + + + +10200802 + +ZQ parameters register +
+

Register ( slcr )CHE_T_ZQ_Short_Interval_Reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_T_ZQ_Short_Interval_Reg +	+0XF80060A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+t_zq_short_interval_x1024 + +19:0 + +fffff + +cb73 + +cb73 + +Average interval to wait between automatically issuing ZQCS (ZQ calibration short) commands to DDR3 devices. Meaningless if reg_ddrc_dis_auto_zq=1. Units: 1024 Clock cycles. Applicable for DDR3 and LPDDR2 devices. +
+dram_rstn_x1024 + +27:20 + +ff00000 + +69 + +6900000 + +Number of cycles to assert DRAM reset signal during init sequence. Units: 1024 Clock cycles. Applicable for DDR3 only. +
+CHE_T_ZQ_Short_Interval_Reg@0XF80060A8 + +31:0 + +fffffff + + + +690cb73 + +Misc parameters register +
+

Register ( slcr )deep_pwrdwn_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+deep_pwrdwn_reg +	+0XF80060AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+deeppowerdown_en + +0:0 + +1 + +0 + +0 + +1 - Controller puts the DRAM into Deep Powerdown mode when the transaction store is empty. 0 - Brings Controller out of Deep Powerdown mode Present only in designs configured to support LPDDR or LPDDR2 FOR PERFORMANCE ONLY. +
+deeppowerdown_to_x1024 + +8:1 + +1fe + +ff + +1fe + +Minimum deep power down time applicable only for LPDDR2. LPDDR exits from deep power down mode immediately after reg_ddrc_deeppowerdown_en is deasserted. For LPDDR2, Value from the spec is 500us. Units are in 1024 clock cycles. Present only in designs configured to support LPDDR or LPDDR2. FOR PERFORMANCE ONLY. +
+deep_pwrdwn_reg@0XF80060AC + +31:0 + +1ff + + + +1fe + +Deep powerdown register +
+

Register ( slcr )reg_2c

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_2c +	+0XF80060B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+dfi_wrlvl_max_x1024 + +11:0 + +fff + +fff + +fff + +Write leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_wrlvl_resp) to a write leveling enable signal (ddrc_dfi_wrlvl_en). Only applicable when connecting to PHY's operating in 'PHY WrLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+dfi_rdlvl_max_x1024 + +23:12 + +fff000 + +fff + +fff000 + +Read leveling maximum time. Specifies the maximum number of clock cycles that the controller will wait for a response (phy_dfi_rdlvl_resp) to a read leveling enable signal (ddrc_dfi_rdlvl_en or ddrc_dfi_rdlvl_gate_en). Only applicable when connecting to PHY's operating in 'PHY RdLvl Evaluation' mode. Typical value 0xFFF Units 1024 clocks +
+ddrc_reg_twrlvl_max_error + +24:24 + +1000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_wrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If write leveling timed out, an error is indicated by the DDRC and this bit gets set. The value is held until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3. +
+ddrc_reg_trdlvl_max_error + +25:25 + +2000000 + +0 + +0 + +When '1' indicates that the reg_ddrc_dfi_rdrlvl_max_x1024 timer has timed out. This is a Clear-on-Write register. If read leveling or gate training timed out, an error is indicated by the DDRC and this bit gets set. The value is held at that value until it is cleared. Clearing is done by writing a '0' to this register. Only present in designs that support DDR3 or LPDDR2 devices. +
+reg_ddrc_dfi_wr_level_en + +26:26 + +4000000 + +1 + +4000000 + +1 = Write leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0 = Write leveling disabled. +
+reg_ddrc_dfi_rd_dqs_gate_level + +27:27 + +8000000 + +1 + +8000000 + +1 = Read DQS Gate Leveling mode has been enabled as part of init sequence; Valid only for DDR3 DFI designs 0= Read DQS gate leveling is disabled. +
+reg_ddrc_dfi_rd_data_eye_train + +28:28 + +10000000 + +1 + +10000000 + +1 = Read Data Eye training mode has been enabled as part of init sequence. Only present in designs that support DDR3 or LPDDR2 devices. +
+reg_2c@0XF80060B0 + +31:0 + +1fffffff + + + +1cffffff + +Training control register +
+

Register ( slcr )reg_2d

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_2d +	+0XF80060B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_2t_delay + +8:0 + +1ff + +0 + +0 + +Selects the clock edge in which chip select (CSN) and CKE is asserted. Unsupported feature. +
+reg_ddrc_skip_ocd + +9:9 + +200 + +1 + +200 + +This register must be kept at 1'b1. 1'b0 is NOT supported. 1 - Indicates the controller to skip OCD adjustment step during DDR2 initialization. OCD_Default and OCD_Exit are performed instead. 0 - Not supported. +
+reg_ddrc_dis_pre_bypass + +10:10 + +400 + +0 + +0 + +Only present in designs supporting precharge bypass. When 1, disable bypass path for high priority precharges FOR DEBUG ONLY. +
+reg_2d@0XF80060B4 + +31:0 + +7ff + + + +200 + +Misc Debug register +
+

Register ( slcr )dfi_timing

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+dfi_timing +	+0XF80060B8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_dfi_t_rddata_en + +4:0 + +1f + +6 + +6 + +Time from the assertion of a READ command on the DFI interface to the assertion of the phy_dfi_rddata_en signal. Non-LPDDR -> RL-1 LPDDR -> RL Where RL is read latency of DRAM. +
+reg_ddrc_dfi_t_ctrlup_min + +14:5 + +7fe0 + +3 + +60 + +Specifies the minimum number of clock cycles that the ddrc_dfi_ctrlupd_req signal must be asserted. +
+reg_ddrc_dfi_t_ctrlup_max + +24:15 + +1ff8000 + +40 + +200000 + +Specifies the maximum number of clock cycles that the ddrc_dfi_ctrlupd_req signal can assert. +
+dfi_timing@0XF80060B8 + +31:0 + +1ffffff + + + +200066 + +DFI timing register +
+

RESET ECC ERROR

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_CONTROL_REG_OFFSET +	+0XF80060C4 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )CHE_ECC_CONTROL_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_CONTROL_REG_OFFSET +	+0XF80060C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Clear_Uncorrectable_DRAM_ECC_error + +0:0 + +1 + +0 + +0 + +Writing 1 to this bit will clear the uncorrectable log valid bit and the uncorrectable error counters. +
+Clear_Correctable_DRAM_ECC_error + +1:1 + +2 + +0 + +0 + +Writing 1 to this bit will clear the correctable log valid bit and the correctable error counters. +
+CHE_ECC_CONTROL_REG_OFFSET@0XF80060C4 + +31:0 + +3 + + + +0 + +ECC error clear register +
+

Register ( slcr )CHE_CORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_CORR_ECC_LOG_REG_OFFSET +	+0XF80060C8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when a correctable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x31) +
+ECC_CORRECTED_BIT_NUM + +7:1 + +fe + +0 + +0 + +Indicator of the bit number syndrome in error for single-bit errors. The field is 7-bit wide to handle 72-bits of data. This is an encoded value with ECC bits placed in between data. The encoding is given in section 5.4 Correctable bit number from the lowest error lane is reported here. There are only 13-valid bits going to an ECC lane (8-data + 5-ECC). Only 4-bits are needed to encode a max value of d'13. Bit[7] of this register is used to indicate the exact byte lane. When a error happens, if CORR_ECC_LOG_COL[0] from register 0x33 is 1'b0, then the error happened in Lane 0 or 1. If CORR_ECC_LOG_COL[0] is 1'b1, then the error happened in Lane 2 or 3. Bit[7] of this register indicates whether the error is from upper or lower byte lane. If it is 0, then it is lower byte lane and if it is 1, then it is upper byte lane. Together with CORR_ECC_LOG_COL[0] and bit[7] of this register, the exact byte lane with correctable error can be determined. +
+CHE_CORR_ECC_LOG_REG_OFFSET@0XF80060C8 + +31:0 + +ff + + + +0 + +ECC error correction register +
+

Register ( slcr )CHE_UNCORR_ECC_LOG_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_UNCORR_ECC_LOG_REG_OFFSET +	+0XF80060DC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNCORR_ECC_LOG_VALID + +0:0 + +1 + +0 + +0 + +Set to '1' when an uncorrectable ECC error is captured. As long as this is '1' no further ECC errors will be captured. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x31). +
+CHE_UNCORR_ECC_LOG_REG_OFFSET@0XF80060DC + +31:0 + +1 + + + +0 + +ECC unrecoverable error status register +
+

Register ( slcr )CHE_ECC_STATS_REG_OFFSET

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CHE_ECC_STATS_REG_OFFSET +	+0XF80060F0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STAT_NUM_CORR_ERR + +15:8 + +ff00 + +0 + +0 + +Returns the number of correctable ECC errors seen since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[1] of ECC CONTROL REGISTER (0x58). +
+STAT_NUM_UNCORR_ERR + +7:0 + +ff + +0 + +0 + +Returns the number of un-correctable errors since the last read. Counter saturates at max value. This is cleared when a '1' is written to register bit[0] of ECC CONTROL REGISTER (0x58). +
+CHE_ECC_STATS_REG_OFFSET@0XF80060F0 + +31:0 + +ffff + + + +0 + +ECC error count register +
+

Register ( slcr )ECC_scrub

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ECC_scrub +	+0XF80060F4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_ecc_mode + +2:0 + +7 + +0 + +0 + +DRAM ECC Mode. The only valid values that works for this project are 3'b000 (No ECC) and 3'b100 (SEC/DED over 1-beat). To run the design in ECC mode, set reg_ddrc_data_bus_width to 2'b01 (Half bus width) and reg_ddrc_ecc_mode to 3'b100. In this mode, there will be 16-data bits + 6-bit ECC on the DRAM bus. Controller must NOT be put in full bus width mode, when ECC is turned ON. 000 - No ECC, 001 - Reserved 010 - Parity 011 - Reserved 100 - SEC/DED over 1-beat 101 - SEC/DED over multiple beats 110 - Device Correction 111 - Reserved +
+reg_ddrc_dis_scrub + +3:3 + +8 + +1 + +8 + +This feature is NOT supported. Only default value works. 1 - Disable ECC scrubs 0 - Enable ECC scrubs Valid only when reg_ddrc_ecc_mode = 3'b100. +
+ECC_scrub@0XF80060F4 + +31:0 + +f + + + +8 + +ECC mode/scrub register +
+

Register ( slcr )phy_rcvr_enable

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rcvr_enable +	+0XF8006114 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF8006118 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006118 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF800611C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF800611C + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF8006120 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006120 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )PHY_Config

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+PHY_Config +	+0XF8006124 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_data_slice_in_use + +0:0 + +1 + +1 + +1 + +Data bus width selection for Read FIFO RE generation. One bit for each data slice. 1: data slice is valid. 0: read data responses are ignored. Note: The Phy Data Slice 0 must always be enabled. +
+reg_phy_rdlvl_inc_mode + +1:1 + +2 + +0 + +0 + +RESERVED +
+reg_phy_gatelvl_inc_mode + +2:2 + +4 + +0 + +0 + +RESERVED +
+reg_phy_wrlvl_inc_mode + +3:3 + +8 + +0 + +0 + +RESERVED +
+reg_phy_board_lpbk_tx + +4:4 + +10 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Transmitter for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_board_lpbk_rx + +5:5 + +20 + +0 + +0 + +External Board Loopback testing. 1: This Slice behaves as Receiver for board loopback. 0: disable This port must be set '0' always except when in external board level loopback test mode. +
+reg_phy_bist_shift_dq + +14:6 + +7fc0 + +0 + +0 + +Determines whether early shifting is required for a particular DQ bit when reg_phy_bist_mode is 2'b10; 1'b1: PRBS pattern shifted early by 1 bit. 1'b0: PRBS pattern without any shift. +
+reg_phy_bist_err_clr + +23:15 + +ff8000 + +0 + +0 + +Clear the mismatch error flag from the BIST Checker. 1'b1: sticky error flag is cleared 1'b0: No effect +
+reg_phy_dq_offset + +30:24 + +7f000000 + +40 + +40000000 + +Offset value from DQS to DQ. Default value: 0x40 (for 90 degree shift). This is only used when reg_phy_use_wr_level=1. #Note 1: When a port width (W) is multiple of N instances of Ranks or Slices, each instance will get W/N bits. Instance n will get (n+1)*(W/N) -1: n (W/N) bits where n (0, 1, to N-1) is the instance number of Rank or Slice. +
+PHY_Config@0XF8006124 + +31:0 + +7fffffff + + + +40000001 + +PHY configuration register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF800612C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF8006130 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +12 + +12 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +d8 + +36000 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006130 + +31:0 + +fffff + + + +36012 + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF8006134 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +c + +c + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +de + +37800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006134 + +31:0 + +fffff + + + +3780c + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_init_ratio

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_init_ratio +	+0XF8006138 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wrlvl_init_ratio + +9:0 + +3ff + +21 + +21 + +The user programmable init ratio used by Write Leveling FSM +
+reg_phy_gatelvl_init_ratio + +19:10 + +ffc00 + +ee + +3b800 + +The user programmable init ratio used Gate Leveling FSM +
+phy_init_ratio@0XF8006138 + +31:0 + +fffff + + + +3b821 + +PHY init ratio register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF8006140 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006140 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF8006144 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006144 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF8006148 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF8006148 + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_rd_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_rd_dqs_cfg +	+0XF800614C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_rd_dqs_slave_ratio + +9:0 + +3ff + +35 + +35 + +Ratio value for read DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. Provide a default value of 0x40 for most applications +
+reg_phy_rd_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for read DQS slave DLL with the value of the debug_rd_dqs_slave_delay bus. +
+reg_phy_rd_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for read DQS slave DLL with this value. +
+phy_rd_dqs_cfg@0XF800614C + +31:0 + +fffff + + + +35 + +PHY read DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF8006154 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +9d + +9d + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006154 + +31:0 + +fffff + + + +9d + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF8006158 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +92 + +92 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006158 + +31:0 + +fffff + + + +92 + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF800615C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +8c + +8c + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF800615C + +31:0 + +fffff + + + +8c + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_wr_dqs_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_wr_dqs_cfg +	+0XF8006160 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_dqs_slave_ratio + +9:0 + +3ff + +a1 + +a1 + +Ratio value for write DQS slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQS in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_dqs_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write DQS slave DLL with the value of the reg_phy_wr_dqs_slave_delay bus. +
+reg_phy_wr_dqs_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_dqs_slave_force is 1, replace delay/tap value for write DQS slave DLL with this value. +
+phy_wr_dqs_cfg@0XF8006160 + +31:0 + +fffff + + + +a1 + +PHY write DQS configuration register for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF8006168 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +147 + +147 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF8006168 + +31:0 + +1fffff + + + +147 + +PHY fifo write enable configuration register for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF800616C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +12d + +12d + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF800616C + +31:0 + +1fffff + + + +12d + +PHY fifo write enable configuration register for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF8006170 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +133 + +133 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF8006170 + +31:0 + +1fffff + + + +133 + +PHY fifo write enable configuration register for data slice 0. +
+

Register ( slcr )phy_we_cfg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+phy_we_cfg +	+0XF8006174 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_fifo_we_slave_ratio + +10:0 + +7ff + +143 + +143 + +Ratio value to be used when fifo_we_X_force_mode is set to 0. +
+reg_phy_fifo_we_in_force + +11:11 + +800 + +0 + +0 + +1: overwrite the delay/tap value for fifo_we_X slave DLL with the value of the debug_fifo_we_in_delayX bus. +
+reg_phy_fifo_we_in_delay + +20:12 + +1ff000 + +0 + +0 + +Delay value to be used when debug_fifo_we_in_forceX is set to 1. R is the number of Ranks supported. +
+phy_we_cfg@0XF8006174 + +31:0 + +1fffff + + + +143 + +PHY fifo write enable configuration register for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF800617C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +dd + +dd + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF800617C + +31:0 + +fffff + + + +dd + +PHY write data slave ratio configuration register for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF8006180 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +d2 + +d2 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006180 + +31:0 + +fffff + + + +d2 + +PHY write data slave ratio configuration register for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF8006184 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +cc + +cc + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006184 + +31:0 + +fffff + + + +cc + +PHY write data slave ratio configuration register for data slice 0. +
+

Register ( slcr )wr_data_slv

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+wr_data_slv +	+0XF8006188 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_data_slave_ratio + +9:0 + +3ff + +e1 + +e1 + +Ratio value for write data slave DLL. This is the fraction of a clock cycle represented by the shift to be applied to the write DQ muxes in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_wr_data_slave_force + +10:10 + +400 + +0 + +0 + +1: overwrite the delay/tap value for write data slave DLL with the value of the reg_phy_wr_data_slave_force bus. +
+reg_phy_wr_data_slave_delay + +19:11 + +ff800 + +0 + +0 + +If reg_phy_wr_data_slave_force is 1, replace delay/tap value for write data slave DLL with this value. +
+wr_data_slv@0XF8006188 + +31:0 + +fffff + + + +e1 + +PHY write data slave ratio configuration register for data slice 0. +
+

Register ( slcr )reg_64

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_64 +	+0XF8006190 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_loopback + +0:0 + +1 + +0 + +0 + +Loopback testing. 1: enable, 0: disable +
+reg_phy_bl2 + +1:1 + +2 + +0 + +0 + +Reserved for future Use. +
+reg_phy_at_spd_atpg + +2:2 + +4 + +0 + +0 + +1 = run scan test at full clock speed but with less coverage 0 = run scan test at slow clock speed but with high coverage During normal function mode, this port must be set 0. +
+reg_phy_bist_enable + +3:3 + +8 + +0 + +0 + +Enable the internal BIST generation and checker logic when this port is set HIGH. Setting this port as 0 will stop the BIST generator/checker. In order to run BIST tests, this port must be set along with reg_phy_loopback. +
+reg_phy_bist_force_err + +4:4 + +10 + +0 + +0 + +This register bit is used to check that BIST checker is not giving false pass. When this port is set 1, data bit gets inverted before sending out to the external memory and BIST checker must return a mismatch error. +
+reg_phy_bist_mode + +6:5 + +60 + +0 + +0 + +The mode bits select the pattern type generated by the BIST generator. All the patterns are transmitted continuously once enabled. 2'b00: constant pattern (0 repeated on each DQ bit) 2'b01: low freq pattern (00001111 repeated on each DQ bit) 2'b10: PRBS pattern (2^7-1 PRBS pattern repeated on each DQ bit) Each DQ bit always has same data value except when early shifting in PRBS mode is requested +
+reg_phy_invert_clkout + +7:7 + +80 + +1 + +80 + +Inverts the polarity of DRAM clock. 0: core clock is passed on to DRAM 1: inverted core clock is passed on to DRAM. Use this when CLK can arrive at a DRAM device ahead of DQS or coincidence with DQS based on boad topology. This effectively delays the CLK to the DRAM device by half -cycle, providing a CLK edge that DQS can align to during leveling. +
+reg_phy_all_dq_mpr_rd_resp + +8:8 + +100 + +0 + +0 + +1=assume DRAM provides read response on all DQ bits. (In this mode, dq_in[7:0] are OR'd together and dq_in[15:8] are AND'd together.) 0=(default) best for DRAM read responses on only 1 DQ bit; works with reduced accuracy if DRAM provides read response on all bits. (In this mode dq_in[7:0] are OR'd together and dq_in[15:8] are OR'd together.) +
+reg_phy_sel_logic + +9:9 + +200 + +0 + +0 + +Selects one of the two read leveling algorithms.'b0 = Select algorithm # 1'b1 = Select algorithm # 2 Please refer to Read Data Eye Training section in PHY User Guide for details about the Read Leveling algorithms +
+reg_phy_ctrl_slave_ratio + +19:10 + +ffc00 + +100 + +40000 + +Ratio value for address/command launch timing in phy_ctrl macro. This is the fraction of a clock cycle represented by the shift to be applied to the read DQS in units of 256ths. In other words, the full cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line. +
+reg_phy_ctrl_slave_force + +20:20 + +100000 + +0 + +0 + +1: overwrite the delay/tap value for address/command timing slave DLL with the value of the reg_phy_rd_dqs_slave_delay bus. +
+reg_phy_ctrl_slave_delay + +27:21 + +fe00000 + +0 + +0 + +If reg_phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value. This is a bit value, the remaining 2 bits are in register 0x65 bits[19:18]. +
+reg_phy_use_rank0_delays + +28:28 + +10000000 + +1 + +10000000 + +Delay selection 1- Rank 0 delays are used for all ranks 0- Each Rank uses its own delay +
+reg_phy_lpddr + +29:29 + +20000000 + +0 + +0 + +1= mobile/LPDDR DRAM device in use. 0=non-LPDDR DRAM device in use. +
+reg_phy_cmd_latency + +30:30 + +40000000 + +0 + +0 + +If set to 1, command comes to phy_ctrl through a flop. +
+reg_phy_int_lpbk + +31:31 + +80000000 + +0 + +0 + +1=enables the PHY internal loopback for DQ,DQS,DM before Ios. By default must be 0. +
+reg_64@0XF8006190 + +31:0 + +ffffffff + + + +10040080 + +Training control register (2) +
+

Register ( slcr )reg_65

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+reg_65 +	+0XF8006194 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_phy_wr_rl_delay + +4:0 + +1f + +2 + +2 + +This delay determines when to select the active rank's ratio logic delay for Write Data and Write DQS slave delay lines after PHY receives a write command at Control Interface. The programmed value must be (Write Latency - 4) with a minimum value of 1. +
+reg_phy_rd_rl_delay + +9:5 + +3e0 + +4 + +80 + +This delay determines when to select the active rank's ratio logic delay for Read Data and Read DQS slave delay lines after PHY receives a read command at Control Interface. The programmed value must be (Read Latency - 3) with a minimum value of 1. +
+reg_phy_dll_lock_diff + +13:10 + +3c00 + +f + +3c00 + +The Maximum number of delay line taps variation allowed while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by the register, the lock signal is deasserted +
+reg_phy_use_wr_level + +14:14 + +4000 + +1 + +4000 + +Write Leveling training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by write leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_dqs_gate_level + +15:15 + +8000 + +1 + +8000 + +Read DQS Gate training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by DQS gate leveling Note: This is a Synchronous dynamic signal that requires timing closure. +
+reg_phy_use_rd_data_eye_level + +16:16 + +10000 + +1 + +10000 + +Read Data Eye training control. 0: Use register programmed ratio values 1: Use ratio for delay line calculated by data eye leveling Note: This is a Synchronous dynamic signal that requires timing closure +
+reg_phy_dis_calib_rst + +17:17 + +20000 + +0 + +0 + +Disable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of phy_data. Note: dll_calib is (i) generated by dfi_ctrl_upd_req or (ii) by the PHY when it detects that the clock frequency variation has exceeded the bounds set by reg_phy_dll_lock_diff or (iii) periodically throughout the leveling process. dll_calib will update the slave DL with PVT-compensated values according to master DLL outputs +
+reg_phy_ctrl_slave_delay + +19:18 + +c0000 + +0 + +0 + +If reg-phy_rd_dqs_slave_force is 1, replace delay/tap value for address/command timing slave DLL with this value +
+reg_65@0XF8006194 + +31:0 + +fffff + + + +1fc82 + +Training control register (3) +
+

Register ( slcr )page_mask

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+page_mask +	+0XF8006204 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_page_addr_mask + +31:0 + +ffffffff + +0 + +0 + +This register must be set based on the value programmed on the reg_ddrc_addrmap_* registers. Set the Column address bits to 0. Set the Page and Bank address bits to 1. This is used for calculating page_match inside the slave modules in Arbiter. The page_match is considered during the arbitration process. This mask applies to 64-bit address and not byte address. Setting this value to 0 disables transaction prioritization based on page/bank match. +
+page_mask@0XF8006204 + +31:0 + +ffffffff + + + +0 + +Page mask register +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF8006208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF8006208 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF800620C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF800620C + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF8006210 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF8006210 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_wr_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_wr_port +	+0XF8006214 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_wr_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Write Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_wr_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Write Port. +
+reg_arb_disable_urgent_wr_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Write Port. +
+reg_arb_dis_page_match_wr_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_dis_rmw_portn + +19:19 + +80000 + +1 + +80000 + +FEATURE NOT SUPPORTED. Only 16-bit data aligned transfers allowed when ECC is used. All commands issued as Writes. No RMW support. Disable RMW command generated for this Port 1 - Disable RMW feature 0 - Enable RMW feature When Enabled and ECC mode is set all Write command generated by this port will be RMW. +
+axi_priority_wr_port@0XF8006214 + +31:0 + +f03ff + + + +803ff + +AXI Priority control for write port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF8006218 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF800621C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF800621C + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF8006220 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006220 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )axi_priority_rd_port

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+axi_priority_rd_port +	+0XF8006224 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_arb_pri_rd_portn + +9:0 + +3ff + +3ff + +3ff + +Priority of this Read Port n. Value in this register used to load the aging counters (when respective port request is asserted and grant is generated to that port). These register can be reprogrammed to set priority of each port. Lower the value more will be priority given to the port. For example if 0x82 (port 0) value is set to 'h3FF, and 0x83 (port 1) is set to 'h0FF, and both port0 and port1 have requests, in this case port1 will get high priority and grant will be given to port1. +
+reg_arb_disable_aging_rd_portn + +16:16 + +10000 + +0 + +0 + +Disable aging for this Read Port. +
+reg_arb_disable_urgent_rd_portn + +17:17 + +20000 + +0 + +0 + +Disable urgent for this Read Port. +
+reg_arb_dis_page_match_rd_portn + +18:18 + +40000 + +0 + +0 + +Disable the page match feature. +
+reg_arb_set_hpr_rd_portn + +19:19 + +80000 + +0 + +0 + +Enable reads to be generated as HPR for this Read Port. +
+axi_priority_rd_port@0XF8006224 + +31:0 + +f03ff + + + +3ff + +AXI Priority control for read port 0. +
+

Register ( slcr )lpddr_ctrl0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl0 +	+0XF80062A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_lpddr2 + +0:0 + +1 + +0 + +0 + +1=LPDDR2 DRAM device in Use. 0=non-LPDDR2 device in use Present only in designs configured to support LPDDR2. +
+reg_ddrc_per_bank_refresh + +1:1 + +2 + +0 + +0 + +1:Per bank refresh 0:All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported on all LPDDR2 devices. Present only in designs configured to support LPDDR2. +
+reg_ddrc_derate_enable + +2:2 + +4 + +0 + +0 + +0: Timing parameter derating is disabled. 1: Timing parameter derating is enabled using MR4 read value. Present only in designs configured to support LPDDR2. +
+reg_ddrc_mr4_margin + +11:4 + +ff0 + +0 + +0 + +UNUSED +
+lpddr_ctrl0@0XF80062A8 + +31:0 + +ff7 + + + +0 + +LPDDR2 Control 0 Register +
+

Register ( slcr )lpddr_ctrl1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl1 +	+0XF80062AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_mr4_read_interval + +31:0 + +ffffffff + +0 + +0 + +Interval between two MR4 reads, USED to derate the timing parameters. Present only in designs configured to support LPDDR2. +
+lpddr_ctrl1@0XF80062AC + +31:0 + +ffffffff + + + +0 + +LPDDR2 Control 1 Register +
+

Register ( slcr )lpddr_ctrl2

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl2 +	+0XF80062B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_min_stable_clock_x1 + +3:0 + +f + +5 + +5 + +Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2. Units: 1 clock cycle. LPDDR2 typically requires 5 x tCK delay. +
+reg_ddrc_idle_after_reset_x32 + +11:4 + +ff0 + +12 + +120 + +Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. +
+reg_ddrc_t_mrw + +21:12 + +3ff000 + +5 + +5000 + +Time to wait during load mode register writes. Present only in designs configured to support LPDDR2. LPDDR2 typically requires value of 5. +
+lpddr_ctrl2@0XF80062B0 + +31:0 + +3fffff + + + +5125 + +LPDDR2 Control 2 Register +
+

Register ( slcr )lpddr_ctrl3

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+lpddr_ctrl3 +	+0XF80062B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_max_auto_init_x1024 + +7:0 + +ff + +a8 + +a8 + +Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2. Units: 1024 clock cycles. LPDDR2 typically requires 10 us. +
+reg_ddrc_dev_zqinit_x32 + +17:8 + +3ff00 + +12 + +1200 + +ZQ initial calibration, tZQINIT. Present only in designs configured to support LPDDR2. Units: 32 clock cycles. LPDDR2 typically requires 1 us. +
+lpddr_ctrl3@0XF80062B4 + +31:0 + +3ffff + + + +12a8 + +LPDDR2 Control 3 Register +
+

POLL ON DCI STATUS

Register ( slcr )DDRIOB_DCI_STATUS

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_STATUS +	+0XF8000B74 +	+32 +	+rw +	+0x00000000 +	+-- +

UNLOCK DDR

Register ( slcr )ddrc_ctrl

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ddrc_ctrl +	+0XF8006000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reg_ddrc_soft_rstb + +0:0 + +1 + +1 + +1 + +Active low soft reset. 0 = Resets the controller 1 = Takes the controller out of reset Note: Controller must be taken out of reset only after all other registers have been programmed. +
+reg_ddrc_powerdown_en + +1:1 + +2 + +0 + +0 + +Controller power down control. 0 = DDRC powerdown disabled 1 = the controller goes into power down after a programmable number of cycles 'Maximum idle clocks before power down' (reg_ddrc_powerdown_to_x32). Note: This register bit may be reprogrammed during the course of normal operation. +
+reg_ddrc_data_bus_width + +3:2 + +c + +0 + +0 + +DDR bus width control 00 = 32 bit DDR bus 01 = 16 bit DDR bus 1x = reserved +
+reg_ddrc_burst8_refresh + +6:4 + +70 + +0 + +0 + +Refresh timeout register. Programmed value plus one will be the number of refresh timeouts that will be allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes; therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for burst_of_N_refresh slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes. 0 = single refresh 1 = burst-of-2 . 7 = burst-of-8 refresh +
+reg_ddrc_rdwr_idle_gap + +13:7 + +3f80 + +1 + +80 + +When the preferred transaction store is empty for this many clock cycles, switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternate store. When 'Prefer write over read' is set this is reversed. +
+reg_ddrc_dis_rd_bypass + +14:14 + +4000 + +0 + +0 + +Only present in designs supporting read bypass. For Debug only. 0 = Do not disable bypass path for high priority read page hits. 1 = disable bypass path for high priority read page hits. +
+reg_ddrc_dis_act_bypass + +15:15 + +8000 + +0 + +0 + +Only present in designs supporting activate bypass. For Debug only. 0 = Do not disable bypass path for high priority read activates. 1 = disable bypass path for high priority read activates. +
+reg_ddrc_dis_auto_refresh + +16:16 + +10000 + +0 + +0 + +Disable auto-refresh. 0 = do not disable auto-refresh generated by the controller. This input is changeable on the fly. 1 = disable auto-refresh generated by the controller. This input is changeable on the fly. Note: When this transitions from 0 to 1, any pending refreshes will be immediately scheduled by the controller. +
+ddrc_ctrl@0XF8006000 + +31:0 + +1ffff + + + +81 + +DDRC Control Register +
+

CHECK DDR STATUS

Register ( slcr )mode_sts_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+mode_sts_reg +	+0XF8006054 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+ddrc_reg_operating_mode + +2:0 + +7 + +1 + +1 + +Gives the status of the controller. 0 = DDRC Init 1 = Normal operation 2 = Power-down mode 3 = Self-refresh mode 4 and above = deep power down mode (LPDDR2 only) +
+mode_sts_reg@0XF8006054 + +31:0 + +7 + + + +1 + +tobe +
+

+ +

ps7_mio_init_data_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +GPIOB_CTRL + +	+0XF8000B00 +	+32 +	+RW +	+0x000000 +	+GPIOB control +
+ +DDRIOB_ADDR0 + +	+0XF8000B40 +	+32 +	+RW +	+0x000000 +	+DDRIOB Address 0 Configuartion Register +
+ +DDRIOB_ADDR1 + +	+0XF8000B44 +	+32 +	+RW +	+0x000000 +	+DDRIOB Address 1 Configuration Register +
+ +DDRIOB_DATA0 + +	+0XF8000B48 +	+32 +	+RW +	+0x000000 +	+DDRIOB Data 0 Configuration Register +
+ +DDRIOB_DATA1 + +	+0XF8000B4C +	+32 +	+RW +	+0x000000 +	+DDRIOB Data 1 Configuration Register +
+ +DDRIOB_DIFF0 + +	+0XF8000B50 +	+32 +	+RW +	+0x000000 +	+DDRIOB Differential DQS 0 Configuration Register +
+ +DDRIOB_DIFF1 + +	+0XF8000B54 +	+32 +	+RW +	+0x000000 +	+DDRIOB Differential DQS 1 Configuration Register +
+ +DDRIOB_CLOCK + +	+0XF8000B58 +	+32 +	+RW +	+0x000000 +	+DDRIOB Differential Clock Configuration Register +
+ +DDRIOB_DRIVE_SLEW_ADDR + +	+0XF8000B5C +	+32 +	+RW +	+0x000000 +	+DDRIOB Drive Slew Address Register +
+ +DDRIOB_DRIVE_SLEW_DATA + +	+0XF8000B60 +	+32 +	+RW +	+0x000000 +	+DDRIOB Drive Slew Data Register +
+ +DDRIOB_DRIVE_SLEW_DIFF + +	+0XF8000B64 +	+32 +	+RW +	+0x000000 +	+DDRIOB Drive Slew Differential Strobe Register +
+ +DDRIOB_DRIVE_SLEW_CLOCK + +	+0XF8000B68 +	+32 +	+RW +	+0x000000 +	+DDRIOB Drive Slew Clcok Register +
+ +DDRIOB_DDR_CTRL + +	+0XF8000B6C +	+32 +	+RW +	+0x000000 +	+DDRIOB DDR Control Register +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDRIOB DCI configuration +
+ +DDRIOB_DCI_CTRL + +	+0XF8000B70 +	+32 +	+RW +	+0x000000 +	+DDRIOB DCI configuration +
+ +MIO_PIN_00 + +	+0XF8000700 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 0 +
+ +MIO_PIN_01 + +	+0XF8000704 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 1 +
+ +MIO_PIN_02 + +	+0XF8000708 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 2 +
+ +MIO_PIN_03 + +	+0XF800070C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 3 +
+ +MIO_PIN_04 + +	+0XF8000710 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 4 +
+ +MIO_PIN_05 + +	+0XF8000714 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 5 +
+ +MIO_PIN_06 + +	+0XF8000718 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 6 +
+ +MIO_PIN_07 + +	+0XF800071C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 7 +
+ +MIO_PIN_08 + +	+0XF8000720 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 8 +
+ +MIO_PIN_09 + +	+0XF8000724 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 9 +
+ +MIO_PIN_10 + +	+0XF8000728 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 10 +
+ +MIO_PIN_11 + +	+0XF800072C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 11 +
+ +MIO_PIN_12 + +	+0XF8000730 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 12 +
+ +MIO_PIN_13 + +	+0XF8000734 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 13 +
+ +MIO_PIN_14 + +	+0XF8000738 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 14 +
+ +MIO_PIN_15 + +	+0XF800073C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 15 +
+ +MIO_PIN_16 + +	+0XF8000740 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 16 +
+ +MIO_PIN_17 + +	+0XF8000744 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 17 +
+ +MIO_PIN_18 + +	+0XF8000748 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 18 +
+ +MIO_PIN_19 + +	+0XF800074C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 19 +
+ +MIO_PIN_20 + +	+0XF8000750 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 20 +
+ +MIO_PIN_21 + +	+0XF8000754 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 21 +
+ +MIO_PIN_22 + +	+0XF8000758 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 22 +
+ +MIO_PIN_23 + +	+0XF800075C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 23 +
+ +MIO_PIN_24 + +	+0XF8000760 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 24 +
+ +MIO_PIN_25 + +	+0XF8000764 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 25 +
+ +MIO_PIN_26 + +	+0XF8000768 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 26 +
+ +MIO_PIN_27 + +	+0XF800076C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 27 +
+ +MIO_PIN_28 + +	+0XF8000770 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 28 +
+ +MIO_PIN_29 + +	+0XF8000774 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 29 +
+ +MIO_PIN_30 + +	+0XF8000778 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 30 +
+ +MIO_PIN_31 + +	+0XF800077C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 31 +
+ +MIO_PIN_32 + +	+0XF8000780 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 32 +
+ +MIO_PIN_33 + +	+0XF8000784 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 33 +
+ +MIO_PIN_34 + +	+0XF8000788 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 34 +
+ +MIO_PIN_35 + +	+0XF800078C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 35 +
+ +MIO_PIN_36 + +	+0XF8000790 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 36 +
+ +MIO_PIN_37 + +	+0XF8000794 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 37 +
+ +MIO_PIN_38 + +	+0XF8000798 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 38 +
+ +MIO_PIN_39 + +	+0XF800079C +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 39 +
+ +MIO_PIN_40 + +	+0XF80007A0 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 40 +
+ +MIO_PIN_41 + +	+0XF80007A4 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 41 +
+ +MIO_PIN_42 + +	+0XF80007A8 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 42 +
+ +MIO_PIN_43 + +	+0XF80007AC +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 43 +
+ +MIO_PIN_44 + +	+0XF80007B0 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 44 +
+ +MIO_PIN_45 + +	+0XF80007B4 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 45 +
+ +MIO_PIN_46 + +	+0XF80007B8 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 46 +
+ +MIO_PIN_47 + +	+0XF80007BC +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 47 +
+ +MIO_PIN_48 + +	+0XF80007C0 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 48 +
+ +MIO_PIN_49 + +	+0XF80007C4 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 49 +
+ +MIO_PIN_50 + +	+0XF80007C8 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 50 +
+ +MIO_PIN_51 + +	+0XF80007CC +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 51 +
+ +MIO_PIN_52 + +	+0XF80007D0 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 52 +
+ +MIO_PIN_53 + +	+0XF80007D4 +	+32 +	+RW +	+0x000000 +	+MIO Control for Pin 53 +
+ +SD0_WP_CD_SEL + +	+0XF8000830 +	+32 +	+RW +	+0x000000 +	+SDIO 0 WP CD select register +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_mio_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

OCM REMAPPING

Register ( slcr )GPIOB_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+GPIOB_CTRL +	+0XF8000B00 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_EN + +0:0 + +1 + +1 + +1 + +Enables VREF internal generator +
+VREF_PULLUP_EN + +1:1 + +2 + +0 + +0 + +Enables internal pullup. 0 - no pullup. 1 - pullup. +
+CLK_PULLUP_EN + +8:8 + +100 + +0 + +0 + +Enables internal pullup. 0 - no pullup. 1 - pullup. +
+SRSTN_PULLUP_EN + +9:9 + +200 + +0 + +0 + +Enables internal pullup. 0 - no pullup. 1 - pullup. +
+GPIOB_CTRL@0XF8000B00 + +31:0 + +303 + + + +1 + +GPIOB control +
+

DDRIOB SETTINGS

Register ( slcr )DDRIOB_ADDR0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_ADDR0 +	+0XF8000B40 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_ADDR0@0XF8000B40 + +31:0 + +fff + + + +600 + +DDRIOB Address 0 Configuartion Register +
+

Register ( slcr )DDRIOB_ADDR1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_ADDR1 +	+0XF8000B44 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_ADDR1@0XF8000B44 + +31:0 + +fff + + + +600 + +DDRIOB Address 1 Configuration Register +
+

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA0 +	+0XF8000B48 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DATA0@0XF8000B48 + +31:0 + +fff + + + +672 + +DDRIOB Data 0 Configuration Register +
+

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA1 +	+0XF8000B4C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +1 + +2 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DATA1@0XF8000B4C + +31:0 + +fff + + + +672 + +DDRIOB Data 1 Configuration Register +
+

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF0 +	+0XF8000B50 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DIFF0@0XF8000B50 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 0 Configuration Register +
+

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF1 +	+0XF8000B54 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +2 + +4 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +1 + +10 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +3 + +60 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_DIFF1@0XF8000B54 + +31:0 + +fff + + + +674 + +DDRIOB Differential DQS 1 Configuration Register +
+

Register ( slcr )DDRIOB_CLOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_CLOCK +	+0XF8000B58 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+INP_POWER + +0:0 + +1 + +0 + +0 + +Specifies DDR IOB input amp power mode. 0- low power mode. 1- high performance mode. +
+INP_TYPE + +2:1 + +6 + +0 + +0 + +Input buffer controls. 00 - Input off, reads 0. 01 - Vref based differential reciever for SSTL, HSTL. 10 - Differential input reciever. 11- LVCMOS reviever. +
+DCI_UPDATE + +3:3 + +8 + +0 + +0 + +DCI Update Enabled 0 - disabled 1 - enabled +
+TERM_EN + +4:4 + +10 + +0 + +0 + +Tri State Termination Enabled 0 - disabled 1 - enabled +
+DCR_TYPE + +6:5 + +60 + +0 + +0 + +DCI Update 00 - DCI Disabled 01 - DCI Drive (HSTL12_DCI) 10 - Reserved 11 - DCI Termination (SSTL15_T_DCI) +
+IBUF_DISABLE_MODE + +7:7 + +80 + +0 + +0 + +Use ibuf_disable_into control ibuf 0 -ibuf is always enabled 1 - use ibuf_disable_in_to control enable +
+TERM_DISABLE_MODE + +8:8 + +100 + +0 + +0 + +Use dynamic_dci_ts to control dci 0 - termination enabled 1 - use 'dynamic_dci_ts' control termination +
+OUTPUT_EN + +10:9 + +600 + +3 + +600 + +Enables output mode to enable output ties to 00 - ibuf 01 - reserved 10 - reserved 11 - obuf +
+PULLUP_EN + +11:11 + +800 + +0 + +0 + +enables pullup on output 0 - no pullup 1 - pullup enabled +
+DDRIOB_CLOCK@0XF8000B58 + +31:0 + +fff + + + +600 + +DDRIOB Differential Clock Configuration Register +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_ADDR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_ADDR +	+0XF8000B5C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +3 + +c000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +3 + +180000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_ADDR@0XF8000B5C + +31:0 + +ffffffff + + + +18c61c + +DDRIOB Drive Slew Address Register +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_DATA

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_DATA +	+0XF8000B60 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DATA@0XF8000B60 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Data Register +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_DIFF

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_DIFF +	+0XF8000B64 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_DIFF@0XF8000B64 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Differential Strobe Register +
+

Register ( slcr )DDRIOB_DRIVE_SLEW_CLOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DRIVE_SLEW_CLOCK +	+0XF8000B68 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DRIVE_P + +6:0 + +7f + +1c + +1c + +Programs the DDRIO drive strength for the P devices +
+DRIVE_N + +13:7 + +3f80 + +c + +600 + +Programs the DDRIO drive strength for the N devices +
+SLEW_P + +18:14 + +7c000 + +6 + +18000 + +Programs the DDRIO slew rate for the P devices +
+SLEW_N + +23:19 + +f80000 + +1f + +f80000 + +Programs the DDRIO slew rate for the N devices +
+GTL + +26:24 + +7000000 + +0 + +0 + +Test Control 000 - Normal Operation 001 : 111 - Test Mode +
+RTERM + +31:27 + +f8000000 + +0 + +0 + +Program the rterm +
+DDRIOB_DRIVE_SLEW_CLOCK@0XF8000B68 + +31:0 + +ffffffff + + + +f9861c + +DDRIOB Drive Slew Clcok Register +
+

Register ( slcr )DDRIOB_DDR_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DDR_CTRL +	+0XF8000B6C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+VREF_INT_EN + +0:0 + +1 + +1 + +1 + +Enables VREF internal generator +
+VREF_SEL + +4:1 + +1e + +4 + +8 + +Specifies DDR IOB Vref generator output 0001 - VREF = 0.6V for LPDDR2 with 1.2V IO 0010 - VREF = 0.675V for LPDDR3 1.35 V IO 0100 - VREF = 0.75V for DDR3 with 1.5V IO 1000 - VREF = 0.90V for DDR2 with 1.8V IO +
+VREF_EXT_EN + +6:5 + +60 + +0 + +0 + +Enables External VREF input X0 - Disable External VREF for lower 16 bits X1 - Enable External VREF for lower 16 bits 0X - Disable External VREF for upper 16 bits 1X - Enable External VREF for upper 16 bits +
+VREF_PULLUP_EN + +8:7 + +180 + +0 + +0 + +Enables VREF pull-up resistors X0 - Disable VREF pull-up for lower 16 bits X1 - Enable VREF pull-up for lower 16 bits 0X - Disable VREF pull-up for upper 16 bits 1X - Enable VREF pull-up for upper 16 bits +
+REFIO_EN + +9:9 + +200 + +1 + +200 + +Enables VRP,VRN 0 - VRP/VRN not used 1 - VRP/VRN used as refio +
+REFIO_PULLUP_EN + +12:12 + +1000 + +0 + +0 + +Enables VRP,VRN pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
+DRST_B_PULLUP_EN + +13:13 + +2000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
+CKE_PULLUP_EN + +14:14 + +4000 + +0 + +0 + +Enables pull-up resistors 0 -no pull-up 1 - enable pull-up resistors +
+DDRIOB_DDR_CTRL@0XF8000B6C + +31:0 + +73ff + + + +209 + +DDRIOB DDR Control Register +
+

ASSERT RESET

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

DEASSERT RESET

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+RESET + +0:0 + +1 + +0 + +0 + +At least toggle once to initialise flops in DCI system +
+VRN_OUT + +5:5 + +20 + +1 + +20 + +VRN output value +
+DDRIOB_DCI_CTRL@0XF8000B70 + +31:0 + +21 + + + +20 + +DDRIOB DCI configuration +
+

Register ( slcr )DDRIOB_DCI_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DCI_CTRL +	+0XF8000B70 +	+32 +	+rw +	+0x00000000 +	+-- +

MIO PROGRAMMING

Register ( slcr )MIO_PIN_00

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_00 +	+0XF8000700 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_00@0XF8000700 + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 0 +
+

Register ( slcr )MIO_PIN_01

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_01 +	+0XF8000704 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi_sel, Output, qspi_n_ss_out- (QSPI Select) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= smc_a25, Output, smc_sram_add[25]- (SRAM Address) 2= smc_cs1, Output, smc_sram_cs_n[1]- (SRAM CS1) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_01@0XF8000704 + +31:0 + +3fff + + + +1202 + +MIO Control for Pin 1 +
+

Register ( slcr )MIO_PIN_02

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_02 +	+0XF8000708 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[8]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_clk- (SRAM Clock) 2= nand, Output, smc_nand_ale- (NAND Address Latch Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_02@0XF8000708 + +31:0 + +3fff + + + +202 + +MIO Control for Pin 2 +
+

Register ( slcr )MIO_PIN_03

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_03 +	+0XF800070C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[9]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[0]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[0]- (SRAM Data) 2= nand, Output, smc_nand_we_b- (NAND Write Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_03@0XF800070C + +31:0 + +3fff + + + +202 + +MIO Control for Pin 3 +
+

Register ( slcr )MIO_PIN_04

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_04 +	+0XF8000710 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[10]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[1]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[1]- (SRAM Data) 2= nand, Input, smc_nand_data_in[2]- (NAND Data Bus) = nand, Output, smc_nand_data_out[2]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[2] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_04@0XF8000710 + +31:0 + +3fff + + + +202 + +MIO Control for Pin 4 +
+

Register ( slcr )MIO_PIN_05

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_05 +	+0XF8000714 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[11]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[2]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[2]- (SRAM Data) 2= nand, Input, smc_nand_data_in[0]- (NAND Data Bus) = nand, Output, smc_nand_data_out[0]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[3] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_05@0XF8000714 + +31:0 + +3fff + + + +202 + +MIO Control for Pin 5 +
+

Register ( slcr )MIO_PIN_06

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_06 +	+0XF8000718 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[12]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[3]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[3]- (SRAM Data) 2= nand, Input, smc_nand_data_in[1]- (NAND Data Bus) = nand, Output, smc_nand_data_out[1]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for mode[4] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_06@0XF8000718 + +31:0 + +3fff + + + +202 + +MIO Control for Pin 6 +
+

Register ( slcr )MIO_PIN_07

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_07 +	+0XF800071C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[13]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_oe_b- (SRAM Output enable) 2= nand, Output, smc_nand_cle- (NAND Command Latch Enable) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= Not Used 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= Not Used +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[0] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_07@0XF800071C + +31:0 + +3fff + + + +200 + +MIO Control for Pin 7 +
+

Register ( slcr )MIO_PIN_08

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_08 +	+0XF8000720 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[14]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_we_b- (SRAM Write enable) 2= nand, Output, smc_nand_re_b- (NAND Read Enable) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled Pull-up disabled by default as this pin is used for vcfg[1] +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_08@0XF8000720 + +31:0 + +3fff + + + +202 + +MIO Control for Pin 8 +
+

Register ( slcr )MIO_PIN_09

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_09 +	+0XF8000724 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[15]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[6]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[6]- (SRAM Data) 2= nand, Input, smc_nand_data_in[4]- (NAND Data Bus) = nand, Output, smc_nand_data_out[4]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= Not Used 3= Not Used 4= Not Used 5= Not Used 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_09@0XF8000724 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 9 +
+

Register ( slcr )MIO_PIN_10

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_10 +	+0XF8000728 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[0]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[7]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[7]- (SRAM Data) 2= nand, Input, smc_nand_data_in[5]- (NAND Data Bus) = nand, Output, smc_nand_data_out[5]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_10@0XF8000728 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 10 +
+

Register ( slcr )MIO_PIN_11

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_11 +	+0XF800072C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[1]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[4]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[4]- (SRAM Data) 2= nand, Input, smc_nand_data_in[6]- (NAND Data Bus) = nand, Output, smc_nand_data_out[6]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_11@0XF800072C + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 11 +
+

Register ( slcr )MIO_PIN_12

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_12 +	+0XF8000730 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[2]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_wait- (SRAM Wait State indicator) 2= nand, Input, smc_nand_data_in[7]- (NAND Data Bus) = nand, Output, smc_nand_data_out[7]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_12@0XF8000730 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 12 +
+

Register ( slcr )MIO_PIN_13

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_13 +	+0XF8000734 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_upper[3]- (QSPI Upper Databus) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_data_in[5]- (SRAM Data) = sram_nor, Output, smc_sram_data_out[5]- (SRAM Data) 2= nand, Input, smc_nand_data_in[3]- (NAND Data Bus) = nand, Output, smc_nand_data_out[3]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_13@0XF8000734 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 13 +
+

Register ( slcr )MIO_PIN_14

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_14 +	+0XF8000738 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Input, smc_sram_fbclk- (SRAM Feedback Clock) 2= nand, Input, smc_nand_busy- (NAND Busy) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_14@0XF8000738 + +31:0 + +3fff + + + +1200 + +MIO Control for Pin 14 +
+

Register ( slcr )MIO_PIN_15

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_15 +	+0XF800073C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_15@0XF800073C + +31:0 + +3f01 + + + +1201 + +MIO Control for Pin 15 +
+

Register ( slcr )MIO_PIN_16

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_16 +	+0XF8000740 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[4]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[1]- (SRAM Address) 2= nand, Input, smc_nand_data_in[8]- (NAND Data Bus) = nand, Output, smc_nand_data_out[8]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_16@0XF8000740 + +31:0 + +3fff + + + +2802 + +MIO Control for Pin 16 +
+

Register ( slcr )MIO_PIN_17

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_17 +	+0XF8000744 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[5]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[2]- (SRAM Address) 2= nand, Input, smc_nand_data_in[9]- (NAND Data Bus) = nand, Output, smc_nand_data_out[9]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_17@0XF8000744 + +31:0 + +3fff + + + +2802 + +MIO Control for Pin 17 +
+

Register ( slcr )MIO_PIN_18

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_18 +	+0XF8000748 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[6]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[3]- (SRAM Address) 2= nand, Input, smc_nand_data_in[10]- (NAND Data Bus) = nand, Output, smc_nand_data_out[10]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_18@0XF8000748 + +31:0 + +3fff + + + +2802 + +MIO Control for Pin 18 +
+

Register ( slcr )MIO_PIN_19

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_19 +	+0XF800074C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[7]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[4]- (SRAM Address) 2= nand, Input, smc_nand_data_in[11]- (NAND Data Bus) = nand, Output, smc_nand_data_out[11]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_19@0XF800074C + +31:0 + +3fff + + + +2802 + +MIO Control for Pin 19 +
+

Register ( slcr )MIO_PIN_20

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_20 +	+0XF8000750 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[5]- (SRAM Address) 2= nand, Input, smc_nand_data_in[12]- (NAND Data Bus) = nand, Output, smc_nand_data_out[12]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_20@0XF8000750 + +31:0 + +3fff + + + +2802 + +MIO Control for Pin 20 +
+

Register ( slcr )MIO_PIN_21

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_21 +	+0XF8000754 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[6]- (SRAM Address) 2= nand, Input, smc_nand_data_in[13]- (NAND Data Bus) = nand, Output, smc_nand_data_out[13]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +1 + +2000 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_21@0XF8000754 + +31:0 + +3fff + + + +2802 + +MIO Control for Pin 21 +
+

Register ( slcr )MIO_PIN_22

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_22 +	+0XF8000758 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[2]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[7]- (SRAM Address) 2= nand, Input, smc_nand_data_in[14]- (NAND Data Bus) = nand, Output, smc_nand_data_out[14]- (NAND Data Bus) 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_22@0XF8000758 + +31:0 + +3fff + + + +803 + +MIO Control for Pin 22 +
+

Register ( slcr )MIO_PIN_23

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_23 +	+0XF800075C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[3]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[8]- (SRAM Address) 2= nand, Input, smc_nand_data_in[15]- (NAND Data Bus) = nand, Output, smc_nand_data_out[15]- (NAND Data Bus) 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_23@0XF800075C + +31:0 + +3fff + + + +803 + +MIO Control for Pin 23 +
+

Register ( slcr )MIO_PIN_24

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_24 +	+0XF8000760 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, traceclk- (Trace Port Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[9]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_24@0XF8000760 + +31:0 + +3fff + + + +803 + +MIO Control for Pin 24 +
+

Register ( slcr )MIO_PIN_25

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_25 +	+0XF8000764 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_ctl, Output, tracectl- (Trace Port Control Signal) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[10]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_25@0XF8000764 + +31:0 + +3fff + + + +803 + +MIO Control for Pin 25 +
+

Register ( slcr )MIO_PIN_26

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_26 +	+0XF8000768 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[0]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[11]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[26]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[26]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_26@0XF8000768 + +31:0 + +3fff + + + +803 + +MIO Control for Pin 26 +
+

Register ( slcr )MIO_PIN_27

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_27 +	+0XF800076C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +1 + +2 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= trace_data, Output, tracedq[1]- (Trace Port Databus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[12]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[27]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[27]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +4 + +800 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_27@0XF800076C + +31:0 + +3fff + + + +803 + +MIO Control for Pin 27 +
+

Register ( slcr )MIO_PIN_28

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_28 +	+0XF8000770 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[13]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[28]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[28]- (GPIO bank 0) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_28@0XF8000770 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 28 +
+

Register ( slcr )MIO_PIN_29

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_29 +	+0XF8000774 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[14]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[29]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[29]- (GPIO bank 0) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_29@0XF8000774 + +31:0 + +3fff + + + +205 + +MIO Control for Pin 29 +
+

Register ( slcr )MIO_PIN_30

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_30 +	+0XF8000778 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[15]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[30]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[30]- (GPIO bank 0) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_30@0XF8000778 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 30 +
+

Register ( slcr )MIO_PIN_31

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_31 +	+0XF800077C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[16]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[31]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[31]- (GPIO bank 0) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_31@0XF800077C + +31:0 + +3fff + + + +205 + +MIO Control for Pin 31 +
+

Register ( slcr )MIO_PIN_32

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_32 +	+0XF8000780 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[17]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_32@0XF8000780 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 32 +
+

Register ( slcr )MIO_PIN_33

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_33 +	+0XF8000784 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[18]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_33@0XF8000784 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 33 +
+

Register ( slcr )MIO_PIN_34

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_34 +	+0XF8000788 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[19]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_34@0XF8000788 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 34 +
+

Register ( slcr )MIO_PIN_35

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_35 +	+0XF800078C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[20]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_35@0XF800078C + +31:0 + +3fff + + + +204 + +MIO Control for Pin 35 +
+

Register ( slcr )MIO_PIN_36

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_36 +	+0XF8000790 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_xcvr_clk_in- (ULPI clock) 1= usb0, Output, usb0_xcvr_clk_out- (ULPI clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[21]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_36@0XF8000790 + +31:0 + +3fff + + + +205 + +MIO Control for Pin 36 +
+

Register ( slcr )MIO_PIN_37

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_37 +	+0XF8000794 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[22]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_37@0XF8000794 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 37 +
+

Register ( slcr )MIO_PIN_38

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_38 +	+0XF8000798 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[23]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_38@0XF8000798 + +31:0 + +3fff + + + +204 + +MIO Control for Pin 38 +
+

Register ( slcr )MIO_PIN_39

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_39 +	+0XF800079C +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control ) +
+L1_SEL + +2:2 + +4 + +1 + +4 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= sram_nor, Output, smc_sram_add[24]- (SRAM Address) 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +0 + +0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_39@0XF800079C + +31:0 + +3fff + + + +204 + +MIO Control for Pin 39 +
+

Register ( slcr )MIO_PIN_40

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_40 +	+0XF80007A0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[4]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_clk_in- (SDSDIO clock) 4= sd0, Output, sd0_clk_out- (SDSDIO clock) 5= spi0, Input, spi0_sclk_in- (SPI Clock) 5= spi0, Output, spi0_sclk_out- (SPI Clock) 6= ttc1, Output, ttc1_wave_out- (TTC waveform clock) 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_40@0XF80007A0 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 40 +
+

Register ( slcr )MIO_PIN_41

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_41 +	+0XF80007A4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_cmd_in- (Command Indicator) 4= sd0, Output, sd0_cmd_out- (Command Indicator) 5= spi0, Input, spi0_mi- (MISO signal) 5= spi0, Output, spi0_so- (MISO signal) 6= ttc1, Input, ttc1_clk_in- (TTC input clock) 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_41@0XF80007A4 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 41 +
+

Register ( slcr )MIO_PIN_42

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_42 +	+0XF80007A8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[0]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[0]- (4-bit Data bus) 5= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 5= spi0, Output, spi0_n_ss_out[0]- (SPI Master Selects) 6= ttc0, Output, ttc0_wave_out- (TTC waveform clock) 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_42@0XF80007A8 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 42 +
+

Register ( slcr )MIO_PIN_43

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_43 +	+0XF80007AC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[1]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[1]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 6= ttc0, Input, ttc0_clk_in- (TTC input clock) 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_43@0XF80007AC + +31:0 + +3fff + + + +280 + +MIO Control for Pin 43 +
+

Register ( slcr )MIO_PIN_44

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_44 +	+0XF80007B0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[0]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd0, Input, sd0_data_in[2]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[2]- (4-bit Data bus) 5= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_44@0XF80007B0 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 44 +
+

Register ( slcr )MIO_PIN_45

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_45 +	+0XF80007B4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[1]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd0, Input, sd0_data_in[3]- (4-bit Data bus) 4= sd0, Output, sd0_data_out[3]- (4-bit Data bus) 5= spi0, Output, spi0_mo- (MOSI signal) 5= spi0, Input, spi0_si- (MOSI signal) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_45@0XF80007B4 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 45 +
+

Register ( slcr )MIO_PIN_46

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_46 +	+0XF80007B8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[2]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_data_in[0]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[0]- (4-bit Data bus) 5= spi1, Output, spi1_mo- (MOSI signal) 5= spi1, Input, spi1_si- (MOSI signal) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_46@0XF80007B8 + +31:0 + +3fff + + + +1221 + +MIO Control for Pin 46 +
+

Register ( slcr )MIO_PIN_47

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_47 +	+0XF80007BC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[3]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +1 + +20 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_cmd_in- (Command Indicator) 4= sd1, Output, sd1_cmd_out- (Command Indicator) 5= spi1, Input, spi1_mi- (MISO signal) 5= spi1, Output, spi1_so- (MISO signal) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_47@0XF80007BC + +31:0 + +3fff + + + +1220 + +MIO Control for Pin 47 +
+

Register ( slcr )MIO_PIN_48

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_48 +	+0XF80007C0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_xcvr_clk_in- (ULPI Clock) 1= usb1, Output, usb1_xcvr_clk_out- (ULPI Clock) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= Not Used 4= sd1, Input, sd1_clk_in- (SDSDIO clock) 4= sd1, Output, sd1_clk_out- (SDSDIO clock) 5= spi1, Input, spi1_sclk_in- (SPI Clock) 5= spi1, Output, spi1_sclk_out- (SPI Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_48@0XF80007C0 + +31:0 + +3fff + + + +2e0 + +MIO Control for Pin 48 +
+

Register ( slcr )MIO_PIN_49

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_49 +	+0XF80007C4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +1 + +1 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[5]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +7 + +e0 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= Not Used 4= sd1, Input, sd1_data_in[1]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[1]- (4-bit Data bus) 5= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 5= spi1, Output, spi1_n_ss_out[0]- (SPI Master Selects) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_49@0XF80007C4 + +31:0 + +3fff + + + +2e1 + +MIO Control for Pin 49 +
+

Register ( slcr )MIO_PIN_50

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_50 +	+0XF80007C8 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[6]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= can0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= sd1, Input, sd1_data_in[2]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[2]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 6= Not Used 7= ua0, Input, ua0_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_50@0XF80007C8 + +31:0 + +3fff + + + +1240 + +MIO Control for Pin 50 +
+

Register ( slcr )MIO_PIN_51

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_51 +	+0XF80007CC +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_data[7]- (ULPI data bus) +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +2 + +40 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= can0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= sd1, Input, sd1_data_in[3]- (4-bit Data bus) 4= sd1, Output, sd1_data_out[3]- (4-bit Data bus) 5= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 6= Not Used 7= ua0, Output, ua0_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +1 + +1000 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_51@0XF80007CC + +31:0 + +3fff + + + +1240 + +MIO Control for Pin 51 +
+

Register ( slcr )MIO_PIN_52

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_52 +	+0XF80007D0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio0_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= can1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signal) 3= wdt, Input, wdt_clk_in- (Watch Dog Timer Input clock) 4= mdio0, Output, gem0_mdc- (MDIO Clock) 5= mdio1, Output, gem1_mdc- (MDIO Clock) 6= Not Used 7= ua1, Output, ua1_txd- (UART transmitter serial output) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_52@0XF80007D0 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 52 +
+

Register ( slcr )MIO_PIN_53

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MIO_PIN_53 +	+0XF80007D4 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+TRI_ENABLE + +0:0 + +1 + +0 + +0 + +Tri-state enable, active high. +
+L0_SEL + +1:1 + +2 + +0 + +0 + +Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used +
+L1_SEL + +2:2 + +4 + +0 + +0 + +Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used +
+L2_SEL + +4:3 + +18 + +0 + +0 + +Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= sdio_pow, Output, sdio1_bus_pow- (SD card bus power) +
+L3_SEL + +7:5 + +e0 + +4 + +80 + +Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= can1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal) 3= wdt, Output, wdt_rst_out- (Watch Dog Timer Output clock) 4= mdio0, Input, gem0_mdio_in- (MDIO Data) 4= mdio0, Output, gem0_mdio_out- (MDIO Data) 5= mdio1, Input, gem1_mdio_in- (MDIO Data) 5= mdio1, Output, gem1_mdio_out- (MDIO Data) 6= Not Used 7= ua1, Input, ua1_rxd- (UART receiver serial input) +
+Speed + +8:8 + +100 + +0 + +0 + +Selects the speed of the I/O when IO_Type=CMOS 0=Slow CMOS 1=Fast CMOS +
+IO_Type + +11:9 + +e00 + +1 + +200 + +Selects the IO Type 0= LVTTL 1= LVCMOS18 2= LVCMOS25 3= LVCMOS33 4= HSTL 5-7= LVCMOS33 +
+PULLUP + +12:12 + +1000 + +0 + +0 + +Controls the use of a pull-up for the associated GPIOB 0= Pull-up disabled 1= Pull-up enabled +
+DisableRcvr + +13:13 + +2000 + +0 + +0 + +Enables the receiver. If the IO is an output only then the receiver can be disabled and save power Only used when IO_Type=HSTL 0= Receiver Enabled 1= Receiver disabled +
+MIO_PIN_53@0XF80007D4 + +31:0 + +3fff + + + +280 + +MIO Control for Pin 53 +
+

Register ( slcr )SD0_WP_CD_SEL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SD0_WP_CD_SEL +	+0XF8000830 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+SDIO0_WP_SEL + +5:0 + +3f + +f + +f + +SDIO0 WP Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
+SDIO0_CD_SEL + +21:16 + +3f0000 + +0 + +0 + +SDIO0 CD Select. 0-53 = Selects matching MIO input however bits 7/8 are not supported and should not be used as they will conflict with the VCFG inputs. 54-63 = Selects the FMIO source +
+SD0_WP_CD_SEL@0XF8000830 + +31:0 + +3f003f + + + +f + +SDIO 0 WP CD select register +
+

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_peripherals_init_data_1_0

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +DDRIOB_DATA0 + +	+0XF8000B48 +	+32 +	+RW +	+0x000000 +	+DDRIOB Data 0 Configuration Register +
+ +DDRIOB_DATA1 + +	+0XF8000B4C +	+32 +	+RW +	+0x000000 +	+DDRIOB Data 1 Configuration Register +
+ +DDRIOB_DIFF0 + +	+0XF8000B50 +	+32 +	+RW +	+0x000000 +	+DDRIOB Differential DQS 0 Configuration Register +
+ +DDRIOB_DIFF1 + +	+0XF8000B54 +	+32 +	+RW +	+0x000000 +	+DDRIOB Differential DQS 1 Configuration Register +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +
+ +Baud_rate_divider_reg0 + +	+0XE0001034 +	+32 +	+RW +	+0x000000 +	+baud rate divider register +
+ +Baud_rate_gen_reg0 + +	+0XE0001018 +	+32 +	+RW +	+0x000000 +	+Baud rate divider register +
+ +Control_reg0 + +	+0XE0001000 +	+32 +	+RW +	+0x000000 +	+UART Control register +
+ +mode_reg0 + +	+0XE0001004 +	+32 +	+RW +	+0x000000 +	+UART Mode register +
+ +Config_reg + +	+0XE000D000 +	+32 +	+RW +	+0x000000 +	+SPI configuration register +
+ +CTRL + +	+0XF8007000 +	+32 +	+RW +	+0x000000 +	+Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable register: Configures the output enables of bank 0 +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable register: Configures the output enables of bank 0 +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +DIRM_0 + +	+0XE000A204 +	+32 +	+RW +	+0x000000 +	+Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +OEN_0 + +	+0XE000A208 +	+32 +	+RW +	+0x000000 +	+Output enable register: Configures the output enables of bank 0 +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+ +MASK_DATA_0_LSW + +	+0XE000A000 +	+32 +	+RW +	+0x000000 +	+Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +

ps7_peripherals_init_data_1_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

DDR TERM/IBUF_DISABLE_MODE SETTINGS

Register ( slcr )DDRIOB_DATA0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA0 +	+0XF8000B48 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DDRIOB_DATA1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DATA1 +	+0XF8000B4C +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DDRIOB_DIFF0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF0 +	+0XF8000B50 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )DDRIOB_DIFF1

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DDRIOB_DIFF1 +	+0XF8000B54 +	+32 +	+rw +	+0x00000000 +	+-- +

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

SRAM/NOR SET OPMODE

TRACE CURRENT PORT SIZE

UART REGISTERS

Register ( slcr )Baud_rate_divider_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Baud_rate_divider_reg0 +	+0XE0001034 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+BDIV + +7:0 + +ff + +6 + +6 + +Baud rate divider value 0 - 3: ignored 4 - 255: Baud rate +
+Baud_rate_divider_reg0@0XE0001034 + +31:0 + +ff + + + +6 + +baud rate divider register +
+

Register ( slcr )Baud_rate_gen_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Baud_rate_gen_reg0 +	+0XE0001018 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+CD + +15:0 + +ffff + +3e + +3e + +Baud Rate Clock Divisor Value 0 = Disables baud_sample 1 = Clock divisor bypass 2 - 65535 = baud_sample value +
+Baud_rate_gen_reg0@0XE0001018 + +31:0 + +ffff + + + +3e + +Baud rate divider register +
+

Register ( slcr )Control_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Control_reg0 +	+0XE0001000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+STPBRK + +8:8 + +100 + +0 + +0 + +Stop transmitter break. 1 = stop transmission of the break. +
+STTBRK + +7:7 + +80 + +0 + +0 + +Start transmitter break 1 = start to transmit a break. Can only be set if STPBRK (Stop transmitter break) is not high. +
+RSTTO + +6:6 + +40 + +0 + +0 + +Restart receiver timeout counter 1 = receiver timeout counter is restarted +
+TXDIS + +5:5 + +20 + +0 + +0 + +Transmit disable. 1, the transmitter is disabled +
+TXEN + +4:4 + +10 + +1 + +10 + +Transmit enable. 1, the transmitter is enabled, provided the TXDIS field is set to 0. +
+RXDIS + +3:3 + +8 + +0 + +0 + +Receive disable. 1= receiver is enabled +
+RXEN + +2:2 + +4 + +1 + +4 + +Receive enable. 1=the receiver logic is enabled, provided RXDIS field is set to 0 +
+TXRES + +1:1 + +2 + +1 + +2 + +Software reset for TX data path. 1=the transmitter logic is reset and all pending transmitter data is discarded self clear +
+RXRES + +0:0 + +1 + +1 + +1 + +Software reset for RX data path 1=receiver logic is reset and all pending receiver data is discarded self clear +
+Control_reg0@0XE0001000 + +31:0 + +1ff + + + +17 + +UART Control register +
+

Register ( slcr )mode_reg0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+mode_reg0 +	+0XE0001004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+IRMODE + +11:11 + +800 + +0 + +0 + +Enable IrDA mode 0 : Default UART mode 1 : Enable IrDA mode +
+UCLKEN + +10:10 + +400 + +0 + +0 + +External uart_clk source select 0 : APB clock, pclk 1 : a user-defined clock +
+CHMODE + +9:8 + +300 + +0 + +0 + +Channel mode 00 = normal 01 = automatic cho 10 = local loopback 11 = remote loopback +
+NBSTOP + +7:6 + +c0 + +0 + +0 + +Number of stop bits 00 = 1 stop bit 01 = 1.5 stop bits 10 = 2 stop bits 11 = reserved +
+PAR + +5:3 + +38 + +4 + +20 + +Parity type select. 000 = even parity 001 = odd parity 010 = forced to 0 parity (space) 011 = forced to 1 parity (mark) 1xx = no parity +
+CHRL + +2:1 + +6 + +0 + +0 + +Character length select 11 = 6 bits 10 = 7 bits 01 / 00 = 8 bits +
+CLKS + +0:0 + +1 + +0 + +0 + +clock source select 1 = clock source is uart_clk/8 0 = clock source is uart_clk +
+mode_reg0@0XE0001004 + +31:0 + +fff + + + +20 + +UART Mode register +
+

QSPI REGISTERS

Register ( slcr )Config_reg

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+Config_reg +	+0XE000D000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+Holdb_dr + +19:19 + +80000 + +1 + +80000 + +Holdb and WPn pins are driven in normal/fast read or dual output/io read by the controller, if set, else external pull-high is required. Both pins are always driven by the controller in quad mode. +
+Config_reg@0XE000D000 + +31:0 + +80000 + + + +80000 + +SPI configuration register +
+

PL POWER ON RESET REGISTERS

Register ( slcr )CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+CTRL +	+0XF8007000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+PCFG_POR_CNT_4K + +29:29 + +20000000 + +0 + +0 + +This is to indicate to the FPGA fabric what timer to use 0 - use 64K timer 1 - use 4K timer +
+CTRL@0XF8007000 + +31:0 + +20000000 + + + +0 + +Control Register : This register defines basic control registers. Some of the register bits can be locked by control bits in the LOCK Register 0x004. +
+

SMC TIMING CALCULATION REGISTER UPDATE

NAND SET CYCLE

OPMODE

DIRECT COMMAND

SRAM/NOR CS0 SET CYCLE

DIRECT COMMAND

NOR CS0 BASE ADDRESS

SRAM/NOR CS1 SET CYCLE

DIRECT COMMAND

NOR CS1 BASE ADDRESS

USB RESET

DIR MODE BANK 0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_0 + +31:0 + +ffffffff + +2880 + +2880 + +Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank +
+DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +2880 + +Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
+

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +ff7f + +ff7f0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +80 + +80 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +ff7f0080 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_0 + +31:0 + +ffffffff + +2880 + +2880 + +Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank +
+OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +2880 + +Output enable register: Configures the output enables of bank 0 +
+

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +ff7f + +ff7f0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +ff7f0000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +ff7f + +ff7f0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +80 + +80 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +ff7f0080 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

ENET RESET

DIR MODE BANK 0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_0 + +31:0 + +ffffffff + +2880 + +2880 + +Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank +
+DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +2880 + +Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
+

DIR MODE BANK 1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +800 + +800 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0800 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE BANK 0

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_0 + +31:0 + +ffffffff + +2880 + +2880 + +Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank +
+OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +2880 + +Output enable register: Configures the output enables of bank 0 +
+

OUTPUT ENABLE BANK 1

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +f7ff + +f7ff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +800 + +800 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +f7ff0800 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

I2C RESET

DIR MODE GPIO BANK0

Register ( slcr )DIRM_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+DIRM_0 +	+0XE000A204 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+DIRECTION_0 + +31:0 + +ffffffff + +2880 + +2880 + +Direction mode for bank 0 0 = input 1 = output Each bit configures the corresponding pin within the 32-bit bank +
+DIRM_0@0XE000A204 + +31:0 + +ffffffff + + + +2880 + +Direction mode configuration register: Configures bank 0 for direction mode, either input or output +
+

DIR MODE GPIO BANK1

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +2000 + +2000 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff2000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

OUTPUT ENABLE

Register ( slcr )OEN_0

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+OEN_0 +	+0XE000A208 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+OP_ENABLE_0 + +31:0 + +ffffffff + +2880 + +2880 + +Output enables for bank 0 0 = disabled 1 = enabled Each bit configures the corresponding pin within the 32-bit bank +
+OEN_0@0XE000A208 + +31:0 + +ffffffff + + + +2880 + +Output enable register: Configures the output enables of bank 0 +
+

OUTPUT ENABLE

MASK_DATA_0_LSW LOW BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +0 + +0 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff0000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW LOW BANK [31:16]

MASK_DATA_1_LSW LOW BANK [47:32]

MASK_DATA_1_MSW LOW BANK [53:48]

ADD 1 MS DELAY

MASK_DATA_0_LSW HIGH BANK [15:0]

Register ( slcr )MASK_DATA_0_LSW

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+MASK_DATA_0_LSW +	+0XE000A000 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+MASK_0_LSW + +31:16 + +ffff0000 + +dfff + +dfff0000 + +Mask values to be applied on writes to the corresponding GPIO pins 0 = pin value is updated 1 = pin is masked Each bit controls the corresponding pin within the 16-bit half-bank Write Only, Read back as zero +
+DATA_0_LSW + +15:0 + +ffff + +2000 + +2000 + +Data values read from or written to the corresponding GPIO pins Each bit controls the corresponding pin within the 16-bit half-bank Note: Bit[6], bit[7] default value = 0 +
+MASK_DATA_0_LSW@0XE000A000 + +31:0 + +ffffffff + + + +dfff2000 + +Maskable single-word-based data access register: Mask and data access for the least significant word of this bank of GPIO pins +
+

MASK_DATA_0_MSW HIGH BANK [31:16]

MASK_DATA_1_LSW HIGH BANK [47:32]

MASK_DATA_1_MSW HIGH BANK [53:48]

+ +

ps7_post_config_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +SLCR_UNLOCK + +	+0XF8000008 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Unlock +
+ +LVL_SHFTR_EN + +	+0XF8000900 +	+32 +	+RW +	+0x000000 +	+Level Shifters Enable +
+ +FPGA_RST_CTRL + +	+0XF8000240 +	+32 +	+RW +	+0x000000 +	+FPGA Software Reset Control +
+ +SLCR_LOCK + +	+0XF8000004 +	+32 +	+WO +	+0x000000 +	+SLCR Write Protection Lock +

ps7_post_config_1_0

+ + + + + + + + + +

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_UNLOCK +	+0XF8000008 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+UNLOCK_KEY + +15:0 + +ffff + +df0d + +df0d + +When write data contains the unlock key value of 0xDF0D, the write protection mode is disabled. All registers defined in SLCR are writeable until locked again through the SLCR_LOCK register. A read of this register always returns zero. +
+SLCR_UNLOCK@0XF8000008 + +31:0 + +ffff + + + +df0d + +SLCR Write Protection Unlock +
+

ENABLING LEVEL SHIFTER

Register ( slcr )LVL_SHFTR_EN

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LVL_SHFTR_EN +	+0XF8000900 +	+32 +	+rw +	+0x00000000 +	+-- +

FPGA RESETS TO 0

Register ( slcr )FPGA_RST_CTRL

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+FPGA_RST_CTRL +	+0XF8000240 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+reserved_3 + +31:25 + +fe000000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FPGA_ACP_RST + +24:24 + +1000000 + +0 + +0 + +FPGA ACP port soft reset. 0 - No reset. 1 - ACP AXI interface reset output asserted. +
+FPGA_AXDS3_RST + +23:23 + +800000 + +0 + +0 + +AXDS3AXI interface soft reset. On assertion of this reset, the AXDS3AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS3AXI interface reset output asserted. +
+FPGA_AXDS2_RST + +22:22 + +400000 + +0 + +0 + +AXDS2 AXI interface soft reset. On assertion of this reset, the AXDS2 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS2 AXI interface reset output asserted. +
+FPGA_AXDS1_RST + +21:21 + +200000 + +0 + +0 + +AXDS1 AXI interface soft reset. On assertion of this reset, the AXDS1 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS1 AXI interface reset output asserted. +
+FPGA_AXDS0_RST + +20:20 + +100000 + +0 + +0 + +AXDS0 AXI interface soft reset. On assertion of this reset, the AXDS0 AXI interface reset output will be asserted. 0 - No reset. 1 - AXDS0 AXI interface reset output asserted. +
+reserved_2 + +19:18 + +c0000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FSSW1_FPGA_RST + +17:17 + +20000 + +0 + +0 + +General purpose FPGA slave interface 1 soft reset. On assertion of this reset, the FPGA slave interface 1 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 1 reset is asserted. +
+FSSW0_FPGA_RST + +16:16 + +10000 + +0 + +0 + +General purpose FPGA slave interface 0 soft reset. On assertion of this reset, the FPGA slave interface 0 reset will be asserted. 0 - No reset. 1 - FPGA slave interface 0 reset is asserted. +
+reserved_1 + +15:14 + +c000 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FPGA_FMSW1_RST + +13:13 + +2000 + +0 + +0 + +General purpose FPGA master interface 1 soft reset. On assertion of this reset, the FPGA master interface 1 reset will be asserted. 0 - No reset. 1 - FPGA master interface 1 reset is asserted. +
+FPGA_FMSW0_RST + +12:12 + +1000 + +0 + +0 + +General purpose FPGA master interface 0 soft reset. On assertion of this reset, the FPGA master interface 0 reset will be asserted. 0 - No reset. 1 - FPGA master interface 0 reset is asserted. +
+FPGA_DMA3_RST + +11:11 + +800 + +0 + +0 + +FPGA DMA 3 peripheral request soft reset. On assertion of this reset, the FPGA DMA 3 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 3 peripheral request reset output asserted. +
+FPGA_DMA2_RST + +10:10 + +400 + +0 + +0 + +FPGA DMA 2 peripheral request soft reset. On assertion of this reset, the FPGA DMA 2 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 2 peripheral request reset output asserted. +
+FPGA_DMA1_RST + +9:9 + +200 + +0 + +0 + +FPGA DMA 1 peripheral request soft reset. On assertion of this reset, the FPGA DMA 1 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 1 peripheral request reset output asserted. +
+FPGA_DMA0_RST + +8:8 + +100 + +0 + +0 + +FPGA DMA 0 peripheral request soft reset. On assertion of this reset, the FPGA DMA 0 peripheral request reset output will be asserted. 0 - No reset. 1 - FPGA DMA 0 peripheral request reset output asserted. +
+reserved + +7:4 + +f0 + +0 + +0 + +Reserved. Writes are ignored, read data is always zero. +
+FPGA3_OUT_RST + +3:3 + +8 + +0 + +0 + +FPGA3software reset. On assertion of this reset, the FPGA 3 top level reset output will be asserted. 0 - No reset. 1 - FPGA 3 top level reset output asserted. +
+FPGA2_OUT_RST + +2:2 + +4 + +0 + +0 + +FPGA2 software reset. On assertion of this reset, the FPGA 2 top level reset output will be asserted. 0 - No reset. 1 - FPGA 2 top level reset output asserted. +
+FPGA1_OUT_RST + +1:1 + +2 + +0 + +0 + +FPGA1 software reset. On assertion of this reset, the FPGA 1 top level reset output will be asserted. 0 - No reset. 1 - FPGA 1 top level reset output asserted. +
+FPGA0_OUT_RST + +0:0 + +1 + +0 + +0 + +FPGA0 software reset. On assertion of this reset, the FPGA 0 top level reset output will be asserted. 0 - No reset. 1 - FPGA 0 top level reset output asserted. +
+FPGA_RST_CTRL@0XF8000240 + +31:0 + +ffffffff + + + +0 + +FPGA Software Reset Control +
+

AFI REGISTERS

AFI0 REGISTERS

AFI1 REGISTERS

AFI2 REGISTERS

AFI3 REGISTERS

LOCK IT BACK

Register ( slcr )SLCR_LOCK

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+SLCR_LOCK +	+0XF8000004 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+LOCK_KEY + +15:0 + +ffff + +767b + +767b + +When write data contains the lock key value of 0x767B, the write protection mode is enabled. All registers defined in SLCR are write protected until unlocked again through the SLCR_UNLOCK register. A read of this register always returns zero. +
+SLCR_LOCK@0XF8000004 + +31:0 + +ffff + + + +767b + +SLCR Write Protection Lock +
+

+ +

ps7_debug_1_0

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+ +LAR + +	+0XF8898FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +
+ +LAR + +	+0XF8899FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +
+ +LAR + +	+0XF8809FB0 +	+32 +	+WO +	+0x000000 +	+Lock Access Register +

ps7_debug_1_0

+ + + + + + + + + +

CROSS TRIGGER CONFIGURATIONS

UNLOCKING CTI REGISTERS

Register ( slcr )LAR

+Register Name +

+Address +

+Width +

+Type +

+Reset Value +

+Description +

+ + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8898FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8899FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8899FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

Register ( slcr )LAR

+ + + + + + + + + + + + + + + + + +

+Register Name +	+Address +	+Width +	+Type +	+Reset Value +	+Description +
+LAR +	+0XF8809FB0 +	+32 +	+rw +	+0x00000000 +	+-- +

+ + + + + + + + + + + + + + + + + + + + + + + + + +
+Field Name + +Bits + +Mask + +Value + +Shifted Value + +Description +
+KEY + +31:0 + +ffffffff + +c5acce55 + +c5acce55 + +Write Access Code. Write behavior depends on PADDRDBG31 pin: - PADDRDBG31=0 (lower 2GB): After reset (via PRESETDBGn), CTI is locked, i.e., writes to all other registers using lower 2GB addresses are ignored. To unlock, 0xC5ACCE55 must be written this register. After the required registers are written, to lock again, write a value other than 0xC5ACCE55 to this register. - PADDRDBG31=1 (upper 2GB): CTI is unlocked when upper 2GB addresses are used to write to all the registers. However, write to this register is ignored using a upper 2GB address! Note: read from this register always returns 0, regardless of PADDRDBG31. +
+LAR@0XF8809FB0 + +31:0 + +ffffffff + + + +c5acce55 + +Lock Access Register +
+

ENABLING CTI MODULES AND CHANNELS

MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS

+ +

+ + + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl new file mode 100644 index 000000000..22b3b691f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/ps7_init.tcl @@ -0,0 +1,887 @@ +proc ps7_pll_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00302301 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00500801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF800015C 0x03F03F33 0x00300E01 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00101400 + mask_write 0XF8000180 0x03F03F30 0x00101400 + mask_write 0XF8000190 0x03F03F30 0x00101400 + mask_write 0XF80001A0 0x03F03F30 0x00101400 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_3_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x0007FFFF 0x00001081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452440D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0x7FDFFFFC 0x27087290 + mask_write 0XF8006024 0x0FFFFFC3 0x00000000 + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x00011054 + mask_write 0XF8006038 0x00000003 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x0003F000 0x0003C000 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x00010000 0x00000000 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x00000200 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000003 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFCF 0x40000001 + mask_write 0XF800611C 0x7FFFFFCF 0x40000001 + mask_write 0XF8006120 0x7FFFFFCF 0x40000001 + mask_write 0XF8006124 0x7FFFFFCF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x0003C81D + mask_write 0XF8006130 0x000FFFFF 0x00036012 + mask_write 0XF8006134 0x000FFFFF 0x0003780C + mask_write 0XF8006138 0x000FFFFF 0x0003B821 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000009D + mask_write 0XF8006158 0x000FFFFF 0x00000092 + mask_write 0XF800615C 0x000FFFFF 0x0000008C + mask_write 0XF8006160 0x000FFFFF 0x000000A1 + mask_write 0XF8006168 0x001FFFFF 0x00000147 + mask_write 0XF800616C 0x001FFFFF 0x0000012D + mask_write 0XF8006170 0x001FFFFF 0x00000133 + mask_write 0XF8006174 0x001FFFFF 0x00000143 + mask_write 0XF800617C 0x000FFFFF 0x000000DD + mask_write 0XF8006180 0x000FFFFF 0x000000D2 + mask_write 0XF8006184 0x000FFFFF 0x000000CC + mask_write 0XF8006188 0x000FFFFF 0x000000E1 + mask_write 0XF8006190 0x6FFFFEFE 0x00040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000703FF 0x000003FF + mask_write 0XF800620C 0x000703FF 0x000003FF + mask_write 0XF8006210 0x000703FF 0x000003FF + mask_write 0XF8006214 0x000703FF 0x000003FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF5 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B00 0x00000071 0x00000001 + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000E09 + mask_write 0XF8000B70 0x00000001 0x00000001 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FEFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001201 + mask_write 0XF8000704 0x00003FFF 0x00001202 + mask_write 0XF8000708 0x00003FFF 0x00000202 + mask_write 0XF800070C 0x00003FFF 0x00000202 + mask_write 0XF8000710 0x00003FFF 0x00000202 + mask_write 0XF8000714 0x00003FFF 0x00000202 + mask_write 0XF8000718 0x00003FFF 0x00000202 + mask_write 0XF800071C 0x00003FFF 0x00000200 + mask_write 0XF8000720 0x00003FFF 0x00000202 + mask_write 0XF8000724 0x00003FFF 0x00001200 + mask_write 0XF8000728 0x00003FFF 0x00001200 + mask_write 0XF800072C 0x00003FFF 0x00001200 + mask_write 0XF8000730 0x00003FFF 0x00001200 + mask_write 0XF8000734 0x00003FFF 0x00001200 + mask_write 0XF8000738 0x00003FFF 0x00001200 + mask_write 0XF800073C 0x00003F01 0x00001201 + mask_write 0XF8000740 0x00003FFF 0x00002802 + mask_write 0XF8000744 0x00003FFF 0x00002802 + mask_write 0XF8000748 0x00003FFF 0x00002802 + mask_write 0XF800074C 0x00003FFF 0x00002802 + mask_write 0XF8000750 0x00003FFF 0x00002802 + mask_write 0XF8000754 0x00003FFF 0x00002802 + mask_write 0XF8000758 0x00003FFF 0x00000803 + mask_write 0XF800075C 0x00003FFF 0x00000803 + mask_write 0XF8000760 0x00003FFF 0x00000803 + mask_write 0XF8000764 0x00003FFF 0x00000803 + mask_write 0XF8000768 0x00003FFF 0x00000803 + mask_write 0XF800076C 0x00003FFF 0x00000803 + mask_write 0XF8000770 0x00003FFF 0x00000204 + mask_write 0XF8000774 0x00003FFF 0x00000205 + mask_write 0XF8000778 0x00003FFF 0x00000204 + mask_write 0XF800077C 0x00003FFF 0x00000205 + mask_write 0XF8000780 0x00003FFF 0x00000204 + mask_write 0XF8000784 0x00003FFF 0x00000204 + mask_write 0XF8000788 0x00003FFF 0x00000204 + mask_write 0XF800078C 0x00003FFF 0x00000204 + mask_write 0XF8000790 0x00003FFF 0x00000205 + mask_write 0XF8000794 0x00003FFF 0x00000204 + mask_write 0XF8000798 0x00003FFF 0x00000204 + mask_write 0XF800079C 0x00003FFF 0x00000204 + mask_write 0XF80007A0 0x00003FFF 0x00000280 + mask_write 0XF80007A4 0x00003FFF 0x00000280 + mask_write 0XF80007A8 0x00003FFF 0x00000280 + mask_write 0XF80007AC 0x00003FFF 0x00000280 + mask_write 0XF80007B0 0x00003FFF 0x00000280 + mask_write 0XF80007B4 0x00003FFF 0x00000280 + mask_write 0XF80007B8 0x00003FFF 0x00001221 + mask_write 0XF80007BC 0x00003FFF 0x00001220 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00001240 + mask_write 0XF80007CC 0x00003FFF 0x00001240 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x0000000F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x000003FF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 +} +proc ps7_post_config_3_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_3_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +proc ps7_pll_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00302301 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00500801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF800015C 0x03F03F33 0x00300E01 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00101400 + mask_write 0XF8000180 0x03F03F30 0x00101400 + mask_write 0XF8000190 0x03F03F30 0x00101400 + mask_write 0XF80001A0 0x03F03F30 0x00101400 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_2_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452440D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x00011054 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF8006078 0x03FFFFFF 0x00466111 + mask_write 0XF800607C 0x000FFFFF 0x00032222 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000003 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x0003C81D + mask_write 0XF8006130 0x000FFFFF 0x00036012 + mask_write 0XF8006134 0x000FFFFF 0x0003780C + mask_write 0XF8006138 0x000FFFFF 0x0003B821 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000009D + mask_write 0XF8006158 0x000FFFFF 0x00000092 + mask_write 0XF800615C 0x000FFFFF 0x0000008C + mask_write 0XF8006160 0x000FFFFF 0x000000A1 + mask_write 0XF8006168 0x001FFFFF 0x00000147 + mask_write 0XF800616C 0x001FFFFF 0x0000012D + mask_write 0XF8006170 0x001FFFFF 0x00000133 + mask_write 0XF8006174 0x001FFFFF 0x00000143 + mask_write 0XF800617C 0x000FFFFF 0x000000DD + mask_write 0XF8006180 0x000FFFFF 0x000000D2 + mask_write 0XF8006184 0x000FFFFF 0x000000CC + mask_write 0XF8006188 0x000FFFFF 0x000000E1 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B00 0x00000303 0x00000001 + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x00007FFF 0x00000E09 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001201 + mask_write 0XF8000704 0x00003FFF 0x00001202 + mask_write 0XF8000708 0x00003FFF 0x00000202 + mask_write 0XF800070C 0x00003FFF 0x00000202 + mask_write 0XF8000710 0x00003FFF 0x00000202 + mask_write 0XF8000714 0x00003FFF 0x00000202 + mask_write 0XF8000718 0x00003FFF 0x00000202 + mask_write 0XF800071C 0x00003FFF 0x00000200 + mask_write 0XF8000720 0x00003FFF 0x00000202 + mask_write 0XF8000724 0x00003FFF 0x00001200 + mask_write 0XF8000728 0x00003FFF 0x00001200 + mask_write 0XF800072C 0x00003FFF 0x00001200 + mask_write 0XF8000730 0x00003FFF 0x00001200 + mask_write 0XF8000734 0x00003FFF 0x00001200 + mask_write 0XF8000738 0x00003FFF 0x00001200 + mask_write 0XF800073C 0x00003F01 0x00001201 + mask_write 0XF8000740 0x00003FFF 0x00002802 + mask_write 0XF8000744 0x00003FFF 0x00002802 + mask_write 0XF8000748 0x00003FFF 0x00002802 + mask_write 0XF800074C 0x00003FFF 0x00002802 + mask_write 0XF8000750 0x00003FFF 0x00002802 + mask_write 0XF8000754 0x00003FFF 0x00002802 + mask_write 0XF8000758 0x00003FFF 0x00000803 + mask_write 0XF800075C 0x00003FFF 0x00000803 + mask_write 0XF8000760 0x00003FFF 0x00000803 + mask_write 0XF8000764 0x00003FFF 0x00000803 + mask_write 0XF8000768 0x00003FFF 0x00000803 + mask_write 0XF800076C 0x00003FFF 0x00000803 + mask_write 0XF8000770 0x00003FFF 0x00000204 + mask_write 0XF8000774 0x00003FFF 0x00000205 + mask_write 0XF8000778 0x00003FFF 0x00000204 + mask_write 0XF800077C 0x00003FFF 0x00000205 + mask_write 0XF8000780 0x00003FFF 0x00000204 + mask_write 0XF8000784 0x00003FFF 0x00000204 + mask_write 0XF8000788 0x00003FFF 0x00000204 + mask_write 0XF800078C 0x00003FFF 0x00000204 + mask_write 0XF8000790 0x00003FFF 0x00000205 + mask_write 0XF8000794 0x00003FFF 0x00000204 + mask_write 0XF8000798 0x00003FFF 0x00000204 + mask_write 0XF800079C 0x00003FFF 0x00000204 + mask_write 0XF80007A0 0x00003FFF 0x00000280 + mask_write 0XF80007A4 0x00003FFF 0x00000280 + mask_write 0XF80007A8 0x00003FFF 0x00000280 + mask_write 0XF80007AC 0x00003FFF 0x00000280 + mask_write 0XF80007B0 0x00003FFF 0x00000280 + mask_write 0XF80007B4 0x00003FFF 0x00000280 + mask_write 0XF80007B8 0x00003FFF 0x00001221 + mask_write 0XF80007BC 0x00003FFF 0x00001220 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00001240 + mask_write 0XF80007CC 0x00003FFF 0x00001240 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x0000000F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 +} +proc ps7_post_config_2_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_2_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +proc ps7_pll_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000110 0x003FFFF0 0x000FA220 + mask_write 0XF8000100 0x0007F000 0x00028000 + mask_write 0XF8000100 0x00000010 0x00000010 + mask_write 0XF8000100 0x00000001 0x00000001 + mask_write 0XF8000100 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000001 + mask_write 0XF8000100 0x00000010 0x00000000 + mask_write 0XF8000120 0x1F003F30 0x1F000200 + mask_write 0XF8000114 0x003FFFF0 0x0012C220 + mask_write 0XF8000104 0x0007F000 0x00020000 + mask_write 0XF8000104 0x00000010 0x00000010 + mask_write 0XF8000104 0x00000001 0x00000001 + mask_write 0XF8000104 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000002 + mask_write 0XF8000104 0x00000010 0x00000000 + mask_write 0XF8000124 0xFFF00003 0x0C200003 + mask_write 0XF8000118 0x003FFFF0 0x001452C0 + mask_write 0XF8000108 0x0007F000 0x0001E000 + mask_write 0XF8000108 0x00000010 0x00000010 + mask_write 0XF8000108 0x00000001 0x00000001 + mask_write 0XF8000108 0x00000001 0x00000000 + mask_poll 0XF800010C 0x00000004 + mask_write 0XF8000108 0x00000010 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_clock_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000128 0x03F03F01 0x00302301 + mask_write 0XF8000138 0x00000011 0x00000001 + mask_write 0XF8000140 0x03F03F71 0x00500801 + mask_write 0XF800014C 0x00003F31 0x00000501 + mask_write 0XF8000150 0x00003F33 0x00001401 + mask_write 0XF8000154 0x00003F33 0x00001402 + mask_write 0XF800015C 0x03F03F33 0x00300E01 + mask_write 0XF8000160 0x007F007F 0x00000000 + mask_write 0XF8000168 0x00003F31 0x00000501 + mask_write 0XF8000170 0x03F03F30 0x00101400 + mask_write 0XF8000180 0x03F03F30 0x00101400 + mask_write 0XF8000190 0x03F03F30 0x00101400 + mask_write 0XF80001A0 0x03F03F30 0x00101400 + mask_write 0XF80001C4 0x00000001 0x00000001 + mask_write 0XF800012C 0x01FFCCCD 0x01ED044D + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_ddr_init_data_1_0 {} { + mask_write 0XF8006000 0x0001FFFF 0x00000080 + mask_write 0XF8006004 0x1FFFFFFF 0x00081081 + mask_write 0XF8006008 0x03FFFFFF 0x03C0780F + mask_write 0XF800600C 0x03FFFFFF 0x02001001 + mask_write 0XF8006010 0x03FFFFFF 0x00014001 + mask_write 0XF8006014 0x001FFFFF 0x0004159B + mask_write 0XF8006018 0xF7FFFFFF 0x452440D2 + mask_write 0XF800601C 0xFFFFFFFF 0x720238E5 + mask_write 0XF8006020 0xFFFFFFFC 0x27287290 + mask_write 0XF8006024 0x0FFFFFFF 0x0000003C + mask_write 0XF8006028 0x00003FFF 0x00002007 + mask_write 0XF800602C 0xFFFFFFFF 0x00000008 + mask_write 0XF8006030 0xFFFFFFFF 0x00040930 + mask_write 0XF8006034 0x13FF3FFF 0x00011054 + mask_write 0XF8006038 0x00001FC3 0x00000000 + mask_write 0XF800603C 0x000FFFFF 0x00000777 + mask_write 0XF8006040 0xFFFFFFFF 0xFFF00000 + mask_write 0XF8006044 0x0FFFFFFF 0x0F666666 + mask_write 0XF8006048 0x3FFFFFFF 0x0003C248 + mask_write 0XF8006050 0xFF0F8FFF 0x77010800 + mask_write 0XF8006058 0x0001FFFF 0x00000101 + mask_write 0XF800605C 0x0000FFFF 0x00005003 + mask_write 0XF8006060 0x000017FF 0x0000003E + mask_write 0XF8006064 0x00021FE0 0x00020000 + mask_write 0XF8006068 0x03FFFFFF 0x00284141 + mask_write 0XF800606C 0x0000FFFF 0x00001610 + mask_write 0XF80060A0 0x00FFFFFF 0x00008000 + mask_write 0XF80060A4 0xFFFFFFFF 0x10200802 + mask_write 0XF80060A8 0x0FFFFFFF 0x0690CB73 + mask_write 0XF80060AC 0x000001FF 0x000001FE + mask_write 0XF80060B0 0x1FFFFFFF 0x1CFFFFFF + mask_write 0XF80060B4 0x000007FF 0x00000200 + mask_write 0XF80060B8 0x01FFFFFF 0x00200066 + mask_write 0XF80060C4 0x00000003 0x00000003 + mask_write 0XF80060C4 0x00000003 0x00000000 + mask_write 0XF80060C8 0x000000FF 0x00000000 + mask_write 0XF80060DC 0x00000001 0x00000000 + mask_write 0XF80060F0 0x0000FFFF 0x00000000 + mask_write 0XF80060F4 0x0000000F 0x00000008 + mask_write 0XF8006114 0x000000FF 0x00000000 + mask_write 0XF8006118 0x7FFFFFFF 0x40000001 + mask_write 0XF800611C 0x7FFFFFFF 0x40000001 + mask_write 0XF8006120 0x7FFFFFFF 0x40000001 + mask_write 0XF8006124 0x7FFFFFFF 0x40000001 + mask_write 0XF800612C 0x000FFFFF 0x0003C81D + mask_write 0XF8006130 0x000FFFFF 0x00036012 + mask_write 0XF8006134 0x000FFFFF 0x0003780C + mask_write 0XF8006138 0x000FFFFF 0x0003B821 + mask_write 0XF8006140 0x000FFFFF 0x00000035 + mask_write 0XF8006144 0x000FFFFF 0x00000035 + mask_write 0XF8006148 0x000FFFFF 0x00000035 + mask_write 0XF800614C 0x000FFFFF 0x00000035 + mask_write 0XF8006154 0x000FFFFF 0x0000009D + mask_write 0XF8006158 0x000FFFFF 0x00000092 + mask_write 0XF800615C 0x000FFFFF 0x0000008C + mask_write 0XF8006160 0x000FFFFF 0x000000A1 + mask_write 0XF8006168 0x001FFFFF 0x00000147 + mask_write 0XF800616C 0x001FFFFF 0x0000012D + mask_write 0XF8006170 0x001FFFFF 0x00000133 + mask_write 0XF8006174 0x001FFFFF 0x00000143 + mask_write 0XF800617C 0x000FFFFF 0x000000DD + mask_write 0XF8006180 0x000FFFFF 0x000000D2 + mask_write 0XF8006184 0x000FFFFF 0x000000CC + mask_write 0XF8006188 0x000FFFFF 0x000000E1 + mask_write 0XF8006190 0xFFFFFFFF 0x10040080 + mask_write 0XF8006194 0x000FFFFF 0x0001FC82 + mask_write 0XF8006204 0xFFFFFFFF 0x00000000 + mask_write 0XF8006208 0x000F03FF 0x000803FF + mask_write 0XF800620C 0x000F03FF 0x000803FF + mask_write 0XF8006210 0x000F03FF 0x000803FF + mask_write 0XF8006214 0x000F03FF 0x000803FF + mask_write 0XF8006218 0x000F03FF 0x000003FF + mask_write 0XF800621C 0x000F03FF 0x000003FF + mask_write 0XF8006220 0x000F03FF 0x000003FF + mask_write 0XF8006224 0x000F03FF 0x000003FF + mask_write 0XF80062A8 0x00000FF7 0x00000000 + mask_write 0XF80062AC 0xFFFFFFFF 0x00000000 + mask_write 0XF80062B0 0x003FFFFF 0x00005125 + mask_write 0XF80062B4 0x0003FFFF 0x000012A8 + mask_poll 0XF8000B74 0x00002000 + mask_write 0XF8006000 0x0001FFFF 0x00000081 + mask_poll 0XF8006054 0x00000007 +} +proc ps7_mio_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B00 0x00000303 0x00000001 + mask_write 0XF8000B40 0x00000FFF 0x00000600 + mask_write 0XF8000B44 0x00000FFF 0x00000600 + mask_write 0XF8000B48 0x00000FFF 0x00000672 + mask_write 0XF8000B4C 0x00000FFF 0x00000672 + mask_write 0XF8000B50 0x00000FFF 0x00000674 + mask_write 0XF8000B54 0x00000FFF 0x00000674 + mask_write 0XF8000B58 0x00000FFF 0x00000600 + mask_write 0XF8000B5C 0xFFFFFFFF 0x0018C61C + mask_write 0XF8000B60 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B64 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B68 0xFFFFFFFF 0x00F9861C + mask_write 0XF8000B6C 0x000073FF 0x00000209 + mask_write 0XF8000B70 0x00000021 0x00000021 + mask_write 0XF8000B70 0x00000021 0x00000020 + mask_write 0XF8000B70 0x07FFFFFF 0x00000823 + mask_write 0XF8000700 0x00003F01 0x00001201 + mask_write 0XF8000704 0x00003FFF 0x00001202 + mask_write 0XF8000708 0x00003FFF 0x00000202 + mask_write 0XF800070C 0x00003FFF 0x00000202 + mask_write 0XF8000710 0x00003FFF 0x00000202 + mask_write 0XF8000714 0x00003FFF 0x00000202 + mask_write 0XF8000718 0x00003FFF 0x00000202 + mask_write 0XF800071C 0x00003FFF 0x00000200 + mask_write 0XF8000720 0x00003FFF 0x00000202 + mask_write 0XF8000724 0x00003FFF 0x00001200 + mask_write 0XF8000728 0x00003FFF 0x00001200 + mask_write 0XF800072C 0x00003FFF 0x00001200 + mask_write 0XF8000730 0x00003FFF 0x00001200 + mask_write 0XF8000734 0x00003FFF 0x00001200 + mask_write 0XF8000738 0x00003FFF 0x00001200 + mask_write 0XF800073C 0x00003F01 0x00001201 + mask_write 0XF8000740 0x00003FFF 0x00002802 + mask_write 0XF8000744 0x00003FFF 0x00002802 + mask_write 0XF8000748 0x00003FFF 0x00002802 + mask_write 0XF800074C 0x00003FFF 0x00002802 + mask_write 0XF8000750 0x00003FFF 0x00002802 + mask_write 0XF8000754 0x00003FFF 0x00002802 + mask_write 0XF8000758 0x00003FFF 0x00000803 + mask_write 0XF800075C 0x00003FFF 0x00000803 + mask_write 0XF8000760 0x00003FFF 0x00000803 + mask_write 0XF8000764 0x00003FFF 0x00000803 + mask_write 0XF8000768 0x00003FFF 0x00000803 + mask_write 0XF800076C 0x00003FFF 0x00000803 + mask_write 0XF8000770 0x00003FFF 0x00000204 + mask_write 0XF8000774 0x00003FFF 0x00000205 + mask_write 0XF8000778 0x00003FFF 0x00000204 + mask_write 0XF800077C 0x00003FFF 0x00000205 + mask_write 0XF8000780 0x00003FFF 0x00000204 + mask_write 0XF8000784 0x00003FFF 0x00000204 + mask_write 0XF8000788 0x00003FFF 0x00000204 + mask_write 0XF800078C 0x00003FFF 0x00000204 + mask_write 0XF8000790 0x00003FFF 0x00000205 + mask_write 0XF8000794 0x00003FFF 0x00000204 + mask_write 0XF8000798 0x00003FFF 0x00000204 + mask_write 0XF800079C 0x00003FFF 0x00000204 + mask_write 0XF80007A0 0x00003FFF 0x00000280 + mask_write 0XF80007A4 0x00003FFF 0x00000280 + mask_write 0XF80007A8 0x00003FFF 0x00000280 + mask_write 0XF80007AC 0x00003FFF 0x00000280 + mask_write 0XF80007B0 0x00003FFF 0x00000280 + mask_write 0XF80007B4 0x00003FFF 0x00000280 + mask_write 0XF80007B8 0x00003FFF 0x00001221 + mask_write 0XF80007BC 0x00003FFF 0x00001220 + mask_write 0XF80007C0 0x00003FFF 0x000002E0 + mask_write 0XF80007C4 0x00003FFF 0x000002E1 + mask_write 0XF80007C8 0x00003FFF 0x00001240 + mask_write 0XF80007CC 0x00003FFF 0x00001240 + mask_write 0XF80007D0 0x00003FFF 0x00000280 + mask_write 0XF80007D4 0x00003FFF 0x00000280 + mask_write 0XF8000830 0x003F003F 0x0000000F + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_peripherals_init_data_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000B48 0x00000180 0x00000180 + mask_write 0XF8000B4C 0x00000180 0x00000180 + mask_write 0XF8000B50 0x00000180 0x00000180 + mask_write 0XF8000B54 0x00000180 0x00000180 + mask_write 0XF8000004 0x0000FFFF 0x0000767B + mask_write 0XE0001034 0x000000FF 0x00000006 + mask_write 0XE0001018 0x0000FFFF 0x0000003E + mask_write 0XE0001000 0x000001FF 0x00000017 + mask_write 0XE0001004 0x00000FFF 0x00000020 + mask_write 0XE000D000 0x00080000 0x00080000 + mask_write 0XF8007000 0x20000000 0x00000000 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xFF7F0080 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xF7FF0800 + mask_write 0XE000A204 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 + mask_write 0XE000A208 0xFFFFFFFF 0x00002880 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF0000 + mask_delay 0XF8F00200 1 + mask_write 0XE000A000 0xFFFFFFFF 0xDFFF2000 +} +proc ps7_post_config_1_0 {} { + mask_write 0XF8000008 0x0000FFFF 0x0000DF0D + mask_write 0XF8000900 0x0000000F 0x0000000F + mask_write 0XF8000240 0xFFFFFFFF 0x00000000 + mask_write 0XF8000004 0x0000FFFF 0x0000767B +} +proc ps7_debug_1_0 {} { + mask_write 0XF8898FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8899FB0 0xFFFFFFFF 0xC5ACCE55 + mask_write 0XF8809FB0 0xFFFFFFFF 0xC5ACCE55 +} +set PCW_SILICON_VER_1_0 "0x0" +set PCW_SILICON_VER_2_0 "0x1" +set PCW_SILICON_VER_3_0 "0x2" +set APU_FREQ 666666666 + + + +proc mask_poll { addr mask } { + set count 1 + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + while { $maskedval == 0 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval & $mask}] + set count [ expr { $count + 1 } ] + if { $count == 100000000 } { + puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask" + break + } + } +} + + + +proc mask_delay { addr val } { + set delay [ get_number_of_cycles_for_delay $val ] + perf_reset_and_start_timer + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + while { $maskedval == 1 } { + set curval "0x[string range [mrd $addr] end-8 end]" + set maskedval [expr {$curval < $delay}] + } + perf_reset_clock +} + +proc ps_version { } { + set si_ver "0x[string range [mrd 0xF8007080] end-8 end]" + set mask_sil_ver "0x[expr {$si_ver >> 28}]" + return $mask_sil_ver; +} + +proc ps7_post_config {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_post_config_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_post_config_2_0 + } else { + ps7_post_config_3_0 + } +} + +proc ps7_debug {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_debug_1_0 + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_debug_2_0 + } else { + ps7_debug_3_0 + } +} + +proc ps7_init {} { + variable PCW_SILICON_VER_1_0 + variable PCW_SILICON_VER_2_0 + variable PCW_SILICON_VER_3_0 + set sil_ver [ps_version] + + if { $sil_ver == $PCW_SILICON_VER_1_0} { + ps7_mio_init_data_1_0 + ps7_pll_init_data_1_0 + ps7_clock_init_data_1_0 + ps7_ddr_init_data_1_0 + ps7_peripherals_init_data_1_0 + #puts "PCW Silicon Version : 1.0" + } elseif { $sil_ver == $PCW_SILICON_VER_2_0 } { + ps7_mio_init_data_2_0 + ps7_pll_init_data_2_0 + ps7_clock_init_data_2_0 + ps7_ddr_init_data_2_0 + ps7_peripherals_init_data_2_0 + #puts "PCW Silicon Version : 2.0" + } else { + ps7_mio_init_data_3_0 + ps7_pll_init_data_3_0 + ps7_clock_init_data_3_0 + ps7_ddr_init_data_3_0 + ps7_peripherals_init_data_3_0 + #puts "PCW Silicon Version : 3.0" + } +} + + +# For delay calculation using global timer + +# start timer + proc perf_start_clock { } { + + #writing SCU_GLOBAL_TIMER_CONTROL register + + mask_write 0xF8F00208 0x00000109 0x00000009 +} + +# stop timer and reset timer count regs + proc perf_reset_clock { } { + perf_disable_clock + mask_write 0xF8F00200 0xFFFFFFFF 0x00000000 + mask_write 0xF8F00204 0xFFFFFFFF 0x00000000 +} + +# Compute mask for given delay in miliseconds +proc get_number_of_cycles_for_delay { delay } { + + # GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) + variable APU_FREQ + return [ expr ($delay * $APU_FREQ /(2 * 1000))] +} + + +# stop timer +proc perf_disable_clock {} { + mask_write 0xF8F00208 0xFFFFFFFF 0x00000000 +} + +proc perf_reset_and_start_timer {} { + perf_reset_clock + perf_start_clock +} + + diff --git a/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml new file mode 100644 index 000000000..3a27714b1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_A9_Zynq_ZC702/ZC702_hw_platform/system.xml @@ -0,0 +1,7184 @@ +ï»¿ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

+Field Name +	+Bits +	+Mask +	+Value +	+Shifted Value +	+Description +
+UNLOCK_KEY +	+15:0 +	+ffff +	+df0d +	+df0d +	+Write the unlock key, 0xDF0D, to enable writes to the slcr registers. All slcr registers, 0xF800_0000 to 0xF800_0B74, are writeable until locked using the SLCR_LOCK register. A read of this register returns zero. +
+SLCR_UNLOCK@0XF8000008 +	+31:0 +	+ffff +	+ +	+df0d +	+SLCR Write Protection Unlock +

404: The requested file cannot be found.

lwIP - A Lightweight TCP/IP Stack

404 - Page not found

Task statistics

Run-time statistics

Introduction

USB Controller Features

Initialization & Configuration

USB Device Endpoints

Interrupt Handling

Data buffer handling

Zero copy

DMA

Introduction

USB Controller Features

Initialization & Configuration

USB Device Endpoints

Interrupt Handling

Data buffer handling

Zero copy

DMA

Zynq Design Summary

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

PLL SLCR REGISTERS

ARM PLL INIT

Register ( slcr )ARM_PLL_CFG

UPDATE FB_DIV

Register ( slcr )ARM_PLL_CTRL

BY PASS PLL

Register ( slcr )ARM_PLL_CTRL

ASSERT RESET

Register ( slcr )ARM_PLL_CTRL

DEASSERT RESET

Register ( slcr )ARM_PLL_CTRL

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

REMOVE PLL BY PASS

Register ( slcr )ARM_PLL_CTRL

Register ( slcr )ARM_CLK_CTRL

DDR PLL INIT

Register ( slcr )DDR_PLL_CFG

UPDATE FB_DIV

Register ( slcr )DDR_PLL_CTRL

BY PASS PLL

Register ( slcr )DDR_PLL_CTRL

ASSERT RESET

Register ( slcr )DDR_PLL_CTRL

DEASSERT RESET

Register ( slcr )DDR_PLL_CTRL

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

REMOVE PLL BY PASS

Register ( slcr )DDR_PLL_CTRL

Register ( slcr )DDR_CLK_CTRL

IO PLL INIT

Register ( slcr )IO_PLL_CFG

UPDATE FB_DIV

Register ( slcr )IO_PLL_CTRL

BY PASS PLL

Register ( slcr )IO_PLL_CTRL

ASSERT RESET

Register ( slcr )IO_PLL_CTRL

DEASSERT RESET

Register ( slcr )IO_PLL_CTRL

CHECK PLL STATUS

Register ( slcr )PLL_STATUS

REMOVE PLL BY PASS

Register ( slcr )IO_PLL_CTRL

LOCK IT BACK

Register ( slcr )SLCR_LOCK

SLCR SETTINGS

Register ( slcr )SLCR_UNLOCK

CLOCK CONTROL SLCR REGISTERS

Register ( slcr )DCI_CLK_CTRL

Register ( slcr )GEM0_RCLK_CTRL

Register ( slcr )GEM0_CLK_CTRL

Register ( slcr )LQSPI_CLK_CTRL

Register ( slcr )SDIO_CLK_CTRL

Register ( slcr )UART_CLK_CTRL