From: Stefano Babic Date: Wed, 9 May 2012 10:07:31 +0000 (+0200) Subject: MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged X-Git-Tag: v2012.07-rc1~144^2~57 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c4559daa9158367878ddb3e115d60d41e0322b1f;p=u-boot MX5: PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH exchanged After an update to the MX51 reference manual (Rev. 5), the values of the PAD_CTL_DRV_VOT_LOW and PAD_CTL_DRV_VOT_HIGH are now clearly wrong: "Bit 13: High / Low Output Voltage Range. This bit selects the output voltage mode for SD2_CMD. 0 High output voltage mode 1 Low output voltage mode" The values are currently negated in code - fixed. Reported-by: David Jander Signed-off-by: Stefano Babic CC: Marek Vasut CC: David Jander Acked-by: David Jander Acked-by: Marek Vasut --- diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h index 760371b48f..e3765a37e3 100644 --- a/arch/arm/include/asm/arch-mx5/iomux.h +++ b/arch/arm/include/asm/arch-mx5/iomux.h @@ -66,8 +66,8 @@ typedef enum iomux_pad_config { PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ - PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ - PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ + PAD_CTL_DRV_VOT_LOW = 0x1 << 13, /* Low voltage mode */ + PAD_CTL_DRV_VOT_HIGH = 0x0 << 13,/* High voltage mode */ } iomux_pad_config_t; /* various IOMUX input functions */