From: David Wu Date: Sat, 13 Jan 2018 06:06:16 +0000 (+0800) Subject: ARM: dts: rk3288: Remove unused LCDC clock assigned X-Git-Tag: v2018.03-rc1~12^2~6 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c513e9e1e6e1ea2aa177aae3b0eb306c949dcd69;p=u-boot ARM: dts: rk3288: Remove unused LCDC clock assigned The LCDC assigned rate is 0, it will make boot error, error log:"pll_para_config: the frequency can not be 0 Hz". Remove them, and the lcdc driver will do the correct clock rate setting. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index da518783e2..2c8a616782 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -604,19 +604,16 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_NPLL>, <&cru ACLK_CPU>, <&cru HCLK_CPU>, <&cru PCLK_CPU>, <&cru ACLK_PERI>, <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <0>, <0>, - <594000000>, <400000000>, + assigned-clock-rates = <594000000>, <400000000>, <500000000>, <300000000>, <150000000>, <75000000>, <300000000>, <150000000>, <75000000>; - assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>; }; grf: syscon@ff770000 {