From: Michal Simek <michal.simek@xilinx.com>
Date: Thu, 7 Apr 2016 13:01:33 +0000 (+0200)
Subject: ARM64: zynqmp: Align register description
X-Git-Tag: v2016.05-rc2~64^2~25
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c588d1544405cba91572583621f5faaa1d56f49a;p=u-boot

ARM64: zynqmp: Align register description

Separate register space and put it on more lines.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index a1804b8da3..e2f7b53858 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -648,7 +648,8 @@
 			interrupts = <0 15 4>;
 			interrupt-parent = <&gic>;
 			num-cs = <1>;
-			reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+			reg = <0x0 0xff0f0000 0x1000>,
+			      <0x0 0xc0000000 0x8000000>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			power-domains = <&pd_qspi>;
@@ -891,7 +892,9 @@
 		xlnx_dp_sub: dp_sub@fd4aa000 {
 			compatible = "xlnx,dp-sub";
 			status = "disabled";
-			reg = <0x0 0xfd4aa000 0x1000>, <0x0 0xfd4ab000 0x1000>, <0x0 0xfd4ac000 0x1000>;
+			reg = <0x0 0xfd4aa000 0x1000>,
+			      <0x0 0xfd4ab000 0x1000>,
+			      <0x0 0xfd4ac000 0x1000>;
 			reg-names = "blend", "av_buf", "aud";
 			xlnx,output-fmt = "rgb";
 			xlnx,vid-fmt = "yuyv";