From: Stefan Agner <stefan.agner@toradex.com>
Date: Mon, 15 Aug 2016 04:33:00 +0000 (-0700)
Subject: arm: cache: add support for LPAE for region D$ behavior
X-Git-Tag: v2016.09~67
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c5b3cabf4a2f78b126a7da92c20b781a52d5307f;p=u-boot

arm: cache: add support for LPAE for region D$ behavior

Add LPAE support for mmu_set_region_dcache_behaviour. The function
is in use in some LPAE capable board such TI DRA7xx or NXP i.MX 7.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3a93..3aabda156b 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,7 +61,11 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
+#ifdef CONFIG_ARMV7_LPAE
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+#else
 	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+#endif
 	unsigned long upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;