From: Kumar Gala Date: Fri, 4 Feb 2011 06:43:34 +0000 (-0600) Subject: powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE X-Git-Tag: v2011.06-rc1~185^2~21 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c657d898bcf95d5af15f081ed9f03e0ea5b1a16e;p=u-boot powerpc/85xx: Specify CONFIG_SYS_FM_MURAM_SIZE CONFIG_SYS_FM_MURAM_SIZE varies from SoC to SoC to specify it in config_mpc85xx.h for those parts with a Frame Manager. Signed-off-by: Kumar Gala --- diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index ac304f30c9..0529632567 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -166,6 +166,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 #elif defined(CONFIG_P1020) #define CONFIG_MAX_CPUS 2 @@ -203,6 +204,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 +#define CONFIG_SYS_FM_MURAM_SIZE 0x10000 /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_P1024) @@ -246,6 +248,7 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -255,11 +258,13 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -271,6 +276,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -290,6 +296,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -299,6 +306,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 +#define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #else #error Processor type not defined for this platform