From: Kumar Gala <galak@kernel.crashing.org>
Date: Thu, 3 Sep 2009 13:41:31 +0000 (-0500)
Subject: ppc/85xx: Fix bug in setup_mp code
X-Git-Tag: v2009.11-rc1~174
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c7259086816405fe0eb77f4dc22e76980a040cef;p=u-boot

ppc/85xx: Fix bug in setup_mp code

Its possible that we try and copy the boot page code out of flash into a
DDR location that doesn't have a TLB cover it.  For example, if we have
3G of DDR we typically only map the first 2G.  In the cases of 4G+ this
wasn't an issue since the reset page TLB mapping covered the last page
of memory which we wanted to copy to.

We now change the physical address of the reset page TLB to map to the
true physical location of the boot page code, copy and than set the
TLB back to its 1:1 mapping of the reset page.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c
index 2df55c71d4..fa65bed083 100644
--- a/cpu/mpc85xx/mp.c
+++ b/cpu/mpc85xx/mp.c
@@ -25,6 +25,7 @@
 #include <ioports.h>
 #include <lmb.h>
 #include <asm/io.h>
+#include <asm/mmu.h>
 #include "mp.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -209,8 +210,33 @@ void setup_mp(void)
 	ulong fixup = (ulong)&__secondary_start_page;
 	u32 bootpg = determine_mp_bootpg();
 
-	memcpy((void *)bootpg, (void *)fixup, 4096);
-	flush_cache(bootpg, 4096);
+	/* look for the tlb covering the reset page, there better be one */
+	int i = find_tlb_idx((void *)0xfffff000, 1);
 
-	pq3_mp_up(bootpg);
+	/* we found a match */
+	if (i != -1) {
+		/* map reset page to bootpg so we can copy code there */
+		disable_tlb(i);
+	
+		set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
+			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+
+		memcpy((void *)0xfffff000, (void *)fixup, 4096);
+		flush_cache(0xfffff000, 4096);
+
+		disable_tlb(i);
+
+		/* setup reset page back to 1:1, we'll use HW boot translation
+		 * to map this where we want
+		 */
+		set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
+			0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
+
+		pq3_mp_up(bootpg);
+	} else {
+		puts("WARNING: No reset page TLB. "
+			"Skipping secondary core setup\n");
+	}
 }