From: Stefan Roese <sr@denx.de>
Date: Thu, 1 Mar 2007 20:16:02 +0000 (+0100)
Subject: Merge with /home/stefan/git/u-boot/denx-merge-sr
X-Git-Tag: v1.3.0-rc1~154
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=c8556d0e0b27c57c0860f55736761a18c7a115f2;p=u-boot

Merge with /home/stefan/git/u-boot/denx-merge-sr
---

c8556d0e0b27c57c0860f55736761a18c7a115f2
diff --cc cpu/ppc4xx/44x_spd_ddr2.c
index fe0f2b6ea4,ab421196b9..35b23152f3
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@@ -44,14 -43,11 +44,14 @@@
  #if defined(CONFIG_SPD_EEPROM) &&				\
  	(defined(CONFIG_440SP) || defined(CONFIG_440SPE))
  
 +/*-----------------------------------------------------------------------------+
 + * Defines
 + *-----------------------------------------------------------------------------*/
  #ifndef	TRUE
- #define TRUE            1
+ #define TRUE		1
  #endif
  #ifndef FALSE
- #define FALSE           0
+ #define FALSE		0
  #endif
  
  #define SDRAM_DDR1	1
@@@ -190,25 -134,18 +190,25 @@@ static void program_initplr(unsigned lo
  static unsigned long is_ecc_enabled(void);
  static void program_ecc(unsigned long *dimm_populated,
  			unsigned char *iic0_dimm_addr,
 -			unsigned long num_dimm_banks);
 +			unsigned long num_dimm_banks,
 +			unsigned long tlb_word2_i_value);
  static void program_ecc_addr(unsigned long start_address,
 -			     unsigned long num_bytes);
 -
 +			     unsigned long num_bytes,
 +			     unsigned long tlb_word2_i_value);
 +static void program_DQS_calibration(unsigned long *dimm_populated,
 +				    unsigned char *iic0_dimm_addr,
 +				    unsigned long num_dimm_banks);
  #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
- static void          test(void);
+ static void	test(void);
  #else
- static void          DQS_calibration_process(void);
+ static void	DQS_calibration_process(void);
  #endif
 -static void program_DQS_calibration(unsigned long *dimm_populated,
 -				    unsigned char *iic0_dimm_addr,
 -				    unsigned long num_dimm_banks);
 +#if defined(DEBUG)
 +static void ppc440sp_sdram_register_dump(void);
 +#endif
 +int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 +void dcbz_area(u32 start_address, u32 num_bytes);
 +void dflush(void);
  
  static u32 mfdcr_any(u32 dcr)
  {
diff --cc cpu/ppc4xx/start.S
index cd2cceced9,200f7b31ad..24b30dfe71
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@@ -1909,50 -1909,7 +1909,50 @@@ pll_wait
  | mftlb1.
  +----------------------------------------------------------------------------*/
  	function_prolog(mftlb1)
-         TLBRE(3,3,0)
+ 	TLBRE(3,3,0)
  	blr
  	function_epilog(mftlb1)
 +
 +/*----------------------------------------------------------------------------+
 +| dcbz_area.
 ++----------------------------------------------------------------------------*/
 +        function_prolog(dcbz_area)
 +        rlwinm. r5,r4,0,27,31
 +        rlwinm  r5,r4,27,5,31
 +        beq     ..d_ra2
 +        addi    r5,r5,0x0001
 +..d_ra2:mtctr   r5
 +..d_ag2:dcbz    r0,r3
 +        addi    r3,r3,32
 +        bdnz    ..d_ag2
 +        sync
 +        blr
 +        function_epilog(dcbz_area)
 +
 +/*----------------------------------------------------------------------------+
 +| dflush.  Assume 32K at vector address is cachable.
 ++----------------------------------------------------------------------------*/
 +        function_prolog(dflush)
 +        mfmsr   r9
 +        rlwinm  r8,r9,0,15,13
 +        rlwinm  r8,r8,0,17,15
 +        mtmsr   r8
 +        addi    r3,r0,0x0000
 +        mtspr   dvlim,r3
 +        mfspr   r3,ivpr
 +        addi    r4,r0,1024
 +        mtctr   r4
 +..dflush_loop:
 +        lwz     r6,0x0(r3)
 +        addi    r3,r3,32
 +        bdnz    ..dflush_loop
 +        addi    r3,r3,-32
 +        mtctr   r4
 +..ag:   dcbf    r0,r3
 +        addi    r3,r3,-32
 +        bdnz    ..ag
 +        sync
 +        mtmsr   r9
 +        blr
 +        function_epilog(dflush)
  #endif /* CONFIG_440 */