From: Ying Zhang <b40530@freescale.com>
Date: Fri, 22 Jan 2016 04:15:12 +0000 (+0800)
Subject: board/freescale/common: Check IR chip mode for VID support
X-Git-Tag: v2016.03-rc1~52^2~1
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=cabe4d2f1970eae618ffac4262b61460b9ad3097;p=u-boot

board/freescale/common: Check IR chip mode for VID support

IR chip on all the boards are required to be used in Intel mode
to support VID. VDD will not be adjusted if IR chip is used in
other modes.

Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c
index f1bed51d30..1ea1b88a10 100644
--- a/board/freescale/common/vid.c
+++ b/board/freescale/common/vid.c
@@ -292,7 +292,7 @@ int adjust_vdd(ulong vdd_override)
 		(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 	u32 fusesr;
-	u8 vid;
+	u8 vid, buf;
 	int vdd_target, vdd_current, vdd_last;
 	int ret, i2caddress;
 	unsigned long vdd_string_override;
@@ -346,6 +346,21 @@ int adjust_vdd(ulong vdd_override)
 		debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
 	}
 
+	/* check IR chip work on Intel mode*/
+	ret = i2c_read(i2caddress,
+		       IR36021_INTEL_MODE_OOFSET,
+		       1, (void *)&buf, 1);
+	if (ret) {
+		printf("VID: failed to read IR chip mode.\n");
+		ret = -1;
+		goto exit;
+	}
+	if ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {
+		printf("VID: IR Chip is not used in Intel mode.\n");
+		ret = -1;
+		goto exit;
+	}
+
 	/* get the voltage ID from fuse status register */
 	fusesr = in_be32(&gur->dcfg_fusesr);
 	/*
diff --git a/board/freescale/common/vid.h b/board/freescale/common/vid.h
index a9c7bb4790..9182c20bc9 100644
--- a/board/freescale/common/vid.h
+++ b/board/freescale/common/vid.h
@@ -11,6 +11,10 @@
 #define IR36021_LOOP1_VOUT_OFFSET	0x9A
 #define IR36021_MFR_ID_OFFSET		0x92
 #define IR36021_MFR_ID			0x43
+#define IR36021_INTEL_MODE_OOFSET	0x14
+#define IR36021_MODE_MASK		0x20
+#define IR36021_INTEL_MODE		0x00
+#define IR36021_AMD_MODE		0x20
 
 /* step the IR regulator in 5mV increments */
 #define IR_VDD_STEP_DOWN		5