From: Ley Foon Tan <ley.foon.tan@intel.com>
Date: Tue, 25 Apr 2017 18:44:42 +0000 (+0800)
Subject: arm: socfpga: Add pinmux for Arria 10
X-Git-Tag: v2017.07-rc1~249^2~6
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=caf36e1edb983a7fa0980e0f86ebd68aa597c85f;p=u-boot

arm: socfpga: Add pinmux for Arria 10

Add pinmux support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index c4949301b7..503b79fec0 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -11,6 +11,7 @@ obj-y	+= misc.o timer.o reset_manager.o clock_manager.o \
 	   fpga_manager.o board.o
 
 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
+					pinmux_arria10.o	\
 					reset_manager_arria10.o
 
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
diff --git a/arch/arm/mach-socfpga/include/mach/pinmux.h b/arch/arm/mach-socfpga/include/mach/pinmux.h
new file mode 100644
index 0000000000..563a3db110
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/pinmux.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+#define PINMUX_UART		0xD
+
+#ifndef __ASSEMBLY__
+int config_dedicated_pins(const void *blob);
+int config_pins(const void *blob, const char *pin_grp);
+#endif
+
+#endif /* _PINMUX_H_ */
diff --git a/arch/arm/mach-socfpga/pinmux_arria10.c b/arch/arm/mach-socfpga/pinmux_arria10.c
new file mode 100644
index 0000000000..69d6a928a0
--- /dev/null
+++ b/arch/arm/mach-socfpga/pinmux_arria10.c
@@ -0,0 +1,96 @@
+/*
+ *  Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#include <asm/arch/pinmux.h>
+#include <asm/io.h>
+#include <common.h>
+#include <fdtdec.h>
+
+static int do_pinctr_pin(const void *blob, int child, const char *node_name)
+{
+	int len;
+	fdt_addr_t base_addr;
+	fdt_size_t size;
+	const u32 *cell;
+	u32 offset, value;
+
+	base_addr = fdtdec_get_addr_size(blob, child, "reg", &size);
+	if (base_addr != FDT_ADDR_T_NONE) {
+		cell = fdt_getprop(blob, child, "pinctrl-single,pins", &len);
+		if (!cell || len <= 0)
+			return -EFAULT;
+
+		debug("%p %d\n", cell, len);
+		for (; len > 0; len -= (2 * sizeof(u32))) {
+			offset = fdt32_to_cpu(*cell++);
+			value = fdt32_to_cpu(*cell++);
+			debug("<0x%x 0x%x>\n", offset, value);
+			writel(value, base_addr + offset);
+		}
+		return 0;
+	}
+	return -EFAULT;
+}
+
+static int do_pinctrl_pins(const void *blob, int node, const char *child_name)
+{
+	int child, len;
+	const char *node_name;
+
+	child = fdt_first_subnode(blob, node);
+
+	if (child < 0)
+		return -EINVAL;
+
+	node_name = fdt_get_name(blob, child, &len);
+
+	while (node_name) {
+		if (!strcmp(child_name, node_name))
+			return do_pinctr_pin(blob, child, node_name);
+
+		child = fdt_next_subnode(blob, child);
+
+		if (child < 0)
+			break;
+
+		node_name = fdt_get_name(blob, child, &len);
+	}
+
+	return -EFAULT;
+}
+
+int config_dedicated_pins(const void *blob)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0,
+			COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+	if (node < 0)
+		return -EINVAL;
+
+	if (do_pinctrl_pins(blob, node, "dedicated_cfg"))
+		return -EFAULT;
+
+	if (do_pinctrl_pins(blob, node, "dedicated"))
+		return -EFAULT;
+
+	return 0;
+}
+
+int config_pins(const void *blob, const char *pin_grp)
+{
+	int node;
+
+	node = fdtdec_next_compatible(blob, 0,
+			COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE);
+	if (node < 0)
+		return -EINVAL;
+
+	if (do_pinctrl_pins(blob, node, pin_grp))
+		return -EFAULT;
+
+	return 0;
+}