From: Marek Vasut Date: Thu, 12 Apr 2018 13:23:46 +0000 (+0200) Subject: clk: renesas: Minor clean up of the R8A7790 clock driver X-Git-Tag: v2018.05-rc2~11^2~9 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=cc64a515465686becc8a991f3e340e8a54496043;p=u-boot clk: renesas: Minor clean up of the R8A7790 clock driver The initconst is not used in U-Boot, drop it. The r8a7790_crit_mod_clks is also not used in U-Boot, so drop it too. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- diff --git a/drivers/clk/renesas/r8a7790-cpg-mssr.c b/drivers/clk/renesas/r8a7790-cpg-mssr.c index 33ab9ad7cc..360c02c5fd 100644 --- a/drivers/clk/renesas/r8a7790-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7790-cpg-mssr.c @@ -40,7 +40,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7790_core_clks[] __initconst = { +static const struct cpg_core_clk r8a7790_core_clks[] = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("usb_extal", CLK_USB_EXTAL), @@ -90,7 +90,7 @@ static const struct cpg_core_clk r8a7790_core_clks[] __initconst = { DEF_DIV6P1("ssprs", R8A7790_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c), }; -static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = { +static const struct mssr_mod_clk r8a7790_mod_clks[] = { DEF_MOD("msiof0", 0, R8A7790_CLK_MP), DEF_MOD("vcp1", 100, R8A7790_CLK_ZS), DEF_MOD("vcp0", 101, R8A7790_CLK_ZS), @@ -209,10 +209,6 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] __initconst = { DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)), }; -static const unsigned int r8a7790_crit_mod_clks[] __initconst = { - MOD_CLK_ID(408), /* INTC-SYS (GIC) */ -}; - /* * CPG Clock Data */ @@ -235,7 +231,7 @@ static const unsigned int r8a7790_crit_mod_clks[] __initconst = { #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \ (((md) & BIT(13)) >> 12) | \ (((md) & BIT(19)) >> 19)) -static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] __initconst = { +static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = { { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 }, { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 }, };