From: rtel Date: Thu, 4 Jun 2015 15:35:12 +0000 (+0000) Subject: Update library files used in STM32F7 demo to the latest version released by ST. X-Git-Tag: V8.2.2~16 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=cc76343cf920df6c1521467fb88ebf69b7995bc2;p=freertos Update library files used in STM32F7 demo to the latest version released by ST. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2351 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c index 88224713e..9c594787c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Blinky_Demo/main_blinky.c @@ -122,7 +122,7 @@ will remove items as they are added, meaning the send task should always find the queue empty. */ #define mainQUEUE_LENGTH ( 1 ) -/* The LED is used to show the demo status. */ +/* The LED is used to show the demo status. (not connected on Rev A hardware) */ #define mainTOGGLE_LED() HAL_GPIO_TogglePin( GPIOF, GPIO_PIN_10 ) /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h index 675a47b1a..615672045 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f746xx.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 28-April-2015 * @brief CMSIS STM32F746xx Device Peripheral Access Layer Header File. * * This file contains: @@ -3810,8 +3810,8 @@ typedef struct #define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C) #define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004) #define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008) -#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000010) -#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000020) +#define FLASH_OPTCR_WWDG_SW ((uint32_t)0x00000010) +#define FLASH_OPTCR_IWDG_SW ((uint32_t)0x00000020) #define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040) #define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080) #define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00) @@ -3832,8 +3832,8 @@ typedef struct #define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000) #define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000) #define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000) -#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x40000000) -#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x80000000) +#define FLASH_OPTCR_IWDG_STDBY ((uint32_t)0x40000000) +#define FLASH_OPTCR_IWDG_STOP ((uint32_t)0x80000000) /******************* Bits definition for FLASH_OPTCR1 register ***************/ #define FLASH_OPTCR1_BOOT_ADD0 ((uint32_t)0x0000FFFF) @@ -8278,7 +8278,7 @@ typedef struct /* USB_OTG */ /* */ /******************************************************************************/ -/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ********************/ #define USB_OTG_GOTGCTL_SRQSCS ((uint32_t)0x00000001) /*!< Session request success */ #define USB_OTG_GOTGCTL_SRQ ((uint32_t)0x00000002) /*!< Session request */ #define USB_OTG_GOTGCTL_VBVALOEN ((uint32_t)0x00000004) /*!< VBUS valid override enable */ @@ -8298,15 +8298,13 @@ typedef struct #define USB_OTG_GOTGCTL_BSESVLD ((uint32_t)0x00080000) /*!< B-session valid */ #define USB_OTG_GOTGCTL_OTGVER ((uint32_t)0x00100000) /*!< OTG version */ -/******************** Bit definition forUSB_OTG_HCFG register ********************/ - +/******************** Bit definition for USB_OTG_HCFG register ********************/ #define USB_OTG_HCFG_FSLSPCS ((uint32_t)0x00000003) /*!< FS/LS PHY clock select */ #define USB_OTG_HCFG_FSLSPCS_0 ((uint32_t)0x00000001) /*!Lib folder. + * - arm_cortexM7lfdp_math.lib (Little endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfdp_math.lib (Big endian and Double Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7lfsp_math.lib (Little endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7bfsp_math.lib (Big endian and Single Precision Floating Point Unit on Cortex-M7) + * - arm_cortexM7l_math.lib (Little endian on Cortex-M7) + * - arm_cortexM7b_math.lib (Big endian on Cortex-M7) * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0 / CortexM0+) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M0 / CortexM0+) * * The library functions are declared in the public file arm_math.h which is placed in the Include folder. * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * public header file arm_math.h for Cortex-M7/M4/M3/M0/M0+ with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM7 or ARM_MATH_CM4 or ARM_MATH_CM3 or * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. * * Examples @@ -89,17 +95,17 @@ * Toolchain Support * ------------ * - * The library has been developed and tested with MDK-ARM version 4.60. + * The library has been developed and tested with MDK-ARM version 5.14.0.0 * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. * * Building the Library * ------------ * * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvproj + * - arm_cortexM_math.uvprojx * * - * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. + * The libraries can be built by opening the arm_cortexM_math.uvprojx project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. * * Pre-processor Macros * ------------ @@ -125,7 +131,8 @@ * - ARM_MATH_CMx: * * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * and ARM_MATH_CM0 for building library on Cortex-M0 target, ARM_MATH_CM0PLUS for building library on Cortex-M0+ target, and + * ARM_MATH_CM7 for building the library on cortex-M7. * * - __FPU_PRESENT: * @@ -151,7 +158,7 @@ * Copyright Notice * ------------ * - * Copyright (C) 2010-2014 ARM Limited. All rights reserved. + * Copyright (C) 2010-2015 ARM Limited. All rights reserved. */ @@ -400,19 +407,22 @@ extern "C" * @brief definition to read/write two 16 bit values. */ #if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED __attribute__((unused)) #elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed + #define __SIMD32_TYPE int32_t __packed + #define CMSIS_UNUSED #elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED __attribute__((unused)) #elif defined __CSMC__ /* Cosmic */ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t + #define __SIMD32_TYPE int32_t + #define CMSIS_UNUSED +#elif defined __TASKING__ + #define __SIMD32_TYPE __unaligned int32_t + #define CMSIS_UNUSED #else -#error Unknown compiler + #error Unknown compiler #endif #define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) @@ -506,11 +516,12 @@ extern "C" } -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif +//#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) +//#define __CLZ __clz +//#endif -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) +//note: function can be removed when all toolchain support __CLZ for Cortex-M0 +#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ) static __INLINE uint32_t __CLZ( q31_t data); @@ -6090,7 +6101,7 @@ void arm_rfft_fast_f32( float32_t in, float32_t * pOut) { - if(in > 0) + if(in >= 0.0f) { // #if __FPU_USED @@ -7522,6 +7533,13 @@ void arm_rfft_fast_f32( #define IAR_ONLY_LOW_OPTIMIZATION_ENTER #define IAR_ONLY_LOW_OPTIMIZATION_EXIT +#elif defined(__TASKING__) // TASKING + +#define LOW_OPTIMIZATION_ENTER +#define LOW_OPTIMIZATION_EXIT +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + #endif diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0.h index dbc4e22d4..1110d17a3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm0.h * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -225,14 +225,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -241,6 +234,19 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -254,6 +260,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -262,16 +272,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -280,6 +283,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -287,14 +309,17 @@ typedef union { struct { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + /*@} end of group CMSIS_CORE */ @@ -358,7 +383,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -386,7 +411,7 @@ typedef struct #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Application Interrupt and Reset Control Register Definitions */ #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ @@ -455,15 +480,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -473,7 +498,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -530,9 +555,9 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable External Interrupt @@ -543,7 +568,7 @@ typedef struct */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -555,7 +580,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -571,7 +596,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -583,7 +608,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -595,7 +620,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -610,12 +635,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } } @@ -633,10 +660,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } } @@ -648,10 +677,10 @@ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -684,15 +713,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0plus.h index 4d7facfa0..62e914b50 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0plus.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm0plus.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm0plus.h * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -236,14 +236,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -252,6 +245,19 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -265,6 +271,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -273,16 +283,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -291,6 +294,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -300,12 +322,18 @@ typedef union { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -373,7 +401,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -401,7 +429,7 @@ typedef struct #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ #if (__VTOR_PRESENT == 1) /* SCB Interrupt Control State Register Definitions */ @@ -476,15 +504,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -494,7 +522,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -524,7 +552,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -534,11 +562,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ @@ -548,7 +576,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -579,7 +607,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -641,9 +669,9 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable External Interrupt @@ -654,7 +682,7 @@ typedef struct */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -666,7 +694,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -682,7 +710,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -694,7 +722,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -706,7 +734,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -721,12 +749,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } } @@ -744,10 +774,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } } @@ -759,10 +791,10 @@ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -795,15 +827,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h index d41ac3f0b..d324f9b78 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm3.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm3.h * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -232,13 +232,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -248,6 +242,22 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -261,6 +271,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -269,13 +283,7 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ @@ -287,6 +295,31 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -296,12 +329,18 @@ typedef union { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -332,7 +371,7 @@ typedef struct /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ @@ -384,7 +423,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -415,7 +454,7 @@ typedef struct #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #if (__CM3_REV < 0x0201) /* core r2p1 */ @@ -449,7 +488,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ @@ -478,7 +517,7 @@ typedef struct #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ @@ -521,7 +560,7 @@ typedef struct #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ @@ -531,7 +570,7 @@ typedef struct #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ @@ -557,7 +596,7 @@ typedef struct #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ @@ -583,7 +622,7 @@ typedef struct /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ @@ -594,7 +633,7 @@ typedef struct #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -626,15 +665,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -644,7 +683,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -695,7 +734,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ @@ -723,19 +762,19 @@ typedef struct #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ @@ -745,7 +784,7 @@ typedef struct #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ @@ -838,31 +877,31 @@ typedef struct #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ @@ -890,7 +929,7 @@ typedef struct #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ @@ -933,11 +972,11 @@ typedef struct /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ @@ -950,7 +989,7 @@ typedef struct #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ @@ -961,7 +1000,7 @@ typedef struct /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ @@ -983,11 +1022,11 @@ typedef struct #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1009,15 +1048,15 @@ typedef struct #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ @@ -1036,15 +1075,15 @@ typedef struct #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1080,7 +1119,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -1090,11 +1129,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ @@ -1104,7 +1143,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -1135,7 +1174,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -1192,14 +1231,14 @@ typedef struct #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ @@ -1239,7 +1278,7 @@ typedef struct #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ @@ -1311,13 +1350,13 @@ typedef struct __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -1330,7 +1369,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1342,7 +1381,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1354,7 +1393,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1370,7 +1409,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1382,7 +1421,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1394,7 +1433,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1409,7 +1448,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1424,10 +1463,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1445,10 +1486,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } } @@ -1466,16 +1509,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } @@ -1494,15 +1537,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } @@ -1512,13 +1555,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1551,15 +1594,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1591,11 +1634,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; } return (ch); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm4.h index 827dc3847..544d41484 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm4.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm4.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm4.h * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -279,13 +279,9 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -295,6 +291,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16 /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -308,6 +323,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -316,13 +335,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ @@ -334,6 +349,34 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -349,6 +392,16 @@ typedef union uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -379,7 +432,7 @@ typedef struct /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ @@ -431,7 +484,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -462,7 +515,7 @@ typedef struct #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ @@ -488,7 +541,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ @@ -517,7 +570,7 @@ typedef struct #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ @@ -560,7 +613,7 @@ typedef struct #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ @@ -570,7 +623,7 @@ typedef struct #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ @@ -596,7 +649,7 @@ typedef struct #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ @@ -618,7 +671,7 @@ typedef struct /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ @@ -634,7 +687,7 @@ typedef struct #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -666,15 +719,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -684,7 +737,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -735,7 +788,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ @@ -763,19 +816,19 @@ typedef struct #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ @@ -785,7 +838,7 @@ typedef struct #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ @@ -878,31 +931,31 @@ typedef struct #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ @@ -930,7 +983,7 @@ typedef struct #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ @@ -973,11 +1026,11 @@ typedef struct /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ @@ -990,7 +1043,7 @@ typedef struct #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ @@ -1001,7 +1054,7 @@ typedef struct /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ @@ -1023,11 +1076,11 @@ typedef struct #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1049,15 +1102,15 @@ typedef struct #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ @@ -1076,15 +1129,15 @@ typedef struct #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1120,7 +1173,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -1130,11 +1183,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ @@ -1144,7 +1197,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -1175,7 +1228,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -1226,7 +1279,7 @@ typedef struct #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ @@ -1268,7 +1321,7 @@ typedef struct #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ @@ -1281,7 +1334,7 @@ typedef struct #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /*@} end of group CMSIS_FPU */ #endif @@ -1338,14 +1391,14 @@ typedef struct #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ @@ -1385,7 +1438,7 @@ typedef struct #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ @@ -1462,13 +1515,13 @@ typedef struct __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -1481,7 +1534,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1493,8 +1546,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1506,7 +1558,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1522,7 +1574,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1534,7 +1586,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1546,7 +1598,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1561,7 +1613,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1576,10 +1628,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1597,10 +1651,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } } @@ -1618,16 +1674,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } @@ -1646,15 +1702,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } @@ -1664,13 +1720,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1703,15 +1759,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1743,11 +1799,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; } return (ch); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm7.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm7.h index 64436103b..cb19b9fac 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm7.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cm7.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cm7.h * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 01. September 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -294,13 +294,9 @@ typedef union { struct { -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -310,6 +306,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16 /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -323,6 +338,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -331,13 +350,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x07) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ @@ -349,6 +364,34 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16 /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -364,6 +407,16 @@ typedef union uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2 /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -394,7 +447,7 @@ typedef struct /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ @@ -444,7 +497,7 @@ typedef struct __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ uint32_t RESERVED6[1]; __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ @@ -475,7 +528,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -506,7 +559,7 @@ typedef struct #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ @@ -532,7 +585,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ @@ -570,7 +623,7 @@ typedef struct #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ @@ -613,7 +666,7 @@ typedef struct #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ @@ -623,7 +676,7 @@ typedef struct #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ @@ -649,7 +702,7 @@ typedef struct #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /* Cache Level ID register */ #define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ @@ -672,7 +725,7 @@ typedef struct #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ #define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ /* Cache Size ID Register */ #define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ @@ -694,31 +747,31 @@ typedef struct #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ #define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ /* Cache Size Selection Register */ -#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ +#define SCB_CSSELR_LEVEL_Pos 1 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ #define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ /* SCB Software Triggered Interrupt Register */ #define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ /* Instruction Tightly-Coupled Memory Control Register*/ #define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ #define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1FFUL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ #define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1FFUL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ #define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1FFUL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ /* Data Tightly-Coupled Memory Control Registers */ #define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ @@ -731,14 +784,14 @@ typedef struct #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ #define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ /* AHBP Control Register */ #define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ #define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ /* L1 Cache Control Register */ #define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ @@ -748,7 +801,7 @@ typedef struct #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ #define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ /* AHBS control register */ #define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ @@ -758,7 +811,7 @@ typedef struct #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ #define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ /* Auxiliary Bus Fault Status Register */ #define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ @@ -777,7 +830,7 @@ typedef struct #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ #define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ /*@} end of group CMSIS_SCB */ @@ -799,7 +852,7 @@ typedef struct /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ @@ -815,7 +868,7 @@ typedef struct #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -847,15 +900,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -865,7 +918,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -916,7 +969,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ @@ -944,19 +997,19 @@ typedef struct #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ @@ -966,7 +1019,7 @@ typedef struct #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ @@ -1062,31 +1115,31 @@ typedef struct #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ @@ -1114,7 +1167,7 @@ typedef struct #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ @@ -1157,11 +1210,11 @@ typedef struct /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ @@ -1174,7 +1227,7 @@ typedef struct #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ @@ -1185,7 +1238,7 @@ typedef struct /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ @@ -1207,11 +1260,11 @@ typedef struct #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -1233,15 +1286,15 @@ typedef struct #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ @@ -1260,15 +1313,15 @@ typedef struct #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1304,7 +1357,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -1314,11 +1367,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ @@ -1328,7 +1381,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -1359,7 +1412,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -1411,7 +1464,7 @@ typedef struct #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ /* Floating-Point Context Address Register */ #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ @@ -1453,7 +1506,7 @@ typedef struct #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ /* Media and FP Feature Register 1 */ #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ @@ -1466,7 +1519,7 @@ typedef struct #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ /* Media and FP Feature Register 2 */ @@ -1525,14 +1578,14 @@ typedef struct #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ @@ -1572,7 +1625,7 @@ typedef struct #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ @@ -1649,13 +1702,13 @@ typedef struct __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -1668,7 +1721,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1680,8 +1733,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1693,7 +1745,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1709,7 +1761,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1721,7 +1773,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1733,7 +1785,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1748,7 +1800,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1763,10 +1815,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + if((int32_t)IRQn < 0) { + SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1784,10 +1838,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } } @@ -1805,16 +1861,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } @@ -1833,15 +1889,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } @@ -1851,18 +1907,52 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ +/* ########################## FPU functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \fn uint32_t SCB_GetFPUType(void) + \brief get FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & 0x00000FF0UL) == 0x220UL) { + return 2UL; // Double + Single precision FPU + } else if ((mvfr0 & 0x00000FF0UL) == 0x020UL) { + return 1UL; // Single precision FPU + } else { + return 0UL; // No FPU + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + /* ########################## Cache functions #################################### */ /** \ingroup CMSIS_Core_FunctionInterface \defgroup CMSIS_Core_CacheFunctions Cache Functions @@ -1873,20 +1963,20 @@ __STATIC_INLINE void NVIC_SystemReset(void) /* Cache Size ID Register Macros */ #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) -#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) /*>> SCB_CCSIDR_LINESIZE_Pos*/ ) /** \brief Enable I-Cache The function turns on I-Cache */ -__STATIC_INLINE void SCB_EnableICache(void) +__STATIC_INLINE void SCB_EnableICache (void) { #if (__ICACHE_PRESENT == 1) __DSB(); __ISB(); - SCB->ICIALLU = 0; // invalidate I-Cache - SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + SCB->ICIALLU = 0UL; // invalidate I-Cache + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; // enable I-Cache __DSB(); __ISB(); #endif @@ -1897,13 +1987,13 @@ __STATIC_INLINE void SCB_EnableICache(void) The function turns off I-Cache */ -__STATIC_INLINE void SCB_DisableICache(void) +__STATIC_INLINE void SCB_DisableICache (void) { #if (__ICACHE_PRESENT == 1) __DSB(); __ISB(); - SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache - SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0UL; // invalidate I-Cache __DSB(); __ISB(); #endif @@ -1914,12 +2004,12 @@ __STATIC_INLINE void SCB_DisableICache(void) The function invalidates I-Cache */ -__STATIC_INLINE void SCB_InvalidateICache(void) +__STATIC_INLINE void SCB_InvalidateICache (void) { #if (__ICACHE_PRESENT == 1) __DSB(); __ISB(); - SCB->ICIALLU = 0; + SCB->ICIALLU = 0UL; __DSB(); __ISB(); #endif @@ -1930,22 +2020,23 @@ __STATIC_INLINE void SCB_InvalidateICache(void) The function turns on D-Cache */ -__STATIC_INLINE void SCB_EnableDCache(void) +__STATIC_INLINE void SCB_EnableDCache (void) { #if (__DCACHE_PRESENT == 1) uint32_t ccsidr, sshift, wshift, sw; uint32_t sets, ways; + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); __DSB(); - do { // invalidate D-Cache - int32_t tmpways = ways; + do { // invalidate D-Cache + uint32_t tmpways = ways; do { sw = ((tmpways << wshift) | (sets << sshift)); SCB->DCISW = sw; @@ -1953,7 +2044,7 @@ __STATIC_INLINE void SCB_EnableDCache(void) } while(sets--); __DSB(); - SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; // enable D-Cache __DSB(); __ISB(); @@ -1965,24 +2056,25 @@ __STATIC_INLINE void SCB_EnableDCache(void) The function turns off D-Cache */ -__STATIC_INLINE void SCB_DisableDCache(void) +__STATIC_INLINE void SCB_DisableDCache (void) { #if (__DCACHE_PRESENT == 1) uint32_t ccsidr, sshift, wshift, sw; uint32_t sets, ways; + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); __DSB(); - SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; // disable D-Cache do { // clean & invalidate D-Cache - int32_t tmpways = ways; + uint32_t tmpways = ways; do { sw = ((tmpways << wshift) | (sets << sshift)); SCB->DCCISW = sw; @@ -1992,7 +2084,7 @@ __STATIC_INLINE void SCB_DisableDCache(void) __DSB(); __ISB(); - #endif + #endif } @@ -2000,22 +2092,23 @@ __STATIC_INLINE void SCB_DisableDCache(void) The function invalidates D-Cache */ -__STATIC_INLINE void SCB_InvalidateDCache(void) +__STATIC_INLINE void SCB_InvalidateDCache (void) { #if (__DCACHE_PRESENT == 1) uint32_t ccsidr, sshift, wshift, sw; uint32_t sets, ways; + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); __DSB(); do { // invalidate D-Cache - int32_t tmpways = ways; + uint32_t tmpways = ways; do { sw = ((tmpways << wshift) | (sets << sshift)); SCB->DCISW = sw; @@ -2024,7 +2117,7 @@ __STATIC_INLINE void SCB_InvalidateDCache(void) __DSB(); __ISB(); - #endif + #endif } @@ -2032,22 +2125,23 @@ __STATIC_INLINE void SCB_InvalidateDCache(void) The function cleans D-Cache */ -__STATIC_INLINE void SCB_CleanDCache(void) +__STATIC_INLINE void SCB_CleanDCache (void) { #if (__DCACHE_PRESENT == 1) uint32_t ccsidr, sshift, wshift, sw; uint32_t sets, ways; + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); __DSB(); do { // clean D-Cache - int32_t tmpways = ways; + uint32_t tmpways = ways; do { sw = ((tmpways << wshift) | (sets << sshift)); SCB->DCCSW = sw; @@ -2056,7 +2150,7 @@ __STATIC_INLINE void SCB_CleanDCache(void) __DSB(); __ISB(); - #endif + #endif } @@ -2064,22 +2158,23 @@ __STATIC_INLINE void SCB_CleanDCache(void) The function cleans and Invalidates D-Cache */ -__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +__STATIC_INLINE void SCB_CleanInvalidateDCache (void) { #if (__DCACHE_PRESENT == 1) uint32_t ccsidr, sshift, wshift, sw; uint32_t sets, ways; + SCB->CSSELR = (0UL << 1) | 0UL; // Level 1 data cache ccsidr = SCB->CCSIDR; - sets = CCSIDR_SETS(ccsidr); - sshift = CCSIDR_LSSHIFT(ccsidr) + 4; - ways = CCSIDR_WAYS(ccsidr); - wshift = __CLZ(ways) & 0x1f; + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + sshift = (uint32_t)(CCSIDR_LSSHIFT(ccsidr) + 4UL); + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + wshift = (uint32_t)((uint32_t)__CLZ(ways) & 0x1FUL); __DSB(); do { // clean & invalidate D-Cache - int32_t tmpways = ways; + uint32_t tmpways = ways; do { sw = ((tmpways << wshift) | (sets << sshift)); SCB->DCCISW = sw; @@ -2088,7 +2183,88 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) __DSB(); __ISB(); - #endif + #endif +} + + +/** + \fn void SCB_InvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) + \brief D-Cache Invalidate by address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t)addr; + uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + + __DSB(); + + while (op_size > 0) { + SCB->DCIMVAC = op_addr; + op_addr += linesize; + op_size -= (int32_t)linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \fn void SCB_CleanDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) + \brief D-Cache Clean by address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + + __DSB(); + + while (op_size > 0) { + SCB->DCCMVAC = op_addr; + op_addr += linesize; + op_size -= (int32_t)linesize; + } + + __DSB(); + __ISB(); + #endif +} + + +/** + \fn void SCB_CleanInvalidateDCache_by_Addr(volatile uint32_t *addr, int32_t dsize) + \brief D-Cache Clean and Invalidate by address + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if (__DCACHE_PRESENT == 1) + int32_t op_size = dsize; + uint32_t op_addr = (uint32_t) addr; + uint32_t linesize = 32UL; // in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) + + __DSB(); + + while (op_size > 0) { + SCB->DCCIMVAC = op_addr; + op_addr += linesize; + op_size -= (int32_t)linesize; + } + + __DSB(); + __ISB(); + #endif } @@ -2122,15 +2298,15 @@ __STATIC_INLINE void SCB_CleanInvalidateDCache(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -2162,11 +2338,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; } return (ch); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmFunc.h index a1bd88c2c..e3c057e65 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmFunc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmFunc.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_cmFunc.h * @brief CMSIS Cortex-M Core Function Access Header File - * @version V4.00 - * @date 28. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -242,6 +242,20 @@ __STATIC_INLINE void __set_BASEPRI(uint32_t basePri) } +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xff); +} + + /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. @@ -518,7 +532,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) { uint32_t result; - __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); return(result); } @@ -535,6 +549,19 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t v } +/** \brief Set Base Priority with condition + + This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + /** \brief Get Fault Mask This function returns the current value of the Fault Mask register. diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmInstr.h index cabf4a02d..c8e045f56 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmInstr.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmInstr.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cmInstr.h * @brief CMSIS Cortex-M Core Instruction Access Header File - * @version V4.00 - * @date 28. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * @@ -89,24 +89,33 @@ so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -#define __ISB() __isb(0xF) - +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0) /** \brief Data Synchronization Barrier This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -#define __DSB() __dsb(0xF) - +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0) /** \brief Data Memory Barrier This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -#define __DMB() __dmb(0xF) - +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0) /** \brief Reverse byte order (32 bit) @@ -171,8 +180,6 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #define __BKPT(value) __breakpoint(value) -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - /** \brief Reverse bit order of value This function reverses the bit order of the given value. @@ -180,8 +187,38 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in \param [in] value Value to reverse \return Reversed value */ -#define __RBIT __rbit +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero + return(result); +} +#endif + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) /** \brief LDR Exclusive (8 bit) @@ -279,19 +316,10 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in #define __USAT __usat -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - /** \brief Rotate Right with Extend (32 bit) - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value @@ -385,7 +413,7 @@ __attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint3 No Operation does nothing. This instruction can be used for code alignment purposes. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) { __ASM volatile ("nop"); } @@ -396,7 +424,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) { __ASM volatile ("wfi"); } @@ -407,7 +435,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) { __ASM volatile ("wfe"); } @@ -417,7 +445,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) Send Event is a hint instruction. It causes an event to be signaled to the CPU. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) { __ASM volatile ("sev"); } @@ -429,9 +457,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) { - __ASM volatile ("isb"); + __ASM volatile ("isb 0xF":::"memory"); } @@ -440,9 +468,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) This function acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) { - __ASM volatile ("dsb"); + __ASM volatile ("dsb 0xF":::"memory"); } @@ -451,9 +479,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) This function ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) { - __ASM volatile ("dmb"); + __ASM volatile ("dmb 0xF":::"memory"); } @@ -464,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) return __builtin_bswap32(value); @@ -484,7 +512,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) { uint32_t result; @@ -500,7 +528,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) { #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) return (short)__builtin_bswap16(value); @@ -521,9 +549,9 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value \param [in] value Number of Bits to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) { - return (op1 >> op2) | (op1 << (32 - op2)); + return (op1 >> op2) | (op1 << (32 - op2)); } @@ -538,8 +566,6 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, #define __BKPT(value) __ASM volatile ("bkpt "#value) -#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) - /** \brief Reverse bit order of value This function reverses the bit order of the given value. @@ -547,15 +573,40 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, \param [in] value Value to reverse \return Reversed value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); - return(result); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; // extra shift needed at end + + result = value; // r will be reversed bits of v; first get LSB of v + for (value >>= 1; value; value >>= 1) + { + result <<= 1; + result |= value & 1; + s--; + } + result <<= s; // shift when v's highest bits are zero +#endif + return(result); } +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) + /** \brief LDR Exclusive (8 bit) This function executes a exclusive LDR instruction for 8 bit value. @@ -563,7 +614,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) { uint32_t result; @@ -586,7 +637,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) { uint32_t result; @@ -609,7 +660,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile ui \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) { uint32_t result; @@ -627,7 +678,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) { uint32_t result; @@ -645,7 +696,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) { uint32_t result; @@ -663,7 +714,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va \return 0 Function succeeded \return 1 Function failed */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) { uint32_t result; @@ -677,7 +728,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va This function removes the exclusive lock which is created by LDREX. */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) { __ASM volatile ("clrex" ::: "memory"); } @@ -715,30 +766,15 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) }) -/** \brief Count leading zeros - - This function counts the number of leading zeros of a data value. - - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - /** \brief Rotate Right with Extend (32 bit) - This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring. + This function moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. \param [in] value Value to rotate \return Rotated value */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) { uint32_t result; @@ -754,7 +790,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RRX(uint32_t value \param [in] ptr Pointer to data \return value of type uint8_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) { uint32_t result; @@ -777,7 +813,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDRBT(volatile uint \param [in] ptr Pointer to data \return value of type uint16_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) { uint32_t result; @@ -800,7 +836,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDRHT(volatile uin \param [in] ptr Pointer to data \return value of type uint32_t at (*ptr) */ -__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) { uint32_t result; @@ -816,7 +852,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDRT(volatile uint \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) { __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); } @@ -829,7 +865,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRBT(uint8_t value, v \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) { __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); } @@ -842,7 +878,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __STRHT(uint16_t value, \param [in] value Value to store \param [in] ptr Pointer to location */ -__attribute__( ( always_inline ) ) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) { __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmSimd.h index 046656175..fd7214ee1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmSimd.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_cmSimd.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_cmSimd.h * @brief CMSIS Cortex-M SIMD Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc000.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc000.h index 5a0635d2a..c442606cf 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc000.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc000.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_sc000.h * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -231,14 +231,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -247,6 +240,19 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -260,6 +266,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -268,16 +278,9 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ @@ -286,6 +289,25 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -293,14 +315,17 @@ typedef union { struct { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + /*@} end of group CMSIS_CORE */ @@ -349,7 +374,7 @@ typedef struct __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ uint32_t RESERVED1[154]; - __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -366,7 +391,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -394,7 +419,7 @@ typedef struct #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ @@ -437,13 +462,6 @@ typedef struct #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ -/* SCB Security Features Register Definitions */ -#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ -#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ - -#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ -#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ - /*@} end of group CMSIS_SCB */ @@ -463,7 +481,7 @@ typedef struct /* Auxiliary Control Register Definitions */ #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -495,15 +513,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -513,7 +531,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -543,7 +561,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -553,11 +571,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ @@ -567,7 +585,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -598,7 +616,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -661,9 +679,9 @@ typedef struct /* Interrupt Priorities are WORD accessible only under ARMv6M */ /* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) -#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) -#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) /** \brief Enable External Interrupt @@ -674,7 +692,7 @@ typedef struct */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -686,7 +704,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -702,7 +720,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); + return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -714,7 +732,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -726,7 +744,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -741,12 +759,14 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + if((int32_t)(IRQn) < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } else { - NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | - (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } } @@ -764,10 +784,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + if((int32_t)(IRQn) < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); + } } @@ -779,10 +801,10 @@ __STATIC_INLINE void NVIC_SystemReset(void) { __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -815,15 +837,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc300.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc300.h index d82eab978..d458d713e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc300.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/CMSIS/Include/core_sc300.h @@ -1,13 +1,13 @@ /**************************************************************************//** * @file core_sc300.h * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V4.00 - * @date 22. August 2014 + * @version V4.10 + * @date 18. March 2015 * * @note * ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED +/* Copyright (c) 2009 - 2015 ARM LIMITED All rights reserved. Redistribution and use in source and binary forms, with or without @@ -232,13 +232,7 @@ typedef union { struct { -#if (__CORTEX_M != 0x04) uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ uint32_t C:1; /*!< bit: 29 Carry condition code flag */ @@ -248,6 +242,22 @@ typedef union uint32_t w; /*!< Type used for word access */ } APSR_Type; +/* APSR Register Definitions */ +#define APSR_N_Pos 31 /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30 /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29 /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28 /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27 /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + /** \brief Union type to access the Interrupt Program Status Register (IPSR). */ @@ -261,6 +271,10 @@ typedef union uint32_t w; /*!< Type used for word access */ } IPSR_Type; +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). */ @@ -269,13 +283,7 @@ typedef union struct { uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ @@ -287,6 +295,31 @@ typedef union uint32_t w; /*!< Type used for word access */ } xPSR_Type; +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31 /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29 /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28 /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27 /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25 /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24 /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + /** \brief Union type to access the Control Registers (CONTROL). */ @@ -296,12 +329,18 @@ typedef union { uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ } b; /*!< Structure used for bit access */ uint32_t w; /*!< Type used for word access */ } CONTROL_Type; +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + /*@} end of group CMSIS_CORE */ @@ -332,7 +371,7 @@ typedef struct /* Software Triggered Interrupt Register Definitions */ #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ /*@} end of group CMSIS_NVIC */ @@ -368,6 +407,8 @@ typedef struct __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ uint32_t RESERVED0[5]; __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ } SCB_Type; /* SCB CPUID Register Definitions */ @@ -384,7 +425,7 @@ typedef struct #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ /* SCB Interrupt Control State Register Definitions */ #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ @@ -415,7 +456,7 @@ typedef struct #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ /* SCB Vector Table Offset Register Definitions */ #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ @@ -444,7 +485,7 @@ typedef struct #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ /* SCB System Control Register Definitions */ #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ @@ -473,7 +514,7 @@ typedef struct #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ /* SCB System Handler Control and State Register Definitions */ #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ @@ -516,7 +557,7 @@ typedef struct #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ /* SCB Configurable Fault Status Registers Definitions */ #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ @@ -526,7 +567,7 @@ typedef struct #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ /* SCB Hard Fault Status Registers Definitions */ #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ @@ -552,7 +593,7 @@ typedef struct #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ /*@} end of group CMSIS_SCB */ @@ -574,7 +615,7 @@ typedef struct /* Interrupt Controller Type Register Definitions */ #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ /*@} end of group CMSIS_SCnotSCB */ @@ -606,15 +647,15 @@ typedef struct #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ /* SysTick Reload Register Definitions */ #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ /* SysTick Current Register Definitions */ #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ /* SysTick Calibration Register Definitions */ #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ @@ -624,7 +665,7 @@ typedef struct #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ /*@} end of group CMSIS_SysTick */ @@ -675,7 +716,7 @@ typedef struct /* ITM Trace Privilege Register Definitions */ #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ /* ITM Trace Control Register Definitions */ #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ @@ -703,19 +744,19 @@ typedef struct #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ /* ITM Integration Write Register Definitions */ #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ /* ITM Integration Read Register Definitions */ #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ /* ITM Integration Mode Control Register Definitions */ #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ /* ITM Lock Status Register Definitions */ #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ @@ -725,7 +766,7 @@ typedef struct #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ /*@}*/ /* end of group CMSIS_ITM */ @@ -818,31 +859,31 @@ typedef struct #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ /* DWT CPI Count Register Definitions */ #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ /* DWT Exception Overhead Count Register Definitions */ #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ /* DWT Sleep Count Register Definitions */ #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ /* DWT LSU Count Register Definitions */ #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ /* DWT Folded-instruction Count Register Definitions */ #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ /* DWT Comparator Mask Register Definitions */ #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ /* DWT Comparator Function Register Definitions */ #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ @@ -870,7 +911,7 @@ typedef struct #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ /*@}*/ /* end of group CMSIS_DWT */ @@ -913,11 +954,11 @@ typedef struct /* TPI Asynchronous Clock Prescaler Register Definitions */ #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ /* TPI Selected Pin Protocol Register Definitions */ #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ /* TPI Formatter and Flush Status Register Definitions */ #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ @@ -930,7 +971,7 @@ typedef struct #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ /* TPI Formatter and Flush Control Register Definitions */ #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ @@ -941,7 +982,7 @@ typedef struct /* TPI TRIGGER Register Definitions */ #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ /* TPI Integration ETM Data Register Definitions (FIFO0) */ #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ @@ -963,11 +1004,11 @@ typedef struct #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ /* TPI ITATBCTR2 Register Definitions */ #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ /* TPI Integration ITM Data Register Definitions (FIFO1) */ #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ @@ -989,15 +1030,15 @@ typedef struct #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ /* TPI ITATBCTR0 Register Definitions */ #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ /* TPI Integration Mode Control Register Definitions */ #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ /* TPI DEVID Register Definitions */ #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ @@ -1016,15 +1057,15 @@ typedef struct #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ /* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + /*@}*/ /* end of group CMSIS_TPI */ @@ -1060,7 +1101,7 @@ typedef struct #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ /* MPU Control Register */ #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ @@ -1070,11 +1111,11 @@ typedef struct #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ /* MPU Region Number Register */ #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ /* MPU Region Base Address Register */ #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ @@ -1084,7 +1125,7 @@ typedef struct #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ /* MPU Region Attribute and Size Register */ #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ @@ -1115,7 +1156,7 @@ typedef struct #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ /*@} end of group CMSIS_MPU */ #endif @@ -1172,14 +1213,14 @@ typedef struct #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ /* Debug Core Register Selector Register */ #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ /* Debug Exception and Monitor Control Register */ #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ @@ -1219,7 +1260,7 @@ typedef struct #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ /*@} end of group CMSIS_CoreDebug */ @@ -1291,13 +1332,13 @@ typedef struct __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; } @@ -1310,7 +1351,7 @@ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); } @@ -1322,7 +1363,7 @@ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) */ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) { - NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1334,7 +1375,7 @@ __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) { - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1350,7 +1391,7 @@ __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) { - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1362,7 +1403,7 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1374,7 +1415,7 @@ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) { - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); } @@ -1389,7 +1430,7 @@ __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) { - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); } @@ -1404,10 +1445,12 @@ __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + if((int32_t)IRQn < 0) { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } } @@ -1425,10 +1468,12 @@ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) { - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + if((int32_t)IRQn < 0) { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS))); + } else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } } @@ -1446,16 +1491,16 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } @@ -1474,15 +1519,15 @@ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t P */ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) { - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); } @@ -1492,13 +1537,13 @@ __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGr */ __STATIC_INLINE void NVIC_SystemReset(void) { - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1) { __NOP(); } /* wait until reset */ } /*@} end of CMSIS_Core_NVICFunctions */ @@ -1531,15 +1576,15 @@ __STATIC_INLINE void NVIC_SystemReset(void) */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */ - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ } #endif @@ -1571,11 +1616,11 @@ extern volatile int32_t ITM_RxBuffer; /*!< External variable */ __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) { - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; + while (ITM->PORT[0].u32 == 0UL) { __NOP(); } + ITM->PORT[0].u8 = (uint8_t)ch; } return (ch); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c index d93a5e95f..5bad1f7b5 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/Full_Demo/main_full.c @@ -168,7 +168,7 @@ purpose of ensuring parameters are passed into tasks correctly. */ /* The base period used by the timer test tasks. */ #define mainTIMER_TEST_PERIOD ( 50 ) -/* The LED is used to show the demo status. */ +/* The LED is used to show the demo status. (not connected on Rev A hardware) */ #define mainTOGGLE_LED() HAL_GPIO_TogglePin( GPIOF, GPIO_PIN_10 ) /*-----------------------------------------------------------*/ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal.h index fc9f0e392..8f41bfa98 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc.h index c3058f88f..3d1a4ff7a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention @@ -200,10 +200,10 @@ typedef struct /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler * @{ */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)0x00000000) -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000) +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0) +#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1) +#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE) /** * @} */ @@ -311,7 +311,6 @@ typedef struct #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)) #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1)) -#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17) #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) /** @@ -566,10 +565,10 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); /** @defgroup ADC_Private_Macros ADC Private Macros * @{ */ -#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ - ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV4) || \ - ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV6) || \ - ((__ADC_CLOCK__) == ADC_CLOCKPRESCALER_PCLK_DIV8)) +#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \ + ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8)) #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ @@ -612,25 +611,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); ((__REGTRIG__) == ADC_SOFTWARE_START)) #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ ((__ALIGN__) == ADC_DATAALIGN_LEFT)) -#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ - ((__CHANNEL__) == ADC_CHANNEL_1) || \ - ((__CHANNEL__) == ADC_CHANNEL_2) || \ - ((__CHANNEL__) == ADC_CHANNEL_3) || \ - ((__CHANNEL__) == ADC_CHANNEL_4) || \ - ((__CHANNEL__) == ADC_CHANNEL_5) || \ - ((__CHANNEL__) == ADC_CHANNEL_6) || \ - ((__CHANNEL__) == ADC_CHANNEL_7) || \ - ((__CHANNEL__) == ADC_CHANNEL_8) || \ - ((__CHANNEL__) == ADC_CHANNEL_9) || \ - ((__CHANNEL__) == ADC_CHANNEL_10) || \ - ((__CHANNEL__) == ADC_CHANNEL_11) || \ - ((__CHANNEL__) == ADC_CHANNEL_12) || \ - ((__CHANNEL__) == ADC_CHANNEL_13) || \ - ((__CHANNEL__) == ADC_CHANNEL_14) || \ - ((__CHANNEL__) == ADC_CHANNEL_15) || \ - ((__CHANNEL__) == ADC_CHANNEL_16) || \ - ((__CHANNEL__) == ADC_CHANNEL_17) || \ - ((__CHANNEL__) == ADC_CHANNEL_18)) + #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \ ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc_ex.h index 97ff9dc36..8a849139d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_adc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -181,7 +181,15 @@ typedef struct /** * @} */ - + +/** @defgroup ADCEx_channels ADC Specific Channels + * @{ + */ +#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16) +/** + * @} + */ + /** * @} */ @@ -190,7 +198,6 @@ typedef struct /** @defgroup ADC_Exported_Macros ADC Exported Macros * @{ */ - /** * @} */ @@ -242,6 +249,9 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_ /** @defgroup ADCEx_Private_Macros ADC Private Macros * @{ */ +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) <= ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)) + #define IS_ADC_MODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_can.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_can.h index 5f34f1ace..30599668a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_can.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_can.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CAN HAL module. ****************************************************************************** * @attention @@ -179,7 +179,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ - uint32_t Data[8]; /*!< Contains the data to be transmitted. + uint8_t Data[8]; /*!< Contains the data to be transmitted. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ }CanTxMsgTypeDef; @@ -204,7 +204,7 @@ typedef struct uint32_t DLC; /*!< Specifies the length of the frame that will be received. This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ - uint32_t Data[8]; /*!< Contains the data to be received. + uint8_t Data[8]; /*!< Contains the data to be received. This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. @@ -354,7 +354,6 @@ typedef struct */ #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ - /** * @} */ @@ -740,35 +739,6 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) -#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_RQCP2) || ((FLAG) == CAN_FLAG_BOF) || \ - ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \ - ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_SLAK) || \ - ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0)) - - -#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_SLAK) || ((FLAG) == CAN_FLAG_RQCP2) || \ - ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \ - ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) || \ - ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \ - ((FLAG) == CAN_FLAG_WKU)) - -#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\ - ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\ - ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - -#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\ - ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\ - ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\ - ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\ - ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\ - ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK)) - /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cec.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cec.h index f1f0b8d05..e953fbca1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cec.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cec.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CEC HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_conf_template.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_conf_template.h index 08f0bfe75..7103e78dd 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_conf_template.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_conf_template.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_conf_template.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief HAL configuration template file. * This file should be copied to the application folder and renamed * to stm32f7xx_hal_conf.h. diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cortex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cortex.h index 4cd926ef9..d3aa239bb 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cortex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cortex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention @@ -436,7 +436,6 @@ void HAL_SYSTICK_Callback(void); #if (__MPU_PRESENT == 1) /** * @brief Disables the MPU - * @param None * @retval None */ __STATIC_INLINE void HAL_MPU_Disable(void) @@ -451,7 +450,7 @@ __STATIC_INLINE void HAL_MPU_Disable(void) /** * @brief Enables the MPU * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged accessto the default memory + * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE * @arg MPU_HARDFAULT_NMI diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc.h index 7adaca642..c7d4ac6c8 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -269,7 +269,7 @@ typedef struct * @param __VALUE__: 8-bit value to be stored in the ID register * @retval None */ -#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)) +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc_ex.h index b42c4fb9b..6e3878f3d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_crc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp.h index 041063fee..5935cee7a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention @@ -517,12 +517,12 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32F756xx */ - /** * @} */ +#endif /* STM32F756xx */ + /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp_ex.h index 1e5c91b19..fb7c26164 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_cryp_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of CRYP HAL Extension module. ****************************************************************************** * @attention @@ -202,11 +202,12 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp); * @} */ -#endif /* STM32F756xx */ /** * @} */ +#endif /* STM32F756xx */ + /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac.h index af134eba0..106abc1b0 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention @@ -43,8 +43,6 @@ extern "C" { #endif -#if defined(STM32F756xx) || defined(STM32F746xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -392,7 +390,6 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac_ex.h index 739388e35..e492a64b9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dac_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention @@ -43,8 +43,6 @@ extern "C" { #endif -#if defined(STM32F756xx) || defined(STM32F746xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -175,7 +173,6 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi.h index 1cc6c12b5..5e76b8538 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -63,15 +63,6 @@ /** @defgroup DCMI_Exported_Types DCMI Exported Types * @{ */ -/** - * @brief DCMI Error source - */ -typedef enum -{ - DCMI_ERROR_SYNC = 1, /*!< Synchronisation error */ - DCMI_OVERRUN = 2, /*!< DCMI Overrun */ -}DCMI_ErrorTypeDef; - /** * @brief HAL DCMI State structures definition */ @@ -387,7 +378,7 @@ typedef struct * @{ */ -/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions * @{ */ /* Initialization and de-initialization functions *****************************/ @@ -399,7 +390,7 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi); * @} */ -/** @addtogroup DCMI_Exported_Functions_Group2 Operations functions +/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions * @{ */ /* IO operation functions *****************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi_ex.h index 14298fe28..9ebd243e7 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dcmi_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention @@ -52,13 +52,13 @@ * @{ */ -/** @addtogroup DCMIEx DCMI Extended - * @brief DCMI HAL module driver +/** @addtogroup DCMIEx DCMIEx * @{ - */ + */ + /* Exported types ------------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Types DCMI Extende Exported Types +/** @defgroup DCMIEx_Exported_Types DCMIEx Exported Types * @{ */ /** @@ -99,7 +99,7 @@ typedef struct uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode. This parameter can be a value of @ref DCMI_MODE_JPEG */ -#if defined(STM32F746xx) || defined(STM32F756xx) + uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */ @@ -111,21 +111,18 @@ typedef struct uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd This parameter can be a value of @ref DCMIEx_Line_Select_Start */ - -#endif /* STM32F746xx || STM32F756xx */ }DCMI_InitTypeDef; /** * @} */ -#if defined(STM32F746xx) || defined(STM32F756xx) /* Exported constants --------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Constants DCMI Exported Constants +/** @defgroup DCMIEx_Exported_Constants DCMIEx Exported Constants * @{ */ -/** @defgroup DCMIEx_Byte_Select_Mode DCMI Byte Select Mode +/** @defgroup DCMIEx_Byte_Select_Mode DCMIEx Byte Select Mode * @{ */ #define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */ @@ -137,7 +134,7 @@ typedef struct * @} */ -/** @defgroup DCMIEx_Byte_Select_Start DCMI Byte Select Start +/** @defgroup DCMIEx_Byte_Select_Start DCMIEx Byte Select Start * @{ */ #define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */ @@ -147,7 +144,7 @@ typedef struct * @} */ -/** @defgroup DCMIEx_Line_Select_Mode DCMI Line Select Mode +/** @defgroup DCMIEx_Line_Select_Mode DCMIEx Line Select Mode * @{ */ #define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */ @@ -157,7 +154,7 @@ typedef struct * @} */ -/** @defgroup DCMIEx_Line_Select_Start DCMI Line Select Start +/** @defgroup DCMIEx_Line_Select_Start DCMIEx Line Select Start * @{ */ #define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */ @@ -177,7 +174,7 @@ typedef struct /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -/** @defgroup DCMIEx_Private_Macros DCMI Extended Private Macros +/** @defgroup DCMIEx_Private_Macros DCMIEx Private Macros * @{ */ #define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \ @@ -196,7 +193,7 @@ typedef struct /** * @} */ -#endif /* STM32F746xx || STM32F756xx */ + /* Private functions ---------------------------------------------------------*/ /** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_def.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_def.h index 186f2c71a..558b81e7c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_def.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_def.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_def.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma.h index 0a071cbdf..6bb64d0aa 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention @@ -585,7 +585,7 @@ typedef struct __DMA_HandleTypeDef ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) /** - * @brief Check whether the specified DMA Stream interrupt has occurred or not. + * @brief Check whether the specified DMA Stream interrupt is enabled or not. * @param __HANDLE__: DMA handle * @param __INTERRUPT__: specifies the DMA interrupt source to check. * This parameter can be one of the following values: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma2d.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma2d.h index fec7cc1a5..68526825d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma2d.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma2d.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma_ex.h index 40d647039..3c680116d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_dma_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_eth.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_eth.h index 36d422ea8..bb88e44e7 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_eth.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_eth.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of ETH HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash.h index 525026cba..869627039 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash_ex.h index dc6efb17f..47a297f31 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_flash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention @@ -211,8 +211,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP * @{ */ -#define OB_IWDG_STOP_FREEZE ((uint32_t)0x40000000) /*!< Freeze IWDG counter in STOP mode */ -#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x00000000) /*!< IWDG counter active in STOP mode */ +#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */ +#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STOP mode */ /** * @} */ @@ -220,8 +220,8 @@ typedef struct /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY * @{ */ -#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x80000000) /*!< Freeze IWDG counter in STANDBY mode */ -#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x00000000) /*!< IWDG counter active in STANDBY mode */ +#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */ +#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio.h index 66ce94155..32676ca13 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio_ex.h index 2a76e5e64..63054f714 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_gpio_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -153,9 +153,10 @@ #define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */ #define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */ #define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */ -#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ #define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */ - +#if defined(STM32F756xx) || defined(STM32F746xx) +#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */ +#endif /* STM32F756xx || STM32F746xx */ /** * @brief AF 10 selection */ @@ -174,18 +175,19 @@ */ #define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */ #define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */ -#define GPIO_AF12_SDMMC ((uint8_t)0xC) /* SDMMC Alternate Function mapping */ +#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */ /** * @brief AF 13 selection */ #define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */ +#if defined(STM32F756xx) || defined(STM32F746xx) /** * @brief AF 14 selection */ #define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */ - +#endif /* STM32F756xx || STM32F746xx */ /** * @brief AF 15 selection */ @@ -278,7 +280,8 @@ (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) /** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function * @{ - */ + */ +#if defined(STM32F756xx) || defined(STM32F746xx) #define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ @@ -306,9 +309,40 @@ ((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \ ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ - ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT) || \ ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF14_LTDC)) +#elif defined(STM32F745xx) +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \ + ((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \ + ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \ + ((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \ + ((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \ + ((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \ + ((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \ + ((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \ + ((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \ + ((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \ + ((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \ + ((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \ + ((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \ + ((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \ + ((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \ + ((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \ + ((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \ + ((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \ + ((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \ + ((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \ + ((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \ + ((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \ + ((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \ + ((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \ + ((AF) == GPIO_AF13_DCMI) || ((AF) == GPIO_AF10_OTG_FS) || \ + ((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \ + ((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \ + ((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \ + ((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT)) +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash.h index 9595a3592..c5c2c2600 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of HASH HAL module. ****************************************************************************** * @attention @@ -428,11 +428,10 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash); * @} */ -#endif /* STM32F756xx */ /** * @} */ - +#endif /* STM32F756xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash_ex.h index be0a0b3f4..8c60611e3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hash_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention @@ -182,11 +182,10 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash); * @} */ -#endif /* STM32F756xx */ /** * @} */ - +#endif /* STM32F756xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hcd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hcd.h index b002488eb..484f6e258 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hcd.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_hcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c.h index 1e6cdc050..4c84d3d48 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c_ex.h index 3ca8d18a3..96fd3add7 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2c_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2s.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2s.h index 9b8859a91..2184dfb10 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2s.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_i2s.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda.h index 3aa2f0f9d..bdd756e3d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention @@ -494,11 +494,11 @@ typedef struct #include "stm32f7xx_hal_irda_ex.h" /* Exported functions --------------------------------------------------------*/ -/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions +/** @addtogroup IRDA_Exported_Functions IrDA Exported Functions * @{ */ -/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions +/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions * @{ */ @@ -535,7 +535,7 @@ void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); * @} */ -/** @addtogroup IRDA_Exported_Functions_Group3 Control functions +/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral Control functions * @{ */ /* Peripheral State methods **************************************************/ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda_ex.h index 490be91f6..96af0abeb 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_irda_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_iwdg.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_iwdg.h index b344f386c..a2a1f6973 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_iwdg.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_iwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_lptim.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_lptim.h index 933edbdac..5339851f3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_lptim.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_lptim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_ltdc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_ltdc.h index ae8bf95cb..52c67c94e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_ltdc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_ltdc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention @@ -43,6 +43,7 @@ extern "C" { #endif +#if defined(STM32F756xx) || defined(STM32F746xx) /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -615,7 +616,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc); /** * @} */ - +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nand.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nand.h index 863202272..6318d5423 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nand.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nand.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -54,7 +54,6 @@ * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) /* Exported typedef ----------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/ /** @defgroup NAND_Exported_Types NAND Exported Types @@ -281,7 +280,6 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nor.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nor.h index b66a998b6..e3359ee43 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nor.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_nor.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of NOR HAL module. ****************************************************************************** * @attention @@ -55,7 +55,6 @@ * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) /* Exported typedef ----------------------------------------------------------*/ /** @defgroup NOR_Exported_Types NOR Exported Types * @{ @@ -192,7 +191,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @} */ -/** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions * @{ */ @@ -203,7 +202,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); * @} */ -/** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions +/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions * @{ */ @@ -282,7 +281,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ + /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd.h index 258aff085..ac6b71db5 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention @@ -130,6 +130,20 @@ typedef struct */ #define PCD_PHY_ULPI 1 #define PCD_PHY_EMBEDDED 2 +/** + * @} + */ + +/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE + #define USBD_HS_TRDT_VALUE 9 +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE + #define USBD_FS_TRDT_VALUE 5 +#endif /* USBD_HS_TRDT_VALUE */ + /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd_ex.h index 7be7e920f..3c270c511 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pcd_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr.h index 5b0c632d9..c3c2d2ccd 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -364,7 +364,7 @@ void HAL_PWR_DisableSEVOnPend(void); /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line * @{ */ -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ +#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr_ex.h index 4daef8999..4b15a2713 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_pwr_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_qspi.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_qspi.h index 59d1d5a73..d45be94ee 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_qspi.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_qspi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -69,7 +69,7 @@ typedef struct This parameter can be a number between 0 and 255 */ uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) - This parameter can be a value between 1 and 16 */ + This parameter can be a value between 1 and 32 */ uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) @@ -353,8 +353,8 @@ typedef struct /** @defgroup QSPI_SIOOMode QSPI SIOO Mode * @{ */ -#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*! 0) && ((THR) <= 16)) +#define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32)) /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc.h index a7d0c8edc..4862c8e70 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention @@ -537,11 +537,11 @@ typedef struct * using it. * @{ */ -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) -#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_WWDGEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR1 & (RCC_APB1ENR1_PWREN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) /** * @} */ @@ -649,11 +649,11 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ -#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) != RESET) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) != RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) != RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != RESET) -#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_CRCSMEN)) == RESET) -#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1SMENR & (RCC_AHB1SMENR_DMA1SMEN)) == RESET) +#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN)) == RESET) +#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == RESET) /** * @} */ @@ -666,11 +666,11 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) != RESET) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) != RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) != RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) != RESET) -#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_WWDGSMEN)) == RESET) -#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1SMENR1 & (RCC_APB1SMENR1_PWRSMEN)) == RESET) +#define __HAL_RCC_WWDG_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_WWDGLPEN)) == RESET) +#define __HAL_RCC_PWR_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_PWRLPEN)) == RESET) /** * @} */ @@ -683,8 +683,8 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. * @{ */ -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) != RESET) -#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2SMENR & (RCC_APB2SMENR_SYSCFGSMEN)) == RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) != RESET) +#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SYSCFGLPEN)) == RESET) /** * @} */ @@ -912,7 +912,7 @@ typedef struct * output frequency is between 192 and 432 MHz. * @param __PLLP__: specifies the division factor for main system clock (SYSCLK) * This parameter must be a number in the range {2, 4, 6, or 8}. - * @note You have to set the PLLP parameter correctly to not exceed 200 MHz on + * @note You have to set the PLLP parameter correctly to not exceed 216 MHz on * the System clock frequency. * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks * This parameter must be a number between Min_Data = 2 and Max_Data = 15. @@ -925,6 +925,27 @@ typedef struct (RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \ ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \ ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)))) + +/** @brief Macro to configure the PLL clock source. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLSOURCE__: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry + * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry + * + */ +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__)) + +/** @brief Macro to configure the PLL multiplication factor. + * @note This function must be used only when the main PLL is disabled. + * @param __PLLM__: specifies the division factor for PLL VCO input clock + * This parameter must be a number between Min_Data = 2 and Max_Data = 63. + * @note You have to set the PLLM parameter correctly to ensure that the VCO input + * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency + * of 2 MHz to limit PLL jitter. + * + */ +#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__)) /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc_ex.h index 71bdeedec..ea776680b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rcc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention @@ -77,8 +77,8 @@ typedef struct This parameter will be used only when PLLI2S is selected as Clock Source SAI */ uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 8. - This parameter will be used only when PLLI2S is selected as Clock Source SAI */ + This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8. + This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */ }RCC_PLLI2SInitTypeDef; /** @@ -99,7 +99,7 @@ typedef struct This parameter will be used only when PLLSAI is selected as Clock Source LTDC */ uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 8. + This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider This parameter will be used only when PLLSAI is disabled */ }RCC_PLLSAIInitTypeDef; @@ -205,7 +205,9 @@ typedef struct * @{ */ #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001) +#if defined(STM32F756xx) || defined(STM32F746xx) #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008) +#endif /* STM32F756xx || STM32F746xx */ #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010) #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040) @@ -227,6 +229,7 @@ typedef struct #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000) #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000) #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000) +#define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000) /** @@ -1164,6 +1167,7 @@ typedef struct UNUSED(tmpreg); \ } while(0) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_CLK_ENABLE() do { \ __IO uint32_t tmpreg; \ SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ @@ -1171,6 +1175,7 @@ typedef struct tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\ UNUSED(tmpreg); \ } while(0) +#endif /* STM32F756xx || STM32F746xx */ #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN)) @@ -1189,8 +1194,9 @@ typedef struct #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN)) #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN)) #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN)) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN)) - +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ @@ -1381,8 +1387,9 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET) - +#endif /* STM32F756xx || STM32F746xx */ #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET) #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) @@ -1400,8 +1407,9 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET) - +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ @@ -1550,7 +1558,9 @@ typedef struct #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST)) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST)) +#endif /* STM32F756xx || STM32F746xx */ #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST)) @@ -1567,8 +1577,9 @@ typedef struct #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST)) #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST)) #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST)) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST)) - +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ @@ -1756,7 +1767,9 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN)) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN)) +#endif /* STM32F756xx || STM32F746xx */ #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN)) #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN)) @@ -1775,8 +1788,9 @@ typedef struct #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN)) #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN)) #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN)) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN)) - +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ @@ -1808,8 +1822,8 @@ typedef struct #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET) #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET) #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET) -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET) #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET) @@ -1834,8 +1848,8 @@ typedef struct #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET) #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET) #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET) -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET) +#define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET) #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET) #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET) #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET) @@ -1968,7 +1982,9 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET) +#endif /* STM32F756xx || STM32F746xx */ #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET) #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET) @@ -1987,7 +2003,9 @@ typedef struct #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET) #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET) #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET) +#if defined(STM32F756xx) || defined(STM32F746xx) #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET) +#endif /* STM32F756xx || STM32F746xx */ /** * @} */ @@ -2029,7 +2047,7 @@ typedef struct * @param __PLLSAIR__: specifies the division factor for LTDC clock * This parameter must be a number between Min_Data = 2 and Max_Data = 7. * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks - * This parameter can be a divider by 2, 4, 6 or 8. + * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider . */ #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28)) @@ -2048,9 +2066,9 @@ typedef struct * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz * on the I2S clock frequency. * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock. - * This parameter can be a divider by 2, 4, 6 or 8. + * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8 */ -#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28)) +#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28)) /** @brief Macro to configure the SAI clock Divider coming from PLLI2S. * @note This function must be called before enabling the PLLI2S. @@ -2500,6 +2518,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters * @{ */ +#if defined(STM32F756xx) || defined(STM32F746xx) #define IS_RCC_PERIPHCLOCK(SELECTION) \ ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \ @@ -2523,7 +2542,32 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ - (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#elif defined(STM32F745xx) +#define IS_RCC_PERIPHCLOCK(SELECTION) \ + ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \ + (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \ + (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ + (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \ + (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \ + (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \ + (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \ + (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \ + (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \ + (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ + (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \ + (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \ + (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \ + (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \ + (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \ + (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \ + (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \ + (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) +#endif /* STM32F756xx || STM32F746xx */ #define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432)) #define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8)) #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15)) diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rng.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rng.h index e798979a5..c94254f96 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rng.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rng.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention @@ -43,9 +43,6 @@ extern "C" { #endif -#if defined(STM32F756xx) || defined(STM32F746xx) - - /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" @@ -352,8 +349,6 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); * @} */ -#endif /* STM32F756xx || STM32F746xx */ - #ifdef __cplusplus } #endif diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc.h index 3cf94b953..dd643838d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -697,7 +697,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define RTC_TIMEOUT_VALUE 1000 -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc_ex.h index ba78c032d..2d353e69e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_rtc_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention @@ -186,7 +186,7 @@ typedef struct /** @defgroup RTCEx_TimeStamp_Pin_Selection RTCEx TimeStamp Pin Selection * @{ */ -#define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000) +#define RTC_TIMESTAMPPIN_DEFAULT ((uint32_t)0x00000000) #define RTC_TIMESTAMPPIN_PI8 ((uint32_t)0x00000002) #define RTC_TIMESTAMPPIN_PC1 ((uint32_t)0x00000004) /** @@ -924,8 +924,8 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_Private_Constants RTCEx Private Constants * @{ */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_MR21) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR22) /*!< External interrupt line 22 Connected to the RTC Wake-up event */ /** * @} */ @@ -947,7 +947,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING)) #define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & (uint32_t)0xFFFFFFD6) == 0x00) && ((__TAMPER__) != (uint32_t)RESET)) #define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & (uint32_t)0xFFB6FFFB) == 0x00) && ((__INTERRUPT__) != (uint32_t)RESET)) -#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_PC13) || \ +#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_DEFAULT) || \ ((__PIN__) == RTC_TIMESTAMPPIN_PI8) || \ ((__PIN__) == RTC_TIMESTAMPPIN_PC1)) #define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai.h index 897616ff1..0f92d9660 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai_ex.h index f50030642..531cad317 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sai_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention @@ -61,7 +61,7 @@ * @{ */ -/** @addtogroup SAIEx_Exported_Functions_Group1 SAI Extended Functions Group1 +/** @addtogroup SAIEx_Exported_Functions_Group1 Extension features functions * @{ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sd.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sd.h index 48455c06d..2aaf83c53 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sd.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sd.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SD HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sdram.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sdram.h index 0c0bae435..71d54231f 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sdram.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sdram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard.h index 3af5fe215..1dd193a7c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard_ex.h index b7031612c..eb7f34165 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_smartcard_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spdifrx.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spdifrx.h index e0b633739..e0bc3ef97 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spdifrx.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spdifrx.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spi.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spi.h index 29bc4bba2..632c9acc5 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spi.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_spi.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -634,7 +634,7 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); * @} */ -/** @addtogroup SPI_Exported_Functions_Group2 Input and Output operation functions +/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions * @{ */ @@ -664,7 +664,7 @@ void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); * @} */ -/** @addtogroup SPI_Exported_Functions_Group3 Peripheral Control functions +/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions * @{ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sram.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sram.h index 0c369f590..a6ea4356f 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sram.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_sram.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim.h index 73e3a8764..a479e4ed9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h index 27c49052a..ee3fc968b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_tim_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention @@ -46,7 +46,7 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal_def.h" -/** @addtogroup STM32F7xx_HAL +/** @addtogroup STM32F7xx_HAL_Driver * @{ */ @@ -126,11 +126,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Exported Constants +/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ */ -/** @defgroup TIMEx_Channel TIM Channel +/** @defgroup TIMEx_Channel TIMEx Channel * @{ */ @@ -146,7 +146,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIM Extended Output Compare and PWM Modes +/** @defgroup TIMEx_Output_Compare_and_PWM_modes TIMEx Output Compare and PWM Modes * @{ */ #define TIM_OCMODE_TIMING ((uint32_t)0x0000) @@ -168,7 +168,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_Remap TIM Remap +/** @defgroup TIMEx_Remap TIMEx Remap * @{ */ #define TIM_TIM2_TIM8_TRGO (0x00000000) @@ -187,7 +187,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_ClearInput_Source TIM Extended Clear Input Source +/** @defgroup TIMEx_ClearInput_Source TIMEx Clear Input Source * @{ */ #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) @@ -197,7 +197,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_Break2_Input_enable_disable TIMEX Break input 2 Enable +/** @defgroup TIMEx_Break2_Input_enable_disable TIMEx Break input 2 Enable * @{ */ #define TIM_BREAK2_DISABLE ((uint32_t)0x00000000) @@ -215,7 +215,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 +/** @defgroup TIMEx_Group_Channel5 TIMEx Group Channel 5 and Channel 1, 2 or 3 * @{ */ #define TIM_GROUPCH5_NONE (uint32_t)0x00000000 /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ @@ -226,7 +226,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_Master_Mode_Selection_2 TIM Extended Master Mode Selection 2 (TRGO2) +/** @defgroup TIMEx_Master_Mode_Selection_2 TIMEx Master Mode Selection 2 (TRGO2) * @{ */ #define TIM_TRGO2_RESET ((uint32_t)0x00000000) @@ -249,7 +249,7 @@ typedef struct * @} */ -/** @defgroup TIMEx_Slave_Mode TIM Extended Slave mode +/** @defgroup TIMEx_Slave_Mode TIMEx Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) @@ -266,7 +266,7 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros +/** @defgroup TIMEx_Exported_Macros TIMEx Exported Macros * @{ */ @@ -441,7 +441,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Private Macros +/** @defgroup TIMEx_Private_Macros TIMEx Private Macros * @{ */ #define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ @@ -527,7 +527,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef* htim); */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIM Private Functions +/** @defgroup TIMEx_Private_Functions TIMEx Private Functions * @{ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart.h index 938fade77..71a052d0e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of UART HAL module. ****************************************************************************** * @attention @@ -936,7 +936,7 @@ typedef struct /** @brief Check UART Baud rate * @param BAUDRATE: Baudrate specified by the user - * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 200 MHz) + * The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz) * divided by the smallest oversampling used on the USART (i.e. 8) * @retval Test result (TRUE or FALSE). */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart_ex.h index 2ee1aa504..2e41fc8d9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_uart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart.h index 12fd6f8ac..7b80e14a3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of USART HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart_ex.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart_ex.h index d1efcf2cb..0f4a3939a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart_ex.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_usart_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_wwdg.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_wwdg.h index b734f078a..ffa999da6 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_wwdg.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_hal_wwdg.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_fmc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_fmc.h index f07dcaeeb..071c55e97 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_fmc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_fmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of FMC HAL module. ****************************************************************************** * @attention @@ -53,8 +53,6 @@ /** @addtogroup FMC_LL * @{ */ -#if defined(STM32F756xx) || defined(STM32F746xx) - /** @addtogroup FMC_LL_Private_Macros * @{ @@ -1323,7 +1321,6 @@ uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t B * @} */ -#endif /* STM32F756xx || STM32F746xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_sdmmc.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_sdmmc.h index 61ef151f9..c85172942 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_sdmmc.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_sdmmc.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_usb.h b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_usb.h index d72d1daff..36e51295e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_usb.h +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/include/stm32f7xx_ll_usb.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal.c index 29fa2cf84..b27728da1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -65,12 +65,12 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /** - * @brief STM32F7xx HAL Driver version number V1.0.0RC1 + * @brief STM32F7xx HAL Driver version number V1.0.0 */ #define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ #define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ #define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32F7xx_HAL_VERSION_RC (0x01) /*!< [7:0] release candidate */ +#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\ |(__STM32F7xx_HAL_VERSION_SUB1 << 16)\ |(__STM32F7xx_HAL_VERSION_SUB2 << 8 )\ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc.c index 9c4a00806..631d707aa 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -284,6 +284,8 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) if(hadc->State == HAL_ADC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hadc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_ADC_MspInit(hadc); } @@ -1250,7 +1252,7 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) /* Private functions ---------------------------------------------------------*/ -/** @defgroup ADC_Private_Functions +/** @defgroup ADC_Private_Functions ADC Private Functions * @{ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc_ex.c index 430e09bfb..38c0f4197 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_can.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_can.c index 7746630e4..cf76e5461 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_can.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_can.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_can.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief CAN HAL module driver. * * This file provides firmware functions to manage the following @@ -19,7 +19,7 @@ ============================================================================== [..] (#) Enable the CAN controller interface clock using - __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN1_CLK_ENABLE() for CAN2 + __HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2 -@- In case you are using CAN2 only, you have to enable the CAN1 clock. (#) CAN pins configuration @@ -191,7 +191,9 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) if(hcan->State == HAL_CAN_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hcan->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CAN_MspInit(hcan); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cec.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cec.c index c3af66e3d..8b33f8c42 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cec.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cec.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief CEC HAL module driver. * * This file provides firmware functions to manage the following @@ -160,6 +160,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) } /* Check the parameters */ + assert_param(IS_CEC_ALL_INSTANCE(hcec->Instance)); assert_param(IS_CEC_SIGNALFREETIME(hcec->Init.SignalFreeTime)); assert_param(IS_CEC_TOLERANCE(hcec->Init.Tolerance)); assert_param(IS_CEC_BRERXSTOP(hcec->Init.BRERxStop)); @@ -173,9 +174,11 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) if(hcec->State == HAL_CEC_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hcec->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ - HAL_CEC_MspInit(hcec); + HAL_CEC_MspInit(hcec); } hcec->State = HAL_CEC_STATE_BUSY; @@ -285,7 +288,7 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) The end of the data processing will be indicated through the dedicated CEC IRQ when using Interrupt mode. The HAL_CEC_TxCpltCallback(), HAL_CEC_RxCpltCallback() user callbacks - will be executed respectivelly at the end of the transmit or Receive process + will be executed respectively at the end of the transmit or Receive process The HAL_CEC_ErrorCallback()user callback will be executed when a communication error is detected @@ -374,7 +377,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationA } } - /* check whether error occured while waiting for TXBR to be set: + /* check whether error occurred while waiting for TXBR to be set: * has Tx underrun occurred ? * has Tx error occurred ? * has Tx Missing Acknowledge error occurred ? @@ -776,56 +779,56 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC transmit error interrupt occured --------------------------------------*/ + /* CEC transmit error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXERR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXERR) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXERR); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC TX underrun error interrupt occured --------------------------------------*/ + /* CEC TX underrun error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_TXUDR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_TXUDR) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TXUDR); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC TX arbitration error interrupt occured --------------------------------------*/ + /* CEC TX arbitration error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_ARBLST) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_ARBLST) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_ARBLST); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX overrun error interrupt occured --------------------------------------*/ + /* CEC RX overrun error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXOVR) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXOVR) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXOVR); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX bit rising error interrupt occured --------------------------------------*/ + /* CEC RX bit rising error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_BRE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_BRE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_BRE); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX short bit period error interrupt occured --------------------------------------*/ + /* CEC RX short bit period error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_SBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_SBPE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_SBPE); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX long bit period error interrupt occured --------------------------------------*/ + /* CEC RX long bit period error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_LBPE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_LBPE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_LBPE); hcec->State = HAL_CEC_STATE_ERROR; } - /* CEC RX missing acknowledge error interrupt occured --------------------------------------*/ + /* CEC RX missing acknowledge error interrupt occurred --------------------------------------*/ if((__HAL_CEC_GET_FLAG(hcec, CEC_FLAG_RXACKE) != RESET) && (__HAL_CEC_GET_IT_SOURCE(hcec, CEC_IT_RXACKE) != RESET)) { __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RXACKE); diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cortex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cortex.c index ff866e928..fb36fd22b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cortex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc.c index dad4db206..0321ea580 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -87,7 +87,7 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); /* Exported functions --------------------------------------------------------*/ -/** @defgroup CRC_Exported_Functions +/** @defgroup CRC_Exported_Functions CRC Exported Functions * @{ */ @@ -128,6 +128,8 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) if(hcrc->State == HAL_CRC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -415,12 +417,12 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ } if (BufferLength%4 == 2) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1])); + *(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1])); } if (BufferLength%4 == 3) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1])); - *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + *(__IO uint32_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1])); + *(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; } } @@ -451,7 +453,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 } if ((BufferLength%2) != 0) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; + *(__IO uint32_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; } /* Return the CRC computed value */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc_ex.c index fdd38d7ad..3dcaa6862 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp.c index fe1063f5a..331bd838d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -103,15 +103,14 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ - +#if defined(STM32F756xx) /** @defgroup CRYP CRYP * @brief CRYP HAL module driver. * @{ */ -#ifdef HAL_CRYP_MODULE_ENABLED -#if defined(STM32F756xx) +#ifdef HAL_CRYP_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -3795,13 +3794,13 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) * @} */ -#endif /* STM32F756xx */ - #endif /* HAL_CRYP_MODULE_ENABLED */ + + /** * @} */ - +#endif /* STM32F756xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp_ex.c index 9df705254..46e4fb571 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_cryp_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -102,15 +102,14 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ - +#if defined(STM32F756xx) /** @defgroup CRYPEx CRYPEx * @brief CRYP Extension HAL module driver. * @{ */ -#ifdef HAL_CRYP_MODULE_ENABLED -#if defined(STM32F756xx) +#ifdef HAL_CRYP_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -3028,14 +3027,12 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp) /** * @} */ -#endif /* STM32F756xx */ - #endif /* HAL_CRYP_MODULE_ENABLED */ /** * @} */ - +#endif /* STM32F756xx */ /** * @} */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac.c index 355033cb6..a54cfb1d3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -185,7 +185,6 @@ #ifdef HAL_DAC_MODULE_ENABLED -#if defined(STM32F756xx) || defined(STM32F746xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -239,7 +238,9 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); if(hdac->State == HAL_DAC_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hdac->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_DAC_MspInit(hdac); } @@ -934,7 +935,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ + #endif /* HAL_DAC_MODULE_ENABLED */ /** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac_ex.c index 899a14a92..639bb62b6 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dac_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -67,8 +67,6 @@ #ifdef HAL_DAC_MODULE_ENABLED -#if defined(STM32F756xx) || defined(STM32F746xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -365,8 +363,6 @@ void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) * @} */ -#endif /* STM32F756xx || STM32F746xx */ - #endif /* HAL_DAC_MODULE_ENABLED */ /** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi.c index 95c7fd065..079aa6699 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -160,6 +160,8 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) if(hdcmi->State == HAL_DCMI_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hdcmi->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_DCMI_MspInit(hdcmi); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi_ex.c index ef58cb726..5506b0849 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dcmi_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief DCMI Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of DCMI extension peripheral: @@ -57,14 +57,13 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ -/** @defgroup DCMI DCMI - * @brief DCMI HAL module driver +/** @defgroup DCMIEx DCMIEx + * @brief DCMI Extended HAL module driver * @{ */ #ifdef HAL_DCMI_MODULE_ENABLED -#if defined(STM32F746xx) || defined(STM32F756xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -72,7 +71,7 @@ /* Private function prototypes -----------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup DCMIEx_Exported_Functions DCMI Extended Exported Functions +/** @defgroup DCMIEx_Exported_Functions DCMIEx Exported Functions * @{ */ @@ -190,7 +189,6 @@ HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi) /** * @} */ -#endif /* STM32F746xx || STM32F756xx */ #endif /* HAL_DCMI_MODULE_ENABLED */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma.c index c773dac11..19efb25a1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma2d.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma2d.c index 50333f067..a3317501e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma2d.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma2d.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief DMA2D HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DMA2D peripheral: @@ -196,6 +196,8 @@ HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d) if(hdma2d->State == HAL_DMA2D_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hdma2d->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_DMA2D_MspInit(hdma2d); } @@ -891,7 +893,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) { /* Prepare the value to be wrote to the BGCOLR register */ - tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF); + tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF); /* Write to DMA2D BGCOLR register */ hdma2d->Instance->BGCOLR = tmp; @@ -937,7 +939,7 @@ HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t La if ((pLayerCfg->InputColorMode == CM_A4) || (pLayerCfg->InputColorMode == CM_A8)) { /* Prepare the value to be wrote to the FGCOLR register */ - tmp |= ((pLayerCfg->InputAlpha) & 0x00FFFFFF); + tmp = ((pLayerCfg->InputAlpha) & 0x00FFFFFF); /* Write to DMA2D FGCOLR register */ hdma2d->Instance->FGCOLR = tmp; diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma_ex.c index 109be75d8..5f03450e8 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_dma_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_eth.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_eth.c index 1bbf8f9c0..cf8c80944 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_eth.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_eth.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_eth.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -190,6 +190,8 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) if(heth->State == HAL_ETH_STATE_RESET) { + /* Allocate lock resource and initialize it */ + heth->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC. */ HAL_ETH_MspInit(heth); } @@ -243,7 +245,7 @@ HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth) } else /* ((hclk >= 150000000)&&(hclk <= 200000000)) */ { - /* CSR Clock Range between 150-200 MHz */ + /* CSR Clock Range between 150-216 MHz */ tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102; } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash.c index 3d2ae6607..03adc9891 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -308,7 +308,6 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /** * @brief This function handles FLASH interrupt request. - * @param None * @retval None */ void HAL_FLASH_IRQHandler(void) @@ -593,7 +592,6 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. - * @param None * @retval FLASH_ErrorCode: The returned value can be: * @arg FLASH_ERROR_ERS: FLASH Erasing Sequence error flag * @arg FLASH_ERROR_PGP: FLASH Programming Parallelism error flag @@ -772,7 +770,6 @@ static void FLASH_Program_Byte(uint32_t Address, uint8_t Data) /** * @brief Set the specific FLASH error flag. - * @param None * @retval None */ static void FLASH_SetErrorCode(void) diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash_ex.c index bada74b33..cb3460b77 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_flash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -326,8 +326,8 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) pOBInit->USERConfig & OB_IWDG_SW, pOBInit->USERConfig & OB_STOP_NO_RST, pOBInit->USERConfig & OB_STDBY_NO_RST, - pOBInit->USERConfig & OB_IWDG_STOP_FREEZE, - pOBInit->USERConfig & OB_IWDG_STDBY_FREEZE); + pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE, + pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE); } /* BOR Level configuration */ @@ -666,7 +666,7 @@ static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level) * This parameter can be one of the following values: * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * Address: specifies Boot base address + * @param Address: specifies Boot base address * This parameter can be one of the following values: * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_gpio.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_gpio.c index 73696d6b8..5f3f2a5de 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_gpio.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash.c index bfc98150b..d70cabba3 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief HASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the HASH peripheral: @@ -102,15 +102,14 @@ * @{ */ +#if defined(STM32F756xx) + /** @defgroup HASH HASH * @brief HASH HAL module driver. * @{ */ - #ifdef HAL_HASH_MODULE_ENABLED -#if defined(STM32F756xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -355,6 +354,8 @@ HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash) if(hhash->State == HAL_HASH_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hhash->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_HASH_MspInit(hhash); } @@ -1828,11 +1829,12 @@ HAL_HASH_STATETypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @} */ -#endif /* STM32F756xx */ #endif /* HAL_HASH_MODULE_ENABLED */ + /** * @} */ +#endif /* STM32F756xx */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash_ex.c index 51b0c95f2..29ca7172f 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hash_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief HASH HAL Extension module driver. * This file provides firmware functions to manage the following * functionalities of HASH peripheral: @@ -98,6 +98,7 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ +#if defined(STM32F756xx) /** @defgroup HASHEx HASHEx * @brief HASH Extension HAL module driver. @@ -106,8 +107,6 @@ #ifdef HAL_HASH_MODULE_ENABLED -#if defined(STM32F756xx) - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ @@ -1611,12 +1610,12 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t /** * @} */ -#endif /* STM32F756xx */ - #endif /* HAL_HASH_MODULE_ENABLED */ + /** * @} */ +#endif /* STM32F756xx */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hcd.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hcd.c index 5b6bb9d12..188f0ffab 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hcd.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_hcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_hcd.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief HCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -896,16 +896,17 @@ static void HCD_HC_IN_IRQHandler (HCD_HandleTypeDef *hhcd, uint8_t chnum) __HAL_HCD_UNMASK_HALT_HC_INT(chnum); USB_HC_Halt(hhcd->Instance, chnum); } - else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| - (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + + hhcd->hc[chnum].state = HC_NAK; + __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)|| + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) { /* re-activate the channel */ USBx_HC(chnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHDIS; USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - hhcd->hc[chnum].state = HC_NAK; - __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK); } } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c.c index e4a2a33d2..743daf684 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief I2C HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: @@ -307,6 +307,8 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) if(hi2c->State == HAL_I2C_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hi2c->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_I2C_MspInit(hi2c); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c_ex.c index bcde7b0d9..9c0d80aaf 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2c_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C Extended peripheral: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2s.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2s.c index 32747201b..2b6b77e00 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2s.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_i2s.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_i2s.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -139,11 +139,11 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f7xx_hal.h" -/** @addtogroup STM32F3xx_HAL_Driver +/** @addtogroup STM32F7xx_HAL_Driver * @{ */ -/** @defgroup I2S I2S HAL module driver +/** @defgroup I2S I2S * @brief I2S HAL module driver * @{ */ @@ -234,11 +234,16 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); - hi2s->State = HAL_I2S_STATE_BUSY; - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2S_MspInit(hi2s); + if(hi2s->State == HAL_I2S_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hi2s->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + HAL_I2S_MspInit(hi2s); + } + hi2s->State = HAL_I2S_STATE_BUSY; + /*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/ /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ hi2s->Instance->I2SCFGR &= ~(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ @@ -1300,7 +1305,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) /** * @brief Get I2S Input Clock based on I2S source clock selection - * @param hsai: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module. * @retval I2S Clock Input */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_irda.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_irda.c index aa6d89f20..68403fd16 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_irda.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA SIR ENDEC block (IrDA): @@ -164,6 +164,7 @@ static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /** * @} @@ -225,6 +226,8 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) if(hirda->State == HAL_IRDA_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hirda->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_IRDA_MspInit(hirda); } @@ -947,7 +950,12 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { IRDA_Transmit_IT(hirda); } - + + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) + { + IRDA_EndTransmit_IT(hirda); + } } /** @@ -1185,7 +1193,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State= HAL_IRDA_STATE_TIMEOUT; + hirda->State= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1210,7 +1218,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State= HAL_IRDA_STATE_TIMEOUT; + hirda->State= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1278,6 +1286,35 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) } } +/** + * @brief Wraps up transmission in non blocking mode. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_TxCpltCallback(hirda); + + return HAL_OK; +} + /** * @brief Receive an amount of data in non blocking mode. * Function called under interruption only, once @@ -1341,49 +1378,30 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) /** * @brief DMA IRDA Tx transfer completed callback - * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains - * the configuration information for the specified IRDA module. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ + /* DMA Normal mode*/ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { hirda->TxXferCount = 0; - + /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); - - /* Wait for IRDA TC Flag */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, HAL_IRDA_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout Occured */ - hirda->State = HAL_IRDA_STATE_TIMEOUT; - HAL_IRDA_ErrorCallback(hirda); - } - else - { - /* No Timeout */ - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - HAL_IRDA_TxCpltCallback(hirda); - } + in the IRDA CR3 register */ + hirda->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); } /* DMA Circular mode */ else { - HAL_IRDA_TxCpltCallback(hirda); + HAL_IRDA_TxCpltCallback(hirda); } } @@ -1408,15 +1426,16 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma) static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode */ if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { hirda->RxXferCount = 0; - + /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the IRDA CR3 register */ + in the IRDA CR3 register */ hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAR); - + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) { hirda->State = HAL_IRDA_STATE_BUSY_TX; @@ -1426,7 +1445,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma) hirda->State = HAL_IRDA_STATE_READY; } } - + HAL_IRDA_RxCpltCallback(hirda); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_iwdg.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_iwdg.c index a156715f5..403cb752c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_iwdg.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief IWDG HAL module driver. * * This file provides firmware functions to manage the following diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_lptim.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_lptim.c index 22d635d0a..6366b15f9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_lptim.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_lptim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_lptim.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief LPTIM HAL module driver. * * This file provides firmware functions to manage the following @@ -258,6 +258,8 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) if(hlptim->State == HAL_LPTIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hlptim->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_LPTIM_MspInit(hlptim); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_ltdc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_ltdc.c index 319533d5f..be8b5f238 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_ltdc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_ltdc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral: @@ -102,6 +102,8 @@ /** @addtogroup STM32F7xx_HAL_Driver * @{ */ +#if defined(STM32F756xx) || defined(STM32F746xx) + /** @defgroup LTDC LTDC * @brief LTDC HAL module driver * @{ @@ -170,6 +172,8 @@ HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc) if(hltdc->State == HAL_LTDC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hltdc->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_LTDC_MspInit(hltdc); } @@ -1176,9 +1180,11 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay */ #endif /* HAL_LTDC_MODULE_ENABLED */ + /** * @} */ +#endif /* STM32F756xx || STM32F746xx */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_msp_template.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_msp_template.c index 9251f39f5..738c9716f 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_msp_template.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_msp_template.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_msp_template.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief HAL MSP module. * This file template is located in the HAL folder and should be copied * to the user folder. @@ -13,7 +13,7 @@ ##### How to use this driver ##### =============================================================================== [..] - This file is generated automatically by MicroXplorer and eventually modified + This file is generated automatically by STM32CubeMX and eventually modified by the user @endverbatim @@ -76,7 +76,7 @@ */ void HAL_MspInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } @@ -87,7 +87,7 @@ void HAL_MspInit(void) */ void HAL_MspDeInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } @@ -98,7 +98,7 @@ void HAL_MspDeInit(void) */ void HAL_PPP_MspInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } @@ -109,7 +109,7 @@ void HAL_PPP_MspInit(void) */ void HAL_PPP_MspDeInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nand.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nand.c index 5e96d330e..b5ce3d124 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nand.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nand.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief NAND HAL module driver. * This file provides a generic firmware to drive NAND memories mounted * as external device. @@ -92,8 +92,6 @@ #ifdef HAL_NAND_MODULE_ENABLED -#if defined(STM32F756xx) || defined(STM32F746xx) - /** @defgroup NAND NAND * @brief NAND HAL module driver * @{ @@ -143,6 +141,8 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT if(hnand->State == HAL_NAND_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hnand->Lock = HAL_UNLOCKED; /* Initialize the low level hardware (MSP) */ HAL_NAND_MspInit(hnand); } @@ -1000,7 +1000,7 @@ HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand) /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ + #endif /* HAL_NAND_MODULE_ENABLED */ /** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nor.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nor.c index 8c8eda803..624d825da 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nor.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_nor.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_nor.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief NOR HAL module driver. * This file provides a generic firmware to drive NOR memories mounted * as external device. @@ -94,7 +94,6 @@ * @{ */ #ifdef HAL_NOR_MODULE_ENABLED -#if defined(STM32F756xx) || defined(STM32F746xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -836,7 +835,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR * @} */ -/** @defgroup NOR_Exported_Functions_Group3 Control functions +/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions * @brief management functions * @verbatim @@ -904,7 +903,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor) * @} */ -/** @defgroup NOR_Exported_Functions_Group4 State functions +/** @defgroup NOR_Exported_Functions_Group4 NOR State functions * @brief Peripheral State functions * @verbatim @@ -1003,7 +1002,6 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres /** * @} */ -#endif /* STM32F756xx || STM32F746xx */ #endif /* HAL_NOR_MODULE_ENABLED */ /** * @} diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd.c index 0bfcf7c6d..715f91397 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -530,14 +530,14 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH) { hpcd->Init.speed = USB_OTG_SPEED_HIGH; - hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_3); + hpcd->Init.ep0_mps = USB_OTG_HS_MAX_PACKET_SIZE ; + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_HS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); } else { hpcd->Init.speed = USB_OTG_SPEED_FULL; hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ; - hpcd->Instance->GUSBCFG |= (USB_OTG_GUSBCFG_TRDT_0 | USB_OTG_GUSBCFG_TRDT_2); + hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT); } HAL_PCD_ResetCallback(hpcd); diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd_ex.c index e1093c2a4..3c60108c8 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr.c index 60960295b..92583521c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr_ex.c index c25cbaf8f..7573e213d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -272,7 +272,7 @@ HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) __HAL_RCC_PWR_CLK_ENABLE(); - /* Enable the Over-drive to extend the clock frequency to 200 Mhz */ + /* Enable the Over-drive to extend the clock frequency to 216 MHz */ __HAL_PWR_OVERDRIVE_ENABLE(); /* Get tick */ @@ -449,7 +449,6 @@ HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t /** * @brief Returns Voltage Scaling Range. - * @param None * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1, PWR_REGULATOR_VOLTAGE_SCALE2 or * PWR_REGULATOR_VOLTAGE_SCALE3)PWR_REGULATOR_VOLTAGE_SCALE1 */ @@ -465,7 +464,7 @@ uint32_t HAL_PWREx_GetVoltageRange(void) * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, * typical output voltage at 1.4 V, - * system frequency up to 200 MHz. + * system frequency up to 216 MHz. * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, * typical output voltage at 1.2 V, * system frequency up to 180 MHz. diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_qspi.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_qspi.c index f14eae5dc..61527e51a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_qspi.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_qspi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief QSPI HAL module driver. * * This file provides firmware functions to manage the following @@ -254,14 +254,21 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); - assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); + if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) + { + assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); + } + /* Process locked */ __HAL_LOCK(hqspi); if(hqspi->State == HAL_QSPI_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hqspi->Lock = HAL_UNLOCKED; + /* Init the low level hardware : GPIO, CLOCK */ HAL_QSPI_MspInit(hqspi); @@ -1772,7 +1779,7 @@ static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqsp * @param hqspi: QSPI handle * @param cmd: structure that contains the command configuration information * @param FunctionalMode: functional mode to configured - * This parameter can be a value of @ref QSPI_FunctionalMode + * This parameter can be one of the following values: * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode * @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode * @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc.c index c475fe2a8..a39ae668e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -157,7 +157,7 @@ const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source. (#) PLL (clocked by HSI or HSE), featuring two different output clocks: - (++) The first output is used to generate the high speed system clock (up to 200 MHz) + (++) The first output is used to generate the high speed system clock (up to 216 MHz) (++) The second output is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc_ex.c index 349361705..8595daa6a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief Extension RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities RCC extension peripheral: @@ -406,11 +406,12 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /*-------------------------------------- LTDC Configuration -----------------------------------*/ +#if defined(STM32F756xx) || defined(STM32F746xx) if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) { pllsaiused = 1; } - +#endif /* STM32F756xx || STM32F746xx */ /*-------------------------------------- LPTIM1 Configuration -----------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) { @@ -433,7 +434,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /*-------------------------------------- PLLI2S Configuration ---------------------------------*/ /* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */ - if(plli2sused == 1) + if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S)) { /* Disable the PLLI2S */ __HAL_RCC_PLLI2S_DISABLE(); @@ -504,8 +505,23 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLM) */ /* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, tmpreg0, tmpreg1); - } - + } + + /*----------------- In Case of PLLI2S is just selected -----------------*/ + if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S) + { + /* Check for Parameters */ + assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN)); + assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP)); + assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR)); + assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ)); + + /* Configure the PLLI2S division factors */ + /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) × (PLLI2SN/PLLI2SM) */ + /* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */ + __HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR); + } + /* Enable the PLLI2S */ __HAL_RCC_PLLI2S_ENABLE(); @@ -583,6 +599,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1); } +#if defined(STM32F756xx) || defined(STM32F746xx) /*---------------------------- LTDC configuration -------------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC)) { @@ -601,7 +618,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */ __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR); } - +#endif /* STM32F756xx || STM32F746xx */ + /* Enable PLLSAI Clock */ __HAL_RCC_PLLSAI_ENABLE(); diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rng.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rng.c index c698ea755..69fb6d10d 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rng.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rng.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -69,9 +69,6 @@ #ifdef HAL_RNG_MODULE_ENABLED -#if defined(STM32F746xx) || defined(STM32F756xx) - - /* Private types -------------------------------------------------------------*/ /* Private defines -----------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ @@ -500,7 +497,6 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) * @} */ -#endif /* STM32F746xx || STM32F756xx */ #endif /* HAL_RNG_MODULE_ENABLED */ /** diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc.c index a54b197a1..a1f4b9e2a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -220,6 +220,8 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) if(hrtc->State == HAL_RTC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; /* Initialize RTC MSP */ HAL_RTC_MspInit(hrtc); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc_ex.c index d985e0adf..0e0b4ea75 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_rtc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) Extension peripheral: @@ -118,7 +118,7 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Functions RTC Extended Exported Functions +/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions * @{ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai.c index 6a47fe21c..7500a5060 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SAI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Serial Audio Interface (SAI) peripheral: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai_ex.c index d06ff65ac..68b107aad 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sai_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SAI Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of SAI extension peripheral: diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sd.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sd.c index 990c1711b..150b29c3a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sd.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SD card HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Secure Digital (SD) peripheral: @@ -340,6 +340,9 @@ HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *S __IO HAL_SD_ErrorTypedef errorstate = SD_OK; SD_InitTypeDef tmpinit; + /* Allocate lock resource and initialize it */ + hsd->Lock = HAL_UNLOCKED; + /* Initialize the low level hardware (MSP) */ HAL_SD_MspInit(hsd); diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sdram.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sdram.c index ed3d83e90..716de29a2 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sdram.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sdram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SDRAM HAL module driver. * This file provides a generic firmware to drive SDRAM memories mounted * as external device. @@ -145,6 +145,8 @@ HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTy if(hsdram->State == HAL_SDRAM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hsdram->Lock = HAL_UNLOCKED; /* Initialize the low level hardware (MSP) */ HAL_SDRAM_MspInit(hsdram); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard.c index d71274851..6bd738f59 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -198,7 +198,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance)); if(hsc->State == HAL_SMARTCARD_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + hsc->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_SMARTCARD_MspInit(hsc); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard_ex.c index f0ebcf6f1..bcd5b765f 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following @@ -72,7 +72,7 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Private_Functions +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARDEx Exported Functions * @{ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spdifrx.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spdifrx.c index e88e320a9..36dc53905 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spdifrx.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spdifrx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration @@ -220,6 +220,8 @@ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) if(hspdif->State == HAL_SPDIFRX_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hspdif->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ HAL_SPDIFRX_MspInit(hspdif); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spi.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spi.c index a0dc0dfb3..5b48fed9c 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spi.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_spi.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SPI HAL module driver. * * This file provides firmware functions to manage the following @@ -43,7 +43,7 @@ (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SPI_MspInit() API. + by calling the customised HAL_SPI_MspInit() API. [..] Circular mode restriction: (#) The DMA circular mode cannot be used when the SPI is configured in these modes: @@ -110,7 +110,7 @@ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/** @defgroup SPI_Private_Functions SPI Private Functions +/** @addtogroup SPI_Private_Functions * @{ */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); @@ -584,15 +584,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->RxXferCount--; } - /* Set the Rx Fido thresold */ + /* Set the Rx Fido threshold */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -669,7 +669,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Wait until TXE flag */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { - /* Erreur on the CRC reception */ + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) @@ -686,7 +686,7 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { - /* Erreur on the CRC reception */ + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_FLAG; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; @@ -866,7 +866,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->RxXferCount -= 2; if(hspi->RxXferCount <= 1) { - /* set fiforxthresold before to switch on 8 bit data size */ + /* set fiforxthreshold before to switch on 8 bit data size */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } @@ -894,7 +894,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Wait until TXE flag */ if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { - /* Erreur on the CRC reception */ + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } @@ -912,7 +912,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, Timeout) != HAL_OK) { - /* Erreur on the CRC reception */ + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; @@ -1090,14 +1090,14 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* check the data size to adapt Rx threshold and the set the function for IT treatment */ if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* set fiforxthreshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_16BIT; hspi->TxISR = NULL; } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* set fiforxthreshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); hspi->RxISR = SPI_RxISR_8BIT; hspi->TxISR = NULL; @@ -1208,12 +1208,12 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* check if packing mode is enabled and if there is more than 2 data to receive */ if((hspi->Init.DataSize > SPI_DATASIZE_8BIT) || (hspi->RxXferCount >= 2)) { - /* set fiforxthresold according the reception data length: 16 bit */ + /* set fiforxthreshold according the reception data length: 16 bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8 bit */ + /* set fiforxthreshold according the reception data length: 8 bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1393,12 +1393,12 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_LDMARX); if( hspi->Init.DataSize > SPI_DATASIZE_8BIT) { - /* set fiforxthresold according the reception data length: 16bit */ + /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } @@ -1487,7 +1487,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } else { - /* set fiforxthresold according the reception data length: 8bit */ + /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); if(hspi->hdmatx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) @@ -1506,7 +1506,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * if(hspi->hdmarx->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) { - /* set fiforxthresold according the reception data length: 16bit */ + /* set fiforxthreshold according the reception data length: 16bit */ CLEAR_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); /* Size must include the CRC length */ @@ -1548,13 +1548,23 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * is performed in DMA reception complete callback */ hspi->hdmatx->XferHalfCpltCallback = NULL; hspi->hdmatx->XferCpltCallback = NULL; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) + { + /* Set the DMA error callback */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + } + else + { + hspi->hdmatx->XferErrorCallback = NULL; + } /* Enable the Tx DMA channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); - + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { @@ -1564,10 +1574,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable Tx DMA Request */ hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - + return HAL_OK; } else @@ -1663,17 +1670,17 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) return; } - /* SPI in mode Tramitter ---------------------------------------------------*/ + /* SPI in mode Transmitter ---------------------------------------------------*/ if((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET)) { hspi->TxISR(hspi); return; } - /* SPI in Erreur Treatment ---------------------------------------------------*/ + /* SPI in ERROR Treatment ---------------------------------------------------*/ if((hspi->Instance->SR & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE)) != RESET) { - /* SPI Overrun error interrupt occured -------------------------------------*/ + /* SPI Overrun error interrupt occurred -------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) { if(hspi->State != HAL_SPI_STATE_BUSY_TX) @@ -1687,14 +1694,14 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) } } - /* SPI Mode Fault error interrupt occured -------------------------------------*/ + /* SPI Mode Fault error interrupt occurred -------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) { hspi->ErrorCode |= HAL_SPI_ERROR_MODF; __HAL_SPI_CLEAR_MODFFLAG(hspi); } - /* SPI Frame error interrupt occured ----------------------------------------*/ + /* SPI Frame error interrupt occurred ----------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) { hspi->ErrorCode |= HAL_SPI_ERROR_FRE; @@ -1807,14 +1814,6 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) * @} */ - - - - - - - - /** * @} */ @@ -1864,10 +1863,10 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) * @} */ -/** @addtogroup SPI_Private_Functions - * @brief Private functions +/** @defgroup SPI_Private_Functions SPI Private Functions * @{ */ + /** * @brief DMA SPI transmit process complete callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -1913,67 +1912,75 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) __IO uint16_t tmpreg; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* CRC handling */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until TXE flag */ - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } - if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - } - else + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + /* CRC handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + /* Wait until TXE flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) { - if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) - { - /* Erreur on the CRC reception */ - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - } - tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + /* Error on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT) + { + tmpreg = hspi->Instance->DR; UNUSED(tmpreg); /* To avoid GCC warning */ } - } - } - - /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); - /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - - /* Check the end of the transaction */ - SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); - - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - hspi->ErrorCode|= HAL_SPI_ERROR_CRC; - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - HAL_SPI_RxCpltCallback(hspi); - } - else - { - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + else + { + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + + if(hspi->Init.CRCLength == SPI_CRC_LENGTH_16BIT) + { + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SPI_FLAG_RXNE, SPI_DEFAULT_TIMEOUT) != HAL_OK) + { + /* Error on the CRC reception */ + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + } + tmpreg = *(__IO uint8_t *)&hspi->Instance->DR; + UNUSED(tmpreg); /* To avoid GCC warning */ + } + } + } + + /* Disable Rx DMA Request */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + /* Disable Tx DMA Request (done by default to handle the case master rx direction 2 lines) */ + hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); + + /* Check the end of the transaction */ + SPI_EndRxTransaction(hspi,SPI_DEFAULT_TIMEOUT); + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { + hspi->ErrorCode|= HAL_SPI_ERROR_CRC; + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); HAL_SPI_RxCpltCallback(hspi); } else { - HAL_SPI_ErrorCallback(hspi); + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_RxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); + } } } + else + { + HAL_SPI_RxCpltCallback(hspi); + } } /** @@ -2004,7 +2011,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { if(SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT) != HAL_OK) { - /* Erreur on the CRC reception */ + /* Error on the CRC reception */ hspi->ErrorCode|= HAL_SPI_ERROR_CRC; } tmpreg = hspi->Instance->DR; @@ -2118,7 +2125,7 @@ static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) hspi->RxXferCount -= 2; if(hspi->RxXferCount == 1) { - /* set fiforxthresold according the reception data length: 8bit */ + /* set fiforxthreshold according the reception data length: 8bit */ SET_BIT(hspi->Instance->CR2, SPI_RXFIFO_THRESHOLD); } } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sram.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sram.c index 2d839d7b7..10991ce54 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sram.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_sram.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SRAM HAL module driver. * This file provides a generic firmware to drive SRAM memories * mounted as external device. @@ -146,6 +146,8 @@ HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTyp if(hsram->State == HAL_SRAM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hsram->Lock = HAL_UNLOCKED; /* Initialize the low level hardware (MSP) */ HAL_SRAM_MspInit(hsram); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim.c index d7b18cef1..10ac18abb 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -489,7 +489,9 @@ HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OC_MspInit(htim); } @@ -997,6 +999,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); } @@ -1506,7 +1510,9 @@ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_IC_MspInit(htim); } @@ -1983,7 +1989,9 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePul assert_param(IS_TIM_OPM_MODE(OnePulseMode)); if(htim->State == HAL_TIM_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_OnePulse_MspInit(htim); } @@ -2265,6 +2273,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini if(htim->State == HAL_TIM_STATE_RESET) { + /* Allocate lock resource and initialize it */ + htim->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim_ex.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim_ex.c index a0e997fc7..1baf195f1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim_ex.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -106,7 +106,7 @@ * @{ */ -/** @defgroup TIMEx TIM Extended HAL module driver +/** @defgroup TIMEx TIMEx * @brief TIM Extended HAL module driver * @{ */ @@ -131,7 +131,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions +/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions * @{ */ @@ -2167,7 +2167,7 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. * @param htim: pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param TIM_Remap: specifies the TIM input remapping source. + * @param Remap: specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_uart.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_uart.c index 081017259..c563c529a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_uart.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief UART HAL module driver. * * This file provides firmware functions to manage the following @@ -181,14 +181,15 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); /* Private functions ---------------------------------------------------------*/ -/** @defgroup UART_Private_Functions +/** @defgroup UART_Exported_Functions UART Exported Functions * @{ */ -/** @defgroup HAL_UART_Group1 Initialization/de-initialization functions +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -297,6 +298,8 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) if(huart->State == HAL_UART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } @@ -358,7 +361,9 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe assert_param(IS_LIN_WORD_LENGTH(huart->Init.WordLength)); if(huart->State == HAL_UART_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } @@ -428,7 +433,9 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); if(huart->State == HAL_UART_STATE_RESET) - { + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); } @@ -539,7 +546,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @} */ -/** @defgroup HAL_UART_Group2 IO operation functions +/** @defgroup UART_Exported_Functions_Group2 IO operation functions * @brief UART Transmit/Receive functions * @verbatim @@ -1172,6 +1179,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) UART_Transmit_IT(huart); } + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + { + UART_EndTransmit_IT(huart); + } + } @@ -1203,7 +1216,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State= HAL_UART_STATE_TIMEOUT; + huart->State= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1228,7 +1241,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State= HAL_UART_STATE_TIMEOUT; + huart->State= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1251,31 +1264,22 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); - /* Wait for UART TC Flag */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, HAL_UART_TXDMA_TIMEOUTVALUE) != HAL_OK) + /* DMA Normal mode*/ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) { - /* Timeout Occured */ - huart->State = HAL_UART_STATE_TIMEOUT; - HAL_UART_ErrorCallback(huart); + huart->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); } + /* DMA Circular mode */ else { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } HAL_UART_TxCpltCallback(huart); } } @@ -1300,20 +1304,25 @@ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - huart->RxXferCount = 0; - - /* Disable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - /* Check if a transmit Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_TX; - } - else - { - huart->State = HAL_UART_STATE_READY; + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + huart->RxXferCount = 0; + + /* Disable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + + /* Check if a transmit Process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_TX; + } + else + { + huart->State = HAL_UART_STATE_READY; + } } HAL_UART_RxCpltCallback(huart); } @@ -1471,6 +1480,35 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) } } +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; +} + /** * @brief Receive an amount of data in interrupt mode * Function called under interruption only, once @@ -1534,7 +1572,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) * @} */ -/** @defgroup HAL_UART_Group3 Peripheral Control functions +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions * @brief UART control functions * @verbatim @@ -1836,7 +1874,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until TEACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { - /* Timeout Occured */ + /* Timeout Occurred */ return HAL_TIMEOUT; } } @@ -1846,7 +1884,7 @@ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) /* Wait until REACK flag is set */ if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK) { - /* Timeout Occured */ + /* Timeout Occurred */ return HAL_TIMEOUT; } } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_usart.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_usart.c index a9bc475a8..3bf220aa6 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_usart.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_usart.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief USART HAL module driver. * * This file provides firmware functions to manage the following @@ -126,6 +126,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); /** @@ -197,6 +198,8 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) if(husart->State == HAL_USART_STATE_RESET) { + /* Allocate lock resource and initialize it */ + husart->Lock = HAL_UNLOCKED; /* Init the low level hardware : GPIO, CLOCK */ HAL_USART_MspInit(husart); } @@ -1133,6 +1136,12 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) } } + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET)) + { + USART_EndTransmit_IT(husart); + } + } /** @@ -1276,16 +1285,8 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) /* Disable the USART Transmit Complete Interrupt */ __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxCpltCallback(husart); + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); return HAL_OK; } @@ -1313,6 +1314,27 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) } } +/** + * @brief Wraps up transmission in non-blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxCpltCallback(husart); + + return HAL_OK; +} + /** * @brief Simplex Receive an amount of data in non-blocking mode. * Function called under interruption only, once @@ -1476,7 +1498,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar __HAL_USART_DISABLE_IT(husart, USART_IT_PE); __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - husart->State= HAL_USART_STATE_TIMEOUT; + husart->State= HAL_USART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1501,7 +1523,7 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar __HAL_USART_DISABLE_IT(husart, USART_IT_PE); __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - husart->State= HAL_USART_STATE_TIMEOUT; + husart->State= HAL_USART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(husart); @@ -1524,32 +1546,29 @@ static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->TxXferCount = 0; - - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Wait for USART TC Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout occurred */ - husart->State = HAL_USART_STATE_TIMEOUT; - HAL_USART_ErrorCallback(husart); - } - else + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + husart->TxXferCount = 0; + + if(husart->State == HAL_USART_STATE_BUSY_TX) { - /* No Timeout */ - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ husart->Instance->CR3 &= ~(USART_CR3_DMAT); - husart->State= HAL_USART_STATE_READY; + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } } - /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ + /* DMA Circular mode */ else { - husart->State= HAL_USART_STATE_BUSY_RX; + if(husart->State == HAL_USART_STATE_BUSY_TX) + { HAL_USART_TxCpltCallback(husart); - } + } + } } @@ -1574,18 +1593,42 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - husart->RxXferCount = 0; - - /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit - in USART CR3 register */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); - /* similarly, disable the DMA TX transfer that was started to provide the - clock to the slave device */ - husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + /* DMA Normal mode */ + if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0) + { + husart->RxXferCount = 0; - husart->State= HAL_USART_STATE_READY; + /* Disable the DMA RX transfer for the receiver request by resetting the DMAR bit + in USART CR3 register */ + husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR); + /* similarly, disable the DMA TX transfer that was started to provide the + clock to the slave device */ + husart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); - HAL_USART_RxCpltCallback(husart); + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + HAL_USART_RxCpltCallback(husart); + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { + HAL_USART_TxRxCpltCallback(husart); + } + husart->State= HAL_USART_STATE_READY; + } + /* DMA circular mode */ + else + { + if(husart->State == HAL_USART_STATE_BUSY_RX) + { + HAL_USART_RxCpltCallback(husart); + } + /* The USART state is HAL_USART_STATE_BUSY_TX_RX */ + else + { + HAL_USART_TxRxCpltCallback(husart); + } + } } /** @@ -1627,6 +1670,8 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) uint32_t tmpreg = 0x0; USART_ClockSourceTypeDef clocksource = USART_CLOCKSOURCE_UNDEFINED; HAL_StatusTypeDef ret = HAL_OK; + uint16_t brrtemp = 0x0000; + uint16_t usartdiv = 0x0000; /* Check the parameters */ assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity)); @@ -1669,27 +1714,31 @@ static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart) USART_GETCLOCKSOURCE(husart, clocksource); switch (clocksource) { - case USART_CLOCKSOURCE_PCLK1: - husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_PCLK2: - husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetPCLK2Freq() / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_HSI: - husart->Instance->BRR = (uint16_t)(2*HSI_VALUE / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_SYSCLK: - husart->Instance->BRR = (uint16_t)(2*HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_LSE: - husart->Instance->BRR = (uint16_t)(2*LSE_VALUE / husart->Init.BaudRate); - break; - case USART_CLOCKSOURCE_UNDEFINED: - default: - ret = HAL_ERROR; - break; + case USART_CLOCKSOURCE_PCLK1: + usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK1Freq()) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_PCLK2: + usartdiv = (uint16_t)((2*HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_HSI: + usartdiv = (uint16_t)((2*HSI_VALUE) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_SYSCLK: + usartdiv = (uint16_t)((2*HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_LSE: + usartdiv = (uint16_t)((2*LSE_VALUE) / husart->Init.BaudRate); + break; + case USART_CLOCKSOURCE_UNDEFINED: + default: + ret = HAL_ERROR; + break; } + brrtemp = usartdiv & 0xFFF0; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000F) >> 1U); + husart->Instance->BRR = brrtemp; + return ret; } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_wwdg.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_wwdg.c index 7fff72493..fb5739f48 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_wwdg.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -163,6 +163,8 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) if(hwwdg->State == HAL_WWDG_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hwwdg->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_WWDG_MspInit(hwwdg); } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_fmc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_fmc.c index 62c60bc37..2412383a9 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_fmc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_fmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_fmc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief FMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_sdmmc.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_sdmmc.c index f97c30076..9b91a222a 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_sdmmc.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_sdmmc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief SDMMC Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_usb.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_usb.c index 9a136bb47..f9b583ea6 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_usb.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/ST_Library/stm32f7xx_ll_usb.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 12-May-2015 * @brief USB Low Layer HAL module driver. * * This file provides firmware functions to manage the following diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/startup_stm32f756xx.s b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/startup_stm32f756xx.s index 20f27e43f..f4b0d7407 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/startup_stm32f756xx.s +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/startup_stm32f756xx.s @@ -1,8 +1,8 @@ ;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f756xx.s ;* Author : MCD Application Team -;* Version : V1.0.0RC1 -;* Date : 24-March-2015 +;* Version : V1.0.0 +;* Date : 22-May-2015 ;* Description : STM32F756xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f756xx_flash.icf b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f756xx_flash.icf index c55a69518..59fadcb49 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f756xx_flash.icf +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f756xx_flash.icf @@ -4,10 +4,12 @@ /*-Specials-*/ define symbol __ICFEDIT_intvec_start__ = 0x08000000; /*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; -define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2004FFFF; +define symbol __ICFEDIT_region_ITCMRAM_start__ = 0x00000000; +define symbol __ICFEDIT_region_ITCMRAM_end__ = 0x00003FFF; /*-Sizes-*/ define symbol __ICFEDIT_size_cstack__ = 0x400; define symbol __ICFEDIT_size_heap__ = 0x200; @@ -17,15 +19,17 @@ define symbol __ICFEDIT_size_heap__ = 0x200; define memory mem with size = 4G; define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region ITCMRAM_region = mem:[from __ICFEDIT_region_ITCMRAM_start__ to __ICFEDIT_region_ITCMRAM_end__]; define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; -initialize by copy { readwrite }; +initialize by copy { readwrite, section .itcmram }; do not initialize { section .noinit }; place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; place in ROM_region { readonly }; place in RAM_region { readwrite, - block CSTACK, block HEAP }; \ No newline at end of file + block CSTACK, block HEAP }; +place in ITCMRAM_region { section .itcmram }; \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_hal_msp.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_hal_msp.c index 0bfa44e01..7b95b8363 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_hal_msp.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/stm32f7xx_hal_msp.c @@ -1,9 +1,9 @@ /** ****************************************************************************** - * @file stm32f7xx_hal_msp_template.c + * @file stm32f7xx_hal_msp.c * @author MCD Application Team - * @version V0.0.1 - * @date 21-October-2014 + * @version V1.0.0 + * @date 22-May-2015 * @brief HAL MSP module. * This file template is located in the HAL folder and should be copied * to the user folder. @@ -13,14 +13,14 @@ ##### How to use this driver ##### =============================================================================== [..] - This file is generated automatically by MicroXplorer and eventually modified + This file is generated automatically by STM32CubeMX and eventually modified by the user @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -77,7 +77,7 @@ */ void HAL_MspInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } @@ -89,31 +89,7 @@ void HAL_MspInit(void) */ void HAL_MspDeInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually - modified by the user - */ -} - -/** - * @brief Initializes the PPP MSP. - * @param None - * @retval None - */ -void HAL_PPP_MspInit(void) -{ - /* NOTE : This function is generated automatically by MicroXplorer and eventually - modified by the user - */ -} - -/** - * @brief DeInitializes the PPP MSP. - * @param None - * @retval None - */ -void HAL_PPP_MspDeInit(void) -{ - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/system_stm32f7xx.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/system_stm32f7xx.c index 8e7934173..296d0412b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/system_stm32f7xx.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_IAR/system_stm32f7xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32f7xx.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 28-April-2015 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/startup_stm32f756xx.s b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/startup_stm32f756xx.s index 72746b293..6436d5f74 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/startup_stm32f756xx.s +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/startup_stm32f756xx.s @@ -1,8 +1,8 @@ ;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32f756xx.s ;* Author : MCD Application Team -;* Version : V1.0.0RC1 -;* Date : 24-March-2015 +;* Version : V1.0.0 +;* Date : 22-May-2015 ;* Description : STM32F756xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -15,7 +15,7 @@ ;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* ; -;* Redistribution and use in source and binary forms, with or without modification, +;* Redistribution and use in so urce and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, ;* this list of conditions and the following disclaimer. @@ -45,7 +45,7 @@ ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Stack_Size EQU 0x00000400 +Stack_Size EQU 0x400; AREA STACK, NOINIT, READWRITE, ALIGN=3 Stack_Mem SPACE Stack_Size @@ -56,7 +56,7 @@ __initial_sp ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> ; -Heap_Size EQU 0x00000200 +Heap_Size EQU 0x200; AREA HEAP, NOINIT, READWRITE, ALIGN=3 __heap_base diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_hal_msp.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_hal_msp.c index 0bfa44e01..7b95b8363 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_hal_msp.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/stm32f7xx_hal_msp.c @@ -1,9 +1,9 @@ /** ****************************************************************************** - * @file stm32f7xx_hal_msp_template.c + * @file stm32f7xx_hal_msp.c * @author MCD Application Team - * @version V0.0.1 - * @date 21-October-2014 + * @version V1.0.0 + * @date 22-May-2015 * @brief HAL MSP module. * This file template is located in the HAL folder and should be copied * to the user folder. @@ -13,14 +13,14 @@ ##### How to use this driver ##### =============================================================================== [..] - This file is generated automatically by MicroXplorer and eventually modified + This file is generated automatically by STM32CubeMX and eventually modified by the user @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -77,7 +77,7 @@ */ void HAL_MspInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } @@ -89,31 +89,7 @@ void HAL_MspInit(void) */ void HAL_MspDeInit(void) { - /* NOTE : This function is generated automatically by MicroXplorer and eventually - modified by the user - */ -} - -/** - * @brief Initializes the PPP MSP. - * @param None - * @retval None - */ -void HAL_PPP_MspInit(void) -{ - /* NOTE : This function is generated automatically by MicroXplorer and eventually - modified by the user - */ -} - -/** - * @brief DeInitializes the PPP MSP. - * @param None - * @retval None - */ -void HAL_PPP_MspDeInit(void) -{ - /* NOTE : This function is generated automatically by MicroXplorer and eventually + /* NOTE : This function is generated automatically by STM32CubeMX and eventually modified by the user */ } diff --git a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/system_stm32f7xx.c b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/system_stm32f7xx.c index 8e7934173..de55a444b 100644 --- a/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/system_stm32f7xx.c +++ b/FreeRTOS/Demo/CORTEX_M7_STM32F7_STM32756G-EVAL_IAR_Keil/System_Keil/system_stm32f7xx.c @@ -1,9 +1,9 @@ /** ****************************************************************************** - * @file system_stm32f7xx.c + * @file Templates/system_stm32f7xx.c * @author MCD Application Team - * @version V1.0.0RC1 - * @date 24-March-2015 + * @version V1.0.0 + * @date 22-May-2015 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from