From: Phil Edworthy Date: Tue, 29 Nov 2016 12:58:26 +0000 (+0000) Subject: spi: cadence_qspi: Fix clearing of pol/pha bits X-Git-Tag: v2017.01-rc2~7^2~11 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=cc80a897e4fafbd9e9b6920eb866f0600a5cd5ee;p=u-boot spi: cadence_qspi: Fix clearing of pol/pha bits Or'ing together bit positions is clearly wrong. Signed-off-by: Phil Edworthy Acked-by: Marek Vasut Reviewed-by: Jagan Teki --- diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index e285d3c1e7..2403e717dc 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -311,8 +311,8 @@ void cadence_qspi_apb_set_clk_mode(void *reg_base, cadence_qspi_apb_controller_disable(reg_base); reg = readl(reg_base + CQSPI_REG_CONFIG); - reg &= ~(1 << - (CQSPI_REG_CONFIG_CLK_POL_LSB | CQSPI_REG_CONFIG_CLK_PHA_LSB)); + reg &= ~(1 << CQSPI_REG_CONFIG_CLK_POL_LSB); + reg &= ~(1 << CQSPI_REG_CONFIG_CLK_PHA_LSB); reg |= ((clk_pol & 0x1) << CQSPI_REG_CONFIG_CLK_POL_LSB); reg |= ((clk_pha & 0x1) << CQSPI_REG_CONFIG_CLK_PHA_LSB);