From: Simon Glass <sjg@chromium.org>
Date: Sat, 22 Aug 2015 21:58:53 +0000 (-0600)
Subject: x86: minnowmax: Add access to GPIOs E0, E1, E2
X-Git-Tag: v2015.10-rc3~92^2~15
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=cce7e0fa2b43b24b6a7553b348d3e716159f6c50;p=u-boot

x86: minnowmax: Add access to GPIOs E0, E1, E2

These GPIOs are accessible on the pin header. Add pinctrl settings for them
so that we they can be adjusted using the 'gpio' command.

Signed-off-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index f4e0a353f2..a8ecf0d5f4 100644
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -30,6 +30,33 @@
 		compatible = "intel,x86-pinctrl";
 		io-base = <0x4c>;
 
+		/* GPIO E0 */
+		soc_gpio_s5_0@0 {
+			gpio-offset = <0x80 0>;
+			pad-offset = <0x1d0>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
+		/* GPIO E1 */
+		soc_gpio_s5_1@0 {
+			gpio-offset = <0x80 1>;
+			pad-offset = <0x210>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
+		/* GPIO E2 */
+		soc_gpio_s5_2@0 {
+			gpio-offset = <0x80 2>;
+			pad-offset = <0x1e0>;
+			mode-gpio;
+			output-value = <0>;
+			direction = <PIN_OUTPUT>;
+		};
+
 		pin_usb_host_en0@0 {
 			gpio-offset = <0x80 8>;
 			pad-offset = <0x260>;