From: Wills Wang <wills.wang@live.com>
Date: Mon, 30 May 2016 14:54:53 +0000 (+0800)
Subject: mips: ath79: Add support for ungating USB and ethernet on qca953x
X-Git-Tag: v2016.07-rc1~64^2~2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=cdeb68e292358f9dedeaea167f6eba894c58823e;p=u-boot

mips: ath79: Add support for ungating USB and ethernet on qca953x

Add code to ungate USB and ethernet controller on qca953x

Signed-off-by: Wills Wang <wills.wang@live.com>
---

diff --git a/arch/mips/mach-ath79/reset.c b/arch/mips/mach-ath79/reset.c
index 33bf979ce0..a5ee14156c 100644
--- a/arch/mips/mach-ath79/reset.c
+++ b/arch/mips/mach-ath79/reset.c
@@ -136,6 +136,23 @@ static int eth_init_ar934x(void)
 	return 0;
 }
 
+static int eth_init_qca953x(void)
+{
+	void __iomem *rregs = map_physmem(AR71XX_RESET_BASE, AR71XX_RESET_SIZE,
+					  MAP_NOCACHE);
+	const u32 mask = QCA953X_RESET_GE0_MAC | QCA953X_RESET_GE0_MDIO |
+			 QCA953X_RESET_GE1_MAC | QCA953X_RESET_GE1_MDIO |
+			 QCA953X_RESET_ETH_SWITCH_ANALOG |
+			 QCA953X_RESET_ETH_SWITCH;
+
+	setbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+	clrbits_be32(rregs + AR934X_RESET_REG_RESET_MODULE, mask);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_eth_reset(void)
 {
 	/*
@@ -146,6 +163,8 @@ int ath79_eth_reset(void)
 		return eth_init_ar933x();
 	if (soc_is_ar934x())
 		return eth_init_ar934x();
+	if (soc_is_qca953x())
+		return eth_init_qca953x();
 
 	return -EINVAL;
 }
@@ -185,6 +204,35 @@ static int usb_reset_ar934x(void __iomem *reset_regs)
 	return 0;
 }
 
+static int usb_reset_qca953x(void __iomem *reset_regs)
+{
+	void __iomem *pregs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
+					  MAP_NOCACHE);
+
+	clrsetbits_be32(pregs + QCA953X_PLL_SWITCH_CLOCK_CONTROL_REG,
+			0xf00, 0x200);
+	mdelay(10);
+
+	/* Ungate the USB block */
+	setbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USBSUS_OVERRIDE);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_ANALOG);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_HOST);
+	mdelay(1);
+	clrbits_be32(reset_regs + QCA953X_RESET_REG_RESET_MODULE,
+		     QCA953X_RESET_USB_PHY_PLL_PWD_EXT);
+	mdelay(1);
+
+	return 0;
+}
+
 int ath79_usb_reset(void)
 {
 	void __iomem *usbc_regs = map_physmem(AR71XX_USB_CTRL_BASE,
@@ -204,6 +252,8 @@ int ath79_usb_reset(void)
 		return usb_reset_ar933x(reset_regs);
 	if (soc_is_ar934x())
 		return usb_reset_ar934x(reset_regs);
+	if (soc_is_qca953x())
+		return usb_reset_qca953x(reset_regs);
 
 	return -EINVAL;
 }