From: Marek Vasut <marex@denx.de>
Date: Tue, 21 Jul 2015 03:32:49 +0000 (+0200)
Subject: ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4
X-Git-Tag: v2015.10-rc2~229
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d043ee5b4964481b529e8ee118598e5aedc902da;p=u-boot

ddr: altera: Clean up rw_mgr_mem_calibrate_writes_center() part 4

Fix return values to match the common return value convention.

Signed-off-by: Marek Vasut <marex@denx.de>
---

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 986f0889f2..9cf2a1ad68 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3024,7 +3024,7 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 	if (ret) {
 		set_failing_group_stage(test_bgn + ret - 1, CAL_STAGE_WRITES,
 					CAL_SUBSTAGE_WRITES_CENTER);
-		return 0;
+		return -EINVAL;
 	}
 
 	min_index = get_window_mid_index(1, left_edge, right_edge, &mid_min);
@@ -3121,7 +3121,10 @@ rw_mgr_mem_calibrate_writes_center(const u32 rank_bgn, const u32 write_group,
 	 */
 	writel(0, &sdr_scc_mgr->update);
 
-	return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
+	if ((dq_margin < 0) || (dqs_margin < 0) || (dm_margin < 0))
+		return -EINVAL;
+
+	return 0;
 }
 
 /**
@@ -3148,13 +3151,11 @@ static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
 	reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
 
 	ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
-	if (!ret) {
+	if (ret)
 		set_failing_group_stage(group, CAL_STAGE_WRITES,
 					CAL_SUBSTAGE_WRITES_CENTER);
-		return -EIO;
-	}
 
-	return 0;
+	return ret;
 }
 
 /**