From: Ben Warren <bwarren@qstreams.com>
Date: Tue, 14 Aug 2007 01:26:03 +0000 (-0400)
Subject: Sync'd u-boot-net with mainline
X-Git-Tag: v1.3.0-rc1~19^2~27
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995;p=u-boot

Sync'd u-boot-net with mainline

Merge git://www.denx.de/git/u-boot

Conflicts:

	drivers/bcm570x.c
	drivers/tigon3.c
---

d1bc6c8d5f4a9c7ca9fb2292d5c65f846dcc3995
diff --cc drivers/bcm570x.c
index 7aeb5474b1,703cda4865..c8f4064224
--- a/drivers/bcm570x.c
+++ b/drivers/bcm570x.c
@@@ -1586,18 -1669,23 +1586,18 @@@ PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQu
  /*                                                                            */
  /* Return:                                                                    */
  /******************************************************************************/
 -PQQ_ENTRY
 -QQ_GetTail(
 -    PQQ_CONTAINER pQueue,
 -    unsigned int Idx)
 +PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx)
  {
 -    if(Idx >= atomic_read(&pQueue->EntryCnt))
 -    {
 -	return (PQQ_ENTRY) 0;
 -    }
 -
 -    Idx += pQueue->Tail;
 -    if(Idx >= pQueue->Size)
 -    {
 -	Idx = Idx - pQueue->Size;
 -    }
 -
 -    return pQueue->Array[Idx];
 +	if (Idx >= atomic_read (&pQueue->EntryCnt)) {
 +		return (PQQ_ENTRY) 0;
 +	}
 +
 +	Idx += pQueue->Tail;
 +	if (Idx >= pQueue->Size) {
 +		Idx = Idx - pQueue->Size;
 +	}
 +
 +	return pQueue->Array[Idx];
  }
  
- #endif				/* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */
+ #endif
diff --cc drivers/tigon3.c
index 91e22ebd21,860a8894fc..5f6a4ecd0a
--- a/drivers/tigon3.c
+++ b/drivers/tigon3.c
@@@ -5634,65 -6134,67 +5634,66 @@@ int t3_do_dma (PLM_DEVICE_BLOCK pDevice
  }
  
  STATIC LM_STATUS
 -LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
 -	   LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
 +LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
 +	    LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
  {
 -    int j;
 -    LM_UINT32 *ptr;
 -    int dma_success = 0;
 +	int j;
 +	LM_UINT32 *ptr;
 +	int dma_success = 0;
 +
 +	if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
 +	    T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
 +		return LM_STATUS_SUCCESS;
 +	}
 +	while (!dma_success) {
 +		/* Fill data with incremental patterns */
 +		ptr = (LM_UINT32 *) pBufferVirt;
 +		for (j = 0; j < BufferSize / 4; j++)
 +			*ptr++ = j;
 +
 +		if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) ==
 +		    LM_STATUS_FAILURE) {
 +			return LM_STATUS_FAILURE;
 +		}
  
 -    if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
 -	T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
 -    {
 -	return LM_STATUS_SUCCESS;
 -    }
 -    while (!dma_success)
 -    {
 -	/* Fill data with incremental patterns */
 -	ptr = (LM_UINT32 *)pBufferVirt;
 -	for (j = 0; j < BufferSize/4; j++)
 -	    *ptr++ = j;
 -
 -	if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
 -	{
 -	    return LM_STATUS_FAILURE;
 -	}
 +		MM_Wait (40);
 +		ptr = (LM_UINT32 *) pBufferVirt;
 +		/* Fill data with zero */
 +		for (j = 0; j < BufferSize / 4; j++)
 +			*ptr++ = 0;
  
 -	MM_Wait(40);
 -	ptr = (LM_UINT32 *)pBufferVirt;
 -	/* Fill data with zero */
 -	for (j = 0; j < BufferSize/4; j++)
 -	    *ptr++ = 0;
 +		if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) ==
 +		    LM_STATUS_FAILURE) {
 +			return LM_STATUS_FAILURE;
 +		}
  
 -	if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
 -	{
 -	    return LM_STATUS_FAILURE;
 +		MM_Wait (40);
 +		/* Check for data */
 +		ptr = (LM_UINT32 *) pBufferVirt;
 +		for (j = 0; j < BufferSize / 4; j++) {
 +			if (*ptr++ != j) {
 +				if ((pDevice->
 +				     DmaReadWriteCtrl &
 +				     DMA_CTRL_WRITE_BOUNDARY_MASK)
 +				    == DMA_CTRL_WRITE_BOUNDARY_DISABLE) {
 +					pDevice->DmaReadWriteCtrl =
 +					    (pDevice->
 +					     DmaReadWriteCtrl &
 +					     ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
 +					    DMA_CTRL_WRITE_BOUNDARY_16;
 +					REG_WR (pDevice,
 +						PciCfg.DmaReadWriteCtrl,
 +						pDevice->DmaReadWriteCtrl);
 +					break;
 +				} else {
 +					return LM_STATUS_FAILURE;
 +				}
 +			}
 +		}
 +		if (j == (BufferSize / 4))
 +			dma_success = 1;
  	}
 -
 -	MM_Wait(40);
 -	/* Check for data */
 -	ptr = (LM_UINT32 *)pBufferVirt;
 -	for (j = 0; j < BufferSize/4; j++)
 -	{
 -	    if (*ptr++ != j)
 -	    {
 -		if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
 -		    == DMA_CTRL_WRITE_BOUNDARY_DISABLE)
 -		{
 -		    pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
 -			 ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
 -			  DMA_CTRL_WRITE_BOUNDARY_16;
 -		    REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
 -			   pDevice->DmaReadWriteCtrl);
 -		    break;
 -		 }
 -		 else
 -		 {
 -		     return LM_STATUS_FAILURE;
 -		 }
 -	    }
 -	}
 -	if (j == (BufferSize/4))
 -	    dma_success = 1;
 -    }
 -    return LM_STATUS_SUCCESS;
 +	return LM_STATUS_SUCCESS;
  }
- #endif				/* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */
++
+ #endif