From: York Sun Date: Mon, 8 Oct 2012 07:44:20 +0000 (+0000) Subject: powerpc/mpc85xx: Add B4860 and variant SoCs X-Git-Tag: v2013.01-rc1~90^2~19 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d2404141f9cb45a01da3297bb873510799351a60;p=u-boot powerpc/mpc85xx: Add B4860 and variant SoCs Add support for Freescale B4860 and variant SoCs. Features of B4860 are (incomplete list): Six fully-programmable StarCore SC3900 FVP subsystems, divided into three clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for wireless base station applications Four dual-thread e6500 Power Architecture processors organized in one cluster-each core runs up to 1.8 GHz Two DDR3/3L controllers for high-speed, industry-standard memory interface each runs at up to 1866.67 MHz MAPLE-B3 hardware acceleration-for forward error correction schemes including Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate acceleration CoreNet fabric that fully supports coherency using MESI protocol between the e6500 cores, SC3900 FVP cores, memories and external interfaces. CoreNet fabric interconnect runs at 667 MHz and supports coherent and non-coherent out of order transactions with prioritization and bandwidth allocation amongst CoreNet endpoints. Data Path Acceleration Architecture, which includes the following: Frame Manager (FMan), which supports in-line packet parsing and general classification to enable policing and QoS-based packet distribution Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading of queue management, task management, load distribution, flow ordering, buffer management, and allocation tasks from the cores Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, SSL, and 802.16 RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and outbound). Supports types 5, 6 (outbound only) Large internal cache memory with snooping and stashing capabilities for bandwidth saving and high utilization of processor elements. The 9856-Kbyte internal memory space includes the following: 32 Kbyte L1 ICache per e6500/SC3900 core 32 Kbyte L1 DCache per e6500/SC3900 core 2048 Kbyte unified L2 cache for each SC3900 FVP cluster 2048 Kbyte unified L2 cache for the e6500 cluster Two 512 Kbyte shared L3 CoreNet platform caches (CPC) Sixteen 10-GHz SerDes lanes serving: Two Serial RapidIO interfaces. Each supports up to 4 lanes and a total of up to 8 lanes Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue- less antenna connection Two 10-Gbit Ethernet controllers (10GEC) Six 1G/2.5-Gbit Ethernet controllers for network communications PCI Express controller Debug (Aurora) Two OCeaN DMAs Various system peripherals 182 32-bit timers Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 5440809e9c..78c412d9f3 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -68,6 +68,7 @@ COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5040) += ddr-gen3.o COBJS-$(CONFIG_PPC_T4240) += ddr-gen3.o +COBJS-$(CONFIG_PPC_B4860) += ddr-gen3.o COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o @@ -84,6 +85,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_ids.o COBJS-$(CONFIG_PPC_P5020) += p5020_ids.o COBJS-$(CONFIG_PPC_P5040) += p5040_ids.o COBJS-$(CONFIG_PPC_T4240) += t4240_ids.o +COBJS-$(CONFIG_PPC_B4860) += b4860_ids.o COBJS-$(CONFIG_QE) += qe_io.o COBJS-$(CONFIG_CPM2) += serial_scc.o @@ -117,6 +119,7 @@ COBJS-$(CONFIG_PPC_P4080) += p4080_serdes.o COBJS-$(CONFIG_PPC_P5020) += p5020_serdes.o COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o +COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o COBJS = $(COBJS-y) COBJS += cpu.o diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c new file mode 100644 index 0000000000..7d33731a7b --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c @@ -0,0 +1,141 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_DPAA_QBMAN +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { + /* dqrr liodn, frame data liodn, liodn off, sdest */ + SET_QP_INFO(1, 27, 1, 0), + SET_QP_INFO(2, 28, 1, 0), + SET_QP_INFO(3, 29, 1, 1), + SET_QP_INFO(4, 30, 1, 1), + SET_QP_INFO(5, 31, 1, 2), + SET_QP_INFO(6, 32, 1, 2), + SET_QP_INFO(7, 33, 1, 3), + SET_QP_INFO(8, 34, 1, 3), + SET_QP_INFO(9, 35, 1, 0), + SET_QP_INFO(10, 36, 1, 0), + SET_QP_INFO(11, 37, 1, 1), + SET_QP_INFO(12, 38, 1, 1), + SET_QP_INFO(13, 39, 1, 2), + SET_QP_INFO(14, 40, 1, 2), + SET_QP_INFO(15, 41, 1, 3), + SET_QP_INFO(16, 42, 1, 3), + SET_QP_INFO(17, 43, 1, 0), + SET_QP_INFO(18, 44, 1, 0), + SET_QP_INFO(19, 45, 1, 1), + SET_QP_INFO(20, 46, 1, 1), + SET_QP_INFO(21, 47, 1, 2), + SET_QP_INFO(22, 48, 1, 2), + SET_QP_INFO(23, 49, 1, 3), + SET_QP_INFO(24, 50, 1, 3), + SET_QP_INFO(25, 51, 1, 0), +}; +#endif + +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 307), + SET_SRIO_LIODN_1(2, 387), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + +struct liodn_id_table liodn_tbl[] = { +#ifdef CONFIG_SYS_DPAA_QBMAN + SET_QMAN_LIODN(62), + SET_BMAN_LIODN(63), +#endif + + SET_SDHC_LIODN(1, 552), + + SET_USB_LIODN(1, "fsl-usb2-mph", 553), + + SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148), + + SET_DMA_LIODN(1, 147), + SET_DMA_LIODN(2, 227), + + SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0), + SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0), + SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0), + SET_GUTS_LIODN(NULL, 202, rio2maintliodnr, 0), + + /* SET_NEXUS_LIODN(557), -- not yet implemented */ +}; +int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_FMAN +struct liodn_id_table fman1_liodn_tbl[] = { + SET_FMAN_RX_1G_LIODN(1, 0, 88), + SET_FMAN_RX_1G_LIODN(1, 1, 89), + SET_FMAN_RX_1G_LIODN(1, 2, 90), + SET_FMAN_RX_1G_LIODN(1, 3, 91), + SET_FMAN_RX_1G_LIODN(1, 4, 92), + SET_FMAN_RX_1G_LIODN(1, 5, 93), + SET_FMAN_RX_10G_LIODN(1, 0, 94), + SET_FMAN_RX_10G_LIODN(1, 1, 95), +}; +int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl); +#endif + +struct liodn_id_table sec_liodn_tbl[] = { + SET_SEC_JR_LIODN_ENTRY(0, 454, 458), + SET_SEC_JR_LIODN_ENTRY(1, 455, 459), + SET_SEC_JR_LIODN_ENTRY(2, 456, 460), + SET_SEC_JR_LIODN_ENTRY(3, 457, 461), + SET_SEC_RTIC_LIODN_ENTRY(a, 453), + SET_SEC_RTIC_LIODN_ENTRY(b, 549), + SET_SEC_RTIC_LIODN_ENTRY(c, 550), + SET_SEC_RTIC_LIODN_ENTRY(d, 551), + SET_SEC_DECO_LIODN_ENTRY(0, 541, 610), + SET_SEC_DECO_LIODN_ENTRY(1, 542, 611), + SET_SEC_DECO_LIODN_ENTRY(2, 543, 612), + SET_SEC_DECO_LIODN_ENTRY(3, 544, 613), + SET_SEC_DECO_LIODN_ENTRY(4, 545, 614), + SET_SEC_DECO_LIODN_ENTRY(5, 546, 615), + SET_SEC_DECO_LIODN_ENTRY(6, 547, 616), + SET_SEC_DECO_LIODN_ENTRY(7, 548, 617), +}; +int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); + +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 678), + SET_RMAN_LIODN(1, 679), + SET_RMAN_LIODN(2, 680), + SET_RMAN_LIODN(3, 681), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + +struct liodn_id_table liodn_bases[] = { + [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558), +#ifdef CONFIG_SYS_DPAA_FMAN + [FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973), +#endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(922), +#endif +}; diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c new file mode 100644 index 0000000000..9990202f42 --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c @@ -0,0 +1,162 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include "fsl_corenet2_serdes.h" + +struct serdes_config { + u8 protocol; + u8 lanes[SRDS_MAX_LANES]; +}; + +static struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {0x0D, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x0E, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x12, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x2a, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6, + CPRI6, CPRI5, CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x30, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x32, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x33, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x34, {AURORA, AURORA, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {0x3E, {CPRI8, CPRI7, CPRI6, CPRI5, + CPRI4, CPRI3, CPRI2, CPRI1}}, + {} +}; +static struct serdes_config serdes2_cfg_tbl[] = { + /* SerDes 2 */ + {0x18, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x1D, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x2B, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, SRIO1, SRIO1}}, + {0x30, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + AURORA, AURORA, + SRIO1, SRIO1}}, + {0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4C, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x4E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, AURORA, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {0x84, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x85, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, AURORA, AURORA, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x87, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SRIO2, SRIO2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0x93, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0x9E, {PCIE1, PCIE1, PCIE1, PCIE1, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0x9A, {PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XAUI_FM1_MAC10, XAUI_FM1_MAC10, + XAUI_FM1_MAC10, XAUI_FM1_MAC10}}, + {0xB2, {PCIE1, PCIE1, PCIE1, PCIE1, + SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, + XFI_FM1_MAC9, XFI_FM1_MAC10}}, + {0xC3, {XAUI_FM1_MAC9, XAUI_FM1_MAC9, + XAUI_FM1_MAC9, XAUI_FM1_MAC9, + SRIO1, SRIO1, SRIO1, SRIO1}}, + {} +}; +static struct serdes_config *serdes_cfg_tbl[] = { + serdes1_cfg_tbl, + serdes2_cfg_tbl, +}; + +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane) +{ + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == cfg) + return ptr->lanes[lane]; + ptr++; + } + + return 0; +} + +int is_serdes_prtcl_valid(int serdes, u32 prtcl) +{ + int i; + struct serdes_config *ptr; + + if (serdes >= ARRAY_SIZE(serdes_cfg_tbl)) + return 0; + + ptr = serdes_cfg_tbl[serdes]; + while (ptr->protocol) { + if (ptr->protocol == prtcl) + break; + ptr++; + } + + if (!ptr->protocol) + return 0; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (ptr->lanes[i] != NONE) + return 1; + } + + return 0; +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 4d96d1b107..2c487cac20 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -77,6 +77,13 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P5040, P5040, 4), CPU_TYPE_ENTRY(T4240, T4240, 0), CPU_TYPE_ENTRY(T4120, T4120, 0), + CPU_TYPE_ENTRY(B4860, B4860, 0), + CPU_TYPE_ENTRY(G4860, G4860, 0), + CPU_TYPE_ENTRY(G4060, G4060, 0), + CPU_TYPE_ENTRY(B4440, B4440, 0), + CPU_TYPE_ENTRY(G4440, G4440, 0), + CPU_TYPE_ENTRY(B4420, B4420, 0), + CPU_TYPE_ENTRY(B4220, B4220, 0), CPU_TYPE_ENTRY(BSC9130, 9130, 1), CPU_TYPE_ENTRY(BSC9131, 9131, 1), #elif defined(CONFIG_MPC86xx) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index cfa5448b5e..5e1d2e90f7 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -510,6 +510,29 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 +#elif defined(CONFIG_PPC_B4860) +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */ +#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ +#define CONFIG_MAX_CPUS 4 +#define CONFIG_SYS_FSL_NUM_CC_PLLS 4 +#define CONFIG_SYS_FSL_NUM_LAWS 32 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 6 +#define CONFIG_SYS_NUM_FM1_10GEC 2 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7 +#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 +#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" +#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_A_004934 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 5001f6eba2..969f726c36 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1729,6 +1729,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR2_10GEC2_2 0x00000400 #define FSL_CORENET_DEVDISR2_FM1 0x00000080 #define FSL_CORENET_DEVDISR2_FM2 0x00000040 +#define FSL_CORENET_DEVDISR2_CPRI 0x00000008 #define FSL_CORENET_DEVDISR3_PCIE1 0x80000000 #define FSL_CORENET_DEVDISR3_PCIE2 0x40000000 #define FSL_CORENET_DEVDISR3_PCIE3 0x20000000 @@ -1738,6 +1739,9 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR3_QMAN 0x00080000 #define FSL_CORENET_DEVDISR3_BMAN 0x00040000 #define FSL_CORENET_DEVDISR3_LA1 0x00008000 +#define FSL_CORENET_DEVDISR3_MAPLE1 0x00000800 +#define FSL_CORENET_DEVDISR3_MAPLE2 0x00000400 +#define FSL_CORENET_DEVDISR3_MAPLE3 0x00000200 #define FSL_CORENET_DEVDISR4_I2C1 0x80000000 #define FSL_CORENET_DEVDISR4_I2C2 0x40000000 #define FSL_CORENET_DEVDISR4_DUART1 0x20000000 @@ -1753,6 +1757,7 @@ typedef struct ccsr_gur { #define FSL_CORENET_DEVDISR5_GPIO 0x00400000 #define FSL_CORENET_DEVDISR5_DBG 0x00200000 #define FSL_CORENET_DEVDISR5_NAL 0x00100000 +#define FSL_CORENET_DEVDISR5_TIMERS 0x00020000 #define FSL_CORENET_NUM_DEVDISR 5 #else #define FSL_CORENET_DEVDISR_PCIE1 0x80000000 @@ -1835,6 +1840,11 @@ typedef struct ccsr_gur { #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT 11 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL 0x000000f8 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT 3 +#elif defined(CONFIG_PPC_B4860) +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfe000000 +#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 25 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL 0x00ff0000 +#define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT 16 #endif #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1 0x00800000 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2 0x00400000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 5bc0da6df1..7aa3231ad4 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1099,6 +1099,13 @@ #define SVR_P5040 0x820400 #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 +#define SVR_B4860 0X868000 +#define SVR_G4860 0x868001 +#define SVR_G4060 0x868003 +#define SVR_B4440 0x868100 +#define SVR_G4440 0x868101 +#define SVR_B4420 0x868102 +#define SVR_B4220 0x868103 #define SVR_8610 0x80A000 #define SVR_8641 0x809000 diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 73f64ad45a..4642c54ece 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -41,6 +41,7 @@ COBJS-$(CONFIG_PPC_P3041) += p5020.o COBJS-$(CONFIG_PPC_P4080) += p4080.o COBJS-$(CONFIG_PPC_P5020) += p5020.o COBJS-$(CONFIG_PPC_T4240) += t4240.o +COBJS-$(CONFIG_PPC_B4860) += b4860.o endif COBJS := $(COBJS-y)