From: Spencer Oliver Date: Thu, 3 May 2012 15:24:11 +0000 (+0100) Subject: build: use generic name for arm_algorithm vars X-Git-Tag: v0.6.0-rc1~102 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d2d4f776d8e24e8e651d1c896c90c15c38633172;p=openocd build: use generic name for arm_algorithm vars This makes the code a bit easier to read as arm_algorithm can refer to other arch's, not just armv4_5. Change-Id: I78c99d40f34cda04e06f2daee75b48ff40a1d23d Signed-off-by: Spencer Oliver Reviewed-on: http://openocd.zylin.com/613 Tested-by: jenkins Reviewed-by: Aurelien Jacobs Reviewed-by: Freddie Chopin --- diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c index dde4e69d..dce6a5e4 100644 --- a/src/flash/nor/aduc702x.c +++ b/src/flash/nor/aduc702x.c @@ -163,7 +163,7 @@ static int aduc702x_write_block(struct flash_bank *bank, struct working_area *source; uint32_t address = bank->base + offset; struct reg_param reg_params[6]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; int retval = ERROR_OK; if (((count%2) != 0) || ((offset%2) != 0)) { @@ -234,9 +234,9 @@ static int aduc702x_write_block(struct flash_bank *bank, } } - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -260,7 +260,7 @@ static int aduc702x_write_block(struct flash_bank *bank, reg_params, aduc702x_info->write_algorithm->address, aduc702x_info->write_algorithm->address + sizeof(aduc702x_flash_write_code) - 4, - 10000, &armv4_5_info); + 10000, &arm_algo); if (retval != ERROR_OK) { LOG_ERROR("error executing aduc702x flash write algorithm"); break; diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c index 0d8c694e..398dd61a 100644 --- a/src/flash/nor/cfi.c +++ b/src/flash/nor/cfi.c @@ -1146,7 +1146,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, struct cfi_flash_bank *cfi_info = bank->driver_priv; struct target *target = bank->target; struct reg_param reg_params[7]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; struct working_area *source = NULL; uint32_t buffer_size = 32768; uint32_t write_command_val, busy_pattern_val, error_pattern_val; @@ -1228,9 +1228,9 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, cfi_intel_clear_status_register(bank); - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; /* If we are setting up the write_algorith, we need target_code_src * if not we only need target_code_size. */ @@ -1344,7 +1344,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t), 10000, /* 10s should be enough for max. 32k of data */ - &armv4_5_info); + &arm_algo); /* On failure try a fall back to direct word writes */ if (retval != ERROR_OK) { @@ -1634,7 +1634,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext; struct target *target = bank->target; struct reg_param reg_params[10]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; struct working_area *source; uint32_t buffer_size = 32768; uint32_t status; @@ -1814,16 +1814,16 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, return cfi_spansion_write_block_mips(bank, buffer, address, count); if (is_armv7m(target_to_armv7m(target))) { /* Cortex-M3 target */ - armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC; - armv4_5_info.core_mode = ARMV7M_MODE_HANDLER; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARMV7M_COMMON_MAGIC; + arm_algo.core_mode = ARMV7M_MODE_HANDLER; + arm_algo.core_state = ARM_STATE_ARM; } else if (is_arm7_9(target_to_arm7_9(target))) { /* All other ARM CPUs have 32 bit instructions */ - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; } else { - LOG_ERROR("Unknown ARM architecture"); + LOG_ERROR("Unknown architecture"); return ERROR_FAIL; } @@ -1832,7 +1832,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, switch (bank->bus_width) { case 1: - if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) { + if (arm_algo.common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("Unknown ARM architecture"); return ERROR_FAIL; } @@ -1842,10 +1842,10 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, case 2: /* Check for DQ5 support */ if (cfi_info->status_poll_mask & (1 << 5)) { - if (armv4_5_info.common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */ + if (arm_algo.common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */ target_code_src = armv4_5_word_16_code; target_code_size = sizeof(armv4_5_word_16_code); - } else if (armv4_5_info.common_magic == ARMV7M_COMMON_MAGIC) { /* + } else if (arm_algo.common_magic == ARMV7M_COMMON_MAGIC) { /* *cortex-m3 *target **/ @@ -1854,7 +1854,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, } } else { /* No DQ5 support. Use DQ7 DATA# polling only. */ - if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) { + if (arm_algo.common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("Unknown ARM architecture"); return ERROR_FAIL; } @@ -1863,7 +1863,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, } break; case 4: - if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) { + if (arm_algo.common_magic != ARM_COMMON_MAGIC) { LOG_ERROR("Unknown ARM architecture"); return ERROR_FAIL; } @@ -1954,7 +1954,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, retval = target_run_algorithm(target, 0, NULL, 10, reg_params, cfi_info->write_algorithm->address, cfi_info->write_algorithm->address + ((target_code_size) - 4), - 10000, &armv4_5_info); + 10000, &arm_algo); if (retval != ERROR_OK) break; diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 04b5bfd1..f3d8f9e9 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -272,7 +272,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, struct target *target = bank->target; struct mem_param mem_params[2]; struct reg_param reg_params[5]; - struct arm_algorithm armv4_5_info; /* for LPC2000 */ + struct arm_algorithm arm_algo; /* for LPC2000 */ struct armv7m_algorithm armv7m_info; /* for LPC1700 */ uint32_t status_code; uint32_t iap_entry_point = 0; /* to make compiler happier */ @@ -322,9 +322,9 @@ static int lpc2000_iap_call(struct flash_bank *bank, break; case lpc2000_v1: case lpc2000_v2: - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; iap_entry_point = 0x7ffffff1; break; default: @@ -389,7 +389,7 @@ static int lpc2000_iap_call(struct flash_bank *bank, target_run_algorithm(target, 2, mem_params, 5, reg_params, lpc2000_info->iap_working_area->address, lpc2000_info->iap_working_area->address + 0x4, - 10000, &armv4_5_info); + 10000, &arm_algo); break; default: LOG_ERROR("BUG: unknown lpc2000->variant encountered"); diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c index 5701670b..5cdfcea5 100644 --- a/src/flash/nor/lpc2900.c +++ b/src/flash/nor/lpc2900.c @@ -1163,7 +1163,7 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer, if (warea) { struct reg_param reg_params[5]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; /* We can use target mode. Download the algorithm. */ retval = target_write_buffer(target, @@ -1270,15 +1270,15 @@ static int lpc2900_write(struct flash_bank *bank, uint8_t *buffer, buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time); /* Execute algorithm, assume breakpoint for last instruction */ - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; retval = target_run_algorithm(target, 0, NULL, 5, reg_params, (warea->address) + buffer_size, (warea->address) + buffer_size + target_code_size - 4, 10000, /* 10s should be enough for max. 16 KiB of data */ - &armv4_5_info); + &arm_algo); if (retval != ERROR_OK) { LOG_ERROR("Execution of flash algorithm failed."); diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c index 6cd5d69f..d7488410 100644 --- a/src/flash/nor/str7x.c +++ b/src/flash/nor/str7x.c @@ -454,7 +454,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, struct working_area *source; uint32_t address = bank->base + offset; struct reg_param reg_params[6]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; int retval = ERROR_OK; /* see contib/loaders/flash/str7x.s for src */ @@ -509,9 +509,9 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, } } - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -534,7 +534,7 @@ static int str7x_write_block(struct flash_bank *bank, uint8_t *buffer, retval = target_run_algorithm(target, 0, NULL, 6, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (sizeof(str7x_flash_write_code) - 4), - 10000, &armv4_5_info); + 10000, &arm_algo); if (retval != ERROR_OK) break; diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c index 472f922c..ea8c35ea 100644 --- a/src/flash/nor/str9x.c +++ b/src/flash/nor/str9x.c @@ -358,7 +358,7 @@ static int str9x_write_block(struct flash_bank *bank, struct working_area *source; uint32_t address = bank->base + offset; struct reg_param reg_params[4]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; int retval = ERROR_OK; /* see contib/loaders/flash/str9x.s for src */ @@ -413,9 +413,9 @@ static int str9x_write_block(struct flash_bank *bank, } } - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -433,7 +433,7 @@ static int str9x_write_block(struct flash_bank *bank, retval = target_run_algorithm(target, 0, NULL, 4, reg_params, str9x_info->write_algorithm->address, - 0, 10000, &armv4_5_info); + 0, 10000, &arm_algo); if (retval != ERROR_OK) { LOG_ERROR("error executing str9x flash write algorithm"); retval = ERROR_FLASH_OPERATION_FAILED; diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c index bf081946..3461da4c 100644 --- a/src/target/arm7_9_common.c +++ b/src/target/arm7_9_common.c @@ -2571,12 +2571,12 @@ int arm7_9_bulk_write_memory(struct target *target, return retval; } - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; struct reg_param reg_params[1]; - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); @@ -2587,7 +2587,7 @@ int arm7_9_bulk_write_memory(struct target *target, retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params, arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, - 20*1000, &armv4_5_info, arm7_9_dcc_completion); + 20*1000, &arm_algo, arm7_9_dcc_completion); if (retval == ERROR_OK) { uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32); diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c index 633e1c71..e31c77e4 100644 --- a/src/target/armv4_5.c +++ b/src/target/armv4_5.c @@ -1300,7 +1300,7 @@ int arm_checksum_memory(struct target *target, uint32_t address, uint32_t count, uint32_t *checksum) { struct working_area *crc_algorithm; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; struct arm *arm = target_to_arm(target); struct reg_param reg_params[2]; int retval; @@ -1352,9 +1352,9 @@ int arm_checksum_memory(struct target *target, return retval; } - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); init_reg_param(®_params[1], "r1", 32, PARAM_OUT); @@ -1372,7 +1372,7 @@ int arm_checksum_memory(struct target *target, retval = target_run_algorithm(target, 0, NULL, 2, reg_params, crc_algorithm->address, exit_var, - timeout, &armv4_5_info); + timeout, &arm_algo); if (retval != ERROR_OK) { LOG_ERROR("error executing ARM crc algorithm"); destroy_reg_param(®_params[0]); @@ -1402,7 +1402,7 @@ int arm_blank_check_memory(struct target *target, { struct working_area *check_algorithm; struct reg_param reg_params[3]; - struct arm_algorithm armv4_5_info; + struct arm_algorithm arm_algo; struct arm *arm = target_to_arm(target); int retval; uint32_t i; @@ -1436,9 +1436,9 @@ int arm_blank_check_memory(struct target *target, return retval; } - armv4_5_info.common_magic = ARM_COMMON_MAGIC; - armv4_5_info.core_mode = ARM_MODE_SVC; - armv4_5_info.core_state = ARM_STATE_ARM; + arm_algo.common_magic = ARM_COMMON_MAGIC; + arm_algo.core_mode = ARM_MODE_SVC; + arm_algo.core_state = ARM_STATE_ARM; init_reg_param(®_params[0], "r0", 32, PARAM_OUT); buf_set_u32(reg_params[0].value, 0, 32, address); @@ -1456,7 +1456,7 @@ int arm_blank_check_memory(struct target *target, retval = target_run_algorithm(target, 0, NULL, 3, reg_params, check_algorithm->address, exit_var, - 10000, &armv4_5_info); + 10000, &arm_algo); if (retval != ERROR_OK) { destroy_reg_param(®_params[0]); destroy_reg_param(®_params[1]);