From: Patrice Chotard Date: Wed, 15 Nov 2017 12:14:43 +0000 (+0100) Subject: ARM: DTS: stm32: add pwrcfg node for stm32f746 X-Git-Tag: v2018.01-rc1~56 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d3651aac4685a21a716c33b0c9636288b013da38;p=u-boot ARM: DTS: stm32: add pwrcfg node for stm32f746 This node is needed to enable performance mode when system frequency is set up to 200Mhz. Signed-off-by: Patrice Chotard Reviewed-by: Vikas Manocha --- diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index 5f77f578af..a56ae93121 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -22,3 +22,7 @@ u-boot,dm-pre-reloc; }; }; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi index 783d4e734e..b95cca21b6 100644 --- a/arch/arm/dts/stm32f746.dtsi +++ b/arch/arm/dts/stm32f746.dtsi @@ -99,12 +99,19 @@ status = "disabled"; u-boot,dm-pre-reloc; }; + + pwrcfg: power-config@58024800 { + compatible = "syscon"; + reg = <0x40007000 0x400>; + }; + rcc: rcc@40023810 { #reset-cells = <1>; #clock-cells = <2>; compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; reg = <0x40023800 0x400>; clocks = <&clk_hse>; + st,syscfg = <&pwrcfg>; u-boot,dm-pre-reloc; };