From: Kumar Gala <galak@kernel.crashing.org>
Date: Fri, 7 Dec 2007 10:59:26 +0000 (-0600)
Subject: Handle Asynchronous DDR clock on 85xx
X-Git-Tag: v1.3.2-rc1~109^2~2
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d435793229ce29a42797c1edc39f5b34f987f91a;p=u-boot

Handle Asynchronous DDR clock on 85xx

The MPC8572 introduces the concept of an asynchronous DDR clock with
regards to the platform clock.

Introduce get_ddr_freq() to report the DDR freq regardless of sync/async
mode.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index e55d337289..ac8b018b0a 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -39,6 +39,8 @@ int checkcpu (void)
 	uint fam;
 	uint ver;
 	uint major, minor;
+	u32 ddr_ratio;
+	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 
 	svr = get_svr();
 	ver = SVR_VER(svr);
@@ -102,7 +104,19 @@ int checkcpu (void)
 	puts("Clock Configuration:\n");
 	printf("       CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
 	printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
-	printf("       DDR:%4lu MHz, ", sysinfo.freqSystemBus / 2000000);
+
+	ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+	switch (ddr_ratio) {
+	case 0x0:
+		printf("       DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
+		break;
+	case 0x7:
+		printf("       DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
+		break;
+	default:
+		printf("       DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
+		break;
+	}
 
 #if defined(CFG_LBC_LCRR)
 	lcrr = CFG_LBC_LCRR;
diff --git a/cpu/mpc85xx/spd_sdram.c b/cpu/mpc85xx/spd_sdram.c
index 2a4cd57b69..553f736a56 100644
--- a/cpu/mpc85xx/spd_sdram.c
+++ b/cpu/mpc85xx/spd_sdram.c
@@ -53,8 +53,8 @@ picos_to_clk(int picos)
 {
 	int clks;
 
-	clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
-	if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
+	clks = picos / (2000000000 / (get_ddr_freq(0) / 1000));
+	if (picos % (2000000000 / (get_ddr_freq(0) / 1000)) != 0) {
 		clks++;
 	}
 
@@ -421,7 +421,7 @@ spd_sdram(void)
 	 * Adjust the CAS Latency to allow for bus speeds that
 	 * are slower than the DDR module.
 	 */
-	busfreq = get_bus_freq(0) / 1000000;	/* MHz */
+	busfreq = get_ddr_freq(0) / 1000000;	/* MHz */
 
 	effective_data_rate = max_data_rate;
 	if (busfreq < 90) {
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 293269c573..27de37afa8 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -48,6 +48,15 @@ void get_sys_info (sys_info_t * sysInfo)
 	 * overflow for processor speeds above 2GHz */
 	half_freqSystemBus = sysInfo->freqSystemBus/2;
 	sysInfo->freqProcessor = e500_ratio*half_freqSystemBus;
+	sysInfo->freqDDRBus = sysInfo->freqSystemBus;
+
+#ifdef CONFIG_DDR_CLK_FREQ
+	{
+		u32 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
+		if (ddr_ratio != 0x7)
+			sysInfo->freqDDRBus = ddr_ratio * CONFIG_DDR_CLK_FREQ;
+	}
+#endif
 }
 
 
@@ -93,3 +102,19 @@ ulong get_bus_freq (ulong dummy)
 
 	return val;
 }
+
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq (ulong dummy)
+{
+	ulong val;
+
+	sys_info_t sys_info;
+
+	get_sys_info (&sys_info);
+	val = sys_info.freqDDRBus;
+
+	return val;
+}
diff --git a/include/common.h b/include/common.h
index 63ac8b062c..01957e3d5f 100644
--- a/include/common.h
+++ b/include/common.h
@@ -497,6 +497,7 @@ ulong	get_bus_freq  (ulong);
 #if defined(CONFIG_MPC85xx)
 typedef MPC85xx_SYS_INFO sys_info_t;
 void	get_sys_info  ( sys_info_t * );
+ulong	get_ddr_freq  (ulong);
 #endif
 #if defined(CONFIG_MPC86xx)
 typedef MPC86xx_SYS_INFO sys_info_t;
diff --git a/include/e500.h b/include/e500.h
index 8e3bf8cb7d..0d73260f40 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -12,6 +12,7 @@ typedef struct
 {
   unsigned long freqProcessor;
   unsigned long freqSystemBus;
+  unsigned long freqDDRBus;
 } MPC85xx_SYS_INFO;
 
 #endif  /* _ASMLANGUAGE */