From: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
Date: Tue, 25 Mar 2008 12:30:07 +0000 (+0900)
Subject: [MIPS] Initialize CP0 Cause before setting up CP0 Status register
X-Git-Tag: v1.3.3-rc1~171^2~5
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d43d43ef2845af309c25a64bb9c2c5fb3261bc23;p=u-boot

[MIPS] Initialize CP0 Cause before setting up CP0 Status register

Without this change, we'll be suffering from deffered WATCH exception
once Status.EXL is cleared. Make sure Cause.WP is cleared.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
---

diff --git a/cpu/mips/start.S b/cpu/mips/start.S
index fde2944a0d..0ecdd83636 100644
--- a/cpu/mips/start.S
+++ b/cpu/mips/start.S
@@ -211,6 +211,9 @@ reset:
 	mtc0	zero, CP0_WATCHLO
 	mtc0	zero, CP0_WATCHHI
 
+	/* WP(Watch Pending), SW0/1 should be cleared. */
+	mtc0	zero, CP0_CAUSE
+
 	/* STATUS register */
 #ifdef  CONFIG_TB0229
 	li	k0, ST0_CU0
@@ -221,9 +224,6 @@ reset:
 	and	k0, k1
 	mtc0	k0, CP0_STATUS
 
-	/* CAUSE register */
-	mtc0	zero, CP0_CAUSE
-
 	/* Init Timer */
 	mtc0	zero, CP0_COUNT
 	mtc0	zero, CP0_COMPARE