From: Spencer Oliver <spen@spen-soft.co.uk>
Date: Tue, 1 May 2012 13:00:27 +0000 (+0100)
Subject: stlink: support connecting under reset
X-Git-Tag: v0.6.0-rc1~97
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d469c686d9c4aaef7dc0ff8376142b8fdd6d1dbd;p=openocd

stlink: support connecting under reset

Some targets support connecting while the target's srst is asserted.
Tested on stm32 family.

Change-Id: I1197dd721a1e1cbf95ee77dfd8e1082b165b22a9
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/607
Tested-by: jenkins
---

diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c
index f9daa014..4044654c 100644
--- a/src/target/stm32_stlink.c
+++ b/src/target/stm32_stlink.c
@@ -406,7 +406,7 @@ static int stm32_stlink_poll(struct target *target)
 
 static int stm32_stlink_assert_reset(struct target *target)
 {
-	int res;
+	int res = ERROR_OK;
 	struct stlink_interface_s *stlink_if = target_to_stlink(target);
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	bool use_srst_fallback = true;
@@ -415,12 +415,22 @@ static int stm32_stlink_assert_reset(struct target *target)
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
+	bool srst_asserted = false;
+
+	if (jtag_reset_config & RESET_SRST_NO_GATING) {
+		jtag_add_reset(0, 1);
+		res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+		srst_asserted = true;
+	}
+
 	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 	stlink_if->layout->api->write_debug_reg(stlink_if->fd, DCB_DEMCR, VC_CORERESET);
 
 	if (jtag_reset_config & RESET_HAS_SRST) {
-		jtag_add_reset(0, 1);
-		res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+		if (!srst_asserted) {
+			jtag_add_reset(0, 1);
+			res = stlink_if->layout->api->assert_srst(stlink_if->fd, 0);
+		}
 		if (res == ERROR_COMMAND_NOTFOUND)
 			LOG_ERROR("Hardware srst not supported, falling back to software reset");
 		else if (res == ERROR_OK) {