From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Thu, 17 Nov 2016 06:59:54 +0000 (+0530)
Subject: armv8: fsl-layerscape : Check SVR for initializing TZASC
X-Git-Tag: v2017.01-rc1~212^2~8
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d5df606d17f80d78e4d577e80fd0034dc66486be;p=u-boot

armv8: fsl-layerscape : Check SVR for initializing TZASC

LS2080 SoC and its personalities does not support TZASC
But other new SoCs like LS2088A, LS1088A supports TZASC

Hence, skip initializing TZASC for Ls2080A based on SVR

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index ac189d3c15..f7b49cb9fe 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -15,6 +15,7 @@
 #endif
 #ifdef CONFIG_FSL_LSCH3
 #include <asm/arch-fsl-layerscape/immap_lsch3.h>
+#include <asm/arch-fsl-layerscape/soc.h>
 #endif
 
 ENTRY(lowlevel_init)
@@ -140,6 +141,16 @@ ENTRY(lowlevel_init)
 #endif
 
 #ifdef CONFIG_FSL_TZASC_400
+	/*
+	 * LS2080 and its personalities does not support TZASC
+	 * So skip TZASC related operations
+	 */
+	bl	get_svr
+	lsr	w0, w0, #16
+	ldr	w1, =SVR_DEV_LS2080A
+	cmp	w0, w1
+	b.eq	1f
+
 	/* Set TZASC so that:
 	 * a. We use only Region0 whose global secure write/read is EN
 	 * b. We use only Region0 whose NSAID write/read is EN
@@ -182,7 +193,7 @@ ENTRY(lowlevel_init)
 	isb
 	dsb	sy
 #endif
-
+1:
 #ifdef CONFIG_ARCH_LS1046A
 	/* Initialize the L2 RAM latency */
 	mrs   x1, S3_1_c11_c0_2