From: Paul Burton Date: Wed, 21 Sep 2016 10:18:58 +0000 (+0100) Subject: MIPS: Clear hazard between TagLo writes & cache ops X-Git-Tag: v2016.11-rc1~120^2~15 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d608254b0aa23607df1dcb5a7ca07de9a8ec9bb0;p=u-boot MIPS: Clear hazard between TagLo writes & cache ops Writing to the coprocessor 0 TagLo registers introduces an execution hazard in that we need that write to complete before any cache instructions execute. Ensure that hazard is cleared by inserting an ehb instruction between the TagLo writes & cache op loop. Signed-off-by: Paul Burton --- diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S index e61432ee9c..53e903a27e 100644 --- a/arch/mips/lib/cache_init.S +++ b/arch/mips/lib/cache_init.S @@ -293,6 +293,7 @@ l2_init: l1_init: mtc0 zero, CP0_TAGLO mtc0 zero, CP0_TAGLO, 2 + ehb /* * The caches are probably in an indeterminate state, so we force good