From: Michal Simek <michal.simek@xilinx.com>
Date: Fri, 1 Dec 2017 14:50:31 +0000 (+0100)
Subject: arm64: zynqmp: Enable phys for zcu102
X-Git-Tag: v2018.01-rc2~8^2~14
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d70cb51830406fd3fd89c595b7b4995e4c75da41;p=u-boot

arm64: zynqmp: Enable phys for zcu102

Enable USB3.0 and SATA phy for zcu102 boards.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index a2128ebfd8..2e382562c4 100644
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -14,6 +14,7 @@
 #include "zynqmp-clk.dtsi"
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
 
 / {
 	model = "ZynqMP ZCU102 RevA";
@@ -884,6 +885,8 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
 	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
 	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+	phy-names = "sata-phy";
+	phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
 };
 
 /* SD1 with level shifter */
@@ -895,6 +898,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 	xlnx,mio_bank = <1>;
 };
 
+&serdes {
+	status = "okay";
+};
+
 &uart0 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -917,6 +924,10 @@ drivers/hwmon/pmbus/Makefile:11:obj-$(CONFIG_SENSORS_MAX20751)  += max20751.o
 &dwc3_0 {
 	status = "okay";
 	dr_mode = "host";
+	snps,usb3_lpm_capable;
+	phy-names = "usb3-phy";
+	phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
+	maximum-speed = "super-speed";
 };
 
 &watchdog0 {