From: Peng Fan Date: Mon, 20 Jul 2015 11:28:24 +0000 (+0800) Subject: imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL X-Git-Tag: v2015.10-rc1~2^2~12 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d73d5aee3c5585e67ece5f6e263259fceaadf890;p=u-boot imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6UL Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan --- diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index d8b5d6f767..4d84a9b753 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -9,7 +9,11 @@ #define ARCH_MXC +#ifdef CONFIG_MX6UL +#define CONFIG_SYS_CACHELINE_SIZE 64 +#else #define CONFIG_SYS_CACHELINE_SIZE 32 +#endif #define ROMCP_ARB_BASE_ADDR 0x00000000 #define ROMCP_ARB_END_ADDR 0x000FFFFF