From: Stefan Roese <sr@denx.de>
Date: Sat, 22 Dec 2007 11:18:26 +0000 (+0100)
Subject: ppc4xx: Fix problem in 44x cache POST routine
X-Git-Tag: v1.3.2-rc1~102^2~57^2~26
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=d91722102cf63f77a0148ed3f3d54a26d87575e9;p=u-boot

ppc4xx: Fix problem in 44x cache POST routine

As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.

Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c
index 30d5088425..c8ddf35a08 100644
--- a/post/cpu/ppc4xx/cache.c
+++ b/post/cpu/ppc4xx/cache.c
@@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size);
 int cache_post_test5 (int tlb, void *p, int size);
 int cache_post_test6 (int tlb, void *p, int size);
 
-static int tlb = -1;		/* index to the victim TLB entry */
-
 #ifdef CONFIG_440
 static unsigned char testarea[CACHE_POST_SIZE]
 __attribute__((__aligned__(CACHE_POST_SIZE)));
@@ -60,7 +58,7 @@ __attribute__((__aligned__(CACHE_POST_SIZE)));
 
 int cache_post_test (int flags)
 {
-	void* virt = (void*)CFG_POST_CACHE_ADDR;
+	void *virt = (void *)CFG_POST_CACHE_ADDR;
 	int ints;
 	int res = 0;
 
@@ -72,26 +70,25 @@ int cache_post_test (int flags)
 	 */
 #ifdef CONFIG_440
 	int word0, i;
+	int tlb;		/* index to the victim TLB entry */
 
-	if (tlb < 0) {
-		/*
-		 * Allocate a new TLB entry, since we are going to modify
-		 * the write-through and caching inhibited storage attributes.
-		 */
-		program_tlb((u32)testarea, (u32)virt,
-			    CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
-
-		/* Find the TLB entry */
-		for (i = 0;; i++) {
-			if (i >= PPC4XX_TLB_SIZE) {
-				printf ("Failed to program tlb entry\n");
-				return -1;
-			}
-			word0 = mftlb1(i);
-			if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
-				tlb = i;
-				break;
-			}
+	/*
+	 * Allocate a new TLB entry, since we are going to modify
+	 * the write-through and caching inhibited storage attributes.
+	 */
+	program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
+		    TLB_WORD2_I_ENABLE);
+
+	/* Find the TLB entry */
+	for (i = 0;; i++) {
+		if (i >= PPC4XX_TLB_SIZE) {
+			printf ("Failed to program tlb entry\n");
+			return -1;
+		}
+		word0 = mftlb1(i);
+		if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
+			tlb = i;
+			break;
 		}
 	}
 #endif