From: Bin Meng Date: Mon, 26 Jun 2017 23:36:15 +0000 (-0700) Subject: Revert "x86: Convert MMC to driver model" X-Git-Tag: v2017.07-rc3~28^2 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=da2364cc14a0b34411c4a228ae687a23504afe04;p=u-boot Revert "x86: Convert MMC to driver model" This reverts commit ddb3ac3c716f56cead695444e65a7ba7b0946555. With MMC converted to driver model, SCSI driver is broken due to zero address access at (ops->read) in block_dread() function. The fix (SCSI driver converted to DM) is ready in u-boot-dm branch, but it is too late for this relese to get that in. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- diff --git a/arch/Kconfig b/arch/Kconfig index e44767113d..d04ab9f177 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -96,7 +96,6 @@ config X86 select DM_SPI select DM_SPI_FLASH select USB_EHCI_HCD - select DM_MMC if MMC imply CMD_FPGA_LOADMK imply CMD_GETTIME imply CMD_IO diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index c58f6a86a8..87ba849c1c 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -11,6 +11,18 @@ #include #include +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2 }, + {}, +}; + +int cpu_mmc_init(bd_t *bis) +{ + return pci_mmc_init("ValleyView SDHCI", mmc_supported); +} + #ifndef CONFIG_EFI_APP int arch_cpu_init(void) { diff --git a/arch/x86/cpu/quark/quark.c b/arch/x86/cpu/quark/quark.c index c36a5892d5..0c2cea4ee9 100644 --- a/arch/x86/cpu/quark/quark.c +++ b/arch/x86/cpu/quark/quark.c @@ -16,6 +16,11 @@ #include #include +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO }, + {}, +}; + static void quark_setup_mtrr(void) { u32 base, mask; @@ -323,6 +328,11 @@ int arch_early_init_r(void) return 0; } +int cpu_mmc_init(bd_t *bis) +{ + return pci_mmc_init("Quark SDHCI", mmc_supported); +} + int arch_misc_init(void) { #ifdef CONFIG_ENABLE_MRC_CACHE diff --git a/arch/x86/cpu/queensbay/Makefile b/arch/x86/cpu/queensbay/Makefile index c0681995bd..af3ffad385 100644 --- a/arch/x86/cpu/queensbay/Makefile +++ b/arch/x86/cpu/queensbay/Makefile @@ -5,4 +5,4 @@ # obj-y += fsp_configs.o irq.o -obj-y += tnc.o +obj-y += tnc.o topcliff.o diff --git a/arch/x86/cpu/queensbay/topcliff.c b/arch/x86/cpu/queensbay/topcliff.c new file mode 100644 index 0000000000..b76dd7de69 --- /dev/null +++ b/arch/x86/cpu/queensbay/topcliff.c @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2014, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static struct pci_device_id mmc_supported[] = { + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0 }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1 }, + {}, +}; + +int cpu_mmc_init(bd_t *bis) +{ + return pci_mmc_init("Topcliff SDHCI", mmc_supported); +} diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index 6db89779ba..e39b476834 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -6,71 +6,37 @@ */ #include -#include #include #include -#include #include #include -struct pci_mmc_plat { - struct mmc_config cfg; - struct mmc mmc; -}; - -struct pci_mmc_priv { - struct sdhci_host host; - void *base; -}; - -static int pci_mmc_probe(struct udevice *dev) +int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported) { - struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); - struct pci_mmc_plat *plat = dev_get_platdata(dev); - struct pci_mmc_priv *priv = dev_get_priv(dev); - struct sdhci_host *host = &priv->host; - u32 ioaddr; + struct sdhci_host *mmc_host; + u32 iobase; int ret; - - dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &ioaddr); - host->ioaddr = map_sysmem(ioaddr, 0); - host->name = dev->name; - ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0); - if (ret) - return ret; - host->mmc = &plat->mmc; - host->mmc->priv = &priv->host; - host->mmc->dev = dev; - upriv->mmc = host->mmc; - - return sdhci_probe(dev); + int i; + + for (i = 0; ; i++) { + struct udevice *dev; + + ret = pci_find_device_id(mmc_supported, i, &dev); + if (ret) + return ret; + mmc_host = malloc(sizeof(struct sdhci_host)); + if (!mmc_host) + return -ENOMEM; + + mmc_host->name = name; + dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); + mmc_host->ioaddr = (void *)(ulong)iobase; + mmc_host->quirks = 0; + mmc_host->max_clk = 0; + ret = add_sdhci(mmc_host, 0, 0); + if (ret) + return ret; + } + + return 0; } - -static int pci_mmc_bind(struct udevice *dev) -{ - struct pci_mmc_plat *plat = dev_get_platdata(dev); - - return sdhci_bind(dev, &plat->mmc, &plat->cfg); -} - -U_BOOT_DRIVER(pci_mmc) = { - .name = "pci_mmc", - .id = UCLASS_MMC, - .bind = pci_mmc_bind, - .probe = pci_mmc_probe, - .ops = &sdhci_ops, - .priv_auto_alloc_size = sizeof(struct pci_mmc_priv), - .platdata_auto_alloc_size = sizeof(struct pci_mmc_plat), -}; - -static struct pci_device_id mmc_supported[] = { - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SDIO) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_SD) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BYT_EMMC2) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_SDIO) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_0) }, - { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SDIO_1) }, - {}, -}; - -U_BOOT_PCI_DEVICE(pci_mmc, mmc_supported); diff --git a/include/mmc.h b/include/mmc.h index 6a0ea0af21..00576fa3d0 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -585,6 +585,18 @@ int cpu_mmc_init(bd_t *bis); int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr); int mmc_get_env_dev(void); +struct pci_device_id; + +/** + * pci_mmc_init() - set up PCI MMC devices + * + * This finds all the matching PCI IDs and sets them up as MMC devices. + * + * @name: Name to use for devices + * @mmc_supported: PCI IDs to search for, terminated by {0, 0} + */ +int pci_mmc_init(const char *name, struct pci_device_id *mmc_supported); + /* Set block count limit because of 16 bit register limit on some hardware*/ #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535