From: ntfreak <ntfreak@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Tue, 22 Jul 2008 14:30:52 +0000 (+0000)
Subject: - fix bug with stm32 high density write protection
X-Git-Tag: v0.1.0~441
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=dad28d0659f53ae87a85c1fe5663f677594a9ecd;p=openocd

- fix bug with stm32 high density write protection

git-svn-id: svn://svn.berlios.de/openocd/trunk@858 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---

diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c
index a8125f47..899dad99 100644
--- a/src/flash/stm32x.c
+++ b/src/flash/stm32x.c
@@ -385,15 +385,43 @@ int stm32x_protect(struct flash_bank_s *bank, int set, int first, int last)
 	prot_reg[2] = (u16)(protection >> 16);
 	prot_reg[3] = (u16)(protection >> 24);
 	
-	for (i = first; i <= last; i++)
+	if (stm32x_info->ppage_size == 2)
 	{
-		reg = (i / stm32x_info->ppage_size) / 8;
-		bit = (i / stm32x_info->ppage_size) - (reg * 8);
+		/* high density flash */
 		
-		if( set )
-			prot_reg[reg] &= ~(1 << bit);
-		else
-			prot_reg[reg] |= (1 << bit);
+		/* bit 7 controls sector 62 - 255 protection */
+		if (first > 61 || last <= 255)
+			prot_reg[3] |= (1 << 7);
+		
+		if (first > 61)
+			first = 61;
+		if (last > 61)
+			last = 61;
+		
+		for (i = first; i <= last; i++)
+		{
+			reg = (i / stm32x_info->ppage_size) / 8;
+			bit = (i / stm32x_info->ppage_size) - (reg * 8);
+			
+			if( set )
+				prot_reg[reg] &= ~(1 << bit);
+			else
+				prot_reg[reg] |= (1 << bit);
+		}
+	}
+	else
+	{
+		/* medium density flash */
+		for (i = first; i <= last; i++)
+		{
+			reg = (i / stm32x_info->ppage_size) / 8;
+			bit = (i / stm32x_info->ppage_size) - (reg * 8);
+			
+			if( set )
+				prot_reg[reg] &= ~(1 << bit);
+			else
+				prot_reg[reg] |= (1 << bit);
+		}
 	}
 	
 	if ((status = stm32x_erase_options(bank)) != ERROR_OK)
diff --git a/src/tcl/cpu/arm/cortex_m3.tcl b/src/tcl/cpu/arm/cortex_m3.tcl
index b4bbcce1..166af847 100644
--- a/src/tcl/cpu/arm/cortex_m3.tcl
+++ b/src/tcl/cpu/arm/cortex_m3.tcl
@@ -1,6 +1,6 @@
-set CPU_TYPE   arm
-set CPU_NAME   cortex_m3
-set CPU_ARCH   armv7
-set CPU_MAX_ADDRESS 0xFFFFFFFF
-set CPU_NBITS  32
-
+set CPU_TYPE   arm
+set CPU_NAME   cortex_m3
+set CPU_ARCH   armv7
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
+