From: Marek Vasut <marex@denx.de>
Date: Sat, 18 Jul 2015 05:23:25 +0000 (+0200)
Subject: ddr: altera: Clean up rw_mgr_mem_calibrate_writes()
X-Git-Tag: v2015.10-rc2~244
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=db3a606158f01ff20adbc42e8d682cdfff29165a;p=u-boot

ddr: altera: Clean up rw_mgr_mem_calibrate_writes()

Reorder the content of the function a little and fix the comments
so they at least become full sentences. Constify function args.
Fix the return value to match the common convention of 0 meaning
success.

Signed-off-by: Marek Vasut <marex@denx.de>
---

diff --git a/drivers/ddr/altera/sequencer.c b/drivers/ddr/altera/sequencer.c
index 0d1e6c877c..714fdf081b 100644
--- a/drivers/ddr/altera/sequencer.c
+++ b/drivers/ddr/altera/sequencer.c
@@ -3160,25 +3160,37 @@ static uint32_t rw_mgr_mem_calibrate_writes_center(uint32_t rank_bgn,
 	return (dq_margin >= 0) && (dqs_margin >= 0) && (dm_margin >= 0);
 }
 
-/* calibrate the write operations */
-static uint32_t rw_mgr_mem_calibrate_writes(uint32_t rank_bgn, uint32_t g,
-	uint32_t test_bgn)
+/**
+ * rw_mgr_mem_calibrate_writes() - Write Calibration Part One
+ * @rank_bgn:		Rank number
+ * @group:		Read/Write Group
+ * @test_bgn:		Rank at which the test begins
+ *
+ * Stage 2: Write Calibration Part One.
+ *
+ * This function implements UniPHY calibration Stage 2, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ */
+static int rw_mgr_mem_calibrate_writes(const u32 rank_bgn, const u32 group,
+				       const u32 test_bgn)
 {
-	/* update info for sims */
-	debug("%s:%d %u %u\n", __func__, __LINE__, g, test_bgn);
+	int ret;
+
+	/* Update info for sims */
+	debug("%s:%d %u %u\n", __func__, __LINE__, group, test_bgn);
 
+	reg_file_set_group(group);
 	reg_file_set_stage(CAL_STAGE_WRITES);
 	reg_file_set_sub_stage(CAL_SUBSTAGE_WRITES_CENTER);
 
-	reg_file_set_group(g);
-
-	if (!rw_mgr_mem_calibrate_writes_center(rank_bgn, g, test_bgn)) {
-		set_failing_group_stage(g, CAL_STAGE_WRITES,
+	ret = rw_mgr_mem_calibrate_writes_center(rank_bgn, group, test_bgn);
+	if (!ret) {
+		set_failing_group_stage(group, CAL_STAGE_WRITES,
 					CAL_SUBSTAGE_WRITES_CENTER);
-		return 0;
+		return -EIO;
 	}
 
-	return 1;
+	return 0;
 }
 
 /**
@@ -3472,7 +3484,7 @@ static uint32_t mem_calibrate(void)
 					continue;
 
 				/* Calibrate WRITEs */
-				if (rw_mgr_mem_calibrate_writes(rank_bgn,
+				if (!rw_mgr_mem_calibrate_writes(rank_bgn,
 						write_group, write_test_bgn))
 					continue;