From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
Date: Tue, 17 May 2016 11:19:01 +0000 (+0530)
Subject: ARM64: zynqmp: Add device tree properties for ZynqMP GT core
X-Git-Tag: v2017.01-rc1~258
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=db6c62e1b945364295812c7be46ea1a630f9bcd3;p=u-boot

ARM64: zynqmp: Add device tree properties for ZynqMP GT core

This patch adds the ZynqMP GT core device-tree properties for
zynqmp.dtsi file.

Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Tested-by: Hyun Kwon <hyunk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---

diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index b796c34449..edfa03ac67 100644
--- a/arch/arm/dts/zynqmp.dtsi
+++ b/arch/arm/dts/zynqmp.dtsi
@@ -688,6 +688,29 @@
 			interrupt-names = "alarm", "sec";
 		};
 
+		serdes: zynqmp_phy@fd400000 {
+			compatible = "xlnx,zynqmp-psgtr";
+			status = "disabled";
+			reg = <0x0 0xfd400000 0x40000>,
+			      <0x0 0xfd3d0000 0x1000>,
+			      <0x0 0xfd1a0000 0x1000>,
+			      <0x0 0xff5e0000 0x1000>;
+			reg-names = "serdes", "siou", "fpd", "lpd";
+			xlnx,tx_termination_fix;
+			lane0: lane0 {
+				#phy-cells = <4>;
+			};
+			lane1: lane1 {
+				#phy-cells = <4>;
+			};
+			lane2: lane2 {
+				#phy-cells = <4>;
+			};
+			lane3: lane3 {
+				#phy-cells = <4>;
+			};
+		};
+
 		sata: ahci@fd0c0000 {
 			compatible = "ceva,ahci-1v84";
 			status = "disabled";