From: Mathias K <kesmtp@freenet.de>
Date: Sat, 10 Mar 2012 13:34:44 +0000 (+0100)
Subject: stm32: Add floating point register read/write.
X-Git-Tag: v0.6.0-rc1~186
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=dbb8de15e39390bf5f323dddb8e5f090515977d1;p=openocd

stm32: Add floating point register read/write.

This patch add floating point register read/write
functionality through the SCS debug interface.

Change-Id: Id20e109dd7cccba00671d55ca8aabeb4936cceb9
Signed-off-by: Mathias K <kesmtp@freenet.de>
Reviewed-on: http://openocd.zylin.com/512
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
---

diff --git a/src/target/stm32_stlink.c b/src/target/stm32_stlink.c
index 64e83f53..d2f38e5a 100644
--- a/src/target/stm32_stlink.c
+++ b/src/target/stm32_stlink.c
@@ -38,6 +38,9 @@
 #include "cortex_m.h"
 #include "arm_semihosting.h"
 
+#define ARMV7M_SCS_DCRSR	0xe000edf4
+#define ARMV7M_SCS_DCRDR	0xe000edf8
+
 static inline struct stlink_interface_s *target_to_stlink(struct target *target)
 {
 	return target->tap->priv;
@@ -65,8 +68,19 @@ static int stm32_stlink_load_core_reg_u32(struct target *target,
 			LOG_ERROR("JTAG failure %i", retval);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",
-			  (int)num, *value);
+		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
+		break;
+
+	case 33:
+	case 64 ... 96:
+		/* Floating-point Status and Registers */
+		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_read_u32(target, ARMV7M_SCS_DCRDR, value);
+		if (retval != ERROR_OK)
+			return retval;
+		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "", (int)num, *value);
 		break;
 
 	case ARMV7M_PRIMASK:
@@ -150,6 +164,18 @@ static int stm32_stlink_store_core_reg_u32(struct target *target,
 		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 		break;
 
+	case 33:
+	case 64 ... 96:
+		/* Floating-point Status and Registers */
+		retval = target_write_u32(target, ARMV7M_SCS_DCRDR, value);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target_write_u32(target, ARMV7M_SCS_DCRSR, num | (1<<16));
+		if (retval != ERROR_OK)
+			return retval;
+		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
+		break;
+
 	case ARMV7M_PRIMASK:
 	case ARMV7M_BASEPRI:
 	case ARMV7M_FAULTMASK: