From: rtel Date: Mon, 21 Oct 2019 04:16:32 +0000 (+0000) Subject: Update RISK-V GCC port to ensure the first task starts with interrupts enabled -... X-Git-Tag: V10.3.0~78 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=dc399f97501e6b426f89cd9ccb25f97209fd1b80;p=freertos Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2745 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S index 436895158..d6157c4d7 100644 --- a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S +++ b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S @@ -172,7 +172,7 @@ handle_asynchronous: li t4, -1 lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */ lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */ - sw t4, 0(t0) /* Low word no smaller than old value. */ + sw t4, 0(t0) /* Low word no smaller than old value to start with - will be overwritten below. */ sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */ sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */ lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */ @@ -223,11 +223,13 @@ test_if_environment_call: j processed_source is_exception: - ebreak + csrr t0, mcause /* For viewing in the debugger only. */ + csrr t1, mepc /* For viewing in the debugger only */ + csrr t2, mstatus j is_exception as_yet_unhandled: - ebreak + csrr t0, mcause /* For viewing in the debugger only. */ j as_yet_unhandled processed_source: @@ -298,6 +300,7 @@ xPortStartFirstTask: portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */ load_x t0, 29 * portWORD_SIZE( sp ) /* mstatus */ + addi t0, t0, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */ csrrw x0, mstatus, t0 /* Interrupts enabled from here! */ load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */ @@ -399,7 +402,7 @@ xPortStartFirstTask: pxPortInitialiseStack: csrr t0, mstatus /* Obtain current mstatus value. */ - addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ + addi t1, x0, 0x188 /* Generate the value 0x1888, which are the MIE, MPIE and privilege bits to set in mstatus. */ slli t1, t1, 4 or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */