From: Bin Meng <bmeng.cn@gmail.com>
Date: Wed, 17 Feb 2016 08:16:23 +0000 (-0800)
Subject: x86: fsp: Make sure HOB list is not overwritten by U-Boot
X-Git-Tag: v2016.03-rc3~78
X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=dc5be508b065ff305cef451ac1aed7465603db02;p=u-boot

x86: fsp: Make sure HOB list is not overwritten by U-Boot

Intel IvyBridge FSP seems to be buggy that it does not report memory
used by FSP itself as reserved in the resource descriptor HOB. The
FSP specification does not describe how resource descriptor HOBs are
generated by the FSP to describe what memory regions. It looks newer
FSPs like Queensbay and BayTrail do not have such issue. This causes
U-Boot relocation overwrites the important boot service data which is
used by FSP, and the subsequent call to fsp_notify() will fail.

To resolve this, we find out the lowest memory base address allocated
by FSP for the boot service data when walking through the HOB list in
fsp_get_usable_lowmem_top(). Check whether the memory top address is
below the FSP HOB list, and if not, use the lowest memory base address
allocated by FSP as the memory top address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested on link (ivybridge non-FSP)
Tested-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 49e173c820..a0bd344ed1 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -248,6 +248,16 @@ config FSP_USE_UPD
 	  are still some FSPs that might not even have UPD. For such FSPs,
 	  override this to n in their platform Kconfig files.
 
+config FSP_BROKEN_HOB
+	bool
+	depends on HAVE_FSP
+	help
+	  Indicate some buggy FSPs that does not report memory used by FSP
+	  itself as reserved in the resource descriptor HOB. Select this to
+	  tell U-Boot to do some additional work to ensure U-Boot relocation
+	  do not overwrite the important boot service data which is used by
+	  FSP, otherwise the subsequent call to fsp_notify() will fail.
+
 config ENABLE_MRC_CACHE
 	bool "Enable MRC cache"
 	depends on !EFI && !SYS_COREBOOT
diff --git a/arch/x86/lib/fsp/fsp_support.c b/arch/x86/lib/fsp/fsp_support.c
index 29fa06098d..b05dcede0c 100644
--- a/arch/x86/lib/fsp/fsp_support.c
+++ b/arch/x86/lib/fsp/fsp_support.c
@@ -225,6 +225,10 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
 	struct hob_res_desc *res_desc;
 	phys_addr_t phys_start;
 	u32 top;
+#ifdef CONFIG_FSP_BROKEN_HOB
+	struct hob_mem_alloc *res_mem;
+	phys_addr_t mem_base = 0;
+#endif
 
 	/* Get the HOB list for processing */
 	hdr = hob_list;
@@ -242,9 +246,38 @@ u32 fsp_get_usable_lowmem_top(const void *hob_list)
 					top += (u32)(res_desc->len);
 			}
 		}
+
+#ifdef CONFIG_FSP_BROKEN_HOB
+		/*
+		 * Find out the lowest memory base address allocated by FSP
+		 * for the boot service data
+		 */
+		if (hdr->type == HOB_TYPE_MEM_ALLOC) {
+			res_mem = (struct hob_mem_alloc *)hdr;
+			if (!mem_base)
+				mem_base = res_mem->mem_base;
+			if (res_mem->mem_base < mem_base)
+				mem_base = res_mem->mem_base;
+		}
+#endif
+
 		hdr = get_next_hob(hdr);
 	}
 
+#ifdef CONFIG_FSP_BROKEN_HOB
+	/*
+	 * Check whether the memory top address is below the FSP HOB list.
+	 * If not, use the lowest memory base address allocated by FSP as
+	 * the memory top address. This is to prevent U-Boot relocation
+	 * overwrites the important boot service data which is used by FSP,
+	 * otherwise the subsequent call to fsp_notify() will fail.
+	 */
+	if (top > (u32)hob_list) {
+		debug("Adjust memory top address due to a buggy FSP\n");
+		top = (u32)mem_base;
+	}
+#endif
+
 	return top;
 }