From: richardbarry Date: Sun, 16 Nov 2008 19:30:23 +0000 (+0000) Subject: Delete unused files. X-Git-Tag: V5.1.2~145 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=dcb5adc5003c17fcb0b7f4cbe33b5990625816b3;p=freertos Delete unused files. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@551 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52233_Ethernet.c b/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52233_Ethernet.c deleted file mode 100644 index d95690379..000000000 --- a/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52233_Ethernet.c +++ /dev/null @@ -1,888 +0,0 @@ -/* - * Copyright (c) 2001-2004 Swedish Institute of Computer Science. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT - * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, - * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT - * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING - * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY - * OF SUCH DAMAGE. - * - * This file is part of the lwIP TCP/IP stack. - * - * Author: Adam Dunkels - * - */ - -/* Standard library includes. */ -#include -#include - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" - -xTaskHandle xEthIntTask; - -/* lwIP includes. */ -#include "lwip/def.h" -#include "lwip/mem.h" -#include "lwip/pbuf.h" -#include "lwip/sys.h" -#include "lwip/stats.h" -#include "lwip/snmp.h" -#include "netif/etharp.h" - -/* Hardware includes. */ -#include "fec.h" - -/* Delay to wait for a DMA buffer to become available if one is not already -available. */ -#define netifBUFFER_WAIT_ATTEMPTS 10 -#define netifBUFFER_WAIT_DELAY (10 / portTICK_RATE_MS) - -/* Delay between polling the PHY to see if a link has been established. */ -#define netifLINK_DELAY ( 500 / portTICK_RATE_MS ) - -/* Delay between looking for incoming packets. In ideal world this would be -infinite. */ -#define netifBLOCK_TIME_WAITING_FOR_INPUT netifLINK_DELAY - -/* Name for the netif. */ -#define IFNAME0 'e' -#define IFNAME1 'n' - -/* Hardware specific. */ -#define netifFIRST_FEC_VECTOR 23 - -/*-----------------------------------------------------------*/ - -/* The DMA descriptors. This is a char array to allow us to align it correctly. */ -static unsigned portCHAR xFECTxDescriptors_unaligned[ ( configNUM_FEC_TX_BUFFERS * sizeof( FECBD ) ) + 16 ]; -static unsigned portCHAR xFECRxDescriptors_unaligned[ ( configNUM_FEC_RX_BUFFERS * sizeof( FECBD ) ) + 16 ]; -static FECBD *xFECTxDescriptors; -static FECBD *xFECRxDescriptors; - -/* The DMA buffers. These are char arrays to allow them to be alligned correctly. */ -static unsigned portCHAR ucFECTxBuffers[ ( configNUM_FEC_TX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ]; -static unsigned portCHAR ucFECRxBuffers[ ( configNUM_FEC_RX_BUFFERS * configFEC_BUFFER_SIZE ) + 16 ]; -static unsigned portBASE_TYPE uxNextRxBuffer = 0, uxNextTxBuffer = 0; - -/* Semaphore used by the FEC interrupt handler to wake the handler task. */ -static xSemaphoreHandle xFecSemaphore; - -#pragma options align= packed -struct ethernetif -{ - struct eth_addr *ethaddr; - /* Add whatever per-interface state that is needed here. */ -}; - -/*-----------------------------------------------------------*/ - -/* Standard lwIP netif handlers. */ -static void prvInitialiseFECBuffers( void ); -static void low_level_init( struct netif *netif ); -static err_t low_level_output(struct netif *netif, struct pbuf *p); -static struct pbuf *low_level_input(struct netif *netif); -static void ethernetif_input( void *pParams ); - -/* Functions adapted from Freescale provided code. */ -static int fec_mii_write( int phy_addr, int reg_addr, int data ); -static int fec_mii_read( int phy_addr, int reg_addr, uint16* data ); -static uint8 fec_hash_address( const uint8* addr ); -static void fec_set_address( const uint8 *pa ); -static void fec_irq_enable( void ); - -/*-----------------------------------------------------------*/ - -/********************************************************************/ -/* - * Write a value to a PHY's MII register. - * - * Parameters: - * ch FEC channel - * phy_addr Address of the PHY. - * reg_addr Address of the register in the PHY. - * data Data to be written to the PHY register. - * - * Return Values: - * 0 on failure - * 1 on success. - * - * Please refer to your PHY manual for registers and their meanings. - * mii_write() polls for the FEC's MII interrupt event and clears it. - * If after a suitable amount of time the event isn't triggered, a - * value of 0 is returned. - */ -static int fec_mii_write( int phy_addr, int reg_addr, int data ) -{ -int timeout; -uint32 eimr; - - /* Clear the MII interrupt bit */ - MCF_FEC_EIR = MCF_FEC_EIR_MII; - - /* Mask the MII interrupt */ - eimr = MCF_FEC_EIMR; - MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII; - - /* Write to the MII Management Frame Register to kick-off the MII write */ - MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_WRITE | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10 | MCF_FEC_MMFR_DATA( data ); - - /* Poll for the MII interrupt (interrupt should be masked) */ - for (timeout = 0; timeout < MII_TIMEOUT; timeout++) - { - if (MCF_FEC_EIR & MCF_FEC_EIR_MII) - { - break; - } - } - - if( timeout == MII_TIMEOUT ) - { - return 0; - } - - /* Clear the MII interrupt bit */ - MCF_FEC_EIR = MCF_FEC_EIR_MII; - - /* Restore the EIMR */ - MCF_FEC_EIMR = eimr; - - return 1; -} - -/********************************************************************/ -/* - * Read a value from a PHY's MII register. - * - * Parameters: - * ch FEC channel - * phy_addr Address of the PHY. - * reg_addr Address of the register in the PHY. - * data Pointer to storage for the Data to be read - * from the PHY register (passed by reference) - * - * Return Values: - * 0 on failure - * 1 on success. - * - * Please refer to your PHY manual for registers and their meanings. - * mii_read() polls for the FEC's MII interrupt event and clears it. - * If after a suitable amount of time the event isn't triggered, a - * value of 0 is returned. - */ -static int fec_mii_read( int phy_addr, int reg_addr, uint16* data ) -{ -int timeout; -uint32 eimr; - - /* Clear the MII interrupt bit */ - MCF_FEC_EIR = MCF_FEC_EIR_MII; - - /* Mask the MII interrupt */ - eimr = MCF_FEC_EIMR; - MCF_FEC_EIMR &= ~MCF_FEC_EIMR_MII; - - /* Write to the MII Management Frame Register to kick-off the MII read */ - MCF_FEC_MMFR = MCF_FEC_MMFR_ST_01 | MCF_FEC_MMFR_OP_READ | MCF_FEC_MMFR_PA(phy_addr) | MCF_FEC_MMFR_RA(reg_addr) | MCF_FEC_MMFR_TA_10; - - /* Poll for the MII interrupt (interrupt should be masked) */ - for (timeout = 0; timeout < MII_TIMEOUT; timeout++) - { - if (MCF_FEC_EIR & MCF_FEC_EIR_MII) - { - break; - } - } - - if(timeout == MII_TIMEOUT) - { - return 0; - } - - /* Clear the MII interrupt bit */ - MCF_FEC_EIR = MCF_FEC_EIR_MII; - - /* Restore the EIMR */ - MCF_FEC_EIMR = eimr; - - *data = (uint16)(MCF_FEC_MMFR & 0x0000FFFF); - - return 1; -} - - -/********************************************************************/ -/* - * Generate the hash table settings for the given address - * - * Parameters: - * addr 48-bit (6 byte) Address to generate the hash for - * - * Return Value: - * The 6 most significant bits of the 32-bit CRC result - */ -static uint8 fec_hash_address( const uint8* addr ) -{ -uint32 crc; -uint8 byte; -int i, j; - - crc = 0xFFFFFFFF; - for(i=0; i<6; ++i) - { - byte = addr[i]; - for(j=0; j<8; ++j) - { - if((byte & 0x01)^(crc & 0x01)) - { - crc >>= 1; - crc = crc ^ 0xEDB88320; - } - else - { - crc >>= 1; - } - - byte >>= 1; - } - } - - return (uint8)(crc >> 26); -} - -/********************************************************************/ -/* - * Set the Physical (Hardware) Address and the Individual Address - * Hash in the selected FEC - * - * Parameters: - * ch FEC channel - * pa Physical (Hardware) Address for the selected FEC - */ -static void fec_set_address( const uint8 *pa ) -{ - uint8 crc; - - /* - * Set the Physical Address - */ - MCF_FEC_PALR = (uint32)((pa[0]<<24) | (pa[1]<<16) | (pa[2]<<8) | pa[3]); - MCF_FEC_PAUR = (uint32)((pa[4]<<24) | (pa[5]<<16)); - - /* - * Calculate and set the hash for given Physical Address - * in the Individual Address Hash registers - */ - crc = fec_hash_address(pa); - if(crc >= 32) - { - MCF_FEC_IAUR |= (uint32)(1 << (crc - 32)); - } - else - { - MCF_FEC_IALR |= (uint32)(1 << crc); - } -} - - -/********************************************************************/ -/* - * Enable interrupts on the selected FEC - * - */ -static void fec_irq_enable( void ) -{ -int fec_vbase; - -#if INTC_LVL_FEC > configMAX_SYSCALL_INTERRUPT_PRIORITY - #error INTC_LVL_FEC must be less than or equal to configMAX_SYSCALL_INTERRUPT_PRIORITY -#endif - - fec_vbase = 64 + netifFIRST_FEC_VECTOR; - - /* Enable FEC interrupts to the ColdFire core - * Setup each ICR with a unique interrupt level combination */ - fec_vbase -= 64; - - /* FEC Rx Frame */ - MCF_INTC0_ICR(fec_vbase+4) = MCF_INTC_ICR_IL(INTC_LVL_FEC); - - /* FEC Rx Buffer */ - MCF_INTC0_ICR(fec_vbase+5) = MCF_INTC_ICR_IL(INTC_LVL_FEC); - - /* FEC FIFO Underrun */ - MCF_INTC0_ICR(fec_vbase+2) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* FEC Collision Retry Limit */ - MCF_INTC0_ICR(fec_vbase+3) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* FEC Late Collision */ - MCF_INTC0_ICR(fec_vbase+7) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* FEC Heartbeat Error */ - MCF_INTC0_ICR(fec_vbase+8) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* FEC Bus Error */ - MCF_INTC0_ICR(fec_vbase+10) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* FEC Babbling Transmit */ - MCF_INTC0_ICR(fec_vbase+11) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* FEC Babbling Receive */ - MCF_INTC0_ICR(fec_vbase+12) = MCF_INTC_ICR_IL(INTC_LVL_FEC+1); - - /* Enable the FEC interrupts in the mask register */ - MCF_INTC0_IMRH &= ~( MCF_INTC_IMRH_INT_MASK33 | MCF_INTC_IMRH_INT_MASK34 | MCF_INTC_IMRH_INT_MASK35 ); - MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK25 | MCF_INTC_IMRL_INT_MASK26 | MCF_INTC_IMRL_INT_MASK27 | MCF_INTC_IMRL_INT_MASK28 | MCF_INTC_IMRL_INT_MASK29 | MCF_INTC_IMRL_INT_MASK30 | MCF_INTC_IMRL_INT_MASK31 | MCF_INTC_IMRL_MASKALL ); - - /* Clear any pending FEC interrupt events */ - MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL; - - /* Unmask all FEC interrupts */ - MCF_FEC_EIMR = MCF_FEC_EIMR_UNMASK_ALL; -} - -/** - * In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -static void low_level_init( struct netif *netif ) -{ -unsigned portSHORT usData; -const unsigned portCHAR ucMACAddress[6] = -{ - configMAC_0, configMAC_1,configMAC_2,configMAC_3,configMAC_4,configMAC_5 -}; - - prvInitialiseFECBuffers(); - vSemaphoreCreateBinary( xFecSemaphore ); - - for( usData = 0; usData < 6; usData++ ) - { - netif->hwaddr[ usData ] = ucMACAddress[ usData ]; - } - - /* Set the Reset bit and clear the Enable bit */ - MCF_FEC_ECR = MCF_FEC_ECR_RESET; - - /* Wait at least 8 clock cycles */ - for( usData = 0; usData < 10; usData++ ) - { - asm( "NOP" ); - } - - /* Set MII speed to 2.5MHz. */ - MCF_FEC_MSCR = MCF_FEC_MSCR_MII_SPEED( ( ( configCPU_CLOCK_HZ / 1000000 ) / 5 ) + 1 ); - - /* - * Make sure the external interface signals are enabled - */ - MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_IRQ3_FEC_MDIO | MCF_GPIO_PNQPAR_IRQ5_FEC_MDC; - - - MCF_GPIO_PTIPAR = MCF_GPIO_PTIPAR_FEC_COL_FEC_COL - | MCF_GPIO_PTIPAR_FEC_CRS_FEC_CRS - | MCF_GPIO_PTIPAR_FEC_RXCLK_FEC_RXCLK - | MCF_GPIO_PTIPAR_FEC_RXD0_FEC_RXD0 - | MCF_GPIO_PTIPAR_FEC_RXD1_FEC_RXD1 - | MCF_GPIO_PTIPAR_FEC_RXD2_FEC_RXD2 - | MCF_GPIO_PTIPAR_FEC_RXD3_FEC_RXD3 - | MCF_GPIO_PTIPAR_FEC_RXDV_FEC_RXDV; - - MCF_GPIO_PTJPAR = MCF_GPIO_PTJPAR_FEC_RXER_FEC_RXER - | MCF_GPIO_PTJPAR_FEC_TXCLK_FEC_TXCLK - | MCF_GPIO_PTJPAR_FEC_TXD0_FEC_TXD0 - | MCF_GPIO_PTJPAR_FEC_TXD1_FEC_TXD1 - | MCF_GPIO_PTJPAR_FEC_TXD2_FEC_TXD2 - | MCF_GPIO_PTJPAR_FEC_TXD3_FEC_TXD3 - | MCF_GPIO_PTJPAR_FEC_TXEN_FEC_TXEN - | MCF_GPIO_PTJPAR_FEC_TXER_FEC_TXER; - - - /* Can we talk to the PHY? */ - do - { - vTaskDelay( netifLINK_DELAY ); - usData = 0; - fec_mii_read( configPHY_ADDRESS, PHY_PHYIDR1, &usData ); - - } while( ( usData == 0xffff ) || ( usData == 0 ) ); - - /* Start auto negotiate. */ - fec_mii_write( configPHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) ); - - /* Wait for auto negotiate to complete. */ - do - { - vTaskDelay( netifLINK_DELAY ); - fec_mii_read( configPHY_ADDRESS, PHY_BMSR, &usData ); - - } while( !( usData & PHY_BMSR_AN_COMPLETE ) ); - - /* When we get here we have a link - find out what has been negotiated. */ - fec_mii_read( configPHY_ADDRESS, PHY_ANLPAR, &usData ); - - if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_100BTX ) ) - { - /* Speed is 100. */ - } - else - { - /* Speed is 10. */ - } - - if( ( usData & PHY_ANLPAR_100BTX_FDX ) || ( usData & PHY_ANLPAR_10BTX_FDX ) ) - { - /* Full duplex. */ - MCF_FEC_RCR &= (uint32)~MCF_FEC_RCR_DRT; - MCF_FEC_TCR |= MCF_FEC_TCR_FDEN; - } - else - { - MCF_FEC_RCR |= MCF_FEC_RCR_DRT; - MCF_FEC_TCR &= (uint32)~MCF_FEC_TCR_FDEN; - } - - /* Clear the Individual and Group Address Hash registers */ - MCF_FEC_IALR = 0; - MCF_FEC_IAUR = 0; - MCF_FEC_GALR = 0; - MCF_FEC_GAUR = 0; - - /* Set the Physical Address for the selected FEC */ - fec_set_address( ucMACAddress ); - - /* Set Rx Buffer Size */ - MCF_FEC_EMRBR = (uint16)configFEC_BUFFER_SIZE; - - /* Point to the start of the circular Rx buffer descriptor queue */ - MCF_FEC_ERDSR = ( volatile unsigned portLONG ) &( xFECRxDescriptors[ 0 ] ); - - /* Point to the start of the circular Tx buffer descriptor queue */ - MCF_FEC_ETSDR = ( volatile unsigned portLONG ) &( xFECTxDescriptors[ 0 ] ); - - /* Mask all FEC interrupts */ - MCF_FEC_EIMR = MCF_FEC_EIMR_MASK_ALL; - - /* Clear all FEC interrupt events */ - MCF_FEC_EIR = MCF_FEC_EIR_CLEAR_ALL; - - /* Initialize the Receive Control Register */ - MCF_FEC_RCR = MCF_FEC_RCR_MAX_FL(ETH_MAX_FRM) | MCF_FEC_RCR_FCE; - - MCF_FEC_RCR |= MCF_FEC_RCR_MII_MODE; - - #if( configUSE_PROMISCUOUS_MODE == 1 ) - { - MCF_FEC_RCR |= MCF_FEC_RCR_PROM; - } - #endif - - /* Create the task that handles the EMAC. */ - xTaskCreate( ethernetif_input, ( signed portCHAR * ) "ETH_INT", configETHERNET_INPUT_TASK_STACK_SIZE, (void *)netif, configETHERNET_INPUT_TASK_PRIORITY, &xEthIntTask ); - - fec_irq_enable(); - MCF_FEC_ECR = MCF_FEC_ECR_ETHER_EN; - MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE; -} - -/** - * This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become availale since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ -static err_t low_level_output(struct netif *netif, struct pbuf *p) -{ -struct pbuf *q; -u32_t l = 0; -unsigned portCHAR *pcTxData = NULL; -portBASE_TYPE i; - - ( void ) netif; - - #if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ - #endif - - /* Get a DMA buffer into which we can write the data to send. */ - for( i = 0; i < netifBUFFER_WAIT_ATTEMPTS; i++ ) - { - if( xFECTxDescriptors[ uxNextTxBuffer ].status & TX_BD_R ) - { - /* Wait for the buffer to become available. */ - vTaskDelay( netifBUFFER_WAIT_DELAY ); - } - else - { - pcTxData = xFECTxDescriptors[ uxNextTxBuffer ].data; - break; - } - } - - if( pcTxData == NULL ) - { - /* For break point only. */ - portNOP(); - - return ERR_BUF; - } - else - { - for( q = p; q != NULL; q = q->next ) - { - /* Send the data from the pbuf to the interface, one pbuf at a - time. The size of the data in each pbuf is kept in the ->len - variable. */ - memcpy( &pcTxData[l], (u8_t*)q->payload, q->len ); - l += q->len; - } - } - - /* Setup the buffer descriptor for transmission */ - xFECTxDescriptors[ uxNextTxBuffer ].length = l;//nbuf->length + ETH_HDR_LEN; - xFECTxDescriptors[ uxNextTxBuffer ].status |= (TX_BD_R | TX_BD_L); - - /* Continue the Tx DMA task (in case it was waiting for a new TxBD) */ - MCF_FEC_TDAR = MCF_FEC_TDAR_X_DES_ACTIVE; - - uxNextTxBuffer++; - if( uxNextTxBuffer >= configNUM_FEC_TX_BUFFERS ) - { - uxNextTxBuffer = 0; - } - - #if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ - #endif - - LINK_STATS_INC(link.xmit); - - return ERR_OK; -} - -/** - * Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - * @param netif the lwip network interface structure for this ethernetif - * @return a pbuf filled with the received packet (including MAC header) - * NULL on memory error - */ -static struct pbuf *low_level_input(struct netif *netif) -{ -struct pbuf *p, *q; -u16_t len, l; - - ( void ) netif; - - l = 0; - p = NULL; - - /* Obtain the size of the packet and put it into the "len" variable. */ - len = xFECRxDescriptors[ uxNextRxBuffer ].length; - - if( ( len != 0 ) && ( ( xFECRxDescriptors[ uxNextRxBuffer ].status & RX_BD_E ) == 0 ) ) - { - #if ETH_PAD_SIZE - len += ETH_PAD_SIZE; /* allow room for Ethernet padding */ - #endif - - /* We allocate a pbuf chain of pbufs from the pool. */ - p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL); - - if (p != NULL) - { - - #if ETH_PAD_SIZE - pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */ - #endif - - /* We iterate over the pbuf chain until we have read the entire - * packet into the pbuf. */ - for(q = p; q != NULL; q = q->next) - { - /* Read enough bytes to fill this pbuf in the chain. The - * available data in the pbuf is given by the q->len - * variable. */ - memcpy((u8_t*)q->payload, &(xFECRxDescriptors[ uxNextRxBuffer ].data[l]), q->len); - l = l + q->len; - } - - - #if ETH_PAD_SIZE - pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ - #endif - - LINK_STATS_INC(link.recv); - - } - else - { - - LINK_STATS_INC(link.memerr); - LINK_STATS_INC(link.drop); - - } /* End else */ - - - /* Free the descriptor. */ - xFECRxDescriptors[ uxNextRxBuffer ].status |= RX_BD_E; - MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE; - - uxNextRxBuffer++; - if( uxNextRxBuffer >= configNUM_FEC_RX_BUFFERS ) - { - uxNextRxBuffer = 0; - } - - } /* End if */ - - return p; -} - -/** - * This function should be called when a packet is ready to be read - * from the interface. It uses the function low_level_input() that - * should handle the actual reception of bytes from the network - * interface.Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ - -static void ethernetif_input( void *pParams ) -{ -struct netif *netif; -struct ethernetif *ethernetif; -struct eth_hdr *ethhdr; -struct pbuf *p; - - netif = (struct netif*) pParams; - ethernetif = netif->state; - - for( ;; ) - { - do - { - - /* move received packet into a new pbuf */ - p = low_level_input( netif ); - - if( p == NULL ) - { - /* No packet could be read. Wait a for an interrupt to tell us - there is more data available. */ - xSemaphoreTake( xFecSemaphore, netifBLOCK_TIME_WAITING_FOR_INPUT ); - } - - } while( p == NULL ); - - /* points to packet payload, which starts with an Ethernet header */ - ethhdr = p->payload; - - switch (htons(ethhdr->type)) { - /* IP or ARP packet? */ - - case ETHTYPE_IP: - - pbuf_header( p, (s16_t)-sizeof(struct eth_hdr) ); - - /* full packet send to tcpip_thread to process */ - if (netif->input(p, netif) != ERR_OK) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - pbuf_free(p); - p = NULL; - } - break; - - case ETHTYPE_ARP: - - #if ETHARP_TRUST_IP_MAC - etharp_ip_input(netif, p); - #endif - - etharp_arp_input(netif, ethernetif->ethaddr, p); - break; - - default: - pbuf_free(p); - p = NULL; - break; - } - } -} - -/** - * Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t ethernetif_init(struct netif *netif) -{ - struct ethernetif *ethernetif; - - LWIP_ASSERT("netif != NULL", (netif != NULL)); - - ethernetif = mem_malloc(sizeof(struct ethernetif)); - - if (ethernetif == NULL) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n")); - return ERR_MEM; - } - - #if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; - #endif /* LWIP_NETIF_HOSTNAME */ - - /* - * Initialize the snmp variables and counters inside the struct netif. - * The last argument should be replaced with your link speed, in units - * of bits per second. - */ - NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, 100); - - netif->state = ethernetif; - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) - */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]); - - low_level_init(netif); - - return ERR_OK; -} -/*-----------------------------------------------------------*/ - -static void prvInitialiseFECBuffers( void ) -{ -unsigned portBASE_TYPE ux; -unsigned portCHAR *pcBufPointer; - - pcBufPointer = &( xFECTxDescriptors_unaligned[ 0 ] ); - while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 ) - { - pcBufPointer++; - } - - xFECTxDescriptors = ( FECBD * ) pcBufPointer; - - pcBufPointer = &( xFECRxDescriptors_unaligned[ 0 ] ); - while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 ) - { - pcBufPointer++; - } - - xFECRxDescriptors = ( FECBD * ) pcBufPointer; - - - /* Setup the buffers and descriptors. */ - pcBufPointer = &( ucFECTxBuffers[ 0 ] ); - while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 ) - { - pcBufPointer++; - } - - for( ux = 0; ux < configNUM_FEC_TX_BUFFERS; ux++ ) - { - xFECTxDescriptors[ ux ].status = TX_BD_TC; - xFECTxDescriptors[ ux ].data = pcBufPointer; - pcBufPointer += configFEC_BUFFER_SIZE; - xFECTxDescriptors[ ux ].length = 0; - } - - pcBufPointer = &( ucFECRxBuffers[ 0 ] ); - while( ( ( unsigned portLONG ) pcBufPointer & 0x0fUL ) != 0 ) - { - pcBufPointer++; - } - - for( ux = 0; ux < configNUM_FEC_RX_BUFFERS; ux++ ) - { - xFECRxDescriptors[ ux ].status = RX_BD_E; - xFECRxDescriptors[ ux ].length = configFEC_BUFFER_SIZE; - xFECRxDescriptors[ ux ].data = pcBufPointer; - pcBufPointer += configFEC_BUFFER_SIZE; - } - - /* Set the wrap bit in the last descriptors to form a ring. */ - xFECTxDescriptors[ configNUM_FEC_TX_BUFFERS - 1 ].status |= TX_BD_W; - xFECRxDescriptors[ configNUM_FEC_RX_BUFFERS - 1 ].status |= RX_BD_W; - - uxNextRxBuffer = 0; - uxNextTxBuffer = 0; -} -/*-----------------------------------------------------------*/ - -__declspec(interrupt:0) void vFECISRHandler( void ) -{ -unsigned portLONG ulEvent; -portBASE_TYPE xHighPriorityTaskWoken = pdFALSE; - - ulEvent = MCF_FEC_EIR & MCF_FEC_EIMR; - MCF_FEC_EIR = ulEvent; - - if( ( ulEvent & MCF_FEC_EIR_RXB ) || ( ulEvent & MCF_FEC_EIR_RXF ) ) - { - /* A packet has been received. Wake the handler task. */ - xSemaphoreGiveFromISR( xFecSemaphore, &xHighPriorityTaskWoken ); - } - - if (ulEvent & ( MCF_FEC_EIR_UN | MCF_FEC_EIR_RL | MCF_FEC_EIR_LC | MCF_FEC_EIR_EBERR | MCF_FEC_EIR_BABT | MCF_FEC_EIR_BABR | MCF_FEC_EIR_HBERR ) ) - { - /* Sledge hammer error handling. */ - prvInitialiseFECBuffers(); - MCF_FEC_RDAR = MCF_FEC_RDAR_R_DES_ACTIVE; - } - - portEND_SWITCHING_ISR( xHighPriorityTaskWoken ); -} diff --git a/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/serial/serial.c b/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/serial/serial.c deleted file mode 100644 index 13c757504..000000000 --- a/Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/serial/serial.c +++ /dev/null @@ -1,230 +0,0 @@ -/* - FreeRTOS.org V5.1.0 - Copyright (C) 2003-2008 Richard Barry. - - This file is part of the FreeRTOS.org distribution. - - FreeRTOS.org is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - FreeRTOS.org is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with FreeRTOS.org; if not, write to the Free Software - Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes FreeRTOS.org, without being obliged to provide - the source code for any proprietary components. See the licensing section - of http://www.FreeRTOS.org for full details of how and when the exception - can be applied. - - *************************************************************************** - *************************************************************************** - * * - * SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, * - * and even write all or part of your application on your behalf. * - * See http://www.OpenRTOS.com for details of the services we provide to * - * expedite your project. * - * * - *************************************************************************** - *************************************************************************** - - Please ensure to read the configuration and relevant port sections of the - online documentation. - - http://www.FreeRTOS.org - Documentation, latest information, license and - contact details. - - http://www.SafeRTOS.com - A version that is certified for use in safety - critical systems. - - http://www.OpenRTOS.com - Commercial support, development, porting, - licensing and training services. -*/ - - -/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER. - -NOTE: This driver is primarily to test the scheduler functionality. It does -not effectively use the buffers or DMA and is therefore not intended to be -an example of an efficient driver. */ - -/* Standard include file. */ -#include - -/* Scheduler include files. */ -#include "FreeRTOS.h" -#include "queue.h" -#include "task.h" - -/* Demo app include files. */ -#include "serial.h" - -/* Hardware definitions. */ -#define serNO_PARITY ( ( unsigned portCHAR ) 0x02 << 3 ) -#define ser8DATA_BITS ( ( unsigned portCHAR ) 0x03 ) -#define ser1STOP_BIT ( ( unsigned portCHAR ) 0x07 ) -#define serSYSTEM_CLOCK ( ( unsigned portCHAR ) 0xdd ) -#define serTX_OUTPUT ( ( unsigned portCHAR ) 0x04 ) -#define serRX_INPUT ( ( unsigned portCHAR ) 0x08 ) -#define serTX_ENABLE ( ( unsigned portCHAR ) 0x04 ) -#define serRX_ENABLE ( ( unsigned portCHAR ) 0x01 ) -#define serTX_INT ( ( unsigned portCHAR ) 0x01 ) -#define serRX_INT ( ( unsigned portCHAR ) 0x02 ) - - -/* The queues used to communicate between tasks and ISR's. */ -static xQueueHandle xRxedChars; -static xQueueHandle xCharsForTx; - -/* Flag used to indicate the tx status. */ -static portBASE_TYPE xTxHasEnded = pdTRUE; - -/*-----------------------------------------------------------*/ - -/* The UART interrupt handler. */ -void __attribute__( ( interrupt ) ) __cs3_isr_interrupt_78( void ); - -/*-----------------------------------------------------------*/ - -xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength ) -{ -const unsigned portLONG ulBaudRateDivisor = ( configCPU_CLOCK_HZ / ( 32UL * ulWantedBaud ) ); - - /* Create the queues used by the com test task. */ - xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) ); - - xTxHasEnded = pdTRUE; - - /* Set the pins to UART mode. */ -//_RB_ MCF_PAD_PUASAR |= ( serTX_OUTPUT | serRX_INPUT ); - - /* Reset the peripheral. */ - MCF_UART1_UCR = MCF_UART_UCR_RESET_RX; - MCF_UART1_UCR = MCF_UART_UCR_RESET_TX; - MCF_UART1_UCR = MCF_UART_UCR_RESET_ERROR; - MCF_UART1_UCR = MCF_UART_UCR_RESET_BKCHGINT; - MCF_UART1_UCR = MCF_UART_UCR_RESET_MR | MCF_UART_UCR_RX_DISABLED | MCF_UART_UCR_TX_DISABLED; - - /* Configure the UART. */ - MCF_UART1_UMR1 = serNO_PARITY | ser8DATA_BITS; - MCF_UART1_UMR2 = ser1STOP_BIT; - MCF_UART1_UCSR = serSYSTEM_CLOCK; - - MCF_UART1_UBG1 = ( unsigned portCHAR ) ( ( ulBaudRateDivisor >> 8UL ) & 0xffUL ); - MCF_UART1_UBG2 = ( unsigned portCHAR ) ( ulBaudRateDivisor & 0xffUL ); - - /* Turn it on. */ - MCF_UART1_UCR = serTX_ENABLE | serRX_ENABLE; - - /* Configure the interrupt controller. Run the UARTs above the kernel - interrupt priority for demo purposes. */ - MCF_INTC0_ICR14 = ( ( configMAX_SYSCALL_INTERRUPT_PRIORITY - 2 ) << 3 ); - MCF_INTC0_IMRL &= ~( MCF_INTC_IMRL_INT_MASK14 | 0x01 ); - - /* The Tx interrupt is not enabled until there is data to send. */ - MCF_UART1_UIMR = serRX_INT; - - /* Only a single port is implemented so we don't need to return anything. */ - return NULL; -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Get the next character from the buffer. Return false if no characters - are available or arrive before xBlockTime expires. */ - if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) ) - { - return pdTRUE; - } - else - { - return pdFALSE; - } -} -/*-----------------------------------------------------------*/ - -signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime ) -{ - /* Only one port is supported. */ - ( void ) pxPort; - - /* Return false if after the block time there is no room on the Tx queue. */ - if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS ) - { - return pdFAIL; - } - - /* A critical section should not be required as xTxHasEnded will not be - written to by the ISR if it is already 0 (is this correct?). */ - if( xTxHasEnded != pdFALSE ) - { - xTxHasEnded = pdFALSE; - MCF_UART1_UIMR = serRX_INT | serTX_INT; - } - - return pdPASS; -} -/*-----------------------------------------------------------*/ - -void vSerialClose( xComPortHandle xPort ) -{ - ( void ) xPort; -} -/*-----------------------------------------------------------*/ - -void __cs3_isr_interrupt_78( void ) -{ -unsigned portCHAR ucChar; -portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE, xDoneSomething = pdTRUE; - - while( xDoneSomething != pdFALSE ) - { - xDoneSomething = pdFALSE; - - /* Does the tx buffer contain space? */ - if( ( MCF_UART1_USR & MCF_UART_USR_TXRDY ) != 0x00 ) - { - /* Are there any characters queued to be sent? */ - if( xQueueReceiveFromISR( xCharsForTx, &ucChar, &xHigherPriorityTaskWoken ) == pdTRUE ) - { - /* Send the next char. */ - MCF_UART1_UTB = ucChar; - xDoneSomething = pdTRUE; - } - else - { - /* Turn off the Tx interrupt until such time as another character - is being transmitted. */ - MCF_UART1_UIMR = serRX_INT; - xTxHasEnded = pdTRUE; - } - } - - if( MCF_UART1_USR & MCF_UART_USR_RXRDY ) - { - ucChar = MCF_UART1_URB; - xQueueSendFromISR( xRxedChars, &ucChar, &xHigherPriorityTaskWoken ); - xDoneSomething = pdTRUE; - } - } - - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); -} - - - - - - -