From: Christophe Leroy Date: Thu, 6 Jul 2017 08:33:27 +0000 (+0200) Subject: powerpc, 8xx: move Serial driver to drivers/serial/ X-Git-Tag: v2017.07~7 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=dd7ff4721aaf46533a42ebd017aecd70cafa98e3;p=u-boot powerpc, 8xx: move Serial driver to drivers/serial/ At the same time, move to Kconfig Signed-off-by: Christophe Leroy --- diff --git a/README b/README index 504b120bc0..ee35dec5b5 100644 --- a/README +++ b/README @@ -687,29 +687,10 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver -- Console Interface: - Depending on board, define exactly one serial port - (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2), - or switch off the serial console by defining - CONFIG_8xx_CONS_NONE - - Note: if CONFIG_8xx_CONS_NONE is defined, the serial - port routines must be defined elsewhere - (i.e. serial_init(), serial_getc(), ...) - - Console Baudrate: CONFIG_BAUDRATE - in bps Select one of the baudrates listed in CONFIG_SYS_BAUDRATE_TABLE, see below. - CONFIG_SYS_BRGCLK_PRESCALE, baudrate prescale - -- Console Rx buffer length - With CONFIG_SYS_SMC_RXBUFLEN it is possible to define - the maximum receive buffer length for the SMC. - This option is actual only for 8xx possible. - If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE - must be defined, to setup the maximum idle timeout for - the SMC. - Autoboot Command: CONFIG_BOOTCOMMAND diff --git a/arch/powerpc/cpu/mpc8xx/Makefile b/arch/powerpc/cpu/mpc8xx/Makefile index 173cf01869..b40bffb047 100644 --- a/arch/powerpc/cpu/mpc8xx/Makefile +++ b/arch/powerpc/cpu/mpc8xx/Makefile @@ -13,5 +13,4 @@ obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_CMD_IMMAP) += immap.o obj-y += interrupts.o obj-$(CONFIG_CMD_REGINFO) += reginfo.o -obj-y += serial.o obj-y += speed.o diff --git a/arch/powerpc/cpu/mpc8xx/serial.c b/arch/powerpc/cpu/mpc8xx/serial.c deleted file mode 100644 index 114dfe9b4b..0000000000 --- a/arch/powerpc/cpu/mpc8xx/serial.c +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */ - -#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ -#define SMC_INDEX 0 -#define PROFF_SMC PROFF_SMC1 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 -#define IOPINS 0xc0 - -#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ -#define SMC_INDEX 1 -#define PROFF_SMC PROFF_SMC2 -#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 -#define IOPINS 0xc00 - -#endif /* CONFIG_8xx_CONS_SMCx */ - -#if !defined(CONFIG_SYS_SMC_RXBUFLEN) -#define CONFIG_SYS_SMC_RXBUFLEN 1 -#define CONFIG_SYS_MAXIDLE 0 -#else -#if !defined(CONFIG_SYS_MAXIDLE) -#error "you must define CONFIG_SYS_MAXIDLE" -#endif -#endif - -struct serialbuffer { - cbd_t rxbd; /* Rx BD */ - cbd_t txbd; /* Tx BD */ - uint rxindex; /* index for next character to read */ - uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ - uchar txbuf; /* tx buffers */ -}; - -static void serial_setdivisor(cpm8xx_t __iomem *cp) -{ - int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate; - - if (divisor / 16 > 0x1000) { - /* bad divisor, assume 50MHz clock and 9600 baud */ - divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600; - } - -#ifdef CONFIG_SYS_BRGCLK_PRESCALE - divisor /= CONFIG_SYS_BRGCLK_PRESCALE; -#endif - - if (divisor <= 0x1000) - out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN); - else - out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN | - CPM_BRG_DIV16); -} - -/* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. - */ - -static void smc_setbrg(void) -{ - immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cp = &(im->im_cpm); - - /* Set up the baud rate generator. - * See 8xx_io/commproc.c for details. - * - * Wire BRG1 to SMCx - */ - - out_be32(&cp->cp_simode, 0); - - serial_setdivisor(cp); -} - -static int smc_init(void) -{ - immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; - smc_t __iomem *sp; - smc_uart_t __iomem *up; - cpm8xx_t __iomem *cp = &(im->im_cpm); - struct serialbuffer __iomem *rtx; - - /* initialize pointers to SMC */ - - sp = cp->cp_smc + SMC_INDEX; - up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC]; - /* Disable relocation */ - out_be16(&up->smc_rpbase, 0); - - /* Disable transmitter/receiver. */ - clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. */ - out_be32(&im->im_siu_conf.sc_sdcr, 1); - - /* clear error conditions */ -#ifdef CONFIG_SYS_SDSR - out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR); -#else - out_8(&im->im_sdma.sdma_sdsr, 0x83); -#endif - - /* clear SDMA interrupt mask */ -#ifdef CONFIG_SYS_SDMR - out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR); -#else - out_8(&im->im_sdma.sdma_sdmr, 0x00); -#endif - - /* Use Port B for SMCx instead of other functions. */ - setbits_be32(&cp->cp_pbpar, IOPINS); - clrbits_be32(&cp->cp_pbdir, IOPINS); - clrbits_be16(&cp->cp_pbodr, IOPINS); - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE]; - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf); - out_be16(&rtx->rxbd.cbd_sc, 0); - - out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf); - out_be16(&rtx->txbd.cbd_sc, 0); - - /* Set up the uart parameters in the parameter ram. */ - out_be16(&up->smc_rbase, CPM_SERIAL_BASE); - out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t)); - out_8(&up->smc_rfcr, SMC_EB); - out_8(&up->smc_tfcr, SMC_EB); - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - */ - out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); - - /* Mask all interrupts and remove anything pending. - */ - out_8(&sp->smc_smcm, 0); - out_8(&sp->smc_smce, 0xff); - - /* Set up the baud rate generator */ - smc_setbrg(); - - /* Make the first buffer the only buffer. */ - setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP); - setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); - - /* single/multi character receive. */ - out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN); - out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE); - out_be32(&rtx->rxindex, 0); - - /* Initialize Tx/Rx parameters. */ - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */ - ; - - out_be16(&cp->cp_cpcr, - mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG); - - while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. */ - setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); - - return 0; -} - -static void smc_putc(const char c) -{ - immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cpmp = &(im->im_cpm); - struct serialbuffer __iomem *rtx; - - if (c == '\n') - smc_putc('\r'); - - rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; - - /* Wait for last character to go. */ - out_8(&rtx->txbuf, c); - out_be16(&rtx->txbd.cbd_datlen, 1); - setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY); - - while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY) - WATCHDOG_RESET(); -} - -static void smc_puts(const char *s) -{ - while (*s) - smc_putc(*s++); -} - -static int smc_getc(void) -{ - immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cpmp = &(im->im_cpm); - struct serialbuffer __iomem *rtx; - unsigned char c; - uint rxindex; - - rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; - - /* Wait for character to show up. */ - while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY) - WATCHDOG_RESET(); - - /* the characters are read one by one, - * use the rxindex to know the next char to deliver - */ - rxindex = in_be32(&rtx->rxindex); - c = in_8(rtx->rxbuf + rxindex); - rxindex++; - - /* check if all char are readout, then make prepare for next receive */ - if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) { - rxindex = 0; - setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY); - } - out_be32(&rtx->rxindex, rxindex); - return c; -} - -static int smc_tstc(void) -{ - immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; - cpm8xx_t __iomem *cpmp = &(im->im_cpm); - struct serialbuffer __iomem *rtx; - - rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; - - return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY); -} - -struct serial_device serial_smc_device = { - .name = "serial_smc", - .start = smc_init, - .stop = NULL, - .setbrg = smc_setbrg, - .getc = smc_getc, - .tstc = smc_tstc, - .putc = smc_putc, - .puts = smc_puts, -}; - -__weak struct serial_device *default_serial_console(void) -{ - return &serial_smc_device; -} - -void mpc8xx_serial_initialize(void) -{ - serial_register(&serial_smc_device); -} - -#endif /* CONFIG_8xx_CONS_NONE */ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c64f4a6d7b..b7dd2ac103 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -491,4 +491,57 @@ config STI_ASC_SERIAL on STiH410 SoC. This is a basic implementation, it supports following baudrate 9600, 19200, 38400, 57600 and 115200. +config MPC8XX_CONS + bool "Console driver for MPC8XX" + depends on 8xx + default y + +choice + prompt "Console port" + default 8xx_CONS_SMC1 + depends on MPC8XX_CONS + help + Depending on board, select one serial port + (CONFIG_8xx_CONS_SMC1 or CONFIG_8xx_CONS_SMC2) + +config 8xx_CONS_SMC1 + bool "SMC1" + +config 8xx_CONS_SMC2 + bool "SMC2" + +endchoice + +config SYS_SMC_RXBUFLEN + int "Console Rx buffer length" + depends on MPC8XX_CONS + default 1 + help + With CONFIG_SYS_SMC_RXBUFLEN it is possible to define + the maximum receive buffer length for the SMC. + This option is actual only for 8xx possible. + If using CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE + must be defined, to setup the maximum idle timeout for + the SMC. + +config SYS_MAXIDLE + int "maximum idle timeout" + depends on MPC8XX_CONS + default 0 + +config SYS_BRGCLK_PRESCALE + int "BRG Clock Prescale" + depends on MPC8XX_CONS + default 1 + +config SYS_SDSR + hex "SDSR Value" + depends on MPC8XX_CONS + default 0x83 + +config SYS_SDMR + hex "SDMR Value" + depends on MPC8XX_CONS + default 0 + endmenu diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index dca31b295c..72a6996a0a 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -48,6 +48,7 @@ obj-$(CONFIG_STM32X7_SERIAL) += serial_stm32x7.o obj-$(CONFIG_BCM283X_MU_SERIAL) += serial_bcm283x_mu.o obj-$(CONFIG_MSM_SERIAL) += serial_msm.o obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o +obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o ifndef CONFIG_SPL_BUILD obj-$(CONFIG_USB_TTY) += usbtty.o diff --git a/drivers/serial/serial_mpc8xx.c b/drivers/serial/serial_mpc8xx.c new file mode 100644 index 0000000000..26a8085a69 --- /dev/null +++ b/drivers/serial/serial_mpc8xx.c @@ -0,0 +1,256 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */ +#define SMC_INDEX 0 +#define PROFF_SMC PROFF_SMC1 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC1 +#define IOPINS 0xc0 + +#elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */ +#define SMC_INDEX 1 +#define PROFF_SMC PROFF_SMC2 +#define CPM_CR_CH_SMC CPM_CR_CH_SMC2 +#define IOPINS 0xc00 + +#endif /* CONFIG_8xx_CONS_SMCx */ + +struct serialbuffer { + cbd_t rxbd; /* Rx BD */ + cbd_t txbd; /* Tx BD */ + uint rxindex; /* index for next character to read */ + uchar rxbuf[CONFIG_SYS_SMC_RXBUFLEN];/* rx buffers */ + uchar txbuf; /* tx buffers */ +}; + +static void serial_setdivisor(cpm8xx_t __iomem *cp) +{ + int divisor = (gd->cpu_clk + 8 * gd->baudrate) / 16 / gd->baudrate; + + if (divisor / 16 > 0x1000) { + /* bad divisor, assume 50MHz clock and 9600 baud */ + divisor = (50 * 1000 * 1000 + 8 * 9600) / 16 / 9600; + } + + divisor /= CONFIG_SYS_BRGCLK_PRESCALE; + + if (divisor <= 0x1000) + out_be32(&cp->cp_brgc1, ((divisor - 1) << 1) | CPM_BRG_EN); + else + out_be32(&cp->cp_brgc1, ((divisor / 16 - 1) << 1) | CPM_BRG_EN | + CPM_BRG_DIV16); +} + +/* + * Minimal serial functions needed to use one of the SMC ports + * as serial console interface. + */ + +static void smc_setbrg(void) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + cpm8xx_t __iomem *cp = &(im->im_cpm); + + /* Set up the baud rate generator. + * See 8xx_io/commproc.c for details. + * + * Wire BRG1 to SMCx + */ + + out_be32(&cp->cp_simode, 0); + + serial_setdivisor(cp); +} + +static int smc_init(void) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + smc_t __iomem *sp; + smc_uart_t __iomem *up; + cpm8xx_t __iomem *cp = &(im->im_cpm); + struct serialbuffer __iomem *rtx; + + /* initialize pointers to SMC */ + + sp = cp->cp_smc + SMC_INDEX; + up = (smc_uart_t __iomem *)&cp->cp_dparam[PROFF_SMC]; + /* Disable relocation */ + out_be16(&up->smc_rpbase, 0); + + /* Disable transmitter/receiver. */ + clrbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); + + /* Enable SDMA. */ + out_be32(&im->im_siu_conf.sc_sdcr, 1); + + /* clear error conditions */ + out_8(&im->im_sdma.sdma_sdsr, CONFIG_SYS_SDSR); + + /* clear SDMA interrupt mask */ + out_8(&im->im_sdma.sdma_sdmr, CONFIG_SYS_SDMR); + + /* Use Port B for SMCx instead of other functions. */ + setbits_be32(&cp->cp_pbpar, IOPINS); + clrbits_be32(&cp->cp_pbdir, IOPINS); + clrbits_be16(&cp->cp_pbodr, IOPINS); + + /* Set the physical address of the host memory buffers in + * the buffer descriptors. + */ + rtx = (struct serialbuffer __iomem *)&cp->cp_dpmem[CPM_SERIAL_BASE]; + /* Allocate space for two buffer descriptors in the DP ram. + * For now, this address seems OK, but it may have to + * change with newer versions of the firmware. + * damm: allocating space after the two buffers for rx/tx data + */ + + out_be32(&rtx->rxbd.cbd_bufaddr, (__force uint)&rtx->rxbuf); + out_be16(&rtx->rxbd.cbd_sc, 0); + + out_be32(&rtx->txbd.cbd_bufaddr, (__force uint)&rtx->txbuf); + out_be16(&rtx->txbd.cbd_sc, 0); + + /* Set up the uart parameters in the parameter ram. */ + out_be16(&up->smc_rbase, CPM_SERIAL_BASE); + out_be16(&up->smc_tbase, CPM_SERIAL_BASE + sizeof(cbd_t)); + out_8(&up->smc_rfcr, SMC_EB); + out_8(&up->smc_tfcr, SMC_EB); + + /* Set UART mode, 8 bit, no parity, one stop. + * Enable receive and transmit. + */ + out_be16(&sp->smc_smcmr, smcr_mk_clen(9) | SMCMR_SM_UART); + + /* Mask all interrupts and remove anything pending. + */ + out_8(&sp->smc_smcm, 0); + out_8(&sp->smc_smce, 0xff); + + /* Set up the baud rate generator */ + smc_setbrg(); + + /* Make the first buffer the only buffer. */ + setbits_be16(&rtx->txbd.cbd_sc, BD_SC_WRAP); + setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY | BD_SC_WRAP); + + /* single/multi character receive. */ + out_be16(&up->smc_mrblr, CONFIG_SYS_SMC_RXBUFLEN); + out_be16(&up->smc_maxidl, CONFIG_SYS_MAXIDLE); + out_be32(&rtx->rxindex, 0); + + /* Initialize Tx/Rx parameters. */ + while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */ + ; + + out_be16(&cp->cp_cpcr, + mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG); + + while (in_be16(&cp->cp_cpcr) & CPM_CR_FLG) /* wait if cp is busy */ + ; + + /* Enable transmitter/receiver. */ + setbits_be16(&sp->smc_smcmr, SMCMR_REN | SMCMR_TEN); + + return 0; +} + +static void smc_putc(const char c) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + cpm8xx_t __iomem *cpmp = &(im->im_cpm); + struct serialbuffer __iomem *rtx; + + if (c == '\n') + smc_putc('\r'); + + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; + + /* Wait for last character to go. */ + out_8(&rtx->txbuf, c); + out_be16(&rtx->txbd.cbd_datlen, 1); + setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY); + + while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY) + WATCHDOG_RESET(); +} + +static void smc_puts(const char *s) +{ + while (*s) + smc_putc(*s++); +} + +static int smc_getc(void) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + cpm8xx_t __iomem *cpmp = &(im->im_cpm); + struct serialbuffer __iomem *rtx; + unsigned char c; + uint rxindex; + + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; + + /* Wait for character to show up. */ + while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY) + WATCHDOG_RESET(); + + /* the characters are read one by one, + * use the rxindex to know the next char to deliver + */ + rxindex = in_be32(&rtx->rxindex); + c = in_8(rtx->rxbuf + rxindex); + rxindex++; + + /* check if all char are readout, then make prepare for next receive */ + if (rxindex >= in_be16(&rtx->rxbd.cbd_datlen)) { + rxindex = 0; + setbits_be16(&rtx->rxbd.cbd_sc, BD_SC_EMPTY); + } + out_be32(&rtx->rxindex, rxindex); + return c; +} + +static int smc_tstc(void) +{ + immap_t __iomem *im = (immap_t __iomem *)CONFIG_SYS_IMMR; + cpm8xx_t __iomem *cpmp = &(im->im_cpm); + struct serialbuffer __iomem *rtx; + + rtx = (struct serialbuffer __iomem *)&cpmp->cp_dpmem[CPM_SERIAL_BASE]; + + return !(in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY); +} + +struct serial_device serial_smc_device = { + .name = "serial_smc", + .start = smc_init, + .stop = NULL, + .setbrg = smc_setbrg, + .getc = smc_getc, + .tstc = smc_tstc, + .putc = smc_putc, + .puts = smc_puts, +}; + +__weak struct serial_device *default_serial_console(void) +{ + return &serial_smc_device; +} + +void mpc8xx_serial_initialize(void) +{ + serial_register(&serial_smc_device); +} diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index a84dad1b5e..54eee53572 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -12,9 +12,6 @@ CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES CONFIG_83XX_PCICLK CONFIG_83XX_PCI_STREAMING CONFIG_88F5182 -CONFIG_8xx_CONS_NONE -CONFIG_8xx_CONS_SMC1 -CONFIG_8xx_CONS_SMC2 CONFIG_A003399_NOR_WORKAROUND CONFIG_A008044_WORKAROUND CONFIG_ACX517AKN @@ -2506,7 +2503,6 @@ CONFIG_SYS_BR6_64M CONFIG_SYS_BR6_8M CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR7_PRELIM -CONFIG_SYS_BRGCLK_PRESCALE CONFIG_SYS_BUSCLK CONFIG_SYS_CACHELINE_SHIFT CONFIG_SYS_CACHE_ACR0 @@ -4645,7 +4641,6 @@ CONFIG_SYS_SDIO_BASE0 CONFIG_SYS_SDIO_BASE1 CONFIG_SYS_SDIO_BASE2 CONFIG_SYS_SDIO_BASE3 -CONFIG_SYS_SDMR CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE @@ -4691,7 +4686,6 @@ CONFIG_SYS_SDRC_MR_VAL5 CONFIG_SYS_SDRC_TR_VAL CONFIG_SYS_SDRC_TR_VAL1 CONFIG_SYS_SDRC_TR_VAL2 -CONFIG_SYS_SDSR CONFIG_SYS_SD_VOLTAGE CONFIG_SYS_SEC_MON_ADDR CONFIG_SYS_SEC_MON_OFFSET @@ -4724,7 +4718,6 @@ CONFIG_SYS_SMC0_MODE0_VAL CONFIG_SYS_SMC0_PULSE0_VAL CONFIG_SYS_SMC0_SETUP0_VAL CONFIG_SYS_SMC_CSR0_VAL -CONFIG_SYS_SMC_RXBUFLEN CONFIG_SYS_SMI_BASE CONFIG_SYS_SPANSION_BASE CONFIG_SYS_SPANSION_BOOT