From: rtel Date: Tue, 16 Jun 2015 12:38:35 +0000 (+0000) Subject: Add SAMV7 (Cortex-M7) demo for Atmel Studio. X-Git-Tag: V8.2.2~15 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=de1d6468dc7040aacca32caf6fb5e051ba686296;p=freertos Add SAMV7 (Cortex-M7) demo for Atmel Studio. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2352 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..b2d55da41 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Blinky_Demo/main_blinky.c @@ -0,0 +1,236 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, toggles an LED. The 'block + * time' parameter passed to the queue receive function specifies that the + * task should be held in the Blocked state indefinitely to wait for data to + * be available on the queue. The queue receive task will only leave the + * Blocked state when the queue send task writes to the queue. As the queue + * send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore toggles + * the LED every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Library includes. */ +#include "board.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_PERIOD_MS ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/* The LED toggled by the Rx task. */ +#define mainTASK_LED ( 0 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in + * main.c. + */ +void main_blinky( void ); + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const unsigned long ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +unsigned long ulReceivedValue; +const unsigned long ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but + is it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + LED_Toggle( mainTASK_LED ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h new file mode 100644 index 000000000..485682531 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/FreeRTOSConfig.h @@ -0,0 +1,187 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* For definition of BOARD_MCK. */ +#ifndef __IAR_SYSTEMS_ASM__ + /* Prevent chip.h being included when this file is included from the IAR + port layer assembly file. */ + #include "board.h" +#endif + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 1 +#define configCPU_CLOCK_HZ ( BOARD_MCK << 1UL ) +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) +#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 46 * 1024 ) ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 + +/* The full demo always has tasks to run so the tick will never be turned off. +The blinky demo will use the default tickless idle implementation to turn the +tick off. */ +#define configUSE_TICKLESS_IDLE 0 + +/* Run time stats gathering definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 1 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTimerPendFunctionCall 1 + +/* Cortex-M specific definitions. */ +#ifdef __NVIC_PRIO_BITS + /* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */ + #define configPRIO_BITS __NVIC_PRIO_BITS +#else + #define configPRIO_BITS 3 /* 7 priority levels */ +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" +function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0x07 + +/* The highest interrupt priority that can be used by any interrupt service +routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL +INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER +PRIORITY THAN THIS! (higher priorities are lower numeric values. */ +#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 4 + +/* Interrupt priorities used by the kernel port layer itself. These are generic +to all Cortex-M ports, and do not rely on any particular library functions. */ +#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) +/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!! +See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */ +#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) ) + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); } + +/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS +standard names. */ +#define xPortPendSVHandler PendSV_Handler +#define vPortSVCHandler SVC_Handler +#define xPortSysTickHandler SysTick_Handler + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..92d02d91f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.c @@ -0,0 +1,204 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file initialises three timers as follows: + * + * TC0 channels 0 and 1 provide the interrupts that are used with the IntQ + * standard demo tasks, which test interrupt nesting and using queues from + * interrupts. As the interrupt is shared the nesting achieved is not as deep + * as normal when this test is executed, but still worth while. + * + * TC2 channel 0 provides a much higher frequency timer that tests the nesting + * of interrupts that don't use the FreeRTOS API. For convenience, the high + * frequency timer also keeps a count of the number of time it executes, and the + * count is used as the time base for the run time stats (which can be viewed + * through the CLI). + * + * All the timers can nest with the tick interrupt - creating a maximum + * interrupt nesting depth of 3 (normally 4, if the first two timers used + * separate interrupts). + * + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Library includes. */ +#include "board.h" + +/* The frequencies at which the first two timers expire are slightly offset to +ensure they don't remain synchronised. The frequency of the highest priority +interrupt is 20 times faster so really hammers the interrupt entry and exit +code. */ +#define tmrTIMER_0_FREQUENCY ( 2000UL ) +#define tmrTIMER_1_FREQUENCY ( 2003UL ) +#define tmrTIMER_2_FREQUENCY ( 20000UL ) + +/* The channels used in TC0 for generating the three interrupts. */ +#define tmrTC0_CHANNEL_0 0 /* At tmrTIMER_0_FREQUENCY */ +#define tmrTC0_CHANNEL_1 1 /* At tmrTIMER_1_FREQUENCY */ +#define tmrTC1_CHANNEL_0 0 /* At tmrTIMER_2_FREQUENCY */ + +/* The bit within the RC_SR register that indicates an RC compare. */ +#define tmrRC_COMPARE ( 1UL << 4UL ) + +/* The high frequency interrupt given a priority above the maximum at which +interrupt safe FreeRTOS calls can be made. The priority of the lower frequency +timers must still be above the tick interrupt priority. */ +#define tmrLOWER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY +#define tmrHIGHER_PRIORITY configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY - 1 +/*-----------------------------------------------------------*/ + +/* For convenience the high frequency timer increments a variable that is then +used as the time base for the run time stats. */ +volatile uint32_t ulHighFrequencyTimerCounts = 0; + +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForIntQueueTest( void ) +{ +const uint32_t ulDivider = 128UL, ulTCCLKS = 3UL; + + /* Enable the TC clocks. */ + PMC_EnablePeripheral( ID_TC0 ); + PMC_EnablePeripheral( ID_TC1 ); + + /* Configure TC0 channel 0 for a tmrTIMER_0_FREQUENCY frequency and trigger + on RC compare. This is part of the IntQTimer test. */ + TC_Configure( TC0, tmrTC0_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG ); + TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_0_FREQUENCY * ulDivider ); + TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_IER = TC_IER_CPCS; + + /* Configure TC0 channel 1 for a tmrTIMER_1_FREQUENCY frequency and trigger + on RC compare. This is part of the IntQTimer test. */ + TC_Configure( TC0, tmrTC0_CHANNEL_1, ulTCCLKS | TC_CMR_CPCTRG ); + TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_1_FREQUENCY * ulDivider ); + TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_IER = TC_IER_CPCS; + + /* Configure and enable TC0 interrupt on RC compare. */ + NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY ); + NVIC_ClearPendingIRQ( TC0_IRQn ); + NVIC_EnableIRQ( TC0_IRQn ); + + /* Configure TC1 channel 0 tmrTIMER_2_FREQUENCY frequency and trigger on + RC compare. This is the very high frequency timer. */ + TC_Configure( TC1, tmrTC1_CHANNEL_0, ulTCCLKS | TC_CMR_CPCTRG ); + TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_RC = ( configCPU_CLOCK_HZ / 2 ) / ( tmrTIMER_2_FREQUENCY * ulDivider ); + TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_IER = TC_IER_CPCS; + + /* Configure and enable TC1 interrupt on RC compare */ +// NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY ); +// NVIC_ClearPendingIRQ( TC1_IRQn ); +// NVIC_EnableIRQ( TC1_IRQn ); + + TC_Start( TC0, tmrTC0_CHANNEL_0 ); + TC_Start( TC0, tmrTC0_CHANNEL_1 ); +// TC_Start( TC1, tmrTC1_CHANNEL_0 ); +} +/*-----------------------------------------------------------*/ + +void TC0_Handler( void ) +{ + /* Read will clear the status bit. */ + if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_0 ].TC_SR & tmrRC_COMPARE ) != 0 ) + { + /* Call the IntQ test function for this channel. */ + portYIELD_FROM_ISR( xFirstTimerHandler() ); + } + + if( ( TC0->TC_CHANNEL[ tmrTC0_CHANNEL_1 ].TC_SR & tmrRC_COMPARE ) != 0 ) + { + /* Call the IntQ test function for this channel. */ + portYIELD_FROM_ISR( xSecondTimerHandler() ); + } +} +/*-----------------------------------------------------------*/ + +void TC1_Handler( void ) +{ +volatile uint32_t ulDummy; + + /* Dummy read to clear status bit. */ + ulDummy = TC1->TC_CHANNEL[ tmrTC1_CHANNEL_0 ].TC_SR; + NVIC_ClearPendingIRQ( TC1_IRQn ); + + /* Keep a count of the number of interrupts to use as a time base for the + run-time stats. */ + ulHighFrequencyTimerCounts++; + + /* Prevent compiler warnings about the variable being set but then + unused. */ + ( void ) ulDummy; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h new file mode 100644 index 000000000..528e6fdfb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/IntQueueTimer.h @@ -0,0 +1,78 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H + +void vInitialiseTimerForIntQueueTest( void ); +BaseType_t xTimer0Handler( void ); +BaseType_t xTimer1Handler( void ); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c new file mode 100644 index 000000000..63df4be3a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/RegTest_GCC.c @@ -0,0 +1,457 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * "Reg test" tasks - These fill the registers with known values, then check + * that each register maintains its expected value for the lifetime of the + * task. Each task uses a different set of values. The reg test tasks execute + * with a very low priority, so get preempted very frequently. A register + * containing an unexpected value is indicative of an error in the context + * switching mechanism. + */ + +void vRegTest1Implementation( void ) __attribute__ ((naked)); +void vRegTest2Implementation( void ) __attribute__ ((naked)); + +void vRegTest1Implementation( void ) +{ + __asm volatile + ( + ".extern ulRegTest1LoopCounter \n" + "/* Fill the core registers with known values. */ \n" + "mov r0, #100 \n" + "mov r1, #101 \n" + "mov r2, #102 \n" + "mov r3, #103 \n" + "mov r4, #104 \n" + "mov r5, #105 \n" + "mov r6, #106 \n" + "mov r7, #107 \n" + "mov r8, #108 \n" + "mov r9, #109 \n" + "mov r10, #110 \n" + "mov r11, #111 \n" + "mov r12, #112 \n" + + "/* Fill the VFP registers with known values. */ \n" + "vmov d0, r0, r1 \n" + "vmov d1, r2, r3 \n" + "vmov d2, r4, r5 \n" + "vmov d3, r6, r7 \n" + "vmov d4, r8, r9 \n" + "vmov d5, r10, r11 \n" + "vmov d6, r0, r1 \n" + "vmov d7, r2, r3 \n" + "vmov d8, r4, r5 \n" + "vmov d9, r6, r7 \n" + "vmov d10, r8, r9 \n" + "vmov d11, r10, r11 \n" + "vmov d12, r0, r1 \n" + "vmov d13, r2, r3 \n" + "vmov d14, r4, r5 \n" + "vmov d15, r6, r7 \n" + + "reg1_loop: \n" + "/* Check all the VFP registers still contain the values set above. \n" + "First save registers that are clobbered by the test. */ \n" + "push { r0-r1 } \n" + + "vmov r0, r1, d0 \n" + "cmp r0, #100 \n" + "bne reg1_error_loopf \n" + "cmp r1, #101 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d1 \n" + "cmp r0, #102 \n" + "bne reg1_error_loopf \n" + "cmp r1, #103 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d2 \n" + "cmp r0, #104 \n" + "bne reg1_error_loopf \n" + "cmp r1, #105 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d3 \n" + "cmp r0, #106 \n" + "bne reg1_error_loopf \n" + "cmp r1, #107 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d4 \n" + "cmp r0, #108 \n" + "bne reg1_error_loopf \n" + "cmp r1, #109 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d5 \n" + "cmp r0, #110 \n" + "bne reg1_error_loopf \n" + "cmp r1, #111 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d6 \n" + "cmp r0, #100 \n" + "bne reg1_error_loopf \n" + "cmp r1, #101 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d7 \n" + "cmp r0, #102 \n" + "bne reg1_error_loopf \n" + "cmp r1, #103 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d8 \n" + "cmp r0, #104 \n" + "bne reg1_error_loopf \n" + "cmp r1, #105 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d9 \n" + "cmp r0, #106 \n" + "bne reg1_error_loopf \n" + "cmp r1, #107 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d10 \n" + "cmp r0, #108 \n" + "bne reg1_error_loopf \n" + "cmp r1, #109 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d11 \n" + "cmp r0, #110 \n" + "bne reg1_error_loopf \n" + "cmp r1, #111 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d12 \n" + "cmp r0, #100 \n" + "bne reg1_error_loopf \n" + "cmp r1, #101 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d13 \n" + "cmp r0, #102 \n" + "bne reg1_error_loopf \n" + "cmp r1, #103 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d14 \n" + "cmp r0, #104 \n" + "bne reg1_error_loopf \n" + "cmp r1, #105 \n" + "bne reg1_error_loopf \n" + "vmov r0, r1, d15 \n" + "cmp r0, #106 \n" + "bne reg1_error_loopf \n" + "cmp r1, #107 \n" + "bne reg1_error_loopf \n" + + "/* Restore the registers that were clobbered by the test. */ \n" + "pop {r0-r1} \n" + + "/* VFP register test passed. Jump to the core register test. */ \n" + "b reg1_loopf_pass \n" + + "reg1_error_loopf: \n" + "/* If this line is hit then a VFP register value was found to be incorrect. */ \n" + "b reg1_error_loopf \n" + + "reg1_loopf_pass: \n" + + "cmp r0, #100 \n" + "bne reg1_error_loop \n" + "cmp r1, #101 \n" + "bne reg1_error_loop \n" + "cmp r2, #102 \n" + "bne reg1_error_loop \n" + "cmp r3, #103 \n" + "bne reg1_error_loop \n" + "cmp r4, #104 \n" + "bne reg1_error_loop \n" + "cmp r5, #105 \n" + "bne reg1_error_loop \n" + "cmp r6, #106 \n" + "bne reg1_error_loop \n" + "cmp r7, #107 \n" + "bne reg1_error_loop \n" + "cmp r8, #108 \n" + "bne reg1_error_loop \n" + "cmp r9, #109 \n" + "bne reg1_error_loop \n" + "cmp r10, #110 \n" + "bne reg1_error_loop \n" + "cmp r11, #111 \n" + "bne reg1_error_loop \n" + "cmp r12, #112 \n" + "bne reg1_error_loop \n" + + "/* Everything passed, increment the loop counter. */ \n" + "push { r0-r1 } \n" + "ldr r0, =ulRegTest1LoopCounter \n" + "ldr r1, [r0] \n" + "adds r1, r1, #1 \n" + "str r1, [r0] \n" + "pop { r0-r1 } \n" + + "/* Start again. */ \n" + "b reg1_loop \n" + + "reg1_error_loop: \n" + "/* If this line is hit then there was an error in a core register value. \n" + "The loop ensures the loop counter stops incrementing. */ \n" + "b reg1_error_loop \n" + "nop " + ); /* __asm volatile. */ +} +/*-----------------------------------------------------------*/ + +void vRegTest2Implementation( void ) +{ + __asm volatile + ( + ".extern ulRegTest2LoopCounter \n" + "/* Set all the core registers to known values. */ \n" + "mov r0, #-1 \n" + "mov r1, #1 \n" + "mov r2, #2 \n" + "mov r3, #3 \n" + "mov r4, #4 \n" + "mov r5, #5 \n" + "mov r6, #6 \n" + "mov r7, #7 \n" + "mov r8, #8 \n" + "mov r9, #9 \n" + "mov r10, #10 \n" + "mov r11, #11 \n" + "mov r12, #12 \n" + + "/* Set all the VFP to known values. */ \n" + "vmov d0, r0, r1 \n" + "vmov d1, r2, r3 \n" + "vmov d2, r4, r5 \n" + "vmov d3, r6, r7 \n" + "vmov d4, r8, r9 \n" + "vmov d5, r10, r11 \n" + "vmov d6, r0, r1 \n" + "vmov d7, r2, r3 \n" + "vmov d8, r4, r5 \n" + "vmov d9, r6, r7 \n" + "vmov d10, r8, r9 \n" + "vmov d11, r10, r11 \n" + "vmov d12, r0, r1 \n" + "vmov d13, r2, r3 \n" + "vmov d14, r4, r5 \n" + "vmov d15, r6, r7 \n" + + "reg2_loop: \n" + + "/* Check all the VFP registers still contain the values set above. \n" + "First save registers that are clobbered by the test. */ \n" + "push { r0-r1 } \n" + + "vmov r0, r1, d0 \n" + "cmp r0, #-1 \n" + "bne reg2_error_loopf \n" + "cmp r1, #1 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d1 \n" + "cmp r0, #2 \n" + "bne reg2_error_loopf \n" + "cmp r1, #3 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d2 \n" + "cmp r0, #4 \n" + "bne reg2_error_loopf \n" + "cmp r1, #5 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d3 \n" + "cmp r0, #6 \n" + "bne reg2_error_loopf \n" + "cmp r1, #7 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d4 \n" + "cmp r0, #8 \n" + "bne reg2_error_loopf \n" + "cmp r1, #9 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d5 \n" + "cmp r0, #10 \n" + "bne reg2_error_loopf \n" + "cmp r1, #11 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d6 \n" + "cmp r0, #-1 \n" + "bne reg2_error_loopf \n" + "cmp r1, #1 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d7 \n" + "cmp r0, #2 \n" + "bne reg2_error_loopf \n" + "cmp r1, #3 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d8 \n" + "cmp r0, #4 \n" + "bne reg2_error_loopf \n" + "cmp r1, #5 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d9 \n" + "cmp r0, #6 \n" + "bne reg2_error_loopf \n" + "cmp r1, #7 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d10 \n" + "cmp r0, #8 \n" + "bne reg2_error_loopf \n" + "cmp r1, #9 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d11 \n" + "cmp r0, #10 \n" + "bne reg2_error_loopf \n" + "cmp r1, #11 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d12 \n" + "cmp r0, #-1 \n" + "bne reg2_error_loopf \n" + "cmp r1, #1 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d13 \n" + "cmp r0, #2 \n" + "bne reg2_error_loopf \n" + "cmp r1, #3 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d14 \n" + "cmp r0, #4 \n" + "bne reg2_error_loopf \n" + "cmp r1, #5 \n" + "bne reg2_error_loopf \n" + "vmov r0, r1, d15 \n" + "cmp r0, #6 \n" + "bne reg2_error_loopf \n" + "cmp r1, #7 \n" + "bne reg2_error_loopf \n" + + "/* Restore the registers that were clobbered by the test. */ \n" + "pop {r0-r1} \n" + + "/* VFP register test passed. Jump to the core register test. */ \n" + "b reg2_loopf_pass \n" + + "reg2_error_loopf: \n" + "/* If this line is hit then a VFP register value was found to be \n" + "incorrect. */ \n" + "b reg2_error_loopf \n" + + "reg2_loopf_pass: \n" + + "cmp r0, #-1 \n" + "bne reg2_error_loop \n" + "cmp r1, #1 \n" + "bne reg2_error_loop \n" + "cmp r2, #2 \n" + "bne reg2_error_loop \n" + "cmp r3, #3 \n" + "bne reg2_error_loop \n" + "cmp r4, #4 \n" + "bne reg2_error_loop \n" + "cmp r5, #5 \n" + "bne reg2_error_loop \n" + "cmp r6, #6 \n" + "bne reg2_error_loop \n" + "cmp r7, #7 \n" + "bne reg2_error_loop \n" + "cmp r8, #8 \n" + "bne reg2_error_loop \n" + "cmp r9, #9 \n" + "bne reg2_error_loop \n" + "cmp r10, #10 \n" + "bne reg2_error_loop \n" + "cmp r11, #11 \n" + "bne reg2_error_loop \n" + "cmp r12, #12 \n" + "bne reg2_error_loop \n" + + "/* Increment the loop counter to indicate this test is still functioning \n" + "correctly. */ \n" + "push { r0-r1 } \n" + "ldr r0, =ulRegTest2LoopCounter \n" + "ldr r1, [r0] \n" + "adds r1, r1, #1 \n" + "str r1, [r0] \n" + + "/* Yield to increase test coverage. */ \n" + "movs r0, #0x01 \n" + "ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ \n" + "lsl r0, r0, #28 /* Shift to PendSV bit */ \n" + "str r0, [r1] \n" + "dsb \n" + + "pop { r0-r1 } \n" + + "/* Start again. */ \n" + "b reg2_loop \n" + + "reg2_error_loop: \n" + "/* If this line is hit then there was an error in a core register value. \n" + "This loop ensures the loop counter variable stops incrementing. */ \n" + "b reg2_error_loop \n" + ); /* __asm volatile */ +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c new file mode 100644 index 000000000..eef1ca3b4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/Full_Demo/main_full.c @@ -0,0 +1,432 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky style + * project, and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select + * between the two. See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY + * in main.c. This file implements the comprehensive test and demo version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is initially set to three seconds. The + * task checks that all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors. + * If the check task discovers that a task has either stalled, or reported an + * error, then it changes its own execution period from the initial three + * seconds, to just 200ms. The check task also toggles an LED each time it is + * called. This provides a visual indication of the system status: If the LED + * toggles every three seconds, then no issues have been discovered. If the LED + * toggles every 200ms, then an issue has been discovered with at least one + * task. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "BlockQ.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "death.h" +#include "partest.h" +#include "comtest2.h" +#include "serial.h" +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "IntSemTest.h" +#include "TaskNotify.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1UL ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2UL ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3UL ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainCDC_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * 2UL ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* The initial priority used by the UART command console task. */ +#define mainUART_COMMAND_CONSOLE_TASK_PRIORITY ( configMAX_PRIORITIES - 2 ) + +/* The LED used by the check timer. */ +#define mainCHECK_LED ( 0 ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( 0UL ) + +/* The period after which the check timer will expire, in ms, provided no errors +have been reported by any of the standard demo tasks. ms are converted to the +equivalent in ticks using the portTICK_PERIOD_MS constant. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD ( 3000UL / portTICK_PERIOD_MS ) + +/* The period at which the check timer will expire, in ms, if an error has been +reported in one of the standard demo tasks. ms are converted to the equivalent +in ticks using the portTICK_PERIOD_MS constant. */ +#define mainERROR_CHECK_TASK_PERIOD ( 200UL / portTICK_PERIOD_MS ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + +/* + * Called by main() to run the full demo (as opposed to the blinky demo) when + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +void main_full( void ); + +/* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY ); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartEventGroupTasks(); + vStartInterruptSemaphoreTasks(); + vStartTaskNotifyTask(); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* The set of tasks created by the following function call have to be + created last as they keep account of the number of tasks they expect to see + running. */ + vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static unsigned long ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +unsigned long ulErrorFound = pdFALSE; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The onboard LED is toggled on each iteration. + If an error is detected then the delay period is decreased from + mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the + effect of increasing the rate at which the onboard LED toggles, and in so + doing gives visual feedback of the system status. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 0UL; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 1UL; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 2UL; + } + + if( xAreBlockingQueuesStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 3UL; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 4UL; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 5UL; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 6UL; + } + + if( xIsCreateTaskStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 7UL; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 8UL; + } + + if( xAreTimerDemoTasksStillRunning( ( TickType_t ) xDelayPeriod ) != pdPASS ) + { + ulErrorFound = 1UL << 9UL; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound = 1UL << 10UL; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdPASS ) + { + ulErrorFound = 1UL << 11UL; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1UL << 12UL; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1UL << 13UL; + } + + if( xAreTaskNotificationTasksStillRunning() != pdPASS ) + { + ulErrorFound = 1UL << 14UL; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound = 1UL << 15UL; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound = 1UL << 16UL; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Toggle the check LED to give an indication of the system status. If + the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then + everything is ok. A faster toggle indicates an error. */ + LED_Toggle( mainCHECK_LED ); + + if( ulErrorFound != pdFALSE ) + { + /* An error has been detected in one of the tasks - flash the LED + at a higher frequency to give visible feedback that something has + gone wrong (it might just be that the loop back connector required + by the comtest tasks has not been fitted). */ + xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; + } + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check timer will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_flash.ld new file mode 100644 index 000000000..21f8553db --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_flash.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_sdram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_sdram.ld new file mode 100644 index 000000000..4a6936cea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_sdram.ld @@ -0,0 +1,10 @@ + +SECTIONS +{ + _sdram_lma = .; + sdram_region : + AT ( _sdram_lma ) + { + *(sdram_region) + } >sdram +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_sram.ld new file mode 100644 index 000000000..b351d1660 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/sam_sram.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(8); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(8); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/samv71q21_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/samv71q21_flash.ld new file mode 100644 index 000000000..f26ff9277 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/samv71q21_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE ../LinkerScripts/sam_flash.ld +INCLUDE ../LinkerScripts/sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/samv71q21_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/samv71q21_sram.ld new file mode 100644 index 000000000..5d23f2dfe --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/LinkerScripts/samv71q21_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.atsln b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.atsln new file mode 100644 index 000000000..9c7c5b581 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.atsln @@ -0,0 +1,17 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Atmel Studio Solution File, Format Version 11.00 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "RTOSDemo", "RTOSDemo.cproj", "{C9E51A8C-F289-47EA-9002-C417C1EEC9DA}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|ARM = Debug|ARM + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {C9E51A8C-F289-47EA-9002-C417C1EEC9DA}.Debug|ARM.ActiveCfg = Debug|ARM + {C9E51A8C-F289-47EA-9002-C417C1EEC9DA}.Debug|ARM.Build.0 = Debug|ARM + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.atsuo b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.atsuo new file mode 100644 index 000000000..779df3000 Binary files /dev/null and b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.atsuo differ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.cproj b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.cproj new file mode 100644 index 000000000..8aac650a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RTOSDemo.cproj @@ -0,0 +1,307 @@ + + + + 2.0 + 6.2 + com.Atmel.ARMGCC.C + {c9e51a8c-f289-47ea-9002-c417c1eec9da} + ATSAMV71Q21 + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + RTOSDemo + RTOSDemo + RTOSDemo + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 1 + + + + + + + + + + + + + com.atmel.avrdbg.tool.samice + SWD + + + + 2000000 + + SWD + + com.atmel.avrdbg.tool.edbg + ATML2407080200001813 + EDBG + + + + + 4000000 + + SWD + C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_AtmelStudio\jlink.config + + com.atmel.avrdbg.tool.samice + 59101789 + J-Link + + + + + + True + True + True + True + True + True + + + flash + TRACE_LEVEL=4 + + + + + ../libchip_samv7/include/cmsis/CMSIS/Include + ../libchip_samv7/include/samv7 + ../libboard_samv7-ek + ../libchip_samv7 + ../../../Source/include + ../../../Source/portable/GCC/ARM_CM7/r0p1 + ../../Common/include + ../Full_Demo + .. + %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\samv71\include + %24(ToolchainDir)\..\..\CMSIS_Atmel + %24(ToolchainDir)\..\..\CMSIS_Atmel\CMSIS\Include + %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL + + + True + Maximum (-g3) + True + True + -std=gnu99 -mfpu=fpv4-sp-d16 -mfloat-abi=softfp + True + + -T../LinkerScripts/samv71q21_flash.ld + Default (-g) + + + %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL\samv71\include + %24(ToolchainDir)\..\..\CMSIS_Atmel + %24(ToolchainDir)\..\..\CMSIS_Atmel\CMSIS\Include + %24(ToolchainDir)\..\..\CMSIS_Atmel\Device\ATMEL + + + Default (-Wa,-g) + + + False + all + clean + + + + compile + FreeRTOS_Source\event_groups.c + + + compile + FreeRTOS_Source\list.c + + + compile + FreeRTOS_Source\portable\port.c + + + compile + FreeRTOS_Source\portable\heap_4.c + + + compile + FreeRTOS_Source\queue.c + + + compile + FreeRTOS_Source\tasks.c + + + compile + FreeRTOS_Source\timers.c + + + compile + Full_Demo\Standard_Demo_Tasks\BlockQ.c + + + compile + Full_Demo\Standard_Demo_Tasks\blocktim.c + + + compile + Full_Demo\Standard_Demo_Tasks\countsem.c + + + compile + Full_Demo\Standard_Demo_Tasks\death.c + + + compile + Full_Demo\Standard_Demo_Tasks\dynamic.c + + + compile + Full_Demo\Standard_Demo_Tasks\EventGroupsDemo.c + + + compile + Full_Demo\Standard_Demo_Tasks\flop.c + + + compile + Full_Demo\Standard_Demo_Tasks\GenQTest.c + + + compile + Full_Demo\Standard_Demo_Tasks\IntQueue.c + + + compile + Full_Demo\Standard_Demo_Tasks\IntSemTest.c + + + compile + Full_Demo\Standard_Demo_Tasks\QueueOverwrite.c + + + compile + Full_Demo\Standard_Demo_Tasks\QueueSet.c + + + compile + Full_Demo\Standard_Demo_Tasks\recmutex.c + + + compile + Full_Demo\Standard_Demo_Tasks\semtest.c + + + compile + Full_Demo\Standard_Demo_Tasks\TaskNotify.c + + + compile + Full_Demo\Standard_Demo_Tasks\TimerDemo.c + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + Atmel_LibBoard\startup_sam.c + + + compile + Atmel_LibBoard\system_sam.c + + + compile + Atmel_LibBoard\board_lowlevel.c + + + compile + Atmel_LibBoard\board_memories.c + + + compile + Atmel_LibBoard\dbg_console.c + + + compile + Atmel_LibBoard\led.c + + + compile + Atmel_LibBoard\syscalls.c + + + compile + Atmel_LibChip\mpu.c + + + compile + Atmel_LibChip\pio.c + + + compile + Atmel_LibChip\pio_capture.c + + + compile + Atmel_LibChip\pmc.c + + + compile + Atmel_LibChip\supc.c + + + compile + Atmel_LibChip\tc.c + + + compile + Atmel_LibChip\wdt.c + + + compile + + + + + + + + + + + + + + compile + FreeRTOS_Source\readme.txt + + + + \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RegTest.s b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RegTest.s new file mode 100644 index 000000000..a24d27ae0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/RegTest.s @@ -0,0 +1,526 @@ +/* + FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that has become a de facto standard. * + * * + * Help yourself get started quickly and support the FreeRTOS * + * project by purchasing a FreeRTOS tutorial book, reference * + * manual, or both from: http://www.FreeRTOS.org/Documentation * + * * + * Thank you! * + * * + *************************************************************************** + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available from the following + link: http://www.freertos.org/a00114.html + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#include + + + RSEG CODE:CODE(2) + thumb + + EXTERN ulRegTest1LoopCounter + EXTERN ulRegTest2LoopCounter + + PUBLIC vRegTest1Implementation + PUBLIC vRegTest2Implementation + PUBLIC vRegTestClearFlopRegistersToParameterValue + PUBLIC ulRegTestCheckFlopRegistersContainParameterValue + +/*-----------------------------------------------------------*/ + +vRegTest1Implementation + + /* Fill the core registers with known values. */ + mov r0, #100 + mov r1, #101 + mov r2, #102 + mov r3, #103 + mov r4, #104 + mov r5, #105 + mov r6, #106 + mov r7, #107 + mov r8, #108 + mov r9, #109 + mov r10, #110 + mov r11, #111 + mov r12, #112 + + /* Fill the VFP registers with known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg1_loop: + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #108 + bne reg1_error_loopf + cmp r1, #109 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #110 + bne reg1_error_loopf + cmp r1, #111 + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #100 + bne reg1_error_loopf + cmp r1, #101 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #102 + bne reg1_error_loopf + cmp r1, #103 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #104 + bne reg1_error_loopf + cmp r1, #105 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #106 + bne reg1_error_loopf + cmp r1, #107 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass + + cmp r0, #100 + bne reg1_error_loop + cmp r1, #101 + bne reg1_error_loop + cmp r2, #102 + bne reg1_error_loop + cmp r3, #103 + bne reg1_error_loop + cmp r4, #104 + bne reg1_error_loop + cmp r5, #105 + bne reg1_error_loop + cmp r6, #106 + bne reg1_error_loop + cmp r7, #107 + bne reg1_error_loop + cmp r8, #108 + bne reg1_error_loop + cmp r9, #109 + bne reg1_error_loop + cmp r10, #110 + bne reg1_error_loop + cmp r11, #111 + bne reg1_error_loop + cmp r12, #112 + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + +/*-----------------------------------------------------------*/ + + +vRegTest2Implementation + + /* Set all the core registers to known values. */ + mov r0, #-1 + mov r1, #1 + mov r2, #2 + mov r3, #3 + mov r4, #4 + mov r5, #5 + mov r6, #6 + mov r7, #7 + mov r8, #8 + mov r9, #9 + mov r10, #10 + mov r11, #11 + mov r12, #12 + + /* Set all the VFP to known values. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + +reg2_loop: + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #8 + bne reg2_error_loopf + cmp r1, #9 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #10 + bne reg2_error_loopf + cmp r1, #11 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #-1 + bne reg2_error_loopf + cmp r1, #1 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #2 + bne reg2_error_loopf + cmp r1, #3 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #4 + bne reg2_error_loopf + cmp r1, #5 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #6 + bne reg2_error_loopf + cmp r1, #7 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass + + cmp r0, #-1 + bne reg2_error_loop + cmp r1, #1 + bne reg2_error_loop + cmp r2, #2 + bne reg2_error_loop + cmp r3, #3 + bne reg2_error_loop + cmp r4, #4 + bne reg2_error_loop + cmp r5, #5 + bne reg2_error_loop + cmp r6, #6 + bne reg2_error_loop + cmp r7, #7 + bne reg2_error_loop + cmp r8, #8 + bne reg2_error_loop + cmp r9, #9 + bne reg2_error_loop + cmp r10, #10 + bne reg2_error_loop + cmp r11, #11 + bne reg2_error_loop + cmp r12, #12 + bne reg2_error_loop + + /* Increment the loop counter to indicate this test is still functioning + correctly. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + + /* Yield to increase test coverage. */ + movs r0, #0x01 + ldr r1, =0xe000ed04 /*NVIC_INT_CTRL */ + lsl r0, r0, #28 /* Shift to PendSV bit */ + str r0, [r1] + dsb + + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + This loop ensures the loop counter variable stops incrementing. */ + b reg2_error_loop + +/*-----------------------------------------------------------*/ + +vRegTestClearFlopRegistersToParameterValue + + /* Clobber the auto saved registers. */ + vmov d0, r0, r0 + vmov d1, r0, r0 + vmov d2, r0, r0 + vmov d3, r0, r0 + vmov d4, r0, r0 + vmov d5, r0, r0 + vmov d6, r0, r0 + vmov d7, r0, r0 + bx lr + +/*-----------------------------------------------------------*/ + +ulRegTestCheckFlopRegistersContainParameterValue + + vmov r1, s0 + cmp r0, r1 + bne return_error + vmov r1, s1 + cmp r0, r1 + bne return_error + vmov r1, s2 + cmp r0, r1 + bne return_error + vmov r1, s3 + cmp r0, r1 + bne return_error + vmov r1, s4 + cmp r0, r1 + bne return_error + vmov r1, s5 + cmp r0, r1 + bne return_error + vmov r1, s6 + cmp r0, r1 + bne return_error + vmov r1, s7 + cmp r0, r1 + bne return_error + vmov r1, s8 + cmp r0, r1 + bne return_error + vmov r1, s9 + cmp r0, r1 + bne return_error + vmov r1, s10 + cmp r0, r1 + bne return_error + vmov r1, s11 + cmp r0, r1 + bne return_error + vmov r1, s12 + cmp r0, r1 + bne return_error + vmov r1, s13 + cmp r0, r1 + bne return_error + vmov r1, s14 + cmp r0, r1 + bne return_error + vmov r1, s15 + cmp r0, r1 + bne return_error + +return_pass + mov r0, #1 + bx lr + +return_error + mov r0, #0 + bx lr + + END + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/jlink.config b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/jlink.config new file mode 100644 index 000000000..4722ca16d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/jlink.config @@ -0,0 +1,34 @@ +[BREAKPOINTS] +ShowInfoWin = 1 +EnableFlashBP = 2 +BPDuringExecution = 0 +[CFI] +CFISize = 0x00 +CFIAddr = 0x00 +[CPU] +OverrideMemMap = 0 +AllowSimulation = 1 +ScriptFile="" +[FLASH] +CacheExcludeSize = 0x00 +CacheExcludeAddr = 0x00 +MinNumBytesFlashDL = 0 +SkipProgOnCRCMatch = 1 +VerifyDownload = 1 +AllowCaching = 1 +EnableFlashDL = 2 +Override = 1 +Device="Unspecified" +[GENERAL] +WorkRAMSize = 0x00 +WorkRAMAddr = 0x00 +RAMUsageLimit = 0x00 +[SWO] +SWOLogFile="" +[MEM] +RdOverrideOrMask = 0x00 +RdOverrideAndMask = 0xFFFFFFFF +RdOverrideAddr = 0xFFFFFFFF +WrOverrideOrMask = 0x00 +WrOverrideAndMask = 0xFFFFFFFF +WrOverrideAddr = 0xFFFFFFFF diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/jlink.log b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/jlink.log new file mode 100644 index 000000000..0f96e7e4e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/jlink.log @@ -0,0 +1,2719 @@ +T1BFC 4487:345 SEGGER J-Link V4.98e Log File (0001ms, 6426ms total) +T1BFC 4487:345 DLL Compiled: May 5 2015 11:00:52 (0001ms, 6426ms total) +T1BFC 4487:345 Logging started @ 2015-06-16 13:36 (0001ms, 6426ms total) +T1BFC 4487:372 JLINK_ExecCommand("Device = ATSAMV71Q21", ...)Device "ATSAMV71Q21" selected. returns 0x00 (0000ms, 6426ms total) +T1BFC 4491:348 JLINK_ExecCommand("ProjectFile = C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_AtmelStudio\jlink.config", ...)Device "UNSPECIFIED" selected. returns 0x00 (0000ms, 6426ms total) +T1BFC 4491:374 JLINK_ExecCommand("Device = ATSAMV71Q21", ...)Device "ATSAMV71Q21" selected. returns 0x00 (0001ms, 6427ms total) +T1BFC 4491:375 JLINK_TIF_Select(JLINKARM_TIF_SWD) returns 0x00 (0004ms, 6431ms total) +T1BFC 4491:379 JLINK_SetSpeed(1000) (0001ms, 6432ms total) +T1BFC 4491:380 JLINK_ResetPullsRESET(OFF) (0000ms, 6432ms total) +T1BFC 4491:380 JLINK_Connect() >0x108 TIF>Found SWD-DP with ID 0x0BD11477 >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> + >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>Found Cortex-M7 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000) +FPUnit: 8 code (BP) slots and 0 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FD000 -- CPU_ReadMem(16 bytes @ 0xE00FD000) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) -- CPU_ReadMem(16 bytes @ 0xE00FEFE0) +ROMTbl 0 [0]: 00001000, CID: B105100D, PID: 000BB4C8 ROM TableROMTbl 1 @ E00FE000 -- CPU_ReadMem(16 bytes @ 0xE00FE000) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) -- CPU_ReadMem(16 bytes @ 0xE00FFFE0)ROMTbl 1 [0]: 00001000, CID: B105100D, PID: 000BB4C7 ROM TableROMTbl 2 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 2 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_ReadMem(16 bytes @ 0xE0001FF0) + -- CPU_ReadMem(16 bytes @ 0xE0001FE0)ROMTbl 2 [1]: FFF02000, CID: B105E00D, PID: 000BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 2 [2]: FFF03000, CID: B105E00D, PID: 000BB00E FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 2 [3]: FFF01000, CID: B105E00D, PID: 000BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0) +ROMTbl 1 [1]: FFF43000, CID: B105900D, PID: 000BB975 ETM-M7 -- CPU_ReadMem(16 bytes @ 0xE00FE010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl 0 [1]: FFF43000, CID: B105900D, PID: 000BB9A9 TPIU-M7 -- CPU_ReadMem(16 bytes @ 0xE00FD010) -- CPU_ReadMem(4 bytes @ 0xE000ED78) -- CPU_WriteMem(4 bytes @ 0xE000ED84) -- CPU_ReadMem(4 bytes @ 0xE000ED80)I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way -- CPU_WriteMem(4 bytes @ 0xE000ED84) -- CPU_ReadMem(4 bytes @ 0xE000ED80) +D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way returns 0x00 (0113ms, 6545ms total) +T1BFC 4491:493 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0001ms, 6546ms total) +T1BFC 4491:494 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6547ms total) +T1BFC 4491:495 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6548ms total) +T1BFC 4491:496 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 6549ms total) +T1BFC 4491:497 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6550ms total) +T1BFC 4491:498 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6551ms total) +T1BFC 4491:499 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 6552ms total) +T1BFC 4491:500 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6553ms total) +T1BFC 4491:501 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6554ms total) +T1BFC 4491:502 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 6555ms total) +T1BFC 4491:503 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6556ms total) +T1BFC 4491:504 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6557ms total) +T1BFC 4491:505 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 6558ms total) +T1BFC 4491:506 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6559ms total) +T1BFC 4491:507 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6560ms total) +T1BFC 4491:508 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 6561ms total) +T1BFC 4491:509 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6562ms total) +T1BFC 4491:510 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6563ms total) +T1BFC 4491:511 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 6564ms total) +T1BFC 4491:512 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6565ms total) +T1BFC 4491:513 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6566ms total) +T1BFC 4491:514 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 6567ms total) +T1BFC 4491:515 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 6568ms total) +T1BFC 4491:516 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 6569ms total) +T1BFC 4491:517 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 6570ms total) +T1BFC 4491:518 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 6571ms total) +T1BFC 4491:519 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 6572ms total) +T1BFC 4491:520 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 6573ms total) +T1BFC 4491:521 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 6574ms total) +T1BFC 4491:522 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 6575ms total) +T1BFC 4491:523 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 6576ms total) +T1BFC 4491:524 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU is running -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0000ms, 6576ms total) +T1BFC 4491:525 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU is running -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0000ms, 6577ms total) +T1BFC 4491:526 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0000ms, 6577ms total) +T1BFC 4491:527 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0000ms, 6577ms total) +T1BFC 4491:527 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 6578ms total) +T1BFC 4491:529 JLINK_ReadMem (0xE0001000, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001000) - Data: 01 00 00 40 returns 0x00 (0000ms, 6578ms total) +T1BFC 4491:530 JLINK_ReadMem (0xE0001000, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001000) - Data: 01 00 00 40 returns 0x00 (0000ms, 6578ms total) +T1BFC 4491:531 JLINK_ReadMem (0xE0001028, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x00 (0000ms, 6578ms total) +T1BFC 4491:532 JLINK_WriteMem(0xE0001028, 0x0004 Bytes, ...) - Data: 00 01 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0000ms, 6578ms total) +T1BFC 4491:532 JLINK_ReadMem (0xE0001028, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x00 (0001ms, 6579ms total) +T1BFC 4491:533 JLINK_ReadMem (0xE0001038, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 02 00 00 returns 0x00 (0001ms, 6580ms total) +T1BFC 4491:534 JLINK_WriteMem(0xE0001038, 0x0004 Bytes, ...) - Data: 00 03 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 6581ms total) +T1BFC 4491:535 JLINK_ReadMem (0xE0001038, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 03 00 00 returns 0x00 (0001ms, 6582ms total) +T1BFC 4491:536 JLINK_ReadMem (0xE0001048, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x00 (0002ms, 6584ms total) +T1BFC 4491:538 JLINK_WriteMem(0xE0001048, 0x0004 Bytes, ...) - Data: 00 01 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 6585ms total) +T1BFC 4491:539 JLINK_ReadMem (0xE0001048, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x00 (0001ms, 6586ms total) +T1BFC 4491:540 JLINK_ReadMem (0xE0001058, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x00 (0001ms, 6587ms total) +T1BFC 4491:541 JLINK_WriteMem(0xE0001058, 0x0004 Bytes, ...) - Data: 00 01 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0001ms, 6588ms total) +T1BFC 4491:542 JLINK_ReadMem (0xE0001058, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x00 (0001ms, 6589ms total) +T1BFC 4491:543 JLINK_ReadMem (0xE0001024, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001024) - Data: 00 00 00 00 returns 0x00 (0001ms, 6590ms total) +T1BFC 4491:544 JLINK_WriteMem(0xE0001024, 0x0004 Bytes, ...) - Data: 1F 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001024) returns 0x04 (0001ms, 6591ms total) +T1BFC 4491:545 JLINK_ReadMem (0xE0001024, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001024) - Data: 1F 00 00 00 returns 0x00 (0001ms, 6592ms total) +T1BFC 4491:546 JLINK_ReadMem (0xE0001034, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001034) - Data: 00 00 00 00 returns 0x00 (0001ms, 6593ms total) +T1BFC 4491:547 JLINK_WriteMem(0xE0001034, 0x0004 Bytes, ...) - Data: 1F 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001034) returns 0x04 (0001ms, 6594ms total) +T1BFC 4491:548 JLINK_ReadMem (0xE0001034, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001034) - Data: 1F 00 00 00 returns 0x00 (0001ms, 6595ms total) +T1BFC 4491:549 JLINK_ReadMem (0xE0001044, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001044) - Data: 00 00 00 00 returns 0x00 (0001ms, 6596ms total) +T1BFC 4491:550 JLINK_WriteMem(0xE0001044, 0x0004 Bytes, ...) - Data: 1F 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001044) returns 0x04 (0001ms, 6597ms total) +T1BFC 4491:551 JLINK_ReadMem (0xE0001044, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001044) - Data: 1F 00 00 00 returns 0x00 (0001ms, 6598ms total) +T1BFC 4491:552 JLINK_ReadMem (0xE0001054, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001054) - Data: 00 00 00 00 returns 0x00 (0001ms, 6599ms total) +T1BFC 4491:553 JLINK_WriteMem(0xE0001054, 0x0004 Bytes, ...) - Data: 1F 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001054) returns 0x04 (0001ms, 6600ms total) +T1BFC 4491:554 JLINK_ReadMem (0xE0001054, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001054) - Data: 1F 00 00 00 returns 0x00 (0001ms, 6601ms total) +T1BFC 4491:555 JLINK_ReadMem (0xE0001028, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001028) - Data: 00 00 00 00 returns 0x00 (0001ms, 6602ms total) +T1BFC 4491:556 JLINK_ReadMem (0xE0001038, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001038) - Data: 00 03 00 00 returns 0x00 (0001ms, 6603ms total) +T1BFC 4491:557 JLINK_ReadMem (0xE0001048, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001048) - Data: 00 00 00 00 returns 0x00 (0001ms, 6604ms total) +T1BFC 4491:558 JLINK_ReadMem (0xE0001058, 0x0004 Bytes, ...) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE0001058) - Data: 00 00 00 00 returns 0x00 (0001ms, 6605ms total) +T1BFC 4491:559 JLINK_WriteMem(0xE0001020, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001020) returns 0x04 (0000ms, 6605ms total) +T1BFC 4491:560 JLINK_WriteMem(0xE0001024, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001024) returns 0x04 (0001ms, 6606ms total) +T1BFC 4491:561 JLINK_WriteMem(0xE0001028, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001028) returns 0x04 (0001ms, 6607ms total) +T1BFC 4491:562 JLINK_WriteMem(0xE0001030, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001030) returns 0x04 (0001ms, 6608ms total) +T1BFC 4491:563 JLINK_WriteMem(0xE0001034, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001034) returns 0x04 (0001ms, 6609ms total) +T1BFC 4491:564 JLINK_WriteMem(0xE0001038, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001038) returns 0x04 (0001ms, 6610ms total) +T1BFC 4491:565 JLINK_WriteMem(0xE0001040, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001040) returns 0x04 (0001ms, 6611ms total) +T1BFC 4491:566 JLINK_WriteMem(0xE0001044, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001044) returns 0x04 (0001ms, 6612ms total) +T1BFC 4491:567 JLINK_WriteMem(0xE0001048, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001048) returns 0x04 (0001ms, 6613ms total) +T1BFC 4491:568 JLINK_WriteMem(0xE0001050, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001050) returns 0x04 (0001ms, 6614ms total) +T1BFC 4491:569 JLINK_WriteMem(0xE0001054, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001054) returns 0x04 (0000ms, 6614ms total) +T1BFC 4491:570 JLINK_WriteMem(0xE0001058, 0x0004 Bytes, ...) - Data: 00 00 00 00 -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0001058) returns 0x04 (0000ms, 6615ms total) +T1BFC 4491:571 JLINK_Halt() returns 0x00 (0004ms, 6620ms total) +T1BFC 4491:580 JLINK_WriteMem(0x400E0C04, 0x0004 Bytes, ...) - Data: 0B 01 00 5A -- CPU_WriteMem(4 bytes @ 0x400E0C04) returns 0x04 (0001ms, 6621ms total) +T1BFC 4491:581 JLINK_ReadMem (0x400E0C08, 0x0004 Bytes, ...) -- CPU_ReadMem(4 bytes @ 0x400E0C08) - Data: 01 00 00 00 returns 0x00 (0001ms, 6622ms total) +T1BFC 4491:582 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) >0x35 TIF> -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0024ms, 6646ms total) +T1BFC 4491:607 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x00 (0000ms, 6646ms total) +T1BFC 4491:607 JLINK_ReadMemU32(0x400E0940, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x400E0940) - Data: 00 0E 22 A1 returns 0x01 (0001ms, 6647ms total) +T1BFC 4491:616 JLINK_ReadMemHW(0x0040A000, 0x2000 Bytes, ...) -- CPU_ReadMem(8192 bytes @ 0x0040A000) - Data: 72 B6 83 F3 11 88 BF F3 6F 8F BF F3 4F 8F 62 B6 ... returns 0x00 (0113ms, 6760ms total) +T1BFC 4491:732 JLINK_BeginDownload(Flags = 0x00) (0000ms, 6760ms total) +T1BFC 4491:732 JLINK_WriteMem(0x00400000, 0x0200 Bytes, ...) - Data: B8 E4 40 20 CD 36 40 00 79 37 40 00 79 37 40 00 ... returns 0x200 (0001ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400200, 0x0200 Bytes, ...) - Data: 5A 60 FB 68 9A 68 3B 68 9A 60 FB 68 9B 68 3A 68 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400400, 0x0200 Bytes, ...) - Data: FB 79 DB B2 23 F0 7F 03 DA B2 24 4B 1A 70 24 4B ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400600, 0x0200 Bytes, ...) - Data: 00 2B 03 D0 06 4B 4F F0 80 52 1A 60 00 23 7B 60 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400800, 0x0200 Bytes, ...) - Data: 1A 68 1E 4B 1B 68 9A 42 03 D2 19 4B 1A 68 1B 4B ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400A00, 0x0200 Bytes, ...) - Data: E4 C0 40 20 EC C0 40 20 E8 C0 40 20 F0 C0 40 20 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400C00, 0x0200 Bytes, ...) - Data: BB 61 BB 68 00 2B 03 D1 BB 69 BA 69 1A 60 04 E0 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00400E00, 0x0200 Bytes, ...) - Data: 3B 6B 00 22 5A 64 3B 6B 9B 6C B3 F1 FF 3F 02 D1 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401000, 0x0200 Bytes, ...) - Data: FB 6A 7B 61 7B 69 83 F3 11 88 7B 6B 18 46 38 37 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401200, 0x0200 Bytes, ...) - Data: 15 D1 12 4B 4F F0 80 52 1A 60 BF F3 4F 8F BF F3 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401400, 0x0200 Bytes, ...) - Data: 1A 44 FB 68 DA 60 FB 68 DA 68 FB 68 1B 68 9A 42 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401600, 0x0200 Bytes, ...) - Data: FE E7 7B 68 9A 6B 7B 68 DB 6B 9A 42 02 D1 01 23 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401800, 0x0200 Bytes, ...) - Data: 01 3B 9B 00 13 44 FB 61 FB 69 23 F0 07 03 FB 61 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401A00, 0x0200 Bytes, ...) - Data: 7B 68 1A 68 FB 69 9A 42 03 D8 FA 69 3B 6A 9A 42 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401C00, 0x0200 Bytes, ...) - Data: 02 D3 22 4B 01 22 1A 60 1A 4B 1B 68 00 2B CC D1 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00401E00, 0x0200 Bytes, ...) - Data: 1B 68 5A 1C 13 4B 1A 60 13 4B 98 47 13 4B 1B 68 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402000, 0x0200 Bytes, ...) - Data: A5 02 40 00 DC C1 40 20 C0 C1 40 20 ED 01 40 00 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402200, 0x0200 Bytes, ...) - Data: FB 60 FE E7 3B 68 00 2B 0B D1 4F F0 80 03 72 B6 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402400, 0x0200 Bytes, ...) - Data: 95 01 40 00 64 C1 40 20 78 C1 40 20 94 C1 40 20 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402600, 0x0200 Bytes, ...) - Data: F4 C1 40 20 80 B4 83 B0 00 AF 0B 4B 1B 68 00 2B ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402800, 0x0200 Bytes, ...) - Data: 9A 40 10 4B 1B 68 1A 43 0E 4B 1A 60 3B 69 DA 6A ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402A00, 0x0200 Bytes, ...) - Data: 2C C2 40 20 A5 02 40 00 65 2B 40 00 E9 28 40 00 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402C00, 0x0200 Bytes, ...) - Data: FB 6A 00 2B 0B D1 4F F0 80 03 72 B6 83 F3 11 88 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00402E00, 0x0200 Bytes, ...) - Data: BF F3 4F 8F 62 B6 3B 60 FE E7 09 4B 1B 68 1B 68 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403000, 0x0200 Bytes, ...) - Data: 01 2B 04 D0 57 4B 1B 68 5A 1E 56 4B 1A 60 7B 6B ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403200, 0x0200 Bytes, ...) - Data: 30 4B 1B 68 18 46 30 4B 98 47 03 46 01 2B 2A D0 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403400, 0x0200 Bytes, ...) - Data: 1B 68 5A 1C 2B 4B 1A 60 26 4B 1A 68 3B 46 10 46 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403600, 0x0200 Bytes, ...) - Data: 03 F0 10 03 00 2B 0C D0 11 4B 98 47 03 46 00 2B ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403800, 0x0200 Bytes, ...) - Data: 22 F0 03 02 42 F0 01 02 1A 63 00 BF 17 4B 9B 6E ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403A00, 0x0200 Bytes, ...) - Data: FF FF 03 00 01 00 23 03 15 00 44 20 FF FF 01 00 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403C00, 0x0200 Bytes, ...) - Data: C4 AB 40 00 F5 41 40 00 D9 41 40 00 BD 41 40 00 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00403E00, 0x0200 Bytes, ...) - Data: 02 E0 FB 68 BA 68 1A 66 FB 68 1B 6F 7B 61 FB 68 ... returns 0x200 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00404000, 0x2000 Bytes, ...) - Data: 02 E0 FB 68 BA 68 1A 66 BB 79 00 2B 03 D0 FB 68 ... returns 0x2000 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00406000, 0x2000 Bytes, ...) - Data: F6 03 F6 03 F6 03 F6 03 F6 03 F6 03 F6 03 53 03 ... returns 0x2000 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x00408000, 0x2000 Bytes, ...) - Data: 5B 46 FC F7 67 FE C8 46 4E 46 00 28 7C D0 25 9D ... returns 0x2000 (0000ms, 6761ms total) +T1BFC 4491:733 JLINK_WriteMem(0x0040A000, 0x2000 Bytes, ...) - Data: 20 46 42 F8 24 50 98 47 28 46 38 BD 16 23 03 60 ... returns 0x2000 (0000ms, 6761ms total) +T0AC8 4491:752 JLINK_IsHalted() returns TRUE (0000ms, 6761ms total) +T0AC8 4491:752 JLINK_GetMOEs(...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) -- CPU_WriteMem(4 bytes @ 0xE000ED30) returns 0x01 (0002ms, 6763ms total) +T0AC8 4491:754 JLINK_ReadReg(R15 (PC)) -- -------------------------------------- -- Start of determining dirty areas in flash cache -- End of determining dirty areas -- Start of preparing flash programming -- Calculating RAM usage -- RAM usage = 5852 Bytes -- Preserving registers -- Preparing memory -- Determining CPU clock frequency -- CPU clock frequency: 11856 kHz -- CPU frequency = 11856 kHz -- Preparing target -- Downloading RAMCode -- Using alternate TurboMode RAMCode -- Checking target RAM + -- Preparing RAMCode -- End of preparing flash programming -- CPU is running at 120000 kHz. -- Start of comparing flash -- CRC check was estimated as fastest method -- Comparing range 0x400000 - 0x403FFF (2 Sectors, 16 KB), using multi-block CRC calculation -- CRC does not match for sectors 0-1 -- Comparing range 0x404000 - 0x41FFFF (1 Sector, 112 KB), using multi-block CRC calculation -- CRC does not match for sector 0 -- End of comparing flash -- Start of erasing sectors + -- Erasing range 0x00400000 - 0x00403FFF (002 Sectors, 16 KB) -- Erasing range 0x00404000 - 0x0041FFFF (001 Sector, 112 KB) -- End of erasing sectors -- Start of flash programming -- Programming range 0x00400000 - 0x00403FFF (002 Sectors, 16 KB) -- Programming range 0x00404000 - 0x0041FFFF (001 Sector, 112 KB) -- End of flash programming -- Flash programming performed for 2 ranges (131072 bytes) -- 0x400000 - 0x403FFF (002 Sectors, 16 KB) -- 0x404000 - 0x41FFFF (001 Sector, 112 KB) + -- Start of verifying flash -- Checksum calculation was estimated as fastest method -- Checksum calculation was estimated as fastest method -- End of verifying flash -- Start of restoring -- Restore RAMCode -- Restore content of target memory -- Restore target -- Restore memory -- Restore content of registers -- End of restoring -- Total time needed: 1.444s (Prepare: 0.127s, Compare: 0.008s, Erase: 0.419s, Program: 0.868s, Verify: 0.005s, Restore: 0.015s) returns 0x0040BBA0 (1448ms, 8211ms total) +T1BFC 4493:203 JLINK_EndDownload() returns 0x00 (0000ms, 8212ms total) +T1BFC 4493:204 JLINK_JTAG_GetDeviceID(DeviceIndex = 0) returns 0x00 (0000ms, 8212ms total) +T1BFC 4493:204 JLINK_ReadMemU32(0x400E0940, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0x400E0940) - Data: 00 0E 22 A1 returns 0x01 (0001ms, 8213ms total) +T0AC8 4493:221 JLINK_IsHalted() returns TRUE (0001ms, 8214ms total) +T0CD0 4493:246 JLINK_Halt() returns 0x00 (0000ms, 8213ms total) +T0CD0 4493:246 JLINK_ReadReg(R15 (PC)) returns 0x0040BBA0 (0000ms, 8213ms total) +T0CD0 4493:246 JLINK_ReadReg(R13 (SP)) returns 0x2040E738 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R1) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R2) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R3) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R13 (SP)) returns 0x2040E738 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R14) returns 0xFFFFFFFF (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(R15 (PC)) returns 0x0040BBA0 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(MSP) returns 0x2040E738 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8213ms total) +T0CD0 4493:249 JLINK_ReadReg(FPSCR) returns 0x00000000 (0007ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:257 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R1) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R2) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R3) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R13 (SP)) returns 0x2040E738 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R14) returns 0xFFFFFFFF (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(R15 (PC)) returns 0x0040BBA0 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(MSP) returns 0x2040E738 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:308 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8220ms total) +T0CD0 4493:309 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8220ms total) +T0CD0 4493:330 JLINK_ReadReg(R15 (PC)) returns 0x0040BBA0 (0000ms, 8220ms total) +T0CD0 4493:330 JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) >0x35 TIF> -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0024ms, 8244ms total) +T0AC8 4493:354 JLINK_IsHalted() returns TRUE (0000ms, 8244ms total) +T0AC8 4493:354 JLINK_GetMOEs(...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) -- CPU_WriteMem(4 bytes @ 0xE000ED30) returns 0x01 (0002ms, 8246ms total) +T0AC8 4493:356 JLINK_ReadReg(R15 (PC)) returns 0x004036CC (0000ms, 8246ms total) +T0CD0 4493:364 JLINK_ReadReg(R15 (PC)) returns 0x004036CC (0000ms, 8246ms total) +T0CD0 4493:364 JLINK_ReadReg(R13 (SP)) returns 0x2040E4B8 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R0) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R1) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R2) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R3) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R7) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R13 (SP)) returns 0x2040E4B8 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R14) returns 0xFFFFFFFF (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(R15 (PC)) returns 0x004036CC (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(MSP) returns 0x2040E4B8 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8246ms total) +T0CD0 4493:402 JLINK_ReadReg(FPSCR) returns 0x00000000 (0007ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8253ms total) +T0CD0 4493:409 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8253ms total) +T0CD0 4493:470 JLINK_ReadReg(R15 (PC)) returns 0x004036CC (0000ms, 8253ms total) +T0CD0 4493:470 JLINK_GetNumBPUnits(Type = 0xFFFFFF02) returns 0x08 (0000ms, 8253ms total) +T0CD0 4493:470 JLINK_SetBPEx(Addr = 0x004043AC, Type = 0xFFFFFF02) returns 0x00000001 (0000ms, 8253ms total) +T0CD0 4493:470 JLINK_GetBPInfo(BPHandle = 1) returns 0x00 (0000ms, 8253ms total) +T0CD0 4493:470 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0002020) -- CPU_WriteMem(4 bytes @ 0xE0002024) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0008ms, 8261ms total) +T0AC8 4493:478 JLINK_IsHalted() returns FALSE (0001ms, 8262ms total) +T0AC8 4493:503 JLINK_IsHalted() returns TRUE (0006ms, 8267ms total) +T0AC8 4493:509 JLINK_GetMOEs(...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) -- CPU_WriteMem(4 bytes @ 0xE000ED30) returns 0x01 (0002ms, 8263ms total) +T0AC8 4493:511 JLINK_ReadReg(R15 (PC)) returns 0x004043AC (0000ms, 8263ms total) +T0AC8 4493:511 JLINK_GetBPInfo(BPHandle = 1) returns 0x00 (0000ms, 8263ms total) +T0AC8 4493:511 JLINK_ClrBPEx(BPHandle = 0x00000001) returns 0x00 (0000ms, 8263ms total) +T0CD0 4493:518 JLINK_ReadReg(R15 (PC)) returns 0x004043AC (0000ms, 8263ms total) +T0CD0 4493:518 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A8 (0000ms, 8263ms total) +T1BFC 4493:664 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8263ms total) +T1BFC 4493:664 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8264ms total) +T1BFC 4493:665 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8265ms total) +T1BFC 4493:666 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8266ms total) +T1BFC 4493:667 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8267ms total) +T1BFC 4493:668 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8268ms total) +T1BFC 4493:669 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8269ms total) +T1BFC 4493:670 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8270ms total) +T1BFC 4493:671 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8271ms total) +T1BFC 4493:672 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8272ms total) +T1BFC 4493:673 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8273ms total) +T1BFC 4493:674 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8274ms total) +T1BFC 4493:675 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8275ms total) +T1BFC 4493:676 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8276ms total) +T1BFC 4493:677 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8277ms total) +T1BFC 4493:678 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8278ms total) +T1BFC 4493:679 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8279ms total) +T1BFC 4493:680 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8280ms total) +T1BFC 4493:681 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8281ms total) +T1BFC 4493:682 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8282ms total) +T1BFC 4493:683 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8283ms total) +T1BFC 4493:684 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8284ms total) +T1BFC 4493:685 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8285ms total) +T1BFC 4493:686 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8286ms total) +T1BFC 4493:687 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8287ms total) +T1BFC 4493:688 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8288ms total) +T1BFC 4493:689 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8289ms total) +T1BFC 4493:690 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8290ms total) +T1BFC 4493:691 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8291ms total) +T1BFC 4493:692 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8292ms total) +T1BFC 4493:693 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8293ms total) +T1BFC 4493:694 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8294ms total) +T1BFC 4493:695 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8295ms total) +T1BFC 4493:696 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8296ms total) +T1BFC 4493:697 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8297ms total) +T1BFC 4493:698 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8298ms total) +T1BFC 4493:699 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8298ms total) +T1BFC 4493:699 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8299ms total) +T1BFC 4493:700 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8300ms total) +T1BFC 4493:701 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8301ms total) +T1BFC 4493:702 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8302ms total) +T1BFC 4493:703 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8303ms total) +T1BFC 4493:704 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8304ms total) +T1BFC 4493:705 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8305ms total) +T1BFC 4493:706 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8306ms total) +T1BFC 4493:707 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8307ms total) +T1BFC 4493:708 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8308ms total) +T1BFC 4493:709 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8309ms total) +T1BFC 4493:710 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8310ms total) +T0AC8 4493:711 JLINK_IsHalted() returns TRUE (0000ms, 8310ms total) +T1BFC 4493:711 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8311ms total) +T1BFC 4493:712 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8312ms total) +T1BFC 4493:713 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8313ms total) +T1BFC 4493:714 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8314ms total) +T1BFC 4493:715 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8315ms total) +T1BFC 4493:716 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8316ms total) +T1BFC 4493:717 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8317ms total) +T1BFC 4493:718 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8318ms total) +T1BFC 4493:719 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8319ms total) +T1BFC 4493:720 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8320ms total) +T1BFC 4493:721 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8321ms total) +T1BFC 4493:722 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8322ms total) +T1BFC 4493:723 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8323ms total) +T1BFC 4493:724 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8324ms total) +T1BFC 4493:725 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8325ms total) +T1BFC 4493:726 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8326ms total) +T1BFC 4493:727 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8327ms total) +T1BFC 4493:728 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8328ms total) +T1BFC 4493:729 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8329ms total) +T1BFC 4493:730 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8330ms total) +T1BFC 4493:731 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8331ms total) +T1BFC 4493:732 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8332ms total) +T1BFC 4493:733 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8333ms total) +T1BFC 4493:734 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8333ms total) +T1BFC 4493:734 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8334ms total) +T1BFC 4493:735 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8335ms total) +T1BFC 4493:736 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8336ms total) +T1BFC 4493:737 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8337ms total) +T1BFC 4493:738 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8338ms total) +T1BFC 4493:739 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8339ms total) +T1BFC 4493:740 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8340ms total) +T1BFC 4493:741 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8341ms total) +T1BFC 4493:742 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8342ms total) +T1BFC 4493:743 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8343ms total) +T1BFC 4493:744 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8344ms total) +T1BFC 4493:745 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8345ms total) +T1BFC 4493:746 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8346ms total) +T1BFC 4493:747 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8347ms total) +T1BFC 4493:748 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8348ms total) +T1BFC 4493:749 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8349ms total) +T1BFC 4493:750 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8350ms total) +T1BFC 4493:751 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8351ms total) +T1BFC 4493:752 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8352ms total) +T1BFC 4493:753 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8353ms total) +T1BFC 4493:754 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8354ms total) +T1BFC 4493:755 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8355ms total) +T1BFC 4493:756 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8356ms total) +T1BFC 4493:757 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8357ms total) +T1BFC 4493:758 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8358ms total) +T1BFC 4493:759 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8359ms total) +T1BFC 4493:760 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8360ms total) +T1BFC 4493:761 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8361ms total) +T1BFC 4493:762 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8362ms total) +T1BFC 4493:763 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8363ms total) +T1BFC 4493:764 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8364ms total) +T1BFC 4493:765 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8365ms total) +T1BFC 4493:766 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8366ms total) +T1BFC 4493:767 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8367ms total) +T1BFC 4493:768 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8368ms total) +T1BFC 4493:769 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8368ms total) +T1BFC 4493:769 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8369ms total) +T1BFC 4493:770 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8370ms total) +T1BFC 4493:771 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8371ms total) +T1BFC 4493:772 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8372ms total) +T1BFC 4493:773 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8373ms total) +T1BFC 4493:774 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8374ms total) +T1BFC 4493:775 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8375ms total) +T1BFC 4493:776 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8376ms total) +T1BFC 4493:777 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8377ms total) +T1BFC 4493:778 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8378ms total) +T1BFC 4493:779 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8379ms total) +T1BFC 4493:780 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8380ms total) +T1BFC 4493:781 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8381ms total) +T1BFC 4493:782 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8382ms total) +T1BFC 4493:783 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8383ms total) +T1BFC 4493:784 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8384ms total) +T1BFC 4493:785 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8385ms total) +T1BFC 4493:786 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8386ms total) +T1BFC 4493:787 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8387ms total) +T1BFC 4493:788 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8388ms total) +T1BFC 4493:789 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8389ms total) +T1BFC 4493:790 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8390ms total) +T1BFC 4493:791 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8391ms total) +T1BFC 4493:792 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8392ms total) +T1BFC 4493:793 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8393ms total) +T1BFC 4493:794 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8394ms total) +T1BFC 4493:795 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8395ms total) +T1BFC 4493:796 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8396ms total) +T1BFC 4493:797 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8397ms total) +T1BFC 4493:798 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8398ms total) +T1BFC 4493:799 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8399ms total) +T1BFC 4493:800 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8400ms total) +T1BFC 4493:801 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8401ms total) +T1BFC 4493:802 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8402ms total) +T1BFC 4493:803 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8403ms total) +T1BFC 4493:804 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8403ms total) +T1BFC 4493:804 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8404ms total) +T1BFC 4493:805 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8405ms total) +T1BFC 4493:806 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8406ms total) +T1BFC 4493:807 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8407ms total) +T1BFC 4493:808 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8408ms total) +T1BFC 4493:809 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8409ms total) +T1BFC 4493:810 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8410ms total) +T1BFC 4493:811 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8411ms total) +T1BFC 4493:812 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8412ms total) +T1BFC 4493:813 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8413ms total) +T1BFC 4493:814 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8414ms total) +T1BFC 4493:815 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8415ms total) +T1BFC 4493:816 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8416ms total) +T1BFC 4493:817 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8417ms total) +T1BFC 4493:818 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8418ms total) +T1BFC 4493:819 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8419ms total) +T1BFC 4493:820 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8420ms total) +T1BFC 4493:821 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8421ms total) +T1BFC 4493:822 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8422ms total) +T1BFC 4493:823 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8423ms total) +T1BFC 4493:824 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8424ms total) +T1BFC 4493:825 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8425ms total) +T1BFC 4493:826 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8426ms total) +T1BFC 4493:827 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8427ms total) +T1BFC 4493:828 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8428ms total) +T1BFC 4493:829 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8429ms total) +T1BFC 4493:830 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8430ms total) +T1BFC 4493:831 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8431ms total) +T1BFC 4493:832 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8432ms total) +T1BFC 4493:833 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8433ms total) +T1BFC 4493:834 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8434ms total) +T1BFC 4493:835 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8435ms total) +T1BFC 4493:836 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8436ms total) +T1BFC 4493:837 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8437ms total) +T1BFC 4493:838 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8438ms total) +T1BFC 4493:839 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8438ms total) +T1BFC 4493:839 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8439ms total) +T1BFC 4493:840 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8440ms total) +T1BFC 4493:841 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8441ms total) +T1BFC 4493:842 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8442ms total) +T1BFC 4493:843 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8443ms total) +T1BFC 4493:844 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8444ms total) +T1BFC 4493:845 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8445ms total) +T1BFC 4493:846 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8446ms total) +T1BFC 4493:847 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8447ms total) +T1BFC 4493:848 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8448ms total) +T1BFC 4493:849 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8449ms total) +T1BFC 4493:850 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8450ms total) +T1BFC 4493:851 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8451ms total) +T1BFC 4493:852 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8452ms total) +T1BFC 4493:853 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8453ms total) +T1BFC 4493:854 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8454ms total) +T1BFC 4493:855 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8455ms total) +T1BFC 4493:856 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8456ms total) +T1BFC 4493:857 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8457ms total) +T1BFC 4493:858 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8458ms total) +T1BFC 4493:859 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8459ms total) +T1BFC 4493:860 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8460ms total) +T1BFC 4493:861 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8461ms total) +T1BFC 4493:862 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8462ms total) +T1BFC 4493:863 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8463ms total) +T1BFC 4493:864 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8464ms total) +T1BFC 4493:865 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8465ms total) +T1BFC 4493:866 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8466ms total) +T1BFC 4493:867 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8467ms total) +T1BFC 4493:868 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8468ms total) +T1BFC 4493:869 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8469ms total) +T1BFC 4493:870 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8470ms total) +T1BFC 4493:871 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8471ms total) +T1BFC 4493:872 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8472ms total) +T1BFC 4493:873 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8473ms total) +T1BFC 4493:874 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8473ms total) +T1BFC 4493:874 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8474ms total) +T1BFC 4493:875 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8475ms total) +T1BFC 4493:876 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8476ms total) +T1BFC 4493:877 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8477ms total) +T1BFC 4493:878 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8478ms total) +T1BFC 4493:879 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8479ms total) +T1BFC 4493:880 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8480ms total) +T1BFC 4493:881 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8481ms total) +T1BFC 4493:882 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8482ms total) +T1BFC 4493:883 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8483ms total) +T1BFC 4493:884 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8484ms total) +T1BFC 4493:885 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8485ms total) +T1BFC 4493:886 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8486ms total) +T1BFC 4493:887 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8487ms total) +T1BFC 4493:888 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8488ms total) +T1BFC 4493:889 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8489ms total) +T1BFC 4493:890 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8490ms total) +T1BFC 4493:891 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8491ms total) +T1BFC 4493:892 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8492ms total) +T1BFC 4493:893 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8493ms total) +T1BFC 4493:894 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8494ms total) +T1BFC 4493:895 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8495ms total) +T1BFC 4493:896 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8496ms total) +T1BFC 4493:897 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8497ms total) +T1BFC 4493:898 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8498ms total) +T1BFC 4493:899 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8499ms total) +T1BFC 4493:900 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8500ms total) +T1BFC 4493:901 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8501ms total) +T1BFC 4493:902 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8502ms total) +T1BFC 4493:903 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8503ms total) +T1BFC 4493:904 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8504ms total) +T1BFC 4493:905 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8505ms total) +T1BFC 4493:906 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8506ms total) +T1BFC 4493:907 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8507ms total) +T1BFC 4493:908 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8508ms total) +T1BFC 4493:909 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8508ms total) +T1BFC 4493:909 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8509ms total) +T1BFC 4493:910 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8510ms total) +T0AC8 4493:911 JLINK_IsHalted() returns TRUE (0000ms, 8510ms total) +T1BFC 4493:911 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8511ms total) +T1BFC 4493:912 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8512ms total) +T1BFC 4493:913 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8513ms total) +T1BFC 4493:914 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8514ms total) +T1BFC 4493:915 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8515ms total) +T1BFC 4493:916 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8516ms total) +T1BFC 4493:917 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8517ms total) +T1BFC 4493:918 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8518ms total) +T1BFC 4493:919 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8519ms total) +T1BFC 4493:920 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8520ms total) +T1BFC 4493:921 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8521ms total) +T1BFC 4493:922 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8522ms total) +T1BFC 4493:923 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8523ms total) +T1BFC 4493:924 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8524ms total) +T1BFC 4493:925 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8525ms total) +T1BFC 4493:926 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8526ms total) +T1BFC 4493:927 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8527ms total) +T1BFC 4493:928 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8528ms total) +T1BFC 4493:929 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8529ms total) +T1BFC 4493:930 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8530ms total) +T1BFC 4493:931 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8531ms total) +T1BFC 4493:932 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8532ms total) +T1BFC 4493:933 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8533ms total) +T1BFC 4493:934 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8534ms total) +T1BFC 4493:935 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8535ms total) +T1BFC 4493:936 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8536ms total) +T1BFC 4493:937 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8537ms total) +T1BFC 4493:938 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8538ms total) +T1BFC 4493:939 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8539ms total) +T1BFC 4493:940 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8540ms total) +T1BFC 4493:941 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8541ms total) +T1BFC 4493:942 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8542ms total) +T1BFC 4493:943 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8543ms total) +T1BFC 4493:944 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8543ms total) +T1BFC 4493:944 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8544ms total) +T1BFC 4493:945 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8545ms total) +T1BFC 4493:946 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8546ms total) +T1BFC 4493:947 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8547ms total) +T1BFC 4493:948 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8548ms total) +T1BFC 4493:949 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8549ms total) +T1BFC 4493:950 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8550ms total) +T1BFC 4493:951 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8551ms total) +T1BFC 4493:952 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8552ms total) +T1BFC 4493:953 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8553ms total) +T1BFC 4493:954 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8554ms total) +T1BFC 4493:955 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8555ms total) +T1BFC 4493:956 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8556ms total) +T1BFC 4493:957 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8557ms total) +T1BFC 4493:958 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8558ms total) +T1BFC 4493:959 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8559ms total) +T1BFC 4493:960 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8560ms total) +T1BFC 4493:961 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8561ms total) +T1BFC 4493:962 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8562ms total) +T1BFC 4493:963 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8563ms total) +T1BFC 4493:964 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8564ms total) +T1BFC 4493:965 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8565ms total) +T1BFC 4493:966 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8566ms total) +T1BFC 4493:967 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8567ms total) +T1BFC 4493:968 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8568ms total) +T1BFC 4493:969 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8569ms total) +T1BFC 4493:970 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8570ms total) +T1BFC 4493:971 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8571ms total) +T1BFC 4493:972 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8572ms total) +T1BFC 4493:973 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8573ms total) +T1BFC 4493:974 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8574ms total) +T1BFC 4493:975 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8575ms total) +T1BFC 4493:976 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8576ms total) +T1BFC 4493:977 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8577ms total) +T1BFC 4493:978 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8578ms total) +T1BFC 4493:979 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8578ms total) +T1BFC 4493:979 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8579ms total) +T1BFC 4493:980 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8580ms total) +T1BFC 4493:981 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8581ms total) +T1BFC 4493:982 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8582ms total) +T1BFC 4493:983 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8583ms total) +T1BFC 4493:984 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8584ms total) +T1BFC 4493:985 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8585ms total) +T1BFC 4493:986 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8586ms total) +T1BFC 4493:987 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8587ms total) +T1BFC 4493:988 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8588ms total) +T1BFC 4493:989 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8589ms total) +T1BFC 4493:990 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8590ms total) +T1BFC 4493:991 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8591ms total) +T1BFC 4493:992 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8592ms total) +T1BFC 4493:993 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8593ms total) +T1BFC 4493:994 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8594ms total) +T1BFC 4493:995 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8595ms total) +T1BFC 4493:996 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8596ms total) +T1BFC 4493:997 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8597ms total) +T1BFC 4493:998 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8598ms total) +T1BFC 4493:999 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8599ms total) +T1BFC 4494:000 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8600ms total) +T1BFC 4494:001 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8601ms total) +T1BFC 4494:002 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8602ms total) +T1BFC 4494:003 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8603ms total) +T1BFC 4494:004 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8604ms total) +T1BFC 4494:005 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8605ms total) +T1BFC 4494:006 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8606ms total) +T1BFC 4494:007 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8607ms total) +T1BFC 4494:008 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8608ms total) +T1BFC 4494:009 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8609ms total) +T1BFC 4494:010 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8610ms total) +T1BFC 4494:011 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8611ms total) +T1BFC 4494:012 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8612ms total) +T1BFC 4494:013 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8613ms total) +T1BFC 4494:069 JLINK_ReadReg(R0) returns 0x0040AE98 (0001ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R1) returns 0x13010027 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R3) returns 0x004043AD (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R7) returns 0x2040E4A8 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A8 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R14) returns 0x0040373F (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(R15 (PC)) returns 0x004043AC (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(MSP) returns 0x2040E4A8 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8614ms total) +T1BFC 4494:070 JLINK_ReadReg(FPSCR) returns 0x00000000 (0006ms, 8620ms total) +T1BFC 4494:076 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8620ms total) +T1BFC 4494:076 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8620ms total) +T1BFC 4494:076 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8620ms total) +T1BFC 4494:076 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8620ms total) +T1BFC 4494:076 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8620ms total) +T1BFC 4494:076 JLINK_ReadReg(FPS5) returns 0x00000000 (0001ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8621ms total) +T1BFC 4494:077 JLINK_ReadReg(CycleCnt) -- CPU_ReadMem(4 bytes @ 0xE0001004) returns 0x0004C082 (0000ms, 8621ms total) +T0AC8 4494:111 JLINK_IsHalted() returns TRUE (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R0) returns 0x0040AE98 (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R1) returns 0x13010027 (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R3) returns 0x004043AD (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8621ms total) +T1BFC 4494:131 JLINK_ReadReg(R7) returns 0x2040E4A8 (0001ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A8 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R14) returns 0x0040373F (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(R15 (PC)) returns 0x004043AC (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(MSP) returns 0x2040E4A8 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8622ms total) +T1BFC 4494:132 JLINK_ReadReg(CycleCnt) returns 0x0004C082 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R0) returns 0x0040AE98 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R1) returns 0x13010027 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R3) returns 0x004043AD (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R7) returns 0x2040E4A8 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A8 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R14) returns 0x0040373F (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(R15 (PC)) returns 0x004043AC (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(MSP) returns 0x2040E4A8 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8622ms total) +T1BFC 4494:183 JLINK_ReadReg(FPS21) returns 0x00000000 (0001ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8623ms total) +T1BFC 4494:184 JLINK_ReadReg(CycleCnt) returns 0x0004C082 (0000ms, 8623ms total) +T0AC8 4494:313 JLINK_IsHalted() returns TRUE (0000ms, 8623ms total) +T0CD0 4494:349 JLINK_ReadMem (0x2040C428, 0x0004 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x2040C400) -- Updating C cache (64 bytes @ 0x2040C400) -- Read from C cache (4 bytes @ 0x2040C428) - Data: 00 00 00 00 returns 0x00 (0001ms, 8624ms total) +T0AC8 4494:513 JLINK_IsHalted() returns TRUE (0001ms, 8625ms total) +T0AC8 4494:714 JLINK_IsHalted() returns TRUE (0001ms, 8625ms total) +T0AC8 4494:915 JLINK_IsHalted() returns TRUE (0000ms, 8624ms total) +T0AC8 4495:115 JLINK_IsHalted() returns TRUE (0000ms, 8624ms total) +T0AC8 4495:315 JLINK_IsHalted() returns TRUE (0001ms, 8625ms total) +T0AC8 4495:516 JLINK_IsHalted() returns TRUE (0000ms, 8624ms total) +T0AC8 4495:716 JLINK_IsHalted() returns TRUE (0000ms, 8624ms total) +T0AC8 4495:916 JLINK_IsHalted() returns TRUE (0001ms, 8625ms total) +T0AC8 4496:117 JLINK_IsHalted() returns TRUE (0000ms, 8624ms total) +T0CD0 4496:220 JLINK_ReadReg(R15 (PC)) returns 0x004043AC (0001ms, 8625ms total) +T0CD0 4496:221 JLINK_Step() -- Read from flash cache (2 bytes @ 0x004043AC) -- CPU_WriteMem(8 bytes @ 0x2040E4A0) -- Simulated returns 0x00 (0001ms, 8626ms total) +T0AC8 4496:222 JLINK_IsHalted() returns TRUE (0000ms, 8626ms total) +T0AC8 4496:222 JLINK_GetMOEs(...) returns 0x01 (0000ms, 8626ms total) +T0AC8 4496:222 JLINK_ReadReg(R15 (PC)) returns 0x004043AE (0000ms, 8626ms total) +T0CD0 4496:232 JLINK_ReadReg(R15 (PC)) returns 0x004043AE (0000ms, 8626ms total) +T0CD0 4496:232 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8626ms total) +T0CD0 4496:233 JLINK_ReadReg(R15 (PC)) returns 0x004043AE (0000ms, 8626ms total) +T0CD0 4496:234 JLINK_Step() -- Read from flash cache (2 bytes @ 0x004043AE) -- Simulated returns 0x00 (0000ms, 8626ms total) +T0AC8 4496:236 JLINK_IsHalted() returns TRUE (0001ms, 8627ms total) +T0AC8 4496:237 JLINK_GetMOEs(...) returns 0x01 (0000ms, 8626ms total) +T0AC8 4496:237 JLINK_ReadReg(R15 (PC)) returns 0x004043B0 (0000ms, 8626ms total) +T0CD0 4496:244 JLINK_ReadReg(R15 (PC)) returns 0x004043B0 (0000ms, 8626ms total) +T0CD0 4496:244 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8626ms total) +T0CD0 4496:245 JLINK_ReadReg(R0) returns 0x0040AE98 (0000ms, 8626ms total) +T0CD0 4496:245 JLINK_ReadReg(R1) returns 0x13010027 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R3) returns 0x004043AD (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R14) returns 0x0040373F (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(R15 (PC)) returns 0x004043B0 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8626ms total) +T0CD0 4496:246 JLINK_ReadReg(FPS0) returns 0x00000000 (0001ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:247 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:248 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:248 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:248 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:248 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:248 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8627ms total) +T0CD0 4496:248 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8627ms total) +T1BFC 4496:277 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8627ms total) +T1BFC 4496:277 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8628ms total) +T1BFC 4496:278 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8629ms total) +T1BFC 4496:279 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8630ms total) +T1BFC 4496:280 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8631ms total) +T1BFC 4496:281 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8632ms total) +T1BFC 4496:282 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8633ms total) +T1BFC 4496:283 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8634ms total) +T1BFC 4496:284 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 8636ms total) +T1BFC 4496:286 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8637ms total) +T1BFC 4496:287 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8638ms total) +T1BFC 4496:288 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8639ms total) +T1BFC 4496:289 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8640ms total) +T1BFC 4496:290 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8641ms total) +T1BFC 4496:291 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8642ms total) +T1BFC 4496:292 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8643ms total) +T1BFC 4496:293 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8644ms total) +T1BFC 4496:295 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8645ms total) +T1BFC 4496:296 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8646ms total) +T1BFC 4496:297 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8647ms total) +T1BFC 4496:298 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8648ms total) +T1BFC 4496:299 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8649ms total) +T1BFC 4496:300 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8650ms total) +T1BFC 4496:301 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8651ms total) +T1BFC 4496:302 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8652ms total) +T1BFC 4496:303 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8653ms total) +T1BFC 4496:304 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8654ms total) +T1BFC 4496:305 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8655ms total) +T1BFC 4496:306 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8656ms total) +T1BFC 4496:307 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8657ms total) +T1BFC 4496:308 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8658ms total) +T1BFC 4496:309 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8659ms total) +T1BFC 4496:310 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8660ms total) +T1BFC 4496:311 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8661ms total) +T1BFC 4496:312 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8662ms total) +T1BFC 4496:313 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8663ms total) +T1BFC 4496:314 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8663ms total) +T1BFC 4496:314 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8664ms total) +T1BFC 4496:315 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8665ms total) +T1BFC 4496:316 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8666ms total) +T1BFC 4496:317 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8667ms total) +T1BFC 4496:318 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8668ms total) +T1BFC 4496:319 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8669ms total) +T1BFC 4496:320 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8670ms total) +T1BFC 4496:321 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8671ms total) +T1BFC 4496:322 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8672ms total) +T1BFC 4496:323 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8673ms total) +T1BFC 4496:324 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8674ms total) +T1BFC 4496:325 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8675ms total) +T1BFC 4496:326 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8676ms total) +T1BFC 4496:327 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8677ms total) +T1BFC 4496:328 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8678ms total) +T1BFC 4496:329 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8679ms total) +T1BFC 4496:330 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8680ms total) +T1BFC 4496:331 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8681ms total) +T1BFC 4496:332 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8682ms total) +T1BFC 4496:333 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8683ms total) +T1BFC 4496:334 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8684ms total) +T1BFC 4496:335 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8685ms total) +T1BFC 4496:336 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8686ms total) +T1BFC 4496:337 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8687ms total) +T1BFC 4496:338 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8688ms total) +T1BFC 4496:339 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8689ms total) +T1BFC 4496:340 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8690ms total) +T1BFC 4496:341 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8691ms total) +T1BFC 4496:342 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8692ms total) +T1BFC 4496:343 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8693ms total) +T1BFC 4496:344 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8694ms total) +T1BFC 4496:345 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8695ms total) +T1BFC 4496:346 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8696ms total) +T1BFC 4496:347 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8697ms total) +T1BFC 4496:348 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8698ms total) +T1BFC 4496:349 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8698ms total) +T1BFC 4496:349 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8699ms total) +T1BFC 4496:350 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8700ms total) +T1BFC 4496:351 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8701ms total) +T1BFC 4496:352 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8702ms total) +T1BFC 4496:353 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8703ms total) +T1BFC 4496:354 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8704ms total) +T1BFC 4496:355 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8705ms total) +T1BFC 4496:356 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8706ms total) +T1BFC 4496:357 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8707ms total) +T1BFC 4496:358 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8708ms total) +T1BFC 4496:359 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8709ms total) +T1BFC 4496:360 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8710ms total) +T1BFC 4496:361 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8711ms total) +T1BFC 4496:362 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8712ms total) +T1BFC 4496:363 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8713ms total) +T1BFC 4496:364 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8714ms total) +T1BFC 4496:365 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8715ms total) +T1BFC 4496:366 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8716ms total) +T1BFC 4496:367 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8717ms total) +T1BFC 4496:368 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8718ms total) +T1BFC 4496:369 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8719ms total) +T1BFC 4496:370 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8720ms total) +T1BFC 4496:371 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8721ms total) +T1BFC 4496:372 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8722ms total) +T1BFC 4496:373 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8723ms total) +T1BFC 4496:374 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8724ms total) +T1BFC 4496:375 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8725ms total) +T1BFC 4496:376 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8726ms total) +T1BFC 4496:377 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8727ms total) +T1BFC 4496:378 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8728ms total) +T1BFC 4496:379 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8729ms total) +T1BFC 4496:380 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8730ms total) +T1BFC 4496:381 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8731ms total) +T1BFC 4496:382 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8732ms total) +T1BFC 4496:383 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8733ms total) +T1BFC 4496:384 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8733ms total) +T1BFC 4496:384 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8734ms total) +T1BFC 4496:385 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8735ms total) +T1BFC 4496:386 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8736ms total) +T1BFC 4496:387 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8737ms total) +T1BFC 4496:388 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8738ms total) +T1BFC 4496:389 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8739ms total) +T1BFC 4496:390 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8740ms total) +T1BFC 4496:391 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8741ms total) +T1BFC 4496:392 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8742ms total) +T1BFC 4496:393 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8743ms total) +T1BFC 4496:394 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8744ms total) +T1BFC 4496:395 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8745ms total) +T1BFC 4496:396 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8746ms total) +T1BFC 4496:397 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8747ms total) +T1BFC 4496:398 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8748ms total) +T1BFC 4496:399 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8749ms total) +T1BFC 4496:400 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8750ms total) +T1BFC 4496:401 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8751ms total) +T1BFC 4496:402 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8752ms total) +T1BFC 4496:403 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8753ms total) +T1BFC 4496:404 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8754ms total) +T1BFC 4496:405 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8755ms total) +T1BFC 4496:406 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8756ms total) +T1BFC 4496:407 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8757ms total) +T1BFC 4496:408 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8758ms total) +T1BFC 4496:409 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8759ms total) +T1BFC 4496:410 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8760ms total) +T1BFC 4496:411 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8761ms total) +T1BFC 4496:412 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8762ms total) +T1BFC 4496:413 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8763ms total) +T1BFC 4496:414 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8764ms total) +T1BFC 4496:415 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8765ms total) +T1BFC 4496:416 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8766ms total) +T1BFC 4496:417 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8767ms total) +T1BFC 4496:418 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8768ms total) +T1BFC 4496:419 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8768ms total) +T1BFC 4496:419 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8769ms total) +T1BFC 4496:420 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8770ms total) +T1BFC 4496:421 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8771ms total) +T1BFC 4496:422 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8772ms total) +T1BFC 4496:423 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8773ms total) +T1BFC 4496:424 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8774ms total) +T1BFC 4496:425 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8775ms total) +T1BFC 4496:426 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8776ms total) +T1BFC 4496:427 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8777ms total) +T1BFC 4496:428 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8778ms total) +T1BFC 4496:429 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8779ms total) +T1BFC 4496:430 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8780ms total) +T1BFC 4496:431 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8781ms total) +T1BFC 4496:432 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8782ms total) +T1BFC 4496:433 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8783ms total) +T1BFC 4496:434 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8784ms total) +T1BFC 4496:435 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8785ms total) +T1BFC 4496:436 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8786ms total) +T0AC8 4496:437 JLINK_IsHalted() returns TRUE (0001ms, 8787ms total) +T1BFC 4496:438 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8788ms total) +T1BFC 4496:439 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8789ms total) +T1BFC 4496:440 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8790ms total) +T1BFC 4496:441 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8791ms total) +T1BFC 4496:442 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8792ms total) +T1BFC 4496:443 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8793ms total) +T1BFC 4496:444 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8794ms total) +T1BFC 4496:445 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8795ms total) +T1BFC 4496:446 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8796ms total) +T1BFC 4496:447 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8797ms total) +T1BFC 4496:448 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8798ms total) +T1BFC 4496:449 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8799ms total) +T1BFC 4496:450 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8800ms total) +T1BFC 4496:451 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8801ms total) +T1BFC 4496:452 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8802ms total) +T1BFC 4496:453 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8803ms total) +T1BFC 4496:454 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8804ms total) +T1BFC 4496:455 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8804ms total) +T1BFC 4496:455 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8805ms total) +T1BFC 4496:456 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8806ms total) +T1BFC 4496:457 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8807ms total) +T1BFC 4496:458 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8808ms total) +T1BFC 4496:459 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8809ms total) +T1BFC 4496:460 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8810ms total) +T1BFC 4496:461 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8811ms total) +T1BFC 4496:462 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8812ms total) +T1BFC 4496:463 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8813ms total) +T1BFC 4496:464 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8814ms total) +T1BFC 4496:465 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8815ms total) +T1BFC 4496:466 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8816ms total) +T1BFC 4496:467 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8817ms total) +T1BFC 4496:468 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8818ms total) +T1BFC 4496:469 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8819ms total) +T1BFC 4496:470 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8820ms total) +T1BFC 4496:471 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8821ms total) +T1BFC 4496:472 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8822ms total) +T1BFC 4496:473 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8823ms total) +T1BFC 4496:474 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8824ms total) +T1BFC 4496:475 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8825ms total) +T1BFC 4496:476 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8826ms total) +T1BFC 4496:477 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8827ms total) +T1BFC 4496:478 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8828ms total) +T1BFC 4496:479 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8829ms total) +T1BFC 4496:480 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8830ms total) +T1BFC 4496:481 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8831ms total) +T1BFC 4496:482 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8832ms total) +T1BFC 4496:483 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8833ms total) +T1BFC 4496:484 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8834ms total) +T1BFC 4496:485 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8835ms total) +T1BFC 4496:486 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8836ms total) +T1BFC 4496:487 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8837ms total) +T1BFC 4496:488 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8838ms total) +T1BFC 4496:489 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8839ms total) +T1BFC 4496:490 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8839ms total) +T1BFC 4496:490 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8840ms total) +T1BFC 4496:491 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8841ms total) +T1BFC 4496:492 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8842ms total) +T1BFC 4496:493 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8843ms total) +T1BFC 4496:494 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8844ms total) +T1BFC 4496:495 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8845ms total) +T1BFC 4496:496 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8846ms total) +T1BFC 4496:497 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8847ms total) +T1BFC 4496:498 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8848ms total) +T1BFC 4496:499 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8849ms total) +T1BFC 4496:500 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8850ms total) +T1BFC 4496:501 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8851ms total) +T1BFC 4496:502 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8852ms total) +T1BFC 4496:503 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8853ms total) +T1BFC 4496:504 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8854ms total) +T1BFC 4496:505 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8855ms total) +T1BFC 4496:506 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8856ms total) +T1BFC 4496:507 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8857ms total) +T1BFC 4496:508 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8858ms total) +T1BFC 4496:509 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8859ms total) +T1BFC 4496:510 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8860ms total) +T1BFC 4496:511 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8861ms total) +T1BFC 4496:512 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8862ms total) +T1BFC 4496:513 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8863ms total) +T1BFC 4496:514 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8864ms total) +T1BFC 4496:515 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8865ms total) +T1BFC 4496:516 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8866ms total) +T1BFC 4496:517 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0002ms, 8868ms total) +T1BFC 4496:519 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8869ms total) +T1BFC 4496:520 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8870ms total) +T1BFC 4496:521 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8871ms total) +T1BFC 4496:522 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8872ms total) +T1BFC 4496:523 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8873ms total) +T1BFC 4496:524 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8874ms total) +T1BFC 4496:525 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8875ms total) +T1BFC 4496:526 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8875ms total) +T1BFC 4496:526 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8876ms total) +T1BFC 4496:527 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8877ms total) +T1BFC 4496:528 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8878ms total) +T1BFC 4496:529 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8879ms total) +T1BFC 4496:530 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8880ms total) +T1BFC 4496:531 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8881ms total) +T1BFC 4496:532 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8882ms total) +T1BFC 4496:533 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8883ms total) +T1BFC 4496:534 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8884ms total) +T1BFC 4496:535 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8885ms total) +T1BFC 4496:536 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8886ms total) +T1BFC 4496:537 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8887ms total) +T1BFC 4496:538 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8888ms total) +T1BFC 4496:539 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8889ms total) +T1BFC 4496:540 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8890ms total) +T1BFC 4496:541 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8891ms total) +T1BFC 4496:542 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8892ms total) +T1BFC 4496:543 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8893ms total) +T1BFC 4496:544 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8894ms total) +T1BFC 4496:545 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8895ms total) +T1BFC 4496:546 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8896ms total) +T1BFC 4496:547 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8897ms total) +T1BFC 4496:548 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8898ms total) +T1BFC 4496:549 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8899ms total) +T1BFC 4496:550 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8900ms total) +T1BFC 4496:551 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8901ms total) +T1BFC 4496:552 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8902ms total) +T1BFC 4496:553 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8903ms total) +T1BFC 4496:554 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8904ms total) +T1BFC 4496:555 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8905ms total) +T1BFC 4496:556 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8906ms total) +T1BFC 4496:557 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8907ms total) +T1BFC 4496:558 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8908ms total) +T1BFC 4496:559 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8909ms total) +T1BFC 4496:560 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8910ms total) +T1BFC 4496:561 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8910ms total) +T1BFC 4496:561 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8911ms total) +T1BFC 4496:562 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8912ms total) +T1BFC 4496:563 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8913ms total) +T1BFC 4496:564 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8914ms total) +T1BFC 4496:565 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8915ms total) +T1BFC 4496:566 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8916ms total) +T1BFC 4496:567 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8917ms total) +T1BFC 4496:568 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8918ms total) +T1BFC 4496:569 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8919ms total) +T1BFC 4496:570 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8920ms total) +T1BFC 4496:571 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8921ms total) +T1BFC 4496:572 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8922ms total) +T1BFC 4496:573 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8923ms total) +T1BFC 4496:574 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8924ms total) +T1BFC 4496:575 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8925ms total) +T1BFC 4496:576 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8926ms total) +T1BFC 4496:577 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8927ms total) +T1BFC 4496:578 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8928ms total) +T1BFC 4496:579 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8929ms total) +T1BFC 4496:580 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8930ms total) +T1BFC 4496:581 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8931ms total) +T1BFC 4496:582 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8932ms total) +T1BFC 4496:583 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8933ms total) +T1BFC 4496:584 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8934ms total) +T1BFC 4496:585 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8935ms total) +T1BFC 4496:586 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8936ms total) +T1BFC 4496:587 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8937ms total) +T1BFC 4496:588 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8938ms total) +T1BFC 4496:589 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8939ms total) +T1BFC 4496:590 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8940ms total) +T1BFC 4496:591 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8941ms total) +T1BFC 4496:592 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8942ms total) +T1BFC 4496:593 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8943ms total) +T1BFC 4496:594 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8944ms total) +T1BFC 4496:595 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8945ms total) +T1BFC 4496:596 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 8945ms total) +T1BFC 4496:596 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8946ms total) +T1BFC 4496:597 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8947ms total) +T1BFC 4496:598 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8948ms total) +T1BFC 4496:599 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8949ms total) +T1BFC 4496:600 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8950ms total) +T1BFC 4496:601 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 8951ms total) +T1BFC 4496:602 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8952ms total) +T1BFC 4496:603 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8953ms total) +T1BFC 4496:604 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 8954ms total) +T1BFC 4496:605 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8955ms total) +T1BFC 4496:606 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8956ms total) +T1BFC 4496:607 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 8957ms total) +T1BFC 4496:608 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8958ms total) +T1BFC 4496:609 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8959ms total) +T1BFC 4496:610 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 8960ms total) +T1BFC 4496:611 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8961ms total) +T1BFC 4496:612 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8962ms total) +T1BFC 4496:613 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 8963ms total) +T1BFC 4496:614 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8964ms total) +T1BFC 4496:615 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8965ms total) +T1BFC 4496:616 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 8966ms total) +T1BFC 4496:617 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 8967ms total) +T1BFC 4496:618 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 8968ms total) +T1BFC 4496:619 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8969ms total) +T1BFC 4496:620 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8970ms total) +T1BFC 4496:621 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0003ms, 8973ms total) +T1BFC 4496:624 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 8974ms total) +T1BFC 4496:625 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 8975ms total) +T1BFC 4496:626 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8976ms total) +T1BFC 4496:627 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 8977ms total) +T1BFC 4496:628 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 8978ms total) +T1BFC 4496:629 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 8979ms total) +T1BFC 4496:630 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8980ms total) +T1BFC 4496:631 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 8981ms total) +T1BFC 4496:632 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 8982ms total) +T0AC8 4496:638 JLINK_IsHalted() returns TRUE (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R0) returns 0x0040AE98 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R1) returns 0x13010027 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R3) returns 0x004043AD (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R14) returns 0x0040373F (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(R15 (PC)) returns 0x004043B0 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:707 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8982ms total) +T1BFC 4496:708 JLINK_ReadReg(CycleCnt) returns 0x0004C086 (0000ms, 8982ms total) +T0CD0 4496:730 JLINK_ReadMem (0x2040C428, 0x0004 Bytes, ...) -- Read from C cache (4 bytes @ 0x2040C428) - Data: 00 00 00 00 returns 0x00 (0000ms, 8982ms total) +T0AC8 4496:838 JLINK_IsHalted() returns TRUE (0000ms, 8982ms total) +T0AC8 4497:038 JLINK_IsHalted() returns TRUE (0001ms, 8983ms total) +T0CD0 4497:202 JLINK_ReadReg(R15 (PC)) returns 0x004043B0 (0000ms, 8982ms total) +T0CD0 4497:203 JLINK_Step() -- Read from flash cache (2 bytes @ 0x004043B0) -- Read from flash cache (4 bytes @ 0x004043C0) -- Simulated returns 0x00 (0000ms, 8982ms total) +T0AC8 4497:203 JLINK_IsHalted() returns TRUE (0000ms, 8982ms total) +T0AC8 4497:203 JLINK_GetMOEs(...) returns 0x01 (0000ms, 8982ms total) +T0AC8 4497:203 JLINK_ReadReg(R15 (PC)) returns 0x004043B2 (0000ms, 8982ms total) +T0CD0 4497:213 JLINK_ReadReg(R15 (PC)) returns 0x004043B2 (0000ms, 8982ms total) +T0CD0 4497:213 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R0) returns 0x0040AE98 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R1) returns 0x13010027 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R3) returns 0x004043C9 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R14) returns 0x0040373F (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(R15 (PC)) returns 0x004043B2 (0000ms, 8982ms total) +T0CD0 4497:214 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8982ms total) +T0CD0 4497:215 JLINK_ReadReg(FPS12) returns 0x00000000 (0001ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8983ms total) +T0CD0 4497:216 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8983ms total) +T0CD0 4497:217 JLINK_ReadReg(R15 (PC)) returns 0x004043B2 (0000ms, 8983ms total) +T0CD0 4497:217 JLINK_Step() -- Read from flash cache (2 bytes @ 0x004043B2) -- Simulated returns 0x00 (0001ms, 8984ms total) +T0AC8 4497:218 JLINK_IsHalted() returns TRUE (0000ms, 8984ms total) +T0AC8 4497:218 JLINK_GetMOEs(...) returns 0x01 (0000ms, 8984ms total) +T0AC8 4497:218 JLINK_ReadReg(R15 (PC)) returns 0x004043C8 (0000ms, 8984ms total) +T0CD0 4497:228 JLINK_ReadReg(R15 (PC)) returns 0x004043C8 (0000ms, 8984ms total) +T0CD0 4497:228 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8984ms total) +T0CD0 4497:229 JLINK_ReadReg(R0) returns 0x0040AE98 (0000ms, 8984ms total) +T0CD0 4497:229 JLINK_ReadReg(R1) returns 0x13010027 (0001ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R2) returns 0x00000005 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R3) returns 0x004043C9 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R14) returns 0x004043B5 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(R15 (PC)) returns 0x004043C8 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(XPSR) returns 0x61000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(APSR) returns 0x60000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:230 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8985ms total) +T0CD0 4497:231 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 8986ms total) +T0CD0 4497:231 JLINK_ReadReg(FPS24) returns 0x00000000 (0001ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 8987ms total) +T0CD0 4497:232 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 8987ms total) +T0CD0 4497:233 JLINK_ReadReg(R15 (PC)) returns 0x004043C8 (0000ms, 8987ms total) +T0CD0 4497:233 JLINK_SetBPEx(Addr = 0x004043B4, Type = 0xFFFFFF02) returns 0x00000002 (0000ms, 8987ms total) +T0CD0 4497:233 JLINK_GetBPInfo(BPHandle = 2) returns 0x00 (0000ms, 8987ms total) +T0CD0 4497:235 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0008ms, 8995ms total) +T0AC8 4497:243 JLINK_IsHalted() returns TRUE (0004ms, 8999ms total) +T0AC8 4497:247 JLINK_GetMOEs(...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) -- CPU_WriteMem(4 bytes @ 0xE000ED30) returns 0x01 (0002ms, 8997ms total) +T0AC8 4497:249 JLINK_ReadReg(R15 (PC)) returns 0x004043B4 (0000ms, 8997ms total) +T0AC8 4497:249 JLINK_GetBPInfo(BPHandle = 2) returns 0x00 (0000ms, 8997ms total) +T0AC8 4497:249 JLINK_ClrBPEx(BPHandle = 0x00000002) returns 0x00 (0000ms, 8997ms total) +T0CD0 4497:253 JLINK_ReadReg(R15 (PC)) returns 0x004043B4 (0000ms, 8997ms total) +T0CD0 4497:253 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R1) returns 0x00000200 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R2) returns 0x00000200 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R3) returns 0x00000001 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 8997ms total) +T0CD0 4497:254 JLINK_ReadReg(R14) returns 0x0040417D (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(R15 (PC)) returns 0x004043B4 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 8997ms total) +T0CD0 4497:255 JLINK_ReadReg(FPSCR) returns 0x00000000 (0006ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 9003ms total) +T0CD0 4497:262 JLINK_ReadReg(FPS26) returns 0x00000000 (0001ms, 9004ms total) +T0CD0 4497:263 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 9004ms total) +T0CD0 4497:263 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 9004ms total) +T0CD0 4497:263 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 9004ms total) +T0CD0 4497:263 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 9004ms total) +T0CD0 4497:263 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 9004ms total) +T1BFC 4497:306 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9004ms total) +T1BFC 4497:306 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9005ms total) +T1BFC 4497:307 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9006ms total) +T1BFC 4497:308 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9007ms total) +T1BFC 4497:309 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9008ms total) +T1BFC 4497:310 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9009ms total) +T1BFC 4497:311 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9010ms total) +T1BFC 4497:312 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9011ms total) +T1BFC 4497:313 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9012ms total) +T1BFC 4497:314 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9013ms total) +T1BFC 4497:315 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9014ms total) +T1BFC 4497:316 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9015ms total) +T1BFC 4497:317 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9016ms total) +T1BFC 4497:318 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9017ms total) +T1BFC 4497:319 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9018ms total) +T1BFC 4497:320 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9019ms total) +T1BFC 4497:321 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9020ms total) +T1BFC 4497:323 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9021ms total) +T1BFC 4497:324 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9022ms total) +T1BFC 4497:325 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9023ms total) +T1BFC 4497:326 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9024ms total) +T1BFC 4497:327 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9025ms total) +T1BFC 4497:328 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9026ms total) +T1BFC 4497:329 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9027ms total) +T1BFC 4497:330 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9028ms total) +T1BFC 4497:331 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9029ms total) +T1BFC 4497:332 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9030ms total) +T1BFC 4497:333 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9031ms total) +T1BFC 4497:334 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9032ms total) +T1BFC 4497:335 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9033ms total) +T1BFC 4497:336 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9034ms total) +T1BFC 4497:337 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9035ms total) +T1BFC 4497:338 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9036ms total) +T1BFC 4497:339 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9037ms total) +T1BFC 4497:340 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9038ms total) +T1BFC 4497:341 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9039ms total) +T1BFC 4497:342 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9039ms total) +T1BFC 4497:342 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9040ms total) +T1BFC 4497:343 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9041ms total) +T1BFC 4497:344 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9042ms total) +T1BFC 4497:345 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9043ms total) +T1BFC 4497:346 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9044ms total) +T1BFC 4497:347 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9045ms total) +T1BFC 4497:348 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9046ms total) +T1BFC 4497:349 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9047ms total) +T1BFC 4497:350 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9048ms total) +T1BFC 4497:351 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9049ms total) +T1BFC 4497:352 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9050ms total) +T1BFC 4497:353 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9051ms total) +T1BFC 4497:354 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9052ms total) +T1BFC 4497:355 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9053ms total) +T1BFC 4497:356 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9054ms total) +T1BFC 4497:357 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9055ms total) +T1BFC 4497:358 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9056ms total) +T1BFC 4497:359 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9057ms total) +T1BFC 4497:360 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9058ms total) +T1BFC 4497:361 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9059ms total) +T1BFC 4497:362 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9060ms total) +T1BFC 4497:363 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9061ms total) +T1BFC 4497:364 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9062ms total) +T1BFC 4497:365 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9063ms total) +T1BFC 4497:366 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9064ms total) +T1BFC 4497:367 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9065ms total) +T1BFC 4497:368 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9066ms total) +T1BFC 4497:369 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9067ms total) +T1BFC 4497:370 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9068ms total) +T1BFC 4497:371 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9069ms total) +T1BFC 4497:372 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9070ms total) +T1BFC 4497:373 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9071ms total) +T1BFC 4497:374 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9072ms total) +T1BFC 4497:375 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9073ms total) +T1BFC 4497:376 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9074ms total) +T1BFC 4497:377 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9074ms total) +T1BFC 4497:377 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9075ms total) +T1BFC 4497:378 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9076ms total) +T1BFC 4497:379 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9077ms total) +T1BFC 4497:380 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9078ms total) +T1BFC 4497:381 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9079ms total) +T1BFC 4497:382 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9080ms total) +T1BFC 4497:383 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9081ms total) +T1BFC 4497:384 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9082ms total) +T1BFC 4497:385 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9083ms total) +T1BFC 4497:386 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9084ms total) +T1BFC 4497:387 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9085ms total) +T1BFC 4497:388 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9086ms total) +T1BFC 4497:389 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9087ms total) +T1BFC 4497:390 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9088ms total) +T1BFC 4497:391 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9089ms total) +T1BFC 4497:392 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9090ms total) +T1BFC 4497:393 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9091ms total) +T1BFC 4497:394 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9092ms total) +T1BFC 4497:395 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9093ms total) +T1BFC 4497:396 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9094ms total) +T1BFC 4497:397 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9095ms total) +T1BFC 4497:398 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9096ms total) +T1BFC 4497:399 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9097ms total) +T1BFC 4497:400 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9098ms total) +T1BFC 4497:401 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9099ms total) +T1BFC 4497:402 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9100ms total) +T1BFC 4497:403 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9101ms total) +T1BFC 4497:404 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9102ms total) +T1BFC 4497:405 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9103ms total) +T1BFC 4497:406 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9104ms total) +T1BFC 4497:407 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9105ms total) +T1BFC 4497:408 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9106ms total) +T1BFC 4497:409 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9107ms total) +T1BFC 4497:410 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9108ms total) +T1BFC 4497:411 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9109ms total) +T1BFC 4497:412 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9109ms total) +T1BFC 4497:412 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9110ms total) +T1BFC 4497:413 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9111ms total) +T1BFC 4497:414 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9112ms total) +T1BFC 4497:415 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9113ms total) +T1BFC 4497:416 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9114ms total) +T1BFC 4497:417 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9115ms total) +T1BFC 4497:418 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9116ms total) +T1BFC 4497:419 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9117ms total) +T1BFC 4497:420 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9118ms total) +T1BFC 4497:421 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9119ms total) +T1BFC 4497:422 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9120ms total) +T1BFC 4497:423 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9121ms total) +T1BFC 4497:424 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9122ms total) +T1BFC 4497:425 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9124ms total) +T1BFC 4497:427 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9125ms total) +T1BFC 4497:428 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9126ms total) +T1BFC 4497:429 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9127ms total) +T1BFC 4497:430 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9128ms total) +T1BFC 4497:431 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9129ms total) +T1BFC 4497:432 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9130ms total) +T1BFC 4497:433 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9131ms total) +T1BFC 4497:434 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9132ms total) +T1BFC 4497:435 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9133ms total) +T1BFC 4497:436 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9134ms total) +T1BFC 4497:437 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9135ms total) +T1BFC 4497:438 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9136ms total) +T1BFC 4497:439 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9137ms total) +T1BFC 4497:440 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9138ms total) +T1BFC 4497:441 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9139ms total) +T1BFC 4497:442 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9140ms total) +T1BFC 4497:443 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9141ms total) +T1BFC 4497:444 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9143ms total) +T1BFC 4497:446 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9144ms total) +T1BFC 4497:447 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9145ms total) +T1BFC 4497:448 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9146ms total) +T1BFC 4497:449 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9146ms total) +T1BFC 4497:449 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9147ms total) +T0AC8 4497:450 JLINK_IsHalted() returns TRUE (0000ms, 9147ms total) +T1BFC 4497:450 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9149ms total) +T1BFC 4497:452 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9150ms total) +T1BFC 4497:453 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9151ms total) +T1BFC 4497:454 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9152ms total) +T1BFC 4497:455 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9153ms total) +T1BFC 4497:456 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9154ms total) +T1BFC 4497:457 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9155ms total) +T1BFC 4497:458 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9156ms total) +T1BFC 4497:459 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9157ms total) +T1BFC 4497:460 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9158ms total) +T1BFC 4497:461 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9159ms total) +T1BFC 4497:462 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9160ms total) +T1BFC 4497:463 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9161ms total) +T1BFC 4497:464 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9162ms total) +T1BFC 4497:465 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9163ms total) +T1BFC 4497:466 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9164ms total) +T1BFC 4497:467 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9165ms total) +T1BFC 4497:468 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9166ms total) +T1BFC 4497:469 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9167ms total) +T1BFC 4497:470 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9168ms total) +T1BFC 4497:471 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9169ms total) +T1BFC 4497:472 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9170ms total) +T1BFC 4497:473 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9171ms total) +T1BFC 4497:474 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9172ms total) +T1BFC 4497:475 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9173ms total) +T1BFC 4497:476 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9174ms total) +T1BFC 4497:477 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9175ms total) +T1BFC 4497:478 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9176ms total) +T1BFC 4497:479 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9177ms total) +T1BFC 4497:480 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9178ms total) +T1BFC 4497:481 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9179ms total) +T1BFC 4497:482 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9180ms total) +T1BFC 4497:483 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9181ms total) +T1BFC 4497:484 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9182ms total) +T1BFC 4497:485 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9182ms total) +T1BFC 4497:485 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9183ms total) +T1BFC 4497:486 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9185ms total) +T1BFC 4497:488 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9186ms total) +T1BFC 4497:489 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9187ms total) +T1BFC 4497:490 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9188ms total) +T1BFC 4497:491 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9189ms total) +T1BFC 4497:492 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9190ms total) +T1BFC 4497:493 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9191ms total) +T1BFC 4497:494 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9192ms total) +T1BFC 4497:495 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9193ms total) +T1BFC 4497:496 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9194ms total) +T1BFC 4497:497 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9195ms total) +T1BFC 4497:498 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9196ms total) +T1BFC 4497:499 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9197ms total) +T1BFC 4497:500 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9198ms total) +T1BFC 4497:501 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9199ms total) +T1BFC 4497:502 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9200ms total) +T1BFC 4497:503 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9201ms total) +T1BFC 4497:504 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9202ms total) +T1BFC 4497:505 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9203ms total) +T1BFC 4497:506 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9204ms total) +T1BFC 4497:507 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9205ms total) +T1BFC 4497:508 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9206ms total) +T1BFC 4497:509 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9207ms total) +T1BFC 4497:510 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9208ms total) +T1BFC 4497:511 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9209ms total) +T1BFC 4497:512 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9210ms total) +T1BFC 4497:513 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9211ms total) +T1BFC 4497:514 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9212ms total) +T1BFC 4497:515 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9213ms total) +T1BFC 4497:516 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9214ms total) +T1BFC 4497:517 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9215ms total) +T1BFC 4497:518 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0002ms, 9217ms total) +T1BFC 4497:520 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9218ms total) +T1BFC 4497:521 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9219ms total) +T1BFC 4497:522 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9219ms total) +T1BFC 4497:522 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9220ms total) +T1BFC 4497:523 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9221ms total) +T1BFC 4497:524 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9222ms total) +T1BFC 4497:525 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9223ms total) +T1BFC 4497:526 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9224ms total) +T1BFC 4497:527 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9225ms total) +T1BFC 4497:528 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9226ms total) +T1BFC 4497:529 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9227ms total) +T1BFC 4497:530 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9228ms total) +T1BFC 4497:531 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9229ms total) +T1BFC 4497:532 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9230ms total) +T1BFC 4497:533 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9231ms total) +T1BFC 4497:534 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9232ms total) +T1BFC 4497:535 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9233ms total) +T1BFC 4497:536 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9234ms total) +T1BFC 4497:537 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9235ms total) +T1BFC 4497:538 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9236ms total) +T1BFC 4497:539 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9237ms total) +T1BFC 4497:540 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9238ms total) +T1BFC 4497:541 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9239ms total) +T1BFC 4497:542 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9240ms total) +T1BFC 4497:543 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9241ms total) +T1BFC 4497:544 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9242ms total) +T1BFC 4497:545 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9243ms total) +T1BFC 4497:546 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9244ms total) +T1BFC 4497:547 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9245ms total) +T1BFC 4497:548 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9246ms total) +T1BFC 4497:549 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9247ms total) +T1BFC 4497:550 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9248ms total) +T1BFC 4497:551 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9249ms total) +T1BFC 4497:552 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9250ms total) +T1BFC 4497:553 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9251ms total) +T1BFC 4497:554 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9252ms total) +T1BFC 4497:555 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9253ms total) +T1BFC 4497:556 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9254ms total) +T1BFC 4497:557 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9254ms total) +T1BFC 4497:557 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9255ms total) +T1BFC 4497:558 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9256ms total) +T1BFC 4497:559 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9257ms total) +T1BFC 4497:560 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9258ms total) +T1BFC 4497:561 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9259ms total) +T1BFC 4497:562 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9260ms total) +T1BFC 4497:563 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9261ms total) +T1BFC 4497:564 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9263ms total) +T1BFC 4497:566 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9264ms total) +T1BFC 4497:567 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9265ms total) +T1BFC 4497:568 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9266ms total) +T1BFC 4497:569 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9267ms total) +T1BFC 4497:570 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9268ms total) +T1BFC 4497:571 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9269ms total) +T1BFC 4497:572 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9270ms total) +T1BFC 4497:573 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9271ms total) +T1BFC 4497:574 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9273ms total) +T1BFC 4497:576 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9274ms total) +T1BFC 4497:577 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9275ms total) +T1BFC 4497:578 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9276ms total) +T1BFC 4497:579 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9277ms total) +T1BFC 4497:580 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9278ms total) +T1BFC 4497:581 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9279ms total) +T1BFC 4497:582 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9280ms total) +T1BFC 4497:583 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9281ms total) +T1BFC 4497:584 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9283ms total) +T1BFC 4497:586 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9284ms total) +T1BFC 4497:587 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9285ms total) +T1BFC 4497:588 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9286ms total) +T1BFC 4497:589 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9287ms total) +T1BFC 4497:590 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9288ms total) +T1BFC 4497:591 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9289ms total) +T1BFC 4497:592 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9290ms total) +T1BFC 4497:593 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9291ms total) +T1BFC 4497:594 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9292ms total) +T1BFC 4497:595 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9292ms total) +T1BFC 4497:595 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9293ms total) +T1BFC 4497:596 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9294ms total) +T1BFC 4497:597 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9295ms total) +T1BFC 4497:598 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9296ms total) +T1BFC 4497:599 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9297ms total) +T1BFC 4497:600 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9298ms total) +T1BFC 4497:601 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9299ms total) +T1BFC 4497:602 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9300ms total) +T1BFC 4497:603 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9301ms total) +T1BFC 4497:604 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9302ms total) +T1BFC 4497:605 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9304ms total) +T1BFC 4497:607 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9305ms total) +T1BFC 4497:608 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9306ms total) +T1BFC 4497:609 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9307ms total) +T1BFC 4497:610 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9308ms total) +T1BFC 4497:611 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9309ms total) +T1BFC 4497:612 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9311ms total) +T1BFC 4497:614 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9312ms total) +T1BFC 4497:615 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9313ms total) +T1BFC 4497:616 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9314ms total) +T1BFC 4497:617 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9315ms total) +T1BFC 4497:618 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9316ms total) +T1BFC 4497:619 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9317ms total) +T1BFC 4497:620 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9318ms total) +T1BFC 4497:621 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9319ms total) +T1BFC 4497:622 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9320ms total) +T1BFC 4497:623 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9321ms total) +T1BFC 4497:624 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9322ms total) +T1BFC 4497:625 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9323ms total) +T1BFC 4497:626 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9324ms total) +T1BFC 4497:627 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9325ms total) +T1BFC 4497:628 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9326ms total) +T1BFC 4497:629 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9327ms total) +T1BFC 4497:630 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9328ms total) +T1BFC 4497:631 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9329ms total) +T1BFC 4497:632 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9329ms total) +T1BFC 4497:632 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9330ms total) +T1BFC 4497:633 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9331ms total) +T1BFC 4497:634 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9332ms total) +T1BFC 4497:635 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9333ms total) +T1BFC 4497:636 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9334ms total) +T1BFC 4497:637 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9335ms total) +T1BFC 4497:638 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9336ms total) +T1BFC 4497:639 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9337ms total) +T1BFC 4497:640 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9338ms total) +T1BFC 4497:641 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9339ms total) +T1BFC 4497:642 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9340ms total) +T1BFC 4497:643 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9341ms total) +T1BFC 4497:644 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9342ms total) +T1BFC 4497:645 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9343ms total) +T1BFC 4497:646 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9344ms total) +T1BFC 4497:647 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9345ms total) +T1BFC 4497:648 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9346ms total) +T1BFC 4497:649 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9347ms total) +T0AC8 4497:650 JLINK_IsHalted() returns TRUE (0000ms, 9347ms total) +T1BFC 4497:650 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9348ms total) +T1BFC 4497:651 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9349ms total) +T1BFC 4497:652 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9350ms total) +T1BFC 4497:653 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9351ms total) +T1BFC 4497:654 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9352ms total) +T1BFC 4497:655 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9353ms total) +T1BFC 4497:656 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9354ms total) +T1BFC 4497:657 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9355ms total) +T1BFC 4497:658 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9356ms total) +T1BFC 4497:659 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9357ms total) +T1BFC 4497:660 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9358ms total) +T1BFC 4497:661 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9359ms total) +T1BFC 4497:662 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9360ms total) +T1BFC 4497:663 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9361ms total) +T1BFC 4497:664 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9362ms total) +T1BFC 4497:665 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9363ms total) +T1BFC 4497:666 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9364ms total) +T1BFC 4497:746 JLINK_ReadReg(R0) returns 0x00000001 (0002ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R1) returns 0x00000200 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R2) returns 0x00000200 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R3) returns 0x00000001 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R14) returns 0x0040417D (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(R15 (PC)) returns 0x004043B4 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 9366ms total) +T1BFC 4497:748 JLINK_ReadReg(CycleCnt) -- CPU_ReadMem(4 bytes @ 0xE0001004) returns 0x000593D4 (0002ms, 9368ms total) +T0CD0 4497:775 JLINK_ReadMem (0x2040C428, 0x0004 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x2040C400) -- Updating C cache (64 bytes @ 0x2040C400) -- Read from C cache (4 bytes @ 0x2040C428) - Data: 00 00 00 00 returns 0x00 (0001ms, 9369ms total) +T0AC8 4497:850 JLINK_IsHalted() returns TRUE (0000ms, 9369ms total) +T0AC8 4498:050 JLINK_IsHalted() returns TRUE (0000ms, 9369ms total) +T0CD0 4498:097 JLINK_ReadReg(R15 (PC)) returns 0x004043B4 (0000ms, 9369ms total) +T0CD0 4498:097 JLINK_Step() -- Read from flash cache (2 bytes @ 0x004043B4) -- Read from flash cache (4 bytes @ 0x004043C4) -- Simulated returns 0x00 (0000ms, 9369ms total) +T0AC8 4498:104 JLINK_IsHalted() returns TRUE (0000ms, 9369ms total) +T0AC8 4498:104 JLINK_GetMOEs(...) returns 0x01 (0000ms, 9369ms total) +T0AC8 4498:104 JLINK_ReadReg(R15 (PC)) returns 0x004043B6 (0000ms, 9369ms total) +T0CD0 4498:107 JLINK_ReadReg(R15 (PC)) returns 0x004043B6 (0000ms, 9369ms total) +T0CD0 4498:107 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R1) returns 0x00000200 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R2) returns 0x00000200 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R3) returns 0x004034BD (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R14) returns 0x0040417D (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(R15 (PC)) returns 0x004043B6 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:108 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 9369ms total) +T0CD0 4498:109 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 9370ms total) +T0CD0 4498:109 JLINK_ReadReg(FPS20) returns 0x00000000 (0001ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 9371ms total) +T0CD0 4498:110 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 9371ms total) +T0CD0 4498:111 JLINK_ReadReg(R15 (PC)) returns 0x004043B6 (0000ms, 9371ms total) +T0CD0 4498:111 JLINK_Step() -- Read from flash cache (2 bytes @ 0x004043B6) -- Simulated returns 0x00 (0000ms, 9371ms total) +T0AC8 4498:111 JLINK_IsHalted() returns TRUE (0000ms, 9371ms total) +T0AC8 4498:111 JLINK_GetMOEs(...) returns 0x01 (0000ms, 9371ms total) +T0AC8 4498:111 JLINK_ReadReg(R15 (PC)) returns 0x004034BC (0000ms, 9371ms total) +T0CD0 4498:121 JLINK_ReadReg(R15 (PC)) returns 0x004034BC (0000ms, 9371ms total) +T0CD0 4498:121 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 9371ms total) +T0CD0 4498:180 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 9371ms total) +T0CD0 4498:180 JLINK_ReadReg(R1) returns 0x00000200 (0001ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R2) returns 0x00000200 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R3) returns 0x004034BD (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R7) returns 0x2040E4A0 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R13 (SP)) returns 0x2040E4A0 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R14) returns 0x004043B9 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(R15 (PC)) returns 0x004034BC (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(MSP) returns 0x2040E4A0 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 9372ms total) +T0CD0 4498:181 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 9372ms total) +T0CD0 4498:182 JLINK_ReadReg(R15 (PC)) returns 0x004034BC (0000ms, 9372ms total) +T0CD0 4498:182 JLINK_SetBPEx(Addr = 0x004034C2, Type = 0xFFFFFF02) returns 0x00000003 (0000ms, 9372ms total) +T0CD0 4498:182 JLINK_GetBPInfo(BPHandle = 3) returns 0x00 (0000ms, 9372ms total) +T0CD0 4498:182 JLINK_Go() -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0013ms, 9385ms total) +T0AC8 4498:195 JLINK_IsHalted() returns TRUE (0004ms, 9389ms total) +T0AC8 4498:199 JLINK_GetMOEs(...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) -- CPU_WriteMem(4 bytes @ 0xE000ED30) returns 0x01 (0002ms, 9387ms total) +T0AC8 4498:201 JLINK_ReadReg(R15 (PC)) returns 0x004034C2 (0000ms, 9387ms total) +T0AC8 4498:201 JLINK_GetBPInfo(BPHandle = 3) returns 0x00 (0000ms, 9387ms total) +T0AC8 4498:201 JLINK_ClrBPEx(BPHandle = 0x00000003) returns 0x00 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R15 (PC)) returns 0x004034C2 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R13 (SP)) returns 0x2040E480 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R1) returns 0x00000200 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R2) returns 0x00000200 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R3) returns 0x004034BD (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R7) returns 0x2040E490 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R8) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R13 (SP)) returns 0x2040E480 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R14) returns 0x004043B9 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(R15 (PC)) returns 0x004034C2 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(MSP) returns 0x2040E480 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 9387ms total) +T0CD0 4498:205 JLINK_ReadReg(FPSCR) returns 0x00000000 (0007ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 9394ms total) +T0CD0 4498:212 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 9394ms total) +T0CD0 4498:213 JLINK_ReadMem (0x2040E49C, 0x0004 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x2040E480) -- Updating C cache (64 bytes @ 0x2040E480) -- Read from C cache (4 bytes @ 0x2040E49C) - Data: B9 43 40 00 returns 0x00 (0001ms, 9395ms total) +T0CD0 4498:214 JLINK_ReadMem (0x2040E49C, 0x0004 Bytes, ...) -- Read from C cache (4 bytes @ 0x2040E49C) - Data: B9 43 40 00 returns 0x00 (0001ms, 9396ms total) +T0CD0 4498:215 JLINK_ReadMem (0x2040E498, 0x0004 Bytes, ...) -- Read from C cache (4 bytes @ 0x2040E498) - Data: A0 E4 40 20 returns 0x00 (0000ms, 9396ms total) +T0AC8 4498:401 JLINK_IsHalted() returns TRUE (0000ms, 9396ms total) +T1BFC 4498:411 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9396ms total) +T1BFC 4498:411 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9397ms total) +T1BFC 4498:412 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9398ms total) +T1BFC 4498:413 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9399ms total) +T1BFC 4498:414 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9400ms total) +T1BFC 4498:415 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9401ms total) +T1BFC 4498:416 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9402ms total) +T1BFC 4498:417 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9403ms total) +T1BFC 4498:418 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9404ms total) +T1BFC 4498:419 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9405ms total) +T1BFC 4498:420 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9406ms total) +T1BFC 4498:421 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9407ms total) +T1BFC 4498:422 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9408ms total) +T1BFC 4498:423 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9409ms total) +T1BFC 4498:424 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9410ms total) +T1BFC 4498:425 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9411ms total) +T1BFC 4498:426 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9412ms total) +T1BFC 4498:427 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9413ms total) +T1BFC 4498:428 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9414ms total) +T1BFC 4498:429 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9415ms total) +T1BFC 4498:430 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9416ms total) +T1BFC 4498:431 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9417ms total) +T1BFC 4498:432 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9418ms total) +T1BFC 4498:433 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9419ms total) +T1BFC 4498:434 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9420ms total) +T1BFC 4498:435 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9421ms total) +T1BFC 4498:436 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9422ms total) +T1BFC 4498:437 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9423ms total) +T1BFC 4498:438 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9424ms total) +T1BFC 4498:439 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9425ms total) +T1BFC 4498:440 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9426ms total) +T1BFC 4498:441 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9427ms total) +T1BFC 4498:442 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9428ms total) +T1BFC 4498:443 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9429ms total) +T1BFC 4498:444 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9430ms total) +T1BFC 4498:445 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9431ms total) +T1BFC 4498:446 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9431ms total) +T1BFC 4498:446 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9432ms total) +T1BFC 4498:447 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9433ms total) +T1BFC 4498:448 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9434ms total) +T1BFC 4498:449 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9435ms total) +T1BFC 4498:450 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9436ms total) +T1BFC 4498:451 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9437ms total) +T1BFC 4498:452 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9438ms total) +T1BFC 4498:453 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9439ms total) +T1BFC 4498:454 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9440ms total) +T1BFC 4498:455 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9441ms total) +T1BFC 4498:456 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9442ms total) +T1BFC 4498:457 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9443ms total) +T1BFC 4498:458 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9444ms total) +T1BFC 4498:459 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9445ms total) +T1BFC 4498:460 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9446ms total) +T1BFC 4498:461 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9447ms total) +T1BFC 4498:462 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9448ms total) +T1BFC 4498:463 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9449ms total) +T1BFC 4498:464 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9450ms total) +T1BFC 4498:465 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9451ms total) +T1BFC 4498:466 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9452ms total) +T1BFC 4498:467 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9453ms total) +T1BFC 4498:468 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9454ms total) +T1BFC 4498:469 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9455ms total) +T1BFC 4498:470 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9456ms total) +T1BFC 4498:471 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9457ms total) +T1BFC 4498:472 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9458ms total) +T1BFC 4498:473 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9459ms total) +T1BFC 4498:474 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9460ms total) +T1BFC 4498:475 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9461ms total) +T1BFC 4498:476 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9462ms total) +T1BFC 4498:477 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9463ms total) +T1BFC 4498:478 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9464ms total) +T1BFC 4498:479 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9465ms total) +T1BFC 4498:480 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9466ms total) +T1BFC 4498:481 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9466ms total) +T1BFC 4498:481 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9467ms total) +T1BFC 4498:482 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9468ms total) +T1BFC 4498:483 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9469ms total) +T1BFC 4498:484 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9470ms total) +T1BFC 4498:485 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9471ms total) +T1BFC 4498:486 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9472ms total) +T1BFC 4498:487 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9473ms total) +T1BFC 4498:488 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9474ms total) +T1BFC 4498:489 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9475ms total) +T1BFC 4498:490 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9476ms total) +T1BFC 4498:491 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9477ms total) +T1BFC 4498:492 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9478ms total) +T1BFC 4498:493 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9479ms total) +T1BFC 4498:494 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9480ms total) +T1BFC 4498:495 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9481ms total) +T1BFC 4498:496 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9482ms total) +T1BFC 4498:497 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9483ms total) +T1BFC 4498:498 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9484ms total) +T1BFC 4498:499 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9485ms total) +T1BFC 4498:500 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9486ms total) +T1BFC 4498:501 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9487ms total) +T1BFC 4498:502 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9488ms total) +T1BFC 4498:503 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9489ms total) +T1BFC 4498:504 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9490ms total) +T1BFC 4498:505 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9491ms total) +T1BFC 4498:506 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9492ms total) +T1BFC 4498:507 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9493ms total) +T1BFC 4498:508 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9494ms total) +T1BFC 4498:509 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9495ms total) +T1BFC 4498:510 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9496ms total) +T1BFC 4498:511 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9497ms total) +T1BFC 4498:512 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9498ms total) +T1BFC 4498:513 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9499ms total) +T1BFC 4498:514 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9500ms total) +T1BFC 4498:515 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9501ms total) +T1BFC 4498:516 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9501ms total) +T1BFC 4498:516 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9502ms total) +T1BFC 4498:517 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9503ms total) +T1BFC 4498:518 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9504ms total) +T1BFC 4498:519 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0002ms, 9506ms total) +T1BFC 4498:521 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9507ms total) +T1BFC 4498:522 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9508ms total) +T1BFC 4498:523 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9509ms total) +T1BFC 4498:524 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9510ms total) +T1BFC 4498:525 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9511ms total) +T1BFC 4498:526 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9512ms total) +T1BFC 4498:527 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9513ms total) +T1BFC 4498:528 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9514ms total) +T1BFC 4498:529 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9515ms total) +T1BFC 4498:530 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9516ms total) +T1BFC 4498:531 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9517ms total) +T1BFC 4498:532 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9518ms total) +T1BFC 4498:533 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9519ms total) +T1BFC 4498:534 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9520ms total) +T1BFC 4498:535 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0002ms, 9522ms total) +T1BFC 4498:537 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9524ms total) +T1BFC 4498:539 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9525ms total) +T1BFC 4498:540 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9526ms total) +T1BFC 4498:541 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9527ms total) +T1BFC 4498:542 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9528ms total) +T1BFC 4498:543 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9529ms total) +T1BFC 4498:544 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9530ms total) +T1BFC 4498:545 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9531ms total) +T1BFC 4498:546 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9532ms total) +T1BFC 4498:547 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9533ms total) +T1BFC 4498:548 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9534ms total) +T1BFC 4498:549 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9535ms total) +T1BFC 4498:550 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9536ms total) +T1BFC 4498:551 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9537ms total) +T1BFC 4498:552 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9538ms total) +T1BFC 4498:553 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9539ms total) +T1BFC 4498:554 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9539ms total) +T1BFC 4498:554 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9540ms total) +T1BFC 4498:555 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9542ms total) +T1BFC 4498:557 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9543ms total) +T1BFC 4498:558 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9544ms total) +T1BFC 4498:559 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9545ms total) +T1BFC 4498:560 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9546ms total) +T1BFC 4498:561 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9547ms total) +T1BFC 4498:562 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9548ms total) +T1BFC 4498:563 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9549ms total) +T1BFC 4498:564 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9550ms total) +T1BFC 4498:565 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9551ms total) +T1BFC 4498:566 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9552ms total) +T1BFC 4498:567 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9553ms total) +T1BFC 4498:568 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9554ms total) +T1BFC 4498:569 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9555ms total) +T1BFC 4498:570 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9556ms total) +T1BFC 4498:571 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9557ms total) +T1BFC 4498:572 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9558ms total) +T1BFC 4498:573 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9559ms total) +T1BFC 4498:574 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9561ms total) +T1BFC 4498:576 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9562ms total) +T1BFC 4498:577 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9563ms total) +T1BFC 4498:578 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9564ms total) +T1BFC 4498:579 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9565ms total) +T1BFC 4498:580 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9566ms total) +T1BFC 4498:581 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9567ms total) +T1BFC 4498:582 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9568ms total) +T1BFC 4498:583 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9569ms total) +T1BFC 4498:584 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9570ms total) +T1BFC 4498:585 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9571ms total) +T1BFC 4498:586 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9572ms total) +T1BFC 4498:587 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0002ms, 9574ms total) +T1BFC 4498:589 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9575ms total) +T1BFC 4498:590 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9576ms total) +T1BFC 4498:591 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9577ms total) +T1BFC 4498:592 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9577ms total) +T1BFC 4498:592 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9578ms total) +T1BFC 4498:593 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9579ms total) +T1BFC 4498:594 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9580ms total) +T1BFC 4498:595 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9581ms total) +T1BFC 4498:596 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9582ms total) +T1BFC 4498:597 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9583ms total) +T1BFC 4498:598 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9584ms total) +T1BFC 4498:599 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9585ms total) +T1BFC 4498:600 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9586ms total) +T0AC8 4498:601 JLINK_IsHalted() returns TRUE (0000ms, 9586ms total) +T1BFC 4498:601 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9587ms total) +T1BFC 4498:602 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9588ms total) +T1BFC 4498:603 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9589ms total) +T1BFC 4498:604 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9590ms total) +T1BFC 4498:605 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9591ms total) +T1BFC 4498:606 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9592ms total) +T1BFC 4498:607 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9593ms total) +T1BFC 4498:608 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9594ms total) +T1BFC 4498:609 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9595ms total) +T1BFC 4498:610 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9596ms total) +T1BFC 4498:611 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9597ms total) +T1BFC 4498:612 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9598ms total) +T1BFC 4498:613 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9599ms total) +T1BFC 4498:614 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9600ms total) +T1BFC 4498:615 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9601ms total) +T1BFC 4498:616 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9602ms total) +T1BFC 4498:617 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9603ms total) +T1BFC 4498:618 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9604ms total) +T1BFC 4498:619 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9605ms total) +T1BFC 4498:620 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9606ms total) +T1BFC 4498:621 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9607ms total) +T1BFC 4498:622 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9608ms total) +T1BFC 4498:623 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9609ms total) +T1BFC 4498:624 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9610ms total) +T1BFC 4498:625 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9611ms total) +T1BFC 4498:626 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9612ms total) +T1BFC 4498:627 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9612ms total) +T1BFC 4498:627 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9613ms total) +T1BFC 4498:628 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9614ms total) +T1BFC 4498:629 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9615ms total) +T1BFC 4498:630 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9616ms total) +T1BFC 4498:631 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9617ms total) +T1BFC 4498:632 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9618ms total) +T1BFC 4498:633 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9619ms total) +T1BFC 4498:634 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9620ms total) +T1BFC 4498:635 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9621ms total) +T1BFC 4498:636 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9622ms total) +T1BFC 4498:637 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9623ms total) +T1BFC 4498:638 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9624ms total) +T1BFC 4498:639 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9625ms total) +T1BFC 4498:640 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9626ms total) +T1BFC 4498:641 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9627ms total) +T1BFC 4498:642 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9628ms total) +T1BFC 4498:643 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9629ms total) +T1BFC 4498:644 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9630ms total) +T1BFC 4498:645 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9631ms total) +T1BFC 4498:646 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9632ms total) +T1BFC 4498:647 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9633ms total) +T1BFC 4498:648 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9634ms total) +T1BFC 4498:649 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9635ms total) +T1BFC 4498:650 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9636ms total) +T1BFC 4498:651 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9637ms total) +T1BFC 4498:652 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9638ms total) +T1BFC 4498:653 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9639ms total) +T1BFC 4498:654 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9640ms total) +T1BFC 4498:655 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9641ms total) +T1BFC 4498:656 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9642ms total) +T1BFC 4498:657 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9643ms total) +T1BFC 4498:658 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9644ms total) +T1BFC 4498:659 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9645ms total) +T1BFC 4498:660 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9646ms total) +T1BFC 4498:661 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9647ms total) +T1BFC 4498:662 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9647ms total) +T1BFC 4498:662 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9648ms total) +T1BFC 4498:663 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9649ms total) +T1BFC 4498:664 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9650ms total) +T1BFC 4498:665 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9651ms total) +T1BFC 4498:666 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9652ms total) +T1BFC 4498:667 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9653ms total) +T1BFC 4498:668 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9654ms total) +T1BFC 4498:669 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9655ms total) +T1BFC 4498:670 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9656ms total) +T1BFC 4498:671 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9657ms total) +T1BFC 4498:672 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9658ms total) +T1BFC 4498:673 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9659ms total) +T1BFC 4498:674 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9660ms total) +T1BFC 4498:675 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9661ms total) +T1BFC 4498:676 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9662ms total) +T1BFC 4498:677 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9663ms total) +T1BFC 4498:678 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9664ms total) +T1BFC 4498:679 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9665ms total) +T1BFC 4498:680 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9666ms total) +T1BFC 4498:681 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9667ms total) +T1BFC 4498:682 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9668ms total) +T1BFC 4498:683 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9669ms total) +T1BFC 4498:684 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9670ms total) +T1BFC 4498:685 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9671ms total) +T1BFC 4498:686 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9672ms total) +T1BFC 4498:687 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9673ms total) +T1BFC 4498:688 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9674ms total) +T1BFC 4498:689 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9675ms total) +T1BFC 4498:690 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9676ms total) +T1BFC 4498:691 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9677ms total) +T1BFC 4498:692 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9678ms total) +T1BFC 4498:693 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9679ms total) +T1BFC 4498:694 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9680ms total) +T1BFC 4498:695 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9681ms total) +T1BFC 4498:696 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9682ms total) +T1BFC 4498:697 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9682ms total) +T1BFC 4498:697 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9683ms total) +T1BFC 4498:698 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9684ms total) +T1BFC 4498:699 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9685ms total) +T1BFC 4498:700 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9686ms total) +T1BFC 4498:701 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9687ms total) +T1BFC 4498:702 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9688ms total) +T1BFC 4498:703 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9689ms total) +T1BFC 4498:704 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9690ms total) +T1BFC 4498:705 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9691ms total) +T1BFC 4498:706 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9692ms total) +T1BFC 4498:707 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9693ms total) +T1BFC 4498:708 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9694ms total) +T1BFC 4498:709 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9695ms total) +T1BFC 4498:710 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9696ms total) +T1BFC 4498:711 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9697ms total) +T1BFC 4498:712 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9698ms total) +T1BFC 4498:713 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9699ms total) +T1BFC 4498:714 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9700ms total) +T1BFC 4498:715 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9701ms total) +T1BFC 4498:716 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9702ms total) +T1BFC 4498:717 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9703ms total) +T1BFC 4498:718 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9704ms total) +T1BFC 4498:719 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9705ms total) +T1BFC 4498:720 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9706ms total) +T1BFC 4498:721 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9707ms total) +T1BFC 4498:722 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9708ms total) +T1BFC 4498:723 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9709ms total) +T1BFC 4498:724 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9710ms total) +T1BFC 4498:725 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9711ms total) +T1BFC 4498:726 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9712ms total) +T1BFC 4498:727 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9713ms total) +T1BFC 4498:728 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9714ms total) +T1BFC 4498:729 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9715ms total) +T1BFC 4498:730 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9716ms total) +T1BFC 4498:731 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9717ms total) +T1BFC 4498:732 JLINK_GetDebugInfo(0x100) -- Value=0xE00FD003 returns 0x00 (0000ms, 9717ms total) +T1BFC 4498:732 JLINK_ReadMem (0xE00FDFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FDFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9718ms total) +T1BFC 4498:733 JLINK_ReadMem (0xE00FDFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FDFD0) - Data: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9719ms total) +T1BFC 4498:734 JLINK_ReadMemU32(0xE00FD000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9720ms total) +T1BFC 4498:735 JLINK_ReadMem (0xE00FEFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9721ms total) +T1BFC 4498:736 JLINK_ReadMem (0xE00FEFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FEFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9722ms total) +T1BFC 4498:737 JLINK_ReadMemU32(0xE00FE000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE000) - Data: 03 10 00 00 returns 0x01 (0001ms, 9723ms total) +T1BFC 4498:738 JLINK_ReadMem (0xE00FFFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) - Data: 0D 00 00 00 10 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9724ms total) +T1BFC 4498:739 JLINK_ReadMem (0xE00FFFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE00FFFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9725ms total) +T1BFC 4498:740 JLINK_ReadMemU32(0xE00FF000, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF000) - Data: 03 F0 F0 FF returns 0x01 (0001ms, 9726ms total) +T1BFC 4498:741 JLINK_ReadMem (0xE000EFF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9727ms total) +T1BFC 4498:742 JLINK_ReadMem (0xE000EFD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE000EFD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9728ms total) +T1BFC 4498:743 JLINK_ReadMemU32(0xE00FF004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF004) - Data: 03 20 F0 FF returns 0x01 (0001ms, 9729ms total) +T1BFC 4498:744 JLINK_ReadMem (0xE0001FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9730ms total) +T1BFC 4498:745 JLINK_ReadMem (0xE0001FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0001FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9731ms total) +T1BFC 4498:746 JLINK_ReadMemU32(0xE00FF008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF008) - Data: 03 30 F0 FF returns 0x01 (0001ms, 9732ms total) +T1BFC 4498:747 JLINK_ReadMem (0xE0002FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0002FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9733ms total) +T1BFC 4498:748 JLINK_ReadMem (0xE0002FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0002FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9734ms total) +T1BFC 4498:749 JLINK_ReadMemU32(0xE00FF00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF00C) - Data: 03 10 F0 FF returns 0x01 (0001ms, 9735ms total) +T1BFC 4498:750 JLINK_ReadMem (0xE0000FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0000FF0) - Data: 0D 00 00 00 E0 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9736ms total) +T1BFC 4498:751 JLINK_ReadMem (0xE0000FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0000FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9737ms total) +T1BFC 4498:752 JLINK_ReadMemU32(0xE00FF010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF010) - Data: 02 10 F4 FF returns 0x01 (0001ms, 9738ms total) +T1BFC 4498:753 JLINK_ReadMemU32(0xE00FF014, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF014) - Data: 02 20 F4 FF returns 0x01 (0001ms, 9739ms total) +T1BFC 4498:754 JLINK_ReadMemU32(0xE00FF018, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FF018) - Data: 00 00 00 00 returns 0x01 (0001ms, 9740ms total) +T1BFC 4498:755 JLINK_ReadMemU32(0xE00FE004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9741ms total) +T1BFC 4498:756 JLINK_ReadMem (0xE0041FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9742ms total) +T1BFC 4498:757 JLINK_ReadMem (0xE0041FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0041FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9743ms total) +T1BFC 4498:758 JLINK_ReadMemU32(0xE00FE008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE008) - Data: 02 40 F4 FF returns 0x01 (0001ms, 9744ms total) +T1BFC 4498:759 JLINK_ReadMemU32(0xE00FE00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE00C) - Data: 02 20 F0 1F returns 0x01 (0001ms, 9745ms total) +T1BFC 4498:760 JLINK_ReadMemU32(0xE00FE010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FE010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9746ms total) +T1BFC 4498:761 JLINK_ReadMemU32(0xE00FD004, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD004) - Data: 03 30 F4 FF returns 0x01 (0001ms, 9747ms total) +T1BFC 4498:762 JLINK_ReadMem (0xE0040FF0, 0x0010 Bytes, ...) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) - Data: 0D 00 00 00 90 00 00 00 05 00 00 00 B1 00 00 00 returns 0x00 (0001ms, 9748ms total) +T1BFC 4498:763 JLINK_ReadMem (0xE0040FD0, 0x0020 Bytes, ...) -- CPU_ReadMem(32 bytes @ 0xE0040FD0) - Data: 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ... returns 0x00 (0001ms, 9749ms total) +T1BFC 4498:764 JLINK_ReadMemU32(0xE00FD008, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD008) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9750ms total) +T1BFC 4498:765 JLINK_ReadMemU32(0xE00FD00C, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD00C) - Data: 02 30 F0 1F returns 0x01 (0001ms, 9751ms total) +T1BFC 4498:766 JLINK_ReadMemU32(0xE00FD010, 0x0001 Items, ...) -- CPU_ReadMem(4 bytes @ 0xE00FD010) - Data: 00 00 00 00 returns 0x01 (0001ms, 9752ms total) +T0AC8 4498:801 JLINK_IsHalted() returns TRUE (0001ms, 9753ms total) +T1BFC 4498:832 JLINK_ReadReg(R0) returns 0x00000001 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R1) returns 0x00000200 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R2) returns 0x00000200 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R3) returns 0x004034BD (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R4) returns 0x00000000 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R5) returns 0x00000000 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R6) returns 0x00000000 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R7) returns 0x2040E490 (0000ms, 9752ms total) +T1BFC 4498:832 JLINK_ReadReg(R8) returns 0x00000000 (0001ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R9) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R10) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R11) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R12) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R13 (SP)) returns 0x2040E480 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R14) returns 0x004043B9 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(R15 (PC)) returns 0x004034C2 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(APSR) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(MSP) returns 0x2040E480 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(PSP) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(XPSR) returns 0x01000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(IPSR) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(EPSR) returns 0x01000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(PRIMASK) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FAULTMASK) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(BASEPRI) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(CONTROL) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPSCR) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS0) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS1) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS2) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS3) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS4) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS5) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS6) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS7) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS8) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS9) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS10) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS11) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS12) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS13) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS14) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS15) returns 0xFFFFFFFF (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS16) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS17) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS18) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS19) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS20) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS21) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS22) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS23) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS24) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS25) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS26) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS27) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS28) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS29) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS30) returns 0x00000000 (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(FPS31) returns 0xFFFFFFFF (0000ms, 9753ms total) +T1BFC 4498:833 JLINK_ReadReg(CycleCnt) -- CPU_ReadMem(4 bytes @ 0xE0001004) returns 0x00059424 (0001ms, 9754ms total) +T0CD0 4498:876 JLINK_ReadMem (0x2040C428, 0x0004 Bytes, ...) -- CPU_ReadMem(64 bytes @ 0x2040C400) -- Updating C cache (64 bytes @ 0x2040C400) -- Read from C cache (4 bytes @ 0x2040C428) - Data: 00 00 00 00 returns 0x00 (0001ms, 9755ms total) +T0AC8 4499:002 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4499:202 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4499:402 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4499:603 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4499:803 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4500:003 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4500:204 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4500:407 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4500:607 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4500:808 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4501:008 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4501:208 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4501:409 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4501:609 JLINK_IsHalted() returns TRUE (0002ms, 9757ms total) +T0AC8 4501:811 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4502:012 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4502:212 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4502:412 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4502:613 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4502:813 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4503:013 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4503:214 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4503:414 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4503:614 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4503:815 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4504:015 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4504:216 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4504:417 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0AC8 4504:617 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4504:818 JLINK_IsHalted() returns TRUE (0001ms, 9756ms total) +T0AC8 4505:019 JLINK_IsHalted() returns TRUE (0000ms, 9755ms total) +T0CD0 4505:129 JLINK_ReadReg(R15 (PC)) returns 0x004034C2 (0000ms, 9755ms total) +T0CD0 4505:130 JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) (0011ms, 9766ms total) +T0AC8 4505:141 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4505:182 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4505:343 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4505:984 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4506:625 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4507:266 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4507:907 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4508:548 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4509:189 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4509:831 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0AC8 4510:472 JLINK_IsHalted() returns FALSE (0001ms, 9767ms total) +T0CD0 4511:043 JLINK_Halt() returns 0x00 (0005ms, 9771ms total) +T0AC8 4511:113 JLINK_IsHalted() returns TRUE (0001ms, 9772ms total) +T0AC8 4511:114 JLINK_GetMOEs(...) -- CPU_ReadMem(4 bytes @ 0xE000ED30) -- CPU_WriteMem(4 bytes @ 0xE000ED30) returns 0x01 (0002ms, 9773ms total) +T0AC8 4511:116 JLINK_ReadReg(R15 (PC)) returns 0x00402420 (0000ms, 9773ms total) +T0AC8 4511:316 JLINK_IsHalted() returns TRUE (0000ms, 9773ms total) +T1BFC 4511:317 JLINK_ResetPullsRESET(ON) (0000ms, 9773ms total) +T1BFC 4511:317 JLINK_ResetNoHalt() >0x108 TIF>Found SWD-DP with ID 0x0BD11477 >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> + >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x28 TIF> >0x0D TIF> >0x21 TIF> >0x0D TIF> >0x21 TIF>Found Cortex-M7 r0p1, Little endian. -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE0002000) +FPUnit: 8 code (BP) slots and 0 literal slots -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88) -- CPU_ReadMem(4 bytes @ 0xE000ED88) -- CPU_WriteMem(4 bytes @ 0xE000ED88)CoreSight components:ROMTbl 0 @ E00FD000 -- CPU_ReadMem(16 bytes @ 0xE00FD000) -- CPU_ReadMem(16 bytes @ 0xE00FEFF0) -- CPU_ReadMem(16 bytes @ 0xE00FEFE0)ROMTbl 0 [0]: 00001000, CID: B105100D, PID: 000BB4C8 ROM TableROMTbl 1 @ E00FE000 + -- CPU_ReadMem(16 bytes @ 0xE00FE000) -- CPU_ReadMem(16 bytes @ 0xE00FFFF0) -- CPU_ReadMem(16 bytes @ 0xE00FFFE0)ROMTbl 1 [0]: 00001000, CID: B105100D, PID: 000BB4C7 ROM TableROMTbl 2 @ E00FF000 -- CPU_ReadMem(16 bytes @ 0xE00FF000) -- CPU_ReadMem(16 bytes @ 0xE000EFF0) -- CPU_ReadMem(16 bytes @ 0xE000EFE0)ROMTbl 2 [0]: FFF0F000, CID: B105E00D, PID: 000BB00C SCS -- CPU_WriteMem(4 bytes @ 0xE0001000) -- CPU_ReadMem(16 bytes @ 0xE0001FF0) -- CPU_ReadMem(16 bytes @ 0xE0001FE0) +ROMTbl 2 [1]: FFF02000, CID: B105E00D, PID: 000BB002 DWT -- CPU_ReadMem(16 bytes @ 0xE0002FF0) -- CPU_ReadMem(16 bytes @ 0xE0002FE0)ROMTbl 2 [2]: FFF03000, CID: B105E00D, PID: 000BB00E FPB -- CPU_ReadMem(16 bytes @ 0xE0000FF0) -- CPU_ReadMem(16 bytes @ 0xE0000FE0)ROMTbl 2 [3]: FFF01000, CID: B105E00D, PID: 000BB001 ITM -- CPU_ReadMem(16 bytes @ 0xE00FF010) -- CPU_ReadMem(16 bytes @ 0xE0041FF0) -- CPU_ReadMem(16 bytes @ 0xE0041FE0)ROMTbl 1 [1]: FFF43000, CID: B105900D, PID: 000BB975 ETM-M7 + -- CPU_ReadMem(16 bytes @ 0xE00FE010) -- CPU_ReadMem(16 bytes @ 0xE0040FF0) -- CPU_ReadMem(16 bytes @ 0xE0040FE0)ROMTbl 0 [1]: FFF43000, CID: B105900D, PID: 000BB9A9 TPIU-M7 -- CPU_ReadMem(16 bytes @ 0xE00FD010) -- CPU_ReadMem(4 bytes @ 0xE000ED78) -- CPU_WriteMem(4 bytes @ 0xE000ED84) -- CPU_ReadMem(4 bytes @ 0xE000ED80)I-Cache L1: 16 KB, 256 Sets, 32 Bytes/Line, 2-Way -- CPU_WriteMem(4 bytes @ 0xE000ED84) -- CPU_ReadMem(4 bytes @ 0xE000ED80)D-Cache L1: 16 KB, 128 Sets, 32 Bytes/Line, 4-Way + JLINK_Reset() -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) >0x35 TIF> -- CPU_WriteMem(4 bytes @ 0xE000ED0C) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE000EDFC) -- CPU is running -- CPU_ReadMem(4 bytes @ 0xE000EDF0) -- CPU_WriteMem(4 bytes @ 0xE0002000) -- CPU_ReadMem(4 bytes @ 0xE000EDFC) -- CPU_ReadMem(4 bytes @ 0xE0001000) (0024ms, 0024ms total) + JLINK_Go() -- CPU_ReadMem(4 bytes @ 0xE0001000) -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU_WriteMem(4 bytes @ 0xE0002020) -- CPU_WriteMem(4 bytes @ 0xE0002024) -- CPU_WriteMem(4 bytes @ 0xE0001004) (0007ms, 0031ms total) + (0144ms, 9917ms total) +T1BFC 4511:469 JLINK_Close() -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002008) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000200C) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002010) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002014) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002018) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE000201C) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002020) -- CPU is running -- CPU_WriteMem(4 bytes @ 0xE0002024) >0x42 TIF> >0x28 TIF> >0x0D TIF> + >0x21 TIF> (0015ms, 9932ms total) +T1BFC 4511:469 (0015ms, 9932ms total) +T1BFC 4511:469 Closed (0015ms, 9932ms total) diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/board.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/board.h new file mode 100644 index 000000000..4dfa805e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/board.h @@ -0,0 +1,761 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \page samv7_Xplained_ultra_board_desc SAM V71 Xplained Ultra - Board + * Description + * + * \section Purpose + * + * This file is dedicated to describe the SAM V71 Xplained Ultra board. + * + * \section Contents + * + * - For SAM V71 Xplained Ultra board information, see + * \subpage samv7_Xplained_ultra_board_info. + * - For operating frequency information, see \subpage samv7_Xplained_ultra_opfreq. + * - For using portable PIO definitions, see \subpage samv7_Xplained_ultra_piodef. + * - For using GMAC PIO definitions, see \subpage samv7_Xplained_ultra_gmac. + * - For using ISI definitions, see \subpage samv7_Xplained_ultra_isi. + * - For on-board memories, see \subpage samv7_Xplained_ultra_mem. + * - Several USB definitions are included here, + * see \subpage samv7_Xplained_ultra_usb. + * - For External components, see \subpage samv7_Xplained_ultra_extcomp. + * - For Individual chip definition, see \subpage samv7_Xplained_ultra_chipdef. + * + * To get more software details and the full list of parameters related to the + * SAM V71 Xplained Ultra board configuration, please have a look at the source + * file: + * \ref board.h\n + * + * \section Usage + * + * - The code for booting the board is provided by board_cstartup_xxx.c and + * board_lowlevel.c. + * - For using board PIOs, board characteristics (clock, etc.) and external + * components, see board.h. + * - For manipulating memories, see board_memories.h. + * + * This file can be used as a template and modified to fit a custom board, with + * specific PIOs usage or memory connections. + */ + +/** + * \file board.h + * + * Definition of SAM V71 Xplained Ultra board characteristics, PIOs and + * external components interface. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include "include/board_lowlevel.h" +#include "include/board_memories.h" +#include "include/led.h" +#include "include/gmii.h" +#include "include/gmacb_phy.h" +#include "include/dbg_console.h" +#include "include/bmp.h" +#include "include/lcdd.h" +#include "include/ili9488.h" +#include "include/ili9488_reg.h" +#include "include/ili9488_spi.h" +#include "include/ili9488_ebi.h" +#include "include/ili9488_dma.h" +#include "include/ili9488_spi_dma.h" +#include "include/ili9488_ebi_dma.h" +#include "include/frame_buffer.h" +#include "include/lcd_color.h" +#include "include/lcd_draw.h" +#include "include/lcd_font10x14.h" +#include "include/lcd_font.h" +#include "include/lcd_gimp_image.h" +#include "include/rtc_calib.h" +#include "include/wm8904.h" +#include "include/cs2100.h" +#include "include/s25fl1.h" +#include "include/omnivision.h" +#include "include/ovyuv.h" +#include "include/ov.h" +#include "include/iso7816_4.h" + +#if defined ( __GNUC__ ) +#include "include/syscalls.h" +#endif +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_board_info "SAM V71 Xplained Ultra - Board informations" + * This page lists several definition related to the board description. + * + * \section Definitions + * - \ref BOARD_NAME + */ + +/** Name of the board */ +#define BOARD_NAME "SAM V71 Xplained Ultra" +#define NO_PUSHBUTTON +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_opfreq "SAM V71 Xplained Ultra - Operating frequencies" + * This page lists several definition related to the board operating frequency + * (when using the initialization done by board_lowlevel.c). + * + * \section Definitions + * - \ref BOARD_MAINOSC + * - \ref BOARD_MCK + */ + +/** Frequency of the board main oscillator */ +#define BOARD_MAINOSC 12000000 + +/** Master clock frequency (when using board_lowlevel.c) */ + +#define BOARD_MCK 150000000 + +#if (BOARD_MCK==132000000 ) + +#define PLL_MUL 0x16 +#define PLL_DIV 0x01 + +#else // 300MHz(PCK) and 150MHz(MCK) by default + +#define PLL_MUL 0x19 +#define PLL_DIV 0x01 + +#endif + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_piodef "SAM V71 Xplained Ultra - PIO definitions" + * This pages lists all the PIOs definitions contained in board.h. The constants + * are named using the following convention: PIN_* for a constant which defines + * a single Pin instance (but may include several PIOs sharing the same + * controller), and PINS_* for a list of Pin instances. + * + * UART0 + * - \ref PINS_UART0 + * + * UART4 + * - \ref PINS_UART4 + * + * LEDs + * - \ref PIN_LED_0 + * - \ref PIN_LED_1 + * - \ref PINS_LEDS + * + * Push buttons + * - \ref PIN_PUSHBUTTON_0 + * - \ref PIN_PUSHBUTTON_1 + * - \ref PINS_PUSHBUTTONS + * - \ref PUSHBUTTON_BP0 + * - \ref PUSHBUTTON_BP1 + * + * PWMC + * - \ref PIN_PWMC_PWMH0 + * - \ref PIN_PWMC_PWMH1 + * - \ref PIN_PWM_LED0 + * - \ref PIN_PWM_LED1 + * - \ref CHANNEL_PWM_LED0 + * - \ref CHANNEL_PWM_LED1 + * + * SPI + * - \ref PIN_SPI_MISO + * - \ref PIN_SPI_MOSI + * - \ref PIN_SPI_SPCK + * - \ref PINS_SPI + * + * PCK0 + * - \ref PIN_PCK0 + * - \ref PIN_PCK1 + * - \ref PIN_PCK2 + * + * PIO PARALLEL CAPTURE + * - \ref PIN_PIODCEN1 + * - \ref PIN_PIODCEN2 + * + * TWI + * - \ref TWI_V3XX + * - \ref PIN_TWI_TWD0 + * - \ref PIN_TWI_TWCK0 + * - \ref PINS_TWI0 + * - \ref PIN_TWI_TWD1 + * - \ref PIN_TWI_TWCK1 + * - \ref PINS_TWI1 + * + * USART0 + * - \ref PIN_USART0_RXD + * - \ref PIN_USART0_TXD + * - \ref PIN_USART0_CTS + * - \ref PIN_USART0_RTS + * - \ref PIN_USART0_SCK + * + * USART1 + * - \ref PIN_USART1_RXD + * - \ref PIN_USART1_TXD + * - \ref PIN_USART1_CTS + * - \ref PIN_USART1_RTS + * - \ref PIN_USART1_SCK + * + * USART2 + * - \ref PIN_USART2_RXD + * - \ref PIN_USART2_TXD + * - \ref PIN_USART2_CTS + * - \ref PIN_USART2_RTS + * - \ref PIN_USART2_SCK + * + * SSC + * - \ref PIN_SSC_TD + * - \ref PIN_SSC_TK + * - \ref PIN_SSC_TF + * - \ref PIN_SSC_RD + * - \ref PIN_SSC_RK + * - \ref PIN_SSC_RF + * - \ref PIN_SSC_TD + * - \ref PINS_SSC_CODEC + * + * MCAN + * - \ref PIN_MCAN0_TXD + * - \ref PIN_MCAN0_RXD + * - \ref PIN_MCAN1_TXD + * - \ref PIN_MCAN1_RXD + */ + +/** SSC pin Transmitter Data (TD) */ +#define PIN_SSC_TD {PIO_PD26B_TD, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SSC pin Transmitter Clock (TK) */ +#define PIN_SSC_TK {PIO_PB1D_TK, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +/** SSC pin Transmitter FrameSync (TF) */ +#define PIN_SSC_TF {PIO_PB0D_TF, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +/** SSC pin RD */ +#define PIN_SSC_RD {PIO_PA10C_RD, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} +/** SSC pin RK */ +#define PIN_SSC_RK {PIO_PA22A_RK, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** SSC pin RF */ +#define PIN_SSC_RF {PIO_PD24B_RF, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/** SSC pins definition for codec. */ +#define PINS_SSC_CODEC \ + {PIN_SSC_TD, PIN_SSC_TK, PIN_SSC_TF, PIN_SSC_RD, PIN_SSC_RK, PIN_SSC_RF} + +/** UART pins (UTXD0 and URXD0) definitions, PA9,10. */ +#define PINS_UART0 \ + {PIO_PA9A_URXD0 | PIO_PA10A_UTXD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** UART pins (UTXD4 and URXD4) definitions, PD19,18. */ +#define PINS_UART4 \ + {PIO_PD18C_URXD4 | PIO_PD19C_UTXD4, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} + +/* LED pins definitions */ +#define LED_YELLOW0 0 +#define LED_YELLOW1 1 + +/** LED #0 pin definition (YELLOW). */ +#define PIN_LED_0 {PIO_PA23, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/** LED #0 pin definition (YELLOW). */ +#define PIN_LED_1 {PIO_PC9, PIOC, ID_PIOC, PIO_OUTPUT_0, PIO_DEFAULT} + +/** List of all LEDs definitions. */ +#define PINS_LEDS {PIN_LED_0, PIN_LED_1} + +/** + * Push button #0 definition. + * Attributes = pull-up + debounce + interrupt on rising edge. + */ +#define PIN_PUSHBUTTON_0 \ + {PIO_PA9, PIOA, ID_PIOA, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} +/** + * Push button #1 definition. + * Attributes = pull-up + debounce + interrupt on rising edge. + */ +#define PIN_PUSHBUTTON_1 \ + {PIO_PB12, PIOB, ID_PIOB, PIO_INPUT, PIO_PULLUP | PIO_DEBOUNCE | PIO_IT_FALL_EDGE} + +/** List of all push button definitions. */ +#define PINS_PUSHBUTTONS {PIN_PUSHBUTTON_0, PIN_PUSHBUTTON_1} + +/** Push button #0 index. */ +#define PUSHBUTTON_BP0 0 +/** Push button #1 index. */ +#define PUSHBUTTON_BP1 1 + +/** PWMC PWM0 pin definition: Output High. */ +#define PIN_PWMC_PWMH0 {PIO_PD20A_PWMH0, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** PWMC PWM1 pin definition: Output High. */ +#define PIN_PWMC_PWMH1 {PIO_PD21A_PWMH1, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +/** PWM pins definition for LED0 */ +#define PIN_PWM_LED0 PIN_PWMC_PWMH0 +/** PWM pins definition for LED1 */ +#define PIN_PWM_LED1 PIN_PWMC_PWMH1 +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LED0 0 +/** PWM channel for LED1 */ +#define CHANNEL_PWM_LED1 1 + +/** SPI MISO pin definition. */ +#define PIN_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define PIN_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define PIN_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define PIN_SPI_NPCS0 {PIO_PB2D_SPI0_NPCS0, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +#define PIN_SPI_NPCS1 {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +#define PIN_SPI_NPCS3 {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/** List of SPI pin definitions (MISO, MOSI & SPCK). */ +#define PINS_SPI PIN_SPI_MISO, PIN_SPI_MOSI, PIN_SPI_SPCK + +/** PCK0 */ +#define PIN_PCK0 {PIO_PB13B_PCK0, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT} +/** PCK1 */ +#define PIN_PCK1 {PIO_PA17B_PCK1, PIOB, ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT} +/** PCK2 */ +#define PIN_PCK2 {PIO_PA18B_PCK2, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT} + + +/** PIO PARALLEL CAPTURE */ +/** Parallel Capture Mode Data Enable1 */ +#define PIN_PIODCEN1 PIO_PA15 +/** Parallel Capture Mode Data Enable2 */ +#define PIN_PIODCEN2 PIO_PA16 + +/** TWI version 3.xx */ +#define TWI_V3XX +/** TWI0 data pin */ +#define PIN_TWI_TWD0 {PIO_PA3A_TWD0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI0 clock pin */ +#define PIN_TWI_TWCK0 {PIO_PA4A_TWCK0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI0 pins */ +#define PINS_TWI0 {PIN_TWI_TWD0, PIN_TWI_TWCK0} + +/** TWI1 data pin */ +#define PIN_TWI_TWD1 {PIO_PB4A_TWD1, PIOB, ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT} +/** TWI1 clock pin */ +#define PIN_TWI_TWCK1 {PIO_PB5A_TWCK1, PIOB, ID_PIOB, PIO_PERIPH_A,PIO_DEFAULT} +/** TWI1 pins */ +#define PINS_TWI1 {PIN_TWI_TWD1, PIN_TWI_TWCK1} + +/** USART0 pin RX */ +#define PIN_USART0_RXD {PIO_PB0C_RXD0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin TX */ +#define PIN_USART0_TXD {PIO_PB1C_TXD0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin CTS */ +#define PIN_USART0_CTS {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin RTS */ +#define PIN_USART0_RTS {PIO_PB3C_RTS0, PIOB, ID_PIOB, PIO_PERIPH_C, PIO_DEFAULT} +/** USART0 pin SCK */ +#define PIN_USART0_SCK {PIO_PB13C_SCK0, PIOB, ID_PIOB, PIO_PERIPH_C,PIO_DEFAULT} + +/** USART1 pin RX */ +#define PIN_USART1_RXD {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin TX */ +#define PIN_USART1_TXD {1<<22, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin CTS */ +#define PIN_USART1_CTS {PIO_PA25A_CTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin RTS */ +#define PIN_USART1_RTS {PIO_PA24A_RTS1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin ENABLE */ +#define PIN_USART1_EN {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT} +/** USART1 pin SCK */ +#define PIN_USART1_SCK {PIO_PA23A_SCK1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/** USART2 pin RX */ +#define PIN_USART2_RXD {PIO_PD15B_RXD2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin TX */ +#define PIN_USART2_TXD {PIO_PD16B_TXD2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin CTS */ +#define PIN_USART2_CTS {PIO_PD19B_CTS2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin RTS */ +#define PIN_USART2_RTS {PIO_PD18B_RTS2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** USART2 pin SCK */ +#define PIN_USART2_SCK {PIO_PD17B_SCK2, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} + +/*Pins for USART0 as 7816 mode*/ +/** PIN used for reset the smartcard */ +#define PIN_ISO7816_RSTMC {PIO_PB2C_CTS0, PIOB, ID_PIOB, PIO_OUTPUT_0, PIO_DEFAULT} +/** Pins used for connect the smartcard */ +#define PINS_ISO7816 PIN_USART0_TXD, PIN_USART0_SCK,PIN_ISO7816_RSTMC + +/** MCAN0 pin Transmit Data (TXD) */ +#define PIN_MCAN0_TXD {PIO_PB2A_CANTX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** MCAN0 pin Receive Data (RXD) */ +#define PIN_MCAN0_RXD {PIO_PB3A_CANRX0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/** MCAN1 pin Transmit Data (TXD) */ +#define PIN_MCAN1_TXD {PIO_PC14C_CANTX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} +/** MCAN1 pin Receive Data (RXD) */ +#define PIN_MCAN1_RXD {PIO_PC12C_CANRX1, PIOC, ID_PIOC, PIO_PERIPH_C, PIO_DEFAULT} + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_gmac "SAM V71 Xplained Ultra - GMAC" + * \section GMAC + * - \ref BOARD_GMAC_PHY_ADDR + * - \ref BOARD_GMAC_PHY_COMP_KSZ8061RNB + * - \ref BOARD_GMAC_MODE_RMII + * - \ref BOARD_GMAC_PINS + * - \ref BOARD_GMAC_RESET_PIN + * + */ +/** PHY address */ +#define BOARD_GMAC_PHY_ADDR 1 +/** PHY Component */ +#define BOARD_GMAC_PHY_COMP_KSZ8061RNB 1 +/** Board GMAC power control - ALWAYS ON */ +#define BOARD_GMAC_POWER_ALWAYS_ON +/** Board GMAC work mode - RMII/MII ( 1 / 0 ) */ +#define BOARD_GMAC_MODE_RMII 1 + +/** The PIN list of PIO for GMAC */ +#define BOARD_GMAC_PINS \ + { (PIO_PD0A_GTXCK | PIO_PD1A_GTXEN | PIO_PD2A_GTX0 | PIO_PD3A_GTX1 \ + | PIO_PD4A_GRXDV | PIO_PD5A_GRX0 | PIO_PD6A_GRX1 | PIO_PD7A_GRXER \ + | PIO_PD8A_GMDC | PIO_PD9A_GMDIO ),PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT}, \ + {PIO_PC30, PIOC, ID_PIOC, PIO_INPUT, PIO_PULLUP},\ + {PIO_PA29, PIOA, ID_PIOA, PIO_INPUT, PIO_DEFAULT} + +/** The PIN list of PIO for GMAC */ +#define BOARD_GMAC_RESET_PIN {PIO_PC10, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_PULLUP} + +/** The runtime pin configure list for GMAC */ +#define BOARD_GMAC_RUN_PINS BOARD_GMAC_PINS + + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_isi "SAM V71 Xplained Ultra - ISI" + * This page lists all the IO definitions connected to ISI module. + * ISI + * - \ref PIN_ISI_D0 + * - \ref PIN_ISI_D1 + * - \ref PIN_ISI_D2 + * - \ref PIN_ISI_D3 + * - \ref PIN_ISI_D4 + * - \ref PIN_ISI_D5 + * - \ref PIN_ISI_D6 + * - \ref PIN_ISI_D7 + * - \ref PIN_ISI_D8 + * - \ref PIN_ISI_D9 + * - \ref BOARD_ISI_VSYNC + * - \ref BOARD_ISI_HSYNC + * - \ref BOARD_ISI_PCK + * - \ref BOARD_ISI_PINS + * + */ +#define PIN_ISI_D0 {PIO_PD22D_ISI_D0, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D1 {PIO_PD21D_ISI_D1, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D2 {PIO_PB3D_ISI_D2, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D3 {PIO_PA9B_ISI_D3, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_PULLUP} +#define PIN_ISI_D4 {PIO_PA5B_ISI_D4, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_PULLUP} +#define PIN_ISI_D5 {PIO_PD11D_ISI_D5, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D6 {PIO_PD12D_ISI_D6, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D7 {PIO_PA27D_ISI_D7, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D8 {PIO_PD27D_ISI_D8, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} +#define PIN_ISI_D9 {PIO_PD28D_ISI_D9, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_PULLUP} + +#define BOARD_ISI_VSYNC {PIO_PD25D_ISI_VSYNC, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_DEFAULT} +#define BOARD_ISI_HSYNC {PIO_PD24D_ISI_HSYNC, PIOD, ID_PIOD, PIO_PERIPH_D, PIO_DEFAULT} +#define BOARD_ISI_PCK {PIO_PA24D_ISI_PCK, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_DEFAULT} + +#define BOARD_ISI_PCK0 { PIO_PA6B_PCK0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT } +#define BOARD_ISI_RST { 1 << 13, PIOB, ID_PIOB, PIO_OUTPUT_1, PIO_DEFAULT } +#define BOARD_ISI_PWD { 1 << 19, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT } + +#define BOARD_ISI_PINS \ + PIN_ISI_D0, PIN_ISI_D1, PIN_ISI_D2,PIN_ISI_D3,PIN_ISI_D4, PIN_ISI_D5,\ + PIN_ISI_D6,PIN_ISI_D7,PIN_ISI_D8, PIN_ISI_D9,BOARD_ISI_VSYNC ,\ + BOARD_ISI_HSYNC ,BOARD_ISI_PCK, BOARD_ISI_RST, BOARD_ISI_PWD,BOARD_ISI_PCK0 + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_usb "SAM V71 Xplained Ultra - USB device" + * + * \section Definitions + * - \ref BOARD_USB_BMATTRIBUTES + * + * \section vBus + * - \ref PIN_USB_VBUS + * + */ + +/** + * USB attributes configuration descriptor (bus or self powered, + * remote wakeup) + */ +#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP + +/** USB VBus monitoring pin definition. */ +#define PIN_USB_VBUS {PIO_PC16, PIOC, ID_PIOC, PIO_INPUT, PIO_DEFAULT} + + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_extcomp "SAM V71 Xplained Ultra - External components" + * This page lists the definitions related to external on-board components + * located in the board.h file for the SAM V71 Xplained Ultra board. + * + * LCD + */ +/** Indicates board has an ILI9325 external component to manage LCD. */ +#define BOARD_LCD_ILI9488 +//#define BOARD_LCD_SPI_EXT1 +#define BOARD_LCD_SPI_EXT2 + +/** SPI pin definition for LCD */ +#if defined (BOARD_LCD_SPI_EXT1) +/** SPI MISO pin definition. */ +#define LCD_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define LCD_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define LCD_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define LCD_SPI_NPCS {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT} + +/** SPI chip select pin definition. */ +#define LCD_SPI_NPCS {PIO_PD25B_SPI0_NPCS1, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT} + +/** LCD pins definition. */ +#define BOARD_SPI_LCD_PINS {LCD_SPI_MISO, LCD_SPI_MOSI, LCD_SPI_SPCK, LCD_SPI_NPCS} + +/** Back-light pin definition. */ + +#define BOARD_SPI_LCD_BACKLIGHT_PIN \ + {PIO_PA0A_PWMC0_PWMH0, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} + +/** PWMC PWM0 pin definition: Output Low. */ +#define LCD_SPI_PIN_RESET {PIO_PD28, PIOD, ID_PIOD, PIO_OUTPUT_1, PIO_DEFAULT} + +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LCD 0 + +#endif +/*ENDIF BOARD_LCD_SPI_EXT1 */ + +#if defined (BOARD_LCD_SPI_EXT2) + /** SPI MISO pin definition. */ +#define LCD_SPI_MISO {PIO_PD20B_SPI0_MISO, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI MOSI pin definition. */ +#define LCD_SPI_MOSI {PIO_PD21B_SPI0_MOSI, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI SPCK pin definition. */ +#define LCD_SPI_SPCK {PIO_PD22B_SPI0_SPCK, PIOD, ID_PIOD, PIO_PERIPH_B, PIO_DEFAULT} +/** SPI chip select pin definition. */ +#define LCD_SPI_NPCS {PIO_PD27B_SPI0_NPCS3, PIOD, ID_PIOD, PIO_PERIPH_B,PIO_DEFAULT} + +/** LCD pins definition. */ +#define BOARD_SPI_LCD_PINS {LCD_SPI_MISO, LCD_SPI_MOSI, LCD_SPI_SPCK, LCD_SPI_NPCS} + +/** Back-light pin definition. */ + +#define BOARD_SPI_LCD_PIN_BACKLIGHT \ + {PIO_PC19B_PWMC0_PWMH2, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/** PWMC PWM0 pin definition: Output Low. */ +#define LCD_SPI_PIN_RESET {PIO_PA24, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} + +/** LCD command/data select pin */ +#define BOARD_SPI_LCD_PIN_CDS {PIO_PA6, PIOA, ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT} + +/** PWM channel for LED0 */ +#define CHANNEL_PWM_LCD 2 + +#endif +/*ENDIF BOARD_LCD_SPI_EXT2 */ + +/** SMC pin definition for LCD */ +/** LCD data pin */ +#define PIN_EBI_LCD_DATAL {0xFF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_LCD_DATAH_0 {0x3F, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_PULLUP} +#define PIN_EBI_LCD_DATAH_1 {PIO_PA15A_D14|PIO_PA16A_D15, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_PULLUP} +/** LCD WE pin */ +#define PIN_EBI_LCD_NWE {PIO_PC8A_NWE, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +/** LCD RD pin */ +#define PIN_EBI_LCD_NRD {PIO_PC11A_NRD, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_PULLUP} +/* LCD CS pin (NCS3) */ +#define PIN_EBI_LCD_CS {PIO_PD19A_NCS3, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_PULLUP} +/** LCD command/data select pin */ +#define BOARD_EBI_LCD_PIN_CDS {PIO_PC30, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +/** Back-light pin definition. */ +#define BOARD_EBI_LCD_PIN_BACKLIGHT {PIO_PC9B_TIOB7, PIOC, ID_PIOC, PIO_PERIPH_B, PIO_DEFAULT} +/** LCD reset pin */ +#define LCD_EBI_PIN_RESET {PIO_PC13, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} + +/** LCD pins definition. */ +#define BOARD_EBI_LCD_PINS \ + {PIN_EBI_LCD_DATAL, PIN_EBI_LCD_DATAH_0, PIN_EBI_LCD_DATAH_1, \ + PIN_EBI_LCD_NWE,PIN_EBI_LCD_NRD,PIN_EBI_LCD_CS} + + +/** Display width in pixels. */ +#define BOARD_LCD_WIDTH 320 +/** Display height in pixels. */ +#define BOARD_LCD_HEIGHT 480 + + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_mem "SAM V71 Xplained Ultra - Memories" + * This page lists definitions related to internal & external on-board memories. + * \section SDRAM + * - \ref PIN_SDRAM_D0_7 + * - \ref PIN_SDRAM_D8_13 + * - \ref PIN_SDRAM_D14_15 + * - \ref PIN_SDRAM_A0_9 + * - \ref PIN_SDRAM_SDA10 + * - \ref PIN_SDRAM_CAS + * - \ref PIN_SDRAM_RAS + * - \ref PIN_SDRAM_SDCKE + * - \ref PIN_SDRAM_SDCK + * - \ref PIN_SDRAM_SDSC + * - \ref PIN_SDRAM_NBS0 + * - \ref PIN_SDRAM_NBS1 + * - \ref PIN_SDRAM_SDWE + * - \ref PIN_SDRAM_BA0 + * + * \section SDMMC + * - \ref BOARD_MCI_PIN_CD + * - \ref BOARD_MCI_PIN_CK + * - \ref BOARD_MCI_PINS_SLOTA + * - \ref BOARD_SD_PINS + * + * \section QSPI + * - \ref PINS_QSPI_IO + * - \ref PINS_QSPI_IO3 + * - \ref PINS_QSPI + */ + +/** List of all SDRAM pin definitions. */ +#define BOARD_SDRAM_SIZE (2*1024*1024) +#define PIN_SDRAM_D0_7 {0x000000FF, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_D8_13 {0x0000003F, PIOE, ID_PIOE, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_D14_15 {0x00018000, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_A0_9 {0x3FF00000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_SDA10 {0x00002000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} + +#define PIN_SDRAM_CAS {0x00020000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_RAS {0x00010000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDCKE {0x00004000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDCK {0x00800000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDSC {0x00008000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_NBS0 {0x00040000, PIOC, ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT} +#define PIN_SDRAM_NBS1 {0x00008000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_SDWE {0x20000000, PIOD, ID_PIOD, PIO_PERIPH_C, PIO_DEFAULT} +#define PIN_SDRAM_BA0 {0x00100000, PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} + +#define BOARD_SDRAM_PINS PIN_SDRAM_D0_7, PIN_SDRAM_D8_13 , PIN_SDRAM_D14_15,\ + PIN_SDRAM_A0_9, PIN_SDRAM_SDA10, PIN_SDRAM_BA0, \ + PIN_SDRAM_CAS, PIN_SDRAM_RAS, PIN_SDRAM_SDCKE,PIN_SDRAM_SDCK,\ + PIN_SDRAM_SDSC,PIN_SDRAM_NBS0 ,PIN_SDRAM_NBS1,PIN_SDRAM_SDWE + + +/** List of all MCI pin definitions. */ + +/** MCI0 Card detect pin definition. (PE5) */ +#define BOARD_MCI_PIN_CD {PIO_PD18, PIOD, ID_PIOD, PIO_INPUT, PIO_PULLUP} +/** MCI0 Clock . */ +#define BOARD_MCI_PIN_CK {PIO_PA25D_MCCK, PIOA, ID_PIOA, PIO_PERIPH_D, PIO_DEFAULT} + +/** MCI0 Solt A IO pins definition. (PC4-PC13) */ +#define BOARD_MCI_PINS_SLOTA \ + {(PIO_PA30C_MCDA0 | PIO_PA31C_MCDA1 | PIO_PA26C_MCDA2 | PIO_PA27C_MCDA3 | PIO_PA28C_MCCDA),\ + PIOA, ID_PIOA, PIO_PERIPH_C, PIO_DEFAULT} + +/** MCI pins that shall be configured to access the SD card. */ +#define BOARD_SD_PINS {BOARD_MCI_PINS_SLOTA, BOARD_MCI_PIN_CK} +/** MCI Card Detect pin. */ +#define BOARD_SD_PIN_CD BOARD_MCI_PIN_CD + /** Total number of MCI interface */ +#define BOARD_NUM_MCI 1 + +/** List of all SQPI pin definitions. */ +#define PINS_QSPI_IO \ + {(PIO_PA11A_QCS | PIO_PA13A_QIO0 | PIO_PA12A_QIO1 | PIO_PA17A_QIO2 | PIO_PA14A_QSCK),\ + PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_QSPI_IO3 {PIO_PD31A_QIO3, PIOD, ID_PIOD, PIO_PERIPH_A, PIO_DEFAULT} +#define PINS_QSPI {PINS_QSPI_IO, PINS_QSPI_IO3} + +/*----------------------------------------------------------------------------*/ +/** + * \page samv7_Xplained_ultra_chipdef "SAM V71 Xplained Ultra - Individual chip definition" + * This page lists the definitions related to different chip's definition + * + * \section USART + * - \ref BOARD_PIN_USART_RXD + * - \ref BOARD_PIN_USART_TXD + * - \ref BOARD_PIN_USART_CTS + * - \ref BOARD_PIN_USART_RTS + * - \ref BOARD_PIN_USART_EN + * - \ref BOARD_USART_BASE + * - \ref BOARD_ID_USART + */ + +/** Rtc */ +#define BOARD_RTC_ID ID_RTC + +/** TWI ID for QTouch application to use */ +#define BOARD_ID_TWI_AT42 ID_TWI0 +/** TWI Base for QTouch application to use */ +#define BOARD_BASE_TWI_AT42 TWI0 +/** TWI pins for QTouch application to use */ +#define BOARD_PINS_TWI_AT42 PINS_TWI0 + +/** USART RX pin for application */ +#define BOARD_PIN_USART_RXD PIN_USART1_RXD +/** USART TX pin for application */ +#define BOARD_PIN_USART_TXD PIN_USART1_TXD +/** USART CTS pin for application */ +#define BOARD_PIN_USART_CTS PIN_USART1_CTS +/** USART RTS pin for application */ +#define BOARD_PIN_USART_RTS PIN_USART1_RTS +/** USART ENABLE pin for application */ +#define BOARD_PIN_USART_EN PIN_USART1_EN +/** USART Base for application */ +#define BOARD_USART_BASE USART1 +/** USART ID for application */ +#define BOARD_ID_USART ID_USART1 + + + +/*----------------------------------------------------------------------------*/ + /* + * USB pins + */ +#define PINS_VBUS_EN {PIO_PC16, PIOC, ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT} +#endif /* #ifndef _BOARD_H_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/bmp.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/bmp.h new file mode 100644 index 000000000..f1ad41237 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/bmp.h @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * \section Purpose + * + * Utility for BMP + * + */ + +#ifndef BMP_H +#define BMP_H + +/** BMP magic number ('BM'). */ +#define BMP_TYPE 0x4D42 + +/** headerSize must be set to 40 */ +#define BITMAPINFOHEADER 40 + +/*------------------------------------------------------------------------------ + * Exported types + *------------------------------------------------------------------------------*/ + +#pragma pack( 1 ) + +/** BMP (Windows) Header Format */ +typedef struct _BMPHeader{ + /* signature, must be 4D42 hex */ + uint16_t type; + /* size of BMP file in bytes (unreliable) */ + uint32_t fileSize; + /* reserved, must be zero */ + uint16_t reserved1; + /* reserved, must be zero */ + uint16_t reserved2; + /* offset to start of image data in bytes */ + uint32_t offset; + /* size of BITMAPINFOHEADER structure, must be 40 */ + uint32_t headerSize; + /* image width in pixels */ + uint32_t width; + /* image height in pixels */ + uint32_t height; + /* number of planes in the image, must be 1 */ + uint16_t planes; + /* number of bits per pixel (1, 4, 8, 16, 24, 32) */ + uint16_t bits; + /* compression type (0=none, 1=RLE-8, 2=RLE-4) */ + uint32_t compression; + /* size of image data in bytes (including padding) */ + uint32_t imageSize; + /* horizontal resolution in pixels per meter (unreliable) */ + uint32_t xresolution; + /* vertical resolution in pixels per meter (unreliable) */ + uint32_t yresolution; + /* number of colors in image, or zero */ + uint32_t ncolours; + /* number of important colors, or zero */ + uint32_t importantcolours; + } BMPHeader; + +#pragma pack() + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint8_t BMP_IsValid(void *file); +extern uint32_t BMP_GetFileSize(void *file); + +extern uint8_t BMP_Decode( + void *file, + uint8_t *buffer, + uint32_t width, + uint32_t height, + uint8_t bpp ); + +extern void WriteBMPheader( + uint32_t *pAddressHeader, + uint32_t bmpHSize, + uint32_t bmpVSize, + uint8_t nbByte_Pixels ); + +extern void BMP_displayHeader(uint32_t* pAddressHeader); +extern void RGB565toBGR555( + uint8_t *fileSource, + uint8_t *fileDestination, + uint32_t width, + uint32_t height, + uint8_t bpp ); + +#endif //#ifndef BMP_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/board_lowlevel.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/board_lowlevel.h new file mode 100644 index 000000000..00c285411 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/board_lowlevel.h @@ -0,0 +1,47 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for the low-level initialization function. + * + */ + +#ifndef BOARD_LOWLEVEL_H +#define BOARD_LOWLEVEL_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void LowLevelInit( void ); +extern void _SetupMemoryRegion( void ); + +#endif /* BOARD_LOWLEVEL_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/board_memories.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/board_memories.h new file mode 100644 index 000000000..cfbd3819d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/board_memories.h @@ -0,0 +1,48 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for memories configuration on board. + * + */ + +#ifndef BOARD_MEMORIES_H +#define BOARD_MEMORIES_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void BOARD_ConfigureSdram( void ); +extern uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size); + +#endif /* #ifndef BOARD_MEMORIES_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/cs2100.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/cs2100.h new file mode 100644 index 000000000..b2b1246e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/cs2100.h @@ -0,0 +1,93 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +#ifndef CS2100_H +#define CS2100_H + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define CS2100_SLAVE_ADDRESS 0x4E + +/** ID and Rev register*/ +#define CS2100_REG_ID 0x01 + +/** VMID control 0 register*/ +#define CS2100_REG_CTRL 0x02 + +/** MIC Bias control 0 register*/ +#define CS2100_REG_DEV_CFG1 0x03 + +/** Bias control 1 register*/ +#define CS2100_REG_CFG 0x05 + +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_1 0x06 +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_2 0x07 +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_3 0x08 +/** Power management control 0 register*/ +#define CS2100_REG_32_BIT_RATIO_4 0x09 +/** Power management control 2 register*/ +#define CS2100_REG_FUNC_CFG1 0x16 +/** Power management control 3 register*/ +#define CS2100_REG_FUNC_CFG2 0x17 +/** Power management control 3 register*/ +#define CS2100_REG_FUNC_CFG3 0x1E + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint16_t CS2100_Read( + Twid *pTwid, + uint32_t device, + uint32_t regAddr); + +extern void CS2100_Write( + Twid *pTwid, + uint32_t device, + uint32_t regAddr, + uint16_t data); + +extern uint8_t CS2100_Init(Twid *pTwid, uint32_t device, uint32_t PCK); +#endif // CS2100_H + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/dbg_console.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/dbg_console.h new file mode 100644 index 000000000..2fb50e237 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/dbg_console.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Include function prototype for the UART console. + */ + +#ifndef _DBG_CONSOLE_ +#define _DBG_CONSOLE_ + +#include + +extern void DBG_Configure( uint32_t dwBaudrate, uint32_t dwMasterClock ) ; +extern void DBG_PutChar( uint8_t uc ) ; +extern uint32_t DBG_GetChar( void ) ; +extern uint32_t DBG_IsRxReady( void ) ; + + +extern void DBG_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) ; +extern void DBG_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, uint32_t dwAddress ) ; +extern uint32_t DBG_GetInteger( int32_t* pdwValue ) ; +extern uint32_t DBG_GetIntegerMinMax( int32_t* pdwValue, int32_t dwMin, int32_t dwMax ) ; +extern uint32_t DBG_GetHexa32( uint32_t* pdwValue ) ; + +#endif /* _DBG_CONSOLE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/frame_buffer.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/frame_buffer.h new file mode 100644 index 000000000..3c1da52ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/frame_buffer.h @@ -0,0 +1,83 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of frame buffer driver. + * + */ + +#ifndef _FRAME_BUFFER_ +#define _FRAME_BUFFER_ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void FB_SetFrameBuffer( + LcdColor_t *pBuffer, + uint8_t ucWidth, + uint8_t ucHeight); + +extern void FB_SetColor(uint32_t color); + +extern uint32_t FB_DrawLine ( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 ); + +extern uint32_t FB_DrawPixel( uint32_t x, uint32_t y ); +extern uint32_t FB_DrawCircle( uint32_t x, uint32_t y, uint32_t r ); +extern uint32_t FB_DrawFilledCircle( + uint32_t dwX, + uint32_t dwY, + uint32_t dwRadius); + +extern uint32_t FB_DrawRectangle( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 ); + +extern uint32_t FB_DrawFilledRectangle( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 ); + +extern uint32_t FB_DrawPicture( + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2, + const void *pBuffer ); + +#endif /* #ifndef _FRAME_BUFFER_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/gmacb_phy.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/gmacb_phy.h new file mode 100644 index 000000000..eacaf1134 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/gmacb_phy.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmacb_module Ethernet GMACB Driver + *@{ + * Implement GEMAC PHY driver, that initialize the PHY to prepare for + * Ethernet transfer. + * + * \section Usage + * -# EMAC related pins and Driver should be initialized at first. + * -# Initialize GMACB Driver instance by invoking GMACB_Init(). + * -# Initialize PHY connected via GMACB_InitPhy(), PHY address is + * automatically adjusted by attempt to read. + * -# Perform PHY auto negotiate through GMACB_AutoNegotiate(), so + * connection established. + * + * + * Related files:\n + * \ref gmacb.h\n + * \ref gmacb.c\n + * \ref gmii.h.\n + * + */ +/**@}*/ + +#ifndef _GMACB_PHY_H +#define _GMACB_PHY_H + + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "board.h" + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** The reset length setting for external reset configuration */ +#define GMACB_RESET_LENGTH 0xD + +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ + + +/** The DM9161 instance */ +typedef struct _GMacb { + /**< Driver */ + sGmacd *pGmacd; + /** The retry & timeout settings */ + uint32_t retryMax; + /** PHY address ( pre-defined by pins on reset ) */ + uint8_t phyAddress; + } GMacb; + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ +extern void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax); + +extern void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress); + +extern uint8_t GMACB_InitPhy( + GMacb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pEmacPins, + uint32_t nbEmacPins); + +extern uint8_t GMACB_AutoNegotiate(GMacb *pMacb); + +extern uint8_t GMACB_GetLinkSpeed(GMacb *pMacb, uint8_t applySettings); + +extern uint8_t GMACB_Send(GMacb *pMacb, void *pBuffer, uint32_t size); + +extern uint32_t GMACB_Poll(GMacb *pMacb, uint8_t *pBuffer, uint32_t size); + +extern void GMACB_DumpRegisters(GMacb *pMacb); + +extern uint8_t GMACB_ResetPhy(GMacb *pMacb); + +#endif // #ifndef _GMACB_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/gmii.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/gmii.h new file mode 100644 index 000000000..3309a1cbe --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/gmii.h @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _GMII_DEFINE_H +#define _GMII_DEFINE_H + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +//IEEE defined Registers +#define GMII_BMCR 0x0 // Basic Mode Control Register +#define GMII_BMSR 0x1 // Basic Mode Status Register +#define GMII_PHYID1R 0x2 // PHY Identifier Register 1 +#define GMII_PHYID2R 0x3 // PHY Identifier Register 2 +#define GMII_ANAR 0x4 // Auto_Negotiation Advertisement Register +#define GMII_ANLPAR 0x5 // Auto_negotiation Link Partner Ability Register +#define GMII_ANER 0x6 // Auto-negotiation Expansion Register +#define GMII_ANNPR 0x7 // Auto-negotiation Next Page Register +#define GMII_ANLPNPAR 0x8 // Auto_negotiation Link Partner Next Page Ability Register +#define GMII_AFEC0R 0x11 // AFE Control 0 Register +#define GMII_AFEC3R 0x14 // AFE Control 3 Register +#define GMII_RXERCR 0x15 // RXER Counter Register +#define GMII_OMSSR 0x17 // Operation Mode Strap Status Register +#define GMII_ECR 0x18 // Expanded Control Register +#define GMII_ICSR 0x1B // Interrupt Control/Status Register +#define GMII_FC 0x1C // Function Control +#define GMII_LCSR 0x1D // LinkMD® Control/Status Register +#define GMII_PC1R 0x1E // PHY Control 1 Register +#define GMII_PC2R 0x1F // PHY Control 2 Register + +// PHY ID Identifier Register +#define GMII_LSB_MASK 0x0U +// definitions: MII_PHYID1 +#define GMII_OUI_MSB 0x0022 +// definitions: MII_PHYID2 +#define GMII_OUI_LSB 0x1572 // KSZ8061 PHY Id2 + +// Basic Mode Control Register (BMCR) +// Bit definitions: MII_BMCR +#define GMII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation +#define GMII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation +#define GMII_SPEED_SELECT_LSB (1 << 13) // 1,0=1000Mbps 0,1=100Mbps; 0,0=10Mbps +#define GMII_AUTONEG (1 << 12) // Auto-negotiation Enable +#define GMII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation +#define GMII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation +#define GMII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation +#define GMII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation +// Reserved 7 // Read as 0, ignore on write +#define GMII_SPEED_SELECT_MSB (1 << 6) // +// Reserved 5 to 0 // Read as 0, ignore on write + + +// Basic Mode Status Register (BMSR) +// Bit definitions: MII_BMSR +#define GMII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable +#define GMII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable +#define GMII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable +#define GMII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable +#define GMII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable +// Reserved 10 to 9 // Read as 0, ignore on write +#define GMII_EXTEND_STATUS (1 << 8) // 1 = Extend Status Information In Reg 15 +// Reserved 7 +#define GMII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression +#define GMII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete +#define GMII_REMOTE_FAULT (1 << 4) // Remote Fault +#define GMII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability +#define GMII_LINK_STATUS (1 << 2) // Link Status +#define GMII_JABBER_DETECT (1 << 1) // Jabber Detect +#define GMII_EXTEND_CAPAB (1 << 0) // Extended Capability + +// Auto-negotiation Advertisement Register (ANAR) +// Auto-negotiation Link Partner Ability Register (ANLPAR) +// Bit definitions: MII_ANAR, MII_ANLPAR +#define GMII_NP (1 << 15) // Next page Indication +// Reserved 7 +#define GMII_RF (1 << 13) // Remote Fault +// Reserved 12 // Write as 0, ignore on read +#define GMII_PAUSE_MASK (3 << 11) // 0,0 = No Pause 1,0 = Asymmetric Pause(link partner) + // 0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) +#define GMII_T4 (1 << 9) // 100BASE-T4 Support +#define GMII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support +#define GMII_TX_HDX (1 << 7) // 100BASE-TX Support +#define GMII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support +#define GMII_10_HDX (1 << 5) // 10BASE-T Support +// Selector 4 to 0 // Protocol Selection Bits +#define GMII_AN_IEEE_802_3 0x00001 + +#endif // #ifndef _MII_DEFINE_H diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488.h new file mode 100644 index 000000000..dc04e63cc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488.h @@ -0,0 +1,107 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_H_ +#define _ILI9488_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define ILI9488_SPIMODE 0 +#define ILI9488_EBIMODE 1 + +/* ILI9325 ID code */ +#define ILI9488_DEVICE_CODE 0x9488 + +#define ILI9488_LCD_WIDTH 320 +#define ILI9488_LCD_HEIGHT 480 +#define ILI9488_SELF_TEST_OK 0xC0 + +/* EBI chip select for LCD */ +#define SMC_EBI_LCD_CS 3 + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef enum{ + AccessInst = 0, + AccessRead, + AccessWrite +}AccessIli_t; + +typedef union _union_type +{ + uint32_t value; + struct{ + uint8_t byte_8; + uint8_t byte_l6; + uint8_t byte_24; + uint8_t byte_32; + }byte; + struct{ + uint16_t half_word_l; + uint16_t half_word_h; + }half_word; + }union_type; +typedef volatile uint8_t REG8; + +typedef uint32_t LcdColor_t; + +/*---------------------------------------------------------------------------- + * Marcos + *----------------------------------------------------------------------------*/ +/* Pixel cache used to speed up communication */ +#define LCD_DATA_CACHE_SIZE BOARD_LCD_WIDTH + +/*---------------------------------------------------------------------------- + * Function Marcos + *----------------------------------------------------------------------------*/ +#define get_0b_to_8b(x) (((union_type*)&(x))->byte.byte_8) +#define get_8b_to_16b(x) (((union_type*)&(x))->byte.byte_l6) +#define get_16b_to_24b(x) (((union_type*)&(x))->byte.byte_24) +#define get_24b_to_32b(x) (((union_type*)&(x))->byte.byte_32) + +#endif /* #ifndef ILI9488 */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_dma.h new file mode 100644 index 000000000..8d1cc126b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_dma.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_DMA_H_ +#define _ILI9488_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ +/** An unspecified error has occurred.*/ +#define ILI9488_ERROR_DMA_ALLOCATE_CHANNEL 1 +#define ILI9488_ERROR_DMA_CONFIGURE 2 +#define ILI9488_ERROR_DMA_TRANSFER 3 +#define ILI9488_ERROR_DMA_SIZE 4 + +#define ILI9488_SPI SPI0 +#define ILI9488_SPI_ID ID_SPI0 + +/* EBI BASE ADDRESS for SMC LCD */ +#define ILI9488_BASE_ADDRESS 0x63000000 + +/*------------------------------------------------------------------------------ + * Types + *----------------------------------------------------------------------------*/ + +typedef struct _ILI9488_dma +{ + /** Pointer to DMA driver */ + sXdmad *xdmaD; + /** ili9488 Tx channel */ + uint32_t ili9488DmaTxChannel; + /** ili9488 Rx channel */ + uint32_t ili9488DmaRxChannel; + /** ili9488 Tx/Rx configure descriptor */ + sXdmadCfg xdmadRxCfg,xdmadTxCfg; + /** ili9488 dma interrupt */ + uint32_t xdmaInt; + /** Pointer to SPI Hardware registers */ + Spi* pSpiHw ; + /** SPI Id as defined in the product datasheet */ + uint8_t spiId ; +}sIli9488Dma; + +typedef struct _ILI9488_ctl +{ + /** ili9488 Command/Data mode */ + volatile uint32_t cmdOrDataFlag; + /** ili9488 Rx done */ + volatile uint32_t rxDoneFlag; + /** ili9488 Tx done */ + volatile uint32_t txDoneFlag; +}sIli9488DmaCtl; + +#endif /* #ifndef ILI9488_DMA */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_ebi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_ebi.h new file mode 100644 index 000000000..edcef30d9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_ebi.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_EBI_H_ +#define _ILI9488_EBI_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t ILI9488_EbiReadChipId (void); +extern uint32_t ILI9488_EbiInitialize( sXdmad * dmad ); +extern void ILI9488_EbiSetPixelFormat(uint16_t format); +extern void ILI9488_EbiSetCursor(uint16_t x, uint16_t y); +extern void ILI9488_EbiSetWindow( + uint16_t dwX, uint16_t dwY, uint16_t dwWidth, uint16_t dwHeight ); +extern void ILI9488_EbiSetFullWindow(void); +extern void ILI9488_EbiOn(void ); +extern void ILI9488_EbiOff(void ); +extern void ILI9488_EbiSetDisplayLandscape( uint8_t dwRGB, uint8_t LandscaprMode ); + +#endif /* #ifndef ILI9488_EBI */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_ebi_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_ebi_dma.h new file mode 100644 index 000000000..295749784 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_ebi_dma.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_EBI_DMA_H_ +#define _ILI9488_EBI_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint8_t ILI9488_EbiInitializeWithDma(sXdmad * dmad); +extern uint8_t ILI9488_EbiDmaTxTransfer( uint16_t *pTxBuffer, uint32_t wTxSize); +extern uint8_t ILI9488_EbiDmaRxTransfer( uint32_t *pRxBuffer,uint32_t wRxSize); +extern uint8_t ILI9488_EbiSendCommand(uint16_t Instr, uint16_t *pTxData, + uint32_t *pRxData, AccessIli_t ReadWrite, uint32_t size); +#endif /* #ifndef ILI9488_EBI_DMA */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_reg.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_reg.h new file mode 100644 index 000000000..be457a2a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_reg.h @@ -0,0 +1,131 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef ILI9488_REG_H_INCLUDED +#define ILI9488_REG_H_INCLUDED + +/* Level 1 Commands (from the display Datasheet) */ +#define ILI9488_CMD_NOP 0x00 +#define ILI9488_CMD_SOFTWARE_RESET 0x01 +#define ILI9488_CMD_READ_DISP_ID 0x04 +#define ILI9488_CMD_READ_ERROR_DSI 0x05 +#define ILI9488_CMD_READ_DISP_STATUS 0x09 +#define ILI9488_CMD_READ_DISP_POWER_MODE 0x0A +#define ILI9488_CMD_READ_DISP_MADCTRL 0x0B +#define ILI9488_CMD_READ_DISP_PIXEL_FORMAT 0x0C +#define ILI9488_CMD_READ_DISP_IMAGE_MODE 0x0D +#define ILI9488_CMD_READ_DISP_SIGNAL_MODE 0x0E +#define ILI9488_CMD_READ_DISP_SELF_DIAGNOSTIC 0x0F +#define ILI9488_CMD_ENTER_SLEEP_MODE 0x10 +#define ILI9488_CMD_SLEEP_OUT 0x11 +#define ILI9488_CMD_PARTIAL_MODE_ON 0x12 +#define ILI9488_CMD_NORMAL_DISP_MODE_ON 0x13 +#define ILI9488_CMD_DISP_INVERSION_OFF 0x20 +#define ILI9488_CMD_DISP_INVERSION_ON 0x21 +#define ILI9488_CMD_PIXEL_OFF 0x22 +#define ILI9488_CMD_PIXEL_ON 0x23 +#define ILI9488_CMD_DISPLAY_OFF 0x28 +#define ILI9488_CMD_DISPLAY_ON 0x29 +#define ILI9488_CMD_COLUMN_ADDRESS_SET 0x2A +#define ILI9488_CMD_PAGE_ADDRESS_SET 0x2B +#define ILI9488_CMD_MEMORY_WRITE 0x2C +#define ILI9488_CMD_MEMORY_READ 0x2E +#define ILI9488_CMD_PARTIAL_AREA 0x30 +#define ILI9488_CMD_VERT_SCROLL_DEFINITION 0x33 +#define ILI9488_CMD_TEARING_EFFECT_LINE_OFF 0x34 +#define ILI9488_CMD_TEARING_EFFECT_LINE_ON 0x35 +#define ILI9488_CMD_MEMORY_ACCESS_CONTROL 0x36 +#define ILI9488_CMD_VERT_SCROLL_START_ADDRESS 0x37 +#define ILI9488_CMD_IDLE_MODE_OFF 0x38 +#define ILI9488_CMD_IDLE_MODE_ON 0x39 +#define ILI9488_CMD_COLMOD_PIXEL_FORMAT_SET 0x3A +#define ILI9488_CMD_WRITE_MEMORY_CONTINUE 0x3C +#define ILI9488_CMD_READ_MEMORY_CONTINUE 0x3E +#define ILI9488_CMD_SET_TEAR_SCANLINE 0x44 +#define ILI9488_CMD_GET_SCANLINE 0x45 +#define ILI9488_CMD_WRITE_DISPLAY_BRIGHTNESS 0x51 +#define ILI9488_CMD_READ_DISPLAY_BRIGHTNESS 0x52 +#define ILI9488_CMD_WRITE_CTRL_DISPLAY 0x53 +#define ILI9488_CMD_READ_CTRL_DISPLAY 0x54 +#define ILI9488_CMD_WRITE_CONTENT_ADAPT_BRIGHTNESS 0x55 +#define ILI9488_CMD_READ_CONTENT_ADAPT_BRIGHTNESS 0x56 +#define ILI9488_CMD_WRITE_MIN_CAB_LEVEL 0x5E +#define ILI9488_CMD_READ_MIN_CAB_LEVEL 0x5F +#define ILI9488_CMD_READ_ABC_SELF_DIAG_RES 0x68 +#define ILI9488_CMD_READ_ID1 0xDA +#define ILI9488_CMD_READ_ID2 0xDB +#define ILI9488_CMD_READ_ID3 0xDC + +/* Level 2 Commands (from the display Datasheet) */ +#define ILI9488_CMD_INTERFACE_MODE_CONTROL 0xB0 +#define ILI9488_CMD_FRAME_RATE_CONTROL_NORMAL 0xB1 +#define ILI9488_CMD_FRAME_RATE_CONTROL_IDLE_8COLOR 0xB2 +#define ILI9488_CMD_FRAME_RATE_CONTROL_PARTIAL 0xB3 +#define ILI9488_CMD_DISPLAY_INVERSION_CONTROL 0xB4 +#define ILI9488_CMD_BLANKING_PORCH_CONTROL 0xB5 +#define ILI9488_CMD_DISPLAY_FUNCTION_CONTROL 0xB6 +#define ILI9488_CMD_ENTRY_MODE_SET 0xB7 +#define ILI9488_CMD_BACKLIGHT_CONTROL_1 0xB9 +#define ILI9488_CMD_BACKLIGHT_CONTROL_2 0xBA +#define ILI9488_CMD_HS_LANES_CONTROL 0xBE +#define ILI9488_CMD_POWER_CONTROL_1 0xC0 +#define ILI9488_CMD_POWER_CONTROL_2 0xC1 +#define ILI9488_CMD_POWER_CONTROL_NORMAL_3 0xC2 +#define ILI9488_CMD_POWER_CONTROL_IDEL_4 0xC3 +#define ILI9488_CMD_POWER_CONTROL_PARTIAL_5 0xC4 +#define ILI9488_CMD_VCOM_CONTROL_1 0xC5 +#define ILI9488_CMD_CABC_CONTROL_1 0xC6 +#define ILI9488_CMD_CABC_CONTROL_2 0xC8 +#define ILI9488_CMD_CABC_CONTROL_3 0xC9 +#define ILI9488_CMD_CABC_CONTROL_4 0xCA +#define ILI9488_CMD_CABC_CONTROL_5 0xCB +#define ILI9488_CMD_CABC_CONTROL_6 0xCC +#define ILI9488_CMD_CABC_CONTROL_7 0xCD +#define ILI9488_CMD_CABC_CONTROL_8 0xCE +#define ILI9488_CMD_CABC_CONTROL_9 0xCF +#define ILI9488_CMD_NVMEM_WRITE 0xD0 +#define ILI9488_CMD_NVMEM_PROTECTION_KEY 0xD1 +#define ILI9488_CMD_NVMEM_STATUS_READ 0xD2 +#define ILI9488_CMD_READ_ID4 0xD3 +#define ILI9488_CMD_ADJUST_CONTROL_1 0xD7 +#define ILI9488_CMD_READ_ID_VERSION 0xD8 +#define ILI9488_CMD_POSITIVE_GAMMA_CORRECTION 0xE0 +#define ILI9488_CMD_NEGATIVE_GAMMA_CORRECTION 0xE1 +#define ILI9488_CMD_DIGITAL_GAMMA_CONTROL_1 0xE2 +#define ILI9488_CMD_DIGITAL_GAMMA_CONTROL_2 0xE3 +#define ILI9488_CMD_SET_IMAGE_FUNCTION 0xE9 +#define ILI9488_CMD_ADJUST_CONTROL_2 0xF2 +#define ILI9488_CMD_ADJUST_CONTROL_3 0xF7 +#define ILI9488_CMD_ADJUST_CONTROL_4 0xF8 +#define ILI9488_CMD_ADJUST_CONTROL_5 0xF9 +#define ILI9488_CMD_SPI_READ_SETTINGS 0xFB +#define ILI9488_CMD_ADJUST_CONTROL_6 0xFC +#define ILI9488_CMD_ADJUST_CONTROL_7 0xFF + +#endif /* ILI9488_REGS_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_spi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_spi.h new file mode 100644 index 000000000..c78442c59 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_spi.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 driver. + * + */ + +#ifndef _ILI9488_SPI_H_ +#define _ILI9488_SPI_H_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint32_t ILI9488_SpiReadChipId (void); +extern uint32_t ILI9488_SpiInitialize( sXdmad * dmad ); +extern void ILI9488_SpiSetPixelFormat(uint8_t format); +extern void ILI9488_SpiNop(void); +extern void ILI9488_SpiWriteMemory(const uint8_t *pBuf, uint32_t size); +extern void ILI9488_SpiReadMemory( const uint8_t *pBuf, uint32_t size); +extern void ILI9488_SpiSetCursor(uint16_t x, uint16_t y); +extern void ILI9488_SpiSetWindow( + uint16_t dwX, + uint16_t dwY, + uint16_t dwWidth, + uint16_t dwHeight ); + +extern void ILI9488_SpiSetFullWindow(void); +extern void ILI9488_SpiOn(void ); +extern void ILI9488_SpiOff(void ); +extern void ILI9488_SpiSetDisplayLandscape( + uint8_t dwRGB, uint8_t LandscaprMode ); + +#endif /* #ifndef ILI9488_SPI */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_spi_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_spi_dma.h new file mode 100644 index 000000000..9c873298d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ili9488_spi_dma.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface of ILI9488 DMA driver. + * + */ + +#ifndef _ILI9488_SPI_DMA_H_ +#define _ILI9488_SPI_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint8_t ILI9488_SpiInitializeWithDma(sXdmad * dmad); +extern uint8_t ILI9488_SpiDmaTxTransfer( uint8_t *pTxBuffer, uint32_t wTxSize); +extern uint8_t ILI9488_SpiDmaRxTransfer( uint32_t *pRxBuffer,uint32_t wRxSize); +extern uint8_t ILI9488_SpiSendCommand(uint8_t Instr, uint8_t* pTxData, + uint32_t* pRxData, AccessIli_t ReadWrite, uint32_t size); + +#endif /* #ifndef ILI9488_SPI_DMA */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_color.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_color.h new file mode 100644 index 000000000..19229c346 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_color.h @@ -0,0 +1,109 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef COLOR_H +#define COLOR_H + +/** + * \file + * + * RGB 24-bits color table definition. + * + */ + +/* + * RGB 24 Bpp + * RGB 888 + * R7R6R5R4 R3R2R1R0 G7G6G5G4 G3G2G1G0 B7B6B5B4 B3B2B1B0 + */ + +#define COLOR_BLACK 0x000000 +#define COLOR_WHITE 0xFFFFFF + +#define COLOR_BLUE 0x0000FF +#define COLOR_GREEN 0x00FF00 +#define COLOR_RED 0xFF0000 + +#define COLOR_NAVY 0x000080 +#define COLOR_DARKBLUE 0x00008B +#define COLOR_DARKGREEN 0x006400 +#define COLOR_DARKCYAN 0x008B8B +#define COLOR_CYAN 0x00FFFF +#define COLOR_TURQUOISE 0x40E0D0 +#define COLOR_INDIGO 0x4B0082 +#define COLOR_DARKRED 0x800000 +#define COLOR_OLIVE 0x808000 +#define COLOR_GRAY 0x808080 +#define COLOR_SKYBLUE 0x87CEEB +#define COLOR_BLUEVIOLET 0x8A2BE2 +#define COLOR_LIGHTGREEN 0x90EE90 +#define COLOR_DARKVIOLET 0x9400D3 +#define COLOR_YELLOWGREEN 0x9ACD32 +#define COLOR_BROWN 0xA52A2A +#define COLOR_DARKGRAY 0xA9A9A9 +#define COLOR_SIENNA 0xA0522D +#define COLOR_LIGHTBLUE 0xADD8E6 +#define COLOR_GREENYELLOW 0xADFF2F +#define COLOR_SILVER 0xC0C0C0 +#define COLOR_LIGHTGREY 0xD3D3D3 +#define COLOR_LIGHTCYAN 0xE0FFFF +#define COLOR_VIOLET 0xEE82EE +#define COLOR_AZUR 0xF0FFFF +#define COLOR_BEIGE 0xF5F5DC +#define COLOR_MAGENTA 0xFF00FF +#define COLOR_TOMATO 0xFF6347 +#define COLOR_GOLD 0xFFD700 +#define COLOR_ORANGE 0xFFA500 +#define COLOR_SNOW 0xFFFAFA +#define COLOR_YELLOW 0xFFFF00 + +#define BLACK 0x0000 +#define BLUE 0x001F +#define RED 0xF800 +#define GREEN 0x07E0 +#define WHITE 0xFFFF + +/* level is in [0; 31]*/ +#define BLUE_LEV( level) ( (level)&BLUE ) +#define GREEN_LEV(level) ( (((level)*2)<<5)&GREEN ) +#define RED_LEV( level) ( ((level)<<(5+6))&RED ) +#define GRAY_LEV( level) ( BLUE_LEV(level) | GREEN_LEV(level) | RED_LEV(level)) + +#define RGB_24_TO_RGB565(RGB) \ + (((RGB >>19)<<11) | (((RGB & 0x00FC00) >>5)) | (RGB & 0x00001F)) +#define RGB_24_TO_18BIT(RGB) \ + (((RGB >>16)&0xFC) | (((RGB & 0x00FF00) >>10) << 10) | (RGB & 0x0000FC)<<16) +#define RGB_16_TO_18BIT(RGB) \ + (((((RGB >>11)*63)/31)<<18) | (RGB & 0x00FC00) | (((RGB & 0x00001F)*63)/31)) +#define BGR_TO_RGB_18BIT(RGB) \ + (RGB & 0xFF0000) | ((RGB & 0x00FF00) >> 8 ) | ( (RGB & 0x0000FC) >> 16 )) +#define BGR_16_TO_18BITRGB(RGB) BGR_TO_RGB_18BIT(RGB_16_TO_18BIT(RGB)) + + +#endif /* #define COLOR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_draw.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_draw.h new file mode 100644 index 000000000..5db53ce3e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_draw.h @@ -0,0 +1,186 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** + * \file + * + * Interface for draw function on LCD. + * + */ + +#ifndef DRAW_H +#define DRAW_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" +#include +#include "lcd_gimp_image.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** Horizontal direction line definition */ +#define DIRECTION_HLINE 0 +/** Vertical direction line definition */ +#define DIRECTION_VLINE 1 + +typedef struct _rect{ + uint32_t x; + uint32_t y; + uint32_t width; + uint32_t height; +}rect; + +COMPILER_PACK_SET(1) +typedef struct _rgb{ + uint8_t b; + uint8_t g; + uint8_t r; +}sBGR; +COMPILER_PACK_RESET() + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void LCDD_SetUpdateWindowSize(rect rc); + +extern void LCDD_UpdateWindow(void); + +extern void LCDD_UpdatePartialWindow( uint8_t* pbuf, uint32_t size); + +extern void LCDD_DrawRectangleWithFill( + uint16_t* pbuf, + uint32_t dwX, + uint32_t dwY, + uint32_t dwWidth, + uint32_t dwHeight, + uint32_t dwColor); + +extern uint32_t LCDD_DrawCircle( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + uint32_t r, + uint32_t color); + +extern uint32_t LCD_DrawFilledCircle( + uint16_t* pbuf, + uint32_t dwX, + uint32_t dwY, + uint32_t dwRadius, + uint32_t color); + +extern void LCDD_DrawString( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + const uint8_t *pString, + uint32_t color ); + +extern void LCDD_GetStringSize( + const uint8_t *pString, + uint32_t *pWidth, + uint32_t *pHeight ); + +extern void LCDD_BitBlt( + uint16_t* pbuf, + uint32_t dst_x, + uint32_t dst_y, + uint32_t dst_w, + uint32_t dst_h, + const LcdColor_t *src, + uint32_t src_x, + uint32_t src_y, + uint32_t src_w, + uint32_t src_h); + +extern void LCDD_BitBltAlphaBlend(uint16_t* pbuf, + uint32_t dst_x, + uint32_t dst_y, + uint32_t dst_w, + uint32_t dst_h, + const LcdColor_t *src, + uint32_t src_x, + uint32_t src_y, + uint32_t src_w, + uint32_t src_h, + uint32_t alpha); +extern void LCDD_DrawImage( + uint16_t* pbuf, + uint32_t dwX, + uint32_t dwY, + const LcdColor_t *pImage, + uint32_t dwWidth, + uint32_t dwHeight ); + +extern void LCDD_DrawPixel( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + uint32_t color ); + +extern void LCDD_DrawLine( + uint16_t* pbuf, + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2, + uint32_t color); + +extern uint32_t LCDD_DrawLineBresenham( + uint16_t* pbuf, + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2, + uint32_t color); + +extern void LCDD_DrawRectangle( + uint16_t* pbuf, + uint32_t x, + uint32_t y, + uint32_t width, + uint32_t height, + uint32_t color); + +extern void LCDD_SetCavasBuffer( + void* pBuffer, + uint32_t wBufferSize); + +extern void LCDD_DrawStraightLine( + uint16_t* pbuf, + uint32_t dwX1, + uint32_t dwY1, + uint32_t dwX2, + uint32_t dwY2 , + uint32_t color ); +#endif /* #ifndef DRAW_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_font.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_font.h new file mode 100644 index 000000000..522cae489 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_font.h @@ -0,0 +1,108 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for draw font on LCD. + * + */ + +/** + * + * \section Purpose + * + * The font.h files declares a font structure and a LCDD_DrawChar function + * that must be implemented by a font definition file to be used with the + * LCDD_DrawString method of draw.h. + * + * The font10x14.c implements the necessary variable and function for a 10x14 + * font. + * + * \section Usage + * + * -# Declare a gFont global variable with the necessary Font information. + * -# Implement an LCDD_DrawChar function which displays the specified + * character on the LCD. + * -# Use the LCDD_DrawString method defined in draw.h to display a complete + * string. + */ + +#ifndef _LCD_FONT_ +#define _LCD_FONT_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + + +/** \brief Describes the font (width, height, supported characters, etc.) used by + * the LCD driver draw API. + */ +typedef struct _Font { + /* Font width in pixels. */ + uint8_t width; + /* Font height in pixels. */ + uint8_t height; +} Font; + +/*---------------------------------------------------------------------------- + * Variables + *----------------------------------------------------------------------------*/ + +/** Global variable describing the font being instanced. */ +extern const Font gFont; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void LCDD_DrawChar( + uint16_t* pCanvasBuffer, + uint32_t x, + uint32_t y, + uint8_t c, + uint32_t color ); + +extern void LCD_DrawString( + uint16_t* pCanvasBuffer, + uint32_t dwX, + uint32_t dwY, + const uint8_t *pString, + uint32_t color ); + + +#endif /* #ifndef LCD_FONT_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_font10x14.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_font10x14.h new file mode 100644 index 000000000..4f183d669 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_font10x14.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** + * \file + * + * Font 10x14 table definition. + * + */ + +#ifndef _LCD_FONT_10x14_ +#define _LCD_FONT_10x14_ + +#include + +/** Char set of font 10x14 */ +extern const uint8_t pCharset10x14[]; + +#endif /* #ifdef _LCD_FONT_10x14_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_gimp_image.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_gimp_image.h new file mode 100644 index 000000000..ae6dd3658 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcd_gimp_image.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _GIMP_IMAGE_ +#define _GIMP_IMAGE_ + +#include + +typedef struct _SGIMPImage{ + uint32_t dwWidth; + uint32_t dwHeight; + uint32_t dwBytes_per_pixel; /* 3:RGB, 4:RGBA */ + uint8_t* pucPixel_data ; +} SGIMPImage ; + +#endif // _GIMP_IMAGE_ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcdd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcdd.h new file mode 100644 index 000000000..c453e736a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/lcdd.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for LCD driver. + * + */ + +#ifndef LCDD_H +#define LCDD_H + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void LCDD_Initialize(uint8_t lcdMode, sXdmad * dmad, uint8_t cRotate); + +extern void LCDD_On(void); + +extern void LCDD_Off(void); + +extern void LCDD_SetBacklight (uint32_t step); + +#endif /* #ifndef LCDD_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/led.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/led.h new file mode 100644 index 000000000..e5b0b4281 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/led.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Small set of functions for simple and portable LED usage. + * + * \section Usage + * + * -# Configure one or more LEDs using LED_Configure and + * LED_ConfigureAll. + * -# Set, clear and toggle LEDs using LED_Set, LED_Clear and + * LED_Toggle. + * + * LEDs are numbered starting from 0; the number of LEDs depend on the + * board being used. All the functions defined here will compile properly + * regardless of whether the LED is defined or not; they will simply + * return 0 when a LED which does not exist is given as an argument. + * Also, these functions take into account how each LED is connected on to + * board; thus, \ref LED_Set might change the level on the corresponding pin + * to 0 or 1, but it will always light the LED on; same thing for the other + * methods. + */ + +#ifndef _LED_ +#define _LED_ + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint32_t LED_Configure( uint32_t dwLed ); + +extern uint32_t LED_Set( uint32_t dwLed ); + +extern uint32_t LED_Clear( uint32_t dwLed ); + +extern uint32_t LED_Toggle( uint32_t dwLed ); + +#endif /* #ifndef LED_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/math.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/math.h new file mode 100644 index 000000000..99a4acdab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/math.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MATH_ +#define _MATH_ + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ + +extern uint32_t min( uint32_t dwA, uint32_t dwB ); +extern uint32_t absv( int32_t lValue ); +extern uint32_t power( uint32_t dwX, uint32_t dwY ); + +#endif /* #ifndef _MATH_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/mcan_config.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/mcan_config.h new file mode 100644 index 000000000..60d643f72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/mcan_config.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _MCAN_CONFIG_ +#define _MCAN_CONFIG_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +/* Programmable Clock Source for Baud Rate is Common To Both MCAN Controllers */ +#define MCAN_PROG_CLK_PRESCALER 1 /* /1 to /256 */ +// select one of the following for the programmable clock source +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_SLOW_CLK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MAIN_CLK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_PLLA_CLK +//#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_UPLL_CLK +#define MCAN_PROG_CLK_SELECT PMC_PCK_CSS_MCK +#define MCAN_PROG_CLK_FREQ_HZ \ + ( (float) 150000000 / (float) MCAN_PROG_CLK_PRESCALER ) + +#define MCAN0_BIT_RATE_BPS 500000 +#define MCAN0_PROP_SEG 2 +#define MCAN0_PHASE_SEG1 11 +#define MCAN0_PHASE_SEG2 11 +#define MCAN0_SYNC_JUMP 4 + +#define MCAN0_FAST_BIT_RATE_BPS 2000000 +#define MCAN0_FAST_PROP_SEG 2 +#define MCAN0_FAST_PHASE_SEG1 4 +#define MCAN0_FAST_PHASE_SEG2 4 +#define MCAN0_FAST_SYNC_JUMP 2 + +#define MCAN0_NMBR_STD_FLTS 8 /* 128 max filters */ +#define MCAN0_NMBR_EXT_FLTS 8 /* 64 max filters */ +#define MCAN0_NMBR_RX_FIFO0_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_RX_DED_BUF_ELMTS 16 /* # of elements, 64 elements max */ +#define MCAN0_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN0_NMBR_TX_FIFO_Q_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN0_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_RX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN0_TX_BUF_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ + +#define MCAN1_BIT_RATE_BPS 500000 +#define MCAN1_PROP_SEG 2 +#define MCAN1_PHASE_SEG1 11 +#define MCAN1_PHASE_SEG2 11 +#define MCAN1_SYNC_JUMP 4 + +#define MCAN1_FAST_BIT_RATE_BPS 2000000 +#define MCAN1_FAST_PROP_SEG 2 +#define MCAN1_FAST_PHASE_SEG1 4 +#define MCAN1_FAST_PHASE_SEG2 4 +#define MCAN1_FAST_SYNC_JUMP 2 + +#define MCAN1_NMBR_STD_FLTS 8 /* 128 max filters */ +#define MCAN1_NMBR_EXT_FLTS 8 /* 64 max filters */ +#define MCAN1_NMBR_RX_FIFO0_ELMTS 12 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_RX_FIFO1_ELMTS 0 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_RX_DED_BUF_ELMTS 4 /* # of elements, 64 elements max */ +#define MCAN1_NMBR_TX_EVT_FIFO_ELMTS 0 /* # of elements, 32 elements max */ +#define MCAN1_NMBR_TX_DED_BUF_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN1_NMBR_TX_FIFO_Q_ELMTS 4 /* # of elements, 32 elements max */ +#define MCAN1_RX_FIFO0_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_FIFO1_ELMT_SZ 8 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_RX_BUF_ELMT_SZ 64 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ +#define MCAN1_TX_BUF_ELMT_SZ 32 /* 8, 12, 16, 20, 24, 32, 48, 64 bytes */ + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _MCAN_CONFIG_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/omnivision.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/omnivision.h new file mode 100644 index 000000000..f3310440c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/omnivision.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef OMNIVISION_H +#define OMNIVISION_H + + +/*--------------------------------------------------------------------------- + * TYPE + *---------------------------------------------------------------------------*/ +/** define a structure for ovxxxx register initialization values */ +struct ov_reg +{ + /* Register to be written */ + uint16_t reg; + /* Value to be written in the register */ + uint8_t val; +}; + + +/*--------------------------------------------------------------------------- + * DEFINITAION + *---------------------------------------------------------------------------*/ +#define OV_2640 0x00 +#define OV_2643 0x01 +#define OV_5640 0x02 +#define OV_7740 0x03 +#define OV_9740 0x04 +#define OV_UNKNOWN 0xFF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern uint8_t ov_init(Twid *pTwid); +extern void ov_DumpRegisters8(Twid *pTwid); +extern void ov_DumpRegisters16(Twid *pTwid); +extern uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist); +extern uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist); +extern uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData); +extern uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData); +extern uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val); +extern uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val); +extern void isOV5640_AF_InitDone(Twid *pTwid); +extern uint32_t ov_5640_AF_single(Twid *pTwid); +extern uint32_t ov_5640_AF_continue(Twid *pTwid); +extern uint32_t ov_5640_AFPause(Twid *pTwid); +extern uint32_t ov_5640_AFrelease(Twid *pTwid); + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ov.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ov.h new file mode 100644 index 000000000..4fee91f75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ov.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef OV_H +#define OV_H + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** Captor capture size */ +typedef struct { + uint32_t width; + uint32_t height; +}capture_size; + +extern const capture_size ov_sizes[]; +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ov_configure(Twid *pTwid, uint8_t type, uint32_t width, uint32_t heigth); +extern void ov_5640Afc_Firmware(Twid *pTwid); +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ov_7740.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ov_7740.h new file mode 100644 index 000000000..f509560b8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ov_7740.h @@ -0,0 +1,387 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _YUV_H_ +#define _YUV_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + + +/** Slave address of OMNIVISION chip. */ +#define OV_I2C_SENSOR_ADDRESS (0x42u >> 1) /* OV7740 -> 0x42 */ + + +/** Register definitions. */ +/* -------- OV7740_GAIN : (Address: 0x00) AGC Gain Control LSBs -------- */ +#define OV7740_GAIN (0x00u) + +/* -------- OV7740_BGAIN : (Address: 0x01) AWB - Blue channel gain setting -- */ +#define OV7740_BLUE_GAIN (0x01u) + +/* -------- OV7740_RGAIN : (Address: 0x02) AWB - Red channel gain setting --- */ +#define OV7740_RED_GAIN (0x02u) + +/* -------- OV7740_GGAIN : (Address: 0x03) AWB - Green channel gain setting - */ +#define OV7740_GREEN_GAIN (0x03u) + +/* -------- OV7740_REG04 : (Address: 0x04) Analog setting -------- */ +#define OV7740_REG04 (0x04u) + +/* -------- OV7740_BAVG : (Address: 0x05) B Channel Average -------- */ +#define OV7740_BLUE_AVG (0x05u) + +/* -------- OV7740_GAVG : (Address: 0x06) G Channel Average -------- */ +#define OV7740_GREEN_AVG (0x06u) + +/* -------- OV7740_RAVG : (Address: 0x07) R Channel Average -------- */ +#define OV7740_RED_AVG (0x07u) + +/* -------- OV7740_PIDH : (Address: 0x0a) Product ID number MSB -------- */ +#define OV7740_PIDH (0x0au) +#define OV7740_PIDH_DEFAULT (0x77u << 0) + +/* -------- OV7740_PIDL : (Address: 0x0b) Product ID number LSB -------- */ +#define OV7740_PIDL (0x0bu) +#define OV7740_PIDL_DEFAULT (0x40u << 0) + +/* -------- OV7740_REG0C : (Address: 0x0b) -------- */ +#define OV7740_REG0C (0x0c) +#define OV7740_REG0C_MAX_EXPOSURE_Pos (1) + /**< \brief (OV7740_REG0C) Max exposure = frame length - limit x 2 */ +#define OV7740_REG0C_MAX_EXPOSURE_Msk (0x3u << OV7740_REG0C_MAX_EXPOSURE_Pos) +#define OV7740_REG0C_MAX_EXPOSURE(value) \ +((OV7740_REG0C_MAX_EXPOSURE_Msk & ((value) << OV7740_REG0C_MAX_EXPOSURE_Pos))) +/**< \brief (OV7740_REG0C) High 8-bit MSB and LSB swap */ +#define OV7740_REG0C_BYTE_SWAP_Msk (0x1u << 3) +/**< \brief (OV7740_REG0C) output Y9,Y8...Y3,Y2,Y1,Y0 */ +#define OV7740_REG0C_BYTE_SWAP_DISABLE (0x0u << 3) +/**< \brief (OV7740_REG0C) output Y3,Y2...Y8,Y9,Y1,Y0 */ +#define OV7740_REG0C_BYTE_SWAP_ENABLE (0x1u << 3) +/**< \brief (OV7740_REG0C) YUV output, Y <-> UV swap */ +#define OV7740_REG0C_YUV_SWAP_Msk (0x1u << 4) +/**< \brief (OV7740_REG0C) output YUYVYUYV */ +#define OV7740_REG0C_YUV_SWAP_DISABLE (0x0u << 4) +/**< \brief (OV7740_REG0C) output UYVYUYVY */ +#define OV7740_REG0C_YUV_SWAP_ENABLE (0x1u << 4) +/**< \brief (OV7740_REG0C) Mirror enable */ +#define OV7740_REG0C_MIRROR_ENABLE (0x1u << 6) +/**< \brief (OV7740_REG0C) Flip enable */ +#define OV7740_REG0C_FLIP_ENABLE (0x1u << 7) + +/* -------- OV7740_REG0D : (Address: 0x0d) Analog setting -------- */ +#define OV7740_REG0D (0x0du) + +/* -------- OV7740_REG0E : (Address: 0x0e) Analog setting -------- */ +/* default value: OV7740_REG0E_BLC_BOTH|OV7740_REG0E_BLC_OPTICAL */ +#define OV7740_REG0E (0x0eu) +#define OV7740_REG0E_OUTPUT_Pos (0) +/**< \brief (OV7740_REG0E) Output driving capability */ +#define OV7740_REG0E_OUTPUT_Msk (0x3u << OV7740_REG0E_OUTPUT_Pos) +/**< \brief (OV7740_REG0E) 1x */ +#define OV7740_REG0E_OUTPUT_1X (0x0u << OV7740_REG0E_OUTPUT_Pos) +/**< \brief (OV7740_REG0E) 2x */ +#define OV7740_REG0E_OUTPUT_2X (0x1u << OV7740_REG0E_OUTPUT_Pos) +/**< \brief (OV7740_REG0E) 3x */ +#define OV7740_REG0E_OUTPUT_3X (0x2u << OV7740_REG0E_OUTPUT_Pos) +/**< \brief (OV7740_REG0E) 4x */ +#define OV7740_REG0E_OUTPUT_4X (0x3u << OV7740_REG0E_OUTPUT_Pos) +/**< \brief (OV7740_REG0E) Sleep mode */ +#define OV7740_REG0E_SLEEP_MODE (0x1u << 3) +#define OV7740_REG0E_BLC_Pos (5) +/**< \brief (OV7740_REG0E) BLC line selection */ +#define OV7740_REG0E_BLC_Msk (0x3u << OV7740_REG0E_BLC_Pos) +/**< \brief (OV7740_REG0E) Select both blue line and red line as BLC line. */ +#define OV7740_REG0E_BLC_BOTH0 (0x0u << OV7740_REG0E_BLC_Pos) +/**< \brief (OV7740_REG0E) Select red line as BLC line. */ +#define OV7740_REG0E_BLC_RED (0x1u << OV7740_REG0E_BLC_Pos) +/**< \brief (OV7740_REG0E) Select blue line as BLC line. */ +#define OV7740_REG0E_BLC_BLUE (0x2u << OV7740_REG0E_BLC_Pos) +/**< \brief (OV7740_REG0E) Select both blue line and red line as BLC line. */ +#define OV7740_REG0E_BLC_BOTH (0x3u << OV7740_REG0E_BLC_Pos) +/**< \brief (OV7740_REG0E) BLC line selection */ +#define OV7740_REG0E_BLC_LINE_Msk (0x1u << 7) +/**< \brief (OV7740_REG0E) Electrical BLC */ +#define OV7740_REG0E_BLC_LINE_ELECTRICAL (0x0u << 7) +/**< \brief (OV7740_REG0E) Optical BLC */ +#define OV7740_REG0E_BLC_LINE_OPTICAL (0x1u << 7) + +/* ----- OV7740_HAEC : (Address: 0x0f) Automatic exposure control bit [15:8] - */ +#define OV7740_HAEC (0x0fu) + +/* -------- OV7740_AEC : (Address: 0x10) Automatic exposure control bit [7:0]- */ +#define OV7740_AEC (0x10u) + +/* -------- OV7740_CLK : (Address: 0x11) Clock settings -------- */ +/**< \brief (OV7740_CLK) sysclk=XVCLK1 x PLLDIV / [(CLK[5:0]+1) x2 xPreDiv] */ +#define OV7740_CLK (0x11u) +#define OV7740_CLK_DIVIDER_Pos (0) +/**< \brief (OV7740_CLK) Clock divider */ +#define OV7740_CLK_DIVIDER_Msk (0x3fu << OV7740_CLK_DIVIDER_Pos) +#define OV7740_CLK_DIVIDER(value) \ + ((OV7740_CLK_DIVIDER_Msk & ((value) << OV7740_CLK_DIVIDER_Pos))) +#define OV7740_CLK_PLL_Pos (6) +/**< \brief (OV7740_CLK) PLL setting - Changing this value is not recommended */ +#define OV7740_CLK_PLL_Msk (0x3u << OV7740_CLK_PLL_Pos) +#define OV7740_CLK_PLL(value) \ + ((OV7740_CLK_PLL_Msk & ((value) << OV7740_CLK_PLL_Pos))) + +#define FRAME_RATE_60 0x00 +#define FRAME_RATE_30 0x01 +#define FRAME_RATE_20 0x02 +#define FRAME_RATE_15 0x03 +#define FRAME_RATE_10 0x05 +#define FRAME_RATE_7 0x07 +#define PLL_DIV_DEFAULT 0x40 +#define FRAME_RATE_7_MCK_132 0x0A +#define PLL_DIV_7_MCK_132 0xC0 + +/* -------- OV7740_REG12 : (Address: 0x12) -------- */ +#define OV7740_REG12 (0x12u) +#define OV7740_REG12_RAW_RGB (0x1u << 0) +#define OV7740_REG12_SENSOR_RAW (0x1u << 4) +#define OV7740_REG12_CC656_MODE (0x1u << 5) +#define OV7740_REG12_VSKIP (0x1u << 6) +#define OV7740_REG12_RESET (0x1u << 7) + +/* -------- OV7740_REG13 : (Address: 0x13) -------- */ +#define OV7740_REG13 (0x13u) +/**< \brief (OV7740_REG13) Exposure auto/manual control selection */ +#define OV7740_REG13_EXPOSURE_Msk (0x01u << 0) +#define OV7740_REG13_EXPOSURE_MANUAL (0x0u << 0) +#define OV7740_REG13_EXPOSURE_AUTO (0x1u << 0) +/**< \brief (OV7740_REG13) Auto white balance control selection */ +#define OV7740_REG13_WBAL_Msk (0x1u << 1) +#define OV7740_REG13_WBAL_MANUAL (0x0u << 1) +#define OV7740_REG13_WBAL_AUTO (0x1u << 1) +/**< \brief (OV7740_REG13) AGC auto/manual control selection */ +#define OV7740_REG13_AGC_Msk (0x1u << 2) +#define OV7740_REG13_AGC_MANUAL (0x0u << 2) +#define OV7740_REG13_AGC_AUTO (0x1u << 2) +/**< \brief (OV7740_REG13) LAEC enable */ +#define OV7740_REG13_LAEC_Msk (0x1u << 3) +#define OV7740_REG13_LAEC_DISABLE (0x0u << 3) +#define OV7740_REG13_LAEC_ENABLE (0x1u << 3) + /**< \brief (OV7740_REG13) Banding option */ +#define OV7740_REG13_BANDING_OPT_Msk (0x1u << 4) +/**< \brief (OV7740_REG13) Minimum exposure is limited to 1/120 or 1/100 second + when banding filter is enabled */ +#define OV7740_REG13_BANDING_OPT_LIMITED (0x0u << 4) +/**< \brief (OV7740_REG13) Minimum exposure is allowed to be less than 1/120 or + 1/100 second when banding filter is enabled */ +#define OV7740_REG13_BANDING_OPT_ENABLE (0x1u << 4) +/**< \brief (OV7740_REG13) Banding enable */ +#define OV7740_REG13_BANDING_Mask (0x1u << 5) +#define OV7740_REG13_BANDING_DISABLE (0x0u << 5) +#define OV7740_REG13_BANDING_ENABLE (0x1u << 5) +/**< \brief (OV7740_REG13) Enable frame drop function */ +#define OV7740_REG13_FRAME_DROP_Mask (0x1u << 6) +#define OV7740_REG13_FRAME_DROP_DISABLE (0x0u << 6) +#define OV7740_REG13_FRAME_DROP_ENABLE (0x1u << 6) +/**< \brief (OV7740_REG13) AEC speed selection */ +#define OV7740_REG13_AEC_Mask (0x1u << 7) +/**< \brief (OV7740_REG13) Normal */ +#define OV7740_REG13_AEC_NORMAL (0x0u << 7) +/**< \brief (OV7740_REG13) Faster AEC correction */ +#define OV7740_REG13_AEC_FASTER (0x1u << 7) + +/* -------- OV7740_REG14 : (Address: 0x14) -------- */ +#define OV7740_REG14 (0x14u) + +/* -------- OV7740_REG15 : (Address: 0x15) -------- */ +#define OV7740_REG15 (0x15u) +#define OV7740_REG15_GAIN_Pos (0) +/**< \brief (OV7740_REG15) AGC MSBs (digital gain) (LSBs in GAIN[7:0]) */ +#define OV7740_REG15_GAIN_Msk (0x3u << OV7740_REG15_GAIN_Pos) +#define OV7740_REG15_GAIN(value) \ + ((OV7740_REG15_GAIN_Msk & ((value) << OV7740_REG15_GAIN_Pos))) +/**< \brief (OV7740_REG15) Night mode triggering point */ +#define OV7740_REG15_NIGHT_Mask (0x3u << 2) +/**< \brief (OV7740_REG15) 2x gain */ +#define OV7740_REG15_NIGHT_2X_GAIN (0x0u << 2) +/**< \brief (OV7740_REG15) 4x gain */ +#define OV7740_REG15_NIGHT_4X_GAIN (0x1u << 2) +/**< \brief (OV7740_REG15) 8x gain */ +#define OV7740_REG15_NIGHT_8X_GAIN (0x2u << 2) +/**< \brief (OV7740_REG15) 16x gain */ +#define OV7740_REG15_NIGHT_16X_GAIN (0x3u << 2) +/**< \brief (OV7740_REG15) Ceiling of inserting frames */ +#define OV7740_REG15_CEIL_Mask (0x3u << 4) +/**< \brief (OV7740_REG15) Up to 0 frames */ +#define OV7740_REG15_CEIL_0 (0x0u << 4) +/**< \brief (OV7740_REG15) Up to 1 frames */ +#define OV7740_REG15_CEIL_1 (0x1u << 4) +/**< \brief (OV7740_REG15) Up to 2 frames */ +#define OV7740_REG15_CEIL_2 (0x2u << 4) +/**< \brief (OV7740_REG15) Up to 3 frames */ +#define OV7740_REG15_CEIL_3 (0x3u << 4) +/**< \brief (OV7740_REG15) Up to 7 frames */ +#define OV7740_REG15_CEIL_7 (0x7u << 4) +/**< \brief (OV7740_REG15) Enable inserting frames in night mode */ +#define OV7740_REG15_ENABLE_NIGHT (0x1u << 7) + +/* OV7740_REG16 : (Address: 0x16) */ +#define OV7740_REG16 (0x16u) + +/* + * OV7740_AHSTART : (Address: 0x17) Sensor Horizontal output start point + * 8 MSBs (LSBs in REG16[1:0]) + */ +#define OV7740_AHSTART (0x17u) + +/* + * OV7740_AHSIZE : (Address: 0x18) Sensor Horizontal output size 8 MSBs + * (LSBs in REG16[4:3]) + */ +#define OV7740_AHSIZE (0x18u) + +/* + * OV7740_AVSTART : (Address: 0x19) Sensor Vertical output start point 8 MSBs + * (LSBs in REG16[2]) + */ +#define OV7740_AVSTART (0x19u) + +/* + * OV7740_AVSIZE : (Address: 0x1a) Sensor Vertical output size 8 MSBs + * (LSBs in REG16[5]) + */ +#define OV7740_AVSIZE (0x1au) + +/* -------- OV7740_PIXEL_SHIFT : (Address: 0x1b) Pixel shift -------- */ +#define OV7740_PIXEL_SHIFT (0x1bu) + +/* -------- OV7740_MIDH : (Address: 0x1c) Manufacturer ID Byte - High ------- */ +#define OV7740_MIDH (0x1cu) +#define OV7740_MIDH_DEFAULT (0x7fu << 0) + +/* -------- OV7740_MIDL : (Address: 0x1d) Manufacturer ID Byte - Low -------- */ +#define OV7740_MIDL (0x1du) +#define OV7740_MIDL_DEFAULT (0xa2u << 0) + +/* -------- OV7740_REG1E : (Address: 0x1e) -------- */ +#define OV7740_REG1E (0x1eu) + +/* -------- OV7740_REG1F : (Address: 0x1f) -------- */ +#define OV7740_REG1F (0x1fu) + +/* -------- OV7740_REG1E : (Address: 0x1e) -------- */ +#define OV7740_REG1E (0x1eu) + +/* -------- OV7740_REG20 : (Address: 0x20) -------- */ +#define OV7740_REG20 (0x20u) + +/* -------- OV7740_REG21 : (Address: 0x21) -------- */ +#define OV7740_REG21 (0x21u) + +/* OV7740_REG21 : (Address: 0x24) Luminance signal high range for AEC/AGC + * operation. + */ +#define OV7740_WPT (0x24u) + +/* + * OV7740_REG21 : (Address: 0x25) Luminance signal low range for AEC/AGC + * operation + */ +#define OV7740_BPT (0x25u) + +/* --- OV7740_VPT : (Address: 0x26) effective only in AEG/AGC fast mode ---- */ +#define OV7740_VPT (0x26u) + +/* -------- OV7740_REG27 : (Address: 0x27) -------- */ +#define OV7740_REG27 (0x27u) +/**< \brief (OV7740_REG27) Black sun cancellation enable */ +#define OV7740_REG27_BLACKSUN (0x1u << 7) + +/* -------- OV7740_REG28 : (Address: 0x28) -------- */ +#define OV7740_REG28 (0x28u) +/**< \brief (OV7740_REG28) VSYNC polarity */ +#define OV7740_REG28_VSYNC_Msk (0x1u << 1) +/**< \brief (OV7740_REG28) Positive */ +#define OV7740_REG28_VSYNC_POSITIVE (0x1u << 0) +/**< \brief (OV7740_REG28) Negative */ +#define OV7740_REG28_VSYNC_NEGATIVE (0x1u << 1) +/**< \brief (OV7740_REG28) No VSYNC output option */ +#define OV7740_REG28_VSYNC_OUTPUT_Msk (0x1u << 3) +/**< \brief (OV7740_REG28) Still output VSYNC when frame drop */ +#define OV7740_REG28_VSYNC_OUTPUT_STILL (0x0u << 3) +/**< \brief (OV7740_REG28) No VSYNC output when frame drop */ +#define OV7740_REG28_VSYNC_OUTPUT_NONE (0x1u << 3) +/**< \brief (OV7740_REG28) HREF polarity */ +#define OV7740_REG28_HREF_Msk (0x1u << 4) +/**< \brief (OV7740_REG28) Output positive HREF */ +#define OV7740_REG28_HREF_POSITIVE (0x0u << 4) + /**< \brief (OV7740_REG28) Output negative HREF for data valid */ +#define OV7740_REG28_HREF_NEGATIVE (0x1u << 4) +/**< \brief (OV7740_REG28) HSYNC polarity */ +#define OV7740_REG28_HSYNC_Msk (0x1u << 5) +/**< \brief (OV7740_REG28) Positive */ +#define OV7740_REG28_HSYNC_POSITIVE (0x0u << 5) +/**< \brief (OV7740_REG28) Negative */ +#define OV7740_REG28_HSYNC_NEGATIVE (0x1u << 5) +/**< \brief (OV7740_REG28) HREF pin output swap */ +#define OV7740_REG28_HREF_OUTPUT_Msk (0x1u << 6) +/**< \brief (OV7740_REG28) HREF */ +#define OV7740_REG28_HREF_OUTPUT_HREF (0x0u << 6) +/**< \brief (OV7740_REG28) HSYNC */ +#define OV7740_REG28_HREF_OUTPUT_HSYNC (0x1u << 6) +/**< \brief (OV7740_REG28) Output data bit reverse option */ +#define OV7740_REG28_OUTPUT_REVERSE (0x1u << 7) + +/* -------- OV7740_REG65 : (Address: 0x65) -------- */ +#define OV7740_REG65 (0x65u) +/**< \brief (OV7740_REG65) Output data bit swap option */ +#define OV7740_REG65_BIT_SWAP_Msk (0x1u << 3) + /**< \brief (OV7740_REG65) Output DATA[9:0] */ +#define OV7740_REG65_BIT_SWAP_NORMAL (0x0u << 3) +/**< \brief (OV7740_REG65) Output DATA[0:9] */ +#define OV7740_REG65_BIT_SWAP_REVERSE (0x1u << 3) + +/* -------- OV7740_YUV422CTRL : (Address: 0xd9) -------- */ +#define OV7740_YUV422CTRL (0xd9u) + /**< \brief (OV7740_YUV422CTRL) cnv_opt */ +#define OV7740_YUV422CTRL_CNV_OPT_Msk (0x1u << 0) +/**< \brief (OV7740_YUV422CTRL) Average mode */ +#define OV7740_YUV422CTRL_CNV_OPT_AVERAGE (0x0u << 0) +/**< \brief (OV7740_YUV422CTRL) Drop mode */ +#define OV7740_YUV422CTRL_CNV_OPT_DROP (0x1u << 0) + +/**< \brief (OV7740_YUV422CTRL) v_first */ +#define OV7740_YUV422CTRL_V_FIRST_Msk (0x1u << 1) +/**< \brief (OV7740_YUV422CTRL) Output line will be YUYV... */ +#define OV7740_YUV422CTRL_V_FIRST_YUYV (0x0u << 1) +/**< \brief (OV7740_YUV422CTRL) Output line will be YVYU... (it will affect +definition of U/V in SDE. If it is set, all registers in SDE about U/V must be +swapped */ +#define OV7740_YUV422CTRL_V_FIRST_YVYU (0x1u << 1) + + + +#endif // #ifndef _YUV_H_ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ovyuv.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ovyuv.h new file mode 100644 index 000000000..9adac3d4b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/ovyuv.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _YUV_H_ +#define _YUV_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + + +/*--------------------------------------------------------------------------- + * Exported variable + *---------------------------------------------------------------------------*/ +extern const struct ov_reg ov2640_yuv_vga[]; +extern const struct ov_reg ov2640_yuv_qvga[]; + +extern const struct ov_reg ov2643_yuv_vga[]; +extern const struct ov_reg ov2643_yuv_swvga[]; +extern const struct ov_reg ov2643_yuv_uxga[]; +extern const struct ov_reg ov2643_yuv_qvga[]; + +extern const struct ov_reg ov5640_yuv_vga[]; +extern const struct ov_reg ov5640_yuv_sxga[]; +extern const struct ov_reg ov5640_afc[]; + +extern const struct ov_reg OV7740_VGA_YUV422[]; +extern const struct ov_reg OV7740_QVGA_YUV422[]; +extern const struct ov_reg OV7740_QVGA_RGB888[]; +extern const struct ov_reg OV7740_QQVGA_YUV422[]; +extern const struct ov_reg OV7740_QQVGA_RGB888[]; +extern const struct ov_reg OV7740_CIF_YUV422[]; +extern const struct ov_reg OV7740_TEST_PATTERN[]; + + +extern const struct ov_reg ov9740_yuv_sxga[]; +extern const struct ov_reg ov9740_yuv_vga[]; + +#endif // #ifndef _YUV_H_ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/rtc_calib.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/rtc_calib.h new file mode 100644 index 000000000..331cf3add --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/rtc_calib.h @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Real Time Clock calibration (RTC) . + * + */ + +/** RTC crystal **/ + + +typedef struct{ + int8_t Tempr; + int16_t PPM; + uint8_t NEGPPM; + uint8_t HIGHPPM; + uint16_t CORRECTION; + }RTC_PPMLookup; + + +extern void RTC_ClockCalibration( Rtc* pRtc, int32_t CurrentTempr); diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/s25fl1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/s25fl1.h new file mode 100644 index 000000000..927d06891 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/s25fl1.h @@ -0,0 +1,252 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for the S25fl1 Serial Flash driver. + * + */ + +#ifndef S25FL1_H +#define S25FL1_H +#define USE_QSPI_DMA +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +#define Size(pAt25) ((pAt25)->pDesc->size) +#define PageSize(pAt25) ((pAt25)->pDesc->pageSize) +#define BlockSize(pAt25) ((pAt25)->pDesc->blockSize) +#define Name(pAt25) ((pAt25)->pDesc->name) +#define ManId(pAt25) (((pAt25)->pDesc->jedecId) & 0xFF) +#define PageNumber(pAt25) (Size(pAt25) / PageSize(pAt25)) +#define BlockNumber(pAt25) (Size(pAt25) / BlockSize(pAt25)) +#define PagePerBlock(pAt25) (BlockSize(pAt25) / PageSize(pAt25)) +#define BlockEraseCmd(pAt25) ((pAt25)->pDesc->blockEraseCmd) + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/** Device is protected, operation cannot be carried out. */ +#define ERROR_PROTECTED 1 +/** Device is busy executing a command. */ +#define ERROR_BUSY 2 +/** There was a problem while trying to program page data. */ +#define ERROR_PROGRAM 3 +/** There was an SPI communication error. */ +#define ERROR_SPI 4 + +/** Device ready/busy status bit. */ +#define STATUS_RDYBSY (1 << 0) +/** Device is ready. */ +#define STATUS_RDYBSY_READY (0 << 0) +/** Device is busy with internal operations. */ +#define STATUS_RDYBSY_BUSY (1 << 0) +/** Write enable latch status bit. */ +#define STATUS_WEL (1 << 1) +/** Device is not write enabled. */ +#define STATUS_WEL_DISABLED (0 << 1) +/** Device is write enabled. */ +#define STATUS_WEL_ENABLED (1 << 1) +/** Software protection status bit-field. */ +#define STATUS_SWP (3 << 2) +/** All sectors are software protected. */ +#define STATUS_SWP_PROTALL (3 << 2) +/** Some sectors are software protected. */ +#define STATUS_SWP_PROTSOME (1 << 2) +/** No sector is software protected. */ +#define STATUS_SWP_PROTNONE (0 << 2) +/** Write protect pin status bit. */ +#define STATUS_WPP (1 << 4) +/** Write protect signal is not asserted. */ +#define STATUS_WPP_NOTASSERTED (0 << 4) +/** Write protect signal is asserted. */ +#define STATUS_WPP_ASSERTED (1 << 4) +/** Erase/program error bit. */ +#define STATUS_EPE (1 << 5) +/** Erase or program operation was successful. */ +#define STATUS_EPE_SUCCESS (0 << 5) +/** Erase or program error detected. */ +#define STATUS_EPE_ERROR (1 << 5) +/** Sector protection registers locked bit. */ +#define STATUS_SPRL (1 << 7) +/** Sector protection registers are unlocked. */ +#define STATUS_SPRL_UNLOCKED (0 << 7) +/** Sector protection registers are locked. */ +#define STATUS_SPRL_LOCKED (1 << 7) + +/** Quad enable bit */ +#define STATUS_QUAD_ENABLE (1 << 1) + /** Quad enable bit */ +#define STATUS_WRAP_ENABLE (0 << 4) + + /** Latency control bits */ +#define STATUS_LATENCY_CTRL (0xF << 0) + +#define STATUS_WRAP_BYTE (1 << 5) + +#define BLOCK_PROTECT_Msk (7 << 2) + +#define TOP_BTM_PROTECT_Msk (1 << 5) + +#define SEC_PROTECT_Msk (1 << 6) + +#define CHIP_PROTECT_Msk (0x1F << 2) + +/** Read array command code. */ +#define READ_ARRAY 0x0B +/** Read array (low frequency) command code. */ +#define READ_ARRAY_LF 0x03 +/** Fast Read array command code. */ +#define READ_ARRAY_DUAL 0x3B +/** Fast Read array command code. */ +#define READ_ARRAY_QUAD 0x6B +/** Fast Read array command code. */ +#define READ_ARRAY_DUAL_IO 0xBB +/** Fast Read array command code. */ +#define READ_ARRAY_QUAD_IO 0xEB +/** Block erase command code (4K block). */ +#define BLOCK_ERASE_4K 0x20 +/** Block erase command code (32K block). */ +#define BLOCK_ERASE_32K 0x52 +/** Block erase command code (64K block). */ +#define BLOCK_ERASE_64K 0xD8 +/** Chip erase command code 1. */ +#define CHIP_ERASE_1 0x60 +/** Chip erase command code 2. */ +#define CHIP_ERASE_2 0xC7 +/** Byte/page program command code. */ +#define BYTE_PAGE_PROGRAM 0x02 +/** Sequential program mode command code 1. */ +#define SEQUENTIAL_PROGRAM_1 0xAD +/** Sequential program mode command code 2. */ +#define SEQUENTIAL_PROGRAM_2 0xAF +/** Write enable command code. */ +#define WRITE_ENABLE 0x06 +/** Write disable command code. */ +#define WRITE_DISABLE 0x04 +/** Protect sector command code. */ +#define PROTECT_SECTOR 0x36 +/** Unprotected sector command code. */ +#define UNPROTECT_SECTOR 0x39 +/** Read sector protection registers command code. */ +#define READ_SECTOR_PROT 0x3C +/** Read status register command code. */ +#define READ_STATUS_1 0x05 + /** Read status register command code. */ +#define READ_STATUS_2 0x35 + /** Read status register command code. */ +#define READ_STATUS_3 0x33 +/** Write status register command code. */ +#define WRITE_STATUS 0x01 +/** Read manufacturer and device ID command code. */ +#define READ_JEDEC_ID 0x9F +/** Deep power-down command code. */ +#define DEEP_PDOWN 0xB9 +/** Resume from deep power-down command code. */ +#define RES_DEEP_PDOWN 0xAB +/** Resume from deep power-down command code. */ +#define SOFT_RESET_ENABLE 0x66 +/** Resume from deep power-down command code. */ +#define SOFT_RESET 0x99 +/** Resume from deep power-down command code. */ +#define WRAP_ENABLE 0x77 + +/** SPI Flash Manufacturer JEDEC ID */ +#define ATMEL_SPI_FLASH 0x1F +#define ST_SPI_FLASH 0x20 +#define WINBOND_SPI_FLASH 0xEF +#define MACRONIX_SPI_FLASH 0xC2 +#define SST_SPI_FLASH 0xBF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t S25FL1D_ReadJedecId(void); + +void S25FL1D_InitFlashInterface(uint8_t Mode); + +void S25FL1D_SoftReset(void); + +unsigned char S25FL1D_Unprotect(void); + +unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size); + +void S25FL1D_QuadMode(uint8_t Enable); + +void S25FL1D_EnableWrap(uint8_t ByetAlign); + +void S25FL1D_SetReadLatencyControl(uint8_t Latency); + +unsigned char S25FL1D_EraseChip(void); + +unsigned char S25FL1D_EraseSector( unsigned int address); + +unsigned char S25FL1D_Erase64KBlock( unsigned int address); + +unsigned char S25FL1D_Write( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t Secure); + +extern unsigned char S25FL1D_Read( + uint32_t *pData, + uint32_t size, + uint32_t address); + +extern unsigned char S25FL1D_ReadDual( + uint32_t *pData, + uint32_t size, + uint32_t address); + +extern unsigned char S25FL1D_ReadQuad( + uint32_t *pData, + uint32_t size, + uint32_t address); + +extern unsigned char S25FL1D_ReadDualIO( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t ContMode, + uint8_t Secure); + +extern unsigned char S25FL1D_ReadQuadIO( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t ContMode, + uint8_t Secure); + +#endif // #ifndef S25FL1_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/syscalls.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/syscalls.h new file mode 100644 index 000000000..0391c9a3b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/syscalls.h @@ -0,0 +1,65 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file syscalls.h + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern caddr_t _sbrk ( int incr ); + +extern int link( char *old, char *new ); + +extern int _close( int file ); + +extern int _fstat( int file, struct stat *st ); + +extern int _isatty( int file ); + +extern int _lseek( int file, int ptr, int dir ); + +extern int _read(int file, char *ptr, int len); + +extern int _write( int file, char *ptr, int len ); diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/wm8904.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/wm8904.h new file mode 100644 index 000000000..7072f95ea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/include/wm8904.h @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +#ifndef WM8904_H +#define WM8904_H + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define WM8904_CSB_STATE (0x0 << 0) + +/** Slave address */ +#define WM8904_SLAVE_ADDRESS 0x1a | WM8904_CSB_STATE +#define CS2100_SLAVE_ADDRESS 0x4E + + +/** Reset register*/ +#define WM8904_REG_RESET 0x00 + +/** Bias control 0 register*/ +#define WM8904_REG_BIAS_CTRL0 0x04 + +/** VMID control 0 register*/ +#define WM8904_REG_VMID_CTRL0 0x05 + +/** MIC Bias control 0 register*/ +#define WM8904_REG_MICBIAS_CTRL0 0x06 + +/** Bias control 1 register*/ +#define WM8904_REG_BIAS_CTRL1 0x07 + +/** Power management control 0 register*/ +#define WM8904_REG_POWER_MANG0 0x0C +/** Power management control 2 register*/ +#define WM8904_REG_POWER_MANG2 0x0E +/** Power management control 3 register*/ +#define WM8904_REG_POWER_MANG3 0x0F +/** Power management control 6 register*/ +#define WM8904_REG_POWER_MANG6 0x12 + +/** Clock rate0 register*/ +#define WM8904_REG_CLOCK_RATE0 0x14 +/** Clock rate1 register*/ +#define WM8904_REG_CLOCK_RATE1 0x15 + +/** Clock rate2 register*/ +#define WM8904_REG_CLOCK_RATE2 0x16 + +/** Audio interface0 register*/ +#define WM8904_REG_AUD_INF0 0x18 + +/** Audio interface1 register*/ +#define WM8904_REG_AUD_INF1 0x19 +/** Audio interface2 register*/ +#define WM8904_REG_AUD_INF2 0x1A +/** Audio interface3 register*/ +#define WM8904_REG_AUD_INF3 0x1B + +/** ADC digital 0 register*/ +#define WM8904_REG_ADC_DIG0 0x20 +/** ADC digital 1 register*/ +#define WM8904_REG_ADC_DIG1 0x21 + +/** Analogue left input 0 register*/ +#define WM8904_REG_ANALOGUE_LIN0 0x2C +/** Analogue right input 0 register*/ +#define WM8904_REG_ANALOGUE_RIN0 0x2D + +/** Analogue left input 1 register*/ +#define WM8904_REG_ANALOGUE_LIN1 0x2E +/** Analogue right input 1 register*/ +#define WM8904_REG_ANALOGUE_RIN1 0x2F + +/** Analogue left output 1 register*/ +#define WM8904_REG_ANALOGUE_LOUT1 0x39 +/** Analogue right output 1 register*/ +#define WM8904_REG_ANALOGUE_ROUT1 0x3A + +/** Analogue left output 2 register*/ +#define WM8904_REG_ANALOGUE_LOUT2 0x3B +/** Analogue right output 2 register*/ +#define WM8904_REG_ANALOGUE_ROUT2 0x3C + +/** Analogue output 12 ZC register*/ +#define WM8904_REG_ANALOGUE_OUT12ZC 0x3D + +/** DC servo 0 register*/ +#define WM8904_REG_DC_SERVO0 0x43 + +/** Analogue HP 0 register*/ +#define WM8904_REG_ANALOGUE_HP0 0x5A + +/** Charge pump 0 register*/ +#define WM8904_REG_CHARGE_PUMP0 0x62 + +/** Class W 0 register*/ +#define WM8904_REG_CLASS0 0x68 + +/** FLL control 1 register*/ +#define WM8904_REG_FLL_CRTL1 0x74 +/** FLL control 2 register*/ +#define WM8904_REG_FLL_CRTL2 0x75 +/** FLL control 3 register*/ +#define WM8904_REG_FLL_CRTL3 0x76 +/** FLL control 4 register*/ +#define WM8904_REG_FLL_CRTL4 0x77 +/** FLL control 5 register*/ +#define WM8904_REG_FLL_CRTL5 0x78 + +/** DUMMY register*/ +#define WM8904_REG_END 0xFF + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint16_t WM8904_Read(Twid *pTwid, uint32_t device, uint32_t regAddr); +extern void WM8904_Write(Twid *pTwid, uint32_t device, uint32_t regAddr, + uint16_t data); +extern uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK); +extern uint8_t WM8904_VolumeSet(Twid *pTwid, uint32_t device, uint16_t value); +extern void WM8904_IN2R_IN1L(Twid *pTwid, uint32_t device); +#endif // WM8904_H + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_flash.ld new file mode 100644 index 000000000..21f8553db --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_flash.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_sdram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_sdram.ld new file mode 100644 index 000000000..4a6936cea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_sdram.ld @@ -0,0 +1,10 @@ + +SECTIONS +{ + _sdram_lma = .; + sdram_region : + AT ( _sdram_lma ) + { + *(sdram_region) + } >sdram +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_sram.ld new file mode 100644 index 000000000..b351d1660 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/sam_sram.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + . = ALIGN(8); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(8); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv7-ek-sram.gdb b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv7-ek-sram.gdb new file mode 100644 index 000000000..ec6bf931d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv7-ek-sram.gdb @@ -0,0 +1,28 @@ +#************************************************* +# +# Connect to J-Link and debug application in sram. +# + +# define 'reset' command +define reset + +# Connect to the J-Link gdb server +target remote localhost:2331 + +# Reset the chip to get to a known state +monitor reset + +# Load the program +load + +# Reset peripheral (RSTC_CR) +set *0x400E1800 = 0xA5000004 + +# Initializing PC and stack pointer +mon reg sp = (0x20400000) +set *0x20400004 = *0x20400004 & 0xFFFFFFFE +mon reg pc=(0x20400004) +info reg + +# end of 'reset' command +end diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j19_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j19_flash.ld new file mode 100644 index 000000000..e19661a6c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j19_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71J19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j19_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j19_sram.ld new file mode 100644 index 000000000..017f4ed9e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j19_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71J19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j20_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j20_flash.ld new file mode 100644 index 000000000..b83479b4e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j20_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71J20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00080000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j20_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j20_sram.ld new file mode 100644 index 000000000..28faa4111 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j20_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71J20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00080000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j21_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j21_flash.ld new file mode 100644 index 000000000..4ba29f488 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j21_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71J21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j21_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j21_sram.ld new file mode 100644 index 000000000..82beb4acd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71j21_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71J21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n19_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n19_flash.ld new file mode 100644 index 000000000..c84448698 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n19_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71N19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n19_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n19_sram.ld new file mode 100644 index 000000000..7289c303f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n19_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71N19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n20_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n20_flash.ld new file mode 100644 index 000000000..3c7d068f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n20_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71N20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n20_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n20_sram.ld new file mode 100644 index 000000000..8f28e06cd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n20_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71N20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n21_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n21_flash.ld new file mode 100644 index 000000000..8720b0599 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n21_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71N21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n21_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n21_sram.ld new file mode 100644 index 000000000..d8b674d68 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71n21_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71N21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00040000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q19_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q19_flash.ld new file mode 100644 index 000000000..dfef34b64 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q19_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71Q19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00080000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q19_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q19_sram.ld new file mode 100644 index 000000000..f7bc38a57 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q19_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71Q19 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00080000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q20_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q20_flash.ld new file mode 100644 index 000000000..e6ce226a6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q20_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71Q20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q20_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q20_sram.ld new file mode 100644 index 000000000..431ac9cd5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q20_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71Q20 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00100000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q21_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q21_flash.ld new file mode 100644 index 000000000..b5b32a1ef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q21_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q21_sram.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q21_sram.ld new file mode 100644 index 000000000..5d23f2dfe --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/samv71q21_sram.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal SRAM on the ATSAMV71Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_sram.ld +INCLUDE sam_sdram.ld diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/startup_sam.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/startup_sam.c new file mode 100644 index 000000000..a494f4cc3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/gcc/startup_sam.c @@ -0,0 +1,394 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#include "samv71.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); +void LowLevelInit(void); + + +/* Default empty handler */ +void Dummy_Handler(void); + +#pragma weak NMI_Handler=Dummy_Handler +#pragma weak HardFault_Handler=Dummy_Handler +#pragma weak MemManage_Handler=Dummy_Handler +#pragma weak BusFault_Handler=Dummy_Handler +#pragma weak UsageFault_Handler=Dummy_Handler +#pragma weak SVC_Handler=Dummy_Handler +#pragma weak DebugMon_Handler=Dummy_Handler +#pragma weak PendSV_Handler=Dummy_Handler +#pragma weak SysTick_Handler=Dummy_Handler + +/* Peripherals handlers */ +#pragma weak SUPC_Handler=Dummy_Handler +#pragma weak RSTC_Handler=Dummy_Handler +#pragma weak RTC_Handler=Dummy_Handler +#pragma weak RTT_Handler=Dummy_Handler +#pragma weak WDT_Handler=Dummy_Handler +#pragma weak PMC_Handler=Dummy_Handler +#pragma weak EFC_Handler=Dummy_Handler +#pragma weak UART0_Handler=Dummy_Handler +#pragma weak UART1_Handler=Dummy_Handler +#pragma weak PIOA_Handler=Dummy_Handler +#pragma weak PIOB_Handler=Dummy_Handler +#ifdef _SAMV71_PIOC_INSTANCE_ +#pragma weak PIOC_Handler=Dummy_Handler +#endif /* _SAM_PIOC_INSTANCE_ */ +#pragma weak USART0_Handler=Dummy_Handler +#pragma weak USART1_Handler=Dummy_Handler +#pragma weak USART2_Handler=Dummy_Handler +#pragma weak PIOD_Handler=Dummy_Handler +#ifdef _SAMV71_PIOE_INSTANCE_ +#pragma weak PIOE_Handler=Dummy_Handler +#endif /* _SAM_PIOE_INSTANCE_ */ +#ifdef _SAMV71_HSMCI_INSTANCE_ +#pragma weak HSMCI_Handler=Dummy_Handler +#endif /* _SAM_HSMCI_INSTANCE_ */ +#pragma weak TWIHS0_Handler=Dummy_Handler +#pragma weak TWIHS1_Handler=Dummy_Handler +#pragma weak SPI0_Handler=Dummy_Handler +#pragma weak SSC_Handler=Dummy_Handler +#pragma weak TC0_Handler=Dummy_Handler +#pragma weak TC1_Handler=Dummy_Handler +#pragma weak TC2_Handler=Dummy_Handler +#ifdef _SAMV71_TC1_INSTANCE_ +#pragma weak TC3_Handler=Dummy_Handler +#endif /* _SAM_TC1_INSTANCE_ */ +#ifdef _SAMV71_TC1_INSTANCE_ +#pragma weak TC4_Handler=Dummy_Handler +#endif /* _SAM_TC1_INSTANCE_ */ +#ifdef _SAMV71_TC1_INSTANCE_ +#pragma weak TC5_Handler=Dummy_Handler +#endif /* _SAM_TC1_INSTANCE_ */ +#pragma weak AFEC0_Handler=Dummy_Handler +#ifdef _SAMV71_DACC_INSTANCE_ +#pragma weak DACC_Handler=Dummy_Handler +#endif /* _SAM_DACC_INSTANCE_ */ +#pragma weak PWM0_Handler=Dummy_Handler +#pragma weak ICM_Handler=Dummy_Handler +#pragma weak ACC_Handler=Dummy_Handler +#pragma weak USBHS_Handler=Dummy_Handler +#pragma weak MCAN0_Handler=Dummy_Handler +#pragma weak MCAN0_Line1_Handler=Dummy_Handler +#pragma weak MCAN1_Handler=Dummy_Handler +#pragma weak MCAN1_Line1_Handler=Dummy_Handler +#pragma weak GMAC_Handler=Dummy_Handler +#pragma weak GMACQ1_Handler=Dummy_Handler +#pragma weak GMACQ2_Handler=Dummy_Handler +#pragma weak AFEC1_Handler=Dummy_Handler +#ifdef _SAMV71_TWIHS2_INSTANCE_ +#pragma weak TWIHS2_Handler=Dummy_Handler +#endif /* _SAM_TWI2_INSTANCE_ */ +#pragma weak SPI1_Handler=Dummy_Handler +#pragma weak QSPI_Handler=Dummy_Handler +#pragma weak UART2_Handler=Dummy_Handler +#pragma weak UART3_Handler=Dummy_Handler +#pragma weak UART4_Handler=Dummy_Handler +#ifdef _SAMV71_TC2_INSTANCE_ +#pragma weak TC6_Handler=Dummy_Handler +#endif /* _SAM_TC2_INSTANCE_ */ +#ifdef _SAMV71_TC2_INSTANCE_ +#pragma weak TC7_Handler=Dummy_Handler +#endif /* _SAM_TC2_INSTANCE_ */ +#ifdef _SAMV71_TC2_INSTANCE_ +#pragma weak TC8_Handler=Dummy_Handler +#endif /* _SAM_TC2_INSTANCE_ */ +#pragma weak TC9_Handler=Dummy_Handler +#pragma weak TC10_Handler=Dummy_Handler +#pragma weak TC11_Handler=Dummy_Handler +#pragma weak MLB_Handler=Dummy_Handler +#pragma weak AES_Handler=Dummy_Handler +#pragma weak TRNG_Handler=Dummy_Handler +#pragma weak XDMAC_Handler=Dummy_Handler +#pragma weak ISI_Handler=Dummy_Handler +#pragma weak PWM1_Handler=Dummy_Handler +#pragma weak FPU_Handler=Dummy_Handler +#ifdef _SAMV71_SDRAMC_INSTANCE_ +#pragma weak SDRAMC_Handler=Dummy_Handler +#endif /* _SAM_SDRAMC_INSTANCE_ */ +#pragma weak RSWDT_Handler=Dummy_Handler +#pragma weak CCF_Handler=Dummy_Handler +#pragma weak CCW_Handler=Dummy_Handler + + +/* Exception Table */ +__attribute__ ((section(".vectors"))) +const DeviceVectors exception_table = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void*) (&_estack), + + .pfnReset_Handler = (void*) Reset_Handler, + .pfnNMI_Handler = (void*) NMI_Handler, + .pfnHardFault_Handler = (void*) HardFault_Handler, + .pfnMemManage_Handler = (void*) MemManage_Handler, + .pfnBusFault_Handler = (void*) BusFault_Handler, + .pfnUsageFault_Handler = (void*) UsageFault_Handler, + .pfnReserved1_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved2_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved3_Handler = (void*) (0UL), /* Reserved */ + .pfnReserved4_Handler = (void*) (0UL), /* Reserved */ + .pfnSVC_Handler = (void*) SVC_Handler, + .pfnDebugMon_Handler = (void*) DebugMon_Handler, + .pfnReserved5_Handler = (void*) (0UL), /* Reserved */ + .pfnPendSV_Handler = (void*) PendSV_Handler, + .pfnSysTick_Handler = (void*) SysTick_Handler, + + /* Configurable interrupts */ + .pfnSUPC_Handler = (void*) SUPC_Handler, /* 0 Supply Controller */ + .pfnRSTC_Handler = (void*) RSTC_Handler, /* 1 Reset Controller */ + .pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real Time Clock */ + .pfnRTT_Handler = (void*) RTT_Handler, /* 3 Real Time Timer */ + .pfnWDT_Handler = (void*) WDT_Handler, /* 4 Watchdog Timer 0 */ + .pfnPMC_Handler = (void*) PMC_Handler, /* 5 Power Management Controller */ + .pfnEFC_Handler = (void*) EFC_Handler, /* 6 Enhanced Embedded Flash Controller */ + .pfnUART0_Handler = (void*) UART0_Handler, /* 7 UART 0 */ + .pfnUART1_Handler = (void*) UART1_Handler, /* 8 UART 1 */ + .pvReserved9 = (void*) (0UL), /* 9 Reserved */ + .pfnPIOA_Handler = (void*) PIOA_Handler, /* 10 Parallel I/O Controller A */ + .pfnPIOB_Handler = (void*) PIOB_Handler, /* 11 Parallel I/O Controller B */ +#ifdef _SAMV71_PIOC_INSTANCE_ + .pfnPIOC_Handler = (void*) PIOC_Handler, /* 12 Parallel I/O Controller C */ +#else + .pvReserved12 = (void*) (0UL), /* 12 Reserved */ +#endif /* _SAMV71_PIOC_INSTANCE_ */ + .pfnUSART0_Handler = (void*) USART0_Handler, /* 13 USART 0 */ + .pfnUSART1_Handler = (void*) USART1_Handler, /* 14 USART 1 */ + .pfnUSART2_Handler = (void*) USART2_Handler, /* 15 USART 2 */ + .pfnPIOD_Handler = (void*) PIOD_Handler, /* 16 Parallel I/O Controller D */ +#ifdef _SAMV71_PIOE_INSTANCE_ + .pfnPIOE_Handler = (void*) PIOE_Handler, /* 17 Parallel I/O Controller E */ +#else + .pvReserved17 = (void*) (0UL), /* 17 Reserved */ +#endif /* _SAMV71_PIOE_INSTANCE_ */ +#ifdef _SAMV71_HSMCI_INSTANCE_ + .pfnHSMCI_Handler = (void*) HSMCI_Handler, /* 18 Multimedia Card Interface */ +#else + .pvReserved18 = (void*) (0UL), /* 18 Reserved */ +#endif /* _SAMV71_HSMCI_INSTANCE_ */ + .pfnTWIHS0_Handler = (void*) TWIHS0_Handler, /* 19 Two Wire Interface 0 HS */ + .pfnTWIHS1_Handler = (void*) TWIHS1_Handler, /* 20 Two Wire Interface 1 HS */ + .pfnSPI0_Handler = (void*) SPI0_Handler, /* 21 Serial Peripheral Interface 0 */ + .pfnSSC_Handler = (void*) SSC_Handler, /* 22 Synchronous Serial Controller */ + .pfnTC0_Handler = (void*) TC0_Handler, /* 23 Timer/Counter 0 */ + .pfnTC1_Handler = (void*) TC1_Handler, /* 24 Timer/Counter 1 */ + .pfnTC2_Handler = (void*) TC2_Handler, /* 25 Timer/Counter 2 */ +#ifdef _SAMV71_TC1_INSTANCE_ + .pfnTC3_Handler = (void*) TC3_Handler, /* 26 Timer/Counter 3 */ +#else + .pvReserved26 = (void*) (0UL), /* 26 Reserved */ +#endif /* _SAMV71_TC1_INSTANCE_ */ +#ifdef _SAMV71_TC1_INSTANCE_ + .pfnTC4_Handler = (void*) TC4_Handler, /* 27 Timer/Counter 4 */ +#else + .pvReserved27 = (void*) (0UL), /* 27 Reserved */ +#endif /* _SAMV71_TC1_INSTANCE_ */ +#ifdef _SAMV71_TC1_INSTANCE_ + .pfnTC5_Handler = (void*) TC5_Handler, /* 28 Timer/Counter 5 */ +#else + .pvReserved28 = (void*) (0UL), /* 28 Reserved */ +#endif /* _SAMV71_TC1_INSTANCE_ */ + .pfnAFEC0_Handler = (void*) AFEC0_Handler, /* 29 Analog Front End 0 */ +#ifdef _SAMV71_DACC_INSTANCE_ + .pfnDACC_Handler = (void*) DACC_Handler, /* 30 Digital To Analog Converter */ +#else + .pvReserved30 = (void*) (0UL), /* 30 Reserved */ +#endif /* _SAMV71_DACC_INSTANCE_ */ + .pfnPWM0_Handler = (void*) PWM0_Handler, /* 31 Pulse Width Modulation 0 */ + .pfnICM_Handler = (void*) ICM_Handler, /* 32 Integrity Check Monitor */ + .pfnACC_Handler = (void*) ACC_Handler, /* 33 Analog Comparator */ + .pfnUSBHS_Handler = (void*) USBHS_Handler, /* 34 USB Host / Device Controller */ + .pfnMCAN0_Handler = (void*) MCAN0_Handler, /* 35 CAN Controller 0 */ + .pfnMCAN0_Line1_Handler = (void*) MCAN0_Line1_Handler, /* 36 CAN Controller 0 - Line 1 */ + .pfnMCAN1_Handler = (void*) MCAN1_Handler, /* 37 CAN Controller 1 */ + .pfnMCAN1_Line1_Handler = (void*) MCAN1_Line1_Handler, /* 38 CAN Controller 1 - Line 1 */ + .pfnGMAC_Handler = (void*) GMAC_Handler, /* 39 Ethernet MAC */ + .pfnAFEC1_Handler = (void*) AFEC1_Handler, /* 40 Analog Front End 1 */ +#ifdef _SAMV71_TWIHS2_INSTANCE_ + .pfnTWIHS2_Handler = (void*) TWIHS2_Handler, /* 41 Two Wire Interface 2 HS */ +#else + .pvReserved41 = (void*) (0UL), /* 41 Reserved */ +#endif /* _SAMV71_TWI2_INSTANCE_ */ + .pfnSPI1_Handler = (void*) SPI1_Handler, /* 42 Serial Peripheral Interface 1 */ + .pfnQSPI_Handler = (void*) QSPI_Handler, /* 43 Quad I/O Serial Peripheral Interface */ + .pfnUART2_Handler = (void*) UART2_Handler, /* 44 UART 2 */ + .pfnUART3_Handler = (void*) UART3_Handler, /* 45 UART 3 */ + .pfnUART4_Handler = (void*) UART4_Handler, /* 46 UART 4 */ +#ifdef _SAMV71_TC2_INSTANCE_ + .pfnTC6_Handler = (void*) TC6_Handler, /* 47 Timer/Counter 6 */ +#else + .pvReserved47 = (void*) (0UL), /* 47 Reserved */ +#endif /* _SAMV71_TC2_INSTANCE_ */ +#ifdef _SAMV71_TC2_INSTANCE_ + .pfnTC7_Handler = (void*) TC7_Handler, /* 48 Timer/Counter 7 */ +#else + .pvReserved48 = (void*) (0UL), /* 48 Reserved */ +#endif /* _SAMV71_TC2_INSTANCE_ */ +#ifdef _SAMV71_TC2_INSTANCE_ + .pfnTC8_Handler = (void*) TC8_Handler, /* 49 Timer/Counter 8 */ +#else + .pvReserved49 = (void*) (0UL), /* 49 Reserved */ +#endif /* _SAMV71_TC2_INSTANCE_ */ + .pfnTC9_Handler = (void*) TC9_Handler, /* 50 Timer/Counter 9 */ + .pfnTC10_Handler = (void*) TC10_Handler, /* 51 Timer/Counter 10 */ + .pfnTC11_Handler = (void*) TC11_Handler, /* 52 Timer/Counter 11 */ + .pfnMLB_Handler = (void*) MLB_Handler, /* 53 MediaLB */ + .pvReserved54 = (void*) (0UL), /* 54 Reserved */ + .pvReserved55 = (void*) (0UL), /* 55 Reserved */ + .pfnAES_Handler = (void*) AES_Handler, /* 56 AES */ + .pfnTRNG_Handler = (void*) TRNG_Handler, /* 57 True Random Generator */ + .pfnXDMAC_Handler = (void*) XDMAC_Handler, /* 58 DMA */ + .pfnISI_Handler = (void*) ISI_Handler, /* 59 Camera Interface */ + .pfnPWM1_Handler = (void*) PWM1_Handler, /* 60 Pulse Width Modulation 1 */ + .pvReserved61 = (void*) (0UL), /* 61 Reserved */ +#ifdef _SAMV71_SDRAMC_INSTANCE_ + .pfnSDRAMC_Handler = (void*) SDRAMC_Handler, /* 62 SDRAM Controller */ +#else + .pvReserved62 = (void*) (0UL), /* 62 Reserved */ +#endif /* _SAMV71_SDRAMC_INSTANCE_ */ + .pfnRSWDT_Handler = (void*) RSWDT_Handler /* 63 Watchdog Timer 1 */ +}; + + +#ifdef ENABLE_TCM +/** \brief TCM memory enable + + The function enables TCM memories + */ +__STATIC_INLINE void TCM_Enable(void) +{ + + __DSB(); + __ISB(); + SCB->ITCMCR = (SCB_ITCMCR_EN_Msk | SCB_ITCMCR_RMW_Msk + | SCB_ITCMCR_RETEN_Msk); + SCB->DTCMCR = ( SCB_DTCMCR_EN_Msk | SCB_DTCMCR_RMW_Msk + | SCB_DTCMCR_RETEN_Msk); + __DSB(); + __ISB(); +} +#endif + +/** \brief TCM memory Disable + + The function enables TCM memories + */ +__STATIC_INLINE void TCM_Disable(void) +{ + + __DSB(); + __ISB(); + SCB->ITCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk; + SCB->DTCMCR &= ~(uint32_t)SCB_ITCMCR_EN_Msk; + __DSB(); + __ISB(); +} + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *) & _sfixed; + SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk); + + #ifdef ENABLE_TCM + // 32 Kb + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(8)); + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_SGPB + | EEFC_FCR_FARG(7)); + + TCM_Enable(); + #else + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(8)); + EFC->EEFC_FCR = (EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FCMD_CGPB + | EEFC_FCR_FARG(7)); + + TCM_Disable(); + #endif + + LowLevelInit(); + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1); +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/system_sam.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/system_sam.c new file mode 100644 index 000000000..0da6efd37 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/resources/system_sam.c @@ -0,0 +1,325 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#include "samv71.h" + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +/* %ATMEL_SYSTEM% */ +/* Clock Settings (500MHz PLL VDDIO 3.3V and VDDCORE 1.2V) */ +/* Clock Settings (300MHz HCLK, 150MHz MCK)=> PRESC = 1, MDIV = 2 */ +#define SYS_BOARD_OSCOUNT (CKGR_MOR_MOSCXTST(0x8U)) +#define SYS_BOARD_PLLAR (CKGR_PLLAR_ONE | CKGR_PLLAR_MULA(0x18U) | \ + CKGR_PLLAR_PLLACOUNT(0x3fU) | CKGR_PLLAR_DIVA(0x1U)) + +#define SYS_BOARD_MCKR (PMC_MCKR_PRES_CLK_1 | PMC_MCKR_CSS_PLLA_CLK \ + | PMC_MCKR_MDIV_PCK_DIV2) + +uint32_t SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; +#define USBCLK_DIV 10 + +/** + * \brief Set up the Microcontroller system. + * Initialize the System and update the SystemFrequency variable. + */ + void SystemInit( void ) +{ + uint32_t read_MOR; + /* Set FWS according to SYS_BOARD_MCKR configuration */ + EFC->EEFC_FMR = EEFC_FMR_FWS(5); + + /* Before switching MAIN OSC on external crystal : enable it and don't + * disable at the same time RC OSC in case of if MAIN OSC is still using RC + * OSC + */ + + read_MOR = PMC->CKGR_MOR; + /* enable external crystal - enable RC OSC */ + read_MOR |= (CKGR_MOR_KEY_PASSWD |CKGR_MOR_XT32KFME); + PMC->CKGR_MOR = read_MOR; + + /* Select XTAL 32k instead of internal slow RC 32k for slow clock */ + if ( (SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST ) + { + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL; + + while( !(SUPC->SUPC_SR & SUPC_SR_OSCSEL) ); + } + + /* Initialize main oscillator */ + if ( !(PMC->CKGR_MOR & CKGR_MOR_MOSCSEL) ) + { + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT + | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCXTS) ) + { + } + } + + /* Switch to 3-20MHz Xtal oscillator */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | SYS_BOARD_OSCOUNT + | CKGR_MOR_MOSCRCEN | CKGR_MOR_MOSCXTEN | CKGR_MOR_MOSCSEL; + + while ( !(PMC->PMC_SR & PMC_SR_MOSCSELS) ) + { + } + + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~(uint32_t)PMC_MCKR_CSS_Msk) + | PMC_MCKR_CSS_MAIN_CLK; + + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Initialize PLLA */ + PMC->CKGR_PLLAR = SYS_BOARD_PLLAR; + while ( !(PMC->PMC_SR & PMC_SR_LOCKA) ) + { + } + + /* Switch to main clock */ + PMC->PMC_MCKR = (SYS_BOARD_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + /* Switch to PLLA */ + PMC->PMC_MCKR = SYS_BOARD_MCKR; + while ( !(PMC->PMC_SR & PMC_SR_MCKRDY) ) + { + } + + SystemCoreClock = CHIP_FREQ_CPU_MAX; +} + +void SystemCoreClockUpdate( void ) +{ + /* Determine clock frequency according to clock register values */ + switch (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) + { + case PMC_MCKR_CSS_SLOW_CLK: /* Slow clock */ + if ( SUPC->SUPC_SR & SUPC_SR_OSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_32K; + } + else + { + SystemCoreClock = CHIP_FREQ_SLCK_RC; + } + break; + + case PMC_MCKR_CSS_MAIN_CLK: /* Main clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + break; + + case PMC_MCKR_CSS_PLLA_CLK: /* PLLA clock */ + if ( PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) + { + SystemCoreClock = CHIP_FREQ_XTAL_12M ; + } + else + { + SystemCoreClock = CHIP_FREQ_MAINCK_RC_4MHZ; + + switch ( PMC->CKGR_MOR & CKGR_MOR_MOSCRCF_Msk ) + { + case CKGR_MOR_MOSCRCF_4_MHz: + break; + + case CKGR_MOR_MOSCRCF_8_MHz: + SystemCoreClock *= 2U; + break; + + case CKGR_MOR_MOSCRCF_12_MHz: + SystemCoreClock *= 3U; + break; + + default: + break; + } + } + + if ( (uint32_t) (PMC->PMC_MCKR & (uint32_t) PMC_MCKR_CSS_Msk) + == PMC_MCKR_CSS_PLLA_CLK ) + { + SystemCoreClock *= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_MULA_Msk) + >> CKGR_PLLAR_MULA_Pos) + 1U); + SystemCoreClock /= ((((PMC->CKGR_PLLAR) & CKGR_PLLAR_DIVA_Msk) + >> CKGR_PLLAR_DIVA_Pos)); + } + break; + + default: + break; + } + + if ( (PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) == PMC_MCKR_PRES_CLK_3 ) + { + SystemCoreClock /= 3U; + } + else + { + SystemCoreClock >>= ((PMC->PMC_MCKR & PMC_MCKR_PRES_Msk) + >> PMC_MCKR_PRES_Pos); + } +} +/** + * Initialize flash. + */ +void system_init_flash( uint32_t ul_clk ) +{ + /* Set FWS for embedded Flash access according to operating frequency */ + if ( ul_clk < CHIP_FREQ_FWS_0 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(0)|EEFC_FMR_CLOE; + } + else + { + if (ul_clk < CHIP_FREQ_FWS_1) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(1)|EEFC_FMR_CLOE; + } + else + { + if (ul_clk < CHIP_FREQ_FWS_2) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(2)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_3 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(3)|EEFC_FMR_CLOE; + } + else + { + if ( ul_clk < CHIP_FREQ_FWS_4 ) + { + EFC->EEFC_FMR = EEFC_FMR_FWS(4)|EEFC_FMR_CLOE; + } + else + { + EFC->EEFC_FMR = EEFC_FMR_FWS(5)|EEFC_FMR_CLOE; + } + } + } + } + } +} + +/** + * \brief Enable full speed USB clock. + * + * \note The SAM3X PMC hardware interprets div as div+1. For readability the hardware div+1 + * is hidden in this implementation. Use div as div effective value. + * + * \param pll_id Source of the USB clock. + * \param div Actual clock divisor. Must be superior to 0. + */ +void sysclk_enable_usb(void) +{ + /* Disable FS USB clock*/ + PMC->PMC_SCDR = PMC_SCDR_USBCLK; + + /* Enable PLL 480 MHz */ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF); + /* Wait that PLL is considered locked by the PMC */ + while( !(PMC->PMC_SR & PMC_SR_LOCKU) ); + + /* USB clock register: USB Clock Input is UTMI PLL */ + PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1) ); + + PMC->PMC_SCER = PMC_SCER_USBCLK; +} + + +/** + * \brief Enable full speed USB clock. + * + * \note The SAM3X PMC hardware interprets div as div+1. For readability the hardware div+1 + * is hidden in this implementation. Use div as div effective value. + * + * \param pll_id Source of the USB clock. + * \param div Actual clock divisor. Must be superior to 0. + */ +void sysclk_disable_usb(void) +{ + /* Disable FS USB clock*/ + PMC->PMC_SCDR = PMC_SCDR_USBCLK; + + /* Enable PLL 480 MHz */ + PMC->CKGR_UCKR = CKGR_UCKR_UPLLEN | CKGR_UCKR_UPLLCOUNT(0xF); + /* Wait that PLL is considered locked by the PMC */ + while( !(PMC->PMC_SR & PMC_SR_LOCKU) ); + + /* USB clock register: USB Clock Input is UTMI PLL */ + PMC->PMC_USB = (PMC_USB_USBS | PMC_USB_USBDIV(USBCLK_DIV - 1) ); + + +} + + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/board_lowlevel.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/board_lowlevel.c new file mode 100644 index 000000000..9f498a313 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/board_lowlevel.c @@ -0,0 +1,341 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Provides the low-level initialization function that called on chip startup. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + + +#if defined(ENABLE_TCM) && defined(__GNUC__) + extern char _itcm_lma, _sitcm, _eitcm; +#endif + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/** + * \brief Set up a memory region. + */ +void _SetupMemoryRegion( void ) +{ + + uint32_t dwRegionBaseAddr; + uint32_t dwRegionAttr; + + memory_barrier(); + +/*************************************************** + ITCM memory region --- Normal + START_Addr:- 0x00000000UL + END_Addr:- 0x00400000UL +****************************************************/ + dwRegionBaseAddr = + ITCM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_ITCM_REGION; // 1 + + dwRegionAttr = + MPU_AP_PRIVILEGED_READ_WRITE | + MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + +/**************************************************** + Internal flash memory region --- Normal read-only + (update to Strongly ordered in write accesses) + START_Addr:- 0x00400000UL + END_Addr:- 0x00600000UL +******************************************************/ + + dwRegionBaseAddr = + IFLASH_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_IFLASH_REGION; //2 + + dwRegionAttr = + MPU_AP_READONLY | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + MPU_CalMPURegionSize(IFLASH_END_ADDRESS - IFLASH_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + +/**************************************************** + DTCM memory region --- Normal + START_Addr:- 0x20000000L + END_Addr:- 0x20400000UL +******************************************************/ + + /* DTCM memory region */ + dwRegionBaseAddr = + DTCM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_DTCM_REGION; //3 + + dwRegionAttr = + MPU_AP_PRIVILEGED_READ_WRITE | + MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + +/**************************************************** + SRAM Cacheable memory region --- Normal + START_Addr:- 0x20400000UL + END_Addr:- 0x2043FFFFUL +******************************************************/ + /* SRAM memory region */ + dwRegionBaseAddr = + SRAM_FIRST_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SRAM_REGION_1; //4 + + dwRegionAttr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + MPU_CalMPURegionSize(SRAM_FIRST_END_ADDRESS - SRAM_FIRST_START_ADDRESS) + | MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + + +/**************************************************** + Internal SRAM second partition memory region --- Normal + START_Addr:- 0x20440000UL + END_Addr:- 0x2045FFFFUL +******************************************************/ + /* SRAM memory region */ + dwRegionBaseAddr = + SRAM_SECOND_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SRAM_REGION_2; //5 + + dwRegionAttr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_NWA_TYPE( NON_SHAREABLE ) | + MPU_CalMPURegionSize(SRAM_SECOND_END_ADDRESS - SRAM_SECOND_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + +/**************************************************** + Peripheral memory region --- DEVICE Shareable + START_Addr:- 0x40000000UL + END_Addr:- 0x5FFFFFFFUL +******************************************************/ + dwRegionBaseAddr = + PERIPHERALS_START_ADDRESS | + MPU_REGION_VALID | + MPU_PERIPHERALS_REGION; //6 + + dwRegionAttr = MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + MPU_CalMPURegionSize(PERIPHERALS_END_ADDRESS - PERIPHERALS_START_ADDRESS) + |MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + + +/**************************************************** + External EBI memory memory region --- Strongly Ordered + START_Addr:- 0x60000000UL + END_Addr:- 0x6FFFFFFFUL +******************************************************/ + dwRegionBaseAddr = + EXT_EBI_START_ADDRESS | + MPU_REGION_VALID | + MPU_EXT_EBI_REGION; + + dwRegionAttr = + MPU_AP_FULL_ACCESS | + /* External memory Must be defined with 'Device' or 'Strongly Ordered' + attribute for write accesses (AXI) */ + STRONGLY_ORDERED_SHAREABLE_TYPE | + MPU_CalMPURegionSize(EXT_EBI_END_ADDRESS - EXT_EBI_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + +/**************************************************** + SDRAM Cacheable memory region --- Normal + START_Addr:- 0x70000000UL + END_Addr:- 0x7FFFFFFFUL +******************************************************/ + dwRegionBaseAddr = + SDRAM_START_ADDRESS | + MPU_REGION_VALID | + MPU_DEFAULT_SDRAM_REGION; //7 + + dwRegionAttr = + MPU_AP_FULL_ACCESS | + INNER_NORMAL_WB_RWA_TYPE( SHAREABLE ) | + MPU_CalMPURegionSize(SDRAM_END_ADDRESS - SDRAM_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + +/**************************************************** + QSPI memory region --- Strongly ordered + START_Addr:- 0x80000000UL + END_Addr:- 0x9FFFFFFFUL +******************************************************/ + dwRegionBaseAddr = + QSPI_START_ADDRESS | + MPU_REGION_VALID | + MPU_QSPIMEM_REGION; //8 + + dwRegionAttr = + MPU_AP_FULL_ACCESS | + STRONGLY_ORDERED_SHAREABLE_TYPE | + MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + + +/**************************************************** + USB RAM Memory region --- Device + START_Addr:- 0xA0100000UL + END_Addr:- 0xA01FFFFFUL +******************************************************/ + dwRegionBaseAddr = + USBHSRAM_START_ADDRESS | + MPU_REGION_VALID | + MPU_USBHSRAM_REGION; //9 + + dwRegionAttr = + MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + MPU_CalMPURegionSize(USBHSRAM_END_ADDRESS - USBHSRAM_START_ADDRESS) | + MPU_REGION_ENABLE; + + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + + + /* Enable the memory management fault , Bus Fault, Usage Fault exception */ + SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_USGFAULTENA_Msk); + + /* Enable the MPU region */ + MPU_Enable( MPU_ENABLE | MPU_PRIVDEFENA); + + memory_sync(); +} + +#ifdef ENABLE_TCM + +#if defined ( __ICCARM__ ) /* IAR Ewarm */ +#pragma section = "CSTACK" +#pragma section = "CSTACK_DTCM" + #define SRAM_STACK_BASE (__section_begin("CSTACK")) + #define DTCM_STACK_BASE (__section_begin("CSTACK_DTCM")) + #define SRAM_STACK_LIMIT (__section_end("CSTACK")) + #define DTCM_STACK_LIMIT (__section_end("CSTACK_DTCM")) +#elif defined (__CC_ARM) /* MDK */ + extern uint32_t Image$$ARM_LIB_STACK$$Base; + extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit; + extern uint32_t Image$$DTCM_STACK$$Base; + extern uint32_t Image$$DTCM_STACK$$ZI$$Limit; + #define SRAM_STACK_BASE (&Image$$ARM_LIB_STACK$$Base) + #define DTCM_STACK_BASE (&Image$$DTCM_STACK$$Base) + #define SRAM_STACK_LIMIT (&Image$$ARM_LIB_STACK$$ZI$$Limit) + #define DTCM_STACK_LIMIT (&Image$$DTCM_STACK$$ZI$$Limit) +#elif defined ( __GNUC__ ) /* GCC */ + extern char _sdtcm_stack, _edtcm_stack, _sstack, _estack; + #define SRAM_STACK_BASE ((void *)(&_sstack)) + #define DTCM_STACK_BASE ((void *)(&_sdtcm_stack)) + #define SRAM_STACK_LIMIT ((void *)(&_estack)) + #define DTCM_STACK_LIMIT ((void *)(&_edtcm_stack)) +#endif + +/** \brief Change stack's location to DTCM + + The function changes the stack's location from SRAM to DTCM + */ +void TCM_StackInit(void); +void TCM_StackInit(void) +{ + uint32_t offset = (uint32_t)SRAM_STACK_LIMIT - (uint32_t)DTCM_STACK_LIMIT; + volatile char *dst = (volatile char *)DTCM_STACK_LIMIT; + volatile char *src = (volatile char *)SRAM_STACK_LIMIT; + /* copy code_TCM from flash to ITCM */ + while(src > (volatile char *)SRAM_STACK_BASE){ + *--dst = *--src; + } + __set_MSP(__get_MSP() - offset); +} + +#endif + + +/** + * \brief Performs the low-level initialization of the chip. + */ +extern WEAK void LowLevelInit( void ) +{ + + SystemInit(); +#ifndef MPU_EXAMPLE_FEATURE + _SetupMemoryRegion(); +#endif + + +#if defined(ENABLE_TCM) && defined(__GNUC__) + volatile char *dst = &_sitcm; + volatile char *src = &_itcm_lma; + /* copy code_TCM from flash to ITCM */ + while(dst < &_eitcm){ + *dst++ = *src++; + } +#endif +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/board_memories.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/board_memories.c new file mode 100644 index 000000000..1e8b58adf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/board_memories.c @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of memories configuration on board. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#define SDRAM_BA0 (1 << 20) +#define SDRAM_BA1 (1 << 21) + + +uint32_t BOARD_SdramValidation(uint32_t baseAddr, uint32_t size) +{ + uint32_t i; + uint32_t ret = 1; + uint32_t *ptr32 = (uint32_t *) baseAddr; + uint16_t *ptr16 = (uint16_t *) baseAddr; + uint8_t *ptr8 = (uint8_t *) baseAddr; + /* Test for 55AA55AA/AA55AA55 pattern */ + printf(" Test for 55AA55AA/AA55AA55 pattern ... \n\r"); + for (i = 0; i < size ; i ++) { + if (i & 1) { + ptr32[i] = 0x55AA55AA ; + } else { + ptr32[i] = 0xAA55AA55 ; + } + memory_barrier() + } + for (i = 0; i < size ; i++) { + if (i & 1) { + if (ptr32[i] != 0x55AA55AA ) { + printf("-E- Expected:%x, read %x @ %x \n\r" , + 0xAA55AA55, (unsigned)ptr32[i], (unsigned)(baseAddr + i)); + ret = 0; + + } + } else { + if (ptr32[i] != 0xAA55AA55 ) { + printf("-E- Expected:%x, read %x @ %x \n\r" , + 0xAA55AA55 , (unsigned)ptr32[i], (unsigned)(baseAddr + i)); + ret = 0; + } + } + } + if (!ret) return ret; + printf(" Test for BYTE accessing... \n\r"); + /* Test for BYTE accessing */ + for (i = 0; i < size ; i ++) { + ptr8[i] = (uint8_t)( i & 0xFF) ; + } + + for (i = 0; i < size ; i++) { + if (ptr8[i] != (uint8_t)(i & 0xFF)) { + printf("-E- Expected:%x, read %x @ %x \n\r" , + (unsigned)(i & 0xFF), ptr8[i],(unsigned)(baseAddr + i)); + ret = 0; + } + } + if (!ret) return ret; + + printf(" Test for WORD accessing... \n\r"); + /* Test for WORD accessing */ + for (i = 0; i < size / 2 ; i ++) { + ptr16[i] = (uint16_t)( i & 0xFFFF) ; + } + + for (i = 0; i < size / 2 ; i++) { + if (ptr16[i] != (uint16_t)(i & 0xFFFF)) { + printf("-E- Expected:%x, read %x @ %x \n\r" , + (unsigned)(i & 0xFFFF), ptr16[i],(unsigned)(baseAddr + i)); + ret = 0; + } + } + if (!ret) return ret; + printf(" Test for DWORD accessing... \n\r"); + /* Test for DWORD accessing */ + for (i = 0; i < size / 4 ; i ++) { + ptr32[i] = (uint32_t)( i & 0xFFFFFFFF) ; + memory_barrier() + } + + for (i = 0; i < size / 4 ; i++) { + if (ptr32[i] != (uint32_t)(i & 0xFFFFFFFF)) { + printf("-E- Expected:%x, read %x @ %x \n\r" , + (unsigned)(i & 0xFFFFFFFF), (unsigned)ptr32[i], (unsigned)(baseAddr + i)); + ret = 0; + } + } + return ret; +} + + +/** + * \brief Configures the EBI for SDRAM (IS42S16100E-7B) access. + */ + + +void BOARD_ConfigureSdram( void ) +{ + const Pin pinsSdram[] = {BOARD_SDRAM_PINS}; + volatile uint32_t i; + volatile uint8_t *pSdram = (uint8_t *) SDRAM_CS_ADDR; + + /* Configure PIO */ + PIO_Configure(pinsSdram, PIO_LISTSIZE(pinsSdram)); + PMC_EnablePeripheral(ID_SDRAMC); + MATRIX->CCFG_SMCNFCS = CCFG_SMCNFCS_SDRAMEN; + + /* 1. SDRAM features must be set in the configuration register: + asynchronous timings (TRC, TRAS, etc.), number of columns, rows, + CAS latency, and the data bus width. */ + SDRAMC->SDRAMC_CR = + SDRAMC_CR_NC_COL8 // 8 column bits + | SDRAMC_CR_NR_ROW11 // 12 row bits (4K) + | SDRAMC_CR_CAS_LATENCY3 // CAS Latency 3 + | SDRAMC_CR_NB_BANK2 // 2 banks + | SDRAMC_CR_DBW // 16 bit + | SDRAMC_CR_TWR(4) + | SDRAMC_CR_TRC_TRFC(11) // 63ns min + | SDRAMC_CR_TRP(5) // Command period (PRE to ACT) 21 ns min + | SDRAMC_CR_TRCD(5) // Active Command to read/Write Command delay time 21ns min + | SDRAMC_CR_TRAS(8) // Command period (ACT to PRE) 42ns min + | SDRAMC_CR_TXSR(13U); // Exit self-refresh to active time 70ns Min + + /* 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive + strength (DS) and partial array self refresh (PASR) must be set in the + Low Power Register. */ + + /* 3. The SDRAM memory type must be set in the Memory Device Register.*/ + SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM; + + /* 4. A minimum pause of 200 ¦Ìs is provided to precede any signal toggle.*/ + for (i = 0; i < 100000; i++); + + /* 5. (1)A NOP command is issued to the SDRAM devices. The application must + set Mode to 1 in the Mode Register and perform a write access to + any SDRAM address.*/ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP; + *pSdram = 0; + for (i = 0; i < 100000; i++); + /* 6. An All Banks Precharge command is issued to the SDRAM devices. + The application must set Mode to 2 in the Mode Register and perform a write + access to any SDRAM address. */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE; + *pSdram = 0; + for (i = 0; i < 100000; i++); + /* 7. Eight auto-refresh (CBR) cycles are provided. The application must + set the Mode to 4 in the Mode Register and perform a write access to any + SDRAM location eight times.*/ + for (i = 0 ; i< 8; i++) { + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *pSdram = 0; + } + for (i = 0; i < 100000; i++); + /*8. A Mode Register set (MRS) cycle is issued to program the parameters of + the SDRAM devices, in particular CAS latency and burst length. The + application must set Mode to 3 in the Mode Register and perform a write + access to the SDRAM. The write address must be chosen so that BA[1:0] + are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, + 4 banks) bank address, the SDRAM write access should be done at the address + 0x70000000.*/ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG; + *pSdram = 0; + + for (i = 0; i < 100000; i++); + /*9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) + cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The + application must set Mode to 5 in the Mode Register and perform a write + access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] + are set to 1. + For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank + address the SDRAM write access should be done at the address 0x70800000 or + 0x70400000. */ + //SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG; + // *((uint8_t *)(pSdram + SDRAM_BA0)) = 0; + + /* 10. The application must go into Normal Mode, setting Mode to 0 in the + Mode Register and performing a write access at any location in the SDRAM. */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL; + *pSdram = 0; + for (i = 0; i < 100000; i++); + /* 11. Write the refresh rate into the count field in the SDRAMC Refresh + Timer register. (Refresh rate = delay between refresh cycles). + The SDRAM device requires a refresh every 15.625 ¦Ìs or 7.81 ¦Ìs. + With a 100 MHz frequency, the Refresh Timer Counter Register must be set + with the value 1562(15.625 ¦Ìs x 100 MHz) or 781(7.81 ¦Ìs x 100 MHz). */ + // For IS42S16100E, 2048 refresh cycle every 32ms, every 15.625 ¦Ìs + /* ((32 x 10(^-3))/2048) x150 x (10^6) */ + SDRAMC->SDRAMC_TR = 2343; ; + SDRAMC->SDRAMC_CFR1 |= SDRAMC_CFR1_UNAL; + /* After initialization, the SDRAM devices are fully functional. */ +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/cs2100.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/cs2100.c new file mode 100644 index 000000000..711791ed0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/cs2100.c @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation CS2100 driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct { + uint16_t value; + uint8_t address; +}CS2100_PARA; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Read data from CS2100 Register. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param regAddr Register address to read. + * \return value in the given register. + */ +uint16_t CS2100_Read(Twid *pTwid, + uint32_t device, + uint32_t regAddr) +{ + uint16_t bitsDataRegister; + uint8_t Tdata[2]={0,0}; + + TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0); + bitsDataRegister = (Tdata[0] << 8) | Tdata[1]; + return bitsDataRegister; +} + +/** + * \brief Write data to CS2100 Register. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param regAddr Register address to write. + * \param data Data to write + */ +void CS2100_Write(Twid *pTwid, + uint32_t device, + uint32_t regAddr, + uint16_t data) +{ + uint8_t tmpData[2]; + tmpData[0] = (data & 0xff00) >> 8; + tmpData[1] = data & 0xff; + TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0); +} + +/** + * \brief Initialize CS2100 Clock Multiplier. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param PCK Device programmable clock + */ +uint8_t CS2100_Init(Twid *pTwid, uint32_t device, uint32_t PCK) +{ + uint16_t data = 0; + // Reset (write Reg@0x0 to reset) + CS2100_Write(pTwid, device, 0, 0xFFFF); + + for(data = 0; data < 1000; data++); + //wait ready + while(data!=0x8904) + data = CS2100_Read(pTwid, device, 0); + return 0; +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/dbg_console.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/dbg_console.c new file mode 100644 index 000000000..eea980e47 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/dbg_console.c @@ -0,0 +1,548 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implements UART console. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** Console baud rate always using 115200. */ + + +#define CONSOLE_BAUDRATE 115200 +#define CONSOLE_EDBG + +#if defined CONSOLE_EDBG +#define CONSOLE_ON_USART +#else +#define CONSOLE_ON_UART +#endif + +#if defined CONSOLE_ON_UART +#ifdef SSC_AUDIO +/** Usart Hw interface used by the console (UART4). */ +#warning Please use UART4 pins for debug consol as UART0 pins are used in SSC \ + audio for SAM V71 Xplained Ultra board +#define CONSOLE_UART UART4 + +/** Pins description corresponding to Rxd,Txd, (UART pins) */ +#define CONSOLE_PINS {PINS_UART4} + +#define CONSOLE_ID ID_UART4 +#else +/** Usart Hw interface used by the console (UART0). */ +#define CONSOLE_UART UART0 + +/** Pins description corresponding to Rxd,Txd, (UART pins) */ +#define CONSOLE_PINS {PINS_UART0} + +#define CONSOLE_ID ID_UART0 + +#endif +#endif + +#if defined CONSOLE_ON_USART + +/** USART1 pin RX */ +#define PIN_USART1_RXD_DBG \ + {PIO_PA21A_RXD1, PIOA, ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT} +/** USART1 pin TX */ +#define PIN_USART1_TXD_DBG \ + {PIO_PB4D_TXD1, PIOB, ID_PIOB, PIO_PERIPH_D, PIO_DEFAULT} +#define PINS_USART1 PIN_USART1_TXD_DBG, PIN_USART1_RXD_DBG + +/** Usart Hw interface used by the console (Usart0). */ +#define CONSOLE_Usart USART1 + +/** Pins description corresponding to Rxd,Txd, (Usart pins) */ +#define CONSOLE_PINS {PINS_USART1} + +#define CONSOLE_ID ID_USART1 +#endif + + +/*---------------------------------------------------------------------------- + * Variables + *----------------------------------------------------------------------------*/ + +/** Is Console Initialized. */ +static uint8_t _ucIsConsoleInitialized = 0; + +/** + * \brief Configures an USART peripheral with the specified parameters. + * + * \param baudrate Baudrate at which the USART should operate (in Hz). + * \param masterClock Frequency of the system master clock (in Hz). + */ +extern void DBG_Configure( uint32_t baudrate, uint32_t masterClock) +{ + + const Pin pPins[] = CONSOLE_PINS; +#if defined CONSOLE_ON_UART + Uart *pUart = CONSOLE_UART; + /* Configure PIO */ + PIO_Configure( pPins, PIO_LISTSIZE( pPins ) ); + + // Reset & disable receiver and transmitter, disable interrupts + pUart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX | UART_CR_RSTSTA; + pUart->UART_IDR = 0xFFFFFFFF; + PMC_EnablePeripheral(CONSOLE_ID); + pUart->UART_BRGR = (masterClock / baudrate) / 16; + // Configure mode register + pUart->UART_MR + = (UART_MR_CHMODE_NORMAL | UART_MR_PAR_NO + | UART_MR_BRSRCCK_PERIPH_CLK); + // Enable receiver and transmitter + pUart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; +#endif + +#if defined CONSOLE_ON_USART + Usart *pUsart = CONSOLE_Usart; + // Disable the MATRIX registers write protection + MATRIX->MATRIX_WPMR = MATRIX_WPMR_WPKEY_PASSWD; + MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4; + + PIO_Configure( pPins, PIO_LISTSIZE( pPins ) ); + + // Reset & disable receiver and transmitter, disable interrupts + pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX | US_CR_RSTSTA; + pUsart->US_IDR = 0xFFFFFFFF; + PMC_EnablePeripheral(CONSOLE_ID); + pUsart->US_BRGR = (masterClock / baudrate) / 16; + + // Configure mode register + pUsart->US_MR + = (US_MR_USART_MODE_NORMAL | US_MR_PAR_NO| US_MR_USCLKS_MCK + | US_MR_CHRL_8_BIT); + + // Enable receiver and transmitter + pUsart->US_CR = US_CR_RXEN | US_CR_TXEN; +#endif + _ucIsConsoleInitialized = 1; + + /* Disable buffering for printf(). */ +#if ( defined (__GNUC__) && !defined (__SAMBA__) ) + setvbuf(stdout, (char *)NULL, _IONBF, 0); +#endif +} + +/** + * \brief Outputs a character on the UART line. + * + * \note This function is synchronous (i.e. uses polling). + * \param c Character to send. + */ +extern void DBG_PutChar( uint8_t c ) +{ +#if defined CONSOLE_ON_UART + Uart *pUart=CONSOLE_UART; + if ( !_ucIsConsoleInitialized ) + { + DBG_Configure(CONSOLE_BAUDRATE, BOARD_MCK); + } + // Wait for the transmitter to be ready + while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0); + + // Send character + pUart->UART_THR = c; + // Wait for the transfer to complete + while ((pUart->UART_SR & UART_SR_TXEMPTY) == 0); +#endif + +#if defined CONSOLE_ON_USART + Usart *pUsart=CONSOLE_Usart; + if ( !_ucIsConsoleInitialized ) + { + DBG_Configure(CONSOLE_BAUDRATE, BOARD_MCK); + } + // Wait for the transmitter to be ready + while ((pUsart->US_CSR & US_CSR_TXEMPTY) == 0); + + // Send character + pUsart->US_THR = c; + + // Wait for the transfer to complete + while ((pUsart->US_CSR & US_CSR_TXEMPTY) == 0); +#endif +} + +/** + * \brief Input a character from the UART line. + * + * \note This function is synchronous + * \return character received. + */ +extern uint32_t DBG_GetChar( void ) +{ +#if defined CONSOLE_ON_UART + Uart *pUart= CONSOLE_UART; + + if ( !_ucIsConsoleInitialized ) + { + DBG_Configure(CONSOLE_BAUDRATE, BOARD_MCK); + } + + while ((pUart->UART_SR & UART_SR_RXRDY) == 0); + return pUart->UART_RHR; +#endif + +#if defined CONSOLE_ON_USART + Usart *pUsart= CONSOLE_Usart; + + if ( !_ucIsConsoleInitialized ) + { + DBG_Configure(CONSOLE_BAUDRATE, BOARD_MCK); + } + + while ((pUsart->US_CSR & US_CSR_RXRDY) == 0); + return pUsart->US_RHR; +#endif +} + +/** + * \brief Check if there is Input from UART line. + * + * \return true if there is Input. + */ +extern uint32_t DBG_IsRxReady( void ) +{ +#if defined CONSOLE_ON_UART + Uart *pUart=CONSOLE_UART; + + if ( !_ucIsConsoleInitialized ) + { + DBG_Configure( CONSOLE_BAUDRATE, BOARD_MCK ); + } + return (pUart->UART_SR & UART_SR_RXRDY); +#endif + +#if defined CONSOLE_ON_USART + Usart *pUsart=CONSOLE_Usart; + + if ( !_ucIsConsoleInitialized ) + { + DBG_Configure( CONSOLE_BAUDRATE, BOARD_MCK ); + } + + return (pUsart->US_CSR & US_CSR_RXRDY); +#endif +} + +/** + * Displays the content of the given frame on the UART0. + * + * \param pucFrame Pointer to the frame to dump. + * \param dwSize Buffer size in bytes. + */ +extern void DBG_DumpFrame( uint8_t* pucFrame, uint32_t dwSize ) +{ + uint32_t dw; + + for ( dw=0; dw < dwSize; dw++ ) + { + printf( "%02X ", pucFrame[dw] ); + } + + printf( "\n\r" ); +} + +/** + * Displays the content of the given buffer on the UART0. + * + * \param pucBuffer Pointer to the buffer to dump. + * \param dwSize Buffer size in bytes. + * \param dwAddress Start address to display + */ +extern void DBG_DumpMemory( uint8_t* pucBuffer, uint32_t dwSize, + uint32_t dwAddress ) +{ + uint32_t i; + uint32_t j; + uint32_t dwLastLineStart; + uint8_t* pucTmp; + + for (i=0; i < (dwSize / 16); i++ ) + { + printf( "0x%08X: ", (unsigned int)(dwAddress + (i*16))); + pucTmp = (uint8_t*)&pucBuffer[i*16]; + + for (j=0; j < 4; j++) + { + printf( "%02X%02X%02X%02X ", + pucTmp[0], pucTmp[1], pucTmp[2], pucTmp[3]); + pucTmp += 4; + } + + pucTmp=(uint8_t*)&pucBuffer[i*16]; + + for (j=0; j < 16; j++) + { + DBG_PutChar( *pucTmp++); + } + + printf( "\n\r" ); + } + + if ( (dwSize%16) != 0 ) + { + dwLastLineStart=dwSize - (dwSize%16); + + printf( "0x%08X: ", (unsigned int)(dwAddress + dwLastLineStart)); + for (j=dwLastLineStart; j < dwLastLineStart+16; j++) + { + if ( (j!=dwLastLineStart) && (j%4 == 0) ) + { + printf( " " ); + } + + if ( j < dwSize ) + { + printf( "%02X", pucBuffer[j] ); + } + else + { + printf(" "); + } + } + + printf( " " ); + for (j=dwLastLineStart; j < dwSize; j++) + { + DBG_PutChar( pucBuffer[j] ); + } + + printf( "\n\r" ); + } +} + +/** + * Reads an integer + * + * \param pdwValue Pointer to a integer variable to contain the input value. + * + * \return success(1) or failure(0) + */ +extern uint32_t DBG_GetInteger( int32_t* pdwValue ) +{ + uint8_t ucKey; + uint8_t ucNum = 0; + int32_t dwValue = 0; + int32_t sign = 1; + + while (1) + { + ucKey=DBG_GetChar(); + DBG_PutChar( ucKey ); + + if (((ucKey == '-') || (ucKey == '+')) && (ucNum == 0)) + { + if (ucKey == '-') + { + sign = -1; + } + else + { + sign = 1; + } + ucNum++; + } + else + { + if (ucKey >= '0' && ucKey <= '9') + { + dwValue = (dwValue * 10) + (ucKey - '0'); + ucNum++; + } + else + { + if (ucKey == 0x0D || ucKey == ' ') + { + if ( ucNum == 0 ) + { + printf("\n\rWrite a number and press ENTER or SPACE!\n\r"); + return 0; + } + else + { + printf( "\n\r" ); + *pdwValue = dwValue * sign; + + return 1; + } + } + else + { + printf("\n\r'%c' not a number or sign(+/-)!\n\r", ucKey); + return 0; + } + } + } + } +} + +/** + * Reads an integer and check the value + * + * \param pdwValue Pointer to a integer variable to contain the input value. + * \param dwMin Minimum value + * \param dwMax Maximum value + * + * \return success(1) or failure(0) + */ +extern uint32_t DBG_GetIntegerMinMax(int32_t* pdwValue, int32_t dwMin, + int32_t dwMax) +{ + int32_t dwValue = 0; + + if ( DBG_GetInteger( &dwValue ) == 0 ) + { + return 0; + } + + if ( dwValue < dwMin || dwValue > dwMax ) + { + printf( "\n\rThe number have to be between %d and %d\n\r", + (int)dwMin, (int)dwMax ); + + return 0; + } + + printf( "\n\r" ); + + *pdwValue = dwValue; + + return 1; +} + +/** + * Reads an hexadecimal number + * + * \param pdwValue Pointer to the uint32_t variable to contain the input value. + */ +extern uint32_t DBG_GetHexa32( uint32_t* pdwValue ) +{ + uint8_t ucKey; + uint32_t dw = 0; + uint32_t dwValue = 0; + + for ( dw=0; dw < 8; dw++ ) + { + ucKey = DBG_GetChar(); + DBG_PutChar( ucKey ); + + if ( ucKey >= '0' && ucKey <= '9' ) + { + dwValue = (dwValue * 16) + (ucKey - '0'); + } + else + { + if ( ucKey >= 'A' && ucKey <= 'F' ) + { + dwValue = (dwValue * 16) + (ucKey - 'A' + 10); + } + else + { + if ( ucKey >= 'a' && ucKey <= 'f' ) + { + dwValue = (dwValue * 16) + (ucKey - 'a' + 10); + } + else + { + printf( "\n\rIt is not a hexadecimal character!\n\r" ); + + return 0; + } + } + } + } + + printf("\n\r" ); + *pdwValue = dwValue; + + return 1; +} + +#if defined __ICCARM__ /* IAR Ewarm 5.41+ */ +/** + * \brief Outputs a character on the UART. + * + * \param c Character to output. + * + * \return The character that was output. + */ +extern WEAK signed int putchar( signed int c ) +{ + DBG_PutChar( c ); + + return c; +} + +#endif // defined __ICCARM__ +extern WEAK int puts(const char *ptr ) +{ + + for (; *ptr != 0; ptr++ ) + { + DBG_PutChar( *ptr ); + } + + return 0; + +} + +extern WEAK char * gets(char *ptr) +{ + uint8_t ch = 0; + while (ch != '\r' ) + { + ch = DBG_GetChar(); + DBG_PutChar( ch ); + *(ptr++) = ch; + } + *ptr = '\0'; + return 0; + +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/gmacb_phy.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/gmacb_phy.c new file mode 100644 index 000000000..c30f046cc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/gmacb_phy.c @@ -0,0 +1,500 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "board.h" + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +/** Default max retry count */ +#define GMACB_RETRY_MAX 300000 + +/** Default max retry count */ +#define GACB_RETRY_MAX 1000000 + +/*--------------------------------------------------------------------------- + * Local functions + *---------------------------------------------------------------------------*/ + + +/** + * Wait PHY operation complete. + * Return 1 if the operation completed successfully. + * May be need to re-implemented to reduce CPU load. + * \param retry: the retry times, 0 to wait forever until complete. + */ +static uint8_t GMACB_WaitPhy( Gmac *pHw, uint32_t retry ) +{ + volatile uint32_t retry_count = 0; + + while (!GMAC_IsIdle(pHw)) { + if(retry == 0) continue; + retry_count ++; + if (retry_count >= retry) { + return 0; + } + } + return 1; +} + +/** + * Read PHY register. + * Return 1 if successfully, 0 if timeout. + * \param pHw HW controller address + * \param PhyAddress PHY Address + * \param Address Register Address + * \param pValue Pointer to a 32 bit location to store read data + * \param retry The retry times, 0 to wait forever until complete. + */ +static uint8_t GMACB_ReadPhy(Gmac *pHw, + uint8_t PhyAddress, + uint8_t Address, + uint32_t *pValue, + uint32_t retry) +{ + GMAC_PHYMaintain(pHw, PhyAddress, Address, 1, 0); + if ( GMACB_WaitPhy(pHw, retry) == 0 ) { + TRACE_ERROR("TimeOut GMACB_ReadPhy\n\r"); + return 0; + } + *pValue = GMAC_PHYData(pHw); + return 1; +} + +/** + * Write PHY register + * Return 1 if successfully, 0 if timeout. + * \param pHw HW controller address + * \param PhyAddress PHY Address + * \param Address Register Address + * \param Value Data to write ( Actually 16 bit data ) + * \param retry The retry times, 0 to wait forever until complete. + */ +static uint8_t GMACB_WritePhy(Gmac *pHw, + uint8_t PhyAddress, + uint8_t Address, + uint32_t Value, + uint32_t retry) +{ + GMAC_PHYMaintain(pHw, PhyAddress, Address, 0, Value); + if ( GMACB_WaitPhy(pHw, retry) == 0 ) { + TRACE_ERROR("TimeOut GMACB_WritePhy\n\r"); + return 0; + } + return 1; +} + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * \brief Find a valid PHY Address ( from 0 to 31 ). + * \param pMacb Pointer to the MACB instance + * \return 0xFF when no valid PHY Address found. + */ +static uint8_t GMACB_FindValidPhy(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + + uint32_t retryMax; + uint32_t value=0; + uint8_t rc; + uint8_t phyAddress; + uint8_t cnt; + + TRACE_DEBUG("GMACB_FindValidPhy\n\r"); + + GMAC_EnableMdio(pHw); + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + /* Check current phyAddress */ + rc = phyAddress; + if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax) == 0 ) { + TRACE_ERROR("GMACB PROBLEM\n\r"); + } + TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress); + + /* Find another one */ + if (value != GMII_OUI_MSB) { + rc = 0xFF; + for(cnt = 0; cnt < 32; cnt ++) { + phyAddress = (phyAddress + 1) & 0x1F; + if( GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax) + == 0 ){ + TRACE_ERROR("MACB PROBLEM\n\r"); + } + TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress); + if (value == GMII_OUI_MSB) { + + rc = phyAddress; + break; + } + } + } + if (rc != 0xFF) { + TRACE_INFO("** Valid PHY Found: %d\n\r", rc); + GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax); + TRACE_DEBUG("_PHYID1R : 0x%X, addr: %d\n\r", value, phyAddress); + GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID2R, &value, retryMax); + TRACE_DEBUG("_EMSR : 0x%X, addr: %d\n\r", value, phyAddress); + } + GMAC_DisableMdio(pHw); + return rc; +} + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + +/** + * \brief Dump all the useful registers. + * \param pMacb Pointer to the MACB instance + */ +void GMACB_DumpRegisters(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + + uint8_t phyAddress; + uint32_t retryMax; + uint32_t value; + + TRACE_INFO("GMACB_DumpRegisters\n\r"); + + GMAC_EnableMdio(pHw); + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + TRACE_INFO("GMII MACB @ %d) Registers:\n\r", phyAddress); + + GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax); + TRACE_INFO(" _BMCR : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax); + TRACE_INFO(" _BMSR : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID1R, &value, retryMax); + TRACE_INFO(" _PHYID1 : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_PHYID2R, &value, retryMax); + TRACE_INFO(" _PHYID2 : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &value, retryMax); + TRACE_INFO(" _ANAR : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &value, retryMax); + TRACE_INFO(" _ANLPAR : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANER, &value, retryMax); + TRACE_INFO(" _ANER : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANNPR, &value, retryMax); + TRACE_INFO(" _ANNPR : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPNPAR, &value, retryMax); + TRACE_INFO(" _ANLPNPAR : 0x%X\n\r", (unsigned)value); + + TRACE_INFO(" \n\r"); + + GMACB_ReadPhy(pHw, phyAddress, GMII_RXERCR, &value, retryMax); + TRACE_INFO(" _RXERCR : 0x%X\n\r", (unsigned)value); + GMACB_ReadPhy(pHw, phyAddress, GMII_ICSR, &value, retryMax); + TRACE_INFO(" _ICSR : 0x%X\n\r", (unsigned)value); + TRACE_INFO(" \n\r"); + + GMAC_DisableMdio(pHw); +} + +/** + * \brief Setup the maximum timeout count of the driver. + * \param pMacb Pointer to the MACB instance + * \param toMax Timeout maximum count. + */ +void GMACB_SetupTimeout(GMacb *pMacb, uint32_t toMax) +{ + pMacb->retryMax = toMax; +} + +/** + * \brief Initialize the MACB instance. + * \param pMacb Pointer to the MACB instance + * \param phyAddress The PHY address used to access the PHY + */ +void GMACB_Init(GMacb *pMacb, sGmacd *pGmacd, uint8_t phyAddress) +{ + pMacb->pGmacd = pGmacd; + pMacb->phyAddress = phyAddress; + /* Initialize timeout by default */ + pMacb->retryMax = GMACB_RETRY_MAX; +} + + +/** + * \brief Issue a SW reset to reset all registers of the PHY. + * \param pMacb Pointer to the MACB instance + * \return 1 if successfully, 0 if timeout. + */ +uint8_t GMACB_ResetPhy(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + uint32_t retryMax; + uint32_t bmcr = GMII_RESET; + uint8_t phyAddress; + uint32_t timeout = 10; + uint8_t ret = 1; + + TRACE_INFO(" GMACB_ResetPhy\n\r"); + + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + GMAC_EnableMdio(pHw); + bmcr = GMII_RESET; + GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, bmcr, retryMax); + + do { + GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &bmcr, retryMax); + timeout--; + } while ((bmcr & GMII_RESET) && timeout); + + GMAC_DisableMdio(pHw); + + if (!timeout) { + ret = 0; + } + + return( ret ); +} + +/** + * \brief Do a HW initialize to the PHY ( via RSTC ) and set up clocks & PIOs + * This should be called only once to initialize the PHY pre-settings. + * The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups). + * The COL pin is used to select MII mode on reset (pulled up for Reduced MII) + * The RXDV pin is used to select test mode on reset (pulled up for test mode) + * The above pins should be predefined for corresponding settings in resetPins + * The GMAC peripheral pins are configured after the reset done. + * \param pMacb Pointer to the MACB instance + * \param mck Main clock setting to initialize clock + * \param resetPins Pointer to list of PIOs to configure before HW RESET + * (for PHY power on reset configuration latch) + * \param nbResetPins Number of PIO items that should be configured + * \param emacPins Pointer to list of PIOs for the EMAC interface + * \param nbEmacPins Number of PIO items that should be configured + * \return 1 if RESET OK, 0 if timeout. + */ +uint8_t GMACB_InitPhy(GMacb *pMacb, + uint32_t mck, + const Pin *pResetPins, + uint32_t nbResetPins, + const Pin *pGmacPins, + uint32_t nbGmacPins) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + uint8_t rc = 1; + uint8_t phy; + + /* Perform RESET */ + TRACE_DEBUG("RESET PHY\n\r"); + + if (pResetPins) { + /* Configure PINS */ + PIO_Configure(pResetPins, nbResetPins); + TRACE_INFO(" Hard Reset of GMACD Phy\n\r"); + PIO_Clear(pResetPins); + Wait(100); + PIO_Set(pResetPins); + } + /* Configure GMAC runtime pins */ + if (rc) { + + PIO_Configure(pGmacPins, nbGmacPins); + rc = GMAC_SetMdcClock(pHw, mck ); + if (!rc) { + TRACE_ERROR("No Valid MDC clock\n\r"); + return 0; + } + + /* Check PHY Address */ + phy = GMACB_FindValidPhy(pMacb); + if (phy == 0xFF) { + TRACE_ERROR("PHY Access fail\n\r"); + return 0; + } + if(phy != pMacb->phyAddress) { + pMacb->phyAddress = phy; + GMACB_ResetPhy(pMacb); + } + } + else { + TRACE_ERROR("PHY Reset Timeout\n\r"); + } + return rc; +} + +/** + * \brief Issue a Auto Negotiation of the PHY + * \param pMacb Pointer to the MACB instance + * \return 1 if successfully, 0 if timeout. + */ +uint8_t GMACB_AutoNegotiate(GMacb *pMacb) +{ + sGmacd *pDrv = pMacb->pGmacd; + Gmac *pHw = pDrv->pHw; + uint32_t retryMax; + uint32_t value; + uint32_t phyAnar; + uint32_t phyAnalpar; + uint32_t retryCount= 0; + uint8_t phyAddress; + uint8_t rc = 1; + uint32_t duplex, speed; + phyAddress = pMacb->phyAddress; + retryMax = pMacb->retryMax; + + GMAC_EnableMdio(pHw); + + if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID1R, &value, retryMax)) { + TRACE_ERROR("Pb GEMAC_ReadPhy Id1\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + TRACE_DEBUG("ReadPhy Id1 0x%X, address: %d\n\r", value, phyAddress); + if (!GMACB_ReadPhy(pHw,phyAddress, GMII_PHYID2R, &phyAnar, retryMax)) { + TRACE_ERROR("Pb GMACB_ReadPhy Id2\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar); + + if( ( value == GMII_OUI_MSB ) + && ( ((phyAnar)&(~GMII_LSB_MASK)) == GMII_OUI_LSB ) ) { + TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F)); + TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0xF)); + } else { + TRACE_ERROR("Problem OUI value\n\r"); + } + + /** Set the Auto_negotiation Advertisement Register, MII advertising for + Next page 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */ + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANAR, &phyAnar, retryMax); + if (rc == 0) { + goto AutoNegotiateExit; + } + phyAnar = GMII_TX_FDX | GMII_TX_HDX | + GMII_10_FDX | GMII_10_HDX | GMII_AN_IEEE_802_3; + rc = GMACB_WritePhy(pHw,phyAddress, GMII_ANAR, phyAnar, retryMax); + if (rc == 0) { + goto AutoNegotiateExit; + } + + /* Read & modify control register */ + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMCR, &value, retryMax); + if (rc == 0) { + goto AutoNegotiateExit; + } + + /* Check AutoNegotiate complete */ + value |= GMII_AUTONEG | GMII_RESTART_AUTONEG; + rc = GMACB_WritePhy(pHw, phyAddress, GMII_BMCR, value, retryMax); + if (rc == 0) { + goto AutoNegotiateExit; + } + TRACE_DEBUG(" _BMCR: 0x%X\n\r", value); + + // Check AutoNegotiate complete + while (1) { + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_BMSR, &value, retryMax); + if (rc == 0) { + TRACE_ERROR("rc==0\n\r"); + goto AutoNegotiateExit; + } + /* Done successfully */ + if (value & GMII_AUTONEG_COMP) { + printf("AutoNegotiate complete\n\r"); + break; + } + /* Timeout check */ + if (retryMax) { + if (++ retryCount >= retryMax) { + GMACB_DumpRegisters(pMacb); + TRACE_ERROR("TimeOut\n\r"); + rc = 0; + goto AutoNegotiateExit; + } + } + } + + /*Set local link mode */ + while(1) { + rc = GMACB_ReadPhy(pHw, phyAddress, GMII_ANLPAR, &phyAnalpar, retryMax); + if (rc == 0) { + goto AutoNegotiateExit; + } + /* Set up the GMAC link speed */ + if ((phyAnar & phyAnalpar) & GMII_TX_FDX) { + /* set RGMII for 1000BaseTX and Full Duplex */ + duplex = GMAC_DUPLEX_FULL; + speed = GMAC_SPEED_100M; + break; + } else if ((phyAnar & phyAnalpar) & GMII_10_FDX) { + /* set RGMII for 1000BaseT and Half Duplex*/ + duplex = GMAC_DUPLEX_FULL; + speed = GMAC_SPEED_10M; + break; + } else if ((phyAnar & phyAnalpar) & GMII_TX_HDX) { + /* set RGMII for 100BaseTX and half Duplex */ + duplex = GMAC_DUPLEX_HALF; + speed = GMAC_SPEED_100M; + break; + } else if ((phyAnar & phyAnalpar) & GMII_10_HDX) { + // set RGMII for 10BaseT and half Duplex + duplex = GMAC_DUPLEX_HALF; + speed = GMAC_SPEED_10M; + break; + } + } + TRACE_INFO("GMAC_EnableRGMII duplex %u, speed %u\n\r",(unsigned)duplex,(unsigned)speed); + + GMACB_ReadPhy(pHw,phyAddress, GMII_PC1R, &value, retryMax); + GMACB_ReadPhy(pHw,phyAddress, GMII_PC2R, &value, retryMax); + GMACB_ReadPhy(pHw,phyAddress, GMII_ICSR, &value, retryMax); + /* Set up GMAC mode */ + GMAC_EnableRGMII(pHw, duplex, speed); + +AutoNegotiateExit: + GMAC_DisableMdio(pHw); + return rc; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ili9488.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ili9488.c new file mode 100644 index 000000000..65aed6a68 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ili9488.c @@ -0,0 +1,369 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of ILI9488 driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" +#include +#include + +#ifdef BOARD_LCD_ILI9488 + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Pio pins to configure. */ +static const Pin ILI9488_Reset[] = {LCD_PIN_RESET}; +static const Pin ILI9488_Pwm[] = {BOARD_LCD_PIN_BACKLIGHT}; +/** Pins to configure for the application. */ +static const Pin lcd_pins[] = BOARD_LCD_PINS; +/** Pins to configure for the application. */ +static const Pin ILI9488_CDS[] = {BOARD_LCD_PIN_CDS}; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ +/** + * \brief ILI9488 Hardware Initialization for SPI/SMC LCD. + */ +static void _ILI9488_HW_Initialize(void) +{ + /* Pin configurations */ + PIO_Configure(ILI9488_Reset, PIO_LISTSIZE(ILI9488_Reset)); + PIO_Configure(ILI9488_CDS, PIO_LISTSIZE(ILI9488_CDS)); + PIO_Configure(lcd_pins, PIO_LISTSIZE(lcd_pins)); + PIO_Configure(ILI9488_Pwm, PIO_LISTSIZE(ILI9488_Pwm)); + +#if !defined(BOARD_LCD_SMC) + /* Enable PWM peripheral clock */ + PMC_EnablePeripheral(ID_PWM0); + PMC_EnablePeripheral(ILI9488_ID); + /* Set clock A and clock B */ + // set for 14.11 KHz for CABC control + // mode = PWM_CLK_PREB(0x0A) | (PWM_CLK_DIVB(110)) | + // PWM_CLK_PREA(0x0A) | (PWM_CLK_DIVA(110)); + PWMC_ConfigureClocks(PWM0, 14200, 0, BOARD_MCK); + + /* Configure PWM channel 1 for LED0 */ + PWMC_DisableChannel(PWM0, CHANNEL_PWM_LCD); + + PWMC_ConfigureChannel(PWM0, CHANNEL_PWM_LCD, PWM_CMR_CPRE_CLKA,0,PWM_CMR_CPOL); + PWMC_SetPeriod(PWM0, CHANNEL_PWM_LCD, 16); + PWMC_SetDutyCycle(PWM0, CHANNEL_PWM_LCD, 8); + PWMC_EnableChannel(PWM0, CHANNEL_PWM_LCD); + + SPI_Configure(ILI9488, ILI9488_ID, (SPI_MR_MSTR | SPI_MR_MODFDIS | SPI_PCS( SMC_EBI_LCD_CS ))); + SPI_ConfigureNPCS( ILI9488, + SMC_EBI_LCD_CS, + SPI_CSR_CPOL | SPI_CSR_BITS_8_BIT | SPI_DLYBS(6, BOARD_MCK) | SPI_DLYBCT(100, BOARD_MCK) | + SPI_SCBR( 20000000, BOARD_MCK) ) ; + SPI_Enable(ILI9488); +#else + PIO_Set(ILI9488_Pwm); +#endif +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Set ILI9488 Pixel Format in SPI/SMC mode. + * \param format Format of pixel + */ +void ILI9488_SetPixelFormat(uint16_t format) +{ + ILI9488_WriteReg(ILI9488_CMD_COLMOD_PIXEL_FORMAT_SET, &format, sizeof(format)); +} + +/** + * \brief ILI9488 issue MEMORY write command in SPI/SMC mode. + */ +void ILI9488_MemWriteCmd(void) +{ + ILI9488_SendCmd(ILI9488_CMD_MEMORY_WRITE); +} + +/** + * \brief ILI9488 issue MEMORY read command in SPI/SMC mode. + */ +void ILI9488_MemReadCmd(void) +{ + ILI9488_SendCmd(ILI9488_CMD_MEMORY_READ); +} + +/** + * \brief ILI9488 Write memory with give buffer in SPI/SMC mode. + * \Param pBuf Point to buffer to be written. + * \Param size Size of buffer in byte. + */ +void ILI9488_WriteMemory( const uint16_t *pBuf, uint32_t size) +{ + ILI9488DmaTxTransfer((uint16_t *)pBuf,size); +} + +/** + * \brief ILI9488 Read memory to give buffer in SPI/SMC mode. + * \Param pBuf Point to buffer to be read. + * \Param size Size of buffer in byte. + */ +void ILI9488_ReadMemory( const uint16_t *pBuf, uint32_t size) +{ + uint32_t cnt; +#if !defined(BOARD_LCD_SMC) + cnt = size*3; +#else + cnt = size; +#endif + ILI9488DmaRxTransfer((uint32_t *)pBuf,cnt); +} + +/** + * \brief Initialize the ILI9488 controller in SPI/SMC mode. + */ +uint32_t ILI9488_Initialize( void ) +{ + uint32_t chipid; + uint16_t param; + + _ILI9488_HW_Initialize(); + ILI9488_InitializeWithDma(); + + ILI9488_WriteReg(ILI9488_CMD_SOFTWARE_RESET,¶m,0); + Wait(200); + + ILI9488_WriteReg(ILI9488_CMD_SLEEP_OUT,¶m,0); + Wait(200); + + // make it tRGB and reverse the column order + param = 0x48; + ILI9488_WriteReg(ILI9488_CMD_MEMORY_ACCESS_CONTROL,¶m,1); + Wait(100); + + param = 0x04; + ILI9488_WriteReg(ILI9488_CMD_CABC_CONTROL_9,¶m,1); + + chipid = ILI9488ReadExtReg(ILI9488_CMD_READ_ID4,3); + if ( chipid != ILI9488_DEVICE_CODE ) + { + printf( "Read ILI9488 chip ID (0x%04x) error, skip initialization.\r\n", (unsigned int)chipid ) ; + return 1 ; + } + +#if !defined(BOARD_LCD_SMC) + ILI9488_SetPixelFormat(6); +#else + ILI9488_SetPixelFormat(5); +#endif + ILI9488_WriteReg(ILI9488_CMD_NORMAL_DISP_MODE_ON,¶m,0); + ILI9488_WriteReg(ILI9488_CMD_DISPLAY_ON,¶m,0); + return 0 ; +} + +/** + * \brief ILI9488 configure cursor in SPI/SMC mode. + * \Param x X position. + * \Param y Y position. + */ +void ILI9488_SetCursor(uint16_t x, uint16_t y) +{ + /* Set Horizontal Address Start Position */ + uint32_t cnt = 0; + +#if !defined(BOARD_LCD_SMC) + uint8_t buf[4]; + cnt = sizeof(buf); +#else + uint16_t buf[4]; + cnt = sizeof(buf)/sizeof(uint16_t); +#endif + + buf[0] = get_8b_to_16b(x); + buf[1] = get_0b_to_8b(x); + x+=1; + buf[2] = get_8b_to_16b(x); + buf[3] = get_0b_to_8b(x); + ILI9488_WriteReg(ILI9488_CMD_COLUMN_ADDRESS_SET,(uint16_t*)buf,cnt); + ILI9488_SendCmd(ILI9488_CMD_NOP); + + + /* Set Horizontal Address End Position */ + buf[0] = get_8b_to_16b(y); + buf[1] = get_0b_to_8b(y); + y+=1; + buf[2] = get_8b_to_16b(y); + buf[3] = get_0b_to_8b(y); + ILI9488_WriteReg(ILI9488_CMD_PAGE_ADDRESS_SET,(uint16_t*)buf,cnt); + ILI9488_SendCmd(ILI9488_CMD_NOP); +} + +/** + * \brief ILI9488 configure window. + * \Param dwX X start position. + * \Param dwX Y start position. + * \Param dwWidth Width of window. + * \Param dwHeight Height of window. + */ +void ILI9488_SetWindow( uint16_t dwX, uint16_t dwY, uint16_t dwWidth, uint16_t dwHeight ) +{ + uint16_t ColStart, ColEnd, RowStart, RowEnd; + + uint32_t cnt = 0; + +#if !defined(BOARD_LCD_SMC) + uint8_t buf[4]; + cnt = sizeof(buf); +#else + uint16_t buf[4]; + cnt = sizeof(buf)/sizeof(uint16_t); +#endif + + ColStart = dwX ; + ColEnd = dwWidth; + + RowStart = dwY ; + RowEnd = dwHeight; + + buf[0] = get_8b_to_16b(ColStart); + buf[1] = get_0b_to_8b(ColStart); + buf[2] = get_8b_to_16b(ColEnd); + buf[3] = get_0b_to_8b(ColEnd); + ILI9488_WriteReg(ILI9488_CMD_COLUMN_ADDRESS_SET, (uint16_t*)buf, cnt); + ILI9488_SendCmd(ILI9488_CMD_NOP); + + /* Set Horizontal Address End Position */ + buf[0] = get_8b_to_16b(RowStart); + buf[1] = get_0b_to_8b(RowStart); + buf[2] = get_8b_to_16b(RowEnd); + buf[3] = get_0b_to_8b(RowEnd); + ILI9488_WriteReg(ILI9488_CMD_PAGE_ADDRESS_SET,(uint16_t*)buf,cnt); + ILI9488_SendCmd(ILI9488_CMD_NOP); +} + +/** + * \brief ILI9488 configure window with full size. + */ +void ILI9488_SetFullWindow(void) +{ + uint16_t c_start,c_end,r_start,r_end; + uint32_t cnt = 0; + +#if !defined(BOARD_LCD_SMC) + uint8_t buf[4]; + cnt = sizeof(buf); +#else + uint16_t buf[4]; + cnt = sizeof(buf)/sizeof(uint16_t); +#endif + + c_start = 0 ; + c_end = ILI9488_LCD_WIDTH- 1; + + r_start = 0 ; + r_end = ILI9488_LCD_HEIGHT - 1; + + /* Set Horizontal Address Start Position */ + buf[0] = get_8b_to_16b(c_start); + buf[1] = get_0b_to_8b(c_start); + buf[2] = get_8b_to_16b(c_end); + buf[3] = get_0b_to_8b(c_end); + ILI9488_WriteReg(ILI9488_CMD_COLUMN_ADDRESS_SET,(uint16_t*)buf,cnt); + ILI9488_SendCmd(ILI9488_CMD_NOP); + + /* Set Horizontal Address End Position */ + buf[0] = get_8b_to_16b(r_start); + buf[1] = get_0b_to_8b(r_start); + buf[2] = get_8b_to_16b(r_end); + buf[3] = get_0b_to_8b(r_end); + ILI9488_WriteReg(ILI9488_CMD_COLUMN_ADDRESS_SET,(uint16_t*)buf,cnt); + ILI9488_SendCmd(ILI9488_CMD_NOP); +} + + +/** + * \brief Turn on the ILI9488. + */ +void ILI9488_On( void ) +{ + ILI9488_SendCmd(ILI9488_CMD_PIXEL_OFF); + ILI9488_SendCmd(ILI9488_CMD_DISPLAY_ON); + ILI9488_SendCmd(ILI9488_CMD_NORMAL_DISP_MODE_ON); +} + +/** + * \brief Turn off the ILI9488. + */ +void ILI9488_Off( void ) +{ + ILI9488_SendCmd(ILI9488_CMD_DISPLAY_OFF); +} + +/** + * \brief ILI9488 configure landscape. + * \Param dwRGB RGB mode. + * \Param LandscaprMode Landscape Mode. + */ +void ILI9488_SetDisplayLandscape( uint8_t dwRGB, uint8_t LandscapeMode ) +{ + uint16_t value; + if(LandscapeMode) + { + if(dwRGB) + { + value = 0xE8; + } + else + { + value = 0xE0; + } + } + else + { + if(dwRGB) + { + value = 0x48; + } + else + { + value = 0x40; + } + } + ILI9488_WriteReg(ILI9488_CMD_MEMORY_ACCESS_CONTROL, &value, sizeof(value)); +} + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ili9488_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ili9488_dma.c new file mode 100644 index 000000000..e2012a6c4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ili9488_dma.c @@ -0,0 +1,469 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of ILI9488 SPI DMA driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + +#include +#include + +#ifdef BOARD_LCD_ILI9488 + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ +/** Pins to configure for the application. */ +static const Pin ILI9488_CDS[] = { BOARD_LCD_PIN_CDS}; + +static sIli9488Dma ili9488Dma; +static sIli9488DmaCtl ili9488DmaCtl; + /* Maximum 5 bytes data buffer */ +static uint32_t paramBuf[5]; +static sXdmad xDmaLcd; + +void XDMAC_Handler(void) +{ + XDMAD_Handler(&xDmaLcd); +} + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +#if defined(BOARD_LCD_SMC) + +/** + * \brief Configure SMC timing for static memory (LCD) + */ +static void _ILI9488_ConfigureSmc( void ) +{ + /* Enable peripheral clock */ + PMC_EnablePeripheral( ID_SMC ) ; + + /* Configure SMC, NCS3 is assigned to LCD */ + + SMC->SMC_CS_NUMBER[SMC_EBI_LCD_CS].SMC_SETUP = SMC_SETUP_NWE_SETUP(2) + | SMC_SETUP_NCS_WR_SETUP(0) + | SMC_SETUP_NRD_SETUP(0) + | SMC_SETUP_NCS_RD_SETUP(0); + + SMC->SMC_CS_NUMBER[SMC_EBI_LCD_CS].SMC_PULSE = SMC_PULSE_NWE_PULSE(6) + | SMC_PULSE_NCS_WR_PULSE(0xA) + | SMC_PULSE_NRD_PULSE(0xA) + | SMC_PULSE_NCS_RD_PULSE(0xA); + + SMC->SMC_CS_NUMBER[SMC_EBI_LCD_CS].SMC_CYCLE = SMC_CYCLE_NWE_CYCLE(0xA) + | SMC_CYCLE_NRD_CYCLE(0xA); + + SMC->SMC_CS_NUMBER[SMC_EBI_LCD_CS].SMC_MODE = SMC_MODE_READ_MODE + | SMC_MODE_WRITE_MODE + | SMC_MODE_DBW_16_BIT + | SMC_MODE_EXNW_MODE_DISABLED + | SMC_MODE_TDF_CYCLES(0xF); +} +#endif + + +/** + * \brief ILI9488_SPI xDMA Rx callback + */ +static void _ILI9488_Rx_CB(void) +{ + if(!ili9488DmaCtl.Cds) + ili9488DmaCtl.rxDone = 1; +} + +/** + * \brief ILI9488_SPI xDMA Tx callback + */ +static void _ILI9488_Tx_CB(void) +{ + volatile uint32_t i; + if(ili9488DmaCtl.Cds) + { + for(i = 0; i<0xF; i++); + PIO_Set(ILI9488_CDS); + ili9488DmaCtl.Cds = 0; + } + ili9488DmaCtl.txDone = 1; +} + +/** + * \brief Initializes the ILI9488Dma structure and the corresponding DMA hardware. + * select value. + */ +static void _ILI9488DmaInitialize(void) +{ + ili9488DmaCtl.Cds = 1; + ili9488DmaCtl.rxDone = 0; + ili9488DmaCtl.txDone = 1; + + ili9488Dma.xdmaD = &xDmaLcd; + ili9488Dma.xdmaD->pXdmacs = XDMAC; + ili9488Dma.ili9488DmaTxChannel = 0; + ili9488Dma.ili9488DmaRxChannel = 0; + ili9488Dma.xdmaInt = 0; + ili9488Dma.pSpiHw = ILI9488_SPI; + ili9488Dma.spiId = ILI9488_SPI_ID; +} + +/** + * \brief This function initialize the appropriate DMA channel for Rx/Tx channel of SPI or SMC + * \returns 0 if the transfer has been started successfully; otherwise returns + * ILI9488_ERROR_XX is the driver is in use, or ILI9488_ERROR_XX if the command is not + * valid. + */ +static uint8_t _ILI9488DmaConfigChannels(void) +{ + uint32_t srcType,dstType; + + /* Driver initialize */ + XDMAD_Initialize( ili9488Dma.xdmaD, 0 ); + + XDMAD_FreeChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel); + XDMAD_FreeChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel); + +#if !defined(BOARD_LCD_SMC) + srcType = XDMAD_TRANSFER_MEMORY; + dstType = ili9488Dma.spiId; +#else + srcType = XDMAD_TRANSFER_MEMORY; + dstType = XDMAD_TRANSFER_MEMORY; +#endif + + /* Allocate a DMA channel for ILI9488_SPI TX. */ + ili9488Dma.ili9488DmaTxChannel = XDMAD_AllocateChannel( ili9488Dma.xdmaD, srcType, dstType); + { + if ( ili9488Dma.ili9488DmaTxChannel == XDMAD_ALLOC_FAILED ) + { + return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL; + } + } + + /* Allocate a DMA channel for ILI9488_SPI RX. */ + ili9488Dma.ili9488DmaRxChannel = XDMAD_AllocateChannel( ili9488Dma.xdmaD, dstType, srcType); + { + if ( ili9488Dma.ili9488DmaRxChannel == XDMAD_ALLOC_FAILED ) + { + return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL; + } + } + + /* Setup callbacks for ILI9488_SPI RX */ + XDMAD_SetCallback(ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel, (XdmadTransferCallback)_ILI9488_Rx_CB, &ili9488Dma); + if (XDMAD_PrepareChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel )) + return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL; + + /* Setup callbacks for ILI9488_SPI TX (ignored) */ + XDMAD_SetCallback(ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel, (XdmadTransferCallback)_ILI9488_Tx_CB, &ili9488Dma); + if ( XDMAD_PrepareChannel( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel )) + return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL; + + /* Check if DMA IRQ is enable; if not Enable it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) + { + /* Enable interrupt */ + NVIC_EnableIRQ(XDMAC_IRQn); + } + return 0; +} + +/** + * \brief Configure the SPI/SMC tx/rx DMA. + * \returns 0 if the xDMA configuration successfully; otherwise returns + * ILI9488_ERROR_XXX. + */ +static uint8_t _ILI9488DmaConfigureRxTx(void) +{ + uint32_t txAddress,rxAddress; + sXdmad *pXdmad; + pXdmad = ili9488Dma.xdmaD; + +#if !defined(BOARD_LCD_SMC) + txAddress = (uint32_t)&ILI9488_SPI->SPI_TDR; + rxAddress = (uint32_t)&ILI9488_SPI->SPI_RDR; + ili9488Dma.xdmadExtTxCfg.mbr_cfg = + XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_DSYNC_MEM2PER + | XDMAC_CC_DWIDTH_BYTE + | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ili9488Dma.spiId, XDMAD_TRANSFER_TX )); + + ili9488Dma.xdmadExtRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(ili9488Dma.spiId, XDMAD_TRANSFER_RX )); +#else + txAddress = rxAddress =(uint32_t)ILI9488_BASE_ADDRESS; + ili9488Dma.xdmadExtTxCfg.mbr_cfg = XDMAC_CC_DWIDTH_HALFWORD; + ili9488Dma.xdmadExtRxCfg.mbr_cfg = 0; +#endif + + /* Setup DMA TX channel */ + ili9488Dma.xdmadTxCfg.mbr_sa = 0; + ili9488Dma.xdmadTxCfg.mbr_da = txAddress; + ili9488Dma.xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | XDMA_UBC_NDE_FETCH_DIS| XDMA_UBC_NSEN_UPDATED ; + + ili9488Dma.xdmadTxCfg.mbr_cfg = + XDMAC_CC_TYPE_MEM_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_SIF_AHB_IF0 + | XDMAC_CC_DIF_AHB_IF1 + | XDMAC_CC_SAM_INCREMENTED_AM + | XDMAC_CC_DAM_FIXED_AM; + + ili9488Dma.xdmadTxCfg.mbr_cfg |= ili9488Dma.xdmadExtTxCfg.mbr_cfg; + + ili9488Dma.xdmadTxCfg.mbr_bc = 0; + ili9488Dma.xdmadTxCfg.mbr_sus = 0; + ili9488Dma.xdmadTxCfg.mbr_dus = 0; + + /* Setup RX DMA channel */ + ili9488Dma.xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | XDMA_UBC_NDE_FETCH_DIS | XDMA_UBC_NDEN_UPDATED ; + ili9488Dma.xdmadRxCfg.mbr_da = 0; + ili9488Dma.xdmadRxCfg.mbr_sa = rxAddress; + + ili9488Dma.xdmadRxCfg.mbr_cfg = + XDMAC_CC_TYPE_MEM_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_WORD + | XDMAC_CC_SIF_AHB_IF1 + | XDMAC_CC_DIF_AHB_IF0 + | XDMAC_CC_SAM_FIXED_AM + | XDMAC_CC_DAM_INCREMENTED_AM; + + ili9488Dma.xdmadRxCfg.mbr_cfg |= ili9488Dma.xdmadExtRxCfg.mbr_cfg; + ili9488Dma.xdmadRxCfg.mbr_bc = 0; + ili9488Dma.xdmadRxCfg.mbr_sus = 0; + ili9488Dma.xdmadRxCfg.mbr_dus =0; + + /* Put all interrupts on for non LLI list setup of DMA */ + ili9488Dma.xdmaInt = (XDMAC_CIE_BIE + | XDMAC_CIE_RBIE + | XDMAC_CIE_WBIE + | XDMAC_CIE_ROIE); + + if (XDMAD_ConfigureTransfer( pXdmad, ili9488Dma.ili9488DmaRxChannel, &ili9488Dma.xdmadRxCfg, 0, 0, ili9488Dma.xdmaInt)) + return ILI9488_ERROR_DMA_CONFIGURE; + + if (XDMAD_ConfigureTransfer( pXdmad, ili9488Dma.ili9488DmaTxChannel, &ili9488Dma.xdmadTxCfg, 0, 0, ili9488Dma.xdmaInt)) + return ILI9488_ERROR_DMA_CONFIGURE; + return 0; +} + +/** + * \brief Update Rx/Tx DMA configuration with new buffer address and buffer size. + * \param pTxBuffer point to Tx buffer address + * \param wTxSize Tx buffer size in byte + * \param pRxBuffer point to Rx buffer address + * \param wRxSize Rx buffer size in byte + * \returns 0 if the xDMA configuration successfully; otherwise returns + * ILI9488_DMA_ERROR_XXX. + */ +static uint8_t _ILI9488DmaUpdateBuffer(uint16_t *pTxBuffer,uint32_t wTxSize, uint32_t *pRxBuffer,uint32_t wRxSize) +{ + sXdmad *pXdmad; + pXdmad = ili9488Dma.xdmaD; + + ili9488Dma.xdmadTxCfg.mbr_sa = (uint32_t)pTxBuffer; + ili9488Dma.xdmadTxCfg.mbr_ubc = wTxSize; + + ili9488Dma.xdmadRxCfg.mbr_da = (uint32_t)pRxBuffer; + ili9488Dma.xdmadRxCfg.mbr_ubc = wRxSize; + + if (XDMAD_ConfigureTransfer( pXdmad, ili9488Dma.ili9488DmaRxChannel, &ili9488Dma.xdmadRxCfg, 0, 0, ili9488Dma.xdmaInt)) + return ILI9488_ERROR_DMA_CONFIGURE; + if (XDMAD_ConfigureTransfer( pXdmad, ili9488Dma.ili9488DmaTxChannel, &ili9488Dma.xdmadTxCfg, 0, 0, ili9488Dma.xdmaInt)) + return ILI9488_ERROR_DMA_CONFIGURE; + return 0; +} + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initialize ILI9488 driver with DMA support. + * \returns 0 if the xDMA configuration successfully; otherwise returns + * ILI9488_DMA_ERROR_XXX. + */ +uint8_t ILI9488_InitializeWithDma(void) +{ +#if defined(BOARD_LCD_SMC) + _ILI9488_ConfigureSmc(); +#endif + _ILI9488DmaInitialize(); + if (_ILI9488DmaConfigChannels()) return ILI9488_ERROR_DMA_ALLOCATE_CHANNEL; + if(_ILI9488DmaConfigureRxTx()) return ILI9488_ERROR_DMA_CONFIGURE; + return 0; +} + +/** + * \brief Start ILI9488 DMA transfer . + * \param pTxBuffer point to Tx buffer address + * \param wTxSize Tx buffer size in byte + * \returns 0 if the xDMA configuration successfully; otherwise returns + * ILI9488_DMA_ERROR_XXX. + */ +uint8_t ILI9488DmaTxTransfer( uint16_t *pTxBuffer,uint32_t wTxSize) +{ + _ILI9488DmaUpdateBuffer(pTxBuffer, wTxSize, 0, 0); + SCB_CleanInvalidateDCache(); + if (XDMAD_StartTransfer( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel)) + return ILI9488_ERROR_DMA_TRANSFER; + while(!ili9488DmaCtl.txDone); + ili9488DmaCtl.txDone = 0; + + return 0; +} + +/** + * \brief Start ILI9488 DMA Rx transfer . + * \param pRxBuffer point to Rx buffer address + * \param wRxSize Rx buffer size in byte + * \returns 0 if the xDMA transfer successfully; otherwise returns ILI9488_DMA_ERROR_XXX. + */ +uint8_t ILI9488DmaRxTransfer(uint32_t *pRxBuffer,uint32_t wRxSize) +{ + uint16_t dummyTxBuffer[5]; + + _ILI9488DmaUpdateBuffer(dummyTxBuffer, wRxSize, pRxBuffer, wRxSize); + + SCB_CleanInvalidateDCache(); + if (XDMAD_StartTransfer( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaRxChannel)) + return ILI9488_ERROR_DMA_TRANSFER; + +#if !defined(BOARD_LCD_SMC) + if (XDMAD_StartTransfer( ili9488Dma.xdmaD, ili9488Dma.ili9488DmaTxChannel)) + return ILI9488_ERROR_DMA_TRANSFER; +#endif + return 0; +} + +/** + * \brief ILI9488 Send command with DMA. + * \param command Command to be sent + * \returns 0 if the xDMA transfer successfully; otherwise returns ILI9488_DMA_ERROR_XXX. + */ +uint8_t ILI9488_SendCmd( uint16_t command ) +{ + PIO_Clear(ILI9488_CDS); + ili9488DmaCtl.Cds = 1; + return ILI9488DmaTxTransfer((uint16_t*)&command, 1 ); +} + +/** + * \brief ILI9488 Write register for SPI/SMC mode. + * \param command Command to be sent + * \param pTxBuffer Point to tx buffer contains parameters + * \param bufSize Size of buffer + * \returns 0 if the xDMA transfer successfully; otherwise returns ILI9488_DMA_ERROR_XXX. + */ +void ILI9488_WriteReg(uint16_t command, uint16_t* pTxBuffer, uint32_t bufSize) +{ + ILI9488_SendCmd(command); + if(bufSize == 0) return; + ILI9488DmaTxTransfer(pTxBuffer,bufSize); +} + +/** + * \brief ILI9488 Read registers for SPI/SMC mode. + * \param command Command to be sent + * \param size Size of parameters + * \returns register value. + */ +uint32_t ILI9488ReadReg(uint16_t cmd,uint32_t size) +{ + uint32_t i; + uint32_t value = 0; + uint32_t *ptr; + uint32_t shift_cnt = size-1; + + if (size > 4) return ILI9488_ERROR_DMA_SIZE; + + ILI9488_SendCmd(cmd); + ILI9488DmaRxTransfer(paramBuf, size+1); + + while(!ili9488DmaCtl.rxDone); + ili9488DmaCtl.rxDone = 0; + + ptr = ¶mBuf[1]; + for(i = 1; i < size+1;i++) + { + value |= (*ptr&0xFF)<<(shift_cnt << 3); + ptr++; + shift_cnt--; + } + return value; +} + + +/** + * \brief ILI9488 Read Ext registers for SPI/SMC mode. + * \param command Command to be sent + * \param size Size of buffer + * \returns Ext register value. + */ +uint32_t ILI9488ReadExtReg(uint16_t cmd,uint32_t size) +{ + uint32_t value=0; + +#if !defined(BOARD_LCD_SMC) + uint32_t shift_cnt = size-1; + uint16_t nSpiCnt = 0x81; + uint16_t def_val = 0; + + if (size > 4) return ILI9488_ERROR_DMA_SIZE; + while(size > 0) + { + ILI9488_WriteReg(ILI9488_CMD_SPI_READ_SETTINGS,&nSpiCnt,1); + ILI9488_SendCmd(cmd); + ILI9488DmaRxTransfer( paramBuf,2); + while(!ili9488DmaCtl.rxDone); + ili9488DmaCtl.rxDone = 0; + ILI9488_WriteReg(ILI9488_CMD_SPI_READ_SETTINGS,&def_val,1); + value |= (paramBuf[1]&0xFF)<<(shift_cnt << 3); + nSpiCnt++; + shift_cnt--; + size--; + } +#else + value = ILI9488ReadReg(cmd,size); +#endif + return value; +} +#endif //BOARD_LCD_ILI9488 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_draw.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_draw.c new file mode 100644 index 000000000..0a7fee561 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_draw.c @@ -0,0 +1,655 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of draw function on LCD, Include draw text, image + * and basic shapes (line, rectangle, circle). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ +static void* gpCanvasBuffer; +static uint32_t gwCanvasBufferSize; +static uint32_t gwCanvasMaxWidth, gwCanvasMaxHeight; +extern uint8_t ili9488_lcdMode; +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/* + * \brief Fill rectangle with given color + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param rc rectangle defines X and Y coordinate, width and height of windows. + * \param dwColor color to be filled. + */ +static void LCDD_FillSolidRect(uint16_t *pCanvasBuffer, rect rc, uint32_t dwColor ) +{ + uint32_t row, col; + uint32_t w,h; + + //assert(gpCanvasBuffer!=NULL); + w = rc.x + rc.width; + w = w > gwCanvasMaxWidth ? gwCanvasMaxWidth : w; + h = rc.y + rc.height; + h = h > gwCanvasMaxHeight ? gwCanvasMaxHeight : h; + + if (ili9488_lcdMode == ILI9488_SPIMODE) { + sBGR *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = (sBGR *)((uint8_t*)pCanvasBuffer); + //it'd better change to a DMA transfer + for(row = rc.y; row < h; row++) { + for(col = rc.x; col < w; col++) { + //*p_buf++ = dwColor; + p_buf[row * gwCanvasMaxWidth + col].b = dwColor&0xFF; + p_buf[row * gwCanvasMaxWidth + col].g = dwColor>>8; + p_buf[row * gwCanvasMaxWidth + col].r = dwColor>>16; + } + } + } else { + uint16_t *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = pCanvasBuffer; + //it'd better change to a DMA transfer + for(row = rc.y; row < h; row++) { + for(col = rc.x; col < w; col++) { + p_buf[row * gwCanvasMaxWidth + col] = (uint16_t)dwColor; + } + } + } +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/* + * \brief Update windows size. + * \param rc rectangle defines X and Y coordinate, width and height of windows. + */ +void LCDD_SetUpdateWindowSize(rect rc) +{ + gwCanvasMaxWidth = rc.width + 1; + gwCanvasMaxHeight = rc.height + 1; + if (ili9488_lcdMode == ILI9488_SPIMODE) { + ILI9488_SpiSetWindow( rc.x, rc.y, rc.width, rc.height); + } else { + ILI9488_EbiSetWindow( rc.x, rc.y, rc.width, rc.height); + } +} + +/* + * \brief Update windows in current canvas. + */ +void LCDD_UpdateWindow(void) +{ + uint32_t size = 0; + if (ili9488_lcdMode == ILI9488_SPIMODE) { + size = gwCanvasBufferSize / (sizeof(sBGR)) *3 ; + ILI9488_SpiSendCommand(ILI9488_CMD_MEMORY_WRITE, + (uint8_t*)gpCanvasBuffer, 0, AccessWrite, size); + } else { + size = gwCanvasBufferSize / sizeof(uint16_t); + ILI9488_EbiSendCommand(ILI9488_CMD_MEMORY_WRITE, + (uint16_t*)gpCanvasBuffer, 0, AccessWrite, size); + } + } + +/* + * \brief Update windows in partial canvas. + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param size Size of canvas buffer. + */ +void LCDD_UpdatePartialWindow(uint8_t* pCanvasBuffer,uint32_t size) +{ + uint32_t cnt = 0; + if (ili9488_lcdMode == ILI9488_SPIMODE) { + cnt = size/sizeof(sBGR) * 3; + ILI9488_SpiSendCommand(ILI9488_CMD_MEMORY_WRITE, + (uint8_t*)pCanvasBuffer, 0, AccessWrite, cnt); + } else { + cnt = size/sizeof(uint16_t); + ILI9488_EbiSendCommand(ILI9488_CMD_MEMORY_WRITE, + (uint16_t*)pCanvasBuffer, 0, AccessWrite, cnt); + } +} +/* + * \brief Draws a rectangle with fill inside on LCD, at the given coordinates. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param x X-coordinate of upper-left rectangle corner. + * \param y Y-coordinate of upper-left rectangle corner. + * \param width Rectangle width in pixels. + * \param height Rectangle height in pixels. + * \param color Rectangle color. + */ +void LCDD_DrawRectangleWithFill(uint16_t *pCanvasBuffer, uint32_t dwX, uint32_t dwY, uint32_t dwWidth, + uint32_t dwHeight, uint32_t dwColor) +{ + rect rc; + rc.x = dwX; + rc.y = dwY; + rc.width = dwWidth + 1; + rc.height = dwHeight + 1; + LCDD_FillSolidRect(pCanvasBuffer, rc , dwColor); +} + +/** + * \brief Draws a circle on LCD, at the given coordinates. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param x X-coordinate of circle centre. + * \param y Y-coordinate of circle centre. + * \param r circle radius. + * \param color circle color. + */ +uint32_t LCDD_DrawCircle(uint16_t *pCanvasBuffer, uint32_t x, uint32_t y, uint32_t r, uint32_t color ) +{ + signed int d; /* Decision Variable */ + uint32_t curX; /* Current X Value */ + uint32_t curY; /* Current Y Value */ + + d = 3 - (r << 1); + curX = 0; + curY = r; + + while (curX <= curY) { + LCDD_DrawPixel(pCanvasBuffer, x + curX, y + curY, color); + LCDD_DrawPixel(pCanvasBuffer, x + curX, y - curY, color); + LCDD_DrawPixel(pCanvasBuffer, x - curX, y + curY, color); + LCDD_DrawPixel(pCanvasBuffer, x - curX, y - curY, color); + LCDD_DrawPixel(pCanvasBuffer, x + curY, y + curX, color); + LCDD_DrawPixel(pCanvasBuffer, x + curY, y - curX, color); + LCDD_DrawPixel(pCanvasBuffer, x - curY, y + curX, color); + LCDD_DrawPixel(pCanvasBuffer, x - curY, y - curX, color); + + if (d < 0) { + d += (curX << 2) + 6; + } else { + d += ((curX - curY) << 2) + 10; + curY--; + } + curX++; + } + return 0; +} + +/* + * \brief Draws a circle with fill inside on LCD, at the given coordinates. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dwX X-coordinate of upper-left rectangle corner. + * \param dwY Y-coordinate of upper-left rectangle corner. + * \param dwRadius Radius. + * \param color Rectangle color. + */ +uint32_t LCD_DrawFilledCircle(uint16_t *pCanvasBuffer, uint32_t dwX, uint32_t dwY, + uint32_t dwRadius, uint32_t color) +{ + signed int d; /* Decision Variable */ + uint32_t dwCurX; /* Current X Value */ + uint32_t dwCurY; /* Current Y Value */ + uint32_t dwXmin, dwYmin; + + if (dwRadius == 0) { + return 0; + } + d = 3 - (dwRadius << 1); + dwCurX = 0; + dwCurY = dwRadius; + + while ( dwCurX <= dwCurY ) { + dwXmin = (dwCurX > dwX) ? 0 : dwX-dwCurX; + dwYmin = (dwCurY > dwY) ? 0 : dwY-dwCurY; + LCDD_DrawRectangleWithFill(pCanvasBuffer, dwXmin, dwYmin, + dwX + dwCurX - dwXmin, 1 ,color); + LCDD_DrawRectangleWithFill(pCanvasBuffer, dwXmin, + dwY+dwCurY, dwX + dwCurX - dwXmin, 1, + color ); + dwXmin = (dwCurY > dwX) ? 0 : dwX-dwCurY; + dwYmin = (dwCurX > dwY) ? 0 : dwY-dwCurX; + LCDD_DrawRectangleWithFill(pCanvasBuffer, dwXmin, dwYmin, + dwX + dwCurY -dwXmin , 1, color ); + LCDD_DrawRectangleWithFill(pCanvasBuffer, dwXmin, + dwY + dwCurX, dwX+dwCurY - dwXmin, 1, + color ); + if ( d < 0 ) { + d += (dwCurX << 2) + 6; + } else { + d += ((dwCurX - dwCurY) << 2) + 10; + dwCurY--; + } + dwCurX++; + } + + return 0; +} + +/** + * \brief Draws a string inside a LCD buffer, at the given coordinates. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param x X-coordinate of string top-left corner. + * \param y Y-coordinate of string top-left corner. + * \param pString String to display. + * \param color String color. + */ +void LCDD_DrawString( uint16_t* pCanvasBuffer, uint32_t x, uint32_t y, + const uint8_t *pString, uint32_t color ) +{ + uint32_t xorg = x; + + while ( *pString != 0 ) { + if ( *pString == '\n' ) { + y += gFont.height + 2; + x = xorg; + } else { + LCDD_DrawChar(pCanvasBuffer, x, y, *pString, color ); + x += gFont.width + 2; + } + pString++; + } +} + +/** + * \brief Returns the width & height in pixels that a string will occupy on the + * screen if drawn using LCDD_DrawString. + * + * \param pString String. + * \param pWidth Pointer for storing the string width (optional). + * \param pHeight Pointer for storing the string height (optional). + * + * \return String width in pixels. + */ +void LCDD_GetStringSize( const uint8_t *pString, uint32_t *pWidth, + uint32_t *pHeight ) +{ + uint32_t width = 0; + uint32_t height = gFont.height; + + while ( *pString != 0 ) { + if ( *pString == '\n' ) { + height += gFont.height + 2; + } else { + width += gFont.width + 2; + } + pString++; + } + + if ( width > 0 ) { + width -= 2; + } + + if ( pWidth != NULL ) { + *pWidth = width; + } + + if ( pHeight != NULL ) { + *pHeight = height; + } +} + + +/* + * \brief Performs a bit-block transfer of the color data corresponding to a + * rectangle of pixels from the given source context into destination context. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dst_x X-coordinate of source rectangle. + * \param dst_y Y-coordinate of source rectangle. + * \param dst_w Rectangle width in pixels of source rectangle. + * \param dst_h Rectangle height in pixels of source rectangle. + * \param src Pointer to the source device context. + * \param src_x X-coordinate of destination rectangle. + * \param src_y Y-coordinate of destination rectangle. + * \param src_w Rectangle width in pixels of destination rectangle. + * \param src_h Rectangle height in pixels of destination rectangle. + */ +void LCDD_BitBlt( uint16_t* pCanvasBuffer, uint32_t dst_x,uint32_t dst_y,uint32_t dst_w,uint32_t dst_h, + const LcdColor_t *src, + uint32_t src_x,uint32_t src_y,uint32_t src_w,uint32_t src_h) +{ + uint32_t row,col; + uint32_t src_row,src_col; + //assert(gpCanvasBuffer!=NULL); + + src_h = src_h; + if (ili9488_lcdMode == ILI9488_SPIMODE) { + sBGR *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = (sBGR *)((uint8_t*)pCanvasBuffer); + //it'd better change to a DMA transfer + SCB_CleanInvalidateDCache(); + for(src_row = src_y,row = dst_y; row < dst_h; row++,src_row++) { + for(src_col = src_x,col = dst_x; col < dst_w; col++,src_col++) { + p_buf[row * gwCanvasMaxWidth+col].r = src[src_row*src_w + src_col]&0xFF; + p_buf[row * gwCanvasMaxWidth+col].g = src[src_row*src_w + src_col]>>8; + p_buf[row * gwCanvasMaxWidth+col].b = src[src_row*src_w + src_col]>>16; + } + memory_barrier() + } + memory_barrier() + } else { + uint16_t *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = pCanvasBuffer; + //it'd better change to a DMA transfer + SCB_CleanInvalidateDCache(); + for(src_row = src_y,row = dst_y; row < dst_h; row++,src_row++) { + for(src_col = src_x, col = dst_x; col < dst_w; col++,src_col++) { + p_buf[row * gwCanvasMaxWidth+col] = src[src_row*src_w + src_col]; + } + } + memory_barrier() + } +} + + +/* + * \brief Performs a bit-block transfer of the color data corresponding to a + * rectangle of pixels from the given source context into destination context. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dst_x X-coordinate of source rectangle. + * \param dst_y Y-coordinate of source rectangle. + * \param dst_w Rectangle width in pixels of source rectangle. + * \param dst_h Rectangle height in pixels of source rectangle. + * \param src Pointer to the source device context. + * \param src_x X-coordinate of destination rectangle. + * \param src_y Y-coordinate of destination rectangle. + * \param src_w Rectangle width in pixels of destination rectangle. + * \param src_h Rectangle height in pixels of destination rectangle. + * \param alpha alpha value. + */ +void LCDD_BitBltAlphaBlend(uint16_t* pCanvasBuffer, + uint32_t dst_x, + uint32_t dst_y, + uint32_t dst_w, + uint32_t dst_h, + const LcdColor_t *src, + uint32_t src_x, + uint32_t src_y, + uint32_t src_w, + uint32_t src_h, + uint32_t alpha) +{ + uint32_t row,col; + uint32_t src_row,src_col; + uint32_t w,h; + uint32_t dst_row; + uint32_t r,g,b; + + if (ili9488_lcdMode == ILI9488_SPIMODE) { + sBGR *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = (sBGR *)((uint8_t*)pCanvasBuffer); + + //it'd better change to a DMA transfer + SCB_CleanInvalidateDCache(); + for(src_row = src_y,row = dst_y; row < dst_h; row++,src_row++) { + for(src_col = src_x,col = dst_x; col < dst_w; col++,src_col++) { + p_buf[row *dst_w +col].r = src[src_row*src_w + src_col]&0xFF; + p_buf[row *dst_w +col].g = src[src_row*src_w + src_col]>>8; + p_buf[row *dst_w +col].b = src[src_row*src_w + src_col]>>16; + } + } + memory_barrier() + } else { + uint16_t *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = pCanvasBuffer; + w = src_x + src_w; + h = src_y + src_h; + dst_row = dst_y; + p_buf += (dst_row*dst_w + dst_x); + src += src_y*w + src_x; + SCB_CleanInvalidateDCache(); + for(src_row = src_y; src_row < h; src_row++,dst_row++) { + for(src_col = src_x; src_col < w; src_col++){ + r = (p_buf[src_col] >> 11) * (255 - alpha) / 255 + + (src[src_col] >> 11) * alpha / 255; + if(r > 0x1F) r = 0x1F; + g = ((p_buf[src_col] >> 5) & 0x3F) * (255 - alpha) / 255 + + ((src[src_col] >> 5) & 0x3f) * alpha / 255; + if(g > 0x3F) g = 0x3F; + b = ((p_buf[src_col]) & 0x1F) * (255 - alpha) / 255 + + ((src[src_col]) & 0x1f) * alpha / 255; + if(b > 0x1F) b = 0x1F; + p_buf[src_col] = ((r & 0x1F) << 11)|((g & 0x3F) << 5)|( b & 0x1F); + } + p_buf += dst_w; + src += w; + } + memory_barrier() + } +} + +/* + * \brief Draw a raw image at given position on LCD. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dwX X-coordinate of image start. + * \param dwY Y-coordinate of image start. + * \param pImage Image buffer. + * \param width Image width. + * \param height Image height. + */ + void LCDD_DrawImage(uint16_t* pCanvasBuffer, uint32_t dwX, uint32_t dwY, + const LcdColor_t *pImage, uint32_t dwWidth, uint32_t dwHeight ) +{ + /* Determine the refresh window area */ + /* Horizontal and Vertical RAM Address Position (R50h, R51h, R52h, R53h) */ + //CheckBoxCoordinates(&dwX, &dwY, &dwWidth, &dwHeight); + + LCDD_BitBlt(pCanvasBuffer, dwX, dwY, dwWidth, dwHeight, + pImage, 0, 0, dwWidth - dwX, dwHeight - dwY); +} + +/** + * \brief Draw a pixel on LCD of given color. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param x X-coordinate of pixel. + * \param y Y-coordinate of pixel. + * \param color Pixel color. + */ +void LCDD_DrawPixel(uint16_t* pCanvasBuffer, uint32_t x, uint32_t y, uint32_t color ) +{ + //assert(gpCanvasBuffer!=NULL); + if (ili9488_lcdMode == ILI9488_SPIMODE) { + sBGR *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = (sBGR *)((uint8_t*)pCanvasBuffer); + p_buf += y * gwCanvasMaxWidth; + p_buf += x; + p_buf->b = color&0xFF; + p_buf->g = color>>8; + p_buf->r = color>>16; + p_buf++; + memory_barrier() + } else { + uint16_t *p_buf = gpCanvasBuffer; + if(pCanvasBuffer != NULL) p_buf = pCanvasBuffer; + p_buf += y * gwCanvasMaxWidth; + p_buf += x; + *p_buf = (uint16_t)color; + } +} + +/* + * \brief Draw a line on LCD, horizontal and vertical line are supported. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dwX1 X-coordinate of line start. + * \param dwY1 Y-coordinate of line start. + * \param dwX2 X-coordinate of line end. + * \param dwY2 Y-coordinate of line end. + * \param color Pixel color. + */ +void LCDD_DrawLine(uint16_t* pCanvasBuffer, uint32_t dwX1, uint32_t dwY1, + uint32_t dwX2, uint32_t dwY2 , uint32_t color ) +{ + if (( dwY1 == dwY2 ) || (dwX1 == dwX2)) { + //LCDD_DrawRectangleWithFill( dwX1, dwY1, dwX2, dwY2, color ); + LCDD_DrawStraightLine(pCanvasBuffer, dwX1, dwY1, dwX2, dwY2, color ); + } else { + LCDD_DrawLineBresenham(pCanvasBuffer, dwX1, dwY1, dwX2, dwY2 , color); + } +} + +void LCDD_DrawStraightLine(uint16_t* pCanvasBuffer, uint32_t dwX1, uint32_t dwY1, + uint32_t dwX2, uint32_t dwY2 , uint32_t color ) +{ + uint32_t x,y; + uint32_t tmp; + + if(dwY1 > dwY2) + { + tmp = dwY1; + dwY1 = dwY2; + dwY2 = tmp; + } + if(dwX1 > dwX2) + { + tmp = dwX1; + dwX1 = dwX2; + dwX2 = tmp; + } + for(y = dwY1; y<=dwY2; y++) + { + for(x=dwX1;x<=dwX2;x++) + { + LCDD_DrawPixel(pCanvasBuffer, x , y , color); + } + } +} + +/* + * \brief Draw a line on LCD, which is not horizontal or vertical. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dwX1 X-coordinate of line start. + * \param dwY1 Y-coordinate of line start. + * \param dwX2 X-coordinate of line end. + * \param dwY2 Y-coordinate of line end. + * \param color pixel color. + */ +uint32_t LCDD_DrawLineBresenham(uint16_t* pCanvasBuffer, uint32_t dwX1, + uint32_t dwY1, uint32_t dwX2, uint32_t dwY2 , uint32_t color) +{ + int dx, dy; + int i; + int xinc, yinc, cumul; + int x, y; + + x = dwX1; + y = dwY1; + dx = dwX2 - dwX1; + dy = dwY2 - dwY1; + + xinc = ( dx > 0 ) ? 1 : -1; + yinc = ( dy > 0 ) ? 1 : -1; + dx = ( dx > 0 ) ? dx : -dx; + dy = ( dy > 0 ) ? dy : -dy; + + LCDD_DrawPixel(pCanvasBuffer, x , y , color); + + if ( dx > dy ) { + cumul = dx / 2; + for ( i = 1; i <= dx; i++ ) { + x += xinc; + cumul += dy; + + if ( cumul >= dx ) { + cumul -= dx; + y += yinc; + } + LCDD_DrawPixel(pCanvasBuffer, x , y , color); + } + } else { + cumul = dy / 2; + for ( i = 1; i <= dy; i++ ) { + y += yinc; + cumul += dx; + + if ( cumul >= dy ) { + cumul -= dy; + x += xinc; + } + LCDD_DrawPixel(pCanvasBuffer, x , y , color); + } + } + + return 0; +} + +/* + * \brief Draws a rectangle on LCD, at the given coordinates. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param x X-coordinate of upper-left rectangle corner. + * \param y Y-coordinate of upper-left rectangle corner. + * \param width Rectangle width in pixels. + * \param height Rectangle height in pixels. + * \param color Rectangle color. + */ +void LCDD_DrawRectangle(uint16_t* pCanvasBuffer, uint32_t x, uint32_t y, + uint32_t width, uint32_t height, uint32_t color ) +{ + LCDD_DrawRectangleWithFill(pCanvasBuffer, x, y, width, 1, color); + LCDD_DrawRectangleWithFill(pCanvasBuffer, x, y, 1, height, color); + + LCDD_DrawRectangleWithFill(pCanvasBuffer, x + width , y, 1, height, color); + LCDD_DrawRectangleWithFill(pCanvasBuffer, x, y + height, width, 1, color); +} + +/* + * \brief Set buffer for pCanvas. + * + * \param pCanvasBuffer Pointer of external buffer. + * \param wBufferSize Size of buffer. + */ +void LCDD_SetCavasBuffer( void* pCanvasBuffer, uint32_t wBufferSize) +{ + if (ili9488_lcdMode == ILI9488_SPIMODE) { + gpCanvasBuffer = (sBGR*)pCanvasBuffer; + gwCanvasBufferSize = wBufferSize; + } else { + gpCanvasBuffer = (uint16_t*)pCanvasBuffer; + gwCanvasBufferSize = wBufferSize; + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_font.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_font.c new file mode 100644 index 000000000..a03913843 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_font.c @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of draw font on LCD. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Global variable describing the font being instantiated. */ +const Font gFont = {10, 14}; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Draws an ASCII character on LCD. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param x X-coordinate of character upper-left corner. + * \param y Y-coordinate of character upper-left corner. + * \param c Character to output. + * \param color Character color. + */ +extern void LCDD_DrawChar(uint16_t* pCanvasBuffer, uint32_t x, uint32_t y, + uint8_t c, uint32_t color ) +{ + uint32_t row, col; + + assert( (c >= 0x20) && (c <= 0x7F) ); + + for ( col = 0; col < 10; col++ ) { + for ( row = 0; row < 8; row++ ) { + if ( (pCharset10x14[((c - 0x20) * 20) + col * 2] >> (7 - row)) & 0x1){ + LCDD_DrawPixel(pCanvasBuffer, x+col, y+row, color ); + } + } + for (row = 0; row < 6; row++ ) { + if((pCharset10x14[((c - 0x20) * 20) + col * 2 + 1] + >> (7 - row)) & 0x1) { + LCDD_DrawPixel(pCanvasBuffer, x+col, y+row+8, color ); + } + } + } +} + +/** + * \brief Draws a string inside a LCD buffer, at the given coordinates. + * Line breaks will be honoured. + * + * \param pCanvasBuffer Pointer to dedicate canvas buffer. + * \param dwX X-coordinate of string top-left corner. + * \param dwY Y-coordinate of string top-left corner. + * \param pString String to display. + */ +extern void LCD_DrawString(uint16_t* pCanvasBuffer, uint32_t dwX, uint32_t dwY, + const uint8_t *pString, uint32_t color ) +{ + uint32_t dwXorg = dwX; + + while ( *pString != 0 ) { + if ( *pString == '\n' ) { + dwY += gFont.height + 2; + dwX = dwXorg; + } else { + LCDD_DrawChar(pCanvasBuffer, dwX, dwY, *pString, color ); + dwX += gFont.width + 2; + } + pString++; + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_fontsize.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_fontsize.c new file mode 100644 index 000000000..1643d059d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcd_fontsize.c @@ -0,0 +1,550 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Font 10x14 table definition. + * + */ + +#include "board.h" + +/** + * \var const uint8_t pCharset10x14; + * \brief Char set of font 10x14 + */ +const uint8_t pCharset10x14[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCC, + 0xFF, 0xCC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, + 0x00, 0x00, 0xF0, 0x00, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0C, 0xC0, 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, + 0x0C, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, + 0x0C, 0x60, 0x1E, 0x70, 0x3F, 0x30, 0x33, 0x30, 0xFF, 0xFC, + 0xFF, 0xFC, 0x33, 0x30, 0x33, 0xF0, 0x39, 0xE0, 0x18, 0xC0, + 0x60, 0x00, 0xF0, 0x0C, 0xF0, 0x3C, 0x60, 0xF0, 0x03, 0xC0, + 0x0F, 0x00, 0x3C, 0x18, 0xF0, 0x3C, 0xC0, 0x3C, 0x00, 0x18, + 0x3C, 0xF0, 0x7F, 0xF8, 0xC3, 0x1C, 0xC7, 0x8C, 0xCF, 0xCC, + 0xDC, 0xEC, 0x78, 0x78, 0x30, 0x30, 0x00, 0xFC, 0x00, 0xCC, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x00, 0xEC, 0x00, + 0xF8, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0F, 0xC0, 0x3F, 0xF0, 0x78, 0x78, + 0x60, 0x18, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0x60, 0x18, + 0x78, 0x78, 0x3F, 0xF0, 0x0F, 0xC0, 0x00, 0x00, 0x00, 0x00, + 0x0C, 0x60, 0x0E, 0xE0, 0x07, 0xC0, 0x03, 0x80, 0x3F, 0xF8, + 0x3F, 0xF8, 0x03, 0x80, 0x07, 0xC0, 0x0E, 0xE0, 0x0C, 0x60, + 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x3F, 0xF0, + 0x3F, 0xF0, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x00, 0x44, 0x00, 0xEC, 0x00, 0xF8, 0x00, 0x70, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x00, 0x18, 0x00, 0x3C, 0x00, 0x3C, 0x00, 0x18, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x0C, 0x00, 0x3C, 0x00, 0xF0, 0x03, 0xC0, + 0x0F, 0x00, 0x3C, 0x00, 0xF0, 0x00, 0xC0, 0x00, 0x00, 0x00, + 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0xFC, 0xC1, 0xCC, 0xC3, 0x8C, + 0xC7, 0x0C, 0xCE, 0x0C, 0xFC, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, + 0x00, 0x00, 0x00, 0x00, 0x30, 0x0C, 0x70, 0x0C, 0xFF, 0xFC, + 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x0C, 0x70, 0x1C, 0xE0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, + 0xC1, 0xCC, 0xC3, 0x8C, 0xE7, 0x0C, 0x7E, 0x0C, 0x3C, 0x0C, + 0x30, 0x30, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x7F, 0xF8, 0x3C, 0xF0, + 0x03, 0xC0, 0x07, 0xC0, 0x0E, 0xC0, 0x1C, 0xC0, 0x38, 0xC0, + 0x70, 0xC0, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xC0, 0x00, 0xC0, + 0xFC, 0x30, 0xFC, 0x38, 0xCC, 0x1C, 0xCC, 0x0C, 0xCC, 0x0C, + 0xCC, 0x0C, 0xCC, 0x0C, 0xCE, 0x1C, 0xC7, 0xF8, 0xC3, 0xF0, + 0x3F, 0xF0, 0x7F, 0xF8, 0xE3, 0x1C, 0xC3, 0x0C, 0xC3, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x9C, 0x71, 0xF8, 0x30, 0xF0, + 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC3, 0xFC, + 0xC7, 0xFC, 0xCE, 0x00, 0xDC, 0x00, 0xF8, 0x00, 0xF0, 0x00, + 0x3C, 0xF0, 0x7F, 0xF8, 0xE7, 0x9C, 0xC3, 0x0C, 0xC3, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0, + 0x3C, 0x00, 0x7E, 0x00, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x1C, + 0xC3, 0x38, 0xC3, 0x70, 0xE7, 0xE0, 0x7F, 0xC0, 0x3F, 0x80, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x60, 0x3C, 0xF0, + 0x3C, 0xF0, 0x18, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x44, 0x3C, 0xEC, + 0x3C, 0xF8, 0x18, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, + 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, 0x00, 0x00, + 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, + 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, + 0x00, 0x00, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x38, 0x70, + 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, + 0x30, 0x00, 0x70, 0x00, 0xE0, 0x00, 0xC0, 0x00, 0xC1, 0xEC, + 0xC3, 0xEC, 0xC3, 0x00, 0xE6, 0x00, 0x7E, 0x00, 0x3C, 0x00, + 0x30, 0xF0, 0x71, 0xF8, 0xE3, 0x9C, 0xC3, 0x0C, 0xC3, 0xFC, + 0xC3, 0xFC, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, + 0x3F, 0xFC, 0x7F, 0xFC, 0xE0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, + 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xC0, 0x7F, 0xFC, 0x3F, 0xFC, + 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xE7, 0x9C, 0x7F, 0xF8, 0x3C, 0xF0, + 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x70, 0x38, 0x30, 0x30, + 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, + 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, + 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, 0xC0, 0x00, 0xC0, 0x00, + 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xE3, 0x1C, 0x73, 0xF8, 0x33, 0xF0, + 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC, + 0xFF, 0xFC, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x30, 0x00, 0x38, 0xC0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xC0, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, 0xC0, 0x00, 0xC0, 0x00, + 0xFF, 0xFC, 0xFF, 0xFC, 0x07, 0x80, 0x07, 0x80, 0x0F, 0xC0, + 0x1C, 0xE0, 0x38, 0x70, 0x70, 0x38, 0xE0, 0x1C, 0xC0, 0x0C, + 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, + 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, + 0xFF, 0xFC, 0xFF, 0xFC, 0x70, 0x00, 0x38, 0x00, 0x1F, 0x00, + 0x1F, 0x00, 0x38, 0x00, 0x70, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, + 0xFF, 0xFC, 0xFF, 0xFC, 0x1C, 0x00, 0x0E, 0x00, 0x07, 0x00, + 0x03, 0x80, 0x01, 0xC0, 0x00, 0xE0, 0xFF, 0xFC, 0xFF, 0xFC, + 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, 0x7F, 0xF8, 0x3F, 0xF0, + 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x00, 0xC3, 0x00, + 0xC3, 0x00, 0xC3, 0x00, 0xE7, 0x00, 0x7E, 0x00, 0x3C, 0x00, + 0x3F, 0xF0, 0x7F, 0xF8, 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0xCC, + 0xC0, 0xEC, 0xC0, 0x7C, 0xE0, 0x38, 0x7F, 0xFC, 0x3F, 0xEC, + 0xFF, 0xFC, 0xFF, 0xFC, 0xC3, 0x00, 0xC3, 0x80, 0xC3, 0x80, + 0xC3, 0xC0, 0xC3, 0xC0, 0xE7, 0x70, 0x7E, 0x3C, 0x3C, 0x1C, + 0x3C, 0x18, 0x7E, 0x1C, 0xE7, 0x0C, 0xC3, 0x0C, 0xC3, 0x0C, + 0xC3, 0x0C, 0xC3, 0x0C, 0xC3, 0x9C, 0xE1, 0xF8, 0x60, 0xF0, + 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xFF, 0xFC, + 0xFF, 0xFC, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, + 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C, + 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, + 0xFF, 0xC0, 0xFF, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, + 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0xFF, 0xE0, 0xFF, 0xC0, + 0xFF, 0xF0, 0xFF, 0xF8, 0x00, 0x1C, 0x00, 0x3C, 0x00, 0xF8, + 0x00, 0xF8, 0x00, 0x3C, 0x00, 0x1C, 0xFF, 0xF8, 0xFF, 0xF0, + 0xF0, 0x3C, 0xF8, 0x7C, 0x1C, 0xE0, 0x0F, 0xC0, 0x07, 0x80, + 0x07, 0x80, 0x0F, 0xC0, 0x1C, 0xE0, 0xF8, 0x7C, 0xF0, 0x3C, + 0xFC, 0x00, 0xFE, 0x00, 0x07, 0x00, 0x03, 0x80, 0x01, 0xFC, + 0x01, 0xFC, 0x03, 0x80, 0x07, 0x00, 0xFE, 0x00, 0xFC, 0x00, + 0xC0, 0x3C, 0xC0, 0x7C, 0xC0, 0xEC, 0xC1, 0xCC, 0xC3, 0x8C, + 0xC7, 0x0C, 0xCE, 0x0C, 0xDC, 0x0C, 0xF8, 0x0C, 0xF0, 0x0C, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0xC0, 0x0C, + 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x30, 0x00, 0x30, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0x30, 0x00, 0x30, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, + 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0C, 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x00, 0xE0, 0x00, + 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, 0x00, + 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, + 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x0C, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x00, 0xE0, 0x00, 0x70, 0x00, + 0x38, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x30, 0x06, 0x78, 0x0E, 0xFC, 0x0C, 0xCC, 0x0C, 0xCC, + 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xCC, 0x07, 0xFC, 0x03, 0xF8, + 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, + 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x9C, 0x01, 0xF8, 0x00, 0xF0, + 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0x30, + 0x00, 0xF0, 0x01, 0xF8, 0x03, 0x9C, 0x03, 0x0C, 0x03, 0x0C, + 0x03, 0x0C, 0x03, 0x0C, 0x03, 0x0C, 0xFF, 0xFC, 0xFF, 0xFC, + 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0xDC, 0x0C, 0xCC, 0x0C, 0xCC, + 0x0C, 0xCC, 0x0C, 0xCC, 0x0E, 0xDC, 0x07, 0xD8, 0x03, 0x90, + 0x00, 0x00, 0x03, 0x00, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x00, + 0xE3, 0x00, 0x70, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC, + 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xDC, 0x0F, 0xF8, 0x07, 0xF0, + 0xFF, 0xFC, 0xFF, 0xFC, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00, + 0x03, 0x00, 0x03, 0x80, 0x01, 0xFC, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1B, 0xFC, + 0x1B, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x30, 0x00, 0x38, 0x00, 0x1C, 0x00, 0x0C, + 0x00, 0x0C, 0x00, 0x1C, 0xCF, 0xF8, 0xCF, 0xF0, 0x00, 0x00, + 0x00, 0x00, 0xFF, 0xFC, 0xFF, 0xFC, 0x00, 0xE0, 0x01, 0xE0, + 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xFF, 0xFC, + 0xFF, 0xFC, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xFC, 0x0F, 0xFC, 0x0E, 0x00, 0x07, 0x00, 0x03, 0xC0, + 0x03, 0xC0, 0x07, 0x00, 0x0E, 0x00, 0x0F, 0xFC, 0x0F, 0xFC, + 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x00, 0x07, 0x00, 0x0E, 0x00, + 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0xFC, 0x03, 0xFC, + 0x03, 0xF0, 0x07, 0xF8, 0x0E, 0x1C, 0x0C, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0C, 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0xF8, 0x03, 0xF0, + 0x0F, 0xFC, 0x0F, 0xFC, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, + 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xC0, 0x07, 0x80, 0x03, 0x00, + 0x03, 0x00, 0x07, 0x80, 0x0F, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, + 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0F, 0xFC, 0x0F, 0xFC, + 0x0F, 0xFC, 0x0F, 0xFC, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, + 0x0C, 0x00, 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x00, 0x03, 0x00, + 0x03, 0x18, 0x07, 0x9C, 0x0F, 0xCC, 0x0C, 0xCC, 0x0C, 0xCC, + 0x0C, 0xCC, 0x0C, 0xCC, 0x0C, 0xFC, 0x0E, 0x78, 0x06, 0x30, + 0x00, 0x00, 0x0C, 0x00, 0x0C, 0x00, 0xFF, 0xF0, 0xFF, 0xF8, + 0x0C, 0x1C, 0x0C, 0x1C, 0x0C, 0x38, 0x0C, 0x30, 0x00, 0x00, + 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x0C, 0x00, 0x0C, + 0x00, 0x0C, 0x00, 0x0C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0, + 0x0F, 0xC0, 0x0F, 0xE0, 0x00, 0x70, 0x00, 0x38, 0x00, 0x1C, + 0x00, 0x1C, 0x00, 0x38, 0x00, 0x70, 0x0F, 0xE0, 0x0F, 0xC0, + 0x0F, 0xF0, 0x0F, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x00, 0xF8, + 0x00, 0xF8, 0x00, 0x1C, 0x00, 0x1C, 0x0F, 0xF8, 0x0F, 0xF0, + 0x0C, 0x0C, 0x0E, 0x1C, 0x07, 0x38, 0x03, 0xF0, 0x01, 0xE0, + 0x01, 0xE0, 0x03, 0xF0, 0x07, 0x38, 0x0E, 0x1C, 0x0C, 0x0C, + 0x0C, 0x00, 0x0E, 0x00, 0x07, 0x0C, 0x03, 0x9C, 0x01, 0xF8, + 0x01, 0xF0, 0x03, 0x80, 0x07, 0x00, 0x0E, 0x00, 0x0C, 0x00, + 0x0C, 0x0C, 0x0C, 0x1C, 0x0C, 0x3C, 0x0C, 0x7C, 0x0C, 0xEC, + 0x0D, 0xCC, 0x0F, 0x8C, 0x0F, 0x0C, 0x0E, 0x0C, 0x0C, 0x0C, + 0x00, 0x00, 0x03, 0x00, 0x07, 0x80, 0x3F, 0xF0, 0x7C, 0xF8, + 0xE0, 0x1C, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0x00, 0x00, + 0x03, 0x0C, 0x03, 0x0C, 0x3F, 0xFC, 0x7F, 0xFC, 0xE3, 0x0C, + 0xC3, 0x0C, 0xC0, 0x0C, 0xE0, 0x0C, 0x70, 0x0C, 0x30, 0x0C, + 0x00, 0x00, 0xC0, 0x0C, 0xC0, 0x0C, 0xC0, 0x0C, 0xE0, 0x1C, + 0x7C, 0xF8, 0x3F, 0xF0, 0x07, 0x80, 0x03, 0x00, 0x00, 0x00, + 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, + 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, 0xC0, 0x00, + 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, + 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC, 0xFF, 0xFC +} ; + +/** + * \var const uint8_t FONT6x8; + * \brief Char set of font 6x8 + */ +const uint8_t FONT6x8[97][8] = { + {0x06,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20 + {0x20,0x20,0x20,0x20,0x20,0x00,0x20,0x00}, // ! + {0x50,0x50,0x50,0x00,0x00,0x00,0x00,0x00}, // " + {0x50,0x50,0xF8,0x50,0xF8,0x50,0x50,0x00}, // # + {0x20,0x78,0xA0,0x70,0x28,0xF0,0x20,0x00}, // $ + {0xC0,0xC8,0x10,0x20,0x40,0x98,0x18,0x00}, // % + {0x40,0xA0,0xA0,0x40,0xA8,0x90,0x68,0x00}, // & + {0x30,0x30,0x20,0x40,0x00,0x00,0x00,0x00}, // ' + {0x10,0x20,0x40,0x40,0x40,0x20,0x10,0x00}, // ( + {0x40,0x20,0x10,0x10,0x10,0x20,0x40,0x00}, // ) + {0x00,0x20,0xA8,0x70,0x70,0xA8,0x20,0x00}, // * + {0x00,0x20,0x20,0xF8,0x20,0x20,0x00,0x00}, // + + {0x00,0x00,0x00,0x00,0x30,0x30,0x20,0x40}, // , + {0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00}, // - + {0x00,0x00,0x00,0x00,0x00,0x30,0x30,0x00}, // . + {0x00,0x08,0x10,0x20,0x40,0x80,0x00,0x00}, // / (forward slash) + {0x70,0x88,0x88,0xA8,0x88,0x88,0x70,0x00}, // 0 0x30 + {0x20,0x60,0x20,0x20,0x20,0x20,0x70,0x00}, // 1 + {0x70,0x88,0x08,0x70,0x80,0x80,0xF8,0x00}, // 2 + {0xF8,0x08,0x10,0x30,0x08,0x88,0x70,0x00}, // 3 + {0x10,0x30,0x50,0x90,0xF8,0x10,0x10,0x00}, // 4 + {0xF8,0x80,0xF0,0x08,0x08,0x88,0x70,0x00}, // 5 + {0x38,0x40,0x80,0xF0,0x88,0x88,0x70,0x00}, // 6 + {0xF8,0x08,0x08,0x10,0x20,0x40,0x80,0x00}, // 7 + {0x70,0x88,0x88,0x70,0x88,0x88,0x70,0x00}, // 8 + {0x70,0x88,0x88,0x78,0x08,0x10,0xE0,0x00}, // 9 + {0x00,0x00,0x20,0x00,0x20,0x00,0x00,0x00}, // : + {0x00,0x00,0x20,0x00,0x20,0x20,0x40,0x00}, // ; + {0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x00}, // < + {0x00,0x00,0xF8,0x00,0xF8,0x00,0x00,0x00}, // = + {0x40,0x20,0x10,0x08,0x10,0x20,0x40,0x00}, // > + {0x70,0x88,0x08,0x30,0x20,0x00,0x20,0x00}, // ? + {0x70,0x88,0xA8,0xB8,0xB0,0x80,0x78,0x00}, // @ 0x40 + {0x20,0x50,0x88,0x88,0xF8,0x88,0x88,0x00}, // A + {0xF0,0x88,0x88,0xF0,0x88,0x88,0xF0,0x00}, // B + {0x70,0x88,0x80,0x80,0x80,0x88,0x70,0x00}, // C + {0xF0,0x88,0x88,0x88,0x88,0x88,0xF0,0x00}, // D + {0xF8,0x80,0x80,0xF0,0x80,0x80,0xF8,0x00}, // E + {0xF8,0x80,0x80,0xF0,0x80,0x80,0x80,0x00}, // F + {0x78,0x88,0x80,0x80,0x98,0x88,0x78,0x00}, // G + {0x88,0x88,0x88,0xF8,0x88,0x88,0x88,0x00}, // H + {0x70,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // I + {0x38,0x10,0x10,0x10,0x10,0x90,0x60,0x00}, // J + {0x88,0x90,0xA0,0xC0,0xA0,0x90,0x88,0x00}, // K + {0x80,0x80,0x80,0x80,0x80,0x80,0xF8,0x00}, // L + {0x88,0xD8,0xA8,0xA8,0xA8,0x88,0x88,0x00}, // M + {0x88,0x88,0xC8,0xA8,0x98,0x88,0x88,0x00}, // N + {0x70,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // O + {0xF0,0x88,0x88,0xF0,0x80,0x80,0x80,0x00}, // P 0x50 + {0x70,0x88,0x88,0x88,0xA8,0x90,0x68,0x00}, // Q + {0xF0,0x88,0x88,0xF0,0xA0,0x90,0x88,0x00}, // R + {0x70,0x88,0x80,0x70,0x08,0x88,0x70,0x00}, // S + {0xF8,0xA8,0x20,0x20,0x20,0x20,0x20,0x00}, // T + {0x88,0x88,0x88,0x88,0x88,0x88,0x70,0x00}, // U + {0x88,0x88,0x88,0x88,0x88,0x50,0x20,0x00}, // V + {0x88,0x88,0x88,0xA8,0xA8,0xA8,0x50,0x00}, // W + {0x88,0x88,0x50,0x20,0x50,0x88,0x88,0x00}, // X + {0x88,0x88,0x50,0x20,0x20,0x20,0x20,0x00}, // Y + {0xF8,0x08,0x10,0x70,0x40,0x80,0xF8,0x00}, // Z + {0x78,0x40,0x40,0x40,0x40,0x40,0x78,0x00}, // [ + {0x00,0x80,0x40,0x20,0x10,0x08,0x00,0x00}, // \ (back slash) + {0x78,0x08,0x08,0x08,0x08,0x08,0x78,0x00}, // ] + {0x20,0x50,0x88,0x00,0x00,0x00,0x00,0x00}, // ^ + {0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x00}, // _ + {0x60,0x60,0x20,0x10,0x00,0x00,0x00,0x00}, // ` 0x60 + {0x00,0x00,0x60,0x10,0x70,0x90,0x78,0x00}, // a + {0x80,0x80,0xB0,0xC8,0x88,0xC8,0xB0,0x00}, // b + {0x00,0x00,0x70,0x88,0x80,0x88,0x70,0x00}, // c + {0x08,0x08,0x68,0x98,0x88,0x98,0x68,0x00}, // d + {0x00,0x00,0x70,0x88,0xF8,0x80,0x70,0x00}, // e + {0x10,0x28,0x20,0x70,0x20,0x20,0x20,0x00}, // f + {0x00,0x00,0x70,0x98,0x98,0x68,0x08,0x70}, // g + {0x80,0x80,0xB0,0xC8,0x88,0x88,0x88,0x00}, // h + {0x20,0x00,0x60,0x20,0x20,0x20,0x70,0x00}, // i + {0x10,0x00,0x10,0x10,0x10,0x90,0x60,0x00}, // j + {0x80,0x80,0x90,0xA0,0xC0,0xA0,0x90,0x00}, // k + {0x60,0x20,0x20,0x20,0x20,0x20,0x70,0x00}, // l + {0x00,0x00,0xD0,0xA8,0xA8,0xA8,0xA8,0x00}, // m + {0x00,0x00,0xB0,0xC8,0x88,0x88,0x88,0x00}, // n + {0x00,0x00,0x70,0x88,0x88,0x88,0x70,0x00}, // o + {0x00,0x00,0xB0,0xC8,0xC8,0xB0,0x80,0x80}, // p 0x70 + {0x00,0x00,0x68,0x98,0x98,0x68,0x08,0x08}, // q + {0x00,0x00,0xB0,0xC8,0x80,0x80,0x80,0x00}, // r + {0x00,0x00,0x78,0x80,0x70,0x08,0xF0,0x00}, // s + {0x20,0x20,0xF8,0x20,0x20,0x28,0x10,0x00}, // t + {0x00,0x00,0x88,0x88,0x88,0x98,0x68,0x00}, // u + {0x00,0x00,0x88,0x88,0x88,0x50,0x20,0x00}, // v + {0x00,0x00,0x88,0x88,0xA8,0xA8,0x50,0x00}, // w + {0x00,0x00,0x88,0x50,0x20,0x50,0x88,0x00}, // x + {0x00,0x00,0x88,0x88,0x78,0x08,0x88,0x70}, // y + {0x00,0x00,0xF8,0x10,0x20,0x40,0xF8,0x00}, // z + {0x10,0x20,0x20,0x40,0x20,0x20,0x10,0x00}, // { + {0x20,0x20,0x20,0x00,0x20,0x20,0x20,0x00}, // | + {0x40,0x20,0x20,0x10,0x20,0x20,0x40,0x00}, // } + {0x40,0xA8,0x10,0x00,0x00,0x00,0x00,0x00}, // ~ + {0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00} // DEL +}; + +/** + * \var const uint8_t FONT8x8; + * \brief Char set of font 8x8 + */ + +const uint8_t FONT8x8[97][8] = { + {0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20 + {0x30,0x78,0x78,0x30,0x30,0x00,0x30,0x00}, // ! + {0x6C,0x6C,0x6C,0x00,0x00,0x00,0x00,0x00}, // " + {0x6C,0x6C,0xFE,0x6C,0xFE,0x6C,0x6C,0x00}, // # + {0x18,0x3E,0x60,0x3C,0x06,0x7C,0x18,0x00}, // $ + {0x00,0x63,0x66,0x0C,0x18,0x33,0x63,0x00}, // % + {0x1C,0x36,0x1C,0x3B,0x6E,0x66,0x3B,0x00}, // & + {0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00}, // ' + {0x0C,0x18,0x30,0x30,0x30,0x18,0x0C,0x00}, // ( + {0x30,0x18,0x0C,0x0C,0x0C,0x18,0x30,0x00}, // ) + {0x00,0x66,0x3C,0xFF,0x3C,0x66,0x00,0x00}, // * + {0x00,0x30,0x30,0xFC,0x30,0x30,0x00,0x00}, // + + {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x30}, // , + {0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00}, // - + {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00}, // . + {0x03,0x06,0x0C,0x18,0x30,0x60,0x40,0x00}, // / (forward slash) + {0x3E,0x63,0x63,0x6B,0x63,0x63,0x3E,0x00}, // 0 0x30 + {0x18,0x38,0x58,0x18,0x18,0x18,0x7E,0x00}, // 1 + {0x3C,0x66,0x06,0x1C,0x30,0x66,0x7E,0x00}, // 2 + {0x3C,0x66,0x06,0x1C,0x06,0x66,0x3C,0x00}, // 3 + {0x0E,0x1E,0x36,0x66,0x7F,0x06,0x0F,0x00}, // 4 + {0x7E,0x60,0x7C,0x06,0x06,0x66,0x3C,0x00}, // 5 + {0x1C,0x30,0x60,0x7C,0x66,0x66,0x3C,0x00}, // 6 + {0x7E,0x66,0x06,0x0C,0x18,0x18,0x18,0x00}, // 7 + {0x3C,0x66,0x66,0x3C,0x66,0x66,0x3C,0x00}, // 8 + {0x3C,0x66,0x66,0x3E,0x06,0x0C,0x38,0x00}, // 9 + {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x00}, // : + {0x00,0x18,0x18,0x00,0x00,0x18,0x18,0x30}, // ; + {0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x00}, // < + {0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00}, // = + {0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x00}, // > + {0x3C,0x66,0x06,0x0C,0x18,0x00,0x18,0x00}, // ? + {0x3E,0x63,0x6F,0x69,0x6F,0x60,0x3E,0x00}, // @ 0x40 + {0x18,0x3C,0x66,0x66,0x7E,0x66,0x66,0x00}, // A + {0x7E,0x33,0x33,0x3E,0x33,0x33,0x7E,0x00}, // B + {0x1E,0x33,0x60,0x60,0x60,0x33,0x1E,0x00}, // C + {0x7C,0x36,0x33,0x33,0x33,0x36,0x7C,0x00}, // D + {0x7F,0x31,0x34,0x3C,0x34,0x31,0x7F,0x00}, // E + {0x7F,0x31,0x34,0x3C,0x34,0x30,0x78,0x00}, // F + {0x1E,0x33,0x60,0x60,0x67,0x33,0x1F,0x00}, // G + {0x66,0x66,0x66,0x7E,0x66,0x66,0x66,0x00}, // H + {0x3C,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // I + {0x0F,0x06,0x06,0x06,0x66,0x66,0x3C,0x00}, // J + {0x73,0x33,0x36,0x3C,0x36,0x33,0x73,0x00}, // K + {0x78,0x30,0x30,0x30,0x31,0x33,0x7F,0x00}, // L + {0x63,0x77,0x7F,0x7F,0x6B,0x63,0x63,0x00}, // M + {0x63,0x73,0x7B,0x6F,0x67,0x63,0x63,0x00}, // N + {0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00}, // O + {0x7E,0x33,0x33,0x3E,0x30,0x30,0x78,0x00}, // P 0x50 + {0x3C,0x66,0x66,0x66,0x6E,0x3C,0x0E,0x00}, // Q + {0x7E,0x33,0x33,0x3E,0x36,0x33,0x73,0x00}, // R + {0x3C,0x66,0x30,0x18,0x0C,0x66,0x3C,0x00}, // S + {0x7E,0x5A,0x18,0x18,0x18,0x18,0x3C,0x00}, // T + {0x66,0x66,0x66,0x66,0x66,0x66,0x7E,0x00}, // U + {0x66,0x66,0x66,0x66,0x66,0x3C,0x18,0x00}, // V + {0x63,0x63,0x63,0x6B,0x7F,0x77,0x63,0x00}, // W + {0x63,0x63,0x36,0x1C,0x1C,0x36,0x63,0x00}, // X + {0x66,0x66,0x66,0x3C,0x18,0x18,0x3C,0x00}, // Y + {0x7F,0x63,0x46,0x0C,0x19,0x33,0x7F,0x00}, // Z + {0x3C,0x30,0x30,0x30,0x30,0x30,0x3C,0x00}, // [ + {0x60,0x30,0x18,0x0C,0x06,0x03,0x01,0x00}, // \ (back slash) + {0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00}, // ] + {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // ^ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF}, // _ + {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00}, // ` 0x60 + {0x00,0x00,0x3C,0x06,0x3E,0x66,0x3B,0x00}, // a + {0x70,0x30,0x3E,0x33,0x33,0x33,0x6E,0x00}, // b + {0x00,0x00,0x3C,0x66,0x60,0x66,0x3C,0x00}, // c + {0x0E,0x06,0x3E,0x66,0x66,0x66,0x3B,0x00}, // d + {0x00,0x00,0x3C,0x66,0x7E,0x60,0x3C,0x00}, // e + {0x1C,0x36,0x30,0x78,0x30,0x30,0x78,0x00}, // f + {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x7C}, // g + {0x70,0x30,0x36,0x3B,0x33,0x33,0x73,0x00}, // h + {0x18,0x00,0x38,0x18,0x18,0x18,0x3C,0x00}, // i + {0x06,0x00,0x06,0x06,0x06,0x66,0x66,0x3C}, // j + {0x70,0x30,0x33,0x36,0x3C,0x36,0x73,0x00}, // k + {0x38,0x18,0x18,0x18,0x18,0x18,0x3C,0x00}, // l + {0x00,0x00,0x66,0x7F,0x7F,0x6B,0x63,0x00}, // m + {0x00,0x00,0x7C,0x66,0x66,0x66,0x66,0x00}, // n + {0x00,0x00,0x3C,0x66,0x66,0x66,0x3C,0x00}, // o + {0x00,0x00,0x6E,0x33,0x33,0x3E,0x30,0x78}, // p 0x70 + {0x00,0x00,0x3B,0x66,0x66,0x3E,0x06,0x0F}, // q + {0x00,0x00,0x6E,0x3B,0x33,0x30,0x78,0x00}, // r + {0x00,0x00,0x3E,0x60,0x3C,0x06,0x7C,0x00}, // s + {0x08,0x18,0x3E,0x18,0x18,0x1A,0x0C,0x00}, // t + {0x00,0x00,0x66,0x66,0x66,0x66,0x3B,0x00}, // u + {0x00,0x00,0x66,0x66,0x66,0x3C,0x18,0x00}, // v + {0x00,0x00,0x63,0x6B,0x7F,0x7F,0x36,0x00}, // w + {0x00,0x00,0x63,0x36,0x1C,0x36,0x63,0x00}, // x + {0x00,0x00,0x66,0x66,0x66,0x3E,0x06,0x7C}, // y + {0x00,0x00,0x7E,0x4C,0x18,0x32,0x7E,0x00}, // z + {0x0E,0x18,0x18,0x70,0x18,0x18,0x0E,0x00}, // { + {0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x0C,0x00}, // | + {0x70,0x18,0x18,0x0E,0x18,0x18,0x70,0x00}, // } + {0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00}, // ~ + {0x1C,0x36,0x36,0x1C,0x00,0x00,0x00,0x00}// DEL +}; + +/** + * \var const uint8_t FONT8x16; + * \brief Char set of font 8x16 + */ + +const uint8_t FONT8x16[97][16] = { + {0x08,0x10,0x10,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // columns, rows, num_bytes_per_char + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // space 0x20 + {0x00,0x00,0x18,0x3C,0x3C,0x3C,0x18,0x18,0x18,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // ! + {0x00,0x63,0x63,0x63,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // " + {0x00,0x00,0x00,0x36,0x36,0x7F,0x36,0x36,0x36,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // # + {0x0C,0x0C,0x3E,0x63,0x61,0x60,0x3E,0x03,0x03,0x43,0x63,0x3E,0x0C,0x0C,0x00,0x00}, // $ + {0x00,0x00,0x00,0x00,0x00,0x61,0x63,0x06,0x0C,0x18,0x33,0x63,0x00,0x00,0x00,0x00}, // % + {0x00,0x00,0x00,0x1C,0x36,0x36,0x1C,0x3B,0x6E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // & + {0x00,0x30,0x30,0x30,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ' + {0x00,0x00,0x0C,0x18,0x18,0x30,0x30,0x30,0x30,0x18,0x18,0x0C,0x00,0x00,0x00,0x00}, // ( + {0x00,0x00,0x18,0x0C,0x0C,0x06,0x06,0x06,0x06,0x0C,0x0C,0x18,0x00,0x00,0x00,0x00}, // ) + {0x00,0x00,0x00,0x00,0x42,0x66,0x3C,0xFF,0x3C,0x66,0x42,0x00,0x00,0x00,0x00,0x00}, // * + {0x00,0x00,0x00,0x00,0x18,0x18,0x18,0xFF,0x18,0x18,0x18,0x00,0x00,0x00,0x00,0x00}, // + + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // , + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // - + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // . + {0x00,0x00,0x01,0x03,0x07,0x0E,0x1C,0x38,0x70,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00}, // / (forward slash) + {0x00,0x00,0x3E,0x63,0x63,0x63,0x6B,0x6B,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 0 0x30 + {0x00,0x00,0x0C,0x1C,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3F,0x00,0x00,0x00,0x00}, // 1 + {0x00,0x00,0x3E,0x63,0x03,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // 2 + {0x00,0x00,0x3E,0x63,0x03,0x03,0x1E,0x03,0x03,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // 3 + {0x00,0x00,0x06,0x0E,0x1E,0x36,0x66,0x66,0x7F,0x06,0x06,0x0F,0x00,0x00,0x00,0x00}, // 4 + {0x00,0x00,0x7F,0x60,0x60,0x60,0x7E,0x03,0x03,0x63,0x73,0x3E,0x00,0x00,0x00,0x00}, // 5 + {0x00,0x00,0x1C,0x30,0x60,0x60,0x7E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 6 + {0x00,0x00,0x7F,0x63,0x03,0x06,0x06,0x0C,0x0C,0x18,0x18,0x18,0x00,0x00,0x00,0x00}, // 7 + {0x00,0x00,0x3E,0x63,0x63,0x63,0x3E,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // 8 + {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x3F,0x03,0x03,0x06,0x3C,0x00,0x00,0x00,0x00}, // 9 + {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00}, // : + {0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x18,0x18,0x18,0x30,0x00,0x00}, // ; + {0x00,0x00,0x00,0x06,0x0C,0x18,0x30,0x60,0x30,0x18,0x0C,0x06,0x00,0x00,0x00,0x00}, // < + {0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00}, // = + {0x00,0x00,0x00,0x60,0x30,0x18,0x0C,0x06,0x0C,0x18,0x30,0x60,0x00,0x00,0x00,0x00}, // > + {0x00,0x00,0x3E,0x63,0x63,0x06,0x0C,0x0C,0x0C,0x00,0x0C,0x0C,0x00,0x00,0x00,0x00}, // ? + {0x00,0x00,0x3E,0x63,0x63,0x6F,0x6B,0x6B,0x6E,0x60,0x60,0x3E,0x00,0x00,0x00,0x00}, // @ 0x40 + {0x00,0x00,0x08,0x1C,0x36,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // A + {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x33,0x33,0x33,0x33,0x7E,0x00,0x00,0x00,0x00}, // B + {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x60,0x60,0x61,0x33,0x1E,0x00,0x00,0x00,0x00}, // C + {0x00,0x00,0x7C,0x36,0x33,0x33,0x33,0x33,0x33,0x33,0x36,0x7C,0x00,0x00,0x00,0x00}, // D + {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // E + {0x00,0x00,0x7F,0x33,0x31,0x34,0x3C,0x34,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // F + {0x00,0x00,0x1E,0x33,0x61,0x60,0x60,0x6F,0x63,0x63,0x37,0x1D,0x00,0x00,0x00,0x00}, // G + {0x00,0x00,0x63,0x63,0x63,0x63,0x7F,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // H + {0x00,0x00,0x3C,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // I + {0x00,0x00,0x0F,0x06,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00,0x00,0x00}, // J + {0x00,0x00,0x73,0x33,0x36,0x36,0x3C,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // K + {0x00,0x00,0x78,0x30,0x30,0x30,0x30,0x30,0x30,0x31,0x33,0x7F,0x00,0x00,0x00,0x00}, // L + {0x00,0x00,0x63,0x77,0x7F,0x6B,0x63,0x63,0x63,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // M + {0x00,0x00,0x63,0x63,0x73,0x7B,0x7F,0x6F,0x67,0x63,0x63,0x63,0x00,0x00,0x00,0x00}, // N + {0x00,0x00,0x1C,0x36,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x00,0x00,0x00,0x00}, // O + {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // P 0x50 + {0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x63,0x6B,0x6F,0x3E,0x06,0x07,0x00,0x00}, // Q + {0x00,0x00,0x7E,0x33,0x33,0x33,0x3E,0x36,0x36,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // R + {0x00,0x00,0x3E,0x63,0x63,0x30,0x1C,0x06,0x03,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // S + {0x00,0x00,0xFF,0xDB,0x99,0x18,0x18,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // T + {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // U + {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x63,0x63,0x36,0x1C,0x08,0x00,0x00,0x00,0x00}, // V + {0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x36,0x00,0x00,0x00,0x00}, // W + {0x00,0x00,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x3C,0x66,0xC3,0xC3,0x00,0x00,0x00,0x00}, // X + {0x00,0x00,0xC3,0xC3,0xC3,0x66,0x3C,0x18,0x18,0x18,0x18,0x3C,0x00,0x00,0x00,0x00}, // Y + {0x00,0x00,0x7F,0x63,0x43,0x06,0x0C,0x18,0x30,0x61,0x63,0x7F,0x00,0x00,0x00,0x00}, // Z + {0x00,0x00,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3C,0x00,0x00,0x00,0x00}, // [ + {0x00,0x00,0x80,0xC0,0xE0,0x70,0x38,0x1C,0x0E,0x07,0x03,0x01,0x00,0x00,0x00,0x00}, // \ (back slash) + {0x00,0x00,0x3C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x3C,0x00,0x00,0x00,0x00}, // ] + {0x08,0x1C,0x36,0x63,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ^ + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,0x00}, // _ + {0x18,0x18,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ` 0x60 + {0x00,0x00,0x00,0x00,0x00,0x3C,0x46,0x06,0x3E,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // a + {0x00,0x00,0x70,0x30,0x30,0x3C,0x36,0x33,0x33,0x33,0x33,0x6E,0x00,0x00,0x00,0x00}, // b + {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x60,0x60,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // c + {0x00,0x00,0x0E,0x06,0x06,0x1E,0x36,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // d + {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x7E,0x60,0x63,0x3E,0x00,0x00,0x00,0x00}, // e + {0x00,0x00,0x1C,0x36,0x32,0x30,0x7C,0x30,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // f + {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x66,0x3C,0x00,0x00}, // g + {0x00,0x00,0x70,0x30,0x30,0x36,0x3B,0x33,0x33,0x33,0x33,0x73,0x00,0x00,0x00,0x00}, // h + {0x00,0x00,0x0C,0x0C,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // i + {0x00,0x00,0x06,0x06,0x00,0x0E,0x06,0x06,0x06,0x06,0x06,0x66,0x66,0x3C,0x00,0x00}, // j + {0x00,0x00,0x70,0x30,0x30,0x33,0x33,0x36,0x3C,0x36,0x33,0x73,0x00,0x00,0x00,0x00}, // k + {0x00,0x00,0x1C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x0C,0x1E,0x00,0x00,0x00,0x00}, // l + {0x00,0x00,0x00,0x00,0x00,0x6E,0x7F,0x6B,0x6B,0x6B,0x6B,0x6B,0x00,0x00,0x00,0x00}, // m + {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x33,0x33,0x00,0x00,0x00,0x00}, // n + {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x63,0x63,0x63,0x63,0x3E,0x00,0x00,0x00,0x00}, // o + {0x00,0x00,0x00,0x00,0x00,0x6E,0x33,0x33,0x33,0x33,0x3E,0x30,0x30,0x78,0x00,0x00}, // p 0x70 + {0x00,0x00,0x00,0x00,0x00,0x3B,0x66,0x66,0x66,0x66,0x3E,0x06,0x06,0x0F,0x00,0x00}, // q + {0x00,0x00,0x00,0x00,0x00,0x6E,0x3B,0x33,0x30,0x30,0x30,0x78,0x00,0x00,0x00,0x00}, // r + {0x00,0x00,0x00,0x00,0x00,0x3E,0x63,0x38,0x0E,0x03,0x63,0x3E,0x00,0x00,0x00,0x00}, // s + {0x00,0x00,0x08,0x18,0x18,0x7E,0x18,0x18,0x18,0x18,0x1B,0x0E,0x00,0x00,0x00,0x00}, // t + {0x00,0x00,0x00,0x00,0x00,0x66,0x66,0x66,0x66,0x66,0x66,0x3B,0x00,0x00,0x00,0x00}, // u + {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x36,0x36,0x1C,0x1C,0x08,0x00,0x00,0x00,0x00}, // v + {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x6B,0x6B,0x7F,0x36,0x00,0x00,0x00,0x00}, // w + {0x00,0x00,0x00,0x00,0x00,0x63,0x36,0x1C,0x1C,0x1C,0x36,0x63,0x00,0x00,0x00,0x00}, // x + {0x00,0x00,0x00,0x00,0x00,0x63,0x63,0x63,0x63,0x63,0x3F,0x03,0x06,0x3C,0x00,0x00}, // y + {0x00,0x00,0x00,0x00,0x00,0x7F,0x66,0x0C,0x18,0x30,0x63,0x7F,0x00,0x00,0x00,0x00}, // z + {0x00,0x00,0x0E,0x18,0x18,0x18,0x70,0x18,0x18,0x18,0x18,0x0E,0x00,0x00,0x00,0x00}, // { + {0x00,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x18,0x18,0x18,0x18,0x18,0x00,0x00,0x00}, // | + {0x00,0x00,0x70,0x18,0x18,0x18,0x0E,0x18,0x18,0x18,0x18,0x70,0x00,0x00,0x00,0x00}, // } + {0x00,0x00,0x3B,0x6E,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ~ + {0x00,0x70,0xD8,0xD8,0x70,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00} +}; // DEL diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcdd.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcdd.c new file mode 100644 index 000000000..de00224d2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/lcdd.c @@ -0,0 +1,116 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of LCD driver, Include LCD initialization, + * LCD on/off and LCD back-light control. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" +#include + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + uint8_t ili9488_lcdMode; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Turn on the LCD. + */ +void LCDD_On( void) +{ + if (ili9488_lcdMode == ILI9488_SPIMODE ) { + ILI9488_SpiOn(); + } else { + ILI9488_EbiOn(); + } +} + +/** + * \brief Turn off the LCD. + */ +void LCDD_Off( void) +{ + if (ili9488_lcdMode == ILI9488_SPIMODE ) { + ILI9488_SpiOff(); + } else { + ILI9488_EbiOff(); + } +} + +/** + * \brief Set the back-light of the LCD. + * + * \param level Back-light brightness level [1..16], 1 means maximum brightness. + */ +#if defined (BOARD_LCD_SPI_EXT1) +void LCDD_SpiSetBacklight (uint32_t level) +{ + /* Ensure valid level */ + level = (level < 1) ? 1 : level; + level = (level > 16) ? 16 : level; + PWMC_SetDutyCycle(PWM0, CHANNEL_PWM_LCD, level); +} +#endif + +/** + * \brief Initializes the LCD controller. + * Configure SMC to access LCD controller at 64MHz MCK. + * \param lcdMode LCD_SPI or LCD_EBI mode + * \param cRotate rotate direction 0: H 1:V + */ +void LCDD_Initialize( uint8_t lcdMode, sXdmad * dmad, uint8_t cRotate) +{ + ili9488_lcdMode = lcdMode; + /* Initialize LCD controller */ + if (lcdMode == ILI9488_SPIMODE ) { + ILI9488_SpiInitialize(dmad) ; + ILI9488_SpiSetDisplayLandscape(1, cRotate); + } else { + ILI9488_EbiInitialize(dmad) ; + ILI9488_EbiSetDisplayLandscape(1, cRotate); + } + +#if defined (BOARD_LCD_SPI_EXT1) + /* Set LCD back-light */ + LCDD_SpiSetBacklight( 16 ); +#endif + +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/led.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/led.c new file mode 100644 index 000000000..9f5eafcf3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/led.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*----------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Local Variables + *----------------------------------------------------------------------------*/ + +#ifdef PINS_LEDS +static const Pin pinsLeds[] = {PIN_LED_0, PIN_LED_1}; +static const uint32_t numLeds = PIO_LISTSIZE( pinsLeds ); +#endif + +/*------------------------------------------------------------------------------ + * Global Functions + *----------------------------------------------------------------------------*/ + +/** + * Configures the pin associated with the given LED number. If the LED does + * not exist on the board, the function does nothing. + * \param led Number of the LED to configure. + * \return 1 if the LED exists and has been configured; otherwise 0. + */ +extern uint32_t LED_Configure( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + // Check that LED exists + if ( dwLed >= numLeds) { + return 0; + } + + // Configure LED + return ( PIO_Configure( &pinsLeds[dwLed], 1 ) ); +#else + return 0; +#endif +} + +/** + * Turns the given LED on if it exists; otherwise does nothing. + * \param led Number of the LED to turn on. + * \return 1 if the LED has been turned on; 0 otherwise. + */ +extern uint32_t LED_Set( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + /* Check if LED exists */ + if ( dwLed >= numLeds ) { + return 0; + } + + /* Turn LED on */ + if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 ) { + PIO_Set( &pinsLeds[dwLed] ); + } else { + PIO_Clear( &pinsLeds[dwLed] ); + } + + return 1; +#else + return 0; +#endif +} + +/** + * Turns a LED off. + * + * \param led Number of the LED to turn off. + * \return 1 if the LED has been turned off; 0 otherwise. + */ +extern uint32_t LED_Clear( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + /* Check if LED exists */ + if ( dwLed >= numLeds ) { + return 0; + } + + /* Turn LED off */ + if ( pinsLeds[dwLed].type == PIO_OUTPUT_0 ) { + PIO_Clear( &pinsLeds[dwLed] ); + } else { + PIO_Set( &pinsLeds[dwLed] ); + } + + return 1; +#else + return 0; +#endif +} + +/** + * Toggles the current state of a LED. + * + * \param led Number of the LED to toggle. + * \return 1 if the LED has been toggled; otherwise 0. + */ +extern uint32_t LED_Toggle( uint32_t dwLed ) +{ +#ifdef PINS_LEDS + /* Check if LED exists */ + if ( dwLed >= numLeds ) { + return 0; + } + + /* Toggle LED */ + if ( PIO_GetOutputDataStatus( &pinsLeds[dwLed] ) ) { + PIO_Clear( &pinsLeds[dwLed] ); + } else { + PIO_Set( &pinsLeds[dwLed] ); + } + + return 1; +#else + return 0; +#endif +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/math.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/math.c new file mode 100644 index 000000000..7f82033fe --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/math.c @@ -0,0 +1,87 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Returns the minimum value between two integers. + * + * \param a First integer to compare. + * \param b Second integer to compare. + */ +extern uint32_t min( uint32_t dwA, uint32_t dwB ) +{ + if ( dwA < dwB ) { + return dwA ; + } else { + return dwB ; + } +} + +/*------------------------------------------------------------------------------ + * Returns the absolute value of an integer. + * + * \param value Integer value. + * + * \note Do not call this function "abs", problem with gcc ! + */ +extern uint32_t absv( int32_t lValue ) +{ + if ( lValue < 0 ) { + return -lValue ; + } else { + return lValue ; + } +} + +/*------------------------------------------------------------------------------ + * Computes and returns x power of y. + * + * \param x Value. + * \param y Power. + */ +extern uint32_t power( uint32_t dwX, uint32_t dwY ) +{ + uint32_t dwResult = 1 ; + + while ( dwY > 0 ) { + dwResult *= dwX ; + dwY-- ; + } + return dwResult ; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/omnivision.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/omnivision.c new file mode 100644 index 000000000..67d205efc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/omnivision.c @@ -0,0 +1,429 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + +/** Slave address of OMNIVISION chips. */ +#define OV_CAPTOR_ADDRESS_1 0x30 +#define OV_CAPTOR_ADDRESS_2 0x21 +#define OV_CAPTOR_ADDRESS_3 0x3c +#define OV_CAPTOR_ADDRESS_4 0x10 + +/** terminating list entry for register in configuration file */ +#define OV_REG_TERM 0xFF +#define OV_REG_DELAY 0xFFFF +/** terminating list entry for value in configuration file */ +#define OV_VAL_TERM 0xFF + +static const Pin pin_ISI_RST= BOARD_ISI_RST; +static uint8_t twiSlaveAddr = OV_CAPTOR_ADDRESS_1; +/*---------------------------------------------------------------------------- + * Local Functions + *----------------------------------------------------------------------------*/ +static void ov_reset(void) +{ + volatile uint32_t i; + PIO_Configure(&pin_ISI_RST, 1); + PIO_Clear(&pin_ISI_RST); + for(i = 0; i < 6000; i++ ); + PIO_Set(&pin_ISI_RST); + for(i = 0; i<6000; i++ ); +} + + +/** + * \brief Read PID and VER + * \param pTwid TWI interface + * \return VER | (PID<<8) + */ +static uint16_t ov_id8(Twid *pTwid) +{ + uint8_t id, ver; + uint8_t status; + // OV_PID + status = ov_read_reg8(pTwid, 0x0A, &id); + if( status != 0 ) + return 0; + TRACE_INFO("PID = 0x%X\n\r", id); + + // OV_VER + status = ov_read_reg8(pTwid, 0x0B, &ver); + if( status != 0 ) + return 0; + TRACE_INFO("VER = 0x%X\n\r", ver); + + return((uint16_t)(id <<8) | ver); +} + +/** + * \brief Read PID and VER + * \param pTwid TWI interface + * \return VER | (PID<<8) + */ +static uint16_t ov_id16(Twid *pTwid) +{ + uint8_t id, ver; + // OV_PID + ov_read_reg16(pTwid, 0x300A, &id); + TRACE_INFO("PID = 0x%X\n\r", id); + + // OV_VER + ov_read_reg16(pTwid, 0x300B, &ver); + TRACE_INFO("VER = 0x%X\n\r", ver); + + return((uint16_t)(id <<8) | ver); +} + +/** + * \brief Read PID and VER + * \param pTwid TWI interface + * \return VER | (PID<<8) + */ +static uint16_t ov_id(Twid *pTwid) +{ + uint16_t id; + TRACE_INFO(" Try TWI address 0x%x \n\r", twiSlaveAddr); + twiSlaveAddr = OV_CAPTOR_ADDRESS_1; + id = ov_id8(pTwid); + if (id == 0) { + twiSlaveAddr = OV_CAPTOR_ADDRESS_2; + TRACE_INFO("Try TWI address 0x%x \n\r", twiSlaveAddr); + id = ov_id8(pTwid); + if (id == 0) { + twiSlaveAddr = OV_CAPTOR_ADDRESS_3; + TRACE_INFO("Try TWI address 0x%x \n\r", twiSlaveAddr); + id = ov_id16(pTwid); + if (id == 0) { + twiSlaveAddr = OV_CAPTOR_ADDRESS_4; + TRACE_INFO("Try TWI address 0x%x \n\r", twiSlaveAddr); + id = ov_id16(pTwid); + } + } + } + return id; +} + + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ +/** + * \brief Read a value from a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be read + * \param pData Data read + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint8_t ov_read_reg8(Twid *pTwid, uint8_t reg, uint8_t *pData) +{ + uint8_t status; + + status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, ®, 1, 0); + status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_read_reg pb\n\r"); + } + return status; +} + +/** + * \brief Read a value from a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be read + * \param pData Data read + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint8_t ov_read_reg16(Twid *pTwid, uint16_t reg, uint8_t *pData) +{ + uint8_t status; + uint8_t reg8[2]; + reg8[0] = reg>>8; + reg8[1] = reg & 0xff; + + status = TWID_Write( pTwid, twiSlaveAddr, 0, 0, reg8, 2, 0); + status |= TWID_Read( pTwid, twiSlaveAddr, 0, 0, pData, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_read_reg pb\n\r"); + } + return status; +} + +/** + * \brief Write a value to a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be written + * \param pData Data written + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint8_t ov_write_reg8(Twid *pTwid, uint8_t reg, uint8_t val) +{ + uint8_t status; + + status = TWID_Write(pTwid, twiSlaveAddr, reg, 1, &val, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_write_reg pb\n\r"); + } + return status; +} + +/** + * \brief Write a value to a register in an OV sensor device. + * \param pTwid TWI interface + * \param reg Register to be written + * \param pData Data written + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint8_t ov_write_reg16(Twid *pTwid, uint16_t reg, uint8_t val) +{ + uint8_t status; + status = TWID_Write(pTwid, twiSlaveAddr, reg, 2, &val, 1, 0); + if( status != 0 ) { + TRACE_ERROR("ov_write_reg pb\n\r"); + } + + return status; +} + + +/** + * \brief Initialize a list of OV registers. + * The list of registers is terminated by the pair of values + * \param pTwid TWI interface + * \param pReglist Register list to be written + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint32_t ov_write_regs8(Twid *pTwid, const struct ov_reg* pReglist) +{ + uint32_t err; + uint32_t size=0; + const struct ov_reg *pNext = pReglist; + volatile uint32_t delay; + + TRACE_DEBUG("ov_write_regs:"); + while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) { + err = ov_write_reg8(pTwid, pNext->reg, pNext->val); + + size++; + for(delay=0;delay<=10000;delay++); + if (err == TWID_ERROR_BUSY){ + TRACE_ERROR("ov_write_regs: TWI ERROR\n\r"); + return err; + } + pNext++; + } + TRACE_DEBUG_WP("\n\r"); + return 0; +} + + +/** + * \brief Initialize a list of OV registers. + * The list of registers is terminated by the pair of values + * \param pTwid TWI interface + * \param pReglist Register list to be written + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint32_t ov_write_regs16(Twid *pTwid, const struct ov_reg* pReglist) +{ + uint32_t err = 0; + uint32_t size = 0; + const struct ov_reg *pNext = pReglist; + volatile uint32_t delay; + + TRACE_DEBUG("ov_write_regs:"); + while (!((pNext->reg == OV_REG_TERM) && (pNext->val == OV_VAL_TERM))) { + err = ov_write_reg16(pTwid, pNext->reg, pNext->val); + size++; + for(delay = 0;delay <= 10000; delay++); + if (err == TWID_ERROR_BUSY){ + TRACE_ERROR("ov_write_regs: TWI ERROR\n\r"); + return err; + } + pNext++; + } + TRACE_DEBUG_WP("\n\r"); + return 0; +} + +void isOV5640_AF_InitDone(Twid *pTwid) +{ + uint8_t value = 0; + while(1){ + ov_read_reg16(pTwid, 0x3029, &value); + if (value == 0x70) + break; + } +} + +/** + * \brief AF for OV 5640 + * \param pTwid TWI interface + * \return 0 if no error; otherwise TWID_ERROR_BUSY + */ +uint32_t ov_5640_AF_single(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3023, 1); + ov_write_reg16(pTwid, 0x3022, 3); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) + break; + } + return 0; +} + +uint32_t ov_5640_AF_continue(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3024, 1); + ov_write_reg16(pTwid, 0x3022, 4); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) + break; + } + return 0; +} + +uint32_t ov_5640_AFPause(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3023, 1); + ov_write_reg16(pTwid, 0x3022, 6); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) + break; + } + return 0; +} + +uint32_t ov_5640_AFrelease(Twid *pTwid) +{ + uint8_t value; + ov_write_reg16(pTwid, 0x3023, 1); + ov_write_reg16(pTwid, 0x3022, 8); + value =1; + while(1){ + ov_read_reg16(pTwid, 0x3023, &value); + if (value == 0) + break; + } + return 0; +} + +/** + * \brief Dump all register + * \param pTwid TWI interface + */ +void ov_DumpRegisters8(Twid *pTwid) +{ + uint32_t i; + uint8_t value; + + TRACE_INFO_WP("Dump all camera register\n\r"); + for(i = 0; i <= 0x5C; i++) { + value = 0; + ov_read_reg8(pTwid, i, &value); + TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value); + if( ((i+1)%5) == 0 ) { + TRACE_INFO_WP("\n\r"); + } + } + TRACE_INFO_WP("\n\r"); +} + +/** + * \brief Dump all register + * \param pTwid TWI interface + */ +void ov_DumpRegisters16(Twid *pTwid) +{ + uint32_t i; + uint8_t value; + + TRACE_INFO_WP("Dump all camera register\n\r"); + for(i = 3000; i <= 0x305C; i++) { + value = 0; + ov_read_reg16(pTwid, i, &value); + TRACE_INFO_WP("[0x%02x]=0x%02x ", i, value); + if( ((i+1)%5) == 0 ) { + TRACE_INFO_WP("\n\r"); + } + } + TRACE_INFO_WP("\n\r"); +} + +/** + * \brief Sequence For correct operation of the sensor + * \param pTwid TWI interface + * \return OV type + */ +uint8_t ov_init(Twid *pTwid) +{ + uint16_t id = 0; + uint8_t ovType; + ov_reset(); + id = ov_id(pTwid); + switch (id) { + case 0x7740: case 0x7742: + ovType = OV_7740; + TRACE_INFO(" Camera Model :- OV_7740"); + break; + case 0x9740: case 0x9742: + ovType = OV_9740; + TRACE_INFO(" Camera Model :- OV_9740"); + break; + case 0x2642: case 0x2640: + ovType = OV_2640; + TRACE_INFO(" Camera Model :- OV_2640"); + break; + case 0x2643: + ovType = OV_2643; + TRACE_INFO(" Camera Model :- OV_2643"); + break; + case 0x5640: + ovType = OV_5640; + TRACE_INFO(" Camera Model :- OV_5640"); + break; + default: + ovType = OV_UNKNOWN; + TRACE_INFO(" Camera Model :- UNKNOWN"); + TRACE_ERROR("Can not support product ID %x \n\r", id); + break; + } + return ovType; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov.c new file mode 100644 index 000000000..f471c439a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov.c @@ -0,0 +1,210 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" + + +const capture_size ov_sizes[] = { + //{width, height} + { 160, 120 }, // QQVGA + { 352, 288 }, // CIF + { 320, 240 }, + { 640, 360 }, + { 640, 480 }, + // SWVGA + { 800, 600 }, + /// SXGA + {1280, 960 }, + {1280, 720 }, + /// UXGA + {1600, 1200 }, +}; + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configure the OV for a specified image size, pixel format, + * and frame period. + */ +void ov_configure(Twid *pTwid, uint8_t ovType, uint32_t width, uint32_t heigth) +{ + const struct ov_reg *reg_conf; + uint8_t goodCaptureSize = 0; + uint8_t i; + + reg_conf = ov5640_yuv_vga; + TRACE_DEBUG("ovxxx_configure\n\r"); + for( i = 0; i< sizeof(ov_sizes); i++ ) { + if( ov_sizes[i].width == width ) { + if( ov_sizes[i].height != heigth ) { + TRACE_INFO("ov configure vsize not define\n\r"); + } else { + goodCaptureSize = 1; + break; + } + } + } + if( goodCaptureSize == 0 ) { + TRACE_ERROR("Problem size\n\r"); + while(1); + } + switch (ovType){ + case OV_2640: { + // Default value + reg_conf = ov2640_yuv_qvga; + // common register initialization + switch(width) { + case 320: //VGA + printf("-I- QVGA 640 x 480\n\r"); + reg_conf = ov2640_yuv_qvga; + break; + case 640: //VGA + TRACE_INFO("VGA 640 x 480\n\r"); + reg_conf = ov2640_yuv_vga; + break; + default: + TRACE_DEBUG("ov2640_configure problem\n\r"); + break; + } + break; + } + case OV_7740: { + // Default value + reg_conf = OV7740_VGA_YUV422; + // common register initialization + switch(width) { + case 640: //VGA + TRACE_INFO(" VGA 640 x 480\n\r"); + reg_conf = OV7740_VGA_YUV422; + break; + + case 352: //CIF + TRACE_INFO(" VGA 640 x 480\n\r"); + reg_conf = OV7740_CIF_YUV422; + break; + + case 320: //QVGA + TRACE_INFO(" QVGA 320 x 240\n\r"); + reg_conf = OV7740_QVGA_YUV422; + break; + + case 160: //QQVGA + TRACE_INFO(" QVGA 320 x 240\n\r"); + reg_conf = OV7740_QQVGA_YUV422; + break; + + default: + TRACE_DEBUG("ov7740_configure problem\n\r"); + break; + } + break; + } + case OV_9740: { + // Default value + reg_conf = ov9740_yuv_vga; + // common register initialization + switch(width) { + case 640: //VGA + TRACE_INFO(" VGA 640 x 360\n\r"); + reg_conf = ov9740_yuv_vga; + break; + case 1280: //VGA + TRACE_INFO(" VGA 1280 x 720\n\r"); + reg_conf = ov9740_yuv_sxga; + break; + default: + TRACE_DEBUG("ov9740_configure problem\n\r"); + break; + } + break; + } + case OV_2643: { + // Default value + reg_conf = ov2643_yuv_vga; + // common register initialization + switch(width) { + case 1600: //UXGA + TRACE_INFO(" UXGA 1600 x 1200 \n\r"); + reg_conf = ov2643_yuv_uxga; + break; + case 800: //SWVGA + TRACE_INFO("SWVGA 800 x 600\n\r"); + reg_conf = ov2643_yuv_swvga; + break; + case 640: //VGA + TRACE_INFO(" VGA 640 x 480\n\r"); + reg_conf = ov2643_yuv_vga; + break; + default: + TRACE_DEBUG("ov2643_configure problem\n\r"); + break; + } + break; + } + case OV_5640: { + // Default value + reg_conf = ov5640_yuv_vga; + // common register initialization + switch(width) { + case 640: //VGA + TRACE_INFO(" VGA 640 x 480\n\r"); + reg_conf = ov5640_yuv_vga; + break; + case 1280: //SXGA + TRACE_INFO(" SXGA 1280 x 720\n\r"); + reg_conf = ov5640_yuv_sxga; + break; + default: + TRACE_DEBUG("ov5640_configure problem\n\r"); + break; + } + break; + } + } + if ((ovType == OV_5640) || (ovType == OV_9740)) + ov_write_regs16(pTwid, reg_conf); + else + ov_write_regs8(pTwid, reg_conf); +} + +/** + * \brief Configure the OV 5640 afc firmware. + */ +void ov_5640Afc_Firmware(Twid *pTwid) +{ + const struct ov_reg *reg_conf; + reg_conf = ov5640_afc; + ov_write_regs16(pTwid, reg_conf); +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov2640_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov2640_config.c new file mode 100644 index 000000000..7e5e8d12f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov2640_config.c @@ -0,0 +1,338 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/* + * ID + */ + + + +/*------------------------------------------------------------------------------ + * Local Variables + *----------------------------------------------------------------------------*/ + +/* 320*240 */ +const struct ov_reg ov2640_yuv_qvga[]= { +{0xff, 0x01},{0x12, 0x80},{0xff, 0x00},{0x2c, 0xff},{0x2e, 0xdf}, +{0xff, 0x01},{0x3c, 0x32},{0x11, 0x00},{0x09, 0x02},{0x04, 0x28}, +{0x13, 0xe5},{0x14, 0x48},{0x2c, 0x0c},{0x33, 0x78},{0x3a, 0x33}, +{0x3b, 0xfb},{0x3e, 0x00},{0x43, 0x11},{0x16, 0x10},{0x39, 0x02}, +{0x35, 0x88},{0x22, 0x0a},{0x37, 0x40},{0x23, 0x00},{0x34, 0xa0}, +{0x36, 0x1a},{0x06, 0x02},{0x07, 0xc0},{0x0d, 0xb7},{0x0e, 0x01}, +{0x4c, 0x00},{0x4a, 0x81},{0x21, 0x99},{0x24, 0x3a},{0x25, 0x32}, +{0x26, 0x82},{0x5c, 0x00},{0x63, 0x00},{0x5d, 0x55},{0x5e, 0x7d}, +{0x5f, 0x7d},{0x60, 0x55},{0x61, 0x70},{0x62, 0x80},{0x7c, 0x05}, +{0x20, 0x80},{0x28, 0x30},{0x6c, 0x00},{0x6d, 0x80},{0x6e, 0x00}, +{0x70, 0x02},{0x71, 0x94},{0x73, 0xc1},{0x3d, 0x34},{0x5a, 0x57}, +{0x4f, 0xbb},{0x50, 0x9c},{0xff, 0x00},{0xe5, 0x7f},{0xf9, 0xc0}, +{0x41, 0x24},{0xe0, 0x14},{0x76, 0xff},{0x33, 0xa0},{0x42, 0x20}, +{0x43, 0x18},{0x4c, 0x00},{0x87, 0xd0},{0x88, 0x3f},{0xd7, 0x03}, +{0xd9, 0x10},{0xd3, 0x82},{0xc8, 0x08},{0xc9, 0x80},{0x7c, 0x00}, +{0x7d, 0x02},{0x7c, 0x03},{0x7d, 0x48},{0x7d, 0x48},{0x7c, 0x08}, +{0x7d, 0x20},{0x7d, 0x10},{0x7d, 0x0e},{0x90, 0x00},{0x91, 0x0e}, +{0x91, 0x1a},{0x91, 0x31},{0x91, 0x5a},{0x91, 0x69},{0x91, 0x75}, +{0x91, 0x7e},{0x91, 0x88},{0x91, 0x8f},{0x91, 0x96},{0x91, 0xa3}, +{0x91, 0xaf},{0x91, 0xc4},{0x91, 0xd7},{0x91, 0xe8},{0x91, 0x20}, +{0x92, 0x00},{0x93, 0x06},{0x93, 0xe3},{0x93, 0x05},{0x93, 0x05}, +{0x93, 0x00},{0x93, 0x02},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00}, +{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x93, 0x00},{0x96, 0x00}, +{0x97, 0x08},{0x97, 0x19},{0x97, 0x02},{0x97, 0x0c},{0x97, 0x24}, +{0x97, 0x30},{0x97, 0x28},{0x97, 0x26},{0x97, 0x02},{0x97, 0x98}, +{0x97, 0x80},{0x97, 0x00},{0x97, 0x00},{0xc3, 0xed},{0xa4, 0x00}, +{0xa8, 0x00},{0xc5, 0x11},{0xc6, 0x51},{0xbf, 0x80},{0xc7, 0x10}, +{0xb6, 0x66},{0xb8, 0xa5},{0xb7, 0x64},{0xb9, 0x7c},{0xb3, 0xaf}, +{0xb4, 0x97},{0xb5, 0xff},{0xb0, 0xc5},{0xb1, 0x94},{0xb2, 0x0f}, +{0xc4, 0x5c},{0xc0, 0xc8},{0xc1, 0x96},{0x86, 0x1d},{0x50, 0x00}, +{0x51, 0x90},{0x52, 0x18},{0x53, 0x00},{0x54, 0x00},{0x55, 0x88}, +{0x57, 0x00},{0x5a, 0x90},{0x5b, 0x18},{0x5c, 0x05},{0xc3, 0xed}, +{0x7f, 0x00},{0xda, 0x04},{0xe5, 0x1f},{0xe1, 0x67},{0xe0, 0x00}, +{0xdd, 0xff},{0x05, 0x00},{0xff, 0x01},{0x11, 0x01},{0xff, 0x01}, +{0x12, 0x40},{0x17, 0x11},{0x18, 0x43},{0x19, 0x00},{0x1a, 0x4b}, +{0x32, 0x09},{0x4f, 0xca},{0x50, 0xa8},{0x5a, 0x23},{0x6d, 0x00}, +{0x3d, 0x38},{0x39, 0x12},{0x35, 0xda},{0x22, 0x1a},{0x37, 0xc3}, +{0x23, 0x00},{0x34, 0xc0},{0x36, 0x1a},{0x06, 0x88},{0x07, 0xc0}, +{0x0d, 0x87},{0x0e, 0x41},{0x4c, 0x00},{0x48, 0x00},{0x5B, 0x00}, +{0x42, 0x03},{0xff, 0x00},{0xe0, 0x04},{0xc0, 0x64},{0xc1, 0x4B}, +{0x8c, 0x00},{0x86, 0x1D},{0xd3, 0x82},{0xe0, 0x00},{0xff, 0x00}, +{0xc0, 0x64},{0xc1, 0x4B},{0x8c, 0x00}, //HSIZE 0x64*8 = 800, VSIZE 0x4b*8 = 600 +{0x86, 0x3D},{0x50, 0x89}, //LP_DP, V_DIV 1, H_DIV 1 +{0x51, 0xC8},{0x52, 0x96},{0x53, 0x00},{0x54, 0x00},{0x55, 0x00}, + //HSIZE 0xC8(200)*4 = 800, VSIZE 0x96(150)*4 = 600 +{0x5a, 0x50},{0x5b, 0x3C},{0x5c, 0x00}, //ZMOW 0x50(80)*4 = 320, ZMOH 0x3C(60)*4 = 240 +{0xd3, 0x04},{0xFF, 0x00},{0xE0, 0x04},{0xE1, 0x67},{0xD7, 0x01}, +{0xDA, 0x00},{0xD3, 0x82},{0xE0, 0x00},{0xFF, 0xFF} +}; + +const struct ov_reg ov2640_yuv_vga[]= { + {0xff, 0x01}, //dsp + {0x12, 0x80}, //reset + {0xff, 0x00}, //sensor + {0x2c, 0xff}, //? + {0x2e, 0xdf}, //ADDVSH, VSYNC msb=223 + {0xff, 0x01}, //dsp + {0x3c, 0x32}, //? + {0x11, 0x00}, //clock rate off + {0x09, 0x02}, //2 capablity + standby mode + {0x04, 0x28}, //? ?????????????????????????????????? + {0x13, 0xe5}, // + {0x14, 0x48}, //Auto agc + {0x2c, 0x0c}, //? + {0x33, 0x78}, //? + {0x3a, 0x33}, //? + {0x3b, 0xfb}, //? + {0x3e, 0x00}, //? + {0x43, 0x11}, //? + {0x16, 0x10}, //? + {0x39, 0x02}, //? + {0x35, 0x88}, //? + {0x22, 0x0a}, //? + {0x37, 0x40}, //? + {0x23, 0x00}, //? + {0x34, 0xa0}, //startpoint 0 + {0x36, 0x1a}, //? XXXXXXXXXXXXXXXX + {0x06, 0x02}, //? + {0x07, 0xc0}, //? + {0x0d, 0xb7}, //? + {0x0e, 0x01}, //? + {0x4c, 0x00}, //? + {0x4a, 0x81}, //? + {0x21, 0x99}, //? + {0x24, 0x3a}, // Luminance high + {0x25, 0x32}, // Luminance low + //{0x24, 0x10}, // Luminance high + //{0x25, 0x03}, // Luminance low + + {0x26, 0xF3}, // Fast mode large Step Range Threshold + {0x5c, 0x00}, //? + {0x63, 0x00}, //? + {0x5d, 0x55}, //zone + {0x5e, 0x7d}, //zone + {0x5f, 0x7d}, //zone + {0x60, 0x55}, //zone + {0x61, 0x70}, //Histogram low + {0x62, 0x80}, //Histogram high + {0x7c, 0x05}, //? + {0x20, 0x80}, //? + {0x28, 0x30}, //? + {0x6c, 0x00}, //? + {0x6d, 0x80}, //? + {0x6e, 0x00}, //? + {0x70, 0x02}, //? + {0x71, 0x94}, //? + {0x73, 0xc1}, //? + {0x3d, 0x34}, //? + {0x5a, 0x57}, //? + {0x4f, 0xbb}, //50Hz + {0x50, 0x9c}, //60Hz + + {0xff, 0x00}, //dsp + {0xe5, 0x7f}, //? + {0xf9, 0xc0}, //MicroC reset,Boot + {0x41, 0x24}, //? + {0xe0, 0x14}, //JPEG,DVP reset + {0x76, 0xff}, //? + {0x33, 0xa0}, //? + {0x42, 0x20}, //? + {0x43, 0x18}, //? + {0x4c, 0x00}, //? + {0x87, 0xd0}, //Module Enable BPC+WPC 11010000 + {0x88, 0x3f}, //? + {0xd7, 0x03}, //? + {0xd9, 0x10}, //? + {0xd3, 0x82}, //Auto mode + {0xc8, 0x08}, //? + {0xc9, 0x80}, //? + {0x7c, 0x00}, //SDE indirect register access: address + {0x7d, 0x02}, //SDE indirect register data + {0x7c, 0x03}, // + {0x7d, 0x48}, // + {0x7d, 0x48}, // + {0x7c, 0x08}, // + {0x7d, 0x20}, // + {0x7d, 0x10}, // + {0x7d, 0x0e}, // + {0x90, 0x00}, //? + {0x91, 0x0e}, //? + {0x91, 0x1a}, //? + {0x91, 0x31}, //? + {0x91, 0x5a}, //? + {0x91, 0x69}, //? + {0x91, 0x75}, //? + {0x91, 0x7e}, //? + {0x91, 0x88}, //? + {0x91, 0x8f}, //? + {0x91, 0x96}, //? + {0x91, 0xa3}, //? + {0x91, 0xaf}, //? + {0x91, 0xc4}, //? + {0x91, 0xd7}, //? + {0x91, 0xe8}, //? + {0x91, 0x20}, //? + {0x92, 0x00}, //? + {0x93, 0x06}, //? + {0x93, 0xe3}, //? + {0x93, 0x05}, //? + {0x93, 0x05}, //? + {0x93, 0x00}, //? + {0x93, 0x02}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x93, 0x00}, //? + {0x96, 0x00}, //? + {0x97, 0x08}, //? + {0x97, 0x19}, //? + {0x97, 0x02}, //? + {0x97, 0x0c}, //? + {0x97, 0x24}, //? + {0x97, 0x30}, //? + {0x97, 0x28}, //? + {0x97, 0x26}, //? + {0x97, 0x02}, //? + {0x97, 0x98}, //? + {0x97, 0x80}, //? + {0x97, 0x00}, //? + {0x97, 0x00}, //? + {0xc3, 0xed}, //Module enable + {0xa4, 0x00}, //? + {0xa8, 0x00}, //? + {0xc5, 0x11}, //? + {0xc6, 0x51}, //? + {0xbf, 0x80}, //? + {0xc7, 0x10}, //? + {0xb6, 0x66}, //? + {0xb8, 0xa5}, //? + {0xb7, 0x64}, //? + {0xb9, 0x7c}, //? + {0xb3, 0xaf}, //? + {0xb4, 0x97}, //? + {0xb5, 0xff}, //? + {0xb0, 0xc5}, //? + {0xb1, 0x94}, //? + {0xb2, 0x0f}, //? + {0xc4, 0x5c}, //? + {0xc0, 0xc8}, // HSIZE8[7:0] 1600 + {0xc1, 0x96}, // VSIZE8[7:0] 1200 + {0x86, 0x1d}, //Module enable + {0x50, 0x00}, //? + {0x51, 0x90}, //H_SIZE[7:0] (real/4) 1600 + {0x52, 0x18}, //V_SIZE[7:0] (real/4) 1120 + {0x53, 0x00}, //OFFSET_X[7:0] + {0x54, 0x00}, //OFFSET_Y[7:0] + {0x55, 0x88}, //V_SIZE[8]=1 H_SIZE[8] + {0x57, 0x00}, //? + {0x5a, 0x90}, //OUTW + {0x5b, 0x18}, //OUTH + {0x5c, 0x05}, //OUTW8 ,OUTH8 + {0xc3, 0xed}, // + {0x7f, 0x00}, //? + {0xda, 0x04}, //Image output format select ------ RAW + {0xe5, 0x1f}, //? + {0xe1, 0x67}, //? + {0xe0, 0x00}, //Reset + {0xdd, 0xff}, //? + {0x05, 0x00}, //Bypass DSP no + {0xC2, 0x08 | 0x04 | 0x02 }, + + {0xff, 0x01}, //Sensor + {0x11, 0x01}, //? + {0xff, 0x01}, //Sensor + {0x12, 0x40}, //Preview mode + {0x17, 0x11}, //? + {0x18, 0x43}, //? + {0x19, 0x00}, //? + {0x1a, 0x4b}, //? + {0x32, 0x09}, //? + {0x4f, 0xca}, //? + {0x50, 0xa8}, //10 101 000 V_DIVDER = 5 + {0x5a, 0x23}, // OUTW 23 + {0x6d, 0x00}, //? + {0x3d, 0x38}, //? + {0x39, 0x12}, //? + {0x35, 0xda}, //? + {0x22, 0x1a}, //? + {0x37, 0xc3}, //? + {0x23, 0x00}, //? + {0x34, 0xc0}, //? + {0x36, 0x1a}, //? + {0x06, 0x88}, //? + {0x07, 0xc0}, //? + {0x0d, 0x87}, //? + {0x0e, 0x41}, //? + {0x4c, 0x00}, //? + {0x48, 0x00}, //? + {0x5B, 0x00}, //OUTH + {0x42, 0x03}, //? + {0xff, 0x00}, //DSP + + {0xe0, 0x04}, //Reset DVP + {0xc0, 0x64}, // HSIZE8[7:0] 400 + {0xc1, 0x4B}, // VSIZE8[7:0] 300 + {0x8c, 0x00}, //? + {0x86, 0x1D}, //Modle enable + {0xd3, 0x82}, //Auto mode DVP PCLK=2 + {0xe0, 0x00}, //Reset + + {0xff, 0x00}, //DSP + {0xc0, 0x64}, // HSIZE8[7:0] 400 + {0xc1, 0x4B}, // VSIZE8[7:0] 300 + {0x8c, 0x00}, //? + {0x86, 0x3D}, //? + {0x50, 0x00}, //? + {0x51, 0xC8}, //H_SIZE[7:0] (real/4) 800 + {0x52, 0x96}, //V_SIZE[7:0] (real/4) 600 + {0x53, 0x00}, //OFFSET + {0x54, 0x00}, //OFFSET + {0x55, 0x00}, //H_SIZE[8],V_SIZE[8] + {0x5a, 0xA0}, //OUTW[0-7] 160? + {0x5b, 0x78}, //OUTH[0-7] 120? + {0x5c, 0x00}, //OUTW8,OUTH8 + {0xd3, 0x04}, //? + {0xFF, 0x00}, + {0xE0, 0x04}, + {0xE1, 0x67}, + {0xD7, 0x01}, + {0xDA, 0x00}, //Image output format select ------ YUV422 + {0xD3, 0x82}, + {0xE0, 0x00}, + {0xFF, 0xFF} + }; diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov2643_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov2643_config.c new file mode 100644 index 000000000..a77ade42d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov2643_config.c @@ -0,0 +1,681 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/* + * ID + */ +#define MANUFACTURER_ID 0x7FA2 + + +/*------------------------------------------------------------------------------ + * Local Variables + *----------------------------------------------------------------------------*/ + +const struct ov_reg ov2643_yuv_uxga[]= { + {0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb7}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + + {0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb4}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + {0xFF, 0xFF} +}; + +const struct ov_reg ov2643_yuv_swvga[]= { +{0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb4}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + + {0x3d, 0x48}, + {0x0e, 0xb8}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x20, 0x01}, + {0x21, 0x98}, + {0x22, 0x00}, + {0x23, 0x06}, + {0x24, 0x32}, + {0x25, 0x04}, + {0x26, 0x25}, + {0x27, 0x84}, + {0x28, 0x40}, + {0x29, 0x04}, + {0x2a, 0xce}, + {0x2b, 0x02}, + {0x2c, 0x8a}, + {0x12, 0x09}, + {0x39, 0xd0}, + {0xcd, 0x13}, + {0xde, 0x7c}, + {0x3d, 0x08}, + {0x15, 0x42}, + {0xde, 0x7c}, + {0x0f, 0x24}, + {0xFF, 0xFF} +}; + +const struct ov_reg ov2643_yuv_vga[]= { + {0x12, 0x80}, + {0xc3, 0x1f}, + {0xc4, 0xff}, + {0x3d, 0x48}, + {0xdd, 0xa5}, + {0x0e, 0xb7}, + {0x10, 0x0a}, + {0x11, 0x00}, + {0x0f, 0x14}, + {0x21, 0x25}, + {0x23, 0x0c}, + {0x12, 0x08}, + {0x39, 0x10}, + {0xcd, 0x12}, + {0x13, 0xff}, + {0x14, 0xa7}, + {0x15, 0x42}, + {0x3c, 0xa4}, + {0x18, 0x60}, + {0x19, 0x50}, + {0x1a, 0xe2}, + {0x37, 0xe8}, + {0x16, 0x90}, + //{0x43, 0xC0}, + {0x43, 0x00}, + {0x40, 0xfb}, + {0xa9, 0x44}, + {0x2f, 0xec}, + {0x35, 0x10}, + {0x36, 0x10}, + {0x0c, 0x00}, + {0x0d, 0x00}, + {0xd0, 0x93}, + {0xdc, 0x2b}, + {0xd9, 0x41}, + {0xd3, 0x02}, + {0x3d, 0x08}, + {0x0c, 0x00}, + {0x18, 0x2c}, + {0x19, 0x24}, + {0x1a, 0x71}, + {0x9b, 0x69}, + {0x9c, 0x7d}, + {0x9d, 0x7d}, + {0x9e, 0x69}, + {0x35, 0x04}, + {0x36, 0x04}, + {0x65, 0x12}, + {0x66, 0x20}, + {0x67, 0x39}, + {0x68, 0x4e}, + {0x69, 0x62}, + {0x6a, 0x74}, + {0x6b, 0x85}, + {0x6c, 0x92}, + {0x6d, 0x9e}, + {0x6e, 0xb2}, + {0x6f, 0xc0}, + {0x70, 0xcc}, + {0x71, 0xe0}, + {0x72, 0xee}, + {0x73, 0xf6}, + {0x74, 0x11}, + {0xab, 0x20}, + {0xac, 0x5b}, + {0xad, 0x05}, + {0xae, 0x1b}, + {0xaf, 0x76}, + {0xb0, 0x90}, + {0xb1, 0x90}, + {0xb2, 0x8c}, + {0xb3, 0x04}, + {0xb4, 0x98}, + {0x4c, 0x03}, + {0x4d, 0x30}, + {0x4e, 0x02}, + {0x4f, 0x5c}, + {0x50, 0x56}, + {0x51, 0x00}, + {0x52, 0x66}, + {0x53, 0x03}, + {0x54, 0x30}, + {0x55, 0x02}, + {0x56, 0x5c}, + {0x57, 0x40}, + {0x58, 0x00}, + {0x59, 0x66}, + {0x5a, 0x03}, + {0x5b, 0x20}, + {0x5c, 0x02}, + {0x5d, 0x5c}, + {0x5e, 0x3a}, + {0x5f, 0x00}, + {0x60, 0x66}, + {0x41, 0x1f}, + {0xb5, 0x01}, + {0xb6, 0x02}, + {0xb9, 0x40}, + {0xba, 0x28}, + {0xbf, 0x0c}, + {0xc0, 0x3e}, + {0xa3, 0x0a}, + {0xa4, 0x0f}, + {0xa5, 0x09}, + {0xa6, 0x16}, + {0x9f, 0x0a}, + {0xa0, 0x0f}, + {0xa7, 0x0a}, + {0xa8, 0x0f}, + {0xa1, 0x10}, + {0xa2, 0x04}, + {0xa9, 0x04}, + {0xaa, 0xa6}, + {0x75, 0x6a}, + {0x76, 0x11}, + {0x77, 0x92}, + {0x78, 0x21}, + {0x79, 0xe1}, + {0x7a, 0x02}, + {0x7c, 0x05}, + {0x7d, 0x08}, + {0x7e, 0x08}, + {0x7f, 0x7c}, + {0x80, 0x58}, + {0x81, 0x2a}, + {0x82, 0xc5}, + {0x83, 0x46}, + {0x84, 0x3a}, + {0x85, 0x54}, + {0x86, 0x44}, + {0x87, 0xf8}, + {0x88, 0x08}, + {0x89, 0x70}, + {0x8a, 0xf0}, + {0x8b, 0xf0}, + {0x90, 0xe3}, + {0x93, 0x10}, + {0x94, 0x20}, + {0x95, 0x10}, + {0x96, 0x18}, + {0x0f, 0x34}, + + {0x13, 0x00}, + {0x3d, 0x48}, + {0x0e, 0xb8}, + {0x20, 0x02}, + {0x21, 0x18}, + {0x22, 0x00}, + {0x23, 0x42}, + {0x24, 0x28}, + {0x25, 0x04}, + {0x26, 0x1e}, + {0x27, 0x04}, + {0x28, 0x40}, + {0x29, 0x04}, + {0x2a, 0xce}, + {0x2b, 0x02}, + {0x2c, 0x8a}, + //YUV + {0x12, 0x09}, + //RGB + //{0x12, 0x05}, + + {0x39, 0xd0}, + {0xcd, 0x13}, + {0xde, 0x7c}, + {0x3d, 0x08}, + {0x13, 0xff}, + {0x15, 0x42}, + {0xFF, 0xFF} +}; diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov5640_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov5640_config.c new file mode 100644 index 000000000..5e7a9aee3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov5640_config.c @@ -0,0 +1,4793 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Local Variables + *----------------------------------------------------------------------------*/ + +const struct ov_reg ov5640_yuv_vga[]={ + {0x3103, 0x11}, + {0x3008, 0x82}, + {0xFFFF, 0x05}, + {0x3008, 0x42}, + {0x3103, 0x03}, + {0x3017, 0xff}, + {0x3018, 0xff}, + + {0x3034, 0x1a}, + {0x3035, 0x11}, + {0x3036, 0x6a}, + {0x3037, 0x14}, + {0x3108, 0x01}, + {0x303b, 0x1c}, + {0x303d, 0x30}, + + {0x3630, 0x36}, + {0x3631, 0x0e}, + {0x3632, 0xe2}, + {0x3633, 0x12}, + {0x3621, 0xe0}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3905, 0x02}, + {0x3906, 0x10}, + {0x3901, 0x0a}, + {0x3731, 0x12}, + {0x3600, 0x08}, + {0x3601, 0x33}, + {0x302d, 0x60}, + {0x3620, 0x52}, + {0x371b, 0x20}, + {0x471c, 0x50}, + {0x3a13, 0x43}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3635, 0x13}, + {0x3636, 0x03}, + {0x3634, 0x40}, + {0x3622, 0x01}, + {0x3c01, 0x34}, + {0x3c04, 0x28}, + {0x3c05, 0x98}, + {0x3c06, 0x00}, + {0x3c07, 0x08}, + {0x3c08, 0x00}, + {0x3c09, 0x1c}, + {0x3c0a, 0x9c}, + {0x3c0b, 0x40}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x3f}, + {0x3806, 0x07}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3810, 0x00}, + {0x3811, 0x10}, + {0x3812, 0x00}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x64}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a08, 0x01}, + {0x3a09, 0x27}, + {0x3a0a, 0x00}, + {0x3a0b, 0xf6}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4001, 0x02}, + {0x4004, 0x02}, + {0x3000, 0x00}, + {0x3002, 0x1c}, + {0x3004, 0xff}, + {0x3006, 0xc3}, + {0x300e, 0x58}, + {0x302e, 0x00}, + {0x4300, 0x30}, + {0x501f, 0x00}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x440e, 0x00}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x4837, 0x22}, + {0x3824, 0x02}, + {0x5000, 0xa7}, + {0x5001, 0xa3}, + {0x5180, 0xff}, + {0x5181, 0xf2}, + {0x5182, 0x00}, + {0x5183, 0x14}, + {0x5184, 0x25}, + {0x5185, 0x24}, + {0x5186, 0x09}, + {0x5187, 0x09}, + {0x5188, 0x09}, + {0x5189, 0x75}, + {0x518a, 0x54}, + {0x518b, 0xe0}, + {0x518c, 0xb2}, + {0x518d, 0x42}, + {0x518e, 0x3d}, + {0x518f, 0x56}, + {0x5190, 0x46}, + {0x5191, 0xf8}, + {0x5192, 0x04}, + {0x5193, 0x70}, + {0x5194, 0xf0}, + {0x5195, 0xf0}, + {0x5196, 0x03}, + {0x5197, 0x01}, + {0x5198, 0x04}, + {0x5199, 0x12}, + {0x519a, 0x04}, + {0x519b, 0x00}, + {0x519c, 0x06}, + {0x519d, 0x82}, + {0x519e, 0x38}, + {0x5381, 0x1e}, + {0x5382, 0x5b}, + {0x5383, 0x08}, + {0x5384, 0x0a}, + {0x5385, 0x7e}, + {0x5386, 0x88}, + {0x5387, 0x7c}, + {0x5388, 0x6c}, + {0x5389, 0x10}, + {0x538a, 0x01}, + {0x538b, 0x98}, + {0x5300, 0x08}, + {0x5301, 0x30}, + {0x5302, 0x10}, + {0x5303, 0x00}, + {0x5304, 0x08}, + {0x5305, 0x30}, + {0x5306, 0x08}, + {0x5307, 0x16}, + {0x5309, 0x08}, + {0x530a, 0x30}, + {0x530b, 0x04}, + {0x530c, 0x06}, + {0x5480, 0x01}, + {0x5481, 0x08}, + {0x5482, 0x14}, + {0x5483, 0x28}, + {0x5484, 0x51}, + {0x5485, 0x65}, + {0x5486, 0x71}, + {0x5487, 0x7d}, + {0x5488, 0x87}, + {0x5489, 0x91}, + {0x548a, 0x9a}, + {0x548b, 0xaa}, + {0x548c, 0xb8}, + {0x548d, 0xcd}, + {0x548e, 0xdd}, + {0x548f, 0xea}, + {0x5490, 0x1d}, + {0x5580, 0x02}, + {0x5583, 0x40}, + {0x5584, 0x10}, + {0x5589, 0x10}, + {0x558a, 0x00}, + {0x558b, 0xf8}, + {0x5800, 0x23}, + {0x5801, 0x14}, + {0x5802, 0x0f}, + {0x5803, 0x0f}, + {0x5804, 0x12}, + {0x5805, 0x26}, + {0x5806, 0x0c}, + {0x5807, 0x08}, + {0x5808, 0x05}, + {0x5809, 0x05}, + {0x580a, 0x08}, + {0x580b, 0x0d}, + {0x580c, 0x08}, + {0x580d, 0x03}, + {0x580e, 0x00}, + {0x580f, 0x00}, + {0x5810, 0x03}, + {0x5811, 0x09}, + {0x5812, 0x07}, + {0x5813, 0x03}, + {0x5814, 0x00}, + {0x5815, 0x01}, + {0x5816, 0x03}, + {0x5817, 0x08}, + {0x5818, 0x0d}, + {0x5819, 0x08}, + {0x581a, 0x05}, + {0x581b, 0x06}, + {0x581c, 0x08}, + {0x581d, 0x0e}, + {0x581e, 0x29}, + {0x581f, 0x17}, + {0x5820, 0x11}, + {0x5821, 0x11}, + {0x5822, 0x15}, + {0x5823, 0x28}, + {0x5824, 0x46}, + {0x5825, 0x26}, + {0x5826, 0x08}, + {0x5827, 0x26}, + {0x5828, 0x64}, + {0x5829, 0x26}, + {0x582a, 0x24}, + {0x582b, 0x22}, + {0x582c, 0x24}, + {0x582d, 0x24}, + {0x582e, 0x06}, + {0x582f, 0x22}, + {0x5830, 0x40}, + {0x5831, 0x42}, + {0x5832, 0x24}, + {0x5833, 0x26}, + {0x5834, 0x24}, + {0x5835, 0x22}, + {0x5836, 0x22}, + {0x5837, 0x26}, + {0x5838, 0x44}, + {0x5839, 0x24}, + {0x583a, 0x26}, + {0x583b, 0x28}, + {0x583c, 0x42}, + {0x583d, 0xce}, + {0x5025, 0x00}, + {0x3a0f, 0x30}, + {0x3a10, 0x28}, + {0x3a1b, 0x30}, + {0x3a1e, 0x26}, + {0x3a11, 0x60}, + {0x3a1f, 0x14}, + {0x3008, 0x02}, + + {0x3503, 0x00}, + {0x3c07, 0x08}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3803, 0x04}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x62}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4004, 0x02}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x3824, 0x02}, + {0x5001, 0xa3}, + + {0xFF, 0xFF} +}; + +const struct ov_reg ov5640_yuv_sxga[]= { + {0x3103, 0x11}, + {0x3008, 0x82}, + {0xFFFF, 0x05}, + {0x3008, 0x42}, + {0x3103, 0x03}, + {0x3017, 0xff}, + {0x3018, 0xff}, + + + {0x3034, 0x1a}, + {0x3035, 0x11}, + {0x3036, 0x6a}, + {0x3037, 0x14}, + {0x3108, 0x01}, + {0x303b, 0x1c}, + {0x303d, 0x30}, + + {0x3630, 0x36}, + {0x3631, 0x0e}, + {0x3632, 0xe2}, + {0x3633, 0x12}, + {0x3621, 0xe0}, + {0x3704, 0xa0}, + {0x3703, 0x5a}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x370b, 0x60}, + {0x3705, 0x1a}, + {0x3905, 0x02}, + {0x3906, 0x10}, + {0x3901, 0x0a}, + {0x3731, 0x12}, + {0x3600, 0x08}, + {0x3601, 0x33}, + {0x302d, 0x60}, + {0x3620, 0x52}, + {0x371b, 0x20}, + {0x471c, 0x50}, + {0x3a13, 0x43}, + {0x3a18, 0x00}, + {0x3a19, 0xf8}, + {0x3635, 0x13}, + {0x3636, 0x03}, + {0x3634, 0x40}, + {0x3622, 0x01}, + {0x3c01, 0x34}, + {0x3c04, 0x28}, + {0x3c05, 0x98}, + {0x3c06, 0x00}, + {0x3c07, 0x08}, + {0x3c08, 0x00}, + {0x3c09, 0x1c}, + {0x3c0a, 0x9c}, + {0x3c0b, 0x40}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3800, 0x00}, + {0x3801, 0x00}, + {0x3802, 0x00}, + {0x3803, 0x04}, + {0x3804, 0x0a}, + {0x3805, 0x3f}, + {0x3806, 0x07}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3810, 0x00}, + {0x3811, 0x10}, + {0x3812, 0x00}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x64}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a08, 0x01}, + {0x3a09, 0x27}, + {0x3a0a, 0x00}, + {0x3a0b, 0xf6}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4001, 0x02}, + {0x4004, 0x02}, + {0x3000, 0x00}, + {0x3002, 0x1c}, + {0x3004, 0xff}, + {0x3006, 0xc3}, + {0x300e, 0x58}, + {0x302e, 0x00}, + {0x4300, 0x30}, + {0x501f, 0x00}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x440e, 0x00}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x4837, 0x22}, + {0x3824, 0x02}, + {0x5000, 0xa7}, + {0x5001, 0xa3}, + {0x5180, 0xff}, + {0x5181, 0xf2}, + {0x5182, 0x00}, + {0x5183, 0x14}, + {0x5184, 0x25}, + {0x5185, 0x24}, + {0x5186, 0x09}, + {0x5187, 0x09}, + {0x5188, 0x09}, + {0x5189, 0x75}, + {0x518a, 0x54}, + {0x518b, 0xe0}, + {0x518c, 0xb2}, + {0x518d, 0x42}, + {0x518e, 0x3d}, + {0x518f, 0x56}, + {0x5190, 0x46}, + {0x5191, 0xf8}, + {0x5192, 0x04}, + {0x5193, 0x70}, + {0x5194, 0xf0}, + {0x5195, 0xf0}, + {0x5196, 0x03}, + {0x5197, 0x01}, + {0x5198, 0x04}, + {0x5199, 0x12}, + {0x519a, 0x04}, + {0x519b, 0x00}, + {0x519c, 0x06}, + {0x519d, 0x82}, + {0x519e, 0x38}, + {0x5381, 0x1e}, + {0x5382, 0x5b}, + {0x5383, 0x08}, + {0x5384, 0x0a}, + {0x5385, 0x7e}, + {0x5386, 0x88}, + {0x5387, 0x7c}, + {0x5388, 0x6c}, + {0x5389, 0x10}, + {0x538a, 0x01}, + {0x538b, 0x98}, + {0x5300, 0x08}, + {0x5301, 0x30}, + {0x5302, 0x10}, + {0x5303, 0x00}, + {0x5304, 0x08}, + {0x5305, 0x30}, + {0x5306, 0x08}, + {0x5307, 0x16}, + {0x5309, 0x08}, + {0x530a, 0x30}, + {0x530b, 0x04}, + {0x530c, 0x06}, + {0x5480, 0x01}, + {0x5481, 0x08}, + {0x5482, 0x14}, + {0x5483, 0x28}, + {0x5484, 0x51}, + {0x5485, 0x65}, + {0x5486, 0x71}, + {0x5487, 0x7d}, + {0x5488, 0x87}, + {0x5489, 0x91}, + {0x548a, 0x9a}, + {0x548b, 0xaa}, + {0x548c, 0xb8}, + {0x548d, 0xcd}, + {0x548e, 0xdd}, + {0x548f, 0xea}, + {0x5490, 0x1d}, + {0x5580, 0x02}, + {0x5583, 0x40}, + {0x5584, 0x10}, + {0x5589, 0x10}, + {0x558a, 0x00}, + {0x558b, 0xf8}, + {0x5800, 0x23}, + {0x5801, 0x14}, + {0x5802, 0x0f}, + {0x5803, 0x0f}, + {0x5804, 0x12}, + {0x5805, 0x26}, + {0x5806, 0x0c}, + {0x5807, 0x08}, + {0x5808, 0x05}, + {0x5809, 0x05}, + {0x580a, 0x08}, + {0x580b, 0x0d}, + {0x580c, 0x08}, + {0x580d, 0x03}, + {0x580e, 0x00}, + {0x580f, 0x00}, + {0x5810, 0x03}, + {0x5811, 0x09}, + {0x5812, 0x07}, + {0x5813, 0x03}, + {0x5814, 0x00}, + {0x5815, 0x01}, + {0x5816, 0x03}, + {0x5817, 0x08}, + {0x5818, 0x0d}, + {0x5819, 0x08}, + {0x581a, 0x05}, + {0x581b, 0x06}, + {0x581c, 0x08}, + {0x581d, 0x0e}, + {0x581e, 0x29}, + {0x581f, 0x17}, + {0x5820, 0x11}, + {0x5821, 0x11}, + {0x5822, 0x15}, + {0x5823, 0x28}, + {0x5824, 0x46}, + {0x5825, 0x26}, + {0x5826, 0x08}, + {0x5827, 0x26}, + {0x5828, 0x64}, + {0x5829, 0x26}, + {0x582a, 0x24}, + {0x582b, 0x22}, + {0x582c, 0x24}, + {0x582d, 0x24}, + {0x582e, 0x06}, + {0x582f, 0x22}, + {0x5830, 0x40}, + {0x5831, 0x42}, + {0x5832, 0x24}, + {0x5833, 0x26}, + {0x5834, 0x24}, + {0x5835, 0x22}, + {0x5836, 0x22}, + {0x5837, 0x26}, + {0x5838, 0x44}, + {0x5839, 0x24}, + {0x583a, 0x26}, + {0x583b, 0x28}, + {0x583c, 0x42}, + {0x583d, 0xce}, + {0x5025, 0x00}, + {0x3a0f, 0x30}, + {0x3a10, 0x28}, + {0x3a1b, 0x30}, + {0x3a1e, 0x26}, + {0x3a11, 0x60}, + {0x3a1f, 0x14}, + {0x3008, 0x02}, + + {0x3503, 0x00}, + {0x3c07, 0x08}, + {0x3820, 0x41}, + {0x3821, 0x07}, + {0x3814, 0x31}, + {0x3815, 0x31}, + {0x3803, 0x04}, + {0x3807, 0x9b}, + {0x3808, 0x02}, + {0x3809, 0x80}, + {0x380a, 0x01}, + {0x380b, 0xe0}, + {0x380c, 0x07}, + {0x380d, 0x68}, + {0x380e, 0x03}, + {0x380f, 0xd8}, + {0x3813, 0x06}, + {0x3618, 0x00}, + {0x3612, 0x29}, + {0x3708, 0x62}, + {0x3709, 0x52}, + {0x370c, 0x03}, + {0x3a02, 0x03}, + {0x3a03, 0xd8}, + {0x3a0e, 0x03}, + {0x3a0d, 0x04}, + {0x3a14, 0x03}, + {0x3a15, 0xd8}, + {0x4004, 0x02}, + {0x4713, 0x03}, + {0x4407, 0x04}, + {0x460b, 0x35}, + {0x460c, 0x22}, + {0x3824, 0x02}, + {0x5001, 0xa3}, + + {0x3c07,0x08}, + {0x3820,0x41}, + {0x3821,0x07}, + {0x3800,0x00}, + {0x3801,0x00}, + {0x3802,0x00}, + {0x3803,0x04}, + {0x3804,0x0a}, + {0x3805,0x3f}, + {0x3806,0x07}, + {0x3807,0x9b}, + {0x3808,0x05}, + {0x3809,0x00}, + {0x380a,0x02}, + {0x380b,0xd0}, + {0x380c,0x07}, + {0x380d,0x68}, + {0x380e,0x03}, + {0x380f,0xd8}, + {0x3810,0x00}, + {0x3811,0x10}, + {0x3812,0x00}, + {0x3813,0x7e}, + {0x3814,0x31}, + {0x3815,0x31}, + {0x3618,0x00}, + {0x3612,0x29}, + {0x3709,0x52}, + {0x370c,0x03}, + {0x3a02,0x0b}, + {0x3a03,0x88}, + {0x3a14,0x0b}, + {0x3a15,0x88}, + {0x4004,0x02}, + {0x3002,0x1c}, + {0x3006,0xc3}, + {0x4713,0x03}, + {0x4407,0x04}, + {0x460b,0x35}, + {0x460c,0x20}, + {0x4837,0x22}, + {0x3824,0x02}, + {0x5001,0xa3}, + {0x3034,0x1a}, + {0x3035,0x11}, + {0x3036,0x46}, + {0x3037,0x13}, + {0x3503,0x03}, + {0xFF, 0xFF} +}; + +const struct ov_reg ov5640_afc[]={ + {0x3000 ,0x20 }, + {0x8000 ,0x02 }, + {0x8001 ,0x0f }, + {0x8002 ,0xe0 }, + {0x8003 ,0x02 }, + {0x8004 ,0x09 }, + {0x8005 ,0x28 }, + {0x8006 ,0xc2 }, + {0x8007 ,0x01 }, + {0x8008 ,0x22 }, + {0x8009 ,0x22 }, + {0x800a ,0x00 }, + {0x800b ,0x02 }, + {0x800c ,0x0d }, + {0x800d ,0xea }, + {0x800e ,0x30 }, + {0x800f ,0x01 }, + {0x8010 ,0x03 }, + {0x8011 ,0x02 }, + {0x8012 ,0x02 }, + {0x8013 ,0xa6 }, + {0x8014 ,0x30 }, + {0x8015 ,0x02 }, + {0x8016 ,0x03 }, + {0x8017 ,0x02 }, + {0x8018 ,0x02 }, + {0x8019 ,0xa6 }, + {0x801a ,0x90 }, + {0x801b ,0x51 }, + {0x801c ,0xa5 }, + {0x801d ,0xe0 }, + {0x801e ,0x78 }, + {0x801f ,0x93 }, + {0x8020 ,0xf6 }, + {0x8021 ,0xa3 }, + {0x8022 ,0xe0 }, + {0x8023 ,0x08 }, + {0x8024 ,0xf6 }, + {0x8025 ,0xa3 }, + {0x8026 ,0xe0 }, + {0x8027 ,0x08 }, + {0x8028 ,0xf6 }, + {0x8029 ,0xe5 }, + {0x802a ,0x1f }, + {0x802b ,0x70 }, + {0x802c ,0x4f }, + {0x802d ,0x75 }, + {0x802e ,0x1e }, + {0x802f ,0x20 }, + {0x8030 ,0xd2 }, + {0x8031 ,0x35 }, + {0x8032 ,0xd3 }, + {0x8033 ,0x78 }, + {0x8034 ,0x4f }, + {0x8035 ,0xe6 }, + {0x8036 ,0x94 }, + {0x8037 ,0x00 }, + {0x8038 ,0x18 }, + {0x8039 ,0xe6 }, + {0x803a ,0x94 }, + {0x803b ,0x00 }, + {0x803c ,0x40 }, + {0x803d ,0x07 }, + {0x803e ,0xe6 }, + {0x803f ,0xfe }, + {0x8040 ,0x08 }, + {0x8041 ,0xe6 }, + {0x8042 ,0xff }, + {0x8043 ,0x80 }, + {0x8044 ,0x03 }, + {0x8045 ,0x12 }, + {0x8046 ,0x0c }, + {0x8047 ,0x67 }, + {0x8048 ,0x78 }, + {0x8049 ,0x7e }, + {0x804a ,0xa6 }, + {0x804b ,0x06 }, + {0x804c ,0x08 }, + {0x804d ,0xa6 }, + {0x804e ,0x07 }, + {0x804f ,0x78 }, + {0x8050 ,0x8b }, + {0x8051 ,0xa6 }, + {0x8052 ,0x09 }, + {0x8053 ,0x18 }, + {0x8054 ,0x76 }, + {0x8055 ,0x01 }, + {0x8056 ,0x12 }, + {0x8057 ,0x0c }, + {0x8058 ,0x67 }, + {0x8059 ,0x78 }, + {0x805a ,0x4e }, + {0x805b ,0xa6 }, + {0x805c ,0x06 }, + {0x805d ,0x08 }, + {0x805e ,0xa6 }, + {0x805f ,0x07 }, + {0x8060 ,0x78 }, + {0x8061 ,0x8b }, + {0x8062 ,0xe6 }, + {0x8063 ,0x78 }, + {0x8064 ,0x6e }, + {0x8065 ,0xf6 }, + {0x8066 ,0x75 }, + {0x8067 ,0x1f }, + {0x8068 ,0x01 }, + {0x8069 ,0x78 }, + {0x806a ,0x93 }, + {0x806b ,0xe6 }, + {0x806c ,0x78 }, + {0x806d ,0x90 }, + {0x806e ,0xf6 }, + {0x806f ,0x78 }, + {0x8070 ,0x94 }, + {0x8071 ,0xe6 }, + {0x8072 ,0x78 }, + {0x8073 ,0x91 }, + {0x8074 ,0xf6 }, + {0x8075 ,0x78 }, + {0x8076 ,0x95 }, + {0x8077 ,0xe6 }, + {0x8078 ,0x78 }, + {0x8079 ,0x92 }, + {0x807a ,0xf6 }, + {0x807b ,0x22 }, + {0x807c ,0x79 }, + {0x807d ,0x90 }, + {0x807e ,0xe7 }, + {0x807f ,0xd3 }, + {0x8080 ,0x78 }, + {0x8081 ,0x93 }, + {0x8082 ,0x96 }, + {0x8083 ,0x40 }, + {0x8084 ,0x05 }, + {0x8085 ,0xe7 }, + {0x8086 ,0x96 }, + {0x8087 ,0xff }, + {0x8088 ,0x80 }, + {0x8089 ,0x08 }, + {0x808a ,0xc3 }, + {0x808b ,0x79 }, + {0x808c ,0x93 }, + {0x808d ,0xe7 }, + {0x808e ,0x78 }, + {0x808f ,0x90 }, + {0x8090 ,0x96 }, + {0x8091 ,0xff }, + {0x8092 ,0x78 }, + {0x8093 ,0x88 }, + {0x8094 ,0x76 }, + {0x8095 ,0x00 }, + {0x8096 ,0x08 }, + {0x8097 ,0xa6 }, + {0x8098 ,0x07 }, + {0x8099 ,0x79 }, + {0x809a ,0x91 }, + {0x809b ,0xe7 }, + {0x809c ,0xd3 }, + {0x809d ,0x78 }, + {0x809e ,0x94 }, + {0x809f ,0x96 }, + {0x80a0 ,0x40 }, + {0x80a1 ,0x05 }, + {0x80a2 ,0xe7 }, + {0x80a3 ,0x96 }, + {0x80a4 ,0xff }, + {0x80a5 ,0x80 }, + {0x80a6 ,0x08 }, + {0x80a7 ,0xc3 }, + {0x80a8 ,0x79 }, + {0x80a9 ,0x94 }, + {0x80aa ,0xe7 }, + {0x80ab ,0x78 }, + {0x80ac ,0x91 }, + {0x80ad ,0x96 }, + {0x80ae ,0xff }, + {0x80af ,0x12 }, + {0x80b0 ,0x0c }, + {0x80b1 ,0xb0 }, + {0x80b2 ,0x79 }, + {0x80b3 ,0x92 }, + {0x80b4 ,0xe7 }, + {0x80b5 ,0xd3 }, + {0x80b6 ,0x78 }, + {0x80b7 ,0x95 }, + {0x80b8 ,0x96 }, + {0x80b9 ,0x40 }, + {0x80ba ,0x05 }, + {0x80bb ,0xe7 }, + {0x80bc ,0x96 }, + {0x80bd ,0xff }, + {0x80be ,0x80 }, + {0x80bf ,0x08 }, + {0x80c0 ,0xc3 }, + {0x80c1 ,0x79 }, + {0x80c2 ,0x95 }, + {0x80c3 ,0xe7 }, + {0x80c4 ,0x78 }, + {0x80c5 ,0x92 }, + {0x80c6 ,0x96 }, + {0x80c7 ,0xff }, + {0x80c8 ,0x12 }, + {0x80c9 ,0x0c }, + {0x80ca ,0xb0 }, + {0x80cb ,0x12 }, + {0x80cc ,0x0c }, + {0x80cd ,0x67 }, + {0x80ce ,0x78 }, + {0x80cf ,0x8a }, + {0x80d0 ,0xe6 }, + {0x80d1 ,0x25 }, + {0x80d2 ,0xe0 }, + {0x80d3 ,0x24 }, + {0x80d4 ,0x4e }, + {0x80d5 ,0xf8 }, + {0x80d6 ,0xa6 }, + {0x80d7 ,0x06 }, + {0x80d8 ,0x08 }, + {0x80d9 ,0xa6 }, + {0x80da ,0x07 }, + {0x80db ,0x78 }, + {0x80dc ,0x8a }, + {0x80dd ,0xe6 }, + {0x80de ,0x24 }, + {0x80df ,0x6e }, + {0x80e0 ,0xf8 }, + {0x80e1 ,0xa6 }, + {0x80e2 ,0x09 }, + {0x80e3 ,0x90 }, + {0x80e4 ,0x0e }, + {0x80e5 ,0x93 }, + {0x80e6 ,0xe4 }, + {0x80e7 ,0x93 }, + {0x80e8 ,0x24 }, + {0x80e9 ,0xff }, + {0x80ea ,0xff }, + {0x80eb ,0xe4 }, + {0x80ec ,0x34 }, + {0x80ed ,0xff }, + {0x80ee ,0xfe }, + {0x80ef ,0x78 }, + {0x80f0 ,0x8a }, + {0x80f1 ,0xe6 }, + {0x80f2 ,0x24 }, + {0x80f3 ,0x01 }, + {0x80f4 ,0xfd }, + {0x80f5 ,0xe4 }, + {0x80f6 ,0x33 }, + {0x80f7 ,0xfc }, + {0x80f8 ,0xd3 }, + {0x80f9 ,0xed }, + {0x80fa ,0x9f }, + {0x80fb ,0xee }, + {0x80fc ,0x64 }, + {0x80fd ,0x80 }, + {0x80fe ,0xf8 }, + {0x80ff ,0xec }, + {0x8100 ,0x64 }, + {0x8101 ,0x80 }, + {0x8102 ,0x98 }, + {0x8103 ,0x40 }, + {0x8104 ,0x04 }, + {0x8105 ,0x7f }, + {0x8106 ,0x00 }, + {0x8107 ,0x80 }, + {0x8108 ,0x05 }, + {0x8109 ,0x78 }, + {0x810a ,0x8a }, + {0x810b ,0xe6 }, + {0x810c ,0x04 }, + {0x810d ,0xff }, + {0x810e ,0x78 }, + {0x810f ,0x8a }, + {0x8110 ,0xa6 }, + {0x8111 ,0x07 }, + {0x8112 ,0xe5 }, + {0x8113 ,0x1f }, + {0x8114 ,0xb4 }, + {0x8115 ,0x01 }, + {0x8116 ,0x0a }, + {0x8117 ,0xe6 }, + {0x8118 ,0x60 }, + {0x8119 ,0x03 }, + {0x811a ,0x02 }, + {0x811b ,0x02 }, + {0x811c ,0xa6 }, + {0x811d ,0x75 }, + {0x811e ,0x1f }, + {0x811f ,0x02 }, + {0x8120 ,0x22 }, + {0x8121 ,0x78 }, + {0x8122 ,0x4e }, + {0x8123 ,0xe6 }, + {0x8124 ,0xfe }, + {0x8125 ,0x08 }, + {0x8126 ,0xe6 }, + {0x8127 ,0xff }, + {0x8128 ,0x78 }, + {0x8129 ,0x80 }, + {0x812a ,0xa6 }, + {0x812b ,0x06 }, + {0x812c ,0x08 }, + {0x812d ,0xa6 }, + {0x812e ,0x07 }, + {0x812f ,0x78 }, + {0x8130 ,0x4e }, + {0x8131 ,0xe6 }, + {0x8132 ,0xfe }, + {0x8133 ,0x08 }, + {0x8134 ,0xe6 }, + {0x8135 ,0xff }, + {0x8136 ,0x78 }, + {0x8137 ,0x82 }, + {0x8138 ,0xa6 }, + {0x8139 ,0x06 }, + {0x813a ,0x08 }, + {0x813b ,0xa6 }, + {0x813c ,0x07 }, + {0x813d ,0x78 }, + {0x813e ,0x6e }, + {0x813f ,0xe6 }, + {0x8140 ,0x78 }, + {0x8141 ,0x8c }, + {0x8142 ,0xf6 }, + {0x8143 ,0x78 }, + {0x8144 ,0x6e }, + {0x8145 ,0xe6 }, + {0x8146 ,0x78 }, + {0x8147 ,0x8d }, + {0x8148 ,0xf6 }, + {0x8149 ,0x7f }, + {0x814a ,0x01 }, + {0x814b ,0x90 }, + {0x814c ,0x0e }, + {0x814d ,0x93 }, + {0x814e ,0xe4 }, + {0x814f ,0x93 }, + {0x8150 ,0xfe }, + {0x8151 ,0xef }, + {0x8152 ,0xc3 }, + {0x8153 ,0x9e }, + {0x8154 ,0x50 }, + {0x8155 ,0x5f }, + {0x8156 ,0xef }, + {0x8157 ,0x25 }, + {0x8158 ,0xe0 }, + {0x8159 ,0x24 }, + {0x815a ,0x4f }, + {0x815b ,0xf9 }, + {0x815c ,0xc3 }, + {0x815d ,0x78 }, + {0x815e ,0x81 }, + {0x815f ,0xe6 }, + {0x8160 ,0x97 }, + {0x8161 ,0x18 }, + {0x8162 ,0xe6 }, + {0x8163 ,0x19 }, + {0x8164 ,0x97 }, + {0x8165 ,0x50 }, + {0x8166 ,0x0a }, + {0x8167 ,0x12 }, + {0x8168 ,0x0c }, + {0x8169 ,0x98 }, + {0x816a ,0x78 }, + {0x816b ,0x80 }, + {0x816c ,0xa6 }, + {0x816d ,0x04 }, + {0x816e ,0x08 }, + {0x816f ,0xa6 }, + {0x8170 ,0x05 }, + {0x8171 ,0x74 }, + {0x8172 ,0x6e }, + {0x8173 ,0x2f }, + {0x8174 ,0xf9 }, + {0x8175 ,0x78 }, + {0x8176 ,0x8c }, + {0x8177 ,0xe6 }, + {0x8178 ,0xc3 }, + {0x8179 ,0x97 }, + {0x817a ,0x50 }, + {0x817b ,0x08 }, + {0x817c ,0x74 }, + {0x817d ,0x6e }, + {0x817e ,0x2f }, + {0x817f ,0xf8 }, + {0x8180 ,0xe6 }, + {0x8181 ,0x78 }, + {0x8182 ,0x8c }, + {0x8183 ,0xf6 }, + {0x8184 ,0xef }, + {0x8185 ,0x25 }, + {0x8186 ,0xe0 }, + {0x8187 ,0x24 }, + {0x8188 ,0x4f }, + {0x8189 ,0xf9 }, + {0x818a ,0xd3 }, + {0x818b ,0x78 }, + {0x818c ,0x83 }, + {0x818d ,0xe6 }, + {0x818e ,0x97 }, + {0x818f ,0x18 }, + {0x8190 ,0xe6 }, + {0x8191 ,0x19 }, + {0x8192 ,0x97 }, + {0x8193 ,0x40 }, + {0x8194 ,0x0a }, + {0x8195 ,0x12 }, + {0x8196 ,0x0c }, + {0x8197 ,0x98 }, + {0x8198 ,0x78 }, + {0x8199 ,0x82 }, + {0x819a ,0xa6 }, + {0x819b ,0x04 }, + {0x819c ,0x08 }, + {0x819d ,0xa6 }, + {0x819e ,0x05 }, + {0x819f ,0x74 }, + {0x81a0 ,0x6e }, + {0x81a1 ,0x2f }, + {0x81a2 ,0xf9 }, + {0x81a3 ,0x78 }, + {0x81a4 ,0x8d }, + {0x81a5 ,0xe6 }, + {0x81a6 ,0xd3 }, + {0x81a7 ,0x97 }, + {0x81a8 ,0x40 }, + {0x81a9 ,0x08 }, + {0x81aa ,0x74 }, + {0x81ab ,0x6e }, + {0x81ac ,0x2f }, + {0x81ad ,0xf8 }, + {0x81ae ,0xe6 }, + {0x81af ,0x78 }, + {0x81b0 ,0x8d }, + {0x81b1 ,0xf6 }, + {0x81b2 ,0x0f }, + {0x81b3 ,0x80 }, + {0x81b4 ,0x96 }, + {0x81b5 ,0xc3 }, + {0x81b6 ,0x79 }, + {0x81b7 ,0x81 }, + {0x81b8 ,0xe7 }, + {0x81b9 ,0x78 }, + {0x81ba ,0x83 }, + {0x81bb ,0x96 }, + {0x81bc ,0xff }, + {0x81bd ,0x19 }, + {0x81be ,0xe7 }, + {0x81bf ,0x18 }, + {0x81c0 ,0x96 }, + {0x81c1 ,0x78 }, + {0x81c2 ,0x84 }, + {0x81c3 ,0xf6 }, + {0x81c4 ,0x08 }, + {0x81c5 ,0xa6 }, + {0x81c6 ,0x07 }, + {0x81c7 ,0xc3 }, + {0x81c8 ,0x79 }, + {0x81c9 ,0x8c }, + {0x81ca ,0xe7 }, + {0x81cb ,0x78 }, + {0x81cc ,0x8d }, + {0x81cd ,0x96 }, + {0x81ce ,0x08 }, + {0x81cf ,0xf6 }, + {0x81d0 ,0x12 }, + {0x81d1 ,0x0c }, + {0x81d2 ,0xa4 }, + {0x81d3 ,0x40 }, + {0x81d4 ,0x05 }, + {0x81d5 ,0x09 }, + {0x81d6 ,0xe7 }, + {0x81d7 ,0x08 }, + {0x81d8 ,0x80 }, + {0x81d9 ,0x06 }, + {0x81da ,0xc3 }, + {0x81db ,0x79 }, + {0x81dc ,0x7f }, + {0x81dd ,0xe7 }, + {0x81de ,0x78 }, + {0x81df ,0x81 }, + {0x81e0 ,0x96 }, + {0x81e1 ,0xff }, + {0x81e2 ,0x19 }, + {0x81e3 ,0xe7 }, + {0x81e4 ,0x18 }, + {0x81e5 ,0x96 }, + {0x81e6 ,0xfe }, + {0x81e7 ,0x78 }, + {0x81e8 ,0x86 }, + {0x81e9 ,0xa6 }, + {0x81ea ,0x06 }, + {0x81eb ,0x08 }, + {0x81ec ,0xa6 }, + {0x81ed ,0x07 }, + {0x81ee ,0x79 }, + {0x81ef ,0x8c }, + {0x81f0 ,0xe7 }, + {0x81f1 ,0xd3 }, + {0x81f2 ,0x78 }, + {0x81f3 ,0x8b }, + {0x81f4 ,0x96 }, + {0x81f5 ,0x40 }, + {0x81f6 ,0x05 }, + {0x81f7 ,0xe7 }, + {0x81f8 ,0x96 }, + {0x81f9 ,0xff }, + {0x81fa ,0x80 }, + {0x81fb ,0x08 }, + {0x81fc ,0xc3 }, + {0x81fd ,0x79 }, + {0x81fe ,0x8b }, + {0x81ff ,0xe7 }, + {0x8200 ,0x78 }, + {0x8201 ,0x8c }, + {0x8202 ,0x96 }, + {0x8203 ,0xff }, + {0x8204 ,0x78 }, + {0x8205 ,0x8f }, + {0x8206 ,0xa6 }, + {0x8207 ,0x07 }, + {0x8208 ,0xe5 }, + {0x8209 ,0x1f }, + {0x820a ,0x64 }, + {0x820b ,0x02 }, + {0x820c ,0x60 }, + {0x820d ,0x03 }, + {0x820e ,0x02 }, + {0x820f ,0x02 }, + {0x8210 ,0x92 }, + {0x8211 ,0x90 }, + {0x8212 ,0x0e }, + {0x8213 ,0x91 }, + {0x8214 ,0x93 }, + {0x8215 ,0xff }, + {0x8216 ,0x18 }, + {0x8217 ,0xe6 }, + {0x8218 ,0xc3 }, + {0x8219 ,0x9f }, + {0x821a ,0x40 }, + {0x821b ,0x03 }, + {0x821c ,0x02 }, + {0x821d ,0x02 }, + {0x821e ,0xa6 }, + {0x821f ,0x78 }, + {0x8220 ,0x84 }, + {0x8221 ,0x12 }, + {0x8222 ,0x0c }, + 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,0x2c }, + {0x8f78 ,0x12 }, + {0x8f79 ,0x0f }, + {0x8f7a ,0xc4 }, + {0x8f7b ,0xe0 }, + {0x8f7c ,0xf5 }, + {0x8f7d ,0x2d }, + {0x8f7e ,0x80 }, + {0x8f7f ,0x0c }, + {0x8f80 ,0x12 }, + {0x8f81 ,0x0f }, + {0x8f82 ,0xc7 }, + {0x8f83 ,0xe5 }, + {0x8f84 ,0x30 }, + {0x8f85 ,0xf0 }, + {0x8f86 ,0x12 }, + {0x8f87 ,0x0f }, + {0x8f88 ,0xc4 }, + {0x8f89 ,0xe5 }, + {0x8f8a ,0x31 }, + {0x8f8b ,0xf0 }, + {0x8f8c ,0xa2 }, + {0x8f8d ,0x32 }, + {0x8f8e ,0x92 }, + {0x8f8f ,0xaf }, + {0x8f90 ,0x22 }, + {0x8f91 ,0x8f }, + {0x8f92 ,0x3b }, + {0x8f93 ,0x8e }, + {0x8f94 ,0x3a }, + {0x8f95 ,0x8d }, + {0x8f96 ,0x39 }, + {0x8f97 ,0x8c }, + {0x8f98 ,0x38 }, + {0x8f99 ,0x22 }, + {0x8f9a ,0x12 }, + {0x8f9b ,0x06 }, + {0x8f9c ,0xdd }, + {0x8f9d ,0x8f }, + {0x8f9e ,0x31 }, + {0x8f9f ,0x8e }, + {0x8fa0 ,0x30 }, + {0x8fa1 ,0x8d }, + {0x8fa2 ,0x2f }, + {0x8fa3 ,0x8c }, + {0x8fa4 ,0x2e }, + {0x8fa5 ,0x22 }, + {0x8fa6 ,0x93 }, + {0x8fa7 ,0xf9 }, + {0x8fa8 ,0xf8 }, + {0x8fa9 ,0x02 }, + {0x8faa ,0x06 }, + {0x8fab ,0xca }, + {0x8fac ,0x12 }, + {0x8fad ,0x06 }, + {0x8fae ,0xca }, + {0x8faf ,0xe5 }, + {0x8fb0 ,0x40 }, + {0x8fb1 ,0x2f }, + {0x8fb2 ,0xf5 }, + {0x8fb3 ,0x40 }, + {0x8fb4 ,0xe5 }, + {0x8fb5 ,0x3f }, + {0x8fb6 ,0x3e }, + {0x8fb7 ,0xf5 }, + {0x8fb8 ,0x3f }, + {0x8fb9 ,0xe5 }, + {0x8fba ,0x3e }, + {0x8fbb ,0x3d }, + {0x8fbc ,0xf5 }, + {0x8fbd ,0x3e }, + {0x8fbe ,0xe5 }, + {0x8fbf ,0x3d }, + {0x8fc0 ,0x3c }, + {0x8fc1 ,0xf5 }, + {0x8fc2 ,0x3d }, + {0x8fc3 ,0x22 }, + {0x8fc4 ,0x90 }, + {0x8fc5 ,0x0e }, + {0x8fc6 ,0x5f }, + {0x8fc7 ,0xe4 }, + {0x8fc8 ,0x93 }, + {0x8fc9 ,0xfe }, + {0x8fca ,0x74 }, + {0x8fcb ,0x01 }, + {0x8fcc ,0x93 }, + {0x8fcd ,0xf5 }, + {0x8fce ,0x82 }, + {0x8fcf ,0x8e }, + {0x8fd0 ,0x83 }, + {0x8fd1 ,0x22 }, + {0x8fd2 ,0xd2 }, + {0x8fd3 ,0x01 }, + {0x8fd4 ,0xc2 }, + {0x8fd5 ,0x02 }, + {0x8fd6 ,0xe4 }, + {0x8fd7 ,0xf5 }, + {0x8fd8 ,0x1f }, + {0x8fd9 ,0xf5 }, + {0x8fda ,0x1e }, + {0x8fdb ,0xd2 }, + {0x8fdc ,0x35 }, + {0x8fdd ,0xd2 }, + {0x8fde ,0x33 }, + {0x8fdf ,0x22 }, + {0x8fe0 ,0x78 }, + {0x8fe1 ,0x7f }, + {0x8fe2 ,0xe4 }, + {0x8fe3 ,0xf6 }, + {0x8fe4 ,0xd8 }, + {0x8fe5 ,0xfd }, + {0x8fe6 ,0x75 }, + {0x8fe7 ,0x81 }, + {0x8fe8 ,0xcd }, + {0x8fe9 ,0x02 }, + {0x8fea ,0x0c }, + {0x8feb ,0xc4 }, + {0x8fec ,0x8f }, + {0x8fed ,0x82 }, + {0x8fee ,0x8e }, + {0x8fef ,0x83 }, + {0x8ff0 ,0x75 }, + {0x8ff1 ,0xf0 }, + {0x8ff2 ,0x04 }, + {0x8ff3 ,0xed }, + {0x8ff4 ,0x02 }, + {0x8ff5 ,0x07 }, + {0x8ff6 ,0x06 }, + {0x3022 ,0x00 }, + {0x3023 ,0x00 }, + {0x3024 ,0x00 }, + {0x3025 ,0x00 }, + {0x3026 ,0x00 }, + {0x3027 ,0x00 }, + {0x3028 ,0x00 }, + {0x3029 ,0x7F }, + {0x3000 ,0x00 }, + {0x3004, 0xff }, + {0x3005, 0xF7 }, + + {0xFF, 0xFF} +}; diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov7740_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov7740_config.c new file mode 100644 index 000000000..e2a742ce9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov7740_config.c @@ -0,0 +1,1198 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +#include "include/ov_7740.h" +#include "board.h" + + +#ifdef __cplusplus +extern "C" { +#endif + +#define FRAMERATE 30 + +/** + * \defgroup ov7740_CMOS_image_sensor_registers_group + * + * This file defines several arrays. Each of them contain address of ov7740 + * register and corresponding value for a specific configuration. + * There are seven different configuration: + * - OV7740_VGA_YUV422[] + * - OV7740_QVGA_YUV422[] + * - OV7740_QQVGA_YUV422[] + * - OV7740_QVGA_RGB888[] + * - OV7740_QQVGA_RGB888[] + * - OV7740_TEST_PATTERN[] + + * These values have been obtained from OV7740 datasheet and OmniVision + * Developer Kit. + * @{ + */ + +/*------------------------------------------------------------------------------ + * Local Variables + *----------------------------------------------------------------------------*/ + + /** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_VGA_YUV422 configuration: + * - 640*4800 pixel by picture (VGA) + * - pixel data in YUV422 format (Y1, U, Y2, V) + */ +const struct ov_reg OV7740_VGA_YUV422[] = { + + {0x12, 0x80}, + /* flag for soft reset delay */ + {0x55 ,PLL_DIV_DEFAULT}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz ((PLL/2)/16) (PLL=792)*/ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz(MCK_132)/8 */ + /**************************************************************/ + + {OV7740_CLK, FRAME_RATE_30}, + /**************************************************************/ + + {0x12 ,0x00}, + {0xd5 ,0x10}, + {0x0c, 0x12}, + {0x0d ,0x34}, + {0x17 ,0x25}, + {0x18 ,0xa0}, + {0x19 ,0x03}, + {0x1a ,0xf0}, + {0x1b ,0x89}, + {0x22 ,0x03}, + {0x29 ,0x18}, + {0x2b ,0xf8}, + {0x2c ,0x01}, + {0x31 ,0xa0}, + {0x32 ,0xf0}, + {0x33 ,0xc4}, + {0x35 ,0x05}, + {0x36 ,0x3f}, + + {0x04 ,0x60}, + {0x27 ,0x80}, + {0x3d ,0x0f}, + {0x3e ,0x80}, + {0x3f ,0x40}, + {0x40 ,0x7f}, + {0x41 ,0x6a}, + {0x42 ,0x29}, + {0x44 ,0x22}, + {0x45 ,0x41}, + {0x47 ,0x02}, + {0x49 ,0x64}, + {0x4a ,0xa1}, + {0x4b ,0x40}, + {0x4c ,0x1a}, + {0x4d ,0x50}, + {0x4e ,0x13}, + {0x64 ,0x00}, + {0x67 ,0x88}, + {0x68 ,0x1a}, + + {0x14 ,0x28}, //;38/28/18 for 16/8/4x gain ceiling + {0x24 ,0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + {0x50, 0x97}, // ;12e/97/4b/25 for 60/30/15/7.5fps, 50Hz + + /*********************************/ + /* Normal Mode / No test pattern */ + {0x38, 0x14}, + /*********************************/ + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x84 ,0x70}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + {0x0f ,0x1d}, + {0x0f ,0x1f}, + {0xFF, 0xFF} +}; + + /** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_QVGA_YUV422 configuration: + * - 320*240 pixel by picture (QVGA) + * - pixel data in YUV422 format (Y1, U, Y2, V) + + */ +const struct ov_reg OV7740_QVGA_YUV422[] = { + + {0x12, 0x80}, + /* flag for soft reset delay */ + {0x55 ,PLL_DIV_7_MCK_132}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz */ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz (MCK=132/8) */ + /**************************************************************/ + {OV7740_CLK, FRAME_RATE_30}, + /**************************************************************/ + + {0x12 ,0x00}, + {0xd5 ,0x10}, + {0x0c ,0x12}, + {0x0d ,0x34}, + {0x17 ,0x25}, + {0x18 ,0xa0}, + {0x19 ,0x03}, + {0x1a ,0xf0}, + {0x1b ,0x89}, //;was 81 + {0x22 ,0x03}, //;new + {0x29 ,0x18}, //;was 17 + {0x2b ,0xf8}, + {0x2c ,0x01}, + {0x31 ,0xa0}, + {0x32 ,0xf0}, + {0x33 ,0xc4}, //;was44 + {0x35 ,0x05}, //;new + {0x36 ,0x3f}, + + {0x04 ,0x60}, + {0x27 ,0x80}, //;delete "42 3a b4" + {0x3d ,0x0f}, + {0x3e ,0x80}, + {0x3f ,0x40}, + {0x40 ,0x7f}, + {0x41 ,0x6a}, + {0x42 ,0x29}, + {0x44 ,0x22}, //;was 11 + {0x45 ,0x41}, + {0x47 ,0x02}, + {0x49 ,0x64}, + {0x4a ,0xa1}, + {0x4b ,0x40}, + {0x4c ,0x1a}, + {0x4d ,0x50}, + {0x4e ,0x13}, + {0x64 ,0x00}, + {0x67 ,0x88}, + {0x68 ,0x1a}, + + {0x14 ,0x28}, //;38/28/18 for 16/8/4x gain ceiling + {0x24 ,0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + /*********************************/ + /* To enable Static Test Pattern */ + /*********************************/ + /* {0x38, 0x07}, */ + /* {0x84, 0x02}, */ + + /*********************************/ + /* Normal Mode / No test pattern */ + {0x38, 0x14}, + /*********************************/ + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x84 ,0x70}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + /* 320x240 */ + + {0x31, 0x50}, + {0x32, 0x78}, + {0x82, 0x3f}, + + {0x0f ,0x1d}, + {0x0f ,0x1f}, + {0xFF, 0xFF} +}; + + +/** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_QQVGA_YUV422 configuration: + * - 160*120 pixel by picture (QQVGA) + * - pixel data in YUV422 format (Y1, U, Y2, V) + */ +const struct ov_reg OV7740_QQVGA_YUV422[] = { + { OV7740_REG0E, OV7740_REG0E_OUTPUT_1X}, + { OV7740_REG12, OV7740_REG12_RESET }, + {0x13, 0x00}, + {0x55 ,0x40}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz */ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz (MCK=132/8) */ + /**************************************************************/ + + {OV7740_CLK, FRAME_RATE_30}, + + {0x12, 0x00}, + {0xd5, 0x10}, + {OV7740_REG0C, OV7740_REG0C_MAX_EXPOSURE(2)}, + {0x0d, 0x34}, + {0x16, 0x01}, + {0x17, 0x25}, + {0x18, 0xa0}, + {0x19, 0x03}, + {0x1a, 0xf0}, + {0x1b, 0x89}, + {0x22, 0x03}, + {0x29, 0x18}, + {0x2b, 0xf8}, + {0x2c, 0x01}, + {0x31, 0xa0}, + {0x32, 0xf0}, + {0x33, 0xc4}, + {0x3a, 0xb4}, + {0x36, 0x3f}, + + {0x04, 0x60}, + {0x27, 0x80}, + {0x3d, 0x0f}, + {0x3e, 0x80}, + {0x3f, 0x40}, + {0x40, 0x7f}, + {0x41, 0x6a}, + {0x42, 0x29}, + {0x44, 0xe5}, + {0x45, 0x41}, + {0x47, 0x02}, + {0x49, 0x64}, + {0x4a, 0xa1}, + {0x4b, 0x70}, + {0x4c, 0x1a}, + {0x4d, 0x50}, + {0x4e, 0x13}, + {0x64, 0x00}, + {0x67, 0x88}, + {0x68, 0x1a}, + + {0x14, 0x38}, + {0x24, 0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + {0x38, 0x14}, + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x84, 0x70}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + /* 160x120 */ + { 0x31, 0x28 }, /* HOUTSIZE MSB */ + { 0x32, 0x3c }, /* VOUTSIZE MSB */ + { 0x34, 0x00 }, /* H/V OUTSIZE LSBs */ + { 0x82, 0x3f }, + /* {0x82, 0x01|0x04|0x08|0x10 }, */ + + /* YUV */ + {0x12, 0x00}, + {0x36, 0x3f}, + {0x53, 0x00}, + + {0x33, 0x00}, + /* {0x33, 0xc4}, */ + {0x1b, 0x89}, + {0x22, 0x03}, + + /* VSYNC, inverse */ + { OV7740_REG28, OV7740_REG28_VSYNC_NEGATIVE }, + + { OV7740_YUV422CTRL, OV7740_YUV422CTRL_V_FIRST_YUYV }, + + {0xFF, 0xFF} +}; + + +/** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_QVGA_RGB888 configuration: + * - 320*240 pixel by picture (QVGA) + * - pixel data in RGB format (8-8-8) + */ +const struct ov_reg OV7740_QVGA_RGB888[] = { + {0x0e, 0x00}, + + {0x12, 0x80}, + {0x13, 0x00}, + + {0x55 ,0x40}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz */ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz (MCK=132/8) */ + /**************************************************************/ + + {OV7740_CLK, FRAME_RATE_30}, + + {0x12, 0x00}, + {0xd5, 0x10}, + {OV7740_REG0C, OV7740_REG0C_MAX_EXPOSURE(2)}, + {0x0d, 0x34}, + {0x17, 0x25}, + {0x18, 0xa0}, + {0x19, 0x03}, + {0x1a, 0xf0}, + {0x1b, 0x89}, + {0x22, 0x03}, + {0x29, 0x18}, + {0x2b, 0xf8}, + {0x2c, 0x01}, + {0x31, 0xa0}, + {0x32, 0xf0}, + {0x33, 0xc4}, + {0x3a, 0xb4}, + {0x36, 0x3f}, + + {0x04, 0x60}, + {0x27, 0x80}, + {0x3d, 0x0f}, + {0x3e, 0x80}, + {0x3f, 0x40}, + {0x40, 0x7f}, + {0x41, 0x6a}, + {0x42, 0x29}, + {0x44, 0xe5}, + {0x45, 0x41}, + {0x47, 0x02}, + {0x49, 0x64}, + {0x4a, 0xa1}, + {0x4b, 0x70}, + {0x4c, 0x1a}, + {0x4d, 0x50}, + {0x4e, 0x13}, + {0x64, 0x00}, + {0x67, 0x88}, + {0x68, 0x1a}, + + {0x14, 0x38}, + {0x24, 0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + {0x38, 0x14}, + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x84, 0x70}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + /* 320x240 */ + {0x31, 0x50}, + {0x32, 0x78}, + {0x82, 0x3f}, + + /* VGA,RGBRAW_8 */ + {0x12, 0x01}, + {0x36, 0x2f}, + {0x83, 0x04}, + {0x53, 0x00}, + + {0x33, 0xf4}, + {0x1b, 0x8a}, + {0x22, 0x03}, + + /* */ + {0x84, 0x00}, + {0x84, 0x00}, + + {0x28, 0x02}, + + /* */ + {0xFF, 0xFF}, +}; + + +/** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_QVGA_RGB888 configuration: + * - 160*120 pixel by picture (QQVGA) + * - pixel data in RGB format (8-8-8) + */ +const struct ov_reg OV7740_QQVGA_RGB888[] = { + {0x0e, 0x00}, + + {0x12, 0x80}, + {0x13, 0x00}, + + {0x55 ,0x40}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz */ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz (MCK=132/8) */ + /**************************************************************/ + + {OV7740_CLK, FRAME_RATE_30}, + + {0x12, 0x00}, + {0xd5, 0x10}, + {OV7740_REG0C, (OV7740_REG0C_FLIP_ENABLE | OV7740_REG0C_MAX_EXPOSURE(2))}, + {0x0d, 0x34}, + {0x17, 0x25}, + {0x18, 0xa0}, + {0x19, 0x03}, + {0x1a, 0xf0}, + {0x1b, 0x89}, + {0x22, 0x03}, + {0x29, 0x18}, + {0x2b, 0xf8}, + {0x2c, 0x01}, + {0x31, 0xa0}, + {0x32, 0xf0}, + {0x33, 0xc4}, + {0x3a, 0xb4}, + {0x36, 0x3f}, + + {0x04, 0x60}, + {0x27, 0x80}, + {0x3d, 0x0f}, + {0x3e, 0x80}, + {0x3f, 0x40}, + {0x40, 0x7f}, + {0x41, 0x6a}, + {0x42, 0x29}, + {0x44, 0xe5}, + {0x45, 0x41}, + {0x47, 0x02}, + {0x49, 0x64}, + {0x4a, 0xa1}, + {0x4b, 0x70}, + {0x4c, 0x1a}, + {0x4d, 0x50}, + {0x4e, 0x13}, + {0x64, 0x00}, + {0x67, 0x88}, + {0x68, 0x1a}, + + {0x14, 0x38}, + {0x24, 0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + {0x38, 0x14}, + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x84, 0x70}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + /* 160x120 */ + {0x31, 0x28}, + {0x32, 0x3c}, + {0x82, 0x3f}, + + /* VGA, RGBRAW_8 */ + {0x12, 0x01}, + {0x36, 0x2f}, + {0x83, 0x04}, + {0x53, 0x00}, + + {0x33, 0xf4}, + {0x1b, 0x8a}, + {0x22, 0x03}, + + {0x84, 0x00}, + {0x84, 0x00}, + + {0x28, 0x02}, + + {0xFF, 0xFF}, +}; + +/** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_QQVGA_YUV422 configuration: + * - 352*288 pixel by picture (CIF) + * - pixel data in YUV422 format (Y1, U, Y2, V) + */ +const struct ov_reg OV7740_CIF_YUV422[] = { + { OV7740_REG0E, OV7740_REG0E_OUTPUT_1X}, + { OV7740_REG12, OV7740_REG12_RESET }, + {0x13, 0x00}, + {0x55 ,0x40}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz */ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz (MCK=132/8) */ + /**************************************************************/ + + {OV7740_CLK, FRAME_RATE_30}, + {0x12, 0x00}, + {0xd5, 0x10}, + {OV7740_REG0C, + (OV7740_REG0C_MIRROR_ENABLE | OV7740_REG0C_MAX_EXPOSURE(2) + | OV7740_REG0C_YUV_SWAP_ENABLE)}, + {0x0d, 0x34}, + {0x16, 0x01}, + {0x17, 0x25}, + {0x18, 0xa0}, + {0x19, 0x03}, + {0x1a, 0xf0}, + {0x1b, 0x89}, + {0x22, 0x03}, + {0x29, 0x18}, + {0x2b, 0xf8}, + {0x2c, 0x01}, + {0x31, 0xa0}, + {0x32, 0xf0}, + {0x33, 0xc4}, + {0x3a, 0xb4}, + {0x36, 0x3f}, + + {0x04, 0x60}, + {0x27, 0x80}, + {0x3d, 0x0f}, + {0x3e, 0x80}, + {0x3f, 0x40}, + {0x40, 0x7f}, + {0x41, 0x6a}, + {0x42, 0x29}, + {0x44, 0xe5}, + {0x45, 0x41}, + {0x47, 0x02}, + {0x49, 0x64}, + {0x4a, 0xa1}, + {0x4b, 0x70}, + {0x4c, 0x1a}, + {0x4d, 0x50}, + {0x4e, 0x13}, + {0x64, 0x00}, + {0x67, 0x88}, + {0x68, 0x1a}, + + {0x14, 0x38}, + {0x24, 0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + {0x38, 0x14}, + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x84, 0x70}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + /* 352x288 */ + { 0x31, 0x58 }, /* HOUTSIZE MSB */ + { 0x32, 0x90 }, /* VOUTSIZE MSB */ + { 0x34, 0x00 }, /* H/V OUTSIZE LSBs */ + { 0x82, 0x3f }, + /* {0x82, 0x01|0x04|0x08|0x10 }, */ + + /* YUV */ + {0x12, 0x00}, + {0x36, 0x3f}, + {0x53, 0x00}, + + {0x33, 0x00}, + /* {0x33, 0xc4}, */ + {0x1b, 0x89}, + {0x22, 0x03}, + + /* VSYNC, inverse */ + { OV7740_REG28, OV7740_REG28_VSYNC_NEGATIVE }, + + { OV7740_YUV422CTRL, OV7740_YUV422CTRL_V_FIRST_YUYV }, + + {0xFF, 0xFF} +}; + +/** + * \brief Addresses and values of the OV7740 registers for the + * OV7740_TEST_PATTERN configuration: + * - 320*240 pixel by picture (QVGA) + * - pixel data in YUV422 format (Y1, U, Y2, V) + * - 20 frames per second + * - test pattern enable + */ +const struct ov_reg OV7740_TEST_PATTERN[] = { + {0x0e, 0x00}, + + {0x12, 0x80}, + /* flag for soft reset delay */ + {0xFE, 0x05}, + {0x13, 0x00}, + {0x55 ,0x40}, + + /**************************************************************/ + /* 30fps 11 01 ;clock_divider ;sysclk=24MHz at XCLK=24MHz */ + /* 20fps 11 02 ;clock_divider ;sysclk=16MHz at XCLK=24MHz */ + /* 15fps 11 03 ;clock_divider ;sysclk=12MHz at XCLK=24MHz */ + /* 10fps 11 05 ;sysclk=8MHz at XCLK=24MHz */ + /* 7p5fps 11 07 ;sysclk=6MHz at XCLK=24MHz */ + /**************************************************************/ + /* 7p5fps 11 0x0A ;sysclk=6MHz at XCLK=16.5MHz (MCK=132/8) */ + /**************************************************************/ + + {OV7740_CLK, FRAME_RATE_30}, + + {0x12, 0x00}, + {0xd5, 0x10}, + {OV7740_REG0C, + (OV7740_REG0C_MIRROR_ENABLE | OV7740_REG0C_FLIP_ENABLE + | OV7740_REG0C_MAX_EXPOSURE(2) | OV7740_REG0C_YUV_SWAP_ENABLE)}, + {0x0d, 0x34}, + {0x16, 0x01}, + {0x17, 0x25}, + {0x18, 0xa0}, + {0x19, 0x03}, + {0x1a, 0xf0}, + {0x1b, 0x89}, + {0x22, 0x03}, + {0x29, 0x18}, + {0x2b, 0xf8}, + {0x2c, 0x01}, + {0x31, 0xa0}, + {0x32, 0xf0}, + {0x33, 0xc4}, + {0x3a, 0xb4}, + {0x36, 0x3f}, + + {0x04, 0x60}, + {0x27, 0x80}, + {0x3d, 0x0f}, + {0x3e, 0x80}, + {0x3f, 0x40}, + {0x40, 0x7f}, + {0x41, 0x6a}, + {0x42, 0x29}, + {0x44, 0xe5}, + {0x45, 0x41}, + {0x47, 0x02}, + {0x49, 0x64}, + {0x4a, 0xa1}, + {0x4b, 0x70}, + {0x4c, 0x1a}, + {0x4d, 0x50}, + {0x4e, 0x13}, + {0x64, 0x00}, + {0x67, 0x88}, + {0x68, 0x1a}, + + {0x14, 0x38}, + {0x24, 0x3c}, + {0x25, 0x30}, + {0x26, 0x72}, + {0x50, 0x97}, + {0x51, 0x7e}, + {0x52, 0x00}, + {0x53, 0x00}, + {0x20, 0x00}, + {0x21, 0x23}, + /*********************************/ + /* To enable Static Test Pattern */ + /*********************************/ + {0x38, 0x07}, + {0x84, 0x02}, + /*********************************/ + /* Normal Mode */ + {0x38, 0x14}, + /*********************************/ + {0xe9, 0x00}, + {0x56, 0x55}, + {0x57, 0xff}, + {0x58, 0xff}, + {0x59, 0xff}, + {0x5f, 0x04}, + {0xec, 0x00}, + {0x13, 0xff}, + + {0x80, 0x7f}, + {0x81, 0x3f}, + {0x82, 0x32}, + {0x83, 0x01}, + {0x38, 0x11}, + {0x85, 0x00}, + {0x86, 0x03}, + {0x87, 0x01}, + {0x88, 0x05}, + {0x89, 0x30}, + {0x8d, 0x30}, + {0x8f, 0x85}, + {0x93, 0x30}, + {0x95, 0x85}, + {0x99, 0x30}, + {0x9b, 0x85}, + + {0x9c, 0x08}, + {0x9d, 0x12}, + {0x9e, 0x23}, + {0x9f, 0x45}, + {0xa0, 0x55}, + {0xa1, 0x64}, + {0xa2, 0x72}, + {0xa3, 0x7f}, + {0xa4, 0x8b}, + {0xa5, 0x95}, + {0xa6, 0xa7}, + {0xa7, 0xb5}, + {0xa8, 0xcb}, + {0xa9, 0xdd}, + {0xaa, 0xec}, + {0xab, 0x1a}, + + {0xce, 0x78}, + {0xcf, 0x6e}, + {0xd0, 0x0a}, + {0xd1, 0x0c}, + {0xd2, 0x84}, + {0xd3, 0x90}, + {0xd4, 0x1e}, + + {0x5a, 0x24}, + {0x5b, 0x1f}, + {0x5c, 0x88}, + {0x5d, 0x60}, + + {0xac, 0x6e}, + {0xbe, 0xff}, + {0xbf, 0x00}, + + /* 320x240 */ + + {0x31, 0x50}, + {0x32, 0x78}, + {0x82, 0x3f}, + + /* YUV */ + {0x12, 0x00}, + {0x36, 0x3f}, + {0x53, 0x00}, + + {0x33, 0xc4}, + {0x1b, 0x89}, + {0x22, 0x03}, + + /* VSYNC, inverse */ + {0x28, 0x2}, + + {0xFF, 0xFF} +}; + +/* @} */ + +#ifdef __cplusplus +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov9740_config.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov9740_config.c new file mode 100644 index 000000000..32dfa6f8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/ov9740_config.c @@ -0,0 +1,602 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + */ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Local Variables + *----------------------------------------------------------------------------*/ + +const struct ov_reg ov9740_yuv_vga[]={ +//@@ VGA 640x360 bin YUV DVP 60FPS (Full speed) + {0x0103,0x01}, + {0x3026,0x00}, + {0x3027,0x00}, + {0x3002,0xe8}, + {0x3004,0x03}, + {0x3005,0xff}, + {0x3703,0x42}, + {0x3704,0x10}, + {0x3705,0x45}, + {0x3603,0xaa}, + {0x3632,0x27}, + {0x3620,0x66}, + {0x3621,0xc0}, + {0x0202,0x03}, + {0x0203,0x43}, + {0x3833,0x04}, + {0x3835,0x02}, + {0x4702,0x04}, + {0x4704,0x00}, + {0x4706,0x08}, + {0x3819,0x6e}, + {0x3817,0x94}, + {0x3a18,0x00}, + {0x3a19,0x7f}, + {0x5003,0xa7}, + {0x3631,0x5e}, + {0x3633,0x50}, + {0x3630,0xd2}, + {0x3604,0x0c}, + {0x3601,0x40}, + {0x3602,0x16}, + {0x3610,0xa1}, + {0x3612,0x24}, + {0x034a,0x02}, + {0x034b,0xd3}, + {0x034c,0x02}, + {0x034d,0x80}, + {0x034e,0x01}, + {0x034f,0x68}, + {0x0202,0x01}, + {0x0203,0x9e}, + {0x381a,0x44}, + {0x3707,0x14}, + {0x3622,0x9f}, + {0x5841,0x04}, + {0x4002,0x45}, + {0x5000,0x01}, + {0x5001,0x00}, + {0x3406,0x00}, + {0x5000,0xff}, + {0x5001,0xef}, + {0x5003,0xff}, + {0x4005,0x18}, + {0x3503,0x10}, + {0x3a11,0xa0}, + {0x3a1b,0x50}, + {0x3a0f,0x50}, + {0x3a10,0x4c}, + {0x3a1e,0x4c}, + {0x3a1f,0x26}, + {0x3104,0x20}, + {0x0305,0x03}, + {0x0307,0x5f}, + {0x0303,0x01}, + {0x0301,0x0a}, + {0x3010,0x01}, + {0x300c,0x02}, + {0x0340,0x02}, + {0x0341,0x08}, + {0x0342,0x04}, + {0x0343,0xc0}, + {0x0101,0x01}, + {0x3a08,0x01}, + {0x3a09,0x38}, + {0x3a0e,0x01}, + {0x3a14,0x09}, + {0x3a15,0xc0}, + {0x3a0a,0x01}, + {0x3a0b,0x02}, + {0x3a0d,0x02}, + {0x3a02,0x10}, + {0x3a03,0x30}, + {0x3c0a,0x9c}, + {0x3c0b,0x3f}, + {0x529a,0x1 }, + {0x529b,0x2 }, + {0x529c,0x3 }, + {0x529d,0x5 }, + {0x529e,0x5 }, + {0x529f,0x28}, + {0x52a0,0x32}, + {0x52a2,0x0 }, + {0x52a3,0x2 }, + {0x52a4,0x0 }, + {0x52a5,0x4 }, + {0x52a6,0x0 }, + {0x52a7,0x8 }, + {0x52a8,0x0 }, + {0x52a9,0x10}, + {0x52aa,0x0 }, + {0x52ab,0x38}, + {0x52ac,0x0 }, + {0x52ad,0x3c}, + {0x52ae,0x0 }, + {0x52af,0x4c}, + {0x5842,0x02}, + {0x5843,0x5e}, + {0x5844,0x04}, + {0x5845,0x32}, + {0x5846,0x03}, + {0x5847,0x29}, + {0x5848,0x02}, + {0x5849,0xcc}, + {0x5800,0x22}, + {0x5801,0x1e}, + {0x5802,0x1a}, + {0x5803,0x1a}, + {0x5804,0x1f}, + {0x5805,0x26}, + {0x5806,0xe }, + {0x5807,0x9 }, + {0x5808,0x7 }, + {0x5809,0x8 }, + {0x580a,0xb }, + {0x580b,0x11}, + {0x580c,0x5 }, + {0x580d,0x2 }, + {0x580e,0x0 }, + {0x580f,0x0 }, + {0x5810,0x3 }, + {0x5811,0x7 }, + {0x5812,0x4 }, + {0x5813,0x1 }, + {0x5814,0x0 }, + {0x5815,0x0 }, + {0x5816,0x3 }, + {0x5817,0x7 }, + {0x5818,0xc }, + {0x5819,0x8 }, + {0x581a,0x6 }, + {0x581b,0x6 }, + {0x581c,0x9 }, + {0x581d,0x10}, + {0x581e,0x20}, + {0x581f,0x1b}, + {0x5820,0x17}, + {0x5821,0x18}, + {0x5822,0x1d}, + {0x5823,0x23}, + {0x5824,0x5b}, + {0x5825,0x6e}, + {0x5826,0x6e}, + {0x5827,0x7e}, + {0x5828,0xab}, + {0x5829,0x5e}, + {0x582a,0x8a}, + {0x582b,0x8a}, + {0x582c,0x8a}, + {0x582d,0x9d}, + {0x582e,0x5b}, + {0x582f,0x88}, + {0x5830,0x88}, + {0x5831,0x98}, + {0x5832,0x9a}, + {0x5833,0x4e}, + {0x5834,0x8a}, + {0x5835,0x79}, + {0x5836,0x7a}, + {0x5837,0xad}, + {0x5838,0x9b}, + {0x5839,0x9d}, + {0x583a,0xad}, + {0x583b,0x8e}, + {0x583c,0x5c}, + {0x583e,0x08}, + {0x583f,0x04}, + {0x5840,0x10}, + {0x5480,0x07}, + {0x5481,0x16}, + {0x5482,0x2c}, + {0x5483,0x4d}, + {0x5484,0x59}, + {0x5485,0x64}, + {0x5486,0x6e}, + {0x5487,0x76}, + {0x5488,0x7f}, + {0x5489,0x86}, + {0x548a,0x94}, + {0x548b,0xa3}, + {0x548c,0xba}, + {0x548d,0xd2}, + {0x548e,0xe9}, + {0x548f,0x1e}, + {0x5490,0x0f}, + {0x5491,0xff}, + {0x5492,0x0e}, + {0x5493,0x34}, + {0x5494,0x07}, + {0x5495,0x1a}, + {0x5496,0x04}, + {0x5497,0x0e}, + {0x5498,0x03}, + {0x5499,0x82}, + {0x549a,0x03}, + {0x549b,0x20}, + {0x549c,0x02}, + {0x549d,0xd7}, + {0x549e,0x02}, + {0x549f,0xa5}, + {0x54a0,0x02}, + {0x54a1,0x75}, + {0x54a2,0x02}, + {0x54a3,0x55}, + {0x54a4,0x02}, + {0x54a5,0x1c}, + {0x54a6,0x01}, + {0x54a7,0xea}, + {0x54a8,0x01}, + {0x54a9,0xae}, + {0x54aa,0x01}, + {0x54ab,0x7c}, + {0x54ac,0x01}, + {0x54ad,0x57}, + {0x5180,0xf0}, + {0x5181,0x00}, + {0x5182,0x41}, + {0x5183,0x42}, + {0x5184,0x8f}, + {0x5185,0x63}, + {0x5186,0xce}, + {0x5187,0xa8}, + {0x5188,0x17}, + {0x5189,0x1f}, + {0x518a,0x27}, + {0x518b,0x41}, + {0x518c,0x34}, + {0x518d,0xf0}, + {0x518e,0x10}, + {0x518f,0xff}, + {0x5190,0x00}, + {0x5191,0xff}, + {0x5192,0x00}, + {0x5193,0xff}, + {0x5194,0x00}, + {0x5380,0x1 }, + {0x5381,0x0 }, + {0x5382,0x0 }, + {0x5383,0x17}, + {0x5384,0x0 }, + {0x5385,0x1 }, + {0x5386,0x0 }, + {0x5387,0x0 }, + {0x5388,0x0 }, + {0x5389,0xad}, + {0x538a,0x0 }, + {0x538b,0x11}, + {0x538c,0x0 }, + {0x538d,0x0 }, + {0x538e,0x0 }, + {0x538f,0x7 }, + {0x5390,0x0 }, + {0x5391,0x80}, + {0x5392,0x0 }, + {0x5393,0xa0}, + {0x5394,0x18}, + {0x3c0a,0x9c}, + {0x3c0b,0x3f}, + {0x5501,0x14}, + {0x5502,0x00}, + {0x5503,0x40}, + {0x5504,0x00}, + {0x5505,0x80}, + {0x0100,0x01}, + {0xFF, 0xFF} +}; + + + +const struct ov_reg ov9740_yuv_sxga[]={ +//@@ WXGA 1280x720 YUV DVP 15FPS for card reader + {0x0103, 0x01}, + {0x3026, 0x00}, + {0x3027, 0x00}, + {0x3002, 0xe8}, + {0x3004, 0x03}, + {0x3005, 0xff}, + {0x3406, 0x00}, + {0x3603, 0xaa}, + {0x3632, 0x27}, + {0x3620, 0x66}, + {0x3621, 0xc0}, + {0x3631, 0x5e}, + {0x3633, 0x50}, + {0x3630, 0xd2}, + {0x3604, 0x0c}, + {0x3601, 0x40}, + {0x3602, 0x16}, + {0x3610, 0xa1}, + {0x3612, 0x24}, + {0x3622, 0x9f}, + {0x3703, 0x42}, + {0x3704, 0x10}, + {0x3705, 0x45}, + {0x3707, 0x14}, + {0x3833, 0x04}, + {0x3835, 0x03}, + {0x3819, 0x6e}, + {0x3817, 0x94}, + {0x3503, 0x10}, + {0x3a18, 0x00}, + {0x3a19, 0x7f}, + {0x3a11, 0xa0}, + {0x3a1a, 0x05}, + {0x3a1b, 0x50}, + {0x3a0f, 0x50}, + {0x3a10, 0x4c}, + {0x3a1e, 0x4c}, + {0x3a1f, 0x26}, + {0x4002, 0x45}, + {0x4005, 0x18}, + {0x4702, 0x04}, + {0x4704, 0x00}, + {0x4706, 0x08}, + {0x5000, 0xff}, + {0x5001, 0xef}, + {0x5003, 0xff}, + + {0x3104,0x20}, + {0x0305,0x03}, + {0x0307,0x4c}, + {0x0303,0x01}, + {0x0301,0x08}, + {0x3010,0x01}, + {0x300c,0x03}, + + {0x0340, 0x03}, + {0x0341, 0x07}, + {0x0342, 0x06}, + {0x0343, 0x62}, + {0x034b, 0xd1}, + {0x034c, 0x05}, + {0x034d, 0x00}, + {0x034e, 0x02}, + {0x034f, 0xd0}, + {0x0101, 0x01}, + {0x3a08, 0x00}, + {0x3a09, 0xe8}, + {0x3a0e, 0x03}, + {0x3a14, 0x15}, + {0x3a15, 0xc6}, + {0x3a0a, 0x00}, + {0x3a0b, 0xc0}, + {0x3a0d, 0x04}, + {0x3a02, 0x18}, + {0x3a03, 0x20}, + {0x3c0a, 0x9c}, + {0x3c0b, 0x3f}, + {0x529a, 0x1 }, + {0x529b, 0x2 }, + {0x529c, 0x3 }, + {0x529d, 0x5 }, + {0x529e, 0x5 }, + {0x529f, 0x28}, + {0x52a0, 0x32}, + {0x52a2, 0x0 }, + {0x52a3, 0x2 }, + {0x52a4, 0x0 }, + {0x52a5, 0x4 }, + {0x52a6, 0x0 }, + {0x52a7, 0x8 }, + {0x52a8, 0x0 }, + {0x52a9, 0x10}, + {0x52aa, 0x0 }, + {0x52ab, 0x38}, + {0x52ac, 0x0 }, + {0x52ad, 0x3c}, + {0x52ae, 0x0 }, + {0x52af, 0x4c}, + {0x5842, 0x02}, + {0x5843, 0x5e}, + {0x5844, 0x04}, + {0x5845, 0x32}, + {0x5846, 0x03}, + {0x5847, 0x29}, + {0x5848, 0x02}, + {0x5849, 0xcc}, + {0x5800, 0x22}, + {0x5801, 0x1e}, + {0x5802, 0x1a}, + {0x5803, 0x1a}, + {0x5804, 0x1f}, + {0x5805, 0x26}, + {0x5806, 0xe }, + {0x5807, 0x9 }, + {0x5808, 0x7 }, + {0x5809, 0x8 }, + {0x580a, 0xb }, + {0x580b, 0x11}, + {0x580c, 0x5 }, + {0x580d, 0x2 }, + {0x580e, 0x0 }, + {0x580f, 0x0 }, + {0x5810, 0x3 }, + {0x5811, 0x7 }, + {0x5812, 0x4 }, + {0x5813, 0x1 }, + {0x5814, 0x0 }, + {0x5815, 0x0 }, + {0x5816, 0x3 }, + {0x5817, 0x7 }, + {0x5818, 0xc }, + {0x5819, 0x8 }, + {0x581a, 0x6 }, + {0x581b, 0x6 }, + {0x581c, 0x9 }, + {0x581d, 0x10}, + {0x581e, 0x20}, + {0x581f, 0x1b}, + {0x5820, 0x17}, + {0x5821, 0x18}, + {0x5822, 0x1d}, + {0x5823, 0x23}, + {0x5824, 0x5b}, + {0x5825, 0x6e}, + {0x5826, 0x6e}, + {0x5827, 0x7e}, + {0x5828, 0xab}, + {0x5829, 0x5e}, + {0x582a, 0x8a}, + {0x582b, 0x8a}, + {0x582c, 0x8a}, + {0x582d, 0x9d}, + {0x582e, 0x5b}, + {0x582f, 0x88}, + {0x5830, 0x88}, + {0x5831, 0x98}, + {0x5832, 0x9a}, + {0x5833, 0x4e}, + {0x5834, 0x8a}, + {0x5835, 0x79}, + {0x5836, 0x7a}, + {0x5837, 0xad}, + {0x5838, 0x9b}, + {0x5839, 0x9d}, + {0x583a, 0xad}, + {0x583b, 0x8e}, + {0x583c, 0x5c}, + {0x583e, 0x08}, + {0x583f, 0x04}, + {0x5840, 0x10}, + {0x5480, 0x07}, + {0x5481, 0x16}, + {0x5482, 0x2c}, + {0x5483, 0x4d}, + {0x5484, 0x59}, + {0x5485, 0x64}, + {0x5486, 0x6e}, + {0x5487, 0x76}, + {0x5488, 0x7f}, + {0x5489, 0x86}, + {0x548a, 0x94}, + {0x548b, 0xa3}, + {0x548c, 0xba}, + {0x548d, 0xd2}, + {0x548e, 0xe9}, + {0x548f, 0x1e}, + {0x5490, 0x0f}, + {0x5491, 0xff}, + {0x5492, 0x0e}, + {0x5493, 0x34}, + {0x5494, 0x07}, + {0x5495, 0x1a}, + {0x5496, 0x04}, + {0x5497, 0x0e}, + {0x5498, 0x03}, + {0x5499, 0x82}, + {0x549a, 0x03}, + {0x549b, 0x20}, + {0x549c, 0x02}, + {0x549d, 0xd7}, + {0x549e, 0x02}, + {0x549f, 0xa5}, + {0x54a0, 0x02}, + {0x54a1, 0x75}, + {0x54a2, 0x02}, + {0x54a3, 0x55}, + {0x54a4, 0x02}, + {0x54a5, 0x1c}, + {0x54a6, 0x01}, + {0x54a7, 0xea}, + {0x54a8, 0x01}, + {0x54a9, 0xae}, + {0x54aa, 0x01}, + {0x54ab, 0x7c}, + {0x54ac, 0x01}, + {0x54ad, 0x57}, + {0x5180, 0xf0}, + {0x5181, 0x00}, + {0x5182, 0x41}, + {0x5183, 0x42}, + {0x5184, 0x8f}, + {0x5185, 0x63}, + {0x5186, 0xce}, + {0x5187, 0xa8}, + {0x5188, 0x17}, + {0x5189, 0x1f}, + {0x518a, 0x27}, + {0x518b, 0x41}, + {0x518c, 0x34}, + {0x518d, 0xf0}, + {0x518e, 0x10}, + {0x518f, 0xff}, + {0x5190, 0x00}, + {0x5191, 0xff}, + {0x5192, 0x00}, + {0x5193, 0xff}, + {0x5194, 0x00}, + {0x5380, 0x1 }, + {0x5381, 0x0 }, + {0x5382, 0x0 }, + {0x5383, 0x17}, + {0x5384, 0x0 }, + {0x5385, 0x1 }, + {0x5386, 0x0 }, + {0x5387, 0x0 }, + {0x5388, 0x0 }, + {0x5389, 0xad}, + {0x538a, 0x0 }, + {0x538b, 0x11}, + {0x538c, 0x0 }, + {0x538d, 0x0 }, + {0x538e, 0x0 }, + {0x538f, 0x7 }, + {0x5390, 0x0 }, + {0x5391, 0x80}, + {0x5392, 0x0 }, + {0x5393, 0xa0}, + {0x5394, 0x18}, + {0x3c0a, 0x9c}, + {0x3c0b, 0x3f}, + {0x5501, 0x14}, + {0x5502, 0x00}, + {0x5503, 0x40}, + {0x5504, 0x00}, + {0x5505, 0x80}, + {0x5308, 0x40}, + {0x5309, 0x60}, + {0x3a11, 0xd0}, + {0x3a1b, 0x78}, + {0x3a0f, 0x78}, + {0x3a10, 0x68}, + {0x3a1e, 0x68}, + {0x3a1f, 0x40}, + {0x0100, 0x01}, + {0xFF, 0xFF} +}; + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/rtc_calib.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/rtc_calib.c new file mode 100644 index 000000000..aa4dfb5a8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/rtc_calib.c @@ -0,0 +1,194 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Real Time Clock calibration (RTC) . + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +const RTC_PPMLookup PPM_Lookup[] = +{ + /* Tmp PPM Neg Hi Correction */ + {-40, -168 ,0, 1 ,22 }, + {-39, -163 ,0, 1 ,23 }, + {-38, -158 ,0, 1 ,24 }, + {-37, -153 ,0, 1 ,25 }, + {-36, -148 ,0, 1 ,25 }, + {-35, -143 ,0, 1 ,26 }, + {-34, -138 ,0, 1 ,27 }, + {-33, -134 ,0, 1 ,28 }, + {-32, -129 ,0, 1 ,29 }, + {-31, -124 ,0, 1 ,31 }, + {-30, -120 ,0, 1 ,32 }, + {-29, -116 ,0, 1 ,33 }, + {-28, -111 ,0, 1 ,34 }, + {-27, -107 ,0, 1 ,36 }, + {-26, -103 ,0, 1 ,37 }, + {-25, -99, 0, 1 ,38 }, + {-24, -95, 0, 1 ,40 }, + {-23, -91, 0, 1 ,42 }, + {-22, -87, 0, 1 ,44 }, + {-21, -84, 0, 1 ,45 }, + {-20, -80, 0, 1 ,48 }, + {-19, -76, 0, 1 ,50 }, + {-18, -73, 0, 1 ,53 }, + {-17, -70, 0, 1 ,55 }, + {-16, -66, 0, 1 ,58 }, + {-15, -63, 0, 1 ,61 }, + {-14, -60, 0, 1 ,64 }, + {-13, -57, 0, 1 ,68 }, + {-12, -54, 0, 1 ,71 }, + {-11, -51, 0, 1 ,76 }, + {-10, -48, 0, 1 ,80 }, + {-9 ,-45 , 0, 1 ,86 }, + {-8 ,-43 , 0, 1 ,90 }, + {-7 ,-40 , 0, 1 ,97 }, + {-6 ,-37 , 0, 1 ,105}, + {-5 ,-35 , 0, 1 ,111}, + {-4 ,-33 , 0, 1 ,117}, + {-3 ,-30 , 0, 0 ,6 }, + {-2 ,-28 , 0, 0 ,6 }, + {-1 ,-26 , 0, 0 ,7 }, + {0 ,-24 , 0, 0 ,7 }, + {1 ,-22 , 0, 0 ,8 }, + {2 ,-20 , 0, 0 ,9 }, + {3 ,-18 , 0, 0 ,10 }, + {4 ,-17 , 0, 0 ,10 }, + {5 ,-15 , 0, 0 ,12 }, + {6 ,-13 , 0, 0 ,14 }, + {7 ,-12 , 0, 0 ,15 }, + {8 ,-11 , 0, 0 ,17 }, + {9 ,-9 , 0, 0 ,21 }, + {10 ,-8 , 0, 0 ,23 }, + {11 ,-7 , 0, 0 ,27 }, + {12 ,-6 , 0, 0 ,32 }, + {13 ,-5 , 0, 0 ,38 }, + {14 ,-4 , 0, 0 ,48 }, + {15 ,-3 , 0, 0 ,64 }, + {16 ,-2 , 0, 0 ,97 }, + {17 ,-2 , 0, 0 ,97 }, + {18 ,-1 , 0, 0 ,127}, + {19 ,0, 1, 0 ,0 }, + {20 ,0, 1, 0 ,0 }, + {21 ,0, 1, 0 ,0 }, + {22 ,1, 1, 0 ,127}, + {23 ,1, 1, 0 ,127}, + {24 ,1, 1, 0 ,127}, + {25 ,1, 1, 0 ,127}, + {26 ,1, 1, 0 ,127}, + {27 ,1, 1, 0 ,127}, + {28 ,1, 1, 0 ,127}, + {29 ,0, 1, 0 ,0 }, + {30 ,0, 1, 0 ,0 }, + {31 ,0, 1, 0 ,0 }, + {32 ,-1, 0, 0 ,127}, + {33 ,-2, 0, 0 ,97 }, + {34 ,-2, 0, 0 ,97 }, + {35 ,-3, 0, 0 ,64 }, + {36 ,-4, 0, 0 ,48 }, + {37 ,-5, 0, 0 ,38 }, + {38 ,-6, 0, 0 ,32 }, + {39 ,-7, 0, 0 ,27 }, + {40 ,-8, 0, 0 ,23 }, + {41 ,-9, 0, 0 ,21 }, + {42 ,-11 , 0, 0 ,17 }, + {43 ,-12 , 0, 0 ,15 }, + {44 ,-13 , 0, 0 ,14 }, + {45 ,-15 , 0, 0 ,12 }, + {46 ,-17 , 0, 0 ,10 }, + {47 ,-18 , 0, 0 ,10 }, + {48 ,-20 , 0, 0 ,9 }, + {49 ,-22 , 0, 0 ,8 }, + {50 ,-24 , 0, 0 ,7 }, + {51 ,-26 , 0, 0 ,7 }, + {52 ,-28 , 0, 0 ,6 }, + {53 ,-30 , 0, 0 ,6 }, + {54 ,-33 , 0, 1 ,117}, + {55 ,-35 , 0, 1 ,111}, + {56 ,-37 , 0, 1 ,105}, + {57 ,-40 , 0, 1 ,97 }, + {58 ,-43 , 0, 1 ,90 }, + {59 ,-45 , 0, 1 ,86 }, + {60 ,-48 , 0, 1 ,80 }, + {61 ,-51 , 0, 1 ,76 }, + {62 ,-54 , 0, 1 ,71 }, + {63 ,-57 , 0, 1 ,68 }, + {64 ,-60 , 0, 1 ,64 }, + {65 ,-63 , 0, 1 ,61 }, + {66 ,-66 , 0, 1 ,58 }, + {67 ,-70 , 0, 1 ,55 }, + {68 ,-73 , 0, 1 ,53 }, + {69 ,-76 , 0, 1 ,50 }, + {70 ,-80 , 0, 1 ,48 }, + {71 ,-84 , 0, 1 ,45 }, + {72 ,-87 , 0, 1 ,44 }, + {73 ,-91 , 0, 1 ,42 }, + {74 ,-95 , 0, 1 ,40 }, + {75 ,-99 , 0, 1 ,38 }, + {76 ,-103 , 0, 1 ,37 }, + {77 ,-107 , 0, 1 ,36 }, + {78 ,-111 , 0, 1 ,34 }, + {79 ,-116 , 0, 1 ,33 }, + {80 ,-120 , 0, 1 ,32 }, + {81 ,-124 , 0, 1 ,31 }, + {82 ,-129 , 0, 1 ,29 }, + {83 ,-134 , 0, 1 ,28 }, + {84 ,-138 , 0, 1 ,27 }, + {85 ,-143 , 0, 1 ,26 } +}; + +/** + * \brief RTC calibration for Temperature or PPM drift + */ +extern void RTC_ClockCalibration( Rtc* pRtc, int32_t CurrentTempr) +{ + uint16_t i; + uint32_t MR_Reg, Size; + + Size = sizeof(PPM_Lookup); + + MR_Reg = 0; + for(i=0; i< Size; i++) { + if(PPM_Lookup[i].Tempr == CurrentTempr) { + MR_Reg |= RTC_MR_CORRECTION(PPM_Lookup[i].CORRECTION); + MR_Reg |= (PPM_Lookup[i].HIGHPPM << 15); + MR_Reg |= (PPM_Lookup[i].NEGPPM << 4); + pRtc->RTC_MR = MR_Reg; // update the calibration value + break; + } + } +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/s25fl1.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/s25fl1.c new file mode 100644 index 000000000..f1bfa2a52 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/s25fl1.c @@ -0,0 +1,1126 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \addtogroup at25d_module S25FL1 driver + * \ingroup lib_spiflash + * The S25FL1 serial dataflash driver is based on the corresponding S25FL1 SPI + * driver. + * A S25FL1 instance has to be initialized using the Dataflash level function + * S25FL1D_Configure(). S25FL1 Dataflash can be automatically detected using + * the S25FL1D_FindDevice() function. Then S25FL1 dataflash operations such as + * read, write and erase DF can be launched using S25FL1D_SendCommand function + * with corresponding S25FL1 command set. + * + * \section Usage + *
    + *
  • Reads a serial flash device ID using S25FL1D_ReadJedecId().
    • + *
  • Reads data from the S25fl1 at the specified address using S25FL1D_Read(). + *
    • + *
  • Writes data on the S25fl1 at the specified address using S25FL1D_Write(). + *
    • + *
  • Erases all chip using S25FL1D_EraseBlock().
    • + *
  • Erases a specified block using S25FL1D_EraseBlock().
    • + *
  • Poll until the S25fl1 has completed of corresponding operations using + * S25FL1D_IsBusy().
    • + *
  • Retrieves and returns the S25fl1 current using S25FL1D_ReadStatus().
    • + *
+ * + * Related files :\n + * \ref at25d.c\n + * \ref at25d.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation for the S25FL1 Serialflash driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include +#include "stdlib.h" +#include "string.h" + + +/*---------------------------------------------------------------------------- + * Variable + *----------------------------------------------------------------------------*/ +static QspiInstFrame_t *pDev, *pMem; + +static QspiDma_t qspiDma; +static sXdmad qspiDmaInst; + + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define READ_DEV 0 +#define WRITE_DEV 1 + +#define PAGE_SIZE 256 +/** + * \brief XDMA handler. + */ +void XDMAC_Handler(void) +{ + XDMAD_Handler(&qspiDmaInst); +} + +/** + * \brief Start S25FL1D Send command with/without data write/read. + * \param Instr Instruct + * \param pTxData point to Tx buffer address + * \param pRxData point to Rx buffer address + * \param ReadWrite Command/Write/Read access + * \param Size buffer size in byte + * \returns 0 + */ +static uint8_t S25FL1D_SendCommand(uint8_t Instr, uint32_t *pTxData, + uint32_t *pRxData, Access_t ReadWrite, uint32_t size) +{ + qspiDma.Qspid.qspiCommand.Instruction = Instr; + + if(qspiDma.Qspid.qspiMode) { + pDev->InstFrame.bm.bInstEn = 1; + qspiDma.Qspid.pQspiFrame = pDev; + qspiDma.Qspid.qspiBuffer.pDataTx = pTxData; + qspiDma.Qspid.qspiBuffer.pDataRx = pRxData; + + // to prevent unaligned access + if( (size % sizeof(uint32_t)) && size > 1) { + size += (sizeof(uint32_t) - (size % sizeof(uint32_t))); + } + + if(ReadWrite == CmdAccess) { + pDev->InstFrame.bm.bXfrType + = (QSPI_IFR_TFRTYP_TRSFR_READ >> QSPI_IFR_TFRTYP_Pos); + pDev->InstFrame.bm.bDataEn = 0; + + QSPI_SendCommand(&qspiDma.Qspid, 0); + + } else if (ReadWrite == WriteAccess) { + pDev->InstFrame.bm.bDataEn = 1; + pDev->InstFrame.bm.bXfrType + = (QSPI_IFR_TFRTYP_TRSFR_WRITE >> QSPI_IFR_TFRTYP_Pos); + qspiDma.Qspid.qspiBuffer.TxDataSize = size; + QSPI_SendCommandWithData(&qspiDma.Qspid, 0); + + } else { + pDev->InstFrame.bm.bXfrType + = (QSPI_IFR_TFRTYP_TRSFR_READ >> QSPI_IFR_TFRTYP_Pos); + pDev->InstFrame.bm.bDataEn = 1; + qspiDma.Qspid.qspiBuffer.RxDataSize = size; + QSPI_ReadCommand(&qspiDma.Qspid, 0); + } + } else { + if((ReadWrite == CmdAccess) || (ReadWrite == WriteAccess)) { + qspiDma.Qspid.qspiBuffer.pDataTx = malloc(size+1); + qspiDma.Qspid.qspiBuffer.pDataTx[0] + = qspiDma.Qspid.qspiCommand.Instruction; + if(size) { + memcpy(&qspiDma.Qspid.qspiBuffer.pDataTx[1], pTxData, size); + } + qspiDma.Qspid.qspiBuffer.TxDataSize = size+1; + + QSPI_MultiWriteSPI(&qspiDma.Qspid, + (uint16_t const*)qspiDma.Qspid.qspiBuffer.pDataTx, + qspiDma.Qspid.qspiBuffer.TxDataSize); + + free(qspiDma.Qspid.qspiBuffer.pDataTx); + } else if (ReadWrite == ReadAccess) { + qspiDma.Qspid.qspiBuffer.pDataRx = pRxData; + QSPI_SingleWriteSPI(&qspiDma.Qspid, + (uint16_t const*)&qspiDma.Qspid.qspiCommand.Instruction); + QSPI_MultiReadSPI(&qspiDma.Qspid, + (uint16_t *)qspiDma.Qspid.qspiBuffer.pDataRx, size); + } else { + TRACE_ERROR("%s Wrong access parameter \n\r", __FUNCTION__); + } + QSPI_EndTransfer(qspiDma.Qspid.pQspiHw); + } + return 0; +} + + +/** + * \brief Start S25FL1D Memory access with/without data write/read. + * \param Instr Instruct + * \param pTxData point to Tx buffer address + * \param pRxData point to Rx buffer address + * \param ReadWrite Command/Write/Read access + * \param Size buffer size in byte + * \returns 0 + */ +static uint8_t S25FL1D_MemoryAccess(uint8_t Instr, uint32_t Addr, + uint32_t *pTxData, uint32_t *pRxData, Access_t ReadWrite, + uint32_t size, uint8_t Secure) +{ + uint8_t SpiBuffer[4]; + qspiDma.Qspid.qspiCommand.Instruction = Instr; + + if(qspiDma.Qspid.qspiMode) { + qspiDma.Qspid.qspiBuffer.pDataTx = pTxData; + qspiDma.Qspid.qspiBuffer.pDataRx = pRxData; + pMem->Addr=Addr; + pMem->InstFrame.bm.bInstEn = 1; + pMem->InstFrame.bm.bDataEn = 1; + pMem->InstFrame.bm.bAddrEn = 1; + qspiDma.Qspid.pQspiFrame = pMem; + if (ReadWrite == WriteAccess) { + pMem->InstFrame.bm.bXfrType + = (QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY >> QSPI_IFR_TFRTYP_Pos); + qspiDma.Qspid.qspiBuffer.TxDataSize = size; + } else { + pMem->InstFrame.bm.bXfrType + = (QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY >> QSPI_IFR_TFRTYP_Pos); + qspiDma.Qspid.qspiBuffer.RxDataSize = size; + } + QSPI_EnableMemAccess(&qspiDma.Qspid, 0, Secure); +#ifdef USE_QSPI_DMA + QSPID_ReadWriteQSPI(&qspiDma, ReadWrite); +#else + QSPI_ReadWriteMem(&qspiDma.Qspid, ReadWrite); +#endif + } else { + qspiDma.Qspid.qspiBuffer.pDataTx = malloc((size+4)); + SpiBuffer[0] = Instr; + SpiBuffer[1] = (uint8_t)(Addr >> 16); + SpiBuffer[2] = (uint8_t)(Addr >> 8); + SpiBuffer[3] = (uint8_t)(Addr); + memcpy(qspiDma.Qspid.qspiBuffer.pDataTx, SpiBuffer, 4); + if(pTxData !=NULL) { + memcpy((qspiDma.Qspid.qspiBuffer.pDataTx+1), pTxData, size); + } + + if (ReadWrite == WriteAccess) { + qspiDma.Qspid.qspiBuffer.TxDataSize = size+4; +#ifdef USE_QSPI_DMA + qspiDma.Qspid.qspiBuffer.RxDataSize = size+4; + qspiDma.Qspid.qspiBuffer.pDataRx = qspiDma.Qspid.qspiBuffer.pDataTx; + QSPID_ReadWriteSPI(&qspiDma, ReadWrite); +#else + + QSPI_MultiWriteSPI(&qspiDma.Qspid, + (uint16_t *)qspiDma.Qspid.qspiBuffer.pDataTx, + qspiDma.Qspid.qspiBuffer.TxDataSize); +#endif + } else { +#ifdef USE_QSPI_DMA + qspiDma.Qspid.qspiBuffer.pDataRx = pRxData; + /* instr(1) + addrs(3) + dummy read(1)*/ + qspiDma.Qspid.qspiBuffer.RxDataSize = size+6; + qspiDma.Qspid.qspiBuffer.TxDataSize = size+6; + QSPID_ReadWriteSPI(&qspiDma, ReadWrite); + while(qspiDma.progress); + /*qspiDma.Qspid.qspiBuffer.pDataRx = pRxData; + qspiDma.Qspid.qspiBuffer.RxDataSize = size; + qspiDma.Qspid.qspiBuffer.TxDataSize = size; + QSPID_ReadWriteSPI(&qspiDma, ReadWrite);*/ +#else + qspiDma.Qspid.qspiBuffer.pDataRx = pRxData; + qspiDma.Qspid.qspiBuffer.RxDataSize = size; + qspiDma.Qspid.qspiBuffer.TxDataSize = 4; + QSPI_MultiWriteSPI(&qspiDma.Qspid, + (uint16_t *)qspiDma.Qspid.qspiBuffer.pDataTx, + qspiDma.Qspid.qspiBuffer.TxDataSize); + QSPI_MultiReadSPI(&qspiDma.Qspid, + (uint16_t *)qspiDma.Qspid.qspiBuffer.pDataRx, + size); + QSPI_EndTransfer(qspiDma.Qspid.pQspiHw); +#endif + } + free(qspiDma.Qspid.qspiBuffer.pDataTx); + qspiDma.Qspid.qspiBuffer.pDataTx= NULL; + } + return 0; +} + +/** + * \brief Reads and returns the status register of the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + */ +static uint32_t S25FL1D_ReadStatus(void) +{ + uint32_t status, ReadStatus; + + S25FL1D_SendCommand(READ_STATUS_1, 0, &ReadStatus, ReadAccess, 1); + status = ReadStatus; + + S25FL1D_SendCommand(READ_STATUS_2, 0, &ReadStatus, ReadAccess, 1); + status |= ((ReadStatus << 8) & 0xFF00); + + S25FL1D_SendCommand(READ_STATUS_3, 0, &ReadStatus, ReadAccess, 1); + status |= ((ReadStatus << 16) & 0xFF0000); + return status; +} + +/** + * \brief Reads and returns the status register of the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + */ +static uint8_t S25FL1D_ReadStatus1(void) +{ + uint8_t status; + S25FL1D_SendCommand(READ_STATUS_1, 0, (uint32_t *)&status, ReadAccess, 1); + return status; +} + +/** + * \brief Reads and returns the status register of the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + */ +static uint8_t S25FL1D_ReadStatus2(void) +{ + uint8_t status; + S25FL1D_SendCommand(READ_STATUS_2, 0, (uint32_t *)&status, ReadAccess, 1); + return status; +} + +/** + * \brief Reads and returns the status register of the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + */ +static uint8_t S25FL1D_ReadStatus3(void) +{ + uint8_t status; + S25FL1D_SendCommand(READ_STATUS_3, 0, (uint32_t *)&status, ReadAccess, 1); + return status; +} +/** + * \brief Wait for transfer to finish calling the SPI driver ISR. + * (interrupts are disabled) + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + */ +static void S25FL1D_IsBusy(void) +{ +#ifdef USE_QSPI_DMA + while(QSPID_IsBusy(&qspiDma.progress) ) { + Wait(1); + } +#endif + while(S25FL1D_ReadStatus1() & STATUS_RDYBSY); +} + +static void S25FL1D_EnableWrite(void) +{ + uint8_t status = 0; + + + while(!(status & STATUS_WEL)) { + S25FL1D_SendCommand(WRITE_ENABLE, 0, 0, CmdAccess, 0); + status = S25FL1D_ReadStatus1(); + } +} + + +static void S25FL1D_DisableWrite(void) +{ + uint8_t status; + + status = S25FL1D_ReadStatus1(); + + while( (status & STATUS_WEL) != 0) { + S25FL1D_SendCommand(WRITE_DISABLE, 0, 0, CmdAccess, 0); + status = S25FL1D_ReadStatus1(); + } +} +/** + * \brief Writes the given value in the status register of the serial flash + * device. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param status Status to write. + */ +static void S25FL1D_WriteStatus( uint8_t *pStatus) +{ + S25FL1D_EnableWrite(); + + S25FL1D_SendCommand(WRITE_STATUS, (uint32_t *)pStatus, 0, WriteAccess, 3); + + S25FL1D_DisableWrite(); +} + +/** + * \brief Writes the given value in the status register of the serial flash + * device. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param status Status to write. + */ +static void S25FL1D_WriteVolatileStatus( uint8_t *pStatus) +{ + uint32_t DataWr = 0; + DataWr = *pStatus; + + S25FL1D_SendCommand(0x50, 0, 0 , CmdAccess, 0); + + S25FL1D_SendCommand(WRITE_STATUS,&DataWr, 0 , WriteAccess, 3); + S25FL1D_DisableWrite(); +} + + +static uint8_t S25FL1D_CheckProtectedAddr(uint8_t Status1, uint32_t Addr) +{ + const uint32_t AddrJump + = (Status1 & SEC_PROTECT_Msk) ? 0x001000UL : 0x010000UL; + static uint8_t Protected = 0; + + const uint8_t blockBits = ((Status1 & BLOCK_PROTECT_Msk) >> 2); + + switch(blockBits) { + case 1: + if (Status1 & TOP_BTM_PROTECT_Msk) { + if( ( Addr > 0x000000) && ( Addr < (0x000000 + AddrJump - 1) ) ) { + Protected = 1; + } + } else { + if( ( Addr > (0x1FFFFF - AddrJump + 1) ) && ( Addr < 0x1FFFFF ) ) { + Protected = 1; + } + } + break; + + case 2: + if (Status1 & TOP_BTM_PROTECT_Msk) { + if( ( Addr > 0x000000) && ( Addr < (0x000000 + (2* AddrJump)- 1 )) ) { + Protected = 1; + } + } else { + if( ( Addr > (0x1FFFFF - ( 2*AddrJump ) + 1) ) && ( Addr < 0x1FFFFF ) ){ + Protected = 1; + } + } + break; + case 3: + if (Status1 & TOP_BTM_PROTECT_Msk) { + if( ( Addr > 0x000000) && ( Addr < (0x000000 + (4 * AddrJump) - 1) )) { + Protected = 1; + } + } else { + if( ( Addr > (0x1FFFFF - ( 4*AddrJump ) + 1) ) && ( Addr < 0x1FFFFF )) { + Protected = 1; + } + } + break; + + case 4: + if (Status1 & TOP_BTM_PROTECT_Msk) { + if( ( Addr > 0x000000) && ( Addr < (0x000000 + (8 * AddrJump) - 1) )) { + Protected = 1; + } + } else { + if( ( Addr > (0x1FFFFF - ( 8*AddrJump ) + 1) ) && ( Addr < 0x1FFFFF )) { + Protected = 1; + } + } + break; + case 5: + if( !(Status1 & SEC_PROTECT_Msk) ) { + if (Status1 & TOP_BTM_PROTECT_Msk) { + if( ( Addr > 0x000000) && ( Addr < (0x000000 + (16 * AddrJump) - 1) )) { + Protected = 1; + } + } else { + if( ( Addr > (0x1FFFFF - ( 16*AddrJump ) + 1) ) && ( Addr < 0x1FFFFF )) { + Protected = 1; + } + } + } + break; + + case 6: + + if( !(Status1 & SEC_PROTECT_Msk) ) { + + if (Status1 & TOP_BTM_PROTECT_Msk) { + if( ( Addr > 0x000000) && ( Addr < (0x000000 + (32 * AddrJump) - 1) )) { + Protected = 1; + } + } + } + break; + } + + return Protected; +} + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ +void S25FL1D_InitFlashInterface(uint8_t Mode) +{ + if(Mode) { + QSPID_Configure(&qspiDma, QspiMemMode, + QSPI_MR_CSMODE_LASTXFER, &qspiDmaInst); + qspiDma.Qspid.qspiMode = (QspiMode_t)QSPI_MR_SMM_MEMORY; + + pDev = (QspiInstFrame_t *)malloc (sizeof(QspiInstFrame_t)); + memset(pDev, 0, sizeof(QspiInstFrame_t)); + pDev->InstFrame.bm.bwidth = QSPI_IFR_WIDTH_SINGLE_BIT_SPI; + + + pMem = (QspiInstFrame_t *)malloc (sizeof(QspiInstFrame_t)); + memset(pMem, 0, sizeof(QspiInstFrame_t)); + pMem->InstFrame.bm.bwidth = QSPI_IFR_WIDTH_SINGLE_BIT_SPI; + } else { + QSPID_Configure(&qspiDma, + SpiMode,(QSPI_MR_CSMODE_LASTXFER | QSPI_MR_DLYCS (20)), + &qspiDmaInst); + qspiDma.Qspid.qspiMode = (QspiMode_t)QSPI_MR_SMM_SPI; + } + + QSPI_ConfigureClock(QSPI, ClockMode_00, QSPI_SCR_SCBR(1)); + + QSPI_Enable(QSPI); + +} + +/** + * \brief Reads and returns the serial flash device ID. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + */ +uint32_t S25FL1D_ReadJedecId(void) +{ + static uint32_t pId; + S25FL1D_SendCommand(READ_JEDEC_ID, 0, &pId, ReadAccess, 3); + + return pId; +} + +/** + * \brief Enables critical writes operation on a serial flash device, such as + * sector protection, status register, etc. + * + * \para pS25fl1 Pointer to an S25FL1 driver instance. + */ +void S25FL1D_QuadMode(uint8_t Enable) +{ + + uint8_t status[3]; + + status[0] = S25FL1D_ReadStatus1(); + status[1] = S25FL1D_ReadStatus2(); + status[2] = S25FL1D_ReadStatus3(); + + if(Enable) { + while(!(status[1] & STATUS_QUAD_ENABLE)) { + status[1] |= STATUS_QUAD_ENABLE ; + S25FL1D_WriteStatus(status); + status[1] = S25FL1D_ReadStatus2(); + Wait(50); + } + } else { + while((status[1] & STATUS_QUAD_ENABLE)) { + status[1] &= (~STATUS_QUAD_ENABLE); + S25FL1D_WriteStatus(status); + status[1] = S25FL1D_ReadStatus2(); + Wait(50); + } + } +} + + +/** + * \brief Enables critical writes operation on a serial flash device, such as + * sector protection, status register, etc. + * + * \para pS25fl1 Pointer to an S25FL1 driver instance. + */ +void S25FL1D_EnableWrap(uint8_t ByetAlign) +{ + + uint8_t status[3]; + + status[0] = S25FL1D_ReadStatus1(); + status[1] = S25FL1D_ReadStatus2(); + status[2] = S25FL1D_ReadStatus3(); + + status[2] |= (ByetAlign << 5); + + pDev->InstFrame.bm.bDummyCycles = 24; + S25FL1D_SendCommand(WRAP_ENABLE,(uint32_t *)&status[2], 0, WriteAccess, 1); + + S25FL1D_WriteVolatileStatus(status); + status[2] = S25FL1D_ReadStatus3(); + Wait(50); +} + + +/** + * \brief Enables critical writes operation on a serial flash device, such as + * sector protection, status register, etc. + * + * \para pS25fl1 Pointer to an S25FL1 driver instance. + */ +void S25FL1D_SetReadLatencyControl(uint8_t Latency) +{ + + uint8_t status[3]; + + status[0] = S25FL1D_ReadStatus(); + status[1] = S25FL1D_ReadStatus2(); + status[2] = S25FL1D_ReadStatus3(); + + status[2] |= Latency; + + qspiDma.Qspid.qspiBuffer.pDataTx = (uint32_t *)&status[2]; + while( (status[2] & STATUS_LATENCY_CTRL) != Latency) { + S25FL1D_WriteVolatileStatus(status); + status[2] = S25FL1D_ReadStatus3(); + Wait(50); + } +} +void S25FL1D_SoftReset(void) +{ + S25FL1D_SendCommand(SOFT_RESET_ENABLE,0, 0, CmdAccess, 0); + S25FL1D_SendCommand(SOFT_RESET, 0, 0, CmdAccess, 0); +} + +/** + * \brief Unprotected the contents of the serial flash device. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * + * \return 0 if the device has been unprotected; otherwise returns + * S25FL1D_ERROR_PROTECTED. + */ +unsigned char S25FL1D_Unprotect(void) +{ + unsigned char status[3]; + /* Get the status register value to check the current protection */ + status[0]= S25FL1D_ReadStatus(); + status[1]= S25FL1D_ReadStatus2(); + status[2]= S25FL1D_ReadStatus3(); + if ((status[0] & STATUS_SWP) == STATUS_SWP_PROTNONE) { + + /* Protection already disabled */ + return 0; + } + + status[0] &= (!STATUS_SWP); + /* Check if sector protection registers are locked */ + if ((status[0] & STATUS_SPRL) == STATUS_SPRL_LOCKED) { + status[0] &= (!STATUS_SPRL); + /* Unprotected sector protection registers by writing the status reg. */ + S25FL1D_WriteStatus(status); + } + S25FL1D_WriteStatus(status); + + /* Check the new status */ + status[0] = S25FL1D_ReadStatus(); + if ((status[0] & (STATUS_SPRL | STATUS_SWP)) != 0) { + return ERROR_PROTECTED; + } else { + + return 0; + } +} + +/** + * \brief Unprotected the contents of the serial flash device. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * + * \return 0 if the device has been unprotected; otherwise returns + * S25FL1D_ERROR_PROTECTED. + */ +unsigned char S25FL1D_Protect(uint32_t StartAddr, uint32_t Size) +{ + unsigned char status[3]; + /* Get the status register value to check the current protection */ + status[0]= S25FL1D_ReadStatus1(); + status[1]= S25FL1D_ReadStatus2(); + status[2]= S25FL1D_ReadStatus3(); + + status[0] &= (!STATUS_SWP); + /* Check if sector protection registers are locked */ + if ((status[0] & STATUS_SPRL) == STATUS_SPRL_LOCKED) { + status[0] &= (!STATUS_SPRL); + /* Unprotected sector protection registers by writing the status reg. */ + S25FL1D_WriteStatus(status); + } + S25FL1D_WriteStatus(status); + + /* Check the new status */ + status[0] = S25FL1D_ReadStatus(); + if ((status[0] & (STATUS_SPRL | STATUS_SWP)) != 0) { + return ERROR_PROTECTED; + } else { + return 0; + } +} + + +/** + * \brief Erases all the content of the memory chip. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * + * \return 0 if the device has been unprotected; otherwise returns + * ERROR_PROTECTED. + */ +unsigned char S25FL1D_EraseChip(void) +{ + char wait_ch[4] = {'\\','|','/','-' }; + uint8_t i=0; + uint8_t Status = STATUS_RDYBSY; + uint8_t ChipStatus= S25FL1D_ReadStatus1(); + + if(ChipStatus & CHIP_PROTECT_Msk) { + TRACE_ERROR("Chip is Protected \n\r"); + TRACE_INFO("Flash Status Register 1 is %x", ChipStatus); + return 1; + } else { + S25FL1D_EnableWrite(); + S25FL1D_SendCommand(CHIP_ERASE_2, 0, 0, CmdAccess, 0); + + while(Status & STATUS_RDYBSY) { + + Wait(200); + printf("Erasing flash memory %c\r", wait_ch[i]); + i++; + Status = S25FL1D_ReadStatus1(); + memory_barrier(); + i = i % 4; + } + printf("\rErasing flash memory done..... 100%%\n\r"); + return 0; + } +} + +/** + *\brief Erases the specified block of the serial firmware dataflash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param address Address of the block to erase. + * + * \return 0 if successful; otherwise returns ERROR_PROTECTED if the + * device is protected or ERROR_BUSY if it is busy executing a command. + */ +unsigned char S25FL1D_EraseSector(unsigned int address) +{ + uint8_t status; + uint8_t Secure = 0; + /* Check that the flash is ready and unprotected */ + status = S25FL1D_ReadStatus1(); + if ((status & STATUS_RDYBSY) != STATUS_RDYBSY_READY) { + TRACE_ERROR("%s : Flash busy\n\r", __FUNCTION__); + return ERROR_BUSY; + } else if (status & BLOCK_PROTECT_Msk) { + if(S25FL1D_CheckProtectedAddr(status, address)) { + TRACE_ERROR("%s : Flash Addrs is protected\n\r", __FUNCTION__); + return ERROR_PROTECTED; + } + } + + /* Enable critical write operation */ + S25FL1D_EnableWrite(); + + if(qspiDma.Qspid.qspiMode) { + pDev->Addr = address; + pDev->InstFrame.bm.bAddrEn = 1; + /* Start the block erase command */ + S25FL1D_SendCommand(BLOCK_ERASE_4K, 0, 0, CmdAccess, 0); + } else { + /* Start the block erase command */ + S25FL1D_MemoryAccess(BLOCK_ERASE_4K, address, 0, 0, WriteAccess, + 0, Secure); + } + /* Wait for transfer to finish */ + S25FL1D_IsBusy(); + return 0; +} + +/** + *\brief Erases the specified 64KB block of the serial firmware dataflash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param address Address of the block to erase. + * + * \return 0 if successful; otherwise returns ERROR_PROTECTED if the + * device is protected or ERROR_BUSY if it is busy executing a command. + */ +unsigned char S25FL1D_Erase64KBlock( unsigned int address) +{ + unsigned char status; + + /* Check that the flash is ready and unprotected */ + status = S25FL1D_ReadStatus(); + if ((status & STATUS_RDYBSY) != STATUS_RDYBSY_READY) { + TRACE_ERROR("S25FL1D_EraseBlock : Flash busy\n\r"); + return ERROR_BUSY; + } + else if ((status & STATUS_SWP) != STATUS_SWP_PROTNONE) { + TRACE_ERROR("EraseBlock : Flash protected\n\r"); + return ERROR_PROTECTED; + } + + /* Enable critical write operation */ + S25FL1D_EnableWrite(); + + if(qspiDma.Qspid.qspiMode) { + pDev->Addr = address; + pDev->InstFrame.bm.bAddrEn = 1; + /* Start the block erase command */ + S25FL1D_SendCommand(BLOCK_ERASE_64K, 0, 0, CmdAccess, 0); + } else { +#ifdef USE_QSPI_DMA + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; +#endif + /* Start the block erase command */ + S25FL1D_MemoryAccess(BLOCK_ERASE_64K, address, 0, 0, WriteAccess, 0, 0); +#ifdef USE_QSPI_DMA + QSPID_DisableSpiChannel(&qspiDma); +#endif + } + + /* Wait for transfer to finish */ + S25FL1D_IsBusy(); + return 0; +} + +/** + * \brief Writes data at the specified address on the serial firmware dataflash. + * The page(s) to program must have been erased prior to writing. This function + * handles page boundary crossing automatically. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param pData Data buffer. + * \param size Number of bytes in buffer. + * \param address Write address. + * + * \return 0 if successful; otherwise, returns ERROR_PROGRAM is there has + * been an error during the data programming. + */ +unsigned char S25FL1D_Write( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t Secure) +{ + unsigned int i = 0; + + uint32_t NumberOfWrites = (size >> 8); // ( (Size / pagezize) ) + uint32_t Addrs = address; + +#ifdef USE_QSPI_DMA + if(qspiDma.Qspid.qspiMode) { + if(QSPID_EnableQspiTxChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } else { + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } +#endif + // if less than page size + if(NumberOfWrites == 0) { + S25FL1D_EnableWrite(); + S25FL1D_MemoryAccess(BYTE_PAGE_PROGRAM , Addrs, pData, 0, + WriteAccess, size, Secure); + // multiple page + } else { + for(i=0; i< NumberOfWrites; i++) { + S25FL1D_EnableWrite(); + S25FL1D_MemoryAccess(BYTE_PAGE_PROGRAM , Addrs, pData, 0, + WriteAccess, PAGE_SIZE, Secure); + S25FL1D_IsBusy(); + pData += (PAGE_SIZE >> 2); + Addrs += PAGE_SIZE; + } + if(size % PAGE_SIZE ) { + S25FL1D_EnableWrite(); + S25FL1D_MemoryAccess(BYTE_PAGE_PROGRAM , Addrs, pData, 0, + WriteAccess, (size - (NumberOfWrites * PAGE_SIZE)), + Secure); + S25FL1D_IsBusy(); + } + } +#ifdef USE_QSPI_DMA + + if(qspiDma.Qspid.qspiMode) { + QSPID_DisableQspiTxChannel(&qspiDma); + } else { + QSPID_DisableSpiChannel(&qspiDma); + } + +#endif + S25FL1D_DisableWrite(); + return 0; +} + +/** + * \brief Reads data from the specified address on the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param pData Data buffer. + * \param size Number of bytes to read. + * \param address Read address. + * + * \return 0 if successful; otherwise, fail. + */ +unsigned char S25FL1D_Read( + uint32_t *pData, + uint32_t size, + uint32_t address) +{ + uint8_t Secure = 0; + +#ifdef USE_QSPI_DMA + if(qspiDma.Qspid.qspiMode) { + if(QSPID_EnableQspiRxChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } else { + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } +#endif + + S25FL1D_MemoryAccess(READ_ARRAY , address, 0, pData, + ReadAccess, size , Secure); + +#ifdef USE_QSPI_DMA + + if(qspiDma.Qspid.qspiMode) { + QSPID_DisableQspiRxChannel(&qspiDma); + } else { + QSPID_DisableSpiChannel(&qspiDma); + } +#endif + return 0; + +} + +/** + * \brief Reads data from the specified address on the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param pData Data buffer. + * \param size Number of bytes to read. + * \param address Read address. + * + * \return 0 if successful; otherwise, fail. + */ +unsigned char S25FL1D_ReadDual( + uint32_t *pData, + uint32_t size, + uint32_t address) +{ + + uint8_t Secure = 0; +#ifdef USE_QSPI_DMA + if(qspiDma.Qspid.qspiMode) { + if(QSPID_EnableQspiRxChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } else { + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } +#endif + pMem->InstFrame.bm.bDummyCycles = 8; + pMem->InstFrame.bm.bwidth = QSPI_IFR_WIDTH_DUAL_OUTPUT; + + S25FL1D_MemoryAccess(READ_ARRAY_DUAL , address, 0, pData, + ReadAccess, size, Secure); + +#ifdef USE_QSPI_DMA + while(QSPID_IsBusy(&qspiDma.progress) ) { + Wait(1); + } + if(qspiDma.Qspid.qspiMode) { + QSPID_DisableQspiRxChannel(&qspiDma); + } else { + QSPID_DisableSpiChannel(&qspiDma); + } +#endif + return 0; +} + +/** + * \brief Reads data from the specified address on the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param pData Data buffer. + * \param size Number of bytes to read. + * \param address Read address. + * + * \return 0 if successful; otherwise, fail. + */ +unsigned char S25FL1D_ReadQuad( + uint32_t *pData, + uint32_t size, + uint32_t address) +{ + uint8_t Secure = 0; +#ifdef USE_QSPI_DMA + if(qspiDma.Qspid.qspiMode) { + if(QSPID_EnableQspiRxChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } else { + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } +#endif + pMem->InstFrame.bm.bDummyCycles = 8; + pMem->InstFrame.bm.bwidth = QSPI_IFR_WIDTH_QUAD_OUTPUT; + S25FL1D_MemoryAccess(READ_ARRAY_QUAD, address, 0, pData, + ReadAccess, size, Secure); + +#ifdef USE_QSPI_DMA + while(QSPID_IsBusy(&qspiDma.progress) ) { + Wait(1); + } + if(qspiDma.Qspid.qspiMode) { + QSPID_DisableQspiRxChannel(&qspiDma); + } else { + QSPID_DisableSpiChannel(&qspiDma); + } +#endif + return 0; +} + +/** + * \brief Reads data from the specified address on the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param pData Data buffer. + * \param size Number of bytes to read. + * \param address Read address. + * + * \return 0 if successful; otherwise, fail. + */ +unsigned char S25FL1D_ReadDualIO( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t ContMode, + uint8_t Secure) +{ +#ifdef USE_QSPI_DMA + if(qspiDma.Qspid.qspiMode) { + if(QSPID_EnableQspiRxChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } else { + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } +#endif + pMem->InstFrame.bm.bDummyCycles = 4; + if(ContMode) { + pMem->InstFrame.bm.bOptLen + = (QSPI_IFR_OPTL_OPTION_4BIT >> QSPI_IFR_OPTL_Pos); + qspiDma.Qspid.qspiCommand.Option= 0x2; + pMem->InstFrame.bm.bContinuesRead = ContMode; + pMem->InstFrame.bm.bDummyCycles = 3; + } + pMem->InstFrame.bm.bwidth = QSPI_IFR_WIDTH_DUAL_IO; + S25FL1D_MemoryAccess(READ_ARRAY_DUAL_IO , address, 0, + pData, ReadAccess, size, Secure); + pMem->InstFrame.bm.bOptEn = 0; + pMem->InstFrame.bm.bContinuesRead = 0; +#ifdef USE_QSPI_DMA + while(QSPID_IsBusy(&qspiDma.progress) ) { + Wait(1); + } + if(qspiDma.Qspid.qspiMode) { + QSPID_DisableQspiRxChannel(&qspiDma); + } else { + QSPID_DisableSpiChannel(&qspiDma); + } +#endif + return 0; +} + +/** + * \brief Reads data from the specified address on the serial flash. + * + * \param pS25fl1 Pointer to an S25FL1 driver instance. + * \param pData Data buffer. + * \param size Number of bytes to read. + * \param address Read address. + * + * \return 0 if successful; otherwise, fail. + */ +unsigned char S25FL1D_ReadQuadIO( + uint32_t *pData, + uint32_t size, + uint32_t address, + uint8_t ContMode, + uint8_t Secure) +{ +#ifdef USE_QSPI_DMA + if(qspiDma.Qspid.qspiMode) { + if(QSPID_EnableQspiRxChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } else { + if(QSPID_EnableSpiChannel(&qspiDma) == QSPID_ERROR_LOCK) + return 1; + } +#endif + pMem->InstFrame.bm.bDummyCycles = 6; + if(ContMode) { + pMem->InstFrame.bm.bOptLen + = (QSPI_IFR_OPTL_OPTION_4BIT >> QSPI_IFR_OPTL_Pos); + qspiDma.Qspid.qspiCommand.Option= 0x2; + pMem->InstFrame.bm.bContinuesRead = ContMode; + pMem->InstFrame.bm.bDummyCycles = 5; + pMem->InstFrame.bm.bOptEn = 1; + } + + pMem->InstFrame.bm.bwidth = QSPI_IFR_WIDTH_QUAD_IO; + S25FL1D_MemoryAccess(READ_ARRAY_QUAD_IO , address, 0, + pData, ReadAccess, size, Secure); + pMem->InstFrame.bm.bOptEn = 0; + pMem->InstFrame.bm.bContinuesRead = 0; +#ifdef USE_QSPI_DMA + while(QSPID_IsBusy(&qspiDma.progress) ) { + Wait(1); + } + if(qspiDma.Qspid.qspiMode) { + QSPID_DisableQspiRxChannel(&qspiDma); + } else { + QSPID_DisableSpiChannel(&qspiDma); + } +#endif + return 0; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/syscalls.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/syscalls.c new file mode 100644 index 000000000..09554f91d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/syscalls.c @@ -0,0 +1,153 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file syscalls.c + * + * Implementation of newlib syscall. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +#include "board.h" + +#include +#include +#include +#include +#include + +/*---------------------------------------------------------------------------- + * Exported variables + *----------------------------------------------------------------------------*/ + +#undef errno +extern int errno; +extern int _sheap; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void _exit( int status ); +extern void _kill( int pid, int sig ); +extern int _getpid ( void ); + +extern caddr_t _sbrk ( int incr ) +{ + static unsigned char *heap = NULL; + unsigned char *prev_sheap; + + if ( heap == NULL ) { + heap = (unsigned char *)&_sheap; + } + prev_sheap = heap; + + heap += incr; + + return (caddr_t) prev_sheap; +} + +extern int link( char *old, char *new ) +{ + ( void ) old; + ( void ) new; + return -1; +} + +extern int _close( int file ) +{ + ( void ) file; + return -1; +} + +extern int _fstat( int file, struct stat *st ) +{ + ( void ) file; + st->st_mode = S_IFCHR; + + return 0; +} + +extern int _isatty( int file ) +{ + ( void ) file; + return 1; +} + +extern int _lseek( int file, int ptr, int dir ) +{ + ( void ) file; + ( void ) ptr; + ( void ) dir; + return 0; +} + +extern int _read(int file, char *ptr, int len) +{ + ( void ) file; + ( void ) ptr; + ( void ) len; + return 0; +} + +extern int _write( int file, char *ptr, int len ) +{ + int iIndex; + + ( void ) file; + + // for (; *ptr != 0; ptr++ ) + for ( iIndex=0; iIndex < len; iIndex++, ptr++ ) { + DBG_PutChar( *ptr ); + } + + return iIndex; +} + +extern void _exit( int status ) +{ + printf( "Exiting with status %d.\n", status ); + for (;;); +} + +extern void _kill( int pid, int sig ) +{ + ( void ) pid; + ( void ) sig; + return; +} + +extern int _getpid ( void ) +{ + return -1; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/trace.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/trace.c new file mode 100644 index 000000000..5f22c90a4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/trace.c @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Internal variables + *----------------------------------------------------------------------------*/ + +/** Trace level can be set at applet initialization */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) +uint32_t dwTraceLevel = TRACE_LEVEL; +#endif + +/** + * Initializes the U(S)ART Console + * + * \param dwBaudRate U(S)ART baud-rate. + * \param dwMCk Master clock frequency. + */ +extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) +{ + const Pin pinsUART0[] = { PINS_UART0 }; + + PIO_Configure( pinsUART0, PIO_LISTSIZE( pinsUART0 ) ); + + DBG_Configure( dwBaudRate, dwMCk ); +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/wm8904.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/wm8904.c new file mode 100644 index 000000000..5aff8ccc3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libboard_samv7-ek/source/wm8904.c @@ -0,0 +1,466 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation WM8904 driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct { + uint16_t value; + uint8_t address; + }WM8904_PARA; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Read data from WM8904 Register. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param regAddr Register address to read. + * \return value in the given register. + */ +uint16_t WM8904_Read(Twid *pTwid, + uint32_t device, + uint32_t regAddr) +{ + uint16_t bitsDataRegister; + uint8_t Tdata[2]={0,0}; + + TWID_Read(pTwid, device, regAddr, 1, Tdata, 2, 0); + bitsDataRegister = (Tdata[0] << 8) | Tdata[1]; + return bitsDataRegister; +} + +/** + * \brief Write data to WM8904 Register. + * + * \param pTwid Pointer to twi driver structure + * \param device Twi slave address. + * \param regAddr Register address to read. + * \param data Data to write + */ +void WM8904_Write(Twid *pTwid, + uint32_t device, + uint32_t regAddr, + uint16_t data) +{ + uint8_t tmpData[2]; + + tmpData[0] = (data & 0xff00) >> 8; + tmpData[1] = data & 0xff; + TWID_Write(pTwid, device, regAddr, 1, tmpData, 2, 0); +} + +static WM8904_PARA wm8904_access_slow[]= +{ + { 0x0000, 0}, /** R0 - SW Reset and ID */ + { 0x001A, 4}, /** R4 - Bias Control 0 */ + { 0x0047, 5}, /** R5 - VMID Control 0 */ /*insert_delay_ms 5*/ + + { 0x0043, 5}, /** R5 - VMID Control 0 */ + { 0x000B, 4}, /** R4 - Bias Control 0 */ + + { 0x0003, 0x0C}, /** R12 - Power Management 0 CC */ + + { 0x0003, 0x0E}, /** R14 - Power Management 2 */ + { 0x000C, 0x12}, /** R18 - Power Management 6 */ + { 0x0000, 0x21}, /** R33 - DAC Digital 1 */ + { 0x0000, 0x3D}, /** R61 - Analogue OUT12 ZC */ + { 0x0001, 0x62}, /** R98 - Charge Pump 0 */ + { 0x0005, 0x68}, /** R104 - Class W 0 */ + + //FLL setting,32.768KHZ MCLK input,12.288M output. + { 0x0000, 0x74}, /** R116 - FLL Control 1 */ + { 0x0704, 0x75}, /** R117 - FLL Control 2 */ + { 0x8000, 0x76}, /** R118 - FLL Control 3 */ + { 0x1760, 0x77}, /** R119 - FLL Control 4 */ + { 0x0005, 0x74}, /** R116 - FLL Control 1 */ /*insert_delay_ms 5*/ + + { 0x0C05, 0x15}, /** R21 - Clock Rates 1 */ + { 0x845E, 0x14}, /** R20 - Clock Rates 0 */ + { 0x4006, 0x16}, /** R22 - Clock Rates 2 */ + + //WM8904 IIS master + //BCLK=12.288MHz/8=1.536MHz + //LRCK=1.536MHz/32=48KHz + //{ 0x0042, 0x18}, /** R24 - Audio Interface 0 */ + { 0x0042, 0x19}, /** R25 - Audio Interface 1 */ + { 0x00E8, 0x1A}, /** R26 - Audio Interface 2 */ + { 0x0820, 0x1B}, /** R27 - Audio Interface 3 */ + ////////////////ADC + + { 0x0003, 0x0C}, /** R12 - Power Management 0 */ + { 0x000F, 0x12}, /** R18 - Power Management 6 */ /*insert_delay_ms 5*/ + + { 0x0010, 0x2C}, /** R44 - Analogue Left Input 0 */ + { 0x0010, 0x2D}, /** R45 - Analogue Right Input 0 */ + { 0x0044, 0x2E}, /** R46 - Analogue Left Input 1 */ + { 0x0044, 0x2F}, /** R47 - Analogue Right Input 1 */ + + { 0x0011, 0x5A}, /** R90 - Analogue HP 0 */ + { 0x0033, 0x5A}, /** R90 - Analogue HP 0 */ + + { 0x000F, 0x43}, /** R67 - DC Servo 0 */ + { 0x00F0, 0x44}, /** R68 - DC Servo 1 */ /*insert_delay_ms 100*/ + + { 0x0077, 0x5A}, /** R90 - Analogue HP 0 */ + { 0x00FF, 0x5A}, /** R90 - Analogue HP 0 */ + { 0x00B9, 0x39}, /** R57 - Analogue OUT1 Left */ + { 0x00B9, 0x3A}, /** R58 - Analogue OUT1 Right */ +}; + +static WM8904_PARA wm8904_access_main[] = +{ + //{ 0x8904, 0}, /** R0 - SW Reset and ID */ + //{ 0x0000, 1}, /** R1 - Revision */ + //{ 0x0000, 2}, /** R2 */ + //{ 0x0000, 3}, /** R3 */ + { 0x0019, 4}, /** R4 - Bias Control 0 */ + { 0x0043, 5}, /** R5 - VMID Control 0 */ + //{ 0x0003, 6}, /** R6 - Mic Bias Control 0 */ + //{ 0xC000, 7}, /** R7 - Mic Bias Control 1 */ + //{ 0x001E, 8}, /** R8 - Analogue DAC 0 */ + //{ 0xFFFF, 9}, /** R9 - mic Filter Control */ + //{ 0x0001, 10}, /** R10 - Analogue ADC 0 */ + //{ 0x0000, 11}, /** R11 */ + { 0x0003, 12}, /** R12 - Power Management 0 */ + //{ 0x0000, 13}, /** R13 */ + { 0x0003, 14}, /** R14 - Power Management 2 */ + //{ 0x0003, 15}, /** R15 - Power Management 3 */ + //{ 0x0000, 16}, /** R16 */ + //{ 0x0000, 17}, /** R17 */ + { 0x000F, 18}, /** R18 - Power Management 6 */ + //{ 0x0000, 19}, /** R19 */ + { 0x845E, 20}, /** R20 - Clock Rates 0 */ + //{ 0x3C07, 21}, /** R21 - Clock Rates 1 */ + { 0x0006, 22}, /** R22 - Clock Rates 2 */ + //{ 0x0000, 23}, /** R23 */ + //{ 0x1FFF, 24}, /** R24 - Audio Interface 0 */ + { 0x404A, 25}, /** R25 - Audio Interface 1 */ + //{ 0x0004, 26}, /** R26 - Audio Interface 2 */ + { 0x0840, 27}, /** R27 - Audio Interface 3 */ + //{ 0x0000, 28}, /** R28 */ + //{ 0x0000, 29}, /** R29 */ + //{ 0x00FF, 30}, /** R30 - DAC Digital Volume Left */ + //{ 0x00FF, 31}, /** R31 - DAC Digital Volume Right */ + //{ 0x0FFF, 32}, /** R32 - DAC Digital 0 */ + { 0x0000, 33}, /** R33 - DAC Digital 1 */ + //{ 0x0000, 34}, /** R34 */ + //{ 0x0000, 35}, /** R35 */ + //{ 0x00FF, 36}, /** R36 - ADC Digital Volume Left */ + //{ 0x00FF, 37}, /** R37 - ADC Digital Volume Right */ + //{ 0x0073, 38}, /** R38 - ADC Digital 0 */ + //{ 0x1800, 39}, /** R39 - Digital Microphone 0 */ + //{ 0xDFEF, 40}, /** R40 - DRC 0 */ + //{ 0xFFFF, 41}, /** R41 - DRC 1 */ + //{ 0x003F, 42}, /** R42 - DRC 2 */ + //{ 0x07FF, 43}, /** R43 - DRC 3 */ + { 0x0005, 44}, /** R44 - Analogue Left Input 0 */ + { 0x0005, 45}, /** R45 - Analogue Right Input 0 */ + { 0x0000, 46}, /** R46 - Analogue Left Input 1 */ + { 0x0000, 47}, /** R47 - Analogue Right Input 1 */ + //{ 0x0000, 48}, /** R48 */ + //{ 0x0000, 49}, /** R49 */ + //{ 0x0000, 50}, /** R50 */ + //{ 0x0000, 51}, /** R51 */ + //{ 0x0000, 52}, /** R52 */ + //{ 0x0000, 53}, /** R53 */ + //{ 0x0000, 54}, /** R54 */ + //{ 0x0000, 55}, /** R55 */ + //{ 0x0000, 56}, /** R56 */ + //{ 0x017F, 57}, /** R57 - Analogue OUT1 Left */ + { 0x00AD, 58}, /** R58 - Analogue OUT1 Right */ + //{ 0x017F, 59}, /** R59 - Analogue OUT2 Left */ + //{ 0x017F, 60}, /** R60 - Analogue OUT2 Right */ + //{ 0x000F, 61}, /** R61 - Analogue OUT12 ZC */ + //{ 0x0000, 62}, /** R62 */ + //{ 0x0000, 63}, /** R63 */ + //{ 0x0000, 64}, /** R64 */ + //{ 0x0000, 65}, /** R65 */ + //{ 0x0000, 66}, /** R66 */ + { 0x0003, 67}, /** R67 - DC Servo 0 */ + //{ 0xFFFF, 68}, /** R68 - DC Servo 1 */ + //{ 0x0F0F, 69}, /** R69 - DC Servo 2 */ + //{ 0x0000, 70}, /** R70 */ + //{ 0x007F, 71}, /** R71 - DC Servo 4 */ + //{ 0x007F, 72}, /** R72 - DC Servo 5 */ + //{ 0x00FF, 73}, /** R73 - DC Servo 6 */ + //{ 0x00FF, 74}, /** R74 - DC Servo 7 */ + //{ 0x00FF, 75}, /** R75 - DC Servo 8 */ + //{ 0x00FF, 76}, /** R76 - DC Servo 9 */ + //{ 0x0FFF, 77}, /** R77 - DC Servo Readback 0 */ + //{ 0x0000, 78}, /** R78 */ + //{ 0x0000, 79}, /** R79 */ + //{ 0x0000, 80}, /** R80 */ + //{ 0x0000, 81}, /** R81 */ + //{ 0x0000, 82}, /** R82 */ + //{ 0x0000, 83}, /** R83 */ + //{ 0x0000, 84}, /** R84 */ + //{ 0x0000, 85}, /** R85 */ + //{ 0x0000, 86}, /** R86 */ + //{ 0x0000, 87}, /** R87 */ + //{ 0x0000, 88}, /** R88 */ + //{ 0x0000, 89}, /** R89 */ + { 0x00FF, 90}, /** R90 - Analogue HP 0 */ + //{ 0x0000, 91}, /** R91 */ + //{ 0x0000, 92}, /** R92 */ + //{ 0x0000, 93}, /** R93 */ + //{ 0x00FF, 94}, /** R94 - Analogue Lineout 0 */ + //{ 0x0000, 95}, /** R95 */ + //{ 0x0000, 96}, /** R96 */ + //{ 0x0000, 97}, /** R97 */ + { 0x0001, 98}, /** R98 - Charge Pump 0 */ + //{ 0x0000, 99}, /** R99 */ + //{ 0x0000, 100}, /** R100 */ + //{ 0x0000, 101}, /** R101 */ + //{ 0x0000, 102}, /** R102 */ + //{ 0x0000, 103}, /** R103 */ + { 0x0005, 104}, /** R104 - Class W 0 */ + //{ 0x0000, 105}, /** R105 */ + //{ 0x0000, 106}, /** R106 */ + //{ 0x0000, 107}, /** R107 */ + //{ 0x011F, 108}, /** R108 - Write Sequencer 0 */ + //{ 0x7FFF, 109}, /** R109 - Write Sequencer 1 */ + //{ 0x4FFF, 110}, /** R110 - Write Sequencer 2 */ + //{ 0x003F, 111}, /** R111 - Write Sequencer 3 */ + //{ 0x03F1, 112}, /** R112 - Write Sequencer 4 */ + //{ 0x0000, 113}, /** R113 */ + //{ 0x0000, 114}, /** R114 */ + //{ 0x0000, 115}, /** R115 */ + { 0x0004, 116}, /** R116 - FLL Control 1 */ + { 0x0704, 117}, /** R117 - FLL Control 2 */ + { 0x8000, 118}, /** R118 - FLL Control 3 */ + { 0x1760, 119}, /** R119 - FLL Control 4 */ + //{ 0x001B, 120}, /** R120 - FLL Control 5 */ + //{ 0x0014, 121}, /** R121 - GPIO Control 1 */ + //{ 0x0010, 122}, /** R122 - GPIO Control 2 */ + //{ 0x0010, 123}, /** R123 - GPIO Control 3 */ + //{ 0x0000, 124}, /** R124 - GPIO Control 4 */ + //{ 0x0000, 125}, /** R125 */ + //{ 0x000A, 126}, /** R126 - Digital Pulls */ + //{ 0x07FF, 127}, /** R127 - Interrupt Status */ + //{ 0x03FF, 128}, /** R128 - Interrupt Status Mask */ + //{ 0x03FF, 129}, /** R129 - Interrupt Polarity */ + //{ 0x03FF, 130}, /** R130 - Interrupt Debounce */ + //{ 0x0000, 131}, /** R131 */ + //{ 0x0000, 132}, /** R132 */ + //{ 0x0000, 133}, /** R133 */ + //{ 0x0001, 134}, /** R134 - EQ1 */ + //{ 0x001F, 135}, /** R135 - EQ2 */ + //{ 0x001F, 136}, /** R136 - EQ3 */ + //{ 0x001F, 137}, /** R137 - EQ4 */ + //{ 0x001F, 138}, /** R138 - EQ5 */ + //{ 0x001F, 139}, /** R139 - EQ6 */ + //{ 0xFFFF, 140}, /** R140 - EQ7 */ + //{ 0xFFFF, 141}, /** R141 - EQ8 */ + //{ 0xFFFF, 142}, /** R142 - EQ9 */ + //{ 0xFFFF, 143}, /** R143 - EQ10 */ + //{ 0xFFFF, 144}, /** R144 - EQ11 */ + //{ 0xFFFF, 145}, /** R145 - EQ12 */ + //{ 0xFFFF, 146}, /** R146 - EQ13 */ + //{ 0xFFFF, 147}, /** R147 - EQ14 */ + //{ 0xFFFF, 148}, /** R148 - EQ15 */ + //{ 0xFFFF, 149}, /** R149 - EQ16 */ + //{ 0xFFFF, 150}, /** R150 - EQ17 */ + //{ 0xFFFF, 151}, /** R151wm8523_dai - EQ18 */ + //{ 0xFFFF, 152}, /** R152 - EQ19 */ + //{ 0xFFFF, 153}, /** R153 - EQ20 */ + //{ 0xFFFF, 154}, /** R154 - EQ21 */ + //{ 0xFFFF, 155}, /** R155 - EQ22 */ + //{ 0xFFFF, 156}, /** R156 - EQ23 */ + //{ 0xFFFF, 157}, /** R157 - EQ24 */ + //{ 0x0000, 158}, /** R158 */ + //{ 0x0000, 159}, /** R159 */ + //{ 0x0000, 160}, /** R160 */ + //{ 0x0002, 161}, /** R161 - Control Interface Test 1 */ + //{ 0x0000, 162}, /** R162 */ + //{ 0x0000, 163}, /** R163 */ + //{ 0x0000, 164}, /** R164 */ + //{ 0x0000, 165}, /** R165 */ + //{ 0x0000, 166}, /** R166 */ + //{ 0x0000, 167}, /** R167 */ + //{ 0x0000, 168}, /** R168 */ + //{ 0x0000, 169}, /** R169 */ + //{ 0x0000, 170}, /** R170 */ + //{ 0x0000, 171}, /** R171 */ + //{ 0x0000, 172}, /** R172 */ + //{ 0x0000, 173}, /** R173 */ + //{ 0x0000, 174}, /** R174 */ + //{ 0x0000, 175}, /** R175 */ + //{ 0x0000, 176}, /** R176 */ + //{ 0x0000, 177}, /** R177 */ + //{ 0x0000, 178}, /** R178 */ + //{ 0x0000, 179}, /** R179 */ + //{ 0x0000, 180}, /** R180 */ + //{ 0x0000, 181}, /** R181 */ + //{ 0x0000, 182}, /** R182 */ + //{ 0x0000, 183}, /** R183 */ + //{ 0x0000, 184}, /** R184 */ + //{ 0x0000, 185}, /** R185 */ + //{ 0x0000, 186}, /** R186 */ + //{ 0x0000, 187}, /** R187 */ + //{ 0x0000, 188}, /** R188 */ + //{ 0x0000, 189}, /** R189 */ + //{ 0x0000, 190}, /** R190 */ + //{ 0x0000, 191}, /** R191 */ + //{ 0x0000, 192}, /** R192 */ + //{ 0x0000, 193}, /** R193 */ + //{ 0x0000, 194}, /** R194 */ + //{ 0x0000, 195}, /** R195 */ + //{ 0x0000, 196}, /** R196 */ + //{ 0x0000, 197}, /** R197 */ + //{ 0x0000, 198}, /** R198 */ + //{ 0x0000, 199}, /** R199 */ + //{ 0x0000, 200}, /** R200 */ + //{ 0x0000, 201}, /** R201 */ + //{ 0x0000, 202}, /** R202 */ + //{ 0x0000, 203}, /** R203 */ + //{ 0x0070, 204}, /** R204 - Analogue Output Bias 0 */ + //{ 0x0000, 205}, /** R205 */ + //{ 0x0000, 206}, /** R206 */ + //{ 0x0000, 207}, /** R207 */ + //{ 0x0000, 208}, /** R208 */ + //{ 0x0000, 209}, /** R209 */ + //{ 0x0000, 210}, /** R210 */ + //{ 0x0000, 211}, /** R211 */ + //{ 0x0000, 212}, /** R212 */ + //{ 0x0000, 213}, /** R213 */ + //{ 0x0000, 214}, /** R214 */ + //{ 0x0000, 215}, /** R215 */ + //{ 0x0000, 216}, /** R216 */ + //{ 0x0000, 217}, /** R217 */ + //{ 0x0000, 218}, /** R218 */ + //{ 0x0000, 219}, /** R219 */ + //{ 0x0000, 220}, /** R220 */ + //{ 0x0000, 221}, /** R221 */ + //{ 0x0000, 222}, /** R222 */ + //{ 0x0000, 223}, /** R223 */ + //{ 0x0000, 224}, /** R224 */ + //{ 0x0000, 225}, /** R225 */ + //{ 0x0000, 226}, /** R226 */ + //{ 0x0000, 227}, /** R227 */ + //{ 0x0000, 228}, /** R228 */ + //{ 0x0000, 229}, /** R229 */ + //{ 0x0000, 230}, /** R230 */ + //{ 0x0000, 231}, /** R231 */ + //{ 0x0000, 232}, /** R232 */ + //{ 0x0000, 233}, /** R233 */ + //{ 0x0000, 234}, /** R234 */ + //{ 0x0000, 235}, /** R235 */ + //{ 0x0000, 236}, /** R236 */ + //{ 0x0000, 237}, /** R237 */ + //{ 0x0000, 238}, /** R238 */ + //{ 0x0000, 239}, /** R239 */ + //{ 0x0000, 240}, /** R240 */ + //{ 0x0000, 241}, /** R241 */ + //{ 0x0000, 242}, /** R242 */ + //{ 0x0000, 243}, /** R243 */ + //{ 0x0000, 244}, /** R244 */ + //{ 0x0000, 245}, /** R245 */ + //{ 0x0000, 246}, /** R246 */ + //{ 0x0000, 247}, /** R247 - FLL NCO Test 0 */ + //{ 0x0019, 248}, /** R248 - FLL NCO Test 1 */ + { 0x55AA, 255} /** end */ +}; + +uint8_t WM8904_Init(Twid *pTwid, uint32_t device, uint32_t PCK) +{ + uint8_t count, size; + uint16_t data = 0; + + // Reset (write Reg@0x0 to reset) + WM8904_Write(pTwid, device, 0, 0xFFFF); + + for(data=0;data<1000;data++); + //wait ready + while(data!=0x8904) + data=WM8904_Read(pTwid, device, 0); + + if (PMC_MCKR_CSS_SLOW_CLK == PCK) { + size = sizeof(wm8904_access_slow) / 4 + 1; + for(count=0; count +#include +#include +#include + +/* Define WEAK attribute */ +#if defined ( __CC_ARM ) + #define WEAK __attribute__ ((weak)) +#elif defined ( __ICCARM__ ) + #define WEAK __weak +#elif defined ( __GNUC__ ) + #define WEAK __attribute__ ((weak)) +#endif + +/* Define Compiler name of tool chains */ +#if defined ( __CC_ARM ) + #define COMPILER_NAME "KEIL" +#elif defined ( __ICCARM__ ) + #define COMPILER_NAME "IAR" +#elif defined ( __GNUC__ ) + #define COMPILER_NAME "GCC" +#endif + +/* Define NO_INIT attribute */ +#if defined ( __CC_ARM ) + #define NO_INIT +#elif defined ( __ICCARM__ ) + #define NO_INIT __no_init +#elif defined ( __GNUC__ ) + #define NO_INIT +#endif + + +/* Define memory sync for tool chains */ +#if defined ( __CC_ARM ) + #define memory_sync() __dsb(15);__isb(15); +#elif defined ( __ICCARM__ ) + #define memory_sync() __DSB();__ISB(); +#elif defined ( __GNUC__ ) + #define memory_sync() __DSB();__ISB(); +#endif + +/* Define memory barrier for tool chains */ +#if defined ( __CC_ARM ) + #define memory_barrier() __dmb(15); +#elif defined ( __ICCARM__ ) + #define memory_barrier() __DMB(); +#elif defined ( __GNUC__ ) + #define memory_barrier() __DMB(); +#endif + +/*! \name Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * May be used only within macros with the tokens passed as arguments if the tokens are \#defined. + * + * For example, writing TPASTE2(U, WIDTH) within a macro \#defined by + * UTYPE(WIDTH) and invoked as UTYPE(UL_WIDTH) with UL_WIDTH \#defined as 32 is + * equivalent to writing U32. + */ +//! @{ +#define TPASTE2( a, b) a##b +#define TPASTE3( a, b, c) a##b##c +//! @} + +/*! \name Absolute Token Paste + * + * Paste N preprocessing tokens together, these tokens being allowed to be \#defined. + * + * No restriction of use if the tokens are \#defined. + * + * For example, writing ATPASTE2(U, UL_WIDTH) anywhere with UL_WIDTH \#defined + * as 32 is equivalent to writing U32. + */ +//! @{ +#define ATPASTE2( a, b) TPASTE2( a, b) +#define ATPASTE3( a, b, c) TPASTE3( a, b, c) +//! @} + + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent structure and union + * definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent structure and union + * definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined ( __CC_ARM ) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined ( __ICCARM__ ) + #define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined ( __GNUC__ ) + #define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Set aligned boundary. + */ +#if defined ( __CC_ARM ) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined ( __ICCARM__ ) + #define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined ( __GNUC__ ) + #define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Set word-aligned boundary. + */ + +#if defined ( __CC_ARM ) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#elif defined ( __ICCARM__ ) + #define COMPILER_WORD_ALIGNED COMPILER_PRAGMA(data_alignment = 4) +#elif defined ( __GNUC__ ) + #define COMPILER_WORD_ALIGNED __attribute__((__aligned__(4))) +#endif + + + +/*! \name Mathematics + * + * The same considerations as for clz and ctz apply here but GCC does not + * provide built-in functions to access the assembly instructions abs, min and + * max and it does not produce them by itself in most cases, so two sets of + * macros are defined here: + * - Abs, Min and Max to apply to constant expressions (values known at + * compile time); + * - abs, min and max to apply to non-constant expressions (values unknown at + * compile time), abs is found in stdlib.h. + */ +//! @{ + +/*! \brief Takes the absolute value of \a a. + * + * \param a Input value. + * + * \return Absolute value of \a a. + * + * \note More optimized if only used with values known at compile time. + */ +#define Abs(a) (((a) < 0 ) ? -(a) : (a)) + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Min(a, b) (((a) < (b)) ? (a) : (b)) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values known at compile time. + */ +#define Max(a, b) (((a) > (b)) ? (a) : (b)) + +// abs() is already defined by stdlib.h + +/*! \brief Takes the minimal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Minimal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define min(a, b) Min(a, b) + +/*! \brief Takes the maximal value of \a a and \a b. + * + * \param a Input value. + * \param b Input value. + * + * \return Maximal value of \a a and \a b. + * + * \note More optimized if only used with values unknown at compile time. + */ +#define max(a, b) Max(a, b) + +//! @} + +#define be32_to_cpu(x) __REV(x) +#define cpu_to_be32(x) __REV(x) +#define BE32_TO_CPU(x) __REV(x) +#define CPU_TO_BE32(x) __REV(x) + +/** + * \def UNUSED + * \brief Marking \a v as a unused parameter or value. + */ +#define UNUSED(v) (void)(v) + +/** + * \weakgroup interrupt_group + * + * @{ + */ + +/** + * \name Interrupt Service Routine definition + * + * @{ + */ + +/** + * \brief Initialize interrupt vectors + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to initialize them, except defined the vector function with + * right name. + * + * This must be called prior to \ref irq_register_handler. + */ +# define irq_initialize_vectors() \ + do { \ + } while(0) + +/** + * \brief Register handler for interrupt + * + * For NVIC the interrupt vectors are put in vector table. So nothing + * to do to register them, except defined the vector function with + * right name. + * + * Usage: + * \code + irq_initialize_vectors(); + irq_register_handler(foo_irq_handler); +\endcode + * + * \note The function \a func must be defined with the \ref ISR macro. + * \note The functions prototypes can be found in the device exception header + * files (exceptions.h). + */ +# define irq_register_handler(int_num, int_prio) \ + NVIC_ClearPendingIRQ( (IRQn_Type)int_num); \ + NVIC_SetPriority( (IRQn_Type)int_num, int_prio); \ + NVIC_EnableIRQ( (IRQn_Type)int_num); \ + +//@} + + +# define cpu_irq_enable() \ + do { \ + /*g_interrupt_enabled = true; */ \ + __DMB(); \ + __enable_irq(); \ + } while (0) +# define cpu_irq_disable() \ + do { \ + __disable_irq(); \ + __DMB(); \ + /*g_interrupt_enabled = false; */ \ + } while (0) + +typedef uint32_t irqflags_t; + +#if !defined(__DOXYGEN__) +extern volatile bool g_interrupt_enabled; +#endif + +#define cpu_irq_is_enabled() (__get_PRIMASK() == 0) + +static volatile uint32_t cpu_irq_critical_section_counter; +static volatile bool cpu_irq_prev_interrupt_state; + +static inline irqflags_t cpu_irq_save(void) +{ + irqflags_t flags = cpu_irq_is_enabled(); + cpu_irq_disable(); + return flags; +} + +static inline bool cpu_irq_is_enabled_flags(irqflags_t flags) +{ + return (flags); +} + +static inline void cpu_irq_restore(irqflags_t flags) +{ + if (cpu_irq_is_enabled_flags(flags)) + cpu_irq_enable(); +} +/* +void cpu_irq_enter_critical(void); +void cpu_irq_leave_critical(void);*/ + +/** + * \weakgroup interrupt_deprecated_group + * @{ + */ + +#define Enable_global_interrupt() cpu_irq_enable() +#define Disable_global_interrupt() cpu_irq_disable() +#define Is_global_interrupt_enabled() cpu_irq_is_enabled() + + +//_____ M A C R O S ________________________________________________________ + +/*! \name Usual Constants + */ +//! @{ +#define DISABLE 0 +#define ENABLE 1 +#define DISABLED 0 +#define ENABLED 1 +#define OFF 0 +#define ON 1 +#define FALSE 0 +#define TRUE 1 +#ifndef __cplusplus +#if !defined(__bool_true_false_are_defined) +#define false FALSE +#define true TRUE +#endif +#endif +#define KO 0 +#define OK 1 +#define PASS 0 +#define FAIL 1 +#define LOW 0 +#define HIGH 1 +#define CLR 0 +#define SET 1 +//! @} + +/*! \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#define ctz(u) ((u) & (1ul << 0) ? 0 : \ + (u) & (1ul << 1) ? 1 : \ + (u) & (1ul << 2) ? 2 : \ + (u) & (1ul << 3) ? 3 : \ + (u) & (1ul << 4) ? 4 : \ + (u) & (1ul << 5) ? 5 : \ + (u) & (1ul << 6) ? 6 : \ + (u) & (1ul << 7) ? 7 : \ + (u) & (1ul << 8) ? 8 : \ + (u) & (1ul << 9) ? 9 : \ + (u) & (1ul << 10) ? 10 : \ + (u) & (1ul << 11) ? 11 : \ + (u) & (1ul << 12) ? 12 : \ + (u) & (1ul << 13) ? 13 : \ + (u) & (1ul << 14) ? 14 : \ + (u) & (1ul << 15) ? 15 : \ + (u) & (1ul << 16) ? 16 : \ + (u) & (1ul << 17) ? 17 : \ + (u) & (1ul << 18) ? 18 : \ + (u) & (1ul << 19) ? 19 : \ + (u) & (1ul << 20) ? 20 : \ + (u) & (1ul << 21) ? 21 : \ + (u) & (1ul << 22) ? 22 : \ + (u) & (1ul << 23) ? 23 : \ + (u) & (1ul << 24) ? 24 : \ + (u) & (1ul << 25) ? 25 : \ + (u) & (1ul << 26) ? 26 : \ + (u) & (1ul << 27) ? 27 : \ + (u) & (1ul << 28) ? 28 : \ + (u) & (1ul << 29) ? 29 : \ + (u) & (1ul << 30) ? 30 : \ + (u) & (1ul << 31) ? 31 : \ + 32) + +#endif // __ASSEMBLY__ + +#endif // _COMPILER_H_ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/USBD_Config.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/USBD_Config.h new file mode 100644 index 000000000..2dc1a7777 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/USBD_Config.h @@ -0,0 +1,380 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * USB Device Framework configurations. + * + */ + +#ifndef USBD_CONFIG_H +#define USBD_CONFIG_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/** \addtogroup usbd_config + *@{ + */ +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_ids USBD Device IDs + * @{ + */ +#define USBD_VID_ATMEL 0x03EB /**< Vendor ID: Atmel */ + +#define USBD_PID_ENUM 0x0001 /**< Product ID: Enum (Core) */ +#define USBD_PID_CDCDSERIAL 0x6119 /**< Product ID: CDC Serial */ +#define USBD_PID_HIDKEYBOARD 0x6127 /**< Product ID: HID Keyboard */ +#define USBD_PID_AUDIO 0x6128 /**< Product ID: Audio devices */ +#define USBD_PID_MSD 0x6129 /**< Product ID: Massstorage */ +#define USBD_PID_CDCHID 0x6130 /**< Product ID: composite */ +#define USBD_PID_CDCAUDIO 0x6131 /**< Product ID: composite */ +#define USBD_PID_CDCMSD 0x6132 /**< Product ID: composite */ +#define USBD_PID_CDCCDC 0x6133 /**< Product ID: composite */ +#define USBD_PID_HIDAUDIO 0x6134 /**< Product ID: composite */ +#define USBD_PID_HIDMSD 0x6135 /**< Product ID: composite */ +#define USBD_PID_HIDMOUSE 0x6200 /**< Product ID: HID Mouse */ +#define USBD_PID_HIDTRANSFER 0x6201 /**< Product ID: HID Transfer */ +#define USBD_PID_CCID 0x6203 /**< Product ID: CCID */ +#define USBD_PID_UVC 0x6136 /**< Product ID: UVC */ + +#define USBD_RELEASE_1_00 0x0100 /**< Release: 1.00 */ +#define USBD_RELEASE_0_01 0x0001 /**< Release: 0.01 */ +/** @}*/ + +/** \addtogroup usbd_general_config USBD General Configure + * @{ + * This page lists general configurations for all USB device drivers. + * - \ref USBD_BMATTRIBUTES + */ +/** default USB Device attributes configuration descriptor + * (bus or self powered, remote wakeup) */ +#define USBD_BMATTRIBUTES BOARD_USB_BMATTRIBUTES +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Mass storage + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_msdd_config USB MassStorage Configure + * @{ + * This page lists the defines used by the Mass Storage driver. + * + * \section msd_ep_addr Endpoint Addresses + * - \ref MSDDriverDescriptors_BULKOUT + * - \ref MSDDriverDescriptors_BULKIN + */ +/** Address of the Mass Storage bulk-out endpoint.*/ +#define MSDDriverDescriptors_BULKOUT 2 +/** Address of the Mass Storage bulk-in endpoint.*/ +#define MSDDriverDescriptors_BULKIN 3 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - CDC Serial + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_cdc_serial_config USB CDC Serial Configure + * @{ + * This page lists the defines used by the CDC Serial Device Driver. + * + * \section cdcd_ep_addr Endpoint Addresses + * - \ref CDCDSerialDriverDescriptors_DATAOUT + * - \ref CDCDSerialDriverDescriptors_DATAIN + * - \ref CDCDSerialDriverDescriptors_NOTIFICATION + */ +/** Data OUT endpoint number */ +#define CDCDSerialDriverDescriptors_DATAOUT 2 +/** Data IN endpoint number */ +#define CDCDSerialDriverDescriptors_DATAIN 3 +/** Notification endpoint number */ +#define CDCDSerialDriverDescriptors_NOTIFICATION 4 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Audio + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_audio_config USB Audio General Configure + * @{ + * This page lists definitions for USB Audio Devices Drivers. + * - \ref + */ + +/** Sample rate in Hz. */ +#define AUDDevice_SAMPLERATE 48000UL +/** Number of channels in audio stream. */ +#define AUDDevice_NUMCHANNELS 2 +/** Number of bytes in one sample. */ +#define AUDDevice_BYTESPERSAMPLE 2 + +/** Number of bits in one sample. */ +#define AUDDevice_BITSPERSAMPLE (AUDDevice_BYTESPERSAMPLE * 8) +/** Number of bytes in one USB subframe. */ +#define AUDDevice_BYTESPERSUBFRAME (AUDDevice_NUMCHANNELS * \ + AUDDevice_BYTESPERSAMPLE) +/** Number of samples in one USB frame. */ +#define AUDDevice_SAMPLESPERFRAME (AUDDevice_SAMPLERATE / 1000 \ + * AUDDevice_NUMCHANNELS) +/** Number of bytes in one USB frame. */ +#define AUDDevice_BYTESPERFRAME (AUDDevice_SAMPLESPERFRAME * \ + AUDDevice_BYTESPERSAMPLE) +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Audio - Desktop Speaker + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_audio_speaker_config USB Speaker Configure + * @{ + * This page lists the definitions for USB Audio Speaker Device Driver. + * - \ref AUDDSpeakerDriverDescriptors_DATAOUT + * - \ref AUDDSpeakerDriverDescriptors_FS_INTERVAL + * - \ref AUDDSpeakerDriverDescriptors_HS_INTERVAL + * + * \note for UDP, uses IN EPs that support double buffer; for UDPHS, uses + * IN EPs that support DMA and High bandwidth. + */ +/** Data out endpoint number. */ +#define AUDDSpeakerDriverDescriptors_DATAOUT 0x02 +/** Endpoint polling interval 2^(x-1) * 125us */ +#define AUDDSpeakerDriverDescriptors_HS_INTERVAL 0x04 +/** Endpoint polling interval 2^(x-1) * ms */ +#define AUDDSpeakerDriverDescriptors_FS_INTERVAL 0x01 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Audio - Speaker Phone + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_audio_speakerphone_config USB Speaker Phone Configure + * @{ + * This page lists the definitions for USB Audio Speaker Phone Device Driver. + * - \ref AUDDSpeakerPhoneDriverDescriptors_DATAOUT + * - \ref AUDDSpeakerPhoneDriverDescriptors_DATAIN + * - \ref AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL + * - \ref AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL + */ + + +/** Data out endpoint number, size 192B */ +#define AUDDSpeakerPhoneDriverDescriptors_DATAOUT 0x02 +/** Data in endpoint number, size 192B */ +#define AUDDSpeakerPhoneDriverDescriptors_DATAIN 0x01 + +/** Endpoint polling interval 2^(x-1) * 125us */ +#define AUDDSpeakerPhoneDriverDescriptors_HS_INTERVAL 0x04 +/** Endpoint polling interval 2^(x-1) * ms */ +#define AUDDSpeakerPhoneDriverDescriptors_FS_INTERVAL 0x01 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - HID - Keyboard + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_hid_keyboard_config USB HID Keyboard Device Configure + * @{ + * This page lists the defines used by the HID Keyboard Device Driver. + * + * \section hidd_k_ep_addr Endpoint Addresses + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT + * \section hidd_k_ep_polling Endpoint Polling Rate + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING + * - \ref HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING + */ +/** Interrupt IN endpoint number */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTIN 2 +/** Interrupt IN endpoint polling rate (in milliseconds) */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTIN_POLLING 10 +/** Interrupt OUT endpoint number */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT 3 +/** Interrupt OUT endpoint polling rate (in milliseconds) */ +#define HIDDKeyboardDriverDescriptors_INTERRUPTOUT_POLLING 10 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - HID - Mouse + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_hid_mouse_config USB HID Mouse Device Configure + * @{ + * This page lists the defines used by the HID Mouse Device Driver. + * + * \section hidd_m_ep_addr Endpoint Addresses + * - \ref HIDDMouseDriverDescriptors_INTERRUPTIN + * \section hidd_m_ep_polling Endpoint Polling Rate + * - \ref HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING + */ +/** Interrupt IN endpoint number */ +#define HIDDMouseDriverDescriptors_INTERRUPTIN 2 +/** Interrupt IN endpoint polling rate (in milliseconds) */ +#define HIDDMouseDriverDescriptors_INTERRUPTIN_POLLING 8 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - HID - Transfer (Customize device) + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_hid_xfr_config USB HID Transfer Device Configure + * @{ + * This page lists the defines used by the HID Transfer Device Driver. + * + * \section hidd_t_ep_addr Endpoint Addresses + * - \ref HIDDTransferDriverDescriptors_INTERRUPTIN + * - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT + * \section hidd_t_ep_polling Endpoint Polling Rate + * - \ref HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING + * - \ref HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING + */ +/** Interrupt IN endpoint number. */ +#define HIDDTransferDriverDescriptors_INTERRUPTIN 2 +/** Polling rate in ms */ +#define HIDDTransferDriverDescriptors_INTERRUPTIN_POLLING 50 +/** Interrupt IN endpoint polling rate (in milliseconds). */ +#define HIDDTransferDriverDescriptors_INTERRUPTOUT 3 +/** Polling rate in ms */ +#define HIDDTransferDriverDescriptors_INTERRUPTOUT_POLLING 50 +/** @}*/ + +/*---------------------------------------------------------------------------- + * USB Device - Composite + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_composite_config USB Composite Device Configure + * @{ + */ + +/*---------------------------------------------------------------------------- + * USB Device - HID_AUD + *----------------------------------------------------------------------------*/ + +/** Address of the HID interrupt IN endpoint. */ +#define HIDAUDD_Descriptors_INTERRUPTIN 0x03 +/** Address of the HID interrupt OUT endpoint. */ +#define HIDAUDD_Descriptors_INTERRUPTOUT 0x04 + +/** Audio data out endpoint number */ +#define HIDAUDD_Descriptors_ISO_DATAOUT 0x02 + + +/*---------------------------------------------------------------------------- + * USB Device - CDC AUD + *----------------------------------------------------------------------------*/ + +/** Address of the CDC interrupt-in endpoint. */ +#define CDCAUDD_Descriptors_NOTIFICATION0 0x04 +/** Address of the CDC bulk-in endpoint. */ +#define CDCAUDD_Descriptors_DATAIN0 0x03 +/** Address of the CDC bulk-out endpoint. */ +#define CDCAUDD_Descriptors_DATAOUT0 0x02 +/** Address of the Audio ISO-out endpoint. */ +#define CDCAUDD_Descriptors_ISO_DATAOUT 0x01 + + +/*---------------------------------------------------------------------------- + * USB Device - DUAL CDC + *----------------------------------------------------------------------------*/ + +/// Address of the CDC0 interrupt-in endpoint. +#define CDCD_Descriptors_NOTIFICATION0 3 +/// Address of the CDC0 bulk-in endpoint. +#define CDCD_Descriptors_DATAIN0 2 +/// Address of the CDC0 bulk-out endpoint. +#define CDCD_Descriptors_DATAOUT0 1 + +/// Address of the CDC1 interrupt-in endpoint. +#define CDCD_Descriptors_NOTIFICATION1 6 +/// Address of the CDC1 bulk-in endpoint. +#define CDCD_Descriptors_DATAIN1 5 +/// Address of the CDC1 bulk-out endpoint. +#define CDCD_Descriptors_DATAOUT1 4 + + +/*---------------------------------------------------------------------------- + * USB Device - HID CDC + *----------------------------------------------------------------------------*/ + + +/** Address of the CDC interrupt-in endpoint. */ +#define CDCD_Descriptors_NOTIFICATION0 3 +/** Address of the CDC bulk-in endpoint. */ +#define CDCD_Descriptors_DATAIN0 2 +/** Address of the CDC bulk-out endpoint. */ +#define CDCD_Descriptors_DATAOUT0 1 + +/** Address of the HID interrupt IN endpoint. */ +#define HIDD_Descriptors_INTERRUPTIN 4 +/** Address of the HID interrupt OUT endpoint. */ +#define HIDD_Descriptors_INTERRUPTOUT 5 + + + +/*---------------------------------------------------------------------------- + * USB Device - HID MSD + *----------------------------------------------------------------------------*/ + +/** Address of the Mass Storage bulk-out endpoint. */ +#define HIDMSDD_Descriptors_BULKOUT 2 +/** Address of the Mass Storage bulk-in endpoint. */ +#define HIDMSDD_Descriptors_BULKIN 3 + +/** Address of the HID interrupt IN endpoint. */ +#define HIDMSDD_Descriptors_INTERRUPTIN 4 +/** Address of the HID interrupt OUT endpoint. */ +#define HIDMSDD_Descriptors_INTERRUPTOUT 5 + +/*---------------------------------------------------------------------------- + * USB Device - MSD CDC + *----------------------------------------------------------------------------*/ + +/** Address of the CDC interrupt-in endpoint. */ +#define CDCD_Descriptors_NOTIFICATION0 3 +/** Address of the CDC bulk-in endpoint. */ +#define CDCD_Descriptors_DATAIN0 2 +/** Address of the CDC bulk-out endpoint. */ +#define CDCD_Descriptors_DATAOUT0 1 +/** Address of the Mass Storage bulk-out endpoint. */ +#define MSDD_Descriptors_BULKOUT 4 +/** Address of the Mass Storage bulk-in endpoint. */ +#define MSDD_Descriptors_BULKIN 5 + +/** @}*/ + +/**@}*/ +#endif //#ifndef USBD_CONFIG_H + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/USBD_LEDs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/USBD_LEDs.h new file mode 100644 index 000000000..c2f2d31ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/USBD_LEDs.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Collection of LEDs for using the USB device controller on AT91 + * Microcontrollers. + */ + +#ifndef USBDLEDS_H +#define USBDLEDS_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/** \addtogroup usbd_hal + *@{ + */ +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** \addtogroup usbd_leds USB Device LEDs + * @{ + * This page lists the LEDs used in the USB %device driver. + * + * - USBD_LEDPOWER + * - USBD_LEDUSB + * - USBD_LEDOTHER + */ + +/** LED for indicating that the device is powered. */ +#define USBD_LEDPOWER 0 +/** LED for custom usage. */ +#define USBD_LEDOTHER 1 +/** @}*/ + +/**@}*/ + +#endif //#ifndef USBDLEDS_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/acc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/acc.h new file mode 100644 index 000000000..8538d4245 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/acc.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ACC + * -# Initialize the ACC with ACC_Initialize(). + * -# Select the active channel using ACC_EnableChannel() + * -# Start the conversion with ACC_StartConversion() + * -# Wait the end of the conversion by polling status with ACC_GetStatus() + * -# Finally, get the converted data using ACC_GetConvertedData() + * + */ +#ifndef _ACC_ +#define _ACC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define ACC_SELPLUS_AD12B0 0 +#define ACC_SELPLUS_AD12B1 1 +#define ACC_SELPLUS_AD12B2 2 +#define ACC_SELPLUS_AD12B3 3 +#define ACC_SELPLUS_AD12B4 4 +#define ACC_SELPLUS_AD12B5 5 +#define ACC_SELPLUS_AD12B6 6 +#define ACC_SELPLUS_AD12B7 7 +#define ACC_SELMINUS_TS 0 +#define ACC_SELMINUS_ADVREF 1 +#define ACC_SELMINUS_DAC0 2 +#define ACC_SELMINUS_DAC1 3 +#define ACC_SELMINUS_AD12B0 4 +#define ACC_SELMINUS_AD12B1 5 +#define ACC_SELMINUS_AD12B2 6 +#define ACC_SELMINUS_AD12B3 7 + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define ACC_CfgModeReg(pAcc, mode) { \ + (pAcc)->ACC_MR = (mode);\ + } + +#define ACC_GetModeReg( pAcc ) ((pAcc)->ACC_MR) + +#define ACC_StartConversion( pAcc ) ((pAcc)->ACC_CR = ACC_CR_START) + +#define ACC_SoftReset( pAcc ) ((pAcc)->ACC_CR = ACC_CR_SWRST) + +#define ACC_EnableChannel( pAcc, dwChannel ) {\ + assert( dwChannel < 16 ) ;\ + (pAcc)->ACC_CHER = (1 << (dwChannel));\ + } + +#define ACC_DisableChannel( pAcc, dwChannel ) {\ + assert( dwChannel < 16 ) ;\ + (pAcc)->ACC_CHDR = (1 << (dwChannel));\ + } + +#define ACC_EnableIt( pAcc, dwMode ) {\ + assert( ((dwMode)&0xFFF00000)== 0 ) ;\ + (pAcc)->ACC_IER = (dwMode);\ + } + +#define ACC_DisableIt( pAcc, dwMode ) {\ + assert( ((dwMode)&0xFFF00000)== 0 ) ;\ + (pAcc)->ACC_IDR = (dwMode);\ + } + +#define ACC_EnableDataReadyIt( pAcc ) ((pAcc)->ACC_IER = AT91C_ACC_DRDY) + +#define ACC_GetStatus( pAcc ) ((pAcc)->ACC_ISR) + +#define ACC_GetChannelStatus( pAcc ) ((pAcc)->ACC_CHSR) + +#define ACC_GetInterruptMaskStatus( pAcc ) ((pAcc)->ACC_IMR) + +#define ACC_GetLastConvertedData( pAcc ) ((pAcc)->ACC_LCDR) + +#define ACC_CfgAnalogCtrlReg( pAcc, dwMode ) {\ + assert( ((dwMode) & 0xFFFCFF3C) == 0 ) ;\ + (pAcc)->ACC_ACR = (dwMode);\ + } + +#define ACC_CfgExtModeReg( pAcc, extmode ) {\ + assert( ((extmode) & 0xFF00FFFE) == 0 ) ;\ + (pAcc)->ACC_EMR = (extmode);\ + } + +#define ACC_GetAnalogCtrlReg( pAcc ) ((pAcc)->ACC_ACR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, + uint8_t ucSelminus, uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert ) ; + +extern void ACC_SetComparisonPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus ) ; + +extern uint32_t ACC_GetComparisonResult( Acc* pAcc, uint32_t dwStatus ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ACC_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/adc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/adc.h new file mode 100644 index 000000000..5c9d12959 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/adc.h @@ -0,0 +1,178 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (ADC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for ADC. + * -# Initialize the ADC with ADC_Initialize(). + * -# Set ADC clock and timing with ADC_SetClock() and ADC_SetTiming(). + * -# Select the active channel using ADC_EnableChannel(). + * -# Start the conversion with ADC_StartConversion(). + * -# Wait the end of the conversion by polling status with ADC_GetStatus(). + * -# Finally, get the converted data using ADC_GetConvertedData() or + * ADC_GetLastConvertedData(). + * +*/ +#ifndef _ADC_ +#define _ADC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* Max. ADC Clock Frequency (Hz) */ +#define ADC_CLOCK_MAX 20000000 + +/* Max. normal ADC startup time (us) */ +#define ADC_STARTUP_NORMAL_MAX 40 +/* Max. fast ADC startup time (us) */ +#define ADC_STARTUP_FAST_MAX 12 + +/* Definitions for ADC channels */ +#define ADC_CHANNEL_0 0 +#define ADC_CHANNEL_1 1 +#define ADC_CHANNEL_2 2 +#define ADC_CHANNEL_3 3 +#define ADC_CHANNEL_4 4 +#define ADC_CHANNEL_5 5 +#define ADC_CHANNEL_6 6 +#define ADC_CHANNEL_7 7 +#define ADC_CHANNEL_8 8 +#define ADC_CHANNEL_9 9 +#define ADC_CHANNEL_10 10 +#define ADC_CHANNEL_11 11 +#define ADC_CHANNEL_12 12 +#define ADC_CHANNEL_13 13 +#define ADC_CHANNEL_14 14 +#define ADC_CHANNEL_15 15 + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define ADC_GetModeReg( pAdc ) ((pAdc)->ADC_MR) + +#define ADC_StartConversion( pAdc ) ((pAdc)->ADC_CR = ADC_CR_START) + +#define ADC_SetCalibMode(pAdc) ((pAdc)->ADC_CR |= ADC_CR_AUTOCAL) + +#define ADC_EnableChannel( pAdc, dwChannel ) {\ + (pAdc)->ADC_CHER = (1 << (dwChannel));\ + } + +#define ADC_DisableChannel(pAdc, dwChannel) {\ + (pAdc)->ADC_CHDR = (1 << (dwChannel));\ + } + +#define ADC_EnableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IER = (dwMode);\ + } + +#define ADC_DisableIt(pAdc, dwMode) {\ + (pAdc)->ADC_IDR = (dwMode);\ + } + +#define ADC_SetChannelGain(pAdc,dwMode) {\ + (pAdc)->ADC_CGR = dwMode;\ + } + +#define ADC_SetChannelOffset(pAdc,dwMode) {\ + (pAdc)->ADC_COR = dwMode;\ + } + +#define ADC_EnableDataReadyIt(pAdc) ((pAdc)->ADC_IER = ADC_IER_DRDY) + +#define ADC_GetStatus(pAdc) ((pAdc)->ADC_ISR) + +#define ADC_GetCompareMode(pAdc) (((pAdc)->ADC_EMR)& (ADC_EMR_CMPMODE_Msk)) + +#define ADC_GetChannelStatus(pAdc) ((pAdc)->ADC_CHSR) + +#define ADC_GetInterruptMaskStatus(pAdc) ((pAdc)->ADC_IMR) + +#define ADC_GetLastConvertedData(pAdc) ((pAdc)->ADC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void ADC_Initialize( Adc* pAdc, uint32_t dwId ); +extern uint32_t ADC_SetClock( Adc* pAdc, uint32_t dwPres, uint32_t dwMck ); +extern void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling ); +extern void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel ); +extern void ADC_SetTriggerMode(Adc *pAdc, uint32_t dwMode); +extern void ADC_SetLowResolution( Adc* pAdc, uint32_t bEnDis ); +extern void ADC_SetSleepMode( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetFastWakeup( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetSequenceMode( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetSequence( Adc *pAdc, uint32_t dwSEQ1, uint32_t dwSEQ2 ); +extern void ADC_SetSequenceByList( Adc *pAdc, uint8_t ucChList[], uint8_t ucNumCh ); +extern void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetTagEnable( Adc *pAdc, uint8_t bEnDis ); +extern void ADC_SetCompareChannel( Adc* pAdc, uint32_t dwChannel ) ; +extern void ADC_SetCompareMode( Adc* pAdc, uint32_t dwMode ) ; +extern void ADC_SetComparisonWindow( Adc* pAdc, uint32_t dwHi_Lo ) ; +extern uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ; +extern uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ; +extern void ADC_SetTsAverage(Adc* pADC, uint32_t dwAvg2Conv); +extern uint32_t ADC_GetTsXPosition(Adc *pADC); +extern uint32_t ADC_GetTsYPosition(Adc *pADC); +extern uint32_t ADC_GetTsPressure(Adc *pADC); +extern void ADC_SetTsDebounce(Adc *pADC, uint32_t dwTime); +extern void ADC_SetTsPenDetect(Adc* pADC, uint8_t bEnDis); +extern void ADC_SetStartupTime( Adc *pAdc, uint32_t dwUs ); +extern void ADC_SetTrackingTime( Adc *pAdc, uint32_t dwNs ); +extern void ADC_SetTriggerPeriod(Adc *pAdc, uint32_t dwPeriod); +extern void ADC_SetTsMode(Adc* pADC, uint32_t dwMode); +extern void ADC_TsCalibration( Adc *pAdc ); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _ADC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/aes.h new file mode 100644 index 000000000..d67940b0d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/aes.h @@ -0,0 +1,68 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _AES_ +#define _AES_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define AES_MR_CIPHER_ENCRYPT 1 +#define AES_MR_CIPHER_DECRYPT 0 +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +extern void AES_Start(void); +extern void AES_SoftReset(void); +extern void AES_Recount(void); +extern void AES_Configure(uint32_t mode); +extern void AES_EnableIt(uint32_t sources); +extern void AES_DisableIt(uint32_t sources); +extern uint32_t AES_GetStatus(void); +extern void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength); +extern void AES_SetInput(uint32_t *data); +extern void AES_GetOutput(uint32_t *data); +extern void AES_SetVector(const uint32_t *pVector); +extern void AES_SetAadLen(uint32_t len); +extern void AES_SetDataLen(uint32_t len); +extern void AES_SetGcmHash(uint32_t * hash); +extern void AES_GetGcmTag(uint32_t * tag); +extern void AES_GetGcmCounter(uint32_t * counter); +extern void AES_GetGcmH(uint32_t *h); + + +#endif /* #ifndef _AES_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/afe_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/afe_dma.h new file mode 100644 index 000000000..591199305 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/afe_dma.h @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFE_DMA_ +#define _AFE_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** AFE transfer complete callback. */ +typedef void (*AfeCallback)( uint8_t, void* ) ; + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the AFE_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Rx data. */ + uint32_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** Callback function invoked at the end of transfer. */ + AfeCallback callback; + /** Callback arguments. */ + void *pArgument; +} AfeCmd ; + + +/** Constant structure associated with AFE port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** Pointer to AFE Hardware registers */ + Afec* pAfeHw ; + /** Current SpiCommand being processed */ + AfeCmd *pCurrentCommand ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** AFEC Id as defined in the product datasheet */ + uint8_t afeId ; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore ; +} AfeDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define AFE_OK 0 +#define AFE_ERROR 1 +#define AFE_ERROR_LOCK 2 +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint32_t Afe_ConfigureDma( AfeDma *pAfed , + Afec *pAfeHw , + uint8_t AfeId, + sXdmad *pXdmad ); +extern uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand); + + +#endif /* #ifndef _AFE_DMA_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/afec.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/afec.h new file mode 100644 index 000000000..dd75118c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/afec.h @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (AFEC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for AFEC. + * -# Initialize the AFEC with AFEC_Initialize(). + * -# Set AFEC clock and timing with AFEC_SetClock() and AFEC_SetTiming(). + * -# Select the active channel using AFEC_EnableChannel(). + * -# Start the conversion with AFEC_StartConversion(). + * -# Wait the end of the conversion by polling status with AFEC_GetStatus(). + * -# Finally, get the converted data using AFEC_GetConvertedData() or + * AFEC_GetLastConvertedData(). + * +*/ +#ifndef _AFEC_ +#define _AFEC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include +#include + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ + +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_SETTLING_Pos 20 +#define AFEC_MR_SETTLING_Msk (0x3u << AFEC_MR_SETTLING_Pos) +/**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_SETTLING_AST3 (0x0u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST3 3 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST5 (0x1u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST5 5 periods of AFEClock */ +#define AFEC_MR_SETTLING_AST9 (0x2u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST9 9 periods of AFEClock*/ +#define AFEC_MR_SETTLING_AST17 (0x3u << 20) +/**< \brief (AFEC_MR) ADC_SETTLING_AST17 17 periods of AFEClock*/ + +/***************************** Single Trigger Mode ****************************/ +#define AFEC_EMR_STM_Pos 25 +#define AFEC_EMR_STM_Msk (0x1u << AFEC_EMR_STM_Pos) +/**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_STM_MULTI_TRIG (0x0u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Multiple triggers are required to + get an averaged result. */ +#define AFEC_EMR_STM_SINGLE_TRIG (0x1u << 25) +/**< \brief (AFEC_EMR) Single Trigger Mode: Only a Single Trigger is required + to get an averaged value. */ + +/***************************** TAG of the AFEC_LDCR Register ******************/ +#define AFEC_EMR_TAG_Pos 24 +#define AFEC_EMR_TAG_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register */ +#define AFEC_EMR_TAG_CHNB_ZERO (0x0u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Sets CHNB to zero +in AFEC_LDCR. */ +#define AFEC_EMR_TAG_APPENDS (0x1u << 24) +/**< \brief (AFEC_EMR) TAG of the AFEC_LDCR Register: Appends the channel +number to the conversion result in AFEC_LDCR register. */ + +/***************************** Compare All Channels ******************/ +#define AFEC_EMR_CMPALL_Pos 9 +#define AFEC_EMR_CMPALL_Msk (0x1u << AFEC_EMR_TAG_Pos) +/**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPALL_ONE_CHANNEL_COMP (0x0u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: Only channel indicated in +CMPSEL field is compared. */ +#define AFEC_EMR_CMPALL_ALL_CHANNELS_COMP (0x1u << 9) +/**< \brief (AFEC_EMR) Compare All Channels: All channels are compared. */ + +#define AFEC_ACR_PGA0_ON (0x1u << 2) +#define AFEC_ACR_PGA1_ON (0x1u << 3) + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ + +#define AFEC_GetModeReg( pAFEC ) ((pAFEC)->AFEC_MR) +#define AFEC_SetModeReg( pAFEC, mode ) ((pAFEC)->AFEC_MR = mode) + +#define AFEC_GetExtModeReg( pAFEC ) ((pAFEC)->AFEC_EMR) +#define AFEC_SetExtModeReg( pAFEC, mode ) ((pAFEC)->AFEC_EMR = mode) + +#define AFEC_StartConversion( pAFEC ) ((pAFEC)->AFEC_CR = AFEC_CR_START) + +#define AFEC_EnableChannel( pAFEC, dwChannel ) {\ + (pAFEC)->AFEC_CHER = (1 << (dwChannel));\ + } + +#define AFEC_DisableChannel(pAFEC, dwChannel) {\ + (pAFEC)->AFEC_CHDR = (1 << (dwChannel));\ + } + +#define AFEC_EnableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IER = (dwMode);\ + } + +#define AFEC_DisableIt(pAFEC, dwMode) {\ + (pAFEC)->AFEC_IDR = (dwMode);\ + } + +#define AFEC_SetChannelGain(pAFEC,dwMode) {\ + (pAFEC)->AFEC_CGR = dwMode;\ + } + +#define AFEC_EnableDataReadyIt(pAFEC) ((pAFEC)->AFEC_IER = AFEC_IER_DRDY) + +#define AFEC_GetStatus(pAFEC) ((pAFEC)->AFEC_ISR) + +#define AFEC_GetCompareMode(pAFEC) (((pAFEC)->AFEC_EMR)& (AFEC_EMR_CMPMODE_Msk)) + +#define AFEC_GetChannelStatus(pAFEC) ((pAFEC)->AFEC_CHSR) + +#define AFEC_GetInterruptMaskStatus(pAFEC) ((pAFEC)->AFEC_IMR) + +#define AFEC_GetLastConvertedData(pAFEC) ((pAFEC)->AFEC_LCDR) + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern void AFEC_Initialize( Afec* pAFEC, uint32_t dwId ); +extern uint32_t AFEC_SetClock( Afec* pAFEC, uint32_t dwPres, uint32_t dwMck ); +extern void AFEC_SetTiming( Afec* pAFEC, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling ); +extern void AFEC_SetTrigger( Afec* pAFEC, uint32_t dwTrgSel ); +extern void AFEC_SetAnalogChange( Afec* pAFE, uint8_t bEnDis ); +extern void AFEC_SetSleepMode( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetFastWakeup( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetSequenceMode( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetSequence( Afec* pAFEC, uint32_t dwSEQ1, uint32_t dwSEQ2 ); +extern void AFEC_SetSequenceByList( Afec* pAFEC, uint8_t ucChList[], uint8_t ucNumCh ); +extern void AFEC_SetTagEnable( Afec* pAFEC, uint8_t bEnDis ); +extern void AFEC_SetCompareChannel( Afec* pAFEC, uint32_t dwChannel ) ; +extern void AFEC_SetCompareMode( Afec* pAFEC, uint32_t dwMode ) ; +extern void AFEC_SetComparisonWindow( Afec* pAFEC, uint32_t dwHi_Lo ) ; +extern uint8_t AFEC_CheckConfiguration( Afec* pAFEC, uint32_t dwMcK ) ; +extern uint32_t AFEC_GetConvertedData( Afec* pAFEC, uint32_t dwChannel ) ; +extern void AFEC_SetStartupTime( Afec* pAFEC, uint32_t dwUs ); +extern void AFEC_SetTrackingTime( Afec* pAFEC, uint32_t dwNs ); +extern void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset ); +extern void AFEC_SetAnalogControl( Afec *pAFE, uint32_t control); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _AFEC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h new file mode 100644 index 000000000..c7818749e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,98 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2014 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.3 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +/* Tables for Fast Math Sine and Cosine */ +extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1]; +extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1]; +extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h new file mode 100644 index 000000000..55295ddad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,59 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-20134 ARM Limited. All rights reserved. +* +* $Date: 12. March 2014 +* $Revision: V1.4.3 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048; + extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096; + +#endif diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h new file mode 100644 index 000000000..c5c820efc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0.h @@ -0,0 +1,702 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M0 + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h new file mode 100644 index 000000000..f835ee091 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,813 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex-M0+ + @{ + */ + +/* CMSIS CM0P definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ + __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000 + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0 + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if (__VTOR_PRESENT == 1) + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if (__VTOR_PRESENT == 1) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M0+ Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 000000000..bee997ed6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,697 @@ +/**************************************************************************//** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.30 + * @date 17. February 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +#ifdef __cplusplus + extern "C" { +#endif + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ +#include + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ +/* not yet supported */ + + +#elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/ +/* Cosmic specific functions */ +#include + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_SIMD_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h new file mode 100644 index 000000000..af6c51dae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cm7.h @@ -0,0 +1,2204 @@ + +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V4.00 + * @date 07. April 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M7 + @{ + */ + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x07) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler (use -pc99 on compile line ) */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #if (__FPU_PRESENT == 1) + #define __FPU_USED 1 + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0 + #endif + #else + #define __FPU_USED 0 + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000 + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0 + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0 + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0 + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x07) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHPR[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1]; + __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __I uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93]; + __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15]; + __I uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __I uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */ + uint32_t RESERVED5[1]; + __O uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1]; + __O uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __O uint32_t DCIMVAU; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __O uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __O uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __O uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __O uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __O uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __O uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6]; + __IO uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IO uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IO uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IO uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IO uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1]; + __IO uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18 /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17 /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16 /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/* Cache Level ID register */ +#define SCB_CLIDR_LOUU_Pos 27 /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24 /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_FORMAT_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* Cache Type register */ +#define SCB_CTR_FORMAT_Pos 29 /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24 /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20 /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16 /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0 /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL << SCB_CTR_IMINLINE_Pos) /*!< SCB CTR: ImInLine Mask */ + +/* Cache Size ID Register */ +#define SCB_CCSIDR_WT_Pos 31 /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (7UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30 /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (7UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29 /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (7UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28 /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (7UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13 /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3 /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0 /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL << SCB_CCSIDR_LINESIZE_Pos) /*!< SCB CCSIDR: LineSize Mask */ + +/* Cache Size Selection Register */ +#define SCB_CSSELR_LEVEL_Pos 0 /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (1UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0 /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL << SCB_CSSELR_IND_Pos) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register */ +#define SCB_STIR_INTID_Pos 0 /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL << SCB_STIR_INTID_Pos) /*!< SCB STIR: INTID Mask */ + +/* Instruction Tightly-Coupled Memory Control Register*/ +#define SCB_ITCMCR_SZ_Pos 3 /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2 /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1 /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0 /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL << SCB_ITCMCR_EN_Pos) /*!< SCB ITCMCR: EN Mask */ + + +/* Data Tightly-Coupled Memory Control Registers */ +#define SCB_DTCMCR_SZ_Pos 3 /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2 /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1 /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0 /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL << SCB_DTCMCR_EN_Pos) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register */ +#define SCB_AHBPCR_SZ_Pos 1 /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0 /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL << SCB_AHBPCR_EN_Pos) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register */ +#define SCB_CACR_FORCEWT_Pos 2 /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1 /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0 /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL << SCB_CACR_SIWT_Pos) /*!< SCB CACR: SIWT Mask */ + +/* AHBSCR control register */ +#define SCB_AHBSCR_INITCOUNT_Pos 11 /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2 /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0 /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL << SCB_AHBPCR_CTL_Pos) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register */ +#define SCB_ABFSR_AXIMTYPE_Pos 8 /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4 /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3 /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2 /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1 /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0 /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL << SCB_ABFSR_ITCM_Pos) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12 /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11 /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10 /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M7 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ +/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHPR[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## Cache functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) +#define CCSIDR_LSSHIFT(x) (((x) & SCB_CCSIDR_LINESIZE_Msk ) >> SCB_CCSIDR_LINESIZE_Pos ) + + +/** \brief Enable I-Cache + + The function turns on I-Cache + */ +__STATIC_INLINE void SCB_EnableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; // invalidate I-Cache + SCB->CCR |= SCB_CCR_IC_Msk; // enable I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable I-Cache + + The function turns off I-Cache + */ +__STATIC_INLINE void SCB_DisableICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->CCR &= ~SCB_CCR_IC_Msk; // disable I-Cache + SCB->ICIALLU = 0; // invalidate I-Cache + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate I-Cache + + The function invalidates I-Cache + */ +__STATIC_INLINE void SCB_InvalidateICache(void) +{ + #if (__ICACHE_PRESENT == 1) + __DSB(); + __ISB(); + SCB->ICIALLU = 0; + __DSB(); + __ISB(); + #endif +} + + +/** \brief Enable D-Cache + + The function turns on D-Cache + */ +__STATIC_INLINE void SCB_EnableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + __DSB(); + + SCB->CCR |= SCB_CCR_DC_Msk; // enable D-Cache + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Disable D-Cache + + The function turns off D-Cache + */ +__STATIC_INLINE void SCB_DisableDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + SCB->CCR &= ~SCB_CCR_DC_Msk; // disable D-Cache + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Invalidate D-Cache + + The function invalidates D-Cache + */ +__STATIC_INLINE void SCB_InvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean D-Cache + + The function cleans D-Cache + */ +__STATIC_INLINE void SCB_CleanDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCSW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/** \brief Clean & Invalidate D-Cache + + The function cleans and Invalidates D-Cache + */ +__STATIC_INLINE void SCB_CleanInvalidateDCache(void) +{ + #if (__DCACHE_PRESENT == 1) + uint32_t ccsidr, sshift, wshift, sw; + uint32_t sets, ways; + + ccsidr = SCB->CCSIDR; + sets = CCSIDR_SETS(ccsidr); + sshift = CCSIDR_LSSHIFT(ccsidr) + 4; + ways = CCSIDR_WAYS(ccsidr); + wshift = __CLZ(ways) & 0x1f; + + __DSB(); + + do { // clean & invalidate D-Cache + int32_t tmpways = ways; + do { + sw = ((tmpways << wshift) | (sets << sshift)); + SCB->DCCISW = sw; + } while(tmpways--); + } while(sets--); + + __DSB(); + __ISB(); + #endif +} + + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h new file mode 100644 index 000000000..8b37e0e74 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.21 + * @date 29. November 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) // CM7Pelican + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) // CM7Pelican + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h new file mode 100644 index 000000000..86066313b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,618 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.01 + * @date 06. March 2013 + * + * @note + * Copyright (C) 2009-2014 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + + __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) ); + return(op1); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h new file mode 100644 index 000000000..bd092a7ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_cmSimd.h @@ -0,0 +1,714 @@ +/**************************************************************************//** + * @file core_cmSimd.h + * @brief CMSIS Cortex-M SIMD Header File + * @version V3.21 + * @date 29. November 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CMSIMD_H +#define __CORE_CMSIMD_H + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM SIMD Intrinsics ------------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32) ) >> 32)) + +/*-- End CM SIMD Intrinsics ------------------------------------------------------*/ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM SIMD Intrinsics ------------------------------------------------------*/ +#include + +/*-- End CM SIMD Intrinsics ------------------------------------------------------*/ + + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM SIMD Intrinsics ------------------------------------------------------*/ +#include + +/*-- End CM SIMD Intrinsics ------------------------------------------------------*/ + + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM SIMD Intrinsics ------------------------------------------------------*/ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ // Little endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else // Big endian + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +/*-- End CM SIMD Intrinsics ------------------------------------------------------*/ + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + + +/*------ CM SIMD Intrinsics ------------------------------------------------------*/ +/* not yet supported */ + +/*-- End CM SIMD Intrinsics ------------------------------------------------------*/ + + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CORE_CM7Pelican_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h new file mode 100644 index 000000000..03e361424 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_sc000.h @@ -0,0 +1,833 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC000 + @{ + */ + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (000) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000 + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1]; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154]; + __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/* SCB Security Features Register Definitions */ +#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */ +#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */ + +#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */ +#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) + are only accessible over DAP and not via processor. Therefore + they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of SC000 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h new file mode 100644 index 000000000..3b5e570fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/cmsis/CMSIS/Include/core_sc300.h @@ -0,0 +1,1618 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V3.30 + * @date 06. May 2014 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup SC3000 + @{ + */ + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_SC (300) /*!< Cortex secure core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) /* Cosmic */ + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) /* Cosmic */ + #if ( __CSMC__ & 0x400) // FPU present for parser + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000 + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + uint32_t RESERVED1[1]; +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/dac_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/dac_dma.h new file mode 100644 index 000000000..1ea173acc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/dac_dma.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Analog-to-Digital Converter (DACC) peripheral. + * + * \section Usage + * + * -# Configurate the pins for DACC + * -# Initialize the DACC with DACC_Initialize(). + * -# Select the active channel using DACC_EnableChannel() + * -# Start the conversion with DACC_StartConversion() + * -# Wait the end of the conversion by polling status with DACC_GetStatus() + * -# Finally, get the converted data using DACC_GetConvertedData() + * +*/ +#ifndef _DAC_DMA_ +#define _DAC_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + + +#ifdef __cplusplus + extern "C" { +#endif + + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DAC transfer complete callback. */ +typedef void (*DacCallback)( uint8_t, void* ) ; + +/** \brief Dac Transfer Request prepared by the application upper layer. + * + * This structure is sent to the DAC_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint16_t TxSize; + /** Tx loop back. */ + uint16_t loopback; + /** DACC channel*/ + uint8_t dacChannel; + /** Callback function invoked at the end of transfer. */ + DacCallback callback; + /** Callback arguments. */ + void *pArgument; +} DacCmd ; + + +/** Constant structure associated with DAC port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** Pointer to DAC Hardware registers */ + Dacc* pDacHw ; + /** Current SpiCommand being processed */ + DacCmd *pCurrentCommand ; + /** Pointer to DMA driver */ + sXdmad* pXdmad ; + /** DACC Id as defined in the product datasheet */ + uint8_t dacId ; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore ; +} DacDma; + + +/*------------------------------------------------------------------------------ + * Definitions + *------------------------------------------------------------------------------*/ +#define DAC_OK 0 +#define DAC_ERROR 1 +#define DAC_ERROR_LOCK 2 + +#define DACC_CHANNEL_0 0 +#define DACC_CHANNEL_1 1 + +/*------------------------------------------------------------------------------ + * Exported functions + *------------------------------------------------------------------------------*/ +extern uint32_t Dac_ConfigureDma( DacDma *pDacd , + Dacc *pDacHw , + uint8_t DacId, + sXdmad *pXdmad ); +extern uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand); + + +/*------------------------------------------------------------------------------ + * Macros function of register access + *------------------------------------------------------------------------------*/ +#define DACC_SoftReset(pDACC) ((pDACC)->DACC_CR = DACC_CR_SWRST) +#define DACC_CfgModeReg(pDACC, mode) { (pDACC)->DACC_MR = (mode); } +#define DACC_GetModeReg(pDACC) ((pDACC)->DACC_MR) +#define DACC_CfgTrigger(pDACC, mode) { (pDACC)->DACC_TRIGR = (mode); } + +#define DACC_EnableChannel(pDACC, channel) {(pDACC)->DACC_CHER = (1 << (channel));} +#define DACC_DisableChannel(pDACC, channel) {(pDACC)->DACC_CHDR = (1 << (channel));} + +#define DACC_EnableIt(pDACC, mode) {(pDACC)->DACC_IER = (mode);} +#define DACC_DisableIt(pDACC, mode) {(pDACC)->DACC_IDR = (mode);} +#define DACC_GetStatus(pDACC) ((pDACC)->DACC_ISR) +#define DACC_GetChannelStatus(pDACC) ((pDACC)->DACC_CHSR) +#define DACC_GetInterruptMaskStatus(pDACC) ((pDACC)->DACC_IMR) + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _DAC_DMA_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/efc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/efc.h new file mode 100644 index 000000000..5252968f1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/efc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuration the Enhanced Embedded Flash Controller (EEFC) + * peripheral. + * + * \section Usage + * + * -# Enable/disable %flash ready interrupt sources using EFC_EnableFrdyIt() + * and EFC_DisableFrdyIt(). + * -# Translates the given address into which EEFC, page and offset values + * for difference density %flash memory using EFC_TranslateAddress(). + * -# Computes the address of a %flash access given the EFC, page and offset + * for difference density %flash memory using EFC_ComputeAddress(). + * -# Start the executing command with EFC_PerformCommand() + * -# Retrieve the current status of the EFC using EFC_GetStatus(). + * -# Retrieve the result of the last executed command with EFC_GetResult(). + */ + +#ifndef _EEFC_ +#define _EEFC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* TODO: Temporary definition for missing symbol in header file */ +#define IFLASH_SECTOR_SIZE 65536u + + +/* EFC command */ +#define EFC_FCMD_GETD 0x00 /* Get Flash Descriptor */ +#define EFC_FCMD_WP 0x01 /* Write page */ +#define EFC_FCMD_WPL 0x02 /* Write page and lock */ +#define EFC_FCMD_EWP 0x03 /* Erase page and write page */ +#define EFC_FCMD_EWPL 0x04 /* Erase page and write page then lock */ +#define EFC_FCMD_EA 0x05 /* Erase all */ +#define EFC_FCMD_EPA 0x07 /* Erase pages */ +#define EFC_FCMD_SLB 0x08 /* Set Lock Bit */ +#define EFC_FCMD_CLB 0x09 /* Clear Lock Bit */ +#define EFC_FCMD_GLB 0x0A /* Get Lock Bit */ +#define EFC_FCMD_SFB 0x0B /* Set GPNVM Bit */ +#define EFC_FCMD_CFB 0x0C /* Clear GPNVM Bit */ +#define EFC_FCMD_GFB 0x0D /* Get GPNVM Bit */ +#define EFC_FCMD_STUI 0x0E /* Start unique ID */ +#define EFC_FCMD_SPUI 0x0F /* Stop unique ID */ +#define EFC_FCMD_GCALB 0x10 /* Get CALIB Bit */ +#define EFC_FCMD_ES 0x11 /* Erase Sector */ +#define EFC_FCMD_WUS 0x12 /* Write User Signature */ +#define EFC_FCMD_EUS 0x13 /* Erase User Signature */ +#define EFC_FCMD_STUS 0x14 /* Start Read User Signature */ +#define EFC_FCMD_SPUS 0x15 /* Stop Read User Signature */ + +/* The IAP function entry address */ +#define CHIP_FLASH_IAP_ADDRESS (0x00800008) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void EFC_EnableFrdyIt( Efc* efc ) ; + +extern void EFC_DisableFrdyIt( Efc* efc ) ; + +extern void EFC_SetWaitState( Efc* efc, uint8_t cycles ) ; + +extern void EFC_TranslateAddress( Efc** pEfc, uint32_t dwAddress, + uint16_t *pwPage, uint16_t *pwOffset ) ; + +extern void EFC_ComputeAddress( Efc* efc, uint16_t wPage, uint16_t wOffset, + uint32_t *pdwAddress ) ; + +extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, + uint32_t dwArgument, uint32_t dwUseIAP ) ; + +extern uint32_t EFC_GetStatus( Efc* efc ) ; + +extern uint32_t EFC_GetResult( Efc* efc ) ; + +extern void EFC_SetFlashAccessMode(Efc* efc, uint32_t dwMode) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _EEFC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/exceptions.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/exceptions.h new file mode 100644 index 000000000..514b5d001 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/exceptions.h @@ -0,0 +1,52 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * Interface for default exception handlers. + */ + +#ifndef _EXCEPTIONS_ +#define _EXCEPTIONS_ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/* Function prototype for exception table items (interrupt handler). */ +typedef void( *IntFunc )( void ) ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* Default empty handler */ +extern void IrqHandlerNotUsed( void ) ; + +#endif /* _EXCEPTIONS_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/flashd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/flashd.h new file mode 100644 index 000000000..7e42615f9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/flashd.h @@ -0,0 +1,91 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- +*/ + +/** + * \file + * + * The flash driver provides the unified interface for flash program operations. + * + */ + +#ifndef _FLASHD_ +#define _FLASHD_ + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +#define GPNVBit_SecurityBit 0 +#define GPNVBit_BootMode 1 +#define GPNVBit_TCMBit1 6 +#define GPNVBit_TCMBit2 7 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP ) ; + +extern uint32_t FLASHD_Erase( uint32_t dwAddress ) ; + +extern uint32_t FLASHD_EraseSector( uint32_t dwAddress ) ; + +extern uint32_t FLASHD_ErasePages( uint32_t dwAddress, uint32_t dwPageNum ) ; + +extern uint32_t FLASHD_Write( uint32_t dwAddress, const void *pvBuffer, + uint32_t dwSize ) ; + +extern uint32_t FLASHD_Lock( uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ; + +extern uint32_t FLASHD_Unlock( uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) ; + +extern uint32_t FLASHD_IsLocked( uint32_t dwStart, uint32_t dwEnd ) ; + +extern uint32_t FLASHD_SetGPNVM( uint8_t gpnvm ) ; + +extern uint32_t FLASHD_ClearGPNVM( uint8_t gpnvm ) ; + +extern uint32_t FLASHD_IsGPNVMSet( uint8_t gpnvm ) ; + +#define FLASHD_IsSecurityBitSet() FLASHD_IsGPNVMSet( 0 ) + +#define FLASHD_SetSecurityBit() FLASHD_SetGPNVM( 0 ) + +extern uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _FLASHD_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/gmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/gmac.h new file mode 100644 index 000000000..68c90fb02 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/gmac.h @@ -0,0 +1,334 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmac_module + * @{ + * Provides the interface to configure and use the GMAC peripheral. + * + * \section gmac_usage Usage + * - Configure Gmac::GMAC_NCFG with GMAC_Configure(), some of related controls + * are also available, such as: + * - GMAC_SetSpeed(): Setup GMAC working clock. + * - GMAC_FullDuplexEnable(): Working in full duplex or not. + * - GMAC_CpyAllEnable(): Copying all valid frames (\ref GMAC_NCFG_CAF). + * - ... + * - Setup Gmac::GMAC_NCR with GMAC_NetworkControl(), more related controls + * can modify with: + * - GMAC_ReceiveEnable(): Enable/Disable Rx. + * - GMAC_TransmitEnable(): Enable/Disable Tx. + * - GMAC_BroadcastDisable(): Enable/Disable broadcast receiving. + * - ... + * - Manage GMAC interrupts with GMAC_EnableIt(), GMAC_DisableIt(), + * GMAC_GetItMask() and GMAC_GetItStatus(). + * - Manage GMAC Tx/Rx status with GMAC_GetTxStatus(), GMAC_GetRxStatus() + * GMAC_ClearTxStatus() and GMAC_ClearRxStatus(). + * - Manage GMAC Queue with GMAC_SetTxQueue(), GMAC_GetTxQueue(), + * GMAC_SetRxQueue() and GMAC_GetRxQueue(), the queue descriptor can define + * by \ref sGmacRxDescriptor and \ref sGmacTxDescriptor. + * - Manage PHY through GMAC is performed by + * - GMAC_ManagementEnable(): Enable/Disable PHY management. + * - GMAC_PHYMaintain(): Execute PHY management commands. + * - GMAC_PHYData(): Return PHY management data. + * - GMAC_IsIdle(): Check if PHY is idle. + * - Setup GMAC parameters with following functions: + * - GMAC_SetHash(): Set Hash value. + * - GMAC_SetAddress(): Set MAC address. + * - Enable/Disable GMAC transceiver clock via GMAC_TransceiverClockEnable() + * - Switch GMAC MII/RMII mode through GMAC_RMIIEnable() + * + * For more accurate information, please look at the GMAC section of the + * Datasheet. + * + * \sa \ref gmacd_module + * + * Related files:\n + * gmac.c\n + * gmac.h.\n + * + * \defgroup gmac_defines GMAC Defines + * \defgroup gmac_structs GMAC Data Structs + * \defgroup gmac_functions GMAC Functions + */ +/**@}*/ + +#ifndef _GMAC_H +#define _GMAC_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Defines + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_defines + @{*/ + +#define NUM_GMAC_QUEUES 3 +/// Board GMAC base address + + +#define GMAC_DUPLEX_HALF 0 +#define GMAC_DUPLEX_FULL 1 + +// +#define GMAC_SPEED_10M 0 +#define GMAC_SPEED_100M 1 +#define GMAC_SPEED_1000M 2 + +/*------------------------------------------------------------------------------ + Definitions +------------------------------------------------------------------------------ +*/ +/// The buffer addresses written into the descriptors must be aligned so the +/// last few bits are zero. These bits have special meaning for the GMAC +/// peripheral and cannot be used as part of the address. +#define GMAC_ADDRESS_MASK ((unsigned int)0xFFFFFFFC) +#define GMAC_LENGTH_FRAME ((unsigned int)0x3FFF) /// Length of frame mask + +// receive buffer descriptor bits +#define GMAC_RX_OWNERSHIP_BIT (1u << 0) +#define GMAC_RX_WRAP_BIT (1u << 1) +#define GMAC_RX_SOF_BIT (1u << 14) +#define GMAC_RX_EOF_BIT (1u << 15) + +// Transmit buffer descriptor bits +#define GMAC_TX_LAST_BUFFER_BIT (1u << 15) +#define GMAC_TX_WRAP_BIT (1u << 30) +#define GMAC_TX_USED_BIT (1u << 31) +#define GMAC_TX_RLE_BIT (1u << 29) /// Retry Limit Exceeded +#define GMAC_TX_UND_BIT (1u << 28) /// Tx Buffer Under-run +#define GMAC_TX_ERR_BIT (1u << 27) /// Exhausted in mid-frame +#define GMAC_TX_ERR_BITS \ + (GMAC_TX_RLE_BIT | GMAC_TX_UND_BIT | GMAC_TX_ERR_BIT) + +// Interrupt bits +#define GMAC_INT_RX_BITS \ + (GMAC_IER_RCOMP | GMAC_IER_RXUBR | GMAC_IER_ROVR) +#define GMAC_INT_TX_ERR_BITS \ + (GMAC_IER_TUR | GMAC_IER_RLEX | GMAC_IER_TFC | GMAC_IER_HRESP) +#define GMAC_INT_TX_BITS \ + (GMAC_INT_TX_ERR_BITS | GMAC_IER_TCOMP) +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup gmac_structs + @{*/ + +/* This is the list of GMAC queue */ +typedef enum { + GMAC_QUE_0 = 0, + GMAC_QUE_1 = 1, + GMAC_QUE_2 = 2 +}gmacQueList_t; + +/** Receive buffer descriptor struct */ +typedef struct _GmacRxDescriptor { + union _GmacRxAddr { + uint32_t val; + struct _GmacRxAddrBM { + uint32_t bOwnership:1, /**< User clear, GMAC set this to one once + it has successfully written a frame to + memory */ + bWrap:1, /**< Marks last descriptor in receive buffer */ + addrDW:30; /**< Address in number of DW */ + } bm; + } addr; /**< Address, Wrap & Ownership */ + union _GmacRxStatus { + uint32_t val; + struct _GmacRxStatusBM { + uint32_t len:12, /** Length of frame including FCS */ + offset:2, /** Receive buffer offset, + bits 13:12 of frame length for jumbo + frame */ + bSof:1, /** Start of frame */ + bEof:1, /** End of frame */ + bCFI:1, /** Concatenation Format Indicator */ + vlanPriority:3, /** VLAN priority (if VLAN detected) */ + bPriorityDetected:1, /** Priority tag detected */ + bVlanDetected:1, /**< VLAN tag detected */ + bTypeIDMatch:1, /**< Type ID match */ + bAddr4Match:1, /**< Address register 4 match */ + bAddr3Match:1, /**< Address register 3 match */ + bAddr2Match:1, /**< Address register 2 match */ + bAddr1Match:1, /**< Address register 1 match */ + reserved:1, + bExtAddrMatch:1, /**< External address match */ + bUniHashMatch:1, /**< Unicast hash match */ + bMultiHashMatch:1, /**< Multicast hash match */ + bBroadcastDetected:1; /**< Global all ones broadcast + address detected */ + } bm; + } status; +} sGmacRxDescriptor ; /* GCC */ + +/** Transmit buffer descriptor struct */ +typedef struct _GmacTxDescriptor { + uint32_t addr; + union _GmacTxStatus { + uint32_t val; + struct _GmacTxStatusBM { + uint32_t len:11, /**< Length of buffer */ + reserved:4, + bLastBuffer:1, /**< Last buffer (in the current frame) */ + bNoCRC:1, /**< No CRC */ + reserved1:10, + bExhausted:1, /**< Buffer exhausted in mid frame */ + bUnderrun:1, /**< Transmit under run */ + bError:1, /**< Retry limit exceeded, error detected */ + bWrap:1, /**< Marks last descriptor in TD list */ + bUsed:1; /**< User clear, GMAC sets this once a frame + has been successfully transmitted */ + } bm; + } status; +} sGmacTxDescriptor; /* GCC */ + +/** @}*/ + +//----------------------------------------------------------------------------- +// PHY Exported functions +//----------------------------------------------------------------------------- +extern uint8_t GMAC_IsIdle(Gmac *pGmac); +extern void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData); +extern uint16_t GMAC_PHYData(Gmac *pGmac); +extern void GMAC_ClearStatistics(Gmac *pGmac); +extern void GMAC_IncreaseStatistics(Gmac *pGmac); +extern void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint8_t GMAC_SetMdcClock(Gmac *pGmac, uint32_t mck ); +extern void GMAC_EnableMdio(Gmac *pGmac ); +extern void GMAC_DisableMdio(Gmac *pGmac ); +extern void GMAC_EnableMII(Gmac *pGmac ); +extern void GMAC_EnableRMII(Gmac *pGmac ); +extern void GMAC_EnableGMII( Gmac *pGmac ); +extern void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex); +extern void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx); +extern void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx); +extern void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources); +extern uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxStatus(Gmac *pGmac); +extern void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus); +extern uint32_t GMAC_GetRxStatus(Gmac *pGmac); +extern void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus); +extern void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis); +extern void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis); +extern uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac); +extern void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx); +extern void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR); +extern uint32_t GMAC_GetNetworkControl(Gmac *pGmac); +extern void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr); +extern void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB); +extern void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac); +extern void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg); +extern void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx); +extern uint32_t GMAC_GetConfigure(Gmac *pGmac); +extern void GMAC_TransmissionStart(Gmac *pGmac); +extern void GMAC_TransmissionHalt(Gmac *pGmac); +extern void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed); + +void GMAC_ClearScreener1Reg (Gmac* pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener1Reg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal); + +void GMAC_ClearScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx); + +void GMAC_WriteScreener2Reg (Gmac* pGmac, gmacQueList_t queueIdx, uint32_t regVal); + +void GMAC_WriteEthTypeReg (Gmac* pGmac, gmacQueList_t queueIdx, uint16_t etherType); + +void GMAC_WriteCompareReg(Gmac* pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, uint16_t c1Reg); + +void GMAC_EnableCbsQueA(Gmac *pGmac); + +void GMAC_DisableCbsQueA(Gmac *pGmac); + +void GMAC_EnableCbsQueB(Gmac *pGmac); + +void GMAC_DisableCbsQueB(Gmac *pGmac); + +void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA); + +void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB); + +void GMAC_SetTsuTmrIncReg( Gmac *pGmac, uint32_t nanoSec); + +uint16_t GMAC_GetPtpEvtMsgRxdMsbSec( Gmac *pGmac ); + +uint32_t GMAC_GetPtpEvtMsgRxdLsbSec( Gmac *pGmac ); + +uint32_t GMAC_GetPtpEvtMsgRxdNanoSec( Gmac *pGmac ); + +void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, uint32_t nanosec ); + +void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec); + +void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31); + +void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47); + +uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac); + +uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac); + +#ifdef __cplusplus +} +#endif + +#endif // #ifndef GMAC_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/gmacd.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/gmacd.h new file mode 100644 index 000000000..68ef02a48 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/gmacd.h @@ -0,0 +1,284 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup gmacd_module + * @{ + * Implement GMAC data transfer and PHY management functions. + * + * \section Usage + * -# Implement GMAC interrupt handler, which must invoke GMACD_Handler() + * to handle GMAC interrupt events. + * -# Implement sGmacd instance in application. + * -# Initialize the instance with GMACD_Init() and GMACD_InitTransfer(), + * so that GMAC data can be transmitted/received. + * -# Some management callbacks can be set by GMACD_SetRxCallback() + * and GMACD_SetTxWakeupCallback(). + * -# Send ethernet packets using GMACD_Send(), GMACD_TxLoad() is used + * to check the free space in TX queue. + * -# Check and obtain received ethernet packets via GMACD_Poll(). + * + * \sa \ref gmacb_module, \ref gmac_module + * + * Related files:\n + * \ref gmacd.c\n + * \ref gmacd.h.\n + * + * \defgroup gmacd_defines GMAC Driver Defines + * \defgroup gmacd_types GMAC Driver Types + * \defgroup gmacd_functions GMAC Driver Functions + */ +/**@}*/ + +#ifndef _GMACD_H_ +#define _GMACD_H_ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_defines + @{*/ + + +/** \addtogroup gmacd_rc GMACD Return Codes + @{*/ +#define GMACD_OK 0 /**< Operation OK */ +#define GMACD_TX_BUSY 1 /**< TX in progress */ +#define GMACD_RX_NULL 1 /**< No data received */ +/** Buffer size not enough */ +#define GMACD_SIZE_TOO_SMALL 2 +/** Parameter error, TX packet invalid or RX size too small */ +#define GMACD_PARAM 3 +/** Transfer is not initialized */ +#define GMACD_NOT_INITIALIZED 4 +/** @}*/ + +/** @}*/ + +/* Should be a power of 2. + - Buffer Length to store the timestamps of 1588 event messages +*/ +#define EFRS_BUFFER_LEN (1u) + +/*--------------------------------------------------------------------------- +* Types +*---------------------------------------------------------------------------*/ +/** \addtogroup gmacd_types + @{*/ + +typedef enum ptpMsgType_t +{ + SYNC_MSG_TYPE = 0, + DELAY_REQ_MSG_TYPE = 1, + PDELAY_REQ_TYPE = 2, + PDELAY_RESP_TYPE = 3, + FOLLOW_UP_MSG_TYPE = 8, + DELAY_RESP_MSG_TYPE = 9 +}ptpMsgType; + + + +/** RX callback */ +typedef void (*fGmacdTransferCallback)(uint32_t status); +/** Wakeup callback */ +typedef void (*fGmacdWakeupCallback)(void); +/** Tx PTP message callback */ +typedef void (*fGmacdTxPtpEvtCallBack) (ptpMsgType msg, uint32_t sec, \ + uint32_t nanosec, uint16_t seqId); + +/** + * GMAC scatter-gather entry. + */ +typedef struct _GmacSG { + uint32_t size; + void *pBuffer; +} sGmacSG; + +/** + * GMAC scatter-gather list. + */ +typedef struct _GmacSGList { + uint32_t len; + sGmacSG *sg; +} sGmacSGList; + +/** + * GMAC Queue driver. + */ +typedef struct _GmacQueueDriver { + uint8_t *pTxBuffer; + /** Pointer to allocated RX buffer */ + uint8_t *pRxBuffer; + + /** Pointer to Rx TDs (must be 8-byte aligned) */ + sGmacRxDescriptor *pRxD; + /** Pointer to Tx TDs (must be 8-byte aligned) */ + sGmacTxDescriptor *pTxD; + + /** Optional callback to be invoked once a frame has been received */ + fGmacdTransferCallback fRxCb; + /** Optional callback to be invoked once several TD have been released */ + fGmacdWakeupCallback fWakupCb; + /** Optional callback list to be invoked once TD has been processed */ + fGmacdTransferCallback *fTxCbList; + + /** Optional callback to be invoked on transmit of PTP Event messages */ + fGmacdTxPtpEvtCallBack fTxPtpEvtCb; + + /** RX TD list size */ + uint16_t wRxListSize; + /** RX index for current processing TD */ + uint16_t wRxI; + + /** TX TD list size */ + uint16_t wTxListSize; + /** Circular buffer head pointer by upper layer (buffer to be sent) */ + uint16_t wTxHead; + /** Circular buffer tail pointer incremented by handlers (buffer sent) */ + uint16_t wTxTail; + + /** Number of free TD before wakeup callback is invoked */ + uint8_t bWakeupThreshold; + + /** RX buffer size */ + uint16_t wTxBufferSize; + uint16_t wRxBufferSize; + +} sGmacQd; + +/** + * GMAC driver struct. + */ +typedef struct _GmacDriver { + + /** Pointer to HW register base */ + Gmac *pHw; + /** HW ID */ + uint8_t bId; + /** Base Queue list params **/ + sGmacQd queueList[NUM_GMAC_QUEUES]; +} sGmacd; + +/** + * GMAC driver init struct. + */ +typedef struct _GmacInit { + uint32_t bIsGem:1; + uint32_t reserved:31; + + uint8_t bDmaBurstLength; + + /** RX descriptor and data buffers */ + uint8_t *pRxBuffer; + /** RX data buffers: should be wRxBufferSize * wRxSize byte long in a DMA + capable memory region */ + sGmacRxDescriptor *pRxD; + /** RX buffer descriptors: should have wRxSize entries in a DMA + capable memory region */ + uint16_t wRxBufferSize; /** size of a single RX data buffer */ + uint16_t wRxSize; /** number of RX descriptor and data buffers */ + + /** TX descriptor and data buffers */ + /** TX data buffers: should be wTxBufferSize * wTxSize byte long + in a DMA capable memory region */ + uint8_t *pTxBuffer; + /** TX buffer descriptors: should have wTxSize entries + in a DMA capable non-cached memory region */ + sGmacTxDescriptor *pTxD; + /** size of a single TX data buffer */ + uint16_t wTxBufferSize; + /** number of TX descriptor and data buffers */ + uint16_t wTxSize; + + fGmacdTransferCallback *pTxCb; /** should have wTxSize entries */ +} sGmacInit; +/** @}*/ + +/** \addtogroup gmacd_functions + @{*/ + +/*--------------------------------------------------------------------------- + * GMAC Exported functions + *---------------------------------------------------------------------------*/ + +extern void GMACD_Handler(sGmacd *pGmacd , gmacQueList_t queIdx); + +extern void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC ); + +extern uint8_t GMACD_InitTransfer(sGmacd *pGmacd, + const sGmacInit *pInit, gmacQueList_t queIdx); + +extern void GMACD_Reset(sGmacd *pGmacd); + +extern uint8_t GMACD_SendSG(sGmacd *pGmacd, + const sGmacSGList *sgl, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx); + +extern uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx ); + +extern uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx); + +extern uint8_t GMACD_Poll(sGmacd * pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize, + gmacQueList_t queIdx); + +extern void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback + fRxCb, gmacQueList_t queIdx); + +extern uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold, + gmacQueList_t queIdx); + +extern void GMACD_TxPtpEvtMsgCBRegister (sGmacd * pGmacd, + fGmacdTxPtpEvtCallBack pTxPtpEvtCb, + gmacQueList_t queIdx); + +/** @}*/ + +#endif // #ifndef _GMACD_H_ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/hsmci.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/hsmci.h new file mode 100644 index 000000000..0f54562a9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/hsmci.h @@ -0,0 +1,154 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup hsmci_module Working with HSMCI + * \ingroup mcid_module + * + * \section Purpose + * + * The HSMCI driver provides the interface to configure and use the HSMCI + * peripheral. + * + * \section Usage + * + * -# HSMCI_Enable(), MCI_Disable(): Enable/Disable HSMCI interface. + * -# HSMCI_Reset(): Reset HSMCI interface. + * -# HSMCI_Select(): HSMCI slot and buswidth selection + * (\ref Hsmci::HSMCI_SDCR). + * -# HSMCI_ConfigureMode(): Configure the MCI CLKDIV in the _MR register + * (\ref Hsmci::HSMCI_MR). + * -# HSMCI_EnableIt(), HSMCI_DisableIt(), HSMCI_GetItMask(), HSMCI_GetStatus() + * HSMCI Interrupt control (\ref Hsmci::HSMCI_IER, \ref Hsmci::HSMCI_IDR, + * \ref Hsmci::HSMCI_IMR, \ref Hsmci::HSMCI_SR). + * -# HSMCI_ConfigureTransfer(): Setup block length and count for MCI transfer + * (\ref Hsmci::HSMCI_BLKR). + * -# HSMCI_SendCmd(): Send SD/MMC command with argument + * (\ref Hsmci::HSMCI_ARGR, \ref Hsmci::HSMCI_CMDR). + * -# HSMCI_GetResponse(): Get SD/MMC response after command finished + * (\ref Hsmci::HSMCI_RSPR). + * -# HSMCI_ConfigureDma(): Configure MCI DMA transfer + * (\ref Hsmci::HSMCI_DMA). + * -# HSMCI_Configure(): Configure the HSMCI interface (\ref Hsmci::HSMCI_CFG). + * -# HSMCI_HsEnable(), HSMCI_IsHsEnabled(): High Speed control. + * + * For more accurate information, please look at the HSMCI section of the + * Datasheet. + * + * \sa \ref mcid_module + * + * Related files :\n + * \ref hsmci.h\n + * \ref hsmci.c.\n + */ + +#ifndef HSMCID_H +#define HSMCID_H +/** \addtogroup hsmci_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup hsmci_functions HSMCI Functions + * @{ + */ + +extern void HSMCI_Enable(Hsmci* pRMci); +extern void HSMCI_Disable(Hsmci* pRMci); +extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup); + +extern void HSMCI_Select(Hsmci * pRMci,uint8_t bSlot,uint8_t bBusWidth); +extern void HSMCI_SetSlot(Hsmci * pRMci,uint8_t bSlot); +extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth); +extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci); + +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode); +extern uint32_t HSMCI_GetMode(Hsmci *pRMci); +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof); +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv); +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn); +extern uint8_t HSMCI_IsFByteEnabled(Hsmci * pRMci); +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv); + +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources); +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources); +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci); + +extern void HSMCI_ConfigureTransfer(Hsmci * pRMci,uint16_t wBlkLen,uint16_t wCnt); +extern void HSMCI_SetBlockLen(Hsmci * pRMci,uint16_t wBlkSize); +extern void HSMCI_SetBlockCount(Hsmci * pRMci,uint16_t wBlkCnt); + +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure); + +extern void HSMCI_SendCmd(Hsmci * pRMci,uint32_t dwCmd,uint32_t dwArg); +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci); +extern uint32_t HSMCI_Read(Hsmci *pRMci); +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData); +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize); + +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci); + +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_EnableDma(Hsmci * pRMci,uint8_t bEnable); + +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure); +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable); +extern uint8_t HSMCI_IsHsEnabled(Hsmci *pRMci); + +extern void HSMCI_BusWidthCtl(Hsmci *pRMci, uint8_t bBusWidth); +extern void HSMCI_SlotCtl(Hsmci *pRMci, uint8_t bSlot); +extern uint8_t HSMCI_GetSlot(Hsmci *pRMci); + +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure); +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci); + +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/icm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/icm.h new file mode 100644 index 000000000..eaa04aa16 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/icm.h @@ -0,0 +1,113 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _ICM_ +#define _ICM_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*------------------------------------------------------------------------------*/ +/* Definition */ +/*------------------------------------------------------------------------------*/ +#define ICM_RCFG_CDWBN (0x1u << 0) +/**< \brief (ICM_RCFG) Compare Digest or Write Back Digest */ +#define ICM_RCFG_WRAP (0x1u << 1) +/**< \brief (ICM_RCFG) Wrap Command */ +#define ICM_RCFG_EOM (0x1u << 2) +/**< \brief (ICM_RCFG) End Of Monitoring */ +#define ICM_RCFG_RHIEN (0x1u << 4) +/**< \brief (ICM_RCFG) Region Hash Completed interrupt enable */ +#define ICM_RCFG_DMIEN (0x1u << 5) +/**< \brief (ICM_RCFG) Digest Mismatch interrupt enable */ +#define ICM_RCFG_BEIEN (0x1u << 6) +/**< \brief (ICM_RCFG) Bus error interrupt enable */ +#define ICM_RCFG_WCIEN (0x1u << 7) +/**< \brief (ICM_RCFG) Warp condition interrupt enable */ +#define ICM_RCFG_ECIEN (0x1u << 8) +/**< \brief (ICM_RCFG) End bit condition interrupt enable */ +#define ICM_RCFG_SUIEN (0x1u << 9) +/**< \brief (ICM_RCFG) Monitoring Status Updated Condition Interrupt Enable */ +#define ICM_RCFG_PROCDLY (0x1u << 10) +/**< \brief (ICM_RCFG) Processing Delay*/ +#define ICM_RCFG_UALGO_Pos 12 +#define ICM_RCFG_UALGO_Msk (0x7u << ICM_RCFG_UALGO_Pos) +/**< \brief (ICM_RCFG) User SHA Algorithm */ +#define ICM_RCFG_ALGO_SHA1 (0x0u << 12) +/**< \brief (ICM_RCFG) SHA1 algorithm processed */ +#define ICM_RCFG_ALGO_SHA256 (0x1u << 12) +/**< \brief (ICM_RCFG) SHA256 algorithm processed */ +#define ICM_RCFG_ALGO_SHA224 (0x4u << 12) +/**< \brief (ICM_RCFG) SHA224 algorithm processed */ +#define ICM_RCFG_MRPROT_Pos 24 +#define ICM_RCFG_MRPROT_Msk (0x3fu << ICM_RCFG_MRPROT_Pos) +/**< \brief (ICM_RCFG) Memory Region AHB Protection */ +#define ICM_RCFG_MRPROT(value) \ + ((ICM_RCFG_MRPROT_Msk & ((value) << ICM_RCFG_MRPROT_Pos))) + +/*----------------------------------------------------------------------------*/ +/* Type */ +/*----------------------------------------------------------------------------*/ + +/** \brief Structure ICM region descriptor area. */ +typedef struct _LinkedListDescriporIcmRegion +{ + /** the first byte address of the Region. */ + uint32_t icm_raddr; + /** Configuration Structure Member. */ + uint32_t icm_rcfg; + /** Control Structure Member. */ + uint32_t icm_rctrl; + /** Next Address Structure Member. */ + uint32_t icm_rnext; +}LinkedListDescriporIcmRegion; + +/*----------------------------------------------------------------------------*/ +/* Exported functions */ +/*----------------------------------------------------------------------------*/ +extern void ICM_Enable(void); +extern void ICM_Disable(void); +extern void ICM_SoftReset(void); +extern void ICM_ReComputeHash(uint8_t region); +extern void ICM_EnableMonitor(uint8_t region); +extern void ICM_DisableMonitor(uint8_t region); +extern void ICM_Configure(uint32_t mode); +extern void ICM_EnableIt(uint32_t sources); +extern void ICM_DisableIt(uint32_t sources); +extern uint32_t ICM_GetIntStatus(void); +extern uint32_t ICM_GetStatus(void); +extern uint32_t ICM_GetUStatus(void); +extern void ICM_SetDescStartAddress(uint32_t addr); +extern void ICM_SetHashStartAddress(uint32_t addr); +extern void ICM_SetInitHashValue(uint32_t val); +#endif /* #ifndef _ICM_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/isi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/isi.h new file mode 100644 index 000000000..943f07b83 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/isi.h @@ -0,0 +1,204 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup isi_module + * @{ + * \section gmac_usage Usage + * - ISI_Init: initialize ISI with default parameters + * - ISI_EnableInterrupt: enable one or more interrupts + * - ISI_DisableInterrupt: disable one or more interrupts + * - ISI_Enable: enable isi module + * - ISI_Disable: disable isi module + * - ISI_CodecPathFull: enable codec path + * - ISI_SetFrame: set frame rate + * - ISI_BytesForOnePixel: return number of byte for one pixel + * - ISI_StatusRegister: return ISI status register + * - ISI_Reset: make a software reset + */ +/**@}*/ + +#ifndef ISI_H +#define ISI_H + + + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define YUV_INPUT 0 +#define RGB_INPUT 1 +#define GRAYSCALE_INPUT 2 + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** ISI descriptors */ +typedef struct +{ + /** Current LCD index, used with AT91C_ISI_MAX_PREV_BUFFER */ + uint32_t CurrentLcdIndex; + /** set if Fifo Codec Empty is present */ + volatile uint32_t DisplayCodec; + /** upgrade for each Fifo Codec Overflow (statistics use) */ + uint32_t nb_codec_ovf; + /** upgrade for each Fifo Preview Overflow (statistics use) */ + uint32_t nb_prev_ovf; +}ISI_Descriptors; + +/** Frame Buffer Descriptors */ +typedef struct +{ + /** Address of the Current FrameBuffer */ + uint32_t Current; + /** Address of the Control */ + uint32_t Control; + /** Address of the Next FrameBuffer */ + uint32_t Next; +}ISI_FrameBufferDescriptors; + + +/** ISI Matrix Color Space Conversion YCrCb to RGB */ +typedef struct +{ + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Matrix Coefficient C3 */ + uint8_t C3; + /** Color Space Conversion Red Chrominance Default Offset */ + uint8_t Croff; + /** Color Space Conversion Blue Chrominance Default Offset */ + uint8_t Cboff; + /** Color Space Conversion Luminance Default Offset */ + uint8_t Yoff; + /** Color Space Conversion Matrix Coefficient C4 */ + uint16_t C4; +}ISI_Y2R; + +/** ISI Matrix Color Space Conversion RGB to YCrCb */ +typedef struct +{ + /** Color Space Conversion Matrix Coefficient C0*/ + uint8_t C0; + /** Color Space Conversion Matrix Coefficient C1 */ + uint8_t C1; + /** Color Space Conversion Matrix Coefficient C2 */ + uint8_t C2; + /** Color Space Conversion Red Component Offset */ + uint8_t Roff; + /** Color Space Conversion Matrix Coefficient C3*/ + uint8_t C3; + /** Color Space Conversion Matrix Coefficient C4 */ + uint8_t C4; + /** Color Space Conversion Matrix Coefficient C5 */ + uint8_t C5; + /** Color Space Conversion Green Component Offset */ + uint8_t Goff; + /** Color Space Conversion Matrix Coefficient C6*/ + uint8_t C6; + /** Color Space Conversion Matrix Coefficient C7 */ + uint8_t C7; + /** Color Space Conversion Matrix Coefficient C8 */ + uint8_t C8; + /** Color Space Conversion Blue Component Offset */ + uint8_t Boff; +}ISI_R2Y; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void ISI_Enable(void); + +extern void ISI_Disable(void); + +void ISI_DmaChannelEnable(uint32_t channel); + +void ISI_DmaChannelDisable(uint32_t channel); + +extern void ISI_EnableInterrupt(uint32_t flag); + +extern void ISI_DisableInterrupt(uint32_t flag); + +extern void ISI_CodecPathFull(void); + +extern void ISI_SetFrameRate(uint32_t frame); + +extern uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb); + +extern void ISI_Reset(void); + +extern void ISI_Init(pIsi_Video pVideo); + +extern uint32_t ISI_StatusRegister(void); + +extern void ISI_SetBlank( + uint8_t hBlank, + uint8_t vBlank); + +extern void ISI_SetSensorSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_RgbPixelMapping(uint32_t wRgbPixelMapping); + +extern void ISI_RgbSwapMode(uint32_t swapMode); + +extern void ISI_YCrCbFormat(uint32_t wYuvSwapMode); + +extern void ISI_setGrayScaleMode(uint32_t wPixelFormat); + +extern void ISI_setInputStream(uint32_t wStreamMode); + +extern void ISI_setPreviewSize( + uint32_t hSize, + uint32_t vSize); + +extern void ISI_calcScalerFactor( void ); + +extern void ISI_setDmaInPreviewPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_setDmaInCodecPath( + uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, + uint32_t frameBufferStartAddr); + +extern void ISI_SetMatrix4Yuv2Rgb (ISI_Y2R* yuv2rgb); +extern void ISI_SetMatrix4Rgb2Yuv (ISI_R2Y* rgb2yuv); + +#endif //#ifndef ISI_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/iso7816_4.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/iso7816_4.h new file mode 100644 index 000000000..0b173719b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/iso7816_4.h @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +//------------------------------------------------------------------------------ +/** \page + * + * \section Purpose + * + * Definition of methods for ISO7816 driver. + * + * \section Usage + * + * -# ISO7816_Init + * -# ISO7816_IccPowerOff + * -# ISO7816_XfrBlockTPDU_T0 + * -# ISO7816_Escape + * -# ISO7816_RestartClock + * -# ISO7816_StopClock + * -# ISO7816_toAPDU + * -# ISO7816_Datablock_ATR + * -# ISO7816_SetDataRateandClockFrequency + * -# ISO7816_StatusReset + * -# ISO7816_cold_reset + * -# ISO7816_warm_reset + * -# ISO7816_Decode_ATR + *----------------------------------------------------------------------------*/ + +#ifndef ISO7816_4_H +#define ISO7816_4_H + +#include "chip.h" + +/*------------------------------------------------------------------------------ + * Constants Definition + *----------------------------------------------------------------------------*/ + +/** Size max of Answer To Reset */ +#define ATR_SIZE_MAX 55 + +/** NULL byte to restart byte procedure */ +#define ISO_NULL_VAL 0x60 + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void ISO7816_Init( + Usart *pUsart, + uint32_t usartId , + const Pin pPinIso7816RstMC ); + +extern void ISO7816_IccPowerOff( void ); + +extern uint16_t ISO7816_XfrBlockTPDU_T0( + const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength ); + +extern void ISO7816_Escape( void ); + +extern void ISO7816_RestartClock( void); + +extern void ISO7816_StopClock( void ); + +extern void ISO7816_toAPDU( void ); + +extern void ISO7816_Datablock_ATR( + uint8_t* pAtr, + uint8_t* pLength ); + +extern void ISO7816_SetDataRateandClockFrequency( + uint32_t dwClockFrequency, + uint32_t dwDataRate ); + +extern uint8_t ISO7816_StatusReset( void ); + +extern void ISO7816_cold_reset( void ); + +extern void ISO7816_warm_reset( void ); + +extern void ISO7816_Decode_ATR( uint8_t* pAtr ); + +#endif /* ISO7816_4_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mcan.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mcan.h new file mode 100644 index 000000000..8981fb745 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mcan.h @@ -0,0 +1,344 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _MCAN_ +#define _MCAN_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *------------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +typedef enum +{ + CAN_STD_ID = 0, + CAN_EXT_ID = 1 +} MCan_IdType; + +typedef enum +{ + CAN_DLC_0 = 0, + CAN_DLC_1 = 1, + CAN_DLC_2 = 2, + CAN_DLC_3 = 3, + CAN_DLC_4 = 4, + CAN_DLC_5 = 5, + CAN_DLC_6 = 6, + CAN_DLC_7 = 7, + CAN_DLC_8 = 8, + CAN_DLC_12 = 9, + CAN_DLC_16 = 10, + CAN_DLC_20 = 11, + CAN_DLC_24 = 12, + CAN_DLC_32 = 13, + CAN_DLC_48 = 14, + CAN_DLC_64 = 15 +} MCan_DlcType; + +typedef enum +{ + CAN_FIFO_0 = 0, + CAN_FIFO_1 = 1 +} MCan_FifoType; + +typedef enum +{ + CAN_INTR_LINE_0 = 0, + CAN_INTR_LINE_1 = 1 +} MCan_IntrLineType; + +typedef struct MailboxInfoTag +{ + uint32_t id; + uint32_t length; + uint32_t timestamp; +} MailboxInfoType; + + +typedef struct MailBox8Tag +{ + MailboxInfoType info; + uint8_t data[8]; +} Mailbox8Type; + +typedef struct MailBox12Tag +{ + MailboxInfoType info; + uint8_t data[12]; +} Mailbox12Type; + +typedef struct MailBox16Tag +{ + MailboxInfoType info; + uint8_t data[16]; +} Mailbox16Type; + +typedef struct MailBox20Tag +{ + MailboxInfoType info; + uint8_t data[20]; +} Mailbox20Type; + +typedef struct MailBox24Tag +{ + MailboxInfoType info; + uint8_t data[24]; +} Mailbox24Type; + +typedef struct MailBox32Tag +{ + MailboxInfoType info; + uint8_t data[32]; +} Mailbox32ype; + +typedef struct MailBox48Tag +{ + MailboxInfoType info; + uint8_t data[48]; +} Mailbox48Type; + +typedef struct MailBox64Tag +{ + MailboxInfoType info; + uint8_t data[64]; +} Mailbox64Type; + + + +typedef struct MCan_MsgRamPntrsTag +{ + uint32_t * pStdFilts; + uint32_t * pExtFilts; + uint32_t * pRxFifo0; + uint32_t * pRxFifo1; + uint32_t * pRxDedBuf; + uint32_t * pTxEvtFifo; + uint32_t * pTxDedBuf; + uint32_t * pTxFifoQ; +} MCan_MsgRamPntrs; + +typedef struct MCan_ConfigTag +{ + Mcan * pMCan; + uint32_t bitTiming; + uint32_t fastBitTiming; + uint32_t nmbrStdFilts; + uint32_t nmbrExtFilts; + uint32_t nmbrFifo0Elmts; + uint32_t nmbrFifo1Elmts; + uint32_t nmbrRxDedBufElmts; + uint32_t nmbrTxEvtFifoElmts; + uint32_t nmbrTxDedBufElmts; + uint32_t nmbrTxFifoQElmts; + uint32_t rxFifo0ElmtSize; + uint32_t rxFifo1ElmtSize; + uint32_t rxBufElmtSize; + // Element sizes and data sizes (encoded element size) + uint32_t txBufElmtSize; + // Element size and data size (encoded element size) + MCan_MsgRamPntrs msgRam; +} MCan_ConfigType; + +extern const MCan_ConfigType mcan0Config; +extern const MCan_ConfigType mcan1Config; + +__STATIC_INLINE uint32_t MCAN_IsTxComplete( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + return ( mcan->MCAN_IR & MCAN_IR_TC ); +} + +__STATIC_INLINE void MCAN_ClearTxComplete( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_TC; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxDedBuffer( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + + return ( mcan->MCAN_IR & MCAN_IR_DRX ); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxBuffer( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_DRX; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo0( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + return ( mcan->MCAN_IR & MCAN_IR_RF0N ); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo0( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF0N; +} + +__STATIC_INLINE uint32_t MCAN_IsMessageStoredToRxFifo1( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + return ( mcan->MCAN_IR & MCAN_IR_RF1N ); +} + +__STATIC_INLINE void MCAN_ClearMessageStoredToRxFifo1( + const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_IR = MCAN_IR_RF1N; +} + +void MCAN_Init( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitFdEnable( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitFdBitRateSwitchEnable( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitTxQueue( + const MCan_ConfigType * mcanConfig ); + +void MCAN_InitLoopback( + const MCan_ConfigType * mcanConfig ); + +void MCAN_Enable( + const MCan_ConfigType * mcanConfig ); + +void MCAN_RequestIso11898_1( + const MCan_ConfigType * mcanConfig ); + +void MCAN_RequestFd( + const MCan_ConfigType * mcanConfig ); + +void MCAN_RequestFdBitRateSwitch( + const MCan_ConfigType * mcanConfig ); + +void MCAN_LoopbackOn( + const MCan_ConfigType * mcanConfig ); + +void MCAN_LoopbackOff( + const MCan_ConfigType * mcanConfig ); + +void MCAN_IEnableMessageStoredToRxDedBuffer( + const MCan_ConfigType * mcanConfig, + MCan_IntrLineType line ); + +uint8_t * MCAN_ConfigTxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer, + uint32_t id, + MCan_IdType idType, + MCan_DlcType dlc ); + +void MCAN_SendTxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer ); + +uint32_t MCAN_AddToTxFifoQ( + const MCan_ConfigType * mcanConfig, + uint32_t id, MCan_IdType idType, + MCan_DlcType dlc, uint8_t * data ); + +uint8_t MCAN_IsBufferTxd( + const MCan_ConfigType * mcanConfig, + uint8_t buffer ); + +void MCAN_ConfigRxBufferFilter( + const MCan_ConfigType * mcanConfig, + uint32_t buffer, + uint32_t filter, + uint32_t id, + MCan_IdType idType); + +void MCAN_ConfigRxClassicFilter( + const MCan_ConfigType * mcanConfig, + MCan_FifoType fifo, + uint8_t filter, + uint32_t id, + MCan_IdType idType, + uint32_t mask ); + +uint8_t MCAN_IsNewDataInRxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer ); + +void MCAN_GetRxDedBuffer( + const MCan_ConfigType * mcanConfig, + uint8_t buffer, + Mailbox64Type * pRxMailbox ); + +uint32_t MCAN_GetRxFifoBuffer( + const MCan_ConfigType * mcanConfig, + MCan_FifoType fifo, + Mailbox64Type * pRxMailbox ); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _MCAN_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mcid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mcid.h new file mode 100644 index 000000000..7c7d76884 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mcid.h @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** \file */ + +/** + * \ingroup sdmmc_hal + * \addtogroup mcid_module MCI Driver (HAL for SD/MMC Lib) + * + * \section Purpose + * + * This driver implements SD(IO)/MMC command operations and MCI configuration + * routines to perform SD(IO)/MMC access. It's used for upper layer + * (\ref libsdmmc_module "SD/MMC driver") to perform SD/MMC operations. + * + * \section Usage + * + * -# MCID_Init(): Initializes a MCI driver instance and the underlying + * peripheral. + * -# MCID_SendCmd(): Starts a MCI transfer which described by + * \ref sSdmmcCommand. + * -# MCID_CancelCmd(): Cancel a pending command. + * -# MCID_IsCmdCompleted(): Check if MCI transfer is finished. + * -# MCID_Handler(): Interrupt handler which is called by ISR handler. + * -# MCID_IOCtrl(): IO control function to report HW attributes to upper + * layer driver and modify HW settings (such as clock + * frequency, High-speed support, etc. See + * \ref sdmmc_ioctrls). + * + * \sa \ref dmad_module "DMA Driver", \ref hsmci_module "HSMCI", + * \ref libsdmmc_module "SD/MMC Library" + * + * Related files:\n + * \ref mcid.h\n + * \ref mcid_dma.c.\n + */ + +#ifndef MCID_H +#define MCID_H +/** \addtogroup mcid_module + *@{ + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/** \addtogroup mcid_defines MCI Driver Defines + * @{*/ + +/*---------------------------------------------------------------------------- + * Constants + *----------------------------------------------------------------------------*/ + +/** MCI States */ +#define MCID_IDLE 0 /**< Idle */ +#define MCID_LOCKED 1 /**< Locked for specific slot */ +#define MCID_CMD 2 /**< Processing the command */ +#define MCID_ERROR 3 /**< Command error */ + +/** MCI Initialize clock 400K Hz */ +#define MCI_INITIAL_SPEED 400000 + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_structs MCI Driver Data Structs + * @{ + */ +#ifdef __cplusplus + extern "C" { +#endif + +/** + * \brief MCI Driver + */ +typedef struct _Mcid +{ + /** Pointer to a MCI peripheral. */ + Hsmci *pMciHw; + /** Pointer to a DMA driver */ + sXdmad *pXdmad; + /** Pointer to currently executing command. */ + void *pCmd; + /** MCK source, Hz */ + uint32_t dwMck; + /** DMA transfer channel */ + uint32_t dwDmaCh; + /** DMA transferred data index (bytes) */ + uint32_t dwXfrNdx; + /** DMA transfer size (bytes) */ + uint32_t dwXSize; + /** MCI peripheral identifier. */ + uint8_t bID; + /** Polling mode */ + uint8_t bPolling; + /** Reserved */ + uint8_t reserved; + /** state. */ + volatile uint8_t bState; +} sMcid; + +/** @}*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup mcid_functions MCI Driver Functions + @{*/ +extern void MCID_Init(sMcid * pMcid, + Hsmci * pMci, uint8_t bID, uint32_t dwMck, + sXdmad * pXdmad, + uint8_t bPolling); + +extern void MCID_Reset(sMcid * pMcid); + +extern void MCID_SetSlot(Hsmci *pMci, uint8_t slot); + +extern uint32_t MCID_Lock(sMcid * pMcid, uint8_t bSlot); + +extern uint32_t MCID_Release(sMcid * pMcid); + +extern void MCID_Handler(sMcid * pMcid); + +extern uint32_t MCID_SendCmd(sMcid * pMcid, void * pCmd); + +extern uint32_t MCID_CancelCmd(sMcid * pMcid); + +extern uint32_t MCID_IsCmdCompleted(sMcid * pMcid); + +extern uint32_t MCID_IOCtrl(sMcid * pMcid,uint32_t bCtl,uint32_t param); + +#ifdef __cplusplus +} +#endif +/** @}*/ +/**@}*/ +#endif //#ifndef HSMCID_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mediaLB.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mediaLB.h new file mode 100644 index 000000000..bcf68b7c0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mediaLB.h @@ -0,0 +1,45 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MEDILB_H_ +#define _MEDILB_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + + +#endif /* #ifndef _MEDILB_H_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mpu.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mpu.h new file mode 100644 index 000000000..4e8af3f5a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/mpu.h @@ -0,0 +1,160 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _MPU_H_ +#define _MPU_H_ + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +#define ARM_MODE_USR 0x10 + +#define PRIVILEGE_MODE 0 +#define USER_MODE 1 + +#define MPU_DEFAULT_ITCM_REGION ( 1 ) +#define MPU_DEFAULT_IFLASH_REGION ( 2 ) +#define MPU_DEFAULT_DTCM_REGION ( 3 ) +#define MPU_DEFAULT_SRAM_REGION_1 ( 4 ) +#define MPU_DEFAULT_SRAM_REGION_2 ( 5 ) +#define MPU_PERIPHERALS_REGION ( 6 ) +#define MPU_EXT_EBI_REGION ( 7 ) +#define MPU_DEFAULT_SDRAM_REGION ( 8 ) +#define MPU_QSPIMEM_REGION ( 9 ) +#define MPU_USBHSRAM_REGION ( 10 ) + + +#define MPU_REGION_VALID ( 0x10 ) +#define MPU_REGION_ENABLE ( 0x01 ) +#define MPU_REGION_DISABLE ( 0x0 ) + +#define MPU_ENABLE ( 0x1 << MPU_CTRL_ENABLE_Pos) +#define MPU_HFNMIENA ( 0x1 << MPU_CTRL_HFNMIENA_Pos ) +#define MPU_PRIVDEFENA ( 0x1 << MPU_CTRL_PRIVDEFENA_Pos ) + + +#define MPU_REGION_BUFFERABLE ( 0x01 << MPU_RASR_B_Pos ) +#define MPU_REGION_CACHEABLE ( 0x01 << MPU_RASR_C_Pos ) +#define MPU_REGION_SHAREABLE ( 0x01 << MPU_RASR_S_Pos ) + +#define MPU_REGION_EXECUTE_NEVER ( 0x01 << MPU_RASR_XN_Pos ) + +#define MPU_AP_NO_ACCESS ( 0x00 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READ_WRITE ( 0x01 << MPU_RASR_AP_Pos ) +#define MPU_AP_UNPRIVILEGED_READONLY ( 0x02 << MPU_RASR_AP_Pos ) +#define MPU_AP_FULL_ACCESS ( 0x03 << MPU_RASR_AP_Pos ) +#define MPU_AP_RES ( 0x04 << MPU_RASR_AP_Pos ) +#define MPU_AP_PRIVILEGED_READONLY ( 0x05 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY ( 0x06 << MPU_RASR_AP_Pos ) +#define MPU_AP_READONLY2 ( 0x07 << MPU_RASR_AP_Pos ) + +#define MPU_TEX_B000 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B001 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B010 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B011 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B100 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B101 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B110 ( 0x01 << MPU_RASR_TEX_Pos ) +#define MPU_TEX_B111 ( 0x01 << MPU_RASR_TEX_Pos ) + +/* Default memory map + Address range Memory region Memory type Shareability Cache policy + 0x00000000- 0x1FFFFFFF Code Normal Non-shareable WT + 0x20000000- 0x3FFFFFFF SRAM Normal Non-shareable WBWA + 0x40000000- 0x5FFFFFFF Peripheral Device Non-shareable - + 0x60000000- 0x7FFFFFFF RAM Normal Non-shareable WBWA + 0x80000000- 0x9FFFFFFF RAM Normal Non-shareable WT + 0xA0000000- 0xBFFFFFFF Device Device Shareable + 0xC0000000- 0xDFFFFFFF Device Device Non Shareable + 0xE0000000- 0xFFFFFFFF System - - + */ + +/********* IFLASH memory macros *********************/ +#define ITCM_START_ADDRESS 0x00000000UL +#define ITCM_END_ADDRESS 0x003FFFFFUL +#define IFLASH_START_ADDRESS 0x00400000UL +#define IFLASH_END_ADDRESS 0x005FFFFFUL + + +#define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) +#define IFLASH_PRIVILEGE_END_ADDRESS (IFLASH_START_ADDRESS + 0xFFF) + +#define IFLASH_UNPRIVILEGE_START_ADDRESS (IFLASH_PRIVILEGE_END_ADDRESS + 1) +#define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) + +/**************** DTCM *******************************/ +#define DTCM_START_ADDRESS 0x20000000UL +#define DTCM_END_ADDRESS 0x203FFFFFUL + + +/******* SRAM memory macros ***************************/ + +#define SRAM_START_ADDRESS 0x20400000UL +#define SRAM_END_ADDRESS 0x2045FFFFUL + +/* Regions should be a 2^(N+1) where 4 < N < 31 */ +#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) +#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB + +#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) +#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB + +/************** Peripherals memory region macros ********/ +#define PERIPHERALS_START_ADDRESS 0x40000000UL +#define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL + +/******* Ext EBI memory macros ***************************/ +#define EXT_EBI_START_ADDRESS 0x60000000UL +#define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL + +/******* Ext-SRAM memory macros ***************************/ +#define SDRAM_START_ADDRESS 0x70000000UL +#define SDRAM_END_ADDRESS 0x7FFFFFFFUL + +/******* QSPI macros ***************************/ +#define QSPI_START_ADDRESS 0x80000000UL +#define QSPI_END_ADDRESS 0x9FFFFFFFUL + +/************** USBHS_RAM region macros ******************/ +#define USBHSRAM_START_ADDRESS 0xA0100000UL +#define USBHSRAM_END_ADDRESS 0xA01FFFFFUL + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +void MPU_Enable( uint32_t dwMPUEnable ); +void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr ); +void MPU_SetRegionNum( uint32_t dwRegionNum ); +void MPU_DisableRegion( void ); +uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes ); +void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, + uint32_t dwRegionAttr); + +#endif /* #ifndef _MMU_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio.h new file mode 100644 index 000000000..4d185eb00 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio.h @@ -0,0 +1,218 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * This file provides a basic API for PIO configuration and usage of + * user-controlled pins. Please refer to the board.h file for a list of + * available pin definitions. + * + * \section Usage + * + * -# Define a constant pin description array such as the following one, using + * the existing definitions provided by the board.h file if possible: + * \code + * const Pin pPins[] = {PIN_USART0_TXD, PIN_USART0_RXD}; + * \endcode + * Alternatively, it is possible to add new pins by provided the full Pin + * structure: + * \code + * // Pin instance to configure PA10 & PA11 as inputs with the internal + * // pull-up enabled. + * const Pin pPins = { + * (1 << 10) | (1 << 11), + * REG_PIOA, + * ID_PIOA, + * PIO_INPUT, + * PIO_PULLUP + * }; + * \endcode + * -# Configure a pin array by calling PIO_Configure() with a pointer to the + * array and its size (which is computed using the PIO_LISTSIZE macro). + * -# Change and get the value of a user-controlled pin using the PIO_Set, + * PIO_Clear and PIO_Get methods. + * -# Get the level being currently output by a user-controlled pin configured + * as an output using PIO_GetOutputDataStatus(). + */ + +#ifndef _PIO_ +#define _PIO_ + +/* + * Headers + */ + +#include "chip.h" + +#include + +/* + * Global Definitions + */ + +/** The pin is controlled by the associated signal of peripheral A. */ +#define PIO_PERIPH_A 0 +/** The pin is controlled by the associated signal of peripheral B. */ +#define PIO_PERIPH_B 1 +/** The pin is controlled by the associated signal of peripheral C. */ +#define PIO_PERIPH_C 2 +/** The pin is controlled by the associated signal of peripheral D. */ +#define PIO_PERIPH_D 3 +/** The pin is an input. */ +#define PIO_INPUT 4 +/** The pin is an output and has a default level of 0. */ +#define PIO_OUTPUT_0 5 +/** The pin is an output and has a default level of 1. */ +#define PIO_OUTPUT_1 6 + +/** Default pin configuration (no attribute). */ +#define PIO_DEFAULT (0 << 0) +/** The internal pin pull-up is active. */ +#define PIO_PULLUP (1 << 0) +/** The internal glitch filter is active. */ +#define PIO_DEGLITCH (1 << 1) +/** The pin is open-drain. */ +#define PIO_OPENDRAIN (1 << 2) + +/** The internal debouncing filter is active. */ +#define PIO_DEBOUNCE (1 << 3) + +/** Enable additional interrupt modes. */ +#define PIO_IT_AIME (1 << 4) + +/** Interrupt High Level/Rising Edge detection is active. */ +#define PIO_IT_RE_OR_HL (1 << 5) +/** Interrupt Edge detection is active. */ +#define PIO_IT_EDGE (1 << 6) + +/** Low level interrupt is active */ +#define PIO_IT_LOW_LEVEL (0 | 0 | PIO_IT_AIME) +/** High level interrupt is active */ +#define PIO_IT_HIGH_LEVEL (PIO_IT_RE_OR_HL | 0 | PIO_IT_AIME) +/** Falling edge interrupt is active */ +#define PIO_IT_FALL_EDGE (0 | PIO_IT_EDGE | PIO_IT_AIME) +/** Rising edge interrupt is active */ +#define PIO_IT_RISE_EDGE (PIO_IT_RE_OR_HL | PIO_IT_EDGE | PIO_IT_AIME) +/** The WP is enable */ +#define PIO_WPMR_WPEN_EN ( 0x01 << 0 ) +/** The WP is disable */ +#define PIO_WPMR_WPEN_DIS ( 0x00 << 0 ) +/** Valid WP key */ +#define PIO_WPMR_WPKEY_VALID ( 0x50494F << 8 ) +#ifdef __cplusplus + extern "C" { +#endif + +/* + * Global Macros + */ + +/** + * Calculates the size of an array of Pin instances. The array must be defined + * locally (i.e. not a pointer), otherwise the computation will not be correct. + * \param pPins Local array of Pin instances. + * \return Number of elements in array. + */ +#define PIO_LISTSIZE(pPins) (sizeof(pPins) / sizeof(Pin)) + +/* + * Global Types + */ + + +/* + * Describes the type and attribute of one PIO pin or a group of similar pins. + * The #type# field can have the following values: + * - PIO_PERIPH_A + * - PIO_PERIPH_B + * - PIO_OUTPUT_0 + * - PIO_OUTPUT_1 + * - PIO_INPUT + * + * The #attribute# field is a bitmask that can either be set to PIO_DEFAULt, + * or combine (using bitwise OR '|') any number of the following constants: + * - PIO_PULLUP + * - PIO_DEGLITCH + * - PIO_DEBOUNCE + * - PIO_OPENDRAIN + * - PIO_IT_LOW_LEVEL + * - PIO_IT_HIGH_LEVEL + * - PIO_IT_FALL_EDGE + * - PIO_IT_RISE_EDGE + */ +typedef struct _Pin +{ + /* Bitmask indicating which pin(s) to configure. */ + uint32_t mask; + /* Pointer to the PIO controller which has the pin(s). */ + Pio *pio; + /* Peripheral ID of the PIO controller which has the pin(s). */ + uint8_t id; + /* Pin type. */ + uint8_t type; + /* Pin attribute. */ + uint8_t attribute; +} Pin ; + +/* + * Global Access Macros + */ + +/* + * Global Functions + */ + +extern uint8_t PIO_Configure( const Pin *list, uint32_t size ) ; + +extern void PIO_Set( const Pin *pin ) ; + +extern void PIO_Clear( const Pin *pin ) ; + +extern uint8_t PIO_Get( const Pin *pin ) ; + +extern uint8_t PIO_GetOutputDataStatus( const Pin *pin ) ; + +extern void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff ); + +extern void PIO_EnableWriteProtect( const Pin *pin ); + +extern void PIO_DisableWriteProtect( const Pin *pin ); + +extern void PIO_SetPinType( Pin * pin, uint8_t pinType); + +extern uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin ); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio_capture.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio_capture.h new file mode 100644 index 000000000..fe90617ae --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio_capture.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef PIO_CAPTURE_H +#define PIO_CAPTURE_H + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** \brief PIO Parallel Capture structure for initialize. + * + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpioCaptureInit { + + /** PIO_PCRHR register is a BYTE, HALF-WORD or WORD */ + uint8_t dsize; + /** PDC size, data to be received */ + uint16_t dPDCsize; + /** Data to be received */ + uint32_t *pData; + /** Parallel Capture Mode Always Sampling */ + uint8_t alwaysSampling; + /** Parallel Capture Mode Half Sampling */ + uint8_t halfSampling; + /** Parallel Capture Mode First Sample */ + uint8_t modeFirstSample; + /** Callback function invoked at Mode Data Ready */ + void (*CbkDataReady)( struct _SpioCaptureInit* ); + /** Callback function invoked at Mode Overrun Error */ + void (*CbkOverrun)( struct _SpioCaptureInit* ); + /** Callback function invoked at End of Reception Transfer */ + void (*CbkEndReception)( struct _SpioCaptureInit* ); + /** Callback function invoked at Reception Buffer Full */ + void (*CbkBuffFull)( struct _SpioCaptureInit* ); + /** Callback arguments.*/ + void *pParam; + +} SpioCaptureInit ; + + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ +extern void PIO_CaptureDisableIt( uint32_t itToDisable ) ; +extern void PIO_CaptureEnableIt( uint32_t itToEnable ) ; +extern void PIO_CaptureEnable( void ) ; +extern void PIO_CaptureDisable( void ) ; +extern void PIO_CaptureInit( SpioCaptureInit* pInit ) ; + +#endif /* #ifndef PIO_CAPTURE_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio_it.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio_it.h new file mode 100644 index 000000000..83ef4dc9a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pio_it.h @@ -0,0 +1,97 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Configuration and handling of interrupts on PIO status changes. The API + * provided here have several advantages over the traditional PIO interrupt + * configuration approach: + * - It is highly portable + * - It automatically demultiplexes interrupts when multiples pins have been + * configured on a single PIO controller + * - It allows a group of pins to share the same interrupt + * + * However, it also has several minor drawbacks that may prevent from using it + * in particular applications: + * - It enables the clocks of all PIO controllers + * - PIO controllers all share the same interrupt handler, which does the + * demultiplexing and can be slower than direct configuration + * - It reserves space for a fixed number of interrupts, which can be + * increased by modifying the appropriate constant in pio_it.c. + * + * \par Usage + * + * -# Initialize the PIO interrupt mechanism using PIO_InitializeInterrupts() + * with the desired priority (0 ... 7). + * -# Configure a status change interrupt on one or more pin(s) with + * PIO_ConfigureIt(). + * -# Enable & disable interrupts on pins using PIO_EnableIt() and + * PIO_DisableIt(). + */ + +#ifndef _PIO_IT_ +#define _PIO_IT_ + +/* + * Headers + */ + +#include "pio.h" + +#ifdef __cplusplus + extern "C" { +#endif + +/* + * Global functions + */ + +extern void PIO_InitializeInterrupts( uint32_t dwPriority ) ; + +extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) ; + +extern void PIO_EnableIt( const Pin *pPin ) ; + +extern void PIO_DisableIt( const Pin *pPin ) ; + +extern void PIO_IT_InterruptHandler( void ) ; + +extern void PioInterruptHandler( uint32_t id, Pio *pPio ) ; + +extern void PIO_CaptureHandler( void ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PIO_IT_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pmc.h new file mode 100644 index 000000000..709db5a3d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pmc.h @@ -0,0 +1,101 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _PMC_ +#define _PMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* Definition for fast RC frequency */ +#define FAST_RC_4MHZ CKGR_MOR_MOSCRCF_4MHz +#define FAST_RC_8MHZ CKGR_MOR_MOSCRCF_8MHz +#define FAST_RC_12MHZ CKGR_MOR_MOSCRCF_12MHz + +/* Definitions for startup count. + * Note: 1 count unit stand for: 1 / 32768 * 8 = 244 us + */ +/* Default startup count for 4/8/12MHz fast RC (startup time: 10us ) */ +#define DEFAUTL_FAST_RC_COUNT 1 +/* Default startup count for 3-20MHz main oscillator (startup time: 1.4ms ) */ +#define DEFAUTL_MAIN_OSC_COUNT 8 +/* Default startup count for PLLA (startup time: 200us ) */ +#define DEFAUTL_PLLA_COUNT 1 +/* Default startup count for UPLL */ +#define DEFAUTL_UPLL_COUNT 3 +/* No change for default startup count */ +#define DEFAUTL_COUNT_NO_CHANGE 0xFFFF + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void PMC_EnablePeripheral( uint32_t dwId ) ; +extern void PMC_DisablePeripheral( uint32_t dwId ) ; + +extern void PMC_EnableAllPeripherals( void ) ; +extern void PMC_DisableAllPeripherals( void ) ; + +extern uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) ; + +extern void PMC_SelectExtOsc(void); +extern void PMC_EnableExtOsc(void); +extern void PMC_DisableExtOsc(void); +extern void PMC_SelectExtBypassOsc(void); +extern void PMC_EnableIntRC4_8_12MHz(uint32_t fastRcFreq); +extern void PMC_DisableIntRC4_8_12MHz(void); +extern void PMC_SetPllaClock(uint32_t mul, uint32_t div); +extern void PMC_SetPllbClock(uint32_t mul, uint32_t div); +extern void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler); +extern void PMC_DisableAllClocks(void); +extern void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_ConfigureMckWithPllb(uint32_t mul, uint32_t div, + uint32_t prescaler); +extern void PMC_EnableXT32KFME(void); +extern void PMC_ConfigurePCK0(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK1(uint32_t MasterClk, uint32_t prescaler); +extern void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pwmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pwmc.h new file mode 100644 index 000000000..94cbc335e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/pwmc.h @@ -0,0 +1,135 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Interface for configuration the Pulse Width Modulation Controller (PWM) + * peripheral. + * + * \par Usage + * + * -# Configures PWM clocks A & B to run at the given frequencies using + * \ref PWMC_ConfigureClocks(). + * -# Configure PWMC channel using \ref PWMC_ConfigureChannel(), + * \ref PWMC_ConfigureChannelExt() + * \ref PWMC_SetPeriod(), \ref PWMC_SetDutyCycle() and + * \ref PWMC_SetDeadTime(). + * -# Enable & disable channel using \ref PWMC_EnableChannel() and + * \ref PWMC_DisableChannel(). + * -# Enable & disable the period interrupt for the given PWM channel using + * \ref PWMC_EnableChannelIt() and \ref PWMC_DisableChannelIt(). + * -# Enable & disable the selected interrupts sources on a PWMC peripheral + * using \ref PWMC_EnableIt() and \ref PWMC_DisableIt(). + * -# Control synchronous channel using \ref PWMC_ConfigureSyncChannel(), + * \ref PWMC_SetSyncChannelUpdatePeriod() and + * \ref PWMC_SetSyncChannelUpdateUnlock(). + * -# Control PWM override output using \ref PWMC_SetOverrideValue(), + * \ref PWMC_EnableOverrideOutput() and \ref PWMC_DisableOverrideOutput(). + * -# Send data through the transmitter using \ref PWMC_WriteBuffer(). + * + */ + +#ifndef _PWMC_ +#define _PWMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void PWMC_ConfigureChannel( + Pwm* pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity); +extern void PWMC_ConfigureChannelExt( + Pwm* pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity, + uint32_t countEventSelect, + uint32_t DTEnable, + uint32_t DTHInverte, + uint32_t DTLInverte); +extern void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t clka, uint32_t clkb, + uint32_t mck); +extern void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period); +extern void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty); +extern void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, + uint16_t timeL); +extern void PWMC_ConfigureSyncChannel( Pwm* pPwm, + uint32_t channels, + uint32_t updateMode, + uint32_t requestMode, + uint32_t requestComparisonSelect); +extern void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period); +extern void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm ); +extern void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel); +extern void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel); +extern void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel); +extern void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel); +extern void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2); +extern void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2); +extern uint8_t PWMC_WriteBuffer(Pwm *pwmc, + void *buffer, + uint32_t length); +extern void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value); +extern void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync); +extern void PWMC_OutputOverrideSelection( Pwm* pPwm, uint32_t value ); +extern void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync); +extern void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode); +extern void PWMC_FaultClear( Pwm* pPwm, uint32_t fault); +extern void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value); +extern void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value); +extern void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, + uint32_t value, uint32_t mode); +extern void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode); +extern uint32_t PWMC_GetStatus2( Pwm* pPwm); +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PWMC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/qspi.h new file mode 100644 index 000000000..4ad79e1bd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/qspi.h @@ -0,0 +1,236 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _QSPI_ +#define _QSPI_ +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section qspi_configuration_macros SPI Configuration Macros + * - \ref QSPI_PCS + * - \ref QSPI_SCBR + * - \ref QSPI_DLYBS + * - \ref QSPI_DLYBCT + */ + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define QSPI_SCBR(baudrate, masterClock) \ + ((uint32_t) (masterClock / baudrate) << 8) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define QSPI_DLYBS(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 1000) << 16) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define QSPI_DLYBCT(delay, masterClock) \ + ((uint32_t) (((masterClock / 1000000) * delay) / 32000) << 24) + +/*--------------------------------------------------------------------------- */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** \brief qspi access modes + */ +typedef enum{ + CmdAccess = 0, + ReadAccess, + WriteAccess +}Access_t; + +/** \brief qspi modes SPI or QSPI + */ +typedef enum{ + SpiMode = QSPI_MR_SMM_SPI, + QspiMemMode = QSPI_MR_SMM_MEMORY +}QspiMode_t; + + +/** \brief qspi clock modes , regarding clock phase and clock polarity + */ +typedef enum{ + ClockMode_00 = 0, + ClockMode_10, + ClockMode_01, + ClockMode_11 +}QspiClockMode_t; + + +/** \brief qspi status codes + */ +typedef enum{ + QSPI_SUCCESS = 0, + QSPI_BUSY, + QSPI_BUSY_SENDING, + QSPI_READ_ERROR, + QSPI_WRITE_ERROR, + QSPI_UNKNOWN_ERROR, + QSPI_INIT_ERROR, + QSPI_INPUT_ERROR, + QSPI_TOTAL_ERROR +}QspidStatus_t; + + +/** \brief qspi status regiter bits + */ +typedef enum { + IsReceived = QSPI_SR_RDRF, + IsTxSent = QSPI_SR_TDRE, + IsTxEmpty = QSPI_SR_TXEMPTY, + IsOverrun = QSPI_SR_OVRES, + IsCsRise = QSPI_SR_CSR, + IsCsAsserted = QSPI_SR_CSS, + IsEofInst = QSPI_SR_INSTRE, + IsEnabled = QSPI_SR_QSPIENS +}QspiStatus_t; + +/** \brief qspi command structure + */ +typedef struct { + uint8_t Instruction; + uint8_t Option; +}QspiMemCmd_t; + +/** \brief qspi buffer structure + */ +typedef struct { + uint32_t TxDataSize; /* Tx buffer size */ + uint32_t RxDataSize; /* Rx buffer size */ + uint32_t *pDataTx; /* Tx buffer */ + uint32_t *pDataRx; /* Rx buffer */ +}QspiBuffer_t; + + +/** \brief qspi frame structure for QSPI mode + */ +typedef struct { + union _QspiInstFrame { + uint32_t val; + struct _QspiInstFrameBM { + uint32_t bwidth:3, /** Width of QSPI Addr , inst data */ + reserved0:1, /** Reserved*/ + bInstEn:1, /** Enable Inst */ + bAddrEn:1, /** Enable Address */ + bOptEn:1, /** Enable Option */ + bDataEn:1, /** Enable Data */ + bOptLen:2, /** Option Length*/ + bAddrLen:1, /** Addrs Length*/ + reserved1:1, /** Option Length*/ + bXfrType:2, /** Transfer type*/ + bContinuesRead:1, /** Continoues read mode*/ + reserved2:1, /** Reserved*/ + bDummyCycles:5, /**< Unicast hash match */ + reserved3:11; /** Reserved*/ + } bm; + } InstFrame; + uint32_t Addr; +}QspiInstFrame_t; + +/** \brief qspi driver structure + */ +typedef struct { + uint8_t qspiId; /* QSPI ID */ + Qspi *pQspiHw; /* QSPI Hw instance */ + QspiMode_t qspiMode; /* Qspi mode: SPI or QSPI */ + QspiMemCmd_t qspiCommand; /* Qspi command structure*/ + QspiBuffer_t qspiBuffer; /* Qspi buffer*/ + QspiInstFrame_t *pQspiFrame; /* Qspi QSPI mode Fram register informations*/ +}Qspid_t; + + +void QSPI_SwReset( Qspi *pQspi ); + +void QSPI_Disable( Qspi *pQspi ); + +void QSPI_Enable( Qspi *pQspi ); + +QspidStatus_t QSPI_EndTransfer( Qspi *pQspi ); + +uint32_t QSPI_GetStatus( Qspi *pQspi, const QspiStatus_t rStatus ); + +void QSPI_ConfigureClock( Qspi *pQspi, QspiClockMode_t ClockMode, + uint32_t dwClockCfg ); + +QspidStatus_t QSPI_SingleReadSPI( Qspid_t *pQspid, uint16_t* const pData ); + +QspidStatus_t QSPI_MultiReadSPI( Qspid_t *pQspid, uint16_t* + const pData, uint32_t NumOfBytes ); + +QspidStatus_t QSPI_SingleWriteSPI( Qspid_t *pQspid, uint16_t const *pData ); + +QspidStatus_t QSPI_MultiWriteSPI( Qspid_t *pQspid, uint16_t const *pData , + uint32_t NumOfBytes ); + +QspidStatus_t QSPI_EnableIt( Qspi *pQspi, uint32_t dwSources ); + +QspidStatus_t QSPI_DisableIt( Qspi *pQspi, uint32_t dwSources ); + +uint32_t QSPI_GetItMask( Qspi *pQspi ); + +uint32_t QSPI_GetEnabledItStatus( Qspi *pQspi ); + +QspidStatus_t QSPI_ConfigureInterface( Qspid_t *pQspid, QspiMode_t Mode, + uint32_t dwConfiguration ); + +QspidStatus_t QSPI_SendCommand( Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_SendCommandWithData( Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_ReadCommand( Qspid_t *pQspi, uint8_t const KeepCfg); + +QspidStatus_t QSPI_EnableMemAccess( Qspid_t *pQspi, uint8_t const KeepCfg, + uint8_t ScrambleFlag); + +QspidStatus_t QSPI_ReadWriteMem( Qspid_t *pQspid, Access_t const ReadWrite); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _QSPI_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/qspi_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/qspi_dma.h new file mode 100644 index 000000000..8197f1f8a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/qspi_dma.h @@ -0,0 +1,115 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef QSPI_DMA_H +#define QSPI_DMA_H + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +//_RB_#include "../../../../utils/utility.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define QSPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define QSPID_ERROR_LOCK 2 + +#define QSPID_CH_NOT_ENABLED 0xFF +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*QspidCallback)( uint8_t, void* ) ; + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Qspid +{ + Qspid_t Qspid; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** Polling */ + uint8_t Polling ; + /** Tx ch num */ + uint8_t TxChNum ; + /** Rx ch num */ + uint8_t RxChNum ; + /** QSPI Xfr state. */ + volatile uint8_t progress ; +} QspiDma_t ; + +#ifdef __cplusplus + extern "C" { +#endif +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t QSPID_Configure( QspiDma_t *pQspidma, QspiMode_t Mode, + uint32_t dwConfiguration, sXdmad* pXdmad); + +uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma); + +uint32_t QSPID_ReadWriteQSPI( QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite); + +uint32_t QSPID_IsBusy( volatile uint8_t *QspiSemaphore) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rstc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rstc.h new file mode 100644 index 000000000..b8b2ceea4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rstc.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _RSTC_H +#define _RSTC_H + +/*--------------------------------------------------------------------------- + * Includes + *---------------------------------------------------------------------------*/ + +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +void RSTC_ConfigureMode(uint32_t rmr); + +void RSTC_SetUserResetEnable(uint8_t enable); + +void RSTC_SetUserResetInterruptEnable(uint8_t enable); + +void RSTC_SetExtResetLength(uint8_t powl); + +void RSTC_ProcessorReset(void); + +void RSTC_ExtReset(void); + +uint8_t RSTC_GetNrstLevel(void); + +uint8_t RSTC_IsUserResetDetected(void); + +uint8_t RSTC_IsBusy(void); + +uint32_t RSTC_GetStatus(void); + +#endif /* #ifndef _RSTC_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rtc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rtc.h new file mode 100644 index 000000000..cc528b2d8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rtc.h @@ -0,0 +1,102 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Real Time Clock (RTC) controller. + * + */ + +#ifndef _RTC_ +#define _RTC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define RTC_HOUR_BIT_LEN_MASK 0x3F +#define RTC_MIN_BIT_LEN_MASK 0x7F +#define RTC_SEC_BIT_LEN_MASK 0x7F +#define RTC_CENT_BIT_LEN_MASK 0x7F +#define RTC_YEAR_BIT_LEN_MASK 0xFF +#define RTC_MONTH_BIT_LEN_MASK 0x1F +#define RTC_DATE_BIT_LEN_MASK 0x3F +#define RTC_WEEK_BIT_LEN_MASK 0x07 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) ; + +extern uint32_t RTC_GetHourMode( Rtc* pRtc ) ; + +extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) ; + +extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) ; + +extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, + uint8_t ucSecond ) ; + +extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond ) ; + +extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, uint8_t *pucMinute, + uint8_t *pucSecond ) ; + +extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, + uint8_t *pucDay, uint8_t *pucWeek ) ; + +extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, + uint8_t ucDay, uint8_t ucWeek ) ; + +extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) ; + +extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) ; + +extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _RTC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rtt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rtt.h new file mode 100644 index 000000000..5a3e44c43 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/rtt.h @@ -0,0 +1,82 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Interface for Real Time Timer (RTT) controller. + * + * \par Usage + * + * -# Changes the prescaler value of the given RTT and restarts it + * using \ref RTT_SetPrescaler(). + * -# Get current value of the RTT using \ref RTT_GetTime(). + * -# Enables the specified RTT interrupt using \ref RTT_EnableIT(). + * -# Get the status register value of the given RTT using \ref RTT_GetStatus(). + * -# Configures the RTT to generate an alarm at the given time + * using \ref RTT_SetAlarm(). + */ + +#ifndef _RTT_ +#define _RTT_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void RTT_SetPrescaler( Rtt* pRtt, uint16_t wPrescaler ) ; + +extern uint32_t RTT_GetTime( Rtt* pRtt ) ; + +extern void RTT_EnableIT( Rtt* pRtt, uint32_t dwSources ) ; + +extern uint32_t RTT_GetStatus( Rtt *pRtt ) ; + +extern void RTT_SetAlarm( Rtt *pRtt, uint32_t dwTime ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef RTT_H */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_acc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_acc.h new file mode 100644 index 000000000..ccdf8e297 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_acc.h @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ACC_COMPONENT_ +#define _SAMV71_ACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Comparator Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ACC Analog Comparator Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Acc hardware registers */ +typedef struct { + __O uint32_t ACC_CR; /**< \brief (Acc Offset: 0x00) Control Register */ + __IO uint32_t ACC_MR; /**< \brief (Acc Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[7]; + __O uint32_t ACC_IER; /**< \brief (Acc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t ACC_IDR; /**< \brief (Acc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t ACC_IMR; /**< \brief (Acc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t ACC_ISR; /**< \brief (Acc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t ACC_ACR; /**< \brief (Acc Offset: 0x94) Analog Control Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t ACC_WPMR; /**< \brief (Acc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ACC_WPSR; /**< \brief (Acc Offset: 0xE8) Write Protection Status Register */ +} Acc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ACC_CR : (ACC Offset: 0x00) Control Register -------- */ +#define ACC_CR_SWRST (0x1u << 0) /**< \brief (ACC_CR) Software Reset */ +/* -------- ACC_MR : (ACC Offset: 0x04) Mode Register -------- */ +#define ACC_MR_SELMINUS_Pos 0 +#define ACC_MR_SELMINUS_Msk (0x7u << ACC_MR_SELMINUS_Pos) /**< \brief (ACC_MR) Selection for Minus Comparator Input */ +#define ACC_MR_SELMINUS(value) ((ACC_MR_SELMINUS_Msk & ((value) << ACC_MR_SELMINUS_Pos))) +#define ACC_MR_SELMINUS_TS (0x0u << 0) /**< \brief (ACC_MR) Select TS */ +#define ACC_MR_SELMINUS_ADVREFP (0x1u << 0) /**< \brief (ACC_MR) Select ADVREFP */ +#define ACC_MR_SELMINUS_DAC0 (0x2u << 0) /**< \brief (ACC_MR) Select DAC0 */ +#define ACC_MR_SELMINUS_DAC1 (0x3u << 0) /**< \brief (ACC_MR) Select DAC1 */ +#define ACC_MR_SELMINUS_AFE0_AD0 (0x4u << 0) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELMINUS_AFE0_AD1 (0x5u << 0) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELMINUS_AFE0_AD2 (0x6u << 0) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELMINUS_AFE0_AD3 (0x7u << 0) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_Pos 4 +#define ACC_MR_SELPLUS_Msk (0x7u << ACC_MR_SELPLUS_Pos) /**< \brief (ACC_MR) Selection For Plus Comparator Input */ +#define ACC_MR_SELPLUS(value) ((ACC_MR_SELPLUS_Msk & ((value) << ACC_MR_SELPLUS_Pos))) +#define ACC_MR_SELPLUS_AFE0_AD0 (0x0u << 4) /**< \brief (ACC_MR) Select AFE0_AD0 */ +#define ACC_MR_SELPLUS_AFE0_AD1 (0x1u << 4) /**< \brief (ACC_MR) Select AFE0_AD1 */ +#define ACC_MR_SELPLUS_AFE0_AD2 (0x2u << 4) /**< \brief (ACC_MR) Select AFE0_AD2 */ +#define ACC_MR_SELPLUS_AFE0_AD3 (0x3u << 4) /**< \brief (ACC_MR) Select AFE0_AD3 */ +#define ACC_MR_SELPLUS_AFE0_AD4 (0x4u << 4) /**< \brief (ACC_MR) Select AFE0_AD4 */ +#define ACC_MR_SELPLUS_AFE0_AD5 (0x5u << 4) /**< \brief (ACC_MR) Select AFE0_AD5 */ +#define ACC_MR_SELPLUS_AFE1_AD0 (0x6u << 4) /**< \brief (ACC_MR) Select AFE1_AD0 */ +#define ACC_MR_SELPLUS_AFE1_AD1 (0x7u << 4) /**< \brief (ACC_MR) Select AFE1_AD1 */ +#define ACC_MR_ACEN (0x1u << 8) /**< \brief (ACC_MR) Analog Comparator Enable */ +#define ACC_MR_ACEN_DIS (0x0u << 8) /**< \brief (ACC_MR) Analog comparator disabled. */ +#define ACC_MR_ACEN_EN (0x1u << 8) /**< \brief (ACC_MR) Analog comparator enabled. */ +#define ACC_MR_EDGETYP_Pos 9 +#define ACC_MR_EDGETYP_Msk (0x3u << ACC_MR_EDGETYP_Pos) /**< \brief (ACC_MR) Edge Type */ +#define ACC_MR_EDGETYP(value) ((ACC_MR_EDGETYP_Msk & ((value) << ACC_MR_EDGETYP_Pos))) +#define ACC_MR_EDGETYP_RISING (0x0u << 9) /**< \brief (ACC_MR) Only rising edge of comparator output */ +#define ACC_MR_EDGETYP_FALLING (0x1u << 9) /**< \brief (ACC_MR) Falling edge of comparator output */ +#define ACC_MR_EDGETYP_ANY (0x2u << 9) /**< \brief (ACC_MR) Any edge of comparator output */ +#define ACC_MR_INV (0x1u << 12) /**< \brief (ACC_MR) Invert Comparator Output */ +#define ACC_MR_INV_DIS (0x0u << 12) /**< \brief (ACC_MR) Analog comparator output is directly processed. */ +#define ACC_MR_INV_EN (0x1u << 12) /**< \brief (ACC_MR) Analog comparator output is inverted prior to being processed. */ +#define ACC_MR_SELFS (0x1u << 13) /**< \brief (ACC_MR) Selection Of Fault Source */ +#define ACC_MR_SELFS_CE (0x0u << 13) /**< \brief (ACC_MR) The CE flag is used to drive the FAULT output. */ +#define ACC_MR_SELFS_OUTPUT (0x1u << 13) /**< \brief (ACC_MR) The output of the analog comparator flag is used to drive the FAULT output. */ +#define ACC_MR_FE (0x1u << 14) /**< \brief (ACC_MR) Fault Enable */ +#define ACC_MR_FE_DIS (0x0u << 14) /**< \brief (ACC_MR) The FAULT output is tied to 0. */ +#define ACC_MR_FE_EN (0x1u << 14) /**< \brief (ACC_MR) The FAULT output is driven by the signal defined by SELFS. */ +/* -------- ACC_IER : (ACC Offset: 0x24) Interrupt Enable Register -------- */ +#define ACC_IER_CE (0x1u << 0) /**< \brief (ACC_IER) Comparison Edge */ +/* -------- ACC_IDR : (ACC Offset: 0x28) Interrupt Disable Register -------- */ +#define ACC_IDR_CE (0x1u << 0) /**< \brief (ACC_IDR) Comparison Edge */ +/* -------- ACC_IMR : (ACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define ACC_IMR_CE (0x1u << 0) /**< \brief (ACC_IMR) Comparison Edge */ +/* -------- ACC_ISR : (ACC Offset: 0x30) Interrupt Status Register -------- */ +#define ACC_ISR_CE (0x1u << 0) /**< \brief (ACC_ISR) Comparison Edge (cleared on read) */ +#define ACC_ISR_SCO (0x1u << 1) /**< \brief (ACC_ISR) Synchronized Comparator Output */ +#define ACC_ISR_MASK (0x1u << 31) /**< \brief (ACC_ISR) Flag Mask */ +/* -------- ACC_ACR : (ACC Offset: 0x94) Analog Control Register -------- */ +#define ACC_ACR_ISEL (0x1u << 0) /**< \brief (ACC_ACR) Current Selection */ +#define ACC_ACR_ISEL_LOPW (0x0u << 0) /**< \brief (ACC_ACR) Low-power option. */ +#define ACC_ACR_ISEL_HISP (0x1u << 0) /**< \brief (ACC_ACR) High-speed option. */ +#define ACC_ACR_HYST_Pos 1 +#define ACC_ACR_HYST_Msk (0x3u << ACC_ACR_HYST_Pos) /**< \brief (ACC_ACR) Hysteresis Selection */ +#define ACC_ACR_HYST(value) ((ACC_ACR_HYST_Msk & ((value) << ACC_ACR_HYST_Pos))) +/* -------- ACC_WPMR : (ACC Offset: 0xE4) Write Protection Mode Register -------- */ +#define ACC_WPMR_WPEN (0x1u << 0) /**< \brief (ACC_WPMR) Write Protection Enable */ +#define ACC_WPMR_WPKEY_Pos 8 +#define ACC_WPMR_WPKEY_Msk (0xffffffu << ACC_WPMR_WPKEY_Pos) /**< \brief (ACC_WPMR) Write Protection Key */ +#define ACC_WPMR_WPKEY(value) ((ACC_WPMR_WPKEY_Msk & ((value) << ACC_WPMR_WPKEY_Pos))) +#define ACC_WPMR_WPKEY_PASSWD (0x414343u << 8) /**< \brief (ACC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ACC_WPSR : (ACC Offset: 0xE8) Write Protection Status Register -------- */ +#define ACC_WPSR_WPVS (0x1u << 0) /**< \brief (ACC_WPSR) Write Protection Violation Status */ + +/*@}*/ + + +#endif /* _SAMV71_ACC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_aes.h new file mode 100644 index 000000000..1a9c1ccc4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_aes.h @@ -0,0 +1,172 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AES_COMPONENT_ +#define _SAMV71_AES_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Advanced Encryption Standard */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AES Advanced Encryption Standard */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Aes hardware registers */ +typedef struct { + __O uint32_t AES_CR; /**< \brief (Aes Offset: 0x00) Control Register */ + __IO uint32_t AES_MR; /**< \brief (Aes Offset: 0x04) Mode Register */ + __I uint32_t Reserved1[2]; + __O uint32_t AES_IER; /**< \brief (Aes Offset: 0x10) Interrupt Enable Register */ + __O uint32_t AES_IDR; /**< \brief (Aes Offset: 0x14) Interrupt Disable Register */ + __I uint32_t AES_IMR; /**< \brief (Aes Offset: 0x18) Interrupt Mask Register */ + __I uint32_t AES_ISR; /**< \brief (Aes Offset: 0x1C) Interrupt Status Register */ + __O uint32_t AES_KEYWR[8]; /**< \brief (Aes Offset: 0x20) Key Word Register */ + __O uint32_t AES_IDATAR[4]; /**< \brief (Aes Offset: 0x40) Input Data Register */ + __I uint32_t AES_ODATAR[4]; /**< \brief (Aes Offset: 0x50) Output Data Register */ + __O uint32_t AES_IVR[4]; /**< \brief (Aes Offset: 0x60) Initialization Vector Register */ + __IO uint32_t AES_AADLENR; /**< \brief (Aes Offset: 0x70) Additional Authenticated Data Length Register */ + __IO uint32_t AES_CLENR; /**< \brief (Aes Offset: 0x74) Plaintext/Ciphertext Length Register */ + __IO uint32_t AES_GHASHR[4]; /**< \brief (Aes Offset: 0x78) GCM Intermediate Hash Word Register */ + __I uint32_t AES_TAGR[4]; /**< \brief (Aes Offset: 0x88) GCM Authentication Tag Word Register */ + __I uint32_t AES_CTRR; /**< \brief (Aes Offset: 0x98) GCM Encryption Counter Value Register */ + __IO uint32_t AES_GCMHR[4]; /**< \brief (Aes Offset: 0x9C) GCM H Word Register */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AES_CR : (AES Offset: 0x00) Control Register -------- */ +#define AES_CR_START (0x1u << 0) /**< \brief (AES_CR) Start Processing */ +#define AES_CR_SWRST (0x1u << 8) /**< \brief (AES_CR) Software Reset */ +/* -------- AES_MR : (AES Offset: 0x04) Mode Register -------- */ +#define AES_MR_CIPHER (0x1u << 0) /**< \brief (AES_MR) Processing Mode */ +#define AES_MR_GTAGEN (0x1u << 1) /**< \brief (AES_MR) GCM Automatic Tag Generation Enable */ +#define AES_MR_DUALBUFF (0x1u << 3) /**< \brief (AES_MR) Dual Input Buffer */ +#define AES_MR_DUALBUFF_INACTIVE (0x0u << 3) /**< \brief (AES_MR) AES_IDATARx cannot be written during processing of previous block. */ +#define AES_MR_DUALBUFF_ACTIVE (0x1u << 3) /**< \brief (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. */ +#define AES_MR_PROCDLY_Pos 4 +#define AES_MR_PROCDLY_Msk (0xfu << AES_MR_PROCDLY_Pos) /**< \brief (AES_MR) Processing Delay */ +#define AES_MR_PROCDLY(value) ((AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))) +#define AES_MR_SMOD_Pos 8 +#define AES_MR_SMOD_Msk (0x3u << AES_MR_SMOD_Pos) /**< \brief (AES_MR) Start Mode */ +#define AES_MR_SMOD(value) ((AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))) +#define AES_MR_SMOD_MANUAL_START (0x0u << 8) /**< \brief (AES_MR) Manual Mode */ +#define AES_MR_SMOD_AUTO_START (0x1u << 8) /**< \brief (AES_MR) Auto Mode */ +#define AES_MR_SMOD_IDATAR0_START (0x2u << 8) /**< \brief (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */ +#define AES_MR_KEYSIZE_Pos 10 +#define AES_MR_KEYSIZE_Msk (0x3u << AES_MR_KEYSIZE_Pos) /**< \brief (AES_MR) Key Size */ +#define AES_MR_KEYSIZE(value) ((AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))) +#define AES_MR_KEYSIZE_AES128 (0x0u << 10) /**< \brief (AES_MR) AES Key Size is 128 bits */ +#define AES_MR_KEYSIZE_AES192 (0x1u << 10) /**< \brief (AES_MR) AES Key Size is 192 bits */ +#define AES_MR_KEYSIZE_AES256 (0x2u << 10) /**< \brief (AES_MR) AES Key Size is 256 bits */ +#define AES_MR_OPMOD_Pos 12 +#define AES_MR_OPMOD_Msk (0x7u << AES_MR_OPMOD_Pos) /**< \brief (AES_MR) Operation Mode */ +#define AES_MR_OPMOD(value) ((AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))) +#define AES_MR_OPMOD_ECB (0x0u << 12) /**< \brief (AES_MR) ECB: Electronic Code Book mode */ +#define AES_MR_OPMOD_CBC (0x1u << 12) /**< \brief (AES_MR) CBC: Cipher Block Chaining mode */ +#define AES_MR_OPMOD_OFB (0x2u << 12) /**< \brief (AES_MR) OFB: Output Feedback mode */ +#define AES_MR_OPMOD_CFB (0x3u << 12) /**< \brief (AES_MR) CFB: Cipher Feedback mode */ +#define AES_MR_OPMOD_CTR (0x4u << 12) /**< \brief (AES_MR) CTR: Counter mode (16-bit internal counter) */ +#define AES_MR_OPMOD_GCM (0x5u << 12) /**< \brief (AES_MR) GCM: Galois/Counter mode */ +#define AES_MR_LOD (0x1u << 15) /**< \brief (AES_MR) Last Output Data Mode */ +#define AES_MR_CFBS_Pos 16 +#define AES_MR_CFBS_Msk (0x7u << AES_MR_CFBS_Pos) /**< \brief (AES_MR) Cipher Feedback Data Size */ +#define AES_MR_CFBS(value) ((AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))) +#define AES_MR_CFBS_SIZE_128BIT (0x0u << 16) /**< \brief (AES_MR) 128-bit */ +#define AES_MR_CFBS_SIZE_64BIT (0x1u << 16) /**< \brief (AES_MR) 64-bit */ +#define AES_MR_CFBS_SIZE_32BIT (0x2u << 16) /**< \brief (AES_MR) 32-bit */ +#define AES_MR_CFBS_SIZE_16BIT (0x3u << 16) /**< \brief (AES_MR) 16-bit */ +#define AES_MR_CFBS_SIZE_8BIT (0x4u << 16) /**< \brief (AES_MR) 8-bit */ +#define AES_MR_CKEY_Pos 20 +#define AES_MR_CKEY_Msk (0xfu << AES_MR_CKEY_Pos) /**< \brief (AES_MR) Key */ +#define AES_MR_CKEY(value) ((AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))) +#define AES_MR_CKEY_PASSWD (0xEu << 20) /**< \brief (AES_MR) This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR, any value can be written, including that of 0xE.Always reads as 0. */ +/* -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- */ +#define AES_IER_DATRDY (0x1u << 0) /**< \brief (AES_IER) Data Ready Interrupt Enable */ +#define AES_IER_URAD (0x1u << 8) /**< \brief (AES_IER) Unspecified Register Access Detection Interrupt Enable */ +#define AES_IER_TAGRDY (0x1u << 16) /**< \brief (AES_IER) GCM Tag Ready Interrupt Enable */ +/* -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- */ +#define AES_IDR_DATRDY (0x1u << 0) /**< \brief (AES_IDR) Data Ready Interrupt Disable */ +#define AES_IDR_URAD (0x1u << 8) /**< \brief (AES_IDR) Unspecified Register Access Detection Interrupt Disable */ +#define AES_IDR_TAGRDY (0x1u << 16) /**< \brief (AES_IDR) GCM Tag Ready Interrupt Disable */ +/* -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- */ +#define AES_IMR_DATRDY (0x1u << 0) /**< \brief (AES_IMR) Data Ready Interrupt Mask */ +#define AES_IMR_URAD (0x1u << 8) /**< \brief (AES_IMR) Unspecified Register Access Detection Interrupt Mask */ +#define AES_IMR_TAGRDY (0x1u << 16) /**< \brief (AES_IMR) GCM Tag Ready Interrupt Mask */ +/* -------- AES_ISR : (AES Offset: 0x1C) Interrupt Status Register -------- */ +#define AES_ISR_DATRDY (0x1u << 0) /**< \brief (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) */ +#define AES_ISR_URAD (0x1u << 8) /**< \brief (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_Pos 12 +#define AES_ISR_URAT_Msk (0xfu << AES_ISR_URAT_Pos) /**< \brief (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) */ +#define AES_ISR_URAT_IDR_WR_PROCESSING (0x0u << 12) /**< \brief (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */ +#define AES_ISR_URAT_ODR_RD_PROCESSING (0x1u << 12) /**< \brief (AES_ISR) Output Data Register read during the data processing. */ +#define AES_ISR_URAT_MR_WR_PROCESSING (0x2u << 12) /**< \brief (AES_ISR) Mode Register written during the data processing. */ +#define AES_ISR_URAT_ODR_RD_SUBKGEN (0x3u << 12) /**< \brief (AES_ISR) Output Data Register read during the sub-keys generation. */ +#define AES_ISR_URAT_MR_WR_SUBKGEN (0x4u << 12) /**< \brief (AES_ISR) Mode Register written during the sub-keys generation. */ +#define AES_ISR_URAT_WOR_RD_ACCESS (0x5u << 12) /**< \brief (AES_ISR) Write-only register read access. */ +#define AES_ISR_TAGRDY (0x1u << 16) /**< \brief (AES_ISR) GCM Tag Ready */ +/* -------- AES_KEYWR[8] : (AES Offset: 0x20) Key Word Register -------- */ +#define AES_KEYWR_KEYW_Pos 0 +#define AES_KEYWR_KEYW_Msk (0xffffffffu << AES_KEYWR_KEYW_Pos) /**< \brief (AES_KEYWR[8]) Key Word */ +#define AES_KEYWR_KEYW(value) ((AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))) +/* -------- AES_IDATAR[4] : (AES Offset: 0x40) Input Data Register -------- */ +#define AES_IDATAR_IDATA_Pos 0 +#define AES_IDATAR_IDATA_Msk (0xffffffffu << AES_IDATAR_IDATA_Pos) /**< \brief (AES_IDATAR[4]) Input Data Word */ +#define AES_IDATAR_IDATA(value) ((AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))) +/* -------- AES_ODATAR[4] : (AES Offset: 0x50) Output Data Register -------- */ +#define AES_ODATAR_ODATA_Pos 0 +#define AES_ODATAR_ODATA_Msk (0xffffffffu << AES_ODATAR_ODATA_Pos) /**< \brief (AES_ODATAR[4]) Output Data */ +/* -------- AES_IVR[4] : (AES Offset: 0x60) Initialization Vector Register -------- */ +#define AES_IVR_IV_Pos 0 +#define AES_IVR_IV_Msk (0xffffffffu << AES_IVR_IV_Pos) /**< \brief (AES_IVR[4]) Initialization Vector */ +#define AES_IVR_IV(value) ((AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))) +/* -------- AES_AADLENR : (AES Offset: 0x70) Additional Authenticated Data Length Register -------- */ +#define AES_AADLENR_AADLEN_Pos 0 +#define AES_AADLENR_AADLEN_Msk (0xffffffffu << AES_AADLENR_AADLEN_Pos) /**< \brief (AES_AADLENR) Additional Authenticated Data Length */ +#define AES_AADLENR_AADLEN(value) ((AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))) +/* -------- AES_CLENR : (AES Offset: 0x74) Plaintext/Ciphertext Length Register -------- */ +#define AES_CLENR_CLEN_Pos 0 +#define AES_CLENR_CLEN_Msk (0xffffffffu << AES_CLENR_CLEN_Pos) /**< \brief (AES_CLENR) Plaintext/Ciphertext Length */ +#define AES_CLENR_CLEN(value) ((AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))) +/* -------- AES_GHASHR[4] : (AES Offset: 0x78) GCM Intermediate Hash Word Register -------- */ +#define AES_GHASHR_GHASH_Pos 0 +#define AES_GHASHR_GHASH_Msk (0xffffffffu << AES_GHASHR_GHASH_Pos) /**< \brief (AES_GHASHR[4]) Intermediate GCM Hash Word x */ +#define AES_GHASHR_GHASH(value) ((AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))) +/* -------- AES_TAGR[4] : (AES Offset: 0x88) GCM Authentication Tag Word Register -------- */ +#define AES_TAGR_TAG_Pos 0 +#define AES_TAGR_TAG_Msk (0xffffffffu << AES_TAGR_TAG_Pos) /**< \brief (AES_TAGR[4]) GCM Authentication Tag x */ +/* -------- AES_CTRR : (AES Offset: 0x98) GCM Encryption Counter Value Register -------- */ +#define AES_CTRR_CTR_Pos 0 +#define AES_CTRR_CTR_Msk (0xffffffffu << AES_CTRR_CTR_Pos) /**< \brief (AES_CTRR) GCM Encryption Counter */ +/* -------- AES_GCMHR[4] : (AES Offset: 0x9C) GCM H Word Register -------- */ +#define AES_GCMHR_H_Pos 0 +#define AES_GCMHR_H_Msk (0xffffffffu << AES_GCMHR_H_Pos) /**< \brief (AES_GCMHR[4]) GCM H Word x */ +#define AES_GCMHR_H(value) ((AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_AES_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_afec.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_afec.h new file mode 100644 index 000000000..2adc82645 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_afec.h @@ -0,0 +1,483 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC_COMPONENT_ +#define _SAMV71_AFEC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Analog Front-End Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_AFEC Analog Front-End Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Afec hardware registers */ +typedef struct { + __O uint32_t AFEC_CR; /**< \brief (Afec Offset: 0x00) AFEC Control Register */ + __IO uint32_t AFEC_MR; /**< \brief (Afec Offset: 0x04) AFEC Mode Register */ + __IO uint32_t AFEC_EMR; /**< \brief (Afec Offset: 0x08) AFEC Extended Mode Register */ + __IO uint32_t AFEC_SEQ1R; /**< \brief (Afec Offset: 0x0C) AFEC Channel Sequence 1 Register */ + __IO uint32_t AFEC_SEQ2R; /**< \brief (Afec Offset: 0x10) AFEC Channel Sequence 2 Register */ + __O uint32_t AFEC_CHER; /**< \brief (Afec Offset: 0x14) AFEC Channel Enable Register */ + __O uint32_t AFEC_CHDR; /**< \brief (Afec Offset: 0x18) AFEC Channel Disable Register */ + __I uint32_t AFEC_CHSR; /**< \brief (Afec Offset: 0x1C) AFEC Channel Status Register */ + __I uint32_t AFEC_LCDR; /**< \brief (Afec Offset: 0x20) AFEC Last Converted Data Register */ + __O uint32_t AFEC_IER; /**< \brief (Afec Offset: 0x24) AFEC Interrupt Enable Register */ + __O uint32_t AFEC_IDR; /**< \brief (Afec Offset: 0x28) AFEC Interrupt Disable Register */ + __I uint32_t AFEC_IMR; /**< \brief (Afec Offset: 0x2C) AFEC Interrupt Mask Register */ + __I uint32_t AFEC_ISR; /**< \brief (Afec Offset: 0x30) AFEC Interrupt Status Register */ + __I uint32_t Reserved1[6]; + __I uint32_t AFEC_OVER; /**< \brief (Afec Offset: 0x4C) AFEC Overrun Status Register */ + __IO uint32_t AFEC_CWR; /**< \brief (Afec Offset: 0x50) AFEC Compare Window Register */ + __IO uint32_t AFEC_CGR; /**< \brief (Afec Offset: 0x54) AFEC Channel Gain Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t AFEC_DIFFR; /**< \brief (Afec Offset: 0x60) AFEC Channel Differential Register */ + __IO uint32_t AFEC_CSELR; /**< \brief (Afec Offset: 0x64) AFEC Channel Selection Register */ + __I uint32_t AFEC_CDR; /**< \brief (Afec Offset: 0x68) AFEC Channel Data Register */ + __IO uint32_t AFEC_COCR; /**< \brief (Afec Offset: 0x6C) AFEC Channel Offset Compensation Register */ + __IO uint32_t AFEC_TEMPMR; /**< \brief (Afec Offset: 0x70) AFEC Temperature Sensor Mode Register */ + __IO uint32_t AFEC_TEMPCWR; /**< \brief (Afec Offset: 0x74) AFEC Temperature Compare Window Register */ + __I uint32_t Reserved3[7]; + __IO uint32_t AFEC_ACR; /**< \brief (Afec Offset: 0x94) AFEC Analog Control Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t AFEC_SHMR; /**< \brief (Afec Offset: 0xA0) AFEC Sample & Hold Mode Register */ + __I uint32_t Reserved5[11]; + __IO uint32_t AFEC_COSR; /**< \brief (Afec Offset: 0xD0) AFEC Correction Select Register */ + __IO uint32_t AFEC_CVR; /**< \brief (Afec Offset: 0xD4) AFEC Correction Values Register */ + __IO uint32_t AFEC_CECR; /**< \brief (Afec Offset: 0xD8) AFEC Channel Error Correction Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t AFEC_WPMR; /**< \brief (Afec Offset: 0xE4) AFEC Write Protection Mode Register */ + __I uint32_t AFEC_WPSR; /**< \brief (Afec Offset: 0xE8) AFEC Write Protection Status Register */ +} Afec; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- AFEC_CR : (AFEC Offset: 0x00) AFEC Control Register -------- */ +#define AFEC_CR_SWRST (0x1u << 0) /**< \brief (AFEC_CR) Software Reset */ +#define AFEC_CR_START (0x1u << 1) /**< \brief (AFEC_CR) Start Conversion */ +/* -------- AFEC_MR : (AFEC Offset: 0x04) AFEC Mode Register -------- */ +#define AFEC_MR_TRGEN (0x1u << 0) /**< \brief (AFEC_MR) Trigger Enable */ +#define AFEC_MR_TRGEN_DIS (0x0u << 0) /**< \brief (AFEC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ +#define AFEC_MR_TRGEN_EN (0x1u << 0) /**< \brief (AFEC_MR) Hardware trigger selected by TRGSEL field is enabled. */ +#define AFEC_MR_TRGSEL_Pos 1 +#define AFEC_MR_TRGSEL_Msk (0x7u << AFEC_MR_TRGSEL_Pos) /**< \brief (AFEC_MR) Trigger Selection */ +#define AFEC_MR_TRGSEL(value) ((AFEC_MR_TRGSEL_Msk & ((value) << AFEC_MR_TRGSEL_Pos))) +#define AFEC_MR_TRGSEL_AFEC_TRIG0 (0x0u << 1) /**< \brief (AFEC_MR) AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG1 (0x1u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG2 (0x2u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG3 (0x3u << 1) /**< \brief (AFEC_MR) TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG4 (0x4u << 1) /**< \brief (AFEC_MR) PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG5 (0x5u << 1) /**< \brief (AFEC_MR) PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 */ +#define AFEC_MR_TRGSEL_AFEC_TRIG6 (0x6u << 1) /**< \brief (AFEC_MR) Analog Comparator */ +#define AFEC_MR_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep Mode */ +#define AFEC_MR_SLEEP_NORMAL (0x0u << 5) /**< \brief (AFEC_MR) Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. */ +#define AFEC_MR_SLEEP_SLEEP (0x1u << 5) /**< \brief (AFEC_MR) Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. */ +#define AFEC_MR_FWUP (0x1u << 6) /**< \brief (AFEC_MR) Fast Wake-up */ +#define AFEC_MR_FWUP_OFF (0x0u << 6) /**< \brief (AFEC_MR) Normal Sleep mode: The sleep mode is defined by the SLEEP bit. */ +#define AFEC_MR_FWUP_ON (0x1u << 6) /**< \brief (AFEC_MR) Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. */ +#define AFEC_MR_FREERUN (0x1u << 7) /**< \brief (AFEC_MR) Free Run Mode */ +#define AFEC_MR_FREERUN_OFF (0x0u << 7) /**< \brief (AFEC_MR) Normal mode */ +#define AFEC_MR_FREERUN_ON (0x1u << 7) /**< \brief (AFEC_MR) Free Run mode: Never wait for any trigger. */ +#define AFEC_MR_PRESCAL_Pos 8 +#define AFEC_MR_PRESCAL_Msk (0xffu << AFEC_MR_PRESCAL_Pos) /**< \brief (AFEC_MR) Prescaler Rate Selection */ +#define AFEC_MR_PRESCAL(value) ((AFEC_MR_PRESCAL_Msk & ((value) << AFEC_MR_PRESCAL_Pos))) +#define AFEC_MR_STARTUP_Pos 16 +#define AFEC_MR_STARTUP_Msk (0xfu << AFEC_MR_STARTUP_Pos) /**< \brief (AFEC_MR) Start-up Time */ +#define AFEC_MR_STARTUP(value) ((AFEC_MR_STARTUP_Msk & ((value) << AFEC_MR_STARTUP_Pos))) +#define AFEC_MR_STARTUP_SUT0 (0x0u << 16) /**< \brief (AFEC_MR) 0 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT8 (0x1u << 16) /**< \brief (AFEC_MR) 8 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT16 (0x2u << 16) /**< \brief (AFEC_MR) 16 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT24 (0x3u << 16) /**< \brief (AFEC_MR) 24 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT64 (0x4u << 16) /**< \brief (AFEC_MR) 64 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT80 (0x5u << 16) /**< \brief (AFEC_MR) 80 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT96 (0x6u << 16) /**< \brief (AFEC_MR) 96 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT112 (0x7u << 16) /**< \brief (AFEC_MR) 112 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT512 (0x8u << 16) /**< \brief (AFEC_MR) 512 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT576 (0x9u << 16) /**< \brief (AFEC_MR) 576 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT640 (0xAu << 16) /**< \brief (AFEC_MR) 640 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT704 (0xBu << 16) /**< \brief (AFEC_MR) 704 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT768 (0xCu << 16) /**< \brief (AFEC_MR) 768 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT832 (0xDu << 16) /**< \brief (AFEC_MR) 832 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT896 (0xEu << 16) /**< \brief (AFEC_MR) 896 periods of AFE clock */ +#define AFEC_MR_STARTUP_SUT960 (0xFu << 16) /**< \brief (AFEC_MR) 960 periods of AFE clock */ +#define AFEC_MR_ONE (0x1u << 23) /**< \brief (AFEC_MR) One */ +#define AFEC_MR_TRACKTIM_Pos 24 +#define AFEC_MR_TRACKTIM_Msk (0xfu << AFEC_MR_TRACKTIM_Pos) /**< \brief (AFEC_MR) Tracking Time */ +#define AFEC_MR_TRACKTIM(value) ((AFEC_MR_TRACKTIM_Msk & ((value) << AFEC_MR_TRACKTIM_Pos))) +#define AFEC_MR_TRANSFER_Pos 28 +#define AFEC_MR_TRANSFER_Msk (0x3u << AFEC_MR_TRANSFER_Pos) /**< \brief (AFEC_MR) Transfer Period */ +#define AFEC_MR_TRANSFER(value) ((AFEC_MR_TRANSFER_Msk & ((value) << AFEC_MR_TRANSFER_Pos))) +#define AFEC_MR_USEQ (0x1u << 31) /**< \brief (AFEC_MR) User Sequence Enable */ +#define AFEC_MR_USEQ_NUM_ORDER (0x0u << 31) /**< \brief (AFEC_MR) Normal mode: The controller converts channels in a simple numeric order. */ +#define AFEC_MR_USEQ_REG_ORDER (0x1u << 31) /**< \brief (AFEC_MR) User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. */ +/* -------- AFEC_EMR : (AFEC Offset: 0x08) AFEC Extended Mode Register -------- */ +#define AFEC_EMR_CMPMODE_Pos 0 +#define AFEC_EMR_CMPMODE_Msk (0x3u << AFEC_EMR_CMPMODE_Pos) /**< \brief (AFEC_EMR) Comparison Mode */ +#define AFEC_EMR_CMPMODE(value) ((AFEC_EMR_CMPMODE_Msk & ((value) << AFEC_EMR_CMPMODE_Pos))) +#define AFEC_EMR_CMPMODE_LOW (0x0u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_EMR_CMPMODE_HIGH (0x1u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_EMR_CMPMODE_IN (0x2u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_EMR_CMPMODE_OUT (0x3u << 0) /**< \brief (AFEC_EMR) Generates an event when the converted data is out of the comparison window. */ +#define AFEC_EMR_CMPSEL_Pos 3 +#define AFEC_EMR_CMPSEL_Msk (0x1fu << AFEC_EMR_CMPSEL_Pos) /**< \brief (AFEC_EMR) Comparison Selected Channel */ +#define AFEC_EMR_CMPSEL(value) ((AFEC_EMR_CMPSEL_Msk & ((value) << AFEC_EMR_CMPSEL_Pos))) +#define AFEC_EMR_CMPALL (0x1u << 9) /**< \brief (AFEC_EMR) Compare All Channels */ +#define AFEC_EMR_CMPFILTER_Pos 12 +#define AFEC_EMR_CMPFILTER_Msk (0x3u << AFEC_EMR_CMPFILTER_Pos) /**< \brief (AFEC_EMR) Compare Event Filtering */ +#define AFEC_EMR_CMPFILTER(value) ((AFEC_EMR_CMPFILTER_Msk & ((value) << AFEC_EMR_CMPFILTER_Pos))) +#define AFEC_EMR_RES_Pos 16 +#define AFEC_EMR_RES_Msk (0x7u << AFEC_EMR_RES_Pos) /**< \brief (AFEC_EMR) Resolution */ +#define AFEC_EMR_RES(value) ((AFEC_EMR_RES_Msk & ((value) << AFEC_EMR_RES_Pos))) +#define AFEC_EMR_RES_NO_AVERAGE (0x0u << 16) /**< \brief (AFEC_EMR) 12-bit resolution, AFE sample rate is maximum (no averaging). */ +#define AFEC_EMR_RES_OSR4 (0x2u << 16) /**< \brief (AFEC_EMR) 13-bit resolution, AFE sample rate divided by 4 (averaging). */ +#define AFEC_EMR_RES_OSR16 (0x3u << 16) /**< \brief (AFEC_EMR) 14-bit resolution, AFE sample rate divided by 16 (averaging). */ +#define AFEC_EMR_RES_OSR64 (0x4u << 16) /**< \brief (AFEC_EMR) 15-bit resolution, AFE sample rate divided by 64 (averaging). */ +#define AFEC_EMR_RES_OSR256 (0x5u << 16) /**< \brief (AFEC_EMR) 16-bit resolution, AFE sample rate divided by 256 (averaging). */ +#define AFEC_EMR_TAG (0x1u << 24) /**< \brief (AFEC_EMR) TAG of the AFEC_LDCR */ +#define AFEC_EMR_STM (0x1u << 25) /**< \brief (AFEC_EMR) Single Trigger Mode */ +#define AFEC_EMR_SIGNMODE_Pos 28 +#define AFEC_EMR_SIGNMODE_Msk (0x3u << AFEC_EMR_SIGNMODE_Pos) /**< \brief (AFEC_EMR) Sign Mode */ +#define AFEC_EMR_SIGNMODE(value) ((AFEC_EMR_SIGNMODE_Msk & ((value) << AFEC_EMR_SIGNMODE_Pos))) +#define AFEC_EMR_SIGNMODE_SE_UNSG_DF_SIGN (0x0u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. */ +#define AFEC_EMR_SIGNMODE_SE_SIGN_DF_UNSG (0x1u << 28) /**< \brief (AFEC_EMR) Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_UNSIGNED (0x2u << 28) /**< \brief (AFEC_EMR) All channels: Unsigned conversions. */ +#define AFEC_EMR_SIGNMODE_ALL_SIGNED (0x3u << 28) /**< \brief (AFEC_EMR) All channels: Signed conversions. */ +/* -------- AFEC_SEQ1R : (AFEC Offset: 0x0C) AFEC Channel Sequence 1 Register -------- */ +#define AFEC_SEQ1R_USCH0_Pos 0 +#define AFEC_SEQ1R_USCH0_Msk (0xfu << AFEC_SEQ1R_USCH0_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 0 */ +#define AFEC_SEQ1R_USCH0(value) ((AFEC_SEQ1R_USCH0_Msk & ((value) << AFEC_SEQ1R_USCH0_Pos))) +#define AFEC_SEQ1R_USCH1_Pos 4 +#define AFEC_SEQ1R_USCH1_Msk (0xfu << AFEC_SEQ1R_USCH1_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 1 */ +#define AFEC_SEQ1R_USCH1(value) ((AFEC_SEQ1R_USCH1_Msk & ((value) << AFEC_SEQ1R_USCH1_Pos))) +#define AFEC_SEQ1R_USCH2_Pos 8 +#define AFEC_SEQ1R_USCH2_Msk (0xfu << AFEC_SEQ1R_USCH2_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 2 */ +#define AFEC_SEQ1R_USCH2(value) ((AFEC_SEQ1R_USCH2_Msk & ((value) << AFEC_SEQ1R_USCH2_Pos))) +#define AFEC_SEQ1R_USCH3_Pos 12 +#define AFEC_SEQ1R_USCH3_Msk (0xfu << AFEC_SEQ1R_USCH3_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 3 */ +#define AFEC_SEQ1R_USCH3(value) ((AFEC_SEQ1R_USCH3_Msk & ((value) << AFEC_SEQ1R_USCH3_Pos))) +#define AFEC_SEQ1R_USCH4_Pos 16 +#define AFEC_SEQ1R_USCH4_Msk (0xfu << AFEC_SEQ1R_USCH4_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 4 */ +#define AFEC_SEQ1R_USCH4(value) ((AFEC_SEQ1R_USCH4_Msk & ((value) << AFEC_SEQ1R_USCH4_Pos))) +#define AFEC_SEQ1R_USCH5_Pos 20 +#define AFEC_SEQ1R_USCH5_Msk (0xfu << AFEC_SEQ1R_USCH5_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 5 */ +#define AFEC_SEQ1R_USCH5(value) ((AFEC_SEQ1R_USCH5_Msk & ((value) << AFEC_SEQ1R_USCH5_Pos))) +#define AFEC_SEQ1R_USCH6_Pos 24 +#define AFEC_SEQ1R_USCH6_Msk (0xfu << AFEC_SEQ1R_USCH6_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 6 */ +#define AFEC_SEQ1R_USCH6(value) ((AFEC_SEQ1R_USCH6_Msk & ((value) << AFEC_SEQ1R_USCH6_Pos))) +#define AFEC_SEQ1R_USCH7_Pos 28 +#define AFEC_SEQ1R_USCH7_Msk (0xfu << AFEC_SEQ1R_USCH7_Pos) /**< \brief (AFEC_SEQ1R) User Sequence Number 7 */ +#define AFEC_SEQ1R_USCH7(value) ((AFEC_SEQ1R_USCH7_Msk & ((value) << AFEC_SEQ1R_USCH7_Pos))) +/* -------- AFEC_SEQ2R : (AFEC Offset: 0x10) AFEC Channel Sequence 2 Register -------- */ +#define AFEC_SEQ2R_USCH8_Pos 0 +#define AFEC_SEQ2R_USCH8_Msk (0xfu << AFEC_SEQ2R_USCH8_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 8 */ +#define AFEC_SEQ2R_USCH8(value) ((AFEC_SEQ2R_USCH8_Msk & ((value) << AFEC_SEQ2R_USCH8_Pos))) +#define AFEC_SEQ2R_USCH9_Pos 4 +#define AFEC_SEQ2R_USCH9_Msk (0xfu << AFEC_SEQ2R_USCH9_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 9 */ +#define AFEC_SEQ2R_USCH9(value) ((AFEC_SEQ2R_USCH9_Msk & ((value) << AFEC_SEQ2R_USCH9_Pos))) +#define AFEC_SEQ2R_USCH10_Pos 8 +#define AFEC_SEQ2R_USCH10_Msk (0xfu << AFEC_SEQ2R_USCH10_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 10 */ +#define AFEC_SEQ2R_USCH10(value) ((AFEC_SEQ2R_USCH10_Msk & ((value) << AFEC_SEQ2R_USCH10_Pos))) +#define AFEC_SEQ2R_USCH11_Pos 12 +#define AFEC_SEQ2R_USCH11_Msk (0xfu << AFEC_SEQ2R_USCH11_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 11 */ +#define AFEC_SEQ2R_USCH11(value) ((AFEC_SEQ2R_USCH11_Msk & ((value) << AFEC_SEQ2R_USCH11_Pos))) +#define AFEC_SEQ2R_USCH12_Pos 16 +#define AFEC_SEQ2R_USCH12_Msk (0xfu << AFEC_SEQ2R_USCH12_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 12 */ +#define AFEC_SEQ2R_USCH12(value) ((AFEC_SEQ2R_USCH12_Msk & ((value) << AFEC_SEQ2R_USCH12_Pos))) +#define AFEC_SEQ2R_USCH13_Pos 20 +#define AFEC_SEQ2R_USCH13_Msk (0xfu << AFEC_SEQ2R_USCH13_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 13 */ +#define AFEC_SEQ2R_USCH13(value) ((AFEC_SEQ2R_USCH13_Msk & ((value) << AFEC_SEQ2R_USCH13_Pos))) +#define AFEC_SEQ2R_USCH14_Pos 24 +#define AFEC_SEQ2R_USCH14_Msk (0xfu << AFEC_SEQ2R_USCH14_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 14 */ +#define AFEC_SEQ2R_USCH14(value) ((AFEC_SEQ2R_USCH14_Msk & ((value) << AFEC_SEQ2R_USCH14_Pos))) +#define AFEC_SEQ2R_USCH15_Pos 28 +#define AFEC_SEQ2R_USCH15_Msk (0xfu << AFEC_SEQ2R_USCH15_Pos) /**< \brief (AFEC_SEQ2R) User Sequence Number 15 */ +#define AFEC_SEQ2R_USCH15(value) ((AFEC_SEQ2R_USCH15_Msk & ((value) << AFEC_SEQ2R_USCH15_Pos))) +/* -------- AFEC_CHER : (AFEC Offset: 0x14) AFEC Channel Enable Register -------- */ +#define AFEC_CHER_CH0 (0x1u << 0) /**< \brief (AFEC_CHER) Channel 0 Enable */ +#define AFEC_CHER_CH1 (0x1u << 1) /**< \brief (AFEC_CHER) Channel 1 Enable */ +#define AFEC_CHER_CH2 (0x1u << 2) /**< \brief (AFEC_CHER) Channel 2 Enable */ +#define AFEC_CHER_CH3 (0x1u << 3) /**< \brief (AFEC_CHER) Channel 3 Enable */ +#define AFEC_CHER_CH4 (0x1u << 4) /**< \brief (AFEC_CHER) Channel 4 Enable */ +#define AFEC_CHER_CH5 (0x1u << 5) /**< \brief (AFEC_CHER) Channel 5 Enable */ +#define AFEC_CHER_CH6 (0x1u << 6) /**< \brief (AFEC_CHER) Channel 6 Enable */ +#define AFEC_CHER_CH7 (0x1u << 7) /**< \brief (AFEC_CHER) Channel 7 Enable */ +#define AFEC_CHER_CH8 (0x1u << 8) /**< \brief (AFEC_CHER) Channel 8 Enable */ +#define AFEC_CHER_CH9 (0x1u << 9) /**< \brief (AFEC_CHER) Channel 9 Enable */ +#define AFEC_CHER_CH10 (0x1u << 10) /**< \brief (AFEC_CHER) Channel 10 Enable */ +#define AFEC_CHER_CH11 (0x1u << 11) /**< \brief (AFEC_CHER) Channel 11 Enable */ +/* -------- AFEC_CHDR : (AFEC Offset: 0x18) AFEC Channel Disable Register -------- */ +#define AFEC_CHDR_CH0 (0x1u << 0) /**< \brief (AFEC_CHDR) Channel 0 Disable */ +#define AFEC_CHDR_CH1 (0x1u << 1) /**< \brief (AFEC_CHDR) Channel 1 Disable */ +#define AFEC_CHDR_CH2 (0x1u << 2) /**< \brief (AFEC_CHDR) Channel 2 Disable */ +#define AFEC_CHDR_CH3 (0x1u << 3) /**< \brief (AFEC_CHDR) Channel 3 Disable */ +#define AFEC_CHDR_CH4 (0x1u << 4) /**< \brief (AFEC_CHDR) Channel 4 Disable */ +#define AFEC_CHDR_CH5 (0x1u << 5) /**< \brief (AFEC_CHDR) Channel 5 Disable */ +#define AFEC_CHDR_CH6 (0x1u << 6) /**< \brief (AFEC_CHDR) Channel 6 Disable */ +#define AFEC_CHDR_CH7 (0x1u << 7) /**< \brief (AFEC_CHDR) Channel 7 Disable */ +#define AFEC_CHDR_CH8 (0x1u << 8) /**< \brief (AFEC_CHDR) Channel 8 Disable */ +#define AFEC_CHDR_CH9 (0x1u << 9) /**< \brief (AFEC_CHDR) Channel 9 Disable */ +#define AFEC_CHDR_CH10 (0x1u << 10) /**< \brief (AFEC_CHDR) Channel 10 Disable */ +#define AFEC_CHDR_CH11 (0x1u << 11) /**< \brief (AFEC_CHDR) Channel 11 Disable */ +/* -------- AFEC_CHSR : (AFEC Offset: 0x1C) AFEC Channel Status Register -------- */ +#define AFEC_CHSR_CH0 (0x1u << 0) /**< \brief (AFEC_CHSR) Channel 0 Status */ +#define AFEC_CHSR_CH1 (0x1u << 1) /**< \brief (AFEC_CHSR) Channel 1 Status */ +#define AFEC_CHSR_CH2 (0x1u << 2) /**< \brief (AFEC_CHSR) Channel 2 Status */ +#define AFEC_CHSR_CH3 (0x1u << 3) /**< \brief (AFEC_CHSR) Channel 3 Status */ +#define AFEC_CHSR_CH4 (0x1u << 4) /**< \brief (AFEC_CHSR) Channel 4 Status */ +#define AFEC_CHSR_CH5 (0x1u << 5) /**< \brief (AFEC_CHSR) Channel 5 Status */ +#define AFEC_CHSR_CH6 (0x1u << 6) /**< \brief (AFEC_CHSR) Channel 6 Status */ +#define AFEC_CHSR_CH7 (0x1u << 7) /**< \brief (AFEC_CHSR) Channel 7 Status */ +#define AFEC_CHSR_CH8 (0x1u << 8) /**< \brief (AFEC_CHSR) Channel 8 Status */ +#define AFEC_CHSR_CH9 (0x1u << 9) /**< \brief (AFEC_CHSR) Channel 9 Status */ +#define AFEC_CHSR_CH10 (0x1u << 10) /**< \brief (AFEC_CHSR) Channel 10 Status */ +#define AFEC_CHSR_CH11 (0x1u << 11) /**< \brief (AFEC_CHSR) Channel 11 Status */ +/* -------- AFEC_LCDR : (AFEC Offset: 0x20) AFEC Last Converted Data Register -------- */ +#define AFEC_LCDR_LDATA_Pos 0 +#define AFEC_LCDR_LDATA_Msk (0xffffu << AFEC_LCDR_LDATA_Pos) /**< \brief (AFEC_LCDR) Last Data Converted */ +#define AFEC_LCDR_CHNB_Pos 24 +#define AFEC_LCDR_CHNB_Msk (0xfu << AFEC_LCDR_CHNB_Pos) /**< \brief (AFEC_LCDR) Channel Number */ +/* -------- AFEC_IER : (AFEC Offset: 0x24) AFEC Interrupt Enable Register -------- */ +#define AFEC_IER_EOC0 (0x1u << 0) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 0 */ +#define AFEC_IER_EOC1 (0x1u << 1) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 1 */ +#define AFEC_IER_EOC2 (0x1u << 2) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 2 */ +#define AFEC_IER_EOC3 (0x1u << 3) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 3 */ +#define AFEC_IER_EOC4 (0x1u << 4) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 4 */ +#define AFEC_IER_EOC5 (0x1u << 5) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 5 */ +#define AFEC_IER_EOC6 (0x1u << 6) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 6 */ +#define AFEC_IER_EOC7 (0x1u << 7) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 7 */ +#define AFEC_IER_EOC8 (0x1u << 8) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 8 */ +#define AFEC_IER_EOC9 (0x1u << 9) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 9 */ +#define AFEC_IER_EOC10 (0x1u << 10) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 10 */ +#define AFEC_IER_EOC11 (0x1u << 11) /**< \brief (AFEC_IER) End of Conversion Interrupt Enable 11 */ +#define AFEC_IER_DRDY (0x1u << 24) /**< \brief (AFEC_IER) Data Ready Interrupt Enable */ +#define AFEC_IER_GOVRE (0x1u << 25) /**< \brief (AFEC_IER) General Overrun Error Interrupt Enable */ +#define AFEC_IER_COMPE (0x1u << 26) /**< \brief (AFEC_IER) Comparison Event Interrupt Enable */ +#define AFEC_IER_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IER) Temperature Change Interrupt Enable */ +/* -------- AFEC_IDR : (AFEC Offset: 0x28) AFEC Interrupt Disable Register -------- */ +#define AFEC_IDR_EOC0 (0x1u << 0) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 0 */ +#define AFEC_IDR_EOC1 (0x1u << 1) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 1 */ +#define AFEC_IDR_EOC2 (0x1u << 2) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 2 */ +#define AFEC_IDR_EOC3 (0x1u << 3) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 3 */ +#define AFEC_IDR_EOC4 (0x1u << 4) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 4 */ +#define AFEC_IDR_EOC5 (0x1u << 5) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 5 */ +#define AFEC_IDR_EOC6 (0x1u << 6) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 6 */ +#define AFEC_IDR_EOC7 (0x1u << 7) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 7 */ +#define AFEC_IDR_EOC8 (0x1u << 8) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 8 */ +#define AFEC_IDR_EOC9 (0x1u << 9) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 9 */ +#define AFEC_IDR_EOC10 (0x1u << 10) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 10 */ +#define AFEC_IDR_EOC11 (0x1u << 11) /**< \brief (AFEC_IDR) End of Conversion Interrupt Disable 11 */ +#define AFEC_IDR_DRDY (0x1u << 24) /**< \brief (AFEC_IDR) Data Ready Interrupt Disable */ +#define AFEC_IDR_GOVRE (0x1u << 25) /**< \brief (AFEC_IDR) General Overrun Error Interrupt Disable */ +#define AFEC_IDR_COMPE (0x1u << 26) /**< \brief (AFEC_IDR) Comparison Event Interrupt Disable */ +#define AFEC_IDR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IDR) Temperature Change Interrupt Disable */ +/* -------- AFEC_IMR : (AFEC Offset: 0x2C) AFEC Interrupt Mask Register -------- */ +#define AFEC_IMR_EOC0 (0x1u << 0) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 0 */ +#define AFEC_IMR_EOC1 (0x1u << 1) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 1 */ +#define AFEC_IMR_EOC2 (0x1u << 2) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 2 */ +#define AFEC_IMR_EOC3 (0x1u << 3) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 3 */ +#define AFEC_IMR_EOC4 (0x1u << 4) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 4 */ +#define AFEC_IMR_EOC5 (0x1u << 5) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 5 */ +#define AFEC_IMR_EOC6 (0x1u << 6) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 6 */ +#define AFEC_IMR_EOC7 (0x1u << 7) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 7 */ +#define AFEC_IMR_EOC8 (0x1u << 8) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 8 */ +#define AFEC_IMR_EOC9 (0x1u << 9) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 9 */ +#define AFEC_IMR_EOC10 (0x1u << 10) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 10 */ +#define AFEC_IMR_EOC11 (0x1u << 11) /**< \brief (AFEC_IMR) End of Conversion Interrupt Mask 11 */ +#define AFEC_IMR_DRDY (0x1u << 24) /**< \brief (AFEC_IMR) Data Ready Interrupt Mask */ +#define AFEC_IMR_GOVRE (0x1u << 25) /**< \brief (AFEC_IMR) General Overrun Error Interrupt Mask */ +#define AFEC_IMR_COMPE (0x1u << 26) /**< \brief (AFEC_IMR) Comparison Event Interrupt Mask */ +#define AFEC_IMR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_IMR) Temperature Change Interrupt Mask */ +/* -------- AFEC_ISR : (AFEC Offset: 0x30) AFEC Interrupt Status Register -------- */ +#define AFEC_ISR_EOC0 (0x1u << 0) /**< \brief (AFEC_ISR) End of Conversion 0 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC1 (0x1u << 1) /**< \brief (AFEC_ISR) End of Conversion 1 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC2 (0x1u << 2) /**< \brief (AFEC_ISR) End of Conversion 2 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC3 (0x1u << 3) /**< \brief (AFEC_ISR) End of Conversion 3 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC4 (0x1u << 4) /**< \brief (AFEC_ISR) End of Conversion 4 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC5 (0x1u << 5) /**< \brief (AFEC_ISR) End of Conversion 5 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC6 (0x1u << 6) /**< \brief (AFEC_ISR) End of Conversion 6 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC7 (0x1u << 7) /**< \brief (AFEC_ISR) End of Conversion 7 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC8 (0x1u << 8) /**< \brief (AFEC_ISR) End of Conversion 8 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC9 (0x1u << 9) /**< \brief (AFEC_ISR) End of Conversion 9 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC10 (0x1u << 10) /**< \brief (AFEC_ISR) End of Conversion 10 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_EOC11 (0x1u << 11) /**< \brief (AFEC_ISR) End of Conversion 11 (cleared by reading AFEC_CDRx) */ +#define AFEC_ISR_DRDY (0x1u << 24) /**< \brief (AFEC_ISR) Data Ready (cleared by reading AFEC_LCDR) */ +#define AFEC_ISR_GOVRE (0x1u << 25) /**< \brief (AFEC_ISR) General Overrun Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_COMPE (0x1u << 26) /**< \brief (AFEC_ISR) Comparison Error (cleared by reading AFEC_ISR) */ +#define AFEC_ISR_TEMPCHG (0x1u << 30) /**< \brief (AFEC_ISR) Temperature Change (cleared on read) */ +/* -------- AFEC_OVER : (AFEC Offset: 0x4C) AFEC Overrun Status Register -------- */ +#define AFEC_OVER_OVRE0 (0x1u << 0) /**< \brief (AFEC_OVER) Overrun Error 0 */ +#define AFEC_OVER_OVRE1 (0x1u << 1) /**< \brief (AFEC_OVER) Overrun Error 1 */ +#define AFEC_OVER_OVRE2 (0x1u << 2) /**< \brief (AFEC_OVER) Overrun Error 2 */ +#define AFEC_OVER_OVRE3 (0x1u << 3) /**< \brief (AFEC_OVER) Overrun Error 3 */ +#define AFEC_OVER_OVRE4 (0x1u << 4) /**< \brief (AFEC_OVER) Overrun Error 4 */ +#define AFEC_OVER_OVRE5 (0x1u << 5) /**< \brief (AFEC_OVER) Overrun Error 5 */ +#define AFEC_OVER_OVRE6 (0x1u << 6) /**< \brief (AFEC_OVER) Overrun Error 6 */ +#define AFEC_OVER_OVRE7 (0x1u << 7) /**< \brief (AFEC_OVER) Overrun Error 7 */ +#define AFEC_OVER_OVRE8 (0x1u << 8) /**< \brief (AFEC_OVER) Overrun Error 8 */ +#define AFEC_OVER_OVRE9 (0x1u << 9) /**< \brief (AFEC_OVER) Overrun Error 9 */ +#define AFEC_OVER_OVRE10 (0x1u << 10) /**< \brief (AFEC_OVER) Overrun Error 10 */ +#define AFEC_OVER_OVRE11 (0x1u << 11) /**< \brief (AFEC_OVER) Overrun Error 11 */ +/* -------- AFEC_CWR : (AFEC Offset: 0x50) AFEC Compare Window Register -------- */ +#define AFEC_CWR_LOWTHRES_Pos 0 +#define AFEC_CWR_LOWTHRES_Msk (0xffffu << AFEC_CWR_LOWTHRES_Pos) /**< \brief (AFEC_CWR) Low Threshold */ +#define AFEC_CWR_LOWTHRES(value) ((AFEC_CWR_LOWTHRES_Msk & ((value) << AFEC_CWR_LOWTHRES_Pos))) +#define AFEC_CWR_HIGHTHRES_Pos 16 +#define AFEC_CWR_HIGHTHRES_Msk (0xffffu << AFEC_CWR_HIGHTHRES_Pos) /**< \brief (AFEC_CWR) High Threshold */ +#define AFEC_CWR_HIGHTHRES(value) ((AFEC_CWR_HIGHTHRES_Msk & ((value) << AFEC_CWR_HIGHTHRES_Pos))) +/* -------- AFEC_CGR : (AFEC Offset: 0x54) AFEC Channel Gain Register -------- */ +#define AFEC_CGR_GAIN0_Pos 0 +#define AFEC_CGR_GAIN0_Msk (0x3u << AFEC_CGR_GAIN0_Pos) /**< \brief (AFEC_CGR) Gain for Channel 0 */ +#define AFEC_CGR_GAIN0(value) ((AFEC_CGR_GAIN0_Msk & ((value) << AFEC_CGR_GAIN0_Pos))) +#define AFEC_CGR_GAIN1_Pos 2 +#define AFEC_CGR_GAIN1_Msk (0x3u << AFEC_CGR_GAIN1_Pos) /**< \brief (AFEC_CGR) Gain for Channel 1 */ +#define AFEC_CGR_GAIN1(value) ((AFEC_CGR_GAIN1_Msk & ((value) << AFEC_CGR_GAIN1_Pos))) +#define AFEC_CGR_GAIN2_Pos 4 +#define AFEC_CGR_GAIN2_Msk (0x3u << AFEC_CGR_GAIN2_Pos) /**< \brief (AFEC_CGR) Gain for Channel 2 */ +#define AFEC_CGR_GAIN2(value) ((AFEC_CGR_GAIN2_Msk & ((value) << AFEC_CGR_GAIN2_Pos))) +#define AFEC_CGR_GAIN3_Pos 6 +#define AFEC_CGR_GAIN3_Msk (0x3u << AFEC_CGR_GAIN3_Pos) /**< \brief (AFEC_CGR) Gain for Channel 3 */ +#define AFEC_CGR_GAIN3(value) ((AFEC_CGR_GAIN3_Msk & ((value) << AFEC_CGR_GAIN3_Pos))) +#define AFEC_CGR_GAIN4_Pos 8 +#define AFEC_CGR_GAIN4_Msk (0x3u << AFEC_CGR_GAIN4_Pos) /**< \brief (AFEC_CGR) Gain for Channel 4 */ +#define AFEC_CGR_GAIN4(value) ((AFEC_CGR_GAIN4_Msk & ((value) << AFEC_CGR_GAIN4_Pos))) +#define AFEC_CGR_GAIN5_Pos 10 +#define AFEC_CGR_GAIN5_Msk (0x3u << AFEC_CGR_GAIN5_Pos) /**< \brief (AFEC_CGR) Gain for Channel 5 */ +#define AFEC_CGR_GAIN5(value) ((AFEC_CGR_GAIN5_Msk & ((value) << AFEC_CGR_GAIN5_Pos))) +#define AFEC_CGR_GAIN6_Pos 12 +#define AFEC_CGR_GAIN6_Msk (0x3u << AFEC_CGR_GAIN6_Pos) /**< \brief (AFEC_CGR) Gain for Channel 6 */ +#define AFEC_CGR_GAIN6(value) ((AFEC_CGR_GAIN6_Msk & ((value) << AFEC_CGR_GAIN6_Pos))) +#define AFEC_CGR_GAIN7_Pos 14 +#define AFEC_CGR_GAIN7_Msk (0x3u << AFEC_CGR_GAIN7_Pos) /**< \brief (AFEC_CGR) Gain for Channel 7 */ +#define AFEC_CGR_GAIN7(value) ((AFEC_CGR_GAIN7_Msk & ((value) << AFEC_CGR_GAIN7_Pos))) +#define AFEC_CGR_GAIN8_Pos 16 +#define AFEC_CGR_GAIN8_Msk (0x3u << AFEC_CGR_GAIN8_Pos) /**< \brief (AFEC_CGR) Gain for Channel 8 */ +#define AFEC_CGR_GAIN8(value) ((AFEC_CGR_GAIN8_Msk & ((value) << AFEC_CGR_GAIN8_Pos))) +#define AFEC_CGR_GAIN9_Pos 18 +#define AFEC_CGR_GAIN9_Msk (0x3u << AFEC_CGR_GAIN9_Pos) /**< \brief (AFEC_CGR) Gain for Channel 9 */ +#define AFEC_CGR_GAIN9(value) ((AFEC_CGR_GAIN9_Msk & ((value) << AFEC_CGR_GAIN9_Pos))) +#define AFEC_CGR_GAIN10_Pos 20 +#define AFEC_CGR_GAIN10_Msk (0x3u << AFEC_CGR_GAIN10_Pos) /**< \brief (AFEC_CGR) Gain for Channel 10 */ +#define AFEC_CGR_GAIN10(value) ((AFEC_CGR_GAIN10_Msk & ((value) << AFEC_CGR_GAIN10_Pos))) +#define AFEC_CGR_GAIN11_Pos 22 +#define AFEC_CGR_GAIN11_Msk (0x3u << AFEC_CGR_GAIN11_Pos) /**< \brief (AFEC_CGR) Gain for Channel 11 */ +#define AFEC_CGR_GAIN11(value) ((AFEC_CGR_GAIN11_Msk & ((value) << AFEC_CGR_GAIN11_Pos))) +/* -------- AFEC_DIFFR : (AFEC Offset: 0x60) AFEC Channel Differential Register -------- */ +#define AFEC_DIFFR_DIFF0 (0x1u << 0) /**< \brief (AFEC_DIFFR) Differential inputs for channel 0 */ +#define AFEC_DIFFR_DIFF1 (0x1u << 1) /**< \brief (AFEC_DIFFR) Differential inputs for channel 1 */ +#define AFEC_DIFFR_DIFF2 (0x1u << 2) /**< \brief (AFEC_DIFFR) Differential inputs for channel 2 */ +#define AFEC_DIFFR_DIFF3 (0x1u << 3) /**< \brief (AFEC_DIFFR) Differential inputs for channel 3 */ +#define AFEC_DIFFR_DIFF4 (0x1u << 4) /**< \brief (AFEC_DIFFR) Differential inputs for channel 4 */ +#define AFEC_DIFFR_DIFF5 (0x1u << 5) /**< \brief (AFEC_DIFFR) Differential inputs for channel 5 */ +#define AFEC_DIFFR_DIFF6 (0x1u << 6) /**< \brief (AFEC_DIFFR) Differential inputs for channel 6 */ +#define AFEC_DIFFR_DIFF7 (0x1u << 7) /**< \brief (AFEC_DIFFR) Differential inputs for channel 7 */ +#define AFEC_DIFFR_DIFF8 (0x1u << 8) /**< \brief (AFEC_DIFFR) Differential inputs for channel 8 */ +#define AFEC_DIFFR_DIFF9 (0x1u << 9) /**< \brief (AFEC_DIFFR) Differential inputs for channel 9 */ +#define AFEC_DIFFR_DIFF10 (0x1u << 10) /**< \brief (AFEC_DIFFR) Differential inputs for channel 10 */ +#define AFEC_DIFFR_DIFF11 (0x1u << 11) /**< \brief (AFEC_DIFFR) Differential inputs for channel 11 */ +/* -------- AFEC_CSELR : (AFEC Offset: 0x64) AFEC Channel Selection Register -------- */ +#define AFEC_CSELR_CSEL_Pos 0 +#define AFEC_CSELR_CSEL_Msk (0xfu << AFEC_CSELR_CSEL_Pos) /**< \brief (AFEC_CSELR) Channel Selection */ +#define AFEC_CSELR_CSEL(value) ((AFEC_CSELR_CSEL_Msk & ((value) << AFEC_CSELR_CSEL_Pos))) +/* -------- AFEC_CDR : (AFEC Offset: 0x68) AFEC Channel Data Register -------- */ +#define AFEC_CDR_DATA_Pos 0 +#define AFEC_CDR_DATA_Msk (0xffffu << AFEC_CDR_DATA_Pos) /**< \brief (AFEC_CDR) Converted Data */ +/* -------- AFEC_COCR : (AFEC Offset: 0x6C) AFEC Channel Offset Compensation Register -------- */ +#define AFEC_COCR_AOFF_Pos 0 +#define AFEC_COCR_AOFF_Msk (0xfffu << AFEC_COCR_AOFF_Pos) /**< \brief (AFEC_COCR) Analog Offset */ +#define AFEC_COCR_AOFF(value) ((AFEC_COCR_AOFF_Msk & ((value) << AFEC_COCR_AOFF_Pos))) +/* -------- AFEC_TEMPMR : (AFEC Offset: 0x70) AFEC Temperature Sensor Mode Register -------- */ +#define AFEC_TEMPMR_RTCT (0x1u << 0) /**< \brief (AFEC_TEMPMR) Temperature Sensor RTC Trigger Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD_Pos 4 +#define AFEC_TEMPMR_TEMPCMPMOD_Msk (0x3u << AFEC_TEMPMR_TEMPCMPMOD_Pos) /**< \brief (AFEC_TEMPMR) Temperature Comparison Mode */ +#define AFEC_TEMPMR_TEMPCMPMOD(value) ((AFEC_TEMPMR_TEMPCMPMOD_Msk & ((value) << AFEC_TEMPMR_TEMPCMPMOD_Pos))) +#define AFEC_TEMPMR_TEMPCMPMOD_LOW (0x0u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is lower than the low threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_HIGH (0x1u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is higher than the high threshold of the window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_IN (0x2u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is in the comparison window. */ +#define AFEC_TEMPMR_TEMPCMPMOD_OUT (0x3u << 4) /**< \brief (AFEC_TEMPMR) Generates an event when the converted data is out of the comparison window. */ +/* -------- AFEC_TEMPCWR : (AFEC Offset: 0x74) AFEC Temperature Compare Window Register -------- */ +#define AFEC_TEMPCWR_TLOWTHRES_Pos 0 +#define AFEC_TEMPCWR_TLOWTHRES_Msk (0xffffu << AFEC_TEMPCWR_TLOWTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature Low Threshold */ +#define AFEC_TEMPCWR_TLOWTHRES(value) ((AFEC_TEMPCWR_TLOWTHRES_Msk & ((value) << AFEC_TEMPCWR_TLOWTHRES_Pos))) +#define AFEC_TEMPCWR_THIGHTHRES_Pos 16 +#define AFEC_TEMPCWR_THIGHTHRES_Msk (0xffffu << AFEC_TEMPCWR_THIGHTHRES_Pos) /**< \brief (AFEC_TEMPCWR) Temperature High Threshold */ +#define AFEC_TEMPCWR_THIGHTHRES(value) ((AFEC_TEMPCWR_THIGHTHRES_Msk & ((value) << AFEC_TEMPCWR_THIGHTHRES_Pos))) +/* -------- AFEC_ACR : (AFEC Offset: 0x94) AFEC Analog Control Register -------- */ +#define AFEC_ACR_PGA0EN (0x1u << 2) /**< \brief (AFEC_ACR) PGA0 Enable */ +#define AFEC_ACR_PGA1EN (0x1u << 3) /**< \brief (AFEC_ACR) PGA1 Enable */ +#define AFEC_ACR_IBCTL_Pos 8 +#define AFEC_ACR_IBCTL_Msk (0x3u << AFEC_ACR_IBCTL_Pos) /**< \brief (AFEC_ACR) AFE Bias Current Control */ +#define AFEC_ACR_IBCTL(value) ((AFEC_ACR_IBCTL_Msk & ((value) << AFEC_ACR_IBCTL_Pos))) +/* -------- AFEC_SHMR : (AFEC Offset: 0xA0) AFEC Sample & Hold Mode Register -------- */ +#define AFEC_SHMR_DUAL0 (0x1u << 0) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 0 */ +#define AFEC_SHMR_DUAL1 (0x1u << 1) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 1 */ +#define AFEC_SHMR_DUAL2 (0x1u << 2) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 2 */ +#define AFEC_SHMR_DUAL3 (0x1u << 3) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 3 */ +#define AFEC_SHMR_DUAL4 (0x1u << 4) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 4 */ +#define AFEC_SHMR_DUAL5 (0x1u << 5) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 5 */ +#define AFEC_SHMR_DUAL6 (0x1u << 6) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 6 */ +#define AFEC_SHMR_DUAL7 (0x1u << 7) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 7 */ +#define AFEC_SHMR_DUAL8 (0x1u << 8) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 8 */ +#define AFEC_SHMR_DUAL9 (0x1u << 9) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 9 */ +#define AFEC_SHMR_DUAL10 (0x1u << 10) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 10 */ +#define AFEC_SHMR_DUAL11 (0x1u << 11) /**< \brief (AFEC_SHMR) Dual Sample & Hold for channel 11 */ +/* -------- AFEC_COSR : (AFEC Offset: 0xD0) AFEC Correction Select Register -------- */ +#define AFEC_COSR_CSEL (0x1u << 0) /**< \brief (AFEC_COSR) Sample & Hold unit Correction Select */ +/* -------- AFEC_CVR : (AFEC Offset: 0xD4) AFEC Correction Values Register -------- */ +#define AFEC_CVR_OFFSETCORR_Pos 0 +#define AFEC_CVR_OFFSETCORR_Msk (0xffffu << AFEC_CVR_OFFSETCORR_Pos) /**< \brief (AFEC_CVR) Offset Correction */ +#define AFEC_CVR_OFFSETCORR(value) ((AFEC_CVR_OFFSETCORR_Msk & ((value) << AFEC_CVR_OFFSETCORR_Pos))) +#define AFEC_CVR_GAINCORR_Pos 16 +#define AFEC_CVR_GAINCORR_Msk (0xffffu << AFEC_CVR_GAINCORR_Pos) /**< \brief (AFEC_CVR) Gain Correction */ +#define AFEC_CVR_GAINCORR(value) ((AFEC_CVR_GAINCORR_Msk & ((value) << AFEC_CVR_GAINCORR_Pos))) +/* -------- AFEC_CECR : (AFEC Offset: 0xD8) AFEC Channel Error Correction Register -------- */ +#define AFEC_CECR_ECORR0 (0x1u << 0) /**< \brief (AFEC_CECR) Error Correction Enable for channel 0 */ +#define AFEC_CECR_ECORR1 (0x1u << 1) /**< \brief (AFEC_CECR) Error Correction Enable for channel 1 */ +#define AFEC_CECR_ECORR2 (0x1u << 2) /**< \brief (AFEC_CECR) Error Correction Enable for channel 2 */ +#define AFEC_CECR_ECORR3 (0x1u << 3) /**< \brief (AFEC_CECR) Error Correction Enable for channel 3 */ +#define AFEC_CECR_ECORR4 (0x1u << 4) /**< \brief (AFEC_CECR) Error Correction Enable for channel 4 */ +#define AFEC_CECR_ECORR5 (0x1u << 5) /**< \brief (AFEC_CECR) Error Correction Enable for channel 5 */ +#define AFEC_CECR_ECORR6 (0x1u << 6) /**< \brief (AFEC_CECR) Error Correction Enable for channel 6 */ +#define AFEC_CECR_ECORR7 (0x1u << 7) /**< \brief (AFEC_CECR) Error Correction Enable for channel 7 */ +#define AFEC_CECR_ECORR8 (0x1u << 8) /**< \brief (AFEC_CECR) Error Correction Enable for channel 8 */ +#define AFEC_CECR_ECORR9 (0x1u << 9) /**< \brief (AFEC_CECR) Error Correction Enable for channel 9 */ +#define AFEC_CECR_ECORR10 (0x1u << 10) /**< \brief (AFEC_CECR) Error Correction Enable for channel 10 */ +#define AFEC_CECR_ECORR11 (0x1u << 11) /**< \brief (AFEC_CECR) Error Correction Enable for channel 11 */ +/* -------- AFEC_WPMR : (AFEC Offset: 0xE4) AFEC Write Protection Mode Register -------- */ +#define AFEC_WPMR_WPEN (0x1u << 0) /**< \brief (AFEC_WPMR) Write Protection Enable */ +#define AFEC_WPMR_WPKEY_Pos 8 +#define AFEC_WPMR_WPKEY_Msk (0xffffffu << AFEC_WPMR_WPKEY_Pos) /**< \brief (AFEC_WPMR) Write Protect KEY */ +#define AFEC_WPMR_WPKEY(value) ((AFEC_WPMR_WPKEY_Msk & ((value) << AFEC_WPMR_WPKEY_Pos))) +#define AFEC_WPMR_WPKEY_PASSWD (0x414443u << 8) /**< \brief (AFEC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- AFEC_WPSR : (AFEC Offset: 0xE8) AFEC Write Protection Status Register -------- */ +#define AFEC_WPSR_WPVS (0x1u << 0) /**< \brief (AFEC_WPSR) Write Protect Violation Status */ +#define AFEC_WPSR_WPVSRC_Pos 8 +#define AFEC_WPSR_WPVSRC_Msk (0xffffu << AFEC_WPSR_WPVSRC_Pos) /**< \brief (AFEC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_AFEC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_chipid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_chipid.h new file mode 100644 index 000000000..6e9722793 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_chipid.h @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_CHIPID_COMPONENT_ +#define _SAMV71_CHIPID_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Chip Identifier */ +/* ============================================================================= */ +/** \addtogroup SAMV71_CHIPID Chip Identifier */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Chipid hardware registers */ +typedef struct { + __I uint32_t CHIPID_CIDR; /**< \brief (Chipid Offset: 0x0) Chip ID Register */ + __I uint32_t CHIPID_EXID; /**< \brief (Chipid Offset: 0x4) Chip ID Extension Register */ +} Chipid; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ +#define CHIPID_CIDR_VERSION_Pos 0 +#define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /**< \brief (CHIPID_CIDR) Version of the Device */ +#define CHIPID_CIDR_EPROC_Pos 5 +#define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /**< \brief (CHIPID_CIDR) Embedded Processor */ +#define CHIPID_CIDR_EPROC_SAMx7 (0x0u << 5) /**< \brief (CHIPID_CIDR) Cortex-M7 */ +#define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /**< \brief (CHIPID_CIDR) ARM946ES */ +#define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /**< \brief (CHIPID_CIDR) ARM7TDMI */ +#define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /**< \brief (CHIPID_CIDR) Cortex-M3 */ +#define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /**< \brief (CHIPID_CIDR) ARM920T */ +#define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /**< \brief (CHIPID_CIDR) ARM926EJS */ +#define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /**< \brief (CHIPID_CIDR) Cortex-A5 */ +#define CHIPID_CIDR_EPROC_CM4 (0x7u << 5) /**< \brief (CHIPID_CIDR) Cortex-M4 */ +#define CHIPID_CIDR_NVPSIZ_Pos 8 +#define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_160K (0x8u << 8) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_Pos 12 +#define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /**< \brief (CHIPID_CIDR) Second Nonvolatile Program Memory Size */ +#define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /**< \brief (CHIPID_CIDR) None */ +#define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /**< \brief (CHIPID_CIDR) 1024 Kbytes */ +#define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /**< \brief (CHIPID_CIDR) 2048 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_Pos 16 +#define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /**< \brief (CHIPID_CIDR) Internal SRAM Size */ +#define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /**< \brief (CHIPID_CIDR) 48 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_192K (0x1u << 16) /**< \brief (CHIPID_CIDR) 192 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_384K (0x2u << 16) /**< \brief (CHIPID_CIDR) 384 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /**< \brief (CHIPID_CIDR) 6 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_24K (0x4u << 16) /**< \brief (CHIPID_CIDR) 24 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /**< \brief (CHIPID_CIDR) 4 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /**< \brief (CHIPID_CIDR) 80 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /**< \brief (CHIPID_CIDR) 160 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /**< \brief (CHIPID_CIDR) 8 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /**< \brief (CHIPID_CIDR) 16 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /**< \brief (CHIPID_CIDR) 32 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /**< \brief (CHIPID_CIDR) 64 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /**< \brief (CHIPID_CIDR) 128 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /**< \brief (CHIPID_CIDR) 256 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /**< \brief (CHIPID_CIDR) 96 Kbytes */ +#define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /**< \brief (CHIPID_CIDR) 512 Kbytes */ +#define CHIPID_CIDR_ARCH_Pos 20 +#define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /**< \brief (CHIPID_CIDR) Architecture Identifier */ +#define CHIPID_CIDR_ARCH_SAME70 (0x10u << 20) /**< \brief (CHIPID_CIDR) SAM E70 */ +#define CHIPID_CIDR_ARCH_SAMS70 (0x11u << 20) /**< \brief (CHIPID_CIDR) SAM S70 */ +#define CHIPID_CIDR_ARCH_SAMV71 (0x12u << 20) /**< \brief (CHIPID_CIDR) SAM V71 */ +#define CHIPID_CIDR_ARCH_SAMV70 (0x13u << 20) /**< \brief (CHIPID_CIDR) SAM V70 */ +#define CHIPID_CIDR_NVPTYP_Pos 28 +#define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /**< \brief (CHIPID_CIDR) Nonvolatile Program Memory Type */ +#define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /**< \brief (CHIPID_CIDR) ROM */ +#define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /**< \brief (CHIPID_CIDR) ROMless or on-chip Flash */ +#define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /**< \brief (CHIPID_CIDR) Embedded Flash Memory */ +#define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /**< \brief (CHIPID_CIDR) ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size */ +#define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /**< \brief (CHIPID_CIDR) SRAM emulating ROM */ +#define CHIPID_CIDR_EXT (0x1u << 31) /**< \brief (CHIPID_CIDR) Extension Flag */ +/* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ +#define CHIPID_EXID_EXID_Pos 0 +#define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /**< \brief (CHIPID_EXID) Chip ID Extension */ + +/*@}*/ + + +#endif /* _SAMV71_CHIPID_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_dacc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_dacc.h new file mode 100644 index 000000000..bec96dd43 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_dacc.h @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_DACC_COMPONENT_ +#define _SAMV71_DACC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_DACC Digital-to-Analog Converter Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Dacc hardware registers */ +typedef struct { + __O uint32_t DACC_CR; /**< \brief (Dacc Offset: 0x00) Control Register */ + __IO uint32_t DACC_MR; /**< \brief (Dacc Offset: 0x04) Mode Register */ + __IO uint32_t DACC_TRIGR; /**< \brief (Dacc Offset: 0x08) Trigger Register */ + __I uint32_t Reserved1[1]; + __O uint32_t DACC_CHER; /**< \brief (Dacc Offset: 0x10) Channel Enable Register */ + __O uint32_t DACC_CHDR; /**< \brief (Dacc Offset: 0x14) Channel Disable Register */ + __I uint32_t DACC_CHSR; /**< \brief (Dacc Offset: 0x18) Channel Status Register */ + __O uint32_t DACC_CDR[2]; /**< \brief (Dacc Offset: 0x1C) Conversion Data Register */ + __O uint32_t DACC_IER; /**< \brief (Dacc Offset: 0x24) Interrupt Enable Register */ + __O uint32_t DACC_IDR; /**< \brief (Dacc Offset: 0x28) Interrupt Disable Register */ + __I uint32_t DACC_IMR; /**< \brief (Dacc Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t DACC_ISR; /**< \brief (Dacc Offset: 0x30) Interrupt Status Register */ + __I uint32_t Reserved2[24]; + __IO uint32_t DACC_ACR; /**< \brief (Dacc Offset: 0x94) Analog Current Register */ + __I uint32_t Reserved3[19]; + __IO uint32_t DACC_WPMR; /**< \brief (Dacc Offset: 0xE4) Write Protection Mode register */ + __I uint32_t DACC_WPSR; /**< \brief (Dacc Offset: 0xE8) Write Protection Status register */ +} Dacc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ +#define DACC_CR_SWRST (0x1u << 0) /**< \brief (DACC_CR) Software Reset */ +/* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ +#define DACC_MR_MAXS0 (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode for Channel 0 */ +#define DACC_MR_MAXS0_TRIG_EVENT (0x0u << 0) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS0_MAXIMUM (0x1u << 0) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_MAXS1 (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode for Channel 1 */ +#define DACC_MR_MAXS1_TRIG_EVENT (0x0u << 1) /**< \brief (DACC_MR) Triggered by selected event */ +#define DACC_MR_MAXS1_MAXIMUM (0x1u << 1) /**< \brief (DACC_MR) Max Speed Mode enabled */ +#define DACC_MR_WORD (0x1u << 4) /**< \brief (DACC_MR) Word Transfer Mode */ +#define DACC_MR_WORD_DISABLED (0x0u << 4) /**< \brief (DACC_MR) One data to convert is written to the FIFO per access to DACC */ +#define DACC_MR_WORD_ENABLED (0x1u << 4) /**< \brief (DACC_MR) Two data to convert are written to the FIFO per access to DACC (reduces number of requests to DMA and the number of system bus accesses) */ +#define DACC_MR_REFRESH_Pos 8 +#define DACC_MR_REFRESH_Msk (0xffu << DACC_MR_REFRESH_Pos) /**< \brief (DACC_MR) Refresh Period */ +#define DACC_MR_REFRESH(value) ((DACC_MR_REFRESH_Msk & ((value) << DACC_MR_REFRESH_Pos))) +#define DACC_MR_DIFF (0x1u << 23) /**< \brief (DACC_MR) Differential Mode */ +#define DACC_MR_DIFF_DISABLED (0x0u << 23) /**< \brief (DACC_MR) DAC0 and DAC1 outputs can be separately configured */ +#define DACC_MR_DIFF_ENABLED (0x1u << 23) /**< \brief (DACC_MR) DACP and DACN outputs are configured by the channel 0 value. */ +#define DACC_MR_PRESCALER_Pos 24 +#define DACC_MR_PRESCALER_Msk (0xfu << DACC_MR_PRESCALER_Pos) /**< \brief (DACC_MR) Peripheral Clock to DAC Clock Ratio */ +#define DACC_MR_PRESCALER(value) ((DACC_MR_PRESCALER_Msk & ((value) << DACC_MR_PRESCALER_Pos))) +/* -------- DACC_TRIGR : (DACC Offset: 0x08) Trigger Register -------- */ +#define DACC_TRIGR_TRGEN0 (0x1u << 0) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 0 */ +#define DACC_TRIGR_TRGEN0_DIS (0x0u << 0) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN0_EN (0x1u << 0) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGEN1 (0x1u << 1) /**< \brief (DACC_TRIGR) Trigger Enable of Channel 1 */ +#define DACC_TRIGR_TRGEN1_DIS (0x0u << 1) /**< \brief (DACC_TRIGR) External trigger mode disabled. DAC is in free running mode. */ +#define DACC_TRIGR_TRGEN1_EN (0x1u << 1) /**< \brief (DACC_TRIGR) External trigger mode enabled. */ +#define DACC_TRIGR_TRGSEL0_Pos 4 +#define DACC_TRIGR_TRGSEL0_Msk (0x7u << DACC_TRIGR_TRGSEL0_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 0 */ +#define DACC_TRIGR_TRGSEL0(value) ((DACC_TRIGR_TRGSEL0_Msk & ((value) << DACC_TRIGR_TRGSEL0_Pos))) +#define DACC_TRIGR_TRGSEL0_TRGSEL0 (0x0u << 4) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL1 (0x1u << 4) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL2 (0x2u << 4) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL0_TRGSEL3 (0x3u << 4) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL4 (0x4u << 4) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL5 (0x5u << 4) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL0_TRGSEL6 (0x6u << 4) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_TRGSEL1_Pos 8 +#define DACC_TRIGR_TRGSEL1_Msk (0x7u << DACC_TRIGR_TRGSEL1_Pos) /**< \brief (DACC_TRIGR) Trigger Selection of Channel 1 */ +#define DACC_TRIGR_TRGSEL1(value) ((DACC_TRIGR_TRGSEL1_Msk & ((value) << DACC_TRIGR_TRGSEL1_Pos))) +#define DACC_TRIGR_TRGSEL1_TRGSEL0 (0x0u << 8) /**< \brief (DACC_TRIGR) TC0 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL1 (0x1u << 8) /**< \brief (DACC_TRIGR) TC1 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL2 (0x2u << 8) /**< \brief (DACC_TRIGR) TC2 output */ +#define DACC_TRIGR_TRGSEL1_TRGSEL3 (0x3u << 8) /**< \brief (DACC_TRIGR) PWM0 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL4 (0x4u << 8) /**< \brief (DACC_TRIGR) PWM0 event 1 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL5 (0x5u << 8) /**< \brief (DACC_TRIGR) PWM1 event 0 */ +#define DACC_TRIGR_TRGSEL1_TRGSEL6 (0x6u << 8) /**< \brief (DACC_TRIGR) PWM1 event 1 */ +#define DACC_TRIGR_OSR0_Pos 16 +#define DACC_TRIGR_OSR0_Msk (0x7u << DACC_TRIGR_OSR0_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 0 */ +#define DACC_TRIGR_OSR0(value) ((DACC_TRIGR_OSR0_Msk & ((value) << DACC_TRIGR_OSR0_Pos))) +#define DACC_TRIGR_OSR0_OSR_1 (0x0u << 16) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR0_OSR_2 (0x1u << 16) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR0_OSR_4 (0x2u << 16) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR0_OSR_8 (0x3u << 16) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR0_OSR_16 (0x4u << 16) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR0_OSR_32 (0x5u << 16) /**< \brief (DACC_TRIGR) OSR = 32 */ +#define DACC_TRIGR_OSR1_Pos 20 +#define DACC_TRIGR_OSR1_Msk (0x7u << DACC_TRIGR_OSR1_Pos) /**< \brief (DACC_TRIGR) Over Sampling Ratio of Channel 1 */ +#define DACC_TRIGR_OSR1(value) ((DACC_TRIGR_OSR1_Msk & ((value) << DACC_TRIGR_OSR1_Pos))) +#define DACC_TRIGR_OSR1_OSR_1 (0x0u << 20) /**< \brief (DACC_TRIGR) OSR = 1 */ +#define DACC_TRIGR_OSR1_OSR_2 (0x1u << 20) /**< \brief (DACC_TRIGR) OSR = 2 */ +#define DACC_TRIGR_OSR1_OSR_4 (0x2u << 20) /**< \brief (DACC_TRIGR) OSR = 4 */ +#define DACC_TRIGR_OSR1_OSR_8 (0x3u << 20) /**< \brief (DACC_TRIGR) OSR = 8 */ +#define DACC_TRIGR_OSR1_OSR_16 (0x4u << 20) /**< \brief (DACC_TRIGR) OSR = 16 */ +#define DACC_TRIGR_OSR1_OSR_32 (0x5u << 20) /**< \brief (DACC_TRIGR) OSR = 32 */ +/* -------- DACC_CHER : (DACC Offset: 0x10) Channel Enable Register -------- */ +#define DACC_CHER_CH0 (0x1u << 0) /**< \brief (DACC_CHER) Channel 0 Enable */ +#define DACC_CHER_CH1 (0x1u << 1) /**< \brief (DACC_CHER) Channel 1 Enable */ +/* -------- DACC_CHDR : (DACC Offset: 0x14) Channel Disable Register -------- */ +#define DACC_CHDR_CH0 (0x1u << 0) /**< \brief (DACC_CHDR) Channel 0 Disable */ +#define DACC_CHDR_CH1 (0x1u << 1) /**< \brief (DACC_CHDR) Channel 1 Disable */ +/* -------- DACC_CHSR : (DACC Offset: 0x18) Channel Status Register -------- */ +#define DACC_CHSR_CH0 (0x1u << 0) /**< \brief (DACC_CHSR) Channel 0 Status */ +#define DACC_CHSR_CH1 (0x1u << 1) /**< \brief (DACC_CHSR) Channel 1 Status */ +#define DACC_CHSR_DACRDY0 (0x1u << 8) /**< \brief (DACC_CHSR) DAC ready flag */ +#define DACC_CHSR_DACRDY1 (0x1u << 9) /**< \brief (DACC_CHSR) DAC ready flag */ +/* -------- DACC_CDR[2] : (DACC Offset: 0x1C) Conversion Data Register -------- */ +#define DACC_CDR_DATA0_Pos 0 +#define DACC_CDR_DATA0_Msk (0xffffu << DACC_CDR_DATA0_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 0 */ +#define DACC_CDR_DATA0(value) ((DACC_CDR_DATA0_Msk & ((value) << DACC_CDR_DATA0_Pos))) +#define DACC_CDR_DATA1_Pos 16 +#define DACC_CDR_DATA1_Msk (0xffffu << DACC_CDR_DATA1_Pos) /**< \brief (DACC_CDR[2]) Data to Convert for channel 1 */ +#define DACC_CDR_DATA1(value) ((DACC_CDR_DATA1_Msk & ((value) << DACC_CDR_DATA1_Pos))) +/* -------- DACC_IER : (DACC Offset: 0x24) Interrupt Enable Register -------- */ +#define DACC_IER_TXRDY0 (0x1u << 0) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 0 */ +#define DACC_IER_TXRDY1 (0x1u << 1) /**< \brief (DACC_IER) Transmit Ready Interrupt Enable of channel 1 */ +#define DACC_IER_EOC0 (0x1u << 4) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 0 */ +#define DACC_IER_EOC1 (0x1u << 5) /**< \brief (DACC_IER) End of Conversion Interrupt Enable of channel 1 */ +#define DACC_IER_ENDTX0 (0x1u << 8) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 0 */ +#define DACC_IER_ENDTX1 (0x1u << 9) /**< \brief (DACC_IER) End of Transmit Buffer Interrupt Enable of channel 1 */ +#define DACC_IER_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 0 */ +#define DACC_IER_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IER) Transmit Buffer Empty Interrupt Enable of channel 1 */ +/* -------- DACC_IDR : (DACC Offset: 0x28) Interrupt Disable Register -------- */ +#define DACC_IDR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 0 */ +#define DACC_IDR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IDR) Transmit Ready Interrupt Disable of channel 1 */ +#define DACC_IDR_EOC0 (0x1u << 4) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 0 */ +#define DACC_IDR_EOC1 (0x1u << 5) /**< \brief (DACC_IDR) End of Conversion Interrupt Disable of channel 1 */ +#define DACC_IDR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 0 */ +#define DACC_IDR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IDR) End of Transmit Buffer Interrupt Disable of channel 1 */ +#define DACC_IDR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 0 */ +#define DACC_IDR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IDR) Transmit Buffer Empty Interrupt Disable of channel 1 */ +/* -------- DACC_IMR : (DACC Offset: 0x2C) Interrupt Mask Register -------- */ +#define DACC_IMR_TXRDY0 (0x1u << 0) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 0 */ +#define DACC_IMR_TXRDY1 (0x1u << 1) /**< \brief (DACC_IMR) Transmit Ready Interrupt Mask of channel 1 */ +#define DACC_IMR_EOC0 (0x1u << 4) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 0 */ +#define DACC_IMR_EOC1 (0x1u << 5) /**< \brief (DACC_IMR) End of Conversion Interrupt Mask of channel 1 */ +#define DACC_IMR_ENDTX0 (0x1u << 8) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 0 */ +#define DACC_IMR_ENDTX1 (0x1u << 9) /**< \brief (DACC_IMR) End of Transmit Buffer Interrupt Mask of channel 1 */ +#define DACC_IMR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 0 */ +#define DACC_IMR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_IMR) Transmit Buffer Empty Interrupt Mask of channel 1 */ +/* -------- DACC_ISR : (DACC Offset: 0x30) Interrupt Status Register -------- */ +#define DACC_ISR_TXRDY0 (0x1u << 0) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 0 */ +#define DACC_ISR_TXRDY1 (0x1u << 1) /**< \brief (DACC_ISR) Transmit Ready Interrupt Flag of channel 1 */ +#define DACC_ISR_EOC0 (0x1u << 4) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 0 */ +#define DACC_ISR_EOC1 (0x1u << 5) /**< \brief (DACC_ISR) End of Conversion Interrupt Flag of channel 1 */ +#define DACC_ISR_ENDTX0 (0x1u << 8) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 0 */ +#define DACC_ISR_ENDTX1 (0x1u << 9) /**< \brief (DACC_ISR) End of DMA Interrupt Flag of channel 1 */ +#define DACC_ISR_TXBUFE0 (0x1u << 12) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 0 */ +#define DACC_ISR_TXBUFE1 (0x1u << 13) /**< \brief (DACC_ISR) Transmit Buffer Empty of channel 1 */ +/* -------- DACC_ACR : (DACC Offset: 0x94) Analog Current Register -------- */ +#define DACC_ACR_IBCTLCH0_Pos 0 +#define DACC_ACR_IBCTLCH0_Msk (0x3u << DACC_ACR_IBCTLCH0_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH0(value) ((DACC_ACR_IBCTLCH0_Msk & ((value) << DACC_ACR_IBCTLCH0_Pos))) +#define DACC_ACR_IBCTLCH1_Pos 2 +#define DACC_ACR_IBCTLCH1_Msk (0x3u << DACC_ACR_IBCTLCH1_Pos) /**< \brief (DACC_ACR) Analog Output Current Control */ +#define DACC_ACR_IBCTLCH1(value) ((DACC_ACR_IBCTLCH1_Msk & ((value) << DACC_ACR_IBCTLCH1_Pos))) +/* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protection Mode register -------- */ +#define DACC_WPMR_WPEN (0x1u << 0) /**< \brief (DACC_WPMR) Write Protection Enable */ +#define DACC_WPMR_WPKEY_Pos 8 +#define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /**< \brief (DACC_WPMR) Write Protect Key */ +#define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) +#define DACC_WPMR_WPKEY_PASSWD (0x444143u << 8) /**< \brief (DACC_WPMR) Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. */ +/* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protection Status register -------- */ +#define DACC_WPSR_WPVS (0x1u << 0) /**< \brief (DACC_WPSR) Write Protection Violation Status */ +#define DACC_WPSR_WPVSRC_Pos 8 +#define DACC_WPSR_WPVSRC_Msk (0xffu << DACC_WPSR_WPVSRC_Pos) /**< \brief (DACC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_DACC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_efc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_efc.h new file mode 100644 index 000000000..88c316aab --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_efc.h @@ -0,0 +1,118 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_EFC_COMPONENT_ +#define _SAMV71_EFC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Embedded Flash Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_EFC Embedded Flash Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Efc hardware registers */ +typedef struct { + __IO uint32_t EEFC_FMR; /**< \brief (Efc Offset: 0x00) EEFC Flash Mode Register */ + __O uint32_t EEFC_FCR; /**< \brief (Efc Offset: 0x04) EEFC Flash Command Register */ + __I uint32_t EEFC_FSR; /**< \brief (Efc Offset: 0x08) EEFC Flash Status Register */ + __I uint32_t EEFC_FRR; /**< \brief (Efc Offset: 0x0C) EEFC Flash Result Register */ + __I uint32_t Reserved1[1]; + __I uint32_t EEFC_VERSION; /**< \brief (Efc Offset: 0x14) EEFC Version Register */ + __I uint32_t Reserved2[51]; + __IO uint32_t EEFC_WPMR; /**< \brief (Efc Offset: 0xE4) Write Protection Mode Register */ +} Efc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- EEFC_FMR : (EFC Offset: 0x00) EEFC Flash Mode Register -------- */ +#define EEFC_FMR_FRDY (0x1u << 0) /**< \brief (EEFC_FMR) Flash Ready Interrupt Enable */ +#define EEFC_FMR_FWS_Pos 8 +#define EEFC_FMR_FWS_Msk (0xfu << EEFC_FMR_FWS_Pos) /**< \brief (EEFC_FMR) Flash Wait State */ +#define EEFC_FMR_FWS(value) ((EEFC_FMR_FWS_Msk & ((value) << EEFC_FMR_FWS_Pos))) +#define EEFC_FMR_SCOD (0x1u << 16) /**< \brief (EEFC_FMR) Sequential Code Optimization Disable */ +#define EEFC_FMR_CLOE (0x1u << 26) /**< \brief (EEFC_FMR) Code Loop Optimization Enable */ +/* -------- EEFC_FCR : (EFC Offset: 0x04) EEFC Flash Command Register -------- */ +#define EEFC_FCR_FCMD_Pos 0 +#define EEFC_FCR_FCMD_Msk (0xffu << EEFC_FCR_FCMD_Pos) /**< \brief (EEFC_FCR) Flash Command */ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) +#define EEFC_FCR_FCMD_GETD (0x0u << 0) /**< \brief (EEFC_FCR) Get Flash descriptor */ +#define EEFC_FCR_FCMD_WP (0x1u << 0) /**< \brief (EEFC_FCR) Write page */ +#define EEFC_FCR_FCMD_WPL (0x2u << 0) /**< \brief (EEFC_FCR) Write page and lock */ +#define EEFC_FCR_FCMD_EWP (0x3u << 0) /**< \brief (EEFC_FCR) Erase page and write page */ +#define EEFC_FCR_FCMD_EWPL (0x4u << 0) /**< \brief (EEFC_FCR) Erase page and write page then lock */ +#define EEFC_FCR_FCMD_EA (0x5u << 0) /**< \brief (EEFC_FCR) Erase all */ +#define EEFC_FCR_FCMD_EPA (0x7u << 0) /**< \brief (EEFC_FCR) Erase pages */ +#define EEFC_FCR_FCMD_SLB (0x8u << 0) /**< \brief (EEFC_FCR) Set lock bit */ +#define EEFC_FCR_FCMD_CLB (0x9u << 0) /**< \brief (EEFC_FCR) Clear lock bit */ +#define EEFC_FCR_FCMD_GLB (0xAu << 0) /**< \brief (EEFC_FCR) Get lock bit */ +#define EEFC_FCR_FCMD_SGPB (0xBu << 0) /**< \brief (EEFC_FCR) Set GPNVM bit */ +#define EEFC_FCR_FCMD_CGPB (0xCu << 0) /**< \brief (EEFC_FCR) Clear GPNVM bit */ +#define EEFC_FCR_FCMD_GGPB (0xDu << 0) /**< \brief (EEFC_FCR) Get GPNVM bit */ +#define EEFC_FCR_FCMD_STUI (0xEu << 0) /**< \brief (EEFC_FCR) Start read unique identifier */ +#define EEFC_FCR_FCMD_SPUI (0xFu << 0) /**< \brief (EEFC_FCR) Stop read unique identifier */ +#define EEFC_FCR_FCMD_GCALB (0x10u << 0) /**< \brief (EEFC_FCR) Get CALIB bit */ +#define EEFC_FCR_FCMD_ES (0x11u << 0) /**< \brief (EEFC_FCR) Erase sector */ +#define EEFC_FCR_FCMD_WUS (0x12u << 0) /**< \brief (EEFC_FCR) Write user signature */ +#define EEFC_FCR_FCMD_EUS (0x13u << 0) /**< \brief (EEFC_FCR) Erase user signature */ +#define EEFC_FCR_FCMD_STUS (0x14u << 0) /**< \brief (EEFC_FCR) Start read user signature */ +#define EEFC_FCR_FCMD_SPUS (0x15u << 0) /**< \brief (EEFC_FCR) Stop read user signature */ +#define EEFC_FCR_FARG_Pos 8 +#define EEFC_FCR_FARG_Msk (0xffffu << EEFC_FCR_FARG_Pos) /**< \brief (EEFC_FCR) Flash Command Argument */ +#define EEFC_FCR_FARG(value) ((EEFC_FCR_FARG_Msk & ((value) << EEFC_FCR_FARG_Pos))) +#define EEFC_FCR_FKEY_Pos 24 +#define EEFC_FCR_FKEY_Msk (0xffu << EEFC_FCR_FKEY_Pos) /**< \brief (EEFC_FCR) Flash Writing Protection Key */ +#define EEFC_FCR_FKEY(value) ((EEFC_FCR_FKEY_Msk & ((value) << EEFC_FCR_FKEY_Pos))) +#define EEFC_FCR_FKEY_PASSWD (0x5Au << 24) /**< \brief (EEFC_FCR) The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. */ +/* -------- EEFC_FSR : (EFC Offset: 0x08) EEFC Flash Status Register -------- */ +#define EEFC_FSR_FRDY (0x1u << 0) /**< \brief (EEFC_FSR) Flash Ready Status (cleared when Flash is busy) */ +#define EEFC_FSR_FCMDE (0x1u << 1) /**< \brief (EEFC_FSR) Flash Command Error Status (cleared on read or by writing EEFC_FCR) */ +#define EEFC_FSR_FLOCKE (0x1u << 2) /**< \brief (EEFC_FSR) Flash Lock Error Status (cleared on read) */ +#define EEFC_FSR_FLERR (0x1u << 3) /**< \brief (EEFC_FSR) Flash Error Status (cleared when a programming operation starts) */ +#define EEFC_FSR_UECCELSB (0x1u << 16) /**< \brief (EEFC_FSR) Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCELSB (0x1u << 17) /**< \brief (EEFC_FSR) Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_UECCEMSB (0x1u << 18) /**< \brief (EEFC_FSR) Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +#define EEFC_FSR_MECCEMSB (0x1u << 19) /**< \brief (EEFC_FSR) Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) */ +/* -------- EEFC_FRR : (EFC Offset: 0x0C) EEFC Flash Result Register -------- */ +#define EEFC_FRR_FVALUE_Pos 0 +#define EEFC_FRR_FVALUE_Msk (0xffffffffu << EEFC_FRR_FVALUE_Pos) /**< \brief (EEFC_FRR) Flash Result Value */ +/* -------- EEFC_VERSION : (EFC Offset: 0x14) EEFC Version Register -------- */ +#define EEFC_VERSION_VERSION_Pos 0 +#define EEFC_VERSION_VERSION_Msk (0xfffu << EEFC_VERSION_VERSION_Pos) /**< \brief (EEFC_VERSION) Version of the Hardware Module */ +#define EEFC_VERSION_MFN_Pos 16 +#define EEFC_VERSION_MFN_Msk (0x7u << EEFC_VERSION_MFN_Pos) /**< \brief (EEFC_VERSION) Metal Fix Number */ +/* -------- EEFC_WPMR : (EFC Offset: 0xE4) Write Protection Mode Register -------- */ +#define EEFC_WPMR_WPEN (0x1u << 0) /**< \brief (EEFC_WPMR) Write Protection Enable */ +#define EEFC_WPMR_WPKEY_Pos 8 +#define EEFC_WPMR_WPKEY_Msk (0xffffffu << EEFC_WPMR_WPKEY_Pos) /**< \brief (EEFC_WPMR) Write Protection Key */ +#define EEFC_WPMR_WPKEY(value) ((EEFC_WPMR_WPKEY_Msk & ((value) << EEFC_WPMR_WPKEY_Pos))) +#define EEFC_WPMR_WPKEY_PASSWD (0x454643u << 8) /**< \brief (EEFC_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_EFC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_gmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_gmac.h new file mode 100644 index 000000000..7a5612f39 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_gmac.h @@ -0,0 +1,832 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GMAC_COMPONENT_ +#define _SAMV71_GMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Gigabit Ethernet MAC */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GMAC Gigabit Ethernet MAC */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief GmacSa hardware registers */ +typedef struct { + __IO uint32_t GMAC_SAB; /**< \brief (GmacSa Offset: 0x0) Specific Address 1 Bottom Register */ + __IO uint32_t GMAC_SAT; /**< \brief (GmacSa Offset: 0x4) Specific Address 1 Top Register */ +} GmacSa; + +/** \brief GmacSt2Compare hardware registers */ +typedef struct { + __IO uint32_t GMAC_ST2COM0; /**< \brief 31:16 - Compare Value. 15:0 - Mask Value. */ + __IO uint32_t GMAC_ST2COM1; /**< \brief 31:9 - Reserved; 8:7 - Offset location in frame; 6:0 Offset value in bytes */ +} GmacSt2Compare; + +/** \brief Gmac hardware registers */ +#define GMACSA_NUMBER 4 +#define GMACST2COMPARE_NUMBER 24 +typedef struct { + __IO uint32_t GMAC_NCR; /**< \brief (Gmac Offset: 0x000) Network Control Register */ + __IO uint32_t GMAC_NCFGR; /**< \brief (Gmac Offset: 0x004) Network Configuration Register */ + __I uint32_t GMAC_NSR; /**< \brief (Gmac Offset: 0x008) Network Status Register */ + __IO uint32_t GMAC_UR; /**< \brief (Gmac Offset: 0x00C) User Register */ + __IO uint32_t GMAC_DCFGR; /**< \brief (Gmac Offset: 0x010) DMA Configuration Register */ + __IO uint32_t GMAC_TSR; /**< \brief (Gmac Offset: 0x014) Transmit Status Register */ + __IO uint32_t GMAC_RBQB; /**< \brief (Gmac Offset: 0x018) Receive Buffer Queue Base Address Register */ + __IO uint32_t GMAC_TBQB; /**< \brief (Gmac Offset: 0x01C) Transmit Buffer Queue Base Address Register */ + __IO uint32_t GMAC_RSR; /**< \brief (Gmac Offset: 0x020) Receive Status Register */ + __I uint32_t GMAC_ISR; /**< \brief (Gmac Offset: 0x024) Interrupt Status Register */ + __O uint32_t GMAC_IER; /**< \brief (Gmac Offset: 0x028) Interrupt Enable Register */ + __O uint32_t GMAC_IDR; /**< \brief (Gmac Offset: 0x02C) Interrupt Disable Register */ + __IO uint32_t GMAC_IMR; /**< \brief (Gmac Offset: 0x030) Interrupt Mask Register */ + __IO uint32_t GMAC_MAN; /**< \brief (Gmac Offset: 0x034) PHY Maintenance Register */ + __I uint32_t GMAC_RPQ; /**< \brief (Gmac Offset: 0x038) Received Pause Quantum Register */ + __IO uint32_t GMAC_TPQ; /**< \brief (Gmac Offset: 0x03C) Transmit Pause Quantum Register */ + __IO uint32_t GMAC_TPSF; /**< \brief (Gmac Offset: 0x040) TX Partial Store and Forward Register */ + __IO uint32_t GMAC_RPSF; /**< \brief (Gmac Offset: 0x044) RX Partial Store and Forward Register */ + __IO uint32_t GMAC_RJFML; /**< \brief (Gmac Offset: 0x048) RX Jumbo Frame Max Length Register */ + __I uint32_t Reserved1[13]; + __IO uint32_t GMAC_HRB; /**< \brief (Gmac Offset: 0x080) Hash Register Bottom */ + __IO uint32_t GMAC_HRT; /**< \brief (Gmac Offset: 0x084) Hash Register Top */ + GmacSa GMAC_SA[GMACSA_NUMBER]; /**< \brief (Gmac Offset: 0x088) 1 .. 4 */ + __IO uint32_t GMAC_TIDM1; /**< \brief (Gmac Offset: 0x0A8) Type ID Match 1 Register */ + __IO uint32_t GMAC_TIDM2; /**< \brief (Gmac Offset: 0x0AC) Type ID Match 2 Register */ + __IO uint32_t GMAC_TIDM3; /**< \brief (Gmac Offset: 0x0B0) Type ID Match 3 Register */ + __IO uint32_t GMAC_TIDM4; /**< \brief (Gmac Offset: 0x0B4) Type ID Match 4 Register */ + __IO uint32_t GMAC_WOL; /**< \brief (Gmac Offset: 0x0B8) Wake on LAN Register */ + __IO uint32_t GMAC_IPGS; /**< \brief (Gmac Offset: 0x0BC) IPG Stretch Register */ + __IO uint32_t GMAC_SVLAN; /**< \brief (Gmac Offset: 0x0C0) Stacked VLAN Register */ + __IO uint32_t GMAC_TPFCP; /**< \brief (Gmac Offset: 0x0C4) Transmit PFC Pause Register */ + __IO uint32_t GMAC_SAMB1; /**< \brief (Gmac Offset: 0x0C8) Specific Address 1 Mask Bottom Register */ + __IO uint32_t GMAC_SAMT1; /**< \brief (Gmac Offset: 0x0CC) Specific Address 1 Mask Top Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t GMAC_NSC; /**< \brief (Gmac Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register */ + __IO uint32_t GMAC_SCL; /**< \brief (Gmac Offset: 0x0E0) 1588 Timer Second Comparison Low Register */ + __IO uint32_t GMAC_SCH; /**< \brief (Gmac Offset: 0x0E4) 1588 Timer Second Comparison High Register */ + __I uint32_t GMAC_EFTSH; /**< \brief (Gmac Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_EFRSH; /**< \brief (Gmac Offset: 0x0EC) PTP Event Frame Received Seconds High Register */ + __I uint32_t GMAC_PEFTSH; /**< \brief (Gmac Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register */ + __I uint32_t GMAC_PEFRSH; /**< \brief (Gmac Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register */ + __I uint32_t Reserved3[2]; + __I uint32_t GMAC_OTLO; /**< \brief (Gmac Offset: 0x100) Octets Transmitted Low Register */ + __I uint32_t GMAC_OTHI; /**< \brief (Gmac Offset: 0x104) Octets Transmitted High Register */ + __I uint32_t GMAC_FT; /**< \brief (Gmac Offset: 0x108) Frames Transmitted Register */ + __I uint32_t GMAC_BCFT; /**< \brief (Gmac Offset: 0x10C) Broadcast Frames Transmitted Register */ + __I uint32_t GMAC_MFT; /**< \brief (Gmac Offset: 0x110) Multicast Frames Transmitted Register */ + __I uint32_t GMAC_PFT; /**< \brief (Gmac Offset: 0x114) Pause Frames Transmitted Register */ + __I uint32_t GMAC_BFT64; /**< \brief (Gmac Offset: 0x118) 64 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT127; /**< \brief (Gmac Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT255; /**< \brief (Gmac Offset: 0x120) 128 to 255 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT511; /**< \brief (Gmac Offset: 0x124) 256 to 511 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1023; /**< \brief (Gmac Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TBFT1518; /**< \brief (Gmac Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_GTBFT1518; /**< \brief (Gmac Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register */ + __I uint32_t GMAC_TUR; /**< \brief (Gmac Offset: 0x134) Transmit Underruns Register */ + __I uint32_t GMAC_SCF; /**< \brief (Gmac Offset: 0x138) Single Collision Frames Register */ + __I uint32_t GMAC_MCF; /**< \brief (Gmac Offset: 0x13C) Multiple Collision Frames Register */ + __I uint32_t GMAC_EC; /**< \brief (Gmac Offset: 0x140) Excessive Collisions Register */ + __I uint32_t GMAC_LC; /**< \brief (Gmac Offset: 0x144) Late Collisions Register */ + __I uint32_t GMAC_DTF; /**< \brief (Gmac Offset: 0x148) Deferred Transmission Frames Register */ + __I uint32_t GMAC_CSE; /**< \brief (Gmac Offset: 0x14C) Carrier Sense Errors Register Register */ + __I uint32_t GMAC_ORLO; /**< \brief (Gmac Offset: 0x150) Octets Received Low Received Register */ + __I uint32_t GMAC_ORHI; /**< \brief (Gmac Offset: 0x154) Octets Received High Received Register */ + __I uint32_t GMAC_FR; /**< \brief (Gmac Offset: 0x158) Frames Received Register */ + __I uint32_t GMAC_BCFR; /**< \brief (Gmac Offset: 0x15C) Broadcast Frames Received Register */ + __I uint32_t GMAC_MFR; /**< \brief (Gmac Offset: 0x160) Multicast Frames Received Register */ + __I uint32_t GMAC_PFR; /**< \brief (Gmac Offset: 0x164) Pause Frames Received Register */ + __I uint32_t GMAC_BFR64; /**< \brief (Gmac Offset: 0x168) 64 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR127; /**< \brief (Gmac Offset: 0x16C) 65 to 127 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR255; /**< \brief (Gmac Offset: 0x170) 128 to 255 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR511; /**< \brief (Gmac Offset: 0x174) 256 to 511 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1023; /**< \brief (Gmac Offset: 0x178) 512 to 1023 Byte Frames Received Register */ + __I uint32_t GMAC_TBFR1518; /**< \brief (Gmac Offset: 0x17C) 1024 to 1518 Byte Frames Received Register */ + __I uint32_t GMAC_TMXBFR; /**< \brief (Gmac Offset: 0x180) 1519 to Maximum Byte Frames Received Register */ + __I uint32_t GMAC_UFR; /**< \brief (Gmac Offset: 0x184) Undersize Frames Received Register */ + __I uint32_t GMAC_OFR; /**< \brief (Gmac Offset: 0x188) Oversize Frames Received Register */ + __I uint32_t GMAC_JR; /**< \brief (Gmac Offset: 0x18C) Jabbers Received Register */ + __I uint32_t GMAC_FCSE; /**< \brief (Gmac Offset: 0x190) Frame Check Sequence Errors Register */ + __I uint32_t GMAC_LFFE; /**< \brief (Gmac Offset: 0x194) Length Field Frame Errors Register */ + __I uint32_t GMAC_RSE; /**< \brief (Gmac Offset: 0x198) Receive Symbol Errors Register */ + __I uint32_t GMAC_AE; /**< \brief (Gmac Offset: 0x19C) Alignment Errors Register */ + __I uint32_t GMAC_RRE; /**< \brief (Gmac Offset: 0x1A0) Receive Resource Errors Register */ + __I uint32_t GMAC_ROE; /**< \brief (Gmac Offset: 0x1A4) Receive Overrun Register */ + __I uint32_t GMAC_IHCE; /**< \brief (Gmac Offset: 0x1A8) IP Header Checksum Errors Register */ + __I uint32_t GMAC_TCE; /**< \brief (Gmac Offset: 0x1AC) TCP Checksum Errors Register */ + __I uint32_t GMAC_UCE; /**< \brief (Gmac Offset: 0x1B0) UDP Checksum Errors Register */ + __I uint32_t Reserved4[2]; + __IO uint32_t GMAC_TISUBN; /**< \brief (Gmac Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register */ + __IO uint32_t GMAC_TSH; /**< \brief (Gmac Offset: 0x1C0) 1588 Timer Seconds High Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t GMAC_TSL; /**< \brief (Gmac Offset: 0x1D0) 1588 Timer Seconds Low Register */ + __IO uint32_t GMAC_TN; /**< \brief (Gmac Offset: 0x1D4) 1588 Timer Nanoseconds Register */ + __O uint32_t GMAC_TA; /**< \brief (Gmac Offset: 0x1D8) 1588 Timer Adjust Register */ + __IO uint32_t GMAC_TI; /**< \brief (Gmac Offset: 0x1DC) 1588 Timer Increment Register */ + __I uint32_t GMAC_EFTSL; /**< \brief (Gmac Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_EFTN; /**< \brief (Gmac Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_EFRSL; /**< \brief (Gmac Offset: 0x1E8) PTP Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_EFRN; /**< \brief (Gmac Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register */ + __I uint32_t GMAC_PEFTSL; /**< \brief (Gmac Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register */ + __I uint32_t GMAC_PEFTN; /**< \brief (Gmac Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register */ + __I uint32_t GMAC_PEFRSL; /**< \brief (Gmac Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register */ + __I uint32_t GMAC_PEFRN; /**< \brief (Gmac Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register */ + __I uint32_t Reserved6[128]; + __I uint32_t GMAC_ISRPQ[3]; /**< \brief (Gmac Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) */ + __I uint32_t Reserved7[13]; + __IO uint32_t GMAC_TBQBAPQ[3]; /**< \brief (Gmac Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved8[13]; + __IO uint32_t GMAC_RBQBAPQ[3]; /**< \brief (Gmac Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + __I uint32_t Reserved9[5]; + __IO uint32_t GMAC_RBSRPQ[3]; /**< \brief (Gmac Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) */ + __I uint32_t Reserved10[4]; + __IO uint32_t GMAC_CBSCR; /**< \brief (Gmac Offset: 0x4BC) Credit-Based Shaping Control Register */ + __IO uint32_t GMAC_CBSISQA; /**< \brief (Gmac Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A */ + __IO uint32_t GMAC_CBSISQB; /**< \brief (Gmac Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B */ + __I uint32_t Reserved11[14]; + __IO uint32_t GMAC_ST1RPQ[4]; /**< \brief (Gmac Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) */ + __I uint32_t Reserved12[12]; + __IO uint32_t GMAC_ST2RPQ[8]; /**< \brief (Gmac Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) */ + __I uint32_t Reserved13[12]; + __I uint32_t Reserved14[28]; + __O uint32_t GMAC_IERPQ[3]; /**< \brief (Gmac Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) */ + __I uint32_t Reserved15[5]; + __O uint32_t GMAC_IDRPQ[3]; /**< \brief (Gmac Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) */ + __I uint32_t Reserved16[5]; + __IO uint32_t GMAC_IMRPQ[3]; /**< \brief (Gmac Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) */ + __I uint32_t Reserved17[37]; + __IO uint32_t GMAC_ST2ER[4]; /**< \brief (Gmac Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) */ + __I uint32_t Reserved18[4]; + __IO GmacSt2Compare GMAC_ST2COMP[GMACST2COMPARE_NUMBER];/**< \brief (Gmac Offset: 0x700) Screener Type 2 Compare Registers */ +} Gmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- GMAC_NCR : (GMAC Offset: 0x000) Network Control Register -------- */ +#define GMAC_NCR_LBL (0x1u << 1) /**< \brief (GMAC_NCR) Loop Back Local */ +#define GMAC_NCR_RXEN (0x1u << 2) /**< \brief (GMAC_NCR) Receive Enable */ +#define GMAC_NCR_TXEN (0x1u << 3) /**< \brief (GMAC_NCR) Transmit Enable */ +#define GMAC_NCR_MPE (0x1u << 4) /**< \brief (GMAC_NCR) Management Port Enable */ +#define GMAC_NCR_CLRSTAT (0x1u << 5) /**< \brief (GMAC_NCR) Clear Statistics Registers */ +#define GMAC_NCR_INCSTAT (0x1u << 6) /**< \brief (GMAC_NCR) Increment Statistics Registers */ +#define GMAC_NCR_WESTAT (0x1u << 7) /**< \brief (GMAC_NCR) Write Enable for Statistics Registers */ +#define GMAC_NCR_BP (0x1u << 8) /**< \brief (GMAC_NCR) Back pressure */ +#define GMAC_NCR_TSTART (0x1u << 9) /**< \brief (GMAC_NCR) Start Transmission */ +#define GMAC_NCR_THALT (0x1u << 10) /**< \brief (GMAC_NCR) Transmit Halt */ +#define GMAC_NCR_TXPF (0x1u << 11) /**< \brief (GMAC_NCR) Transmit Pause Frame */ +#define GMAC_NCR_TXZQPF (0x1u << 12) /**< \brief (GMAC_NCR) Transmit Zero Quantum Pause Frame */ +#define GMAC_NCR_SRTSM (0x1u << 15) /**< \brief (GMAC_NCR) Store Receive Time Stamp to Memory */ +#define GMAC_NCR_ENPBPR (0x1u << 16) /**< \brief (GMAC_NCR) Enable PFC Priority-based Pause Reception */ +#define GMAC_NCR_TXPBPF (0x1u << 17) /**< \brief (GMAC_NCR) Transmit PFC Priority-based Pause Frame */ +#define GMAC_NCR_FNP (0x1u << 18) /**< \brief (GMAC_NCR) Flush Next Packet */ +/* -------- GMAC_NCFGR : (GMAC Offset: 0x004) Network Configuration Register -------- */ +#define GMAC_NCFGR_SPD (0x1u << 0) /**< \brief (GMAC_NCFGR) Speed */ +#define GMAC_NCFGR_FD (0x1u << 1) /**< \brief (GMAC_NCFGR) Full Duplex */ +#define GMAC_NCFGR_DNVLAN (0x1u << 2) /**< \brief (GMAC_NCFGR) Discard Non-VLAN FRAMES */ +#define GMAC_NCFGR_JFRAME (0x1u << 3) /**< \brief (GMAC_NCFGR) Jumbo Frame Size */ +#define GMAC_NCFGR_CAF (0x1u << 4) /**< \brief (GMAC_NCFGR) Copy All Frames */ +#define GMAC_NCFGR_NBC (0x1u << 5) /**< \brief (GMAC_NCFGR) No Broadcast */ +#define GMAC_NCFGR_MTIHEN (0x1u << 6) /**< \brief (GMAC_NCFGR) Multicast Hash Enable */ +#define GMAC_NCFGR_UNIHEN (0x1u << 7) /**< \brief (GMAC_NCFGR) Unicast Hash Enable */ +#define GMAC_NCFGR_MAXFS (0x1u << 8) /**< \brief (GMAC_NCFGR) 1536 Maximum Frame Size */ +#define GMAC_NCFGR_RTY (0x1u << 12) /**< \brief (GMAC_NCFGR) Retry Test */ +#define GMAC_NCFGR_PEN (0x1u << 13) /**< \brief (GMAC_NCFGR) Pause Enable */ +#define GMAC_NCFGR_RXBUFO_Pos 14 +#define GMAC_NCFGR_RXBUFO_Msk (0x3u << GMAC_NCFGR_RXBUFO_Pos) /**< \brief (GMAC_NCFGR) Receive Buffer Offset */ +#define GMAC_NCFGR_RXBUFO(value) ((GMAC_NCFGR_RXBUFO_Msk & ((value) << GMAC_NCFGR_RXBUFO_Pos))) +#define GMAC_NCFGR_LFERD (0x1u << 16) /**< \brief (GMAC_NCFGR) Length Field Error Frame Discard */ +#define GMAC_NCFGR_RFCS (0x1u << 17) /**< \brief (GMAC_NCFGR) Remove FCS */ +#define GMAC_NCFGR_CLK_Pos 18 +#define GMAC_NCFGR_CLK_Msk (0x7u << GMAC_NCFGR_CLK_Pos) /**< \brief (GMAC_NCFGR) MDC CLock Division */ +#define GMAC_NCFGR_CLK(value) ((GMAC_NCFGR_CLK_Msk & ((value) << GMAC_NCFGR_CLK_Pos))) +#define GMAC_NCFGR_CLK_MCK_8 (0x0u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 8 (MCK up to 20 MHz) */ +#define GMAC_NCFGR_CLK_MCK_16 (0x1u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 16 (MCK up to 40 MHz) */ +#define GMAC_NCFGR_CLK_MCK_32 (0x2u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 32 (MCK up to 80 MHz) */ +#define GMAC_NCFGR_CLK_MCK_48 (0x3u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 48 (MCK up to 120 MHz) */ +#define GMAC_NCFGR_CLK_MCK_64 (0x4u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 64 (MCK up to 160 MHz) */ +#define GMAC_NCFGR_CLK_MCK_96 (0x5u << 18) /**< \brief (GMAC_NCFGR) MCK divided by 96 (MCK up to 240 MHz) */ +#define GMAC_NCFGR_DBW_Pos 21 +#define GMAC_NCFGR_DBW_Msk (0x3u << GMAC_NCFGR_DBW_Pos) /**< \brief (GMAC_NCFGR) Data Bus Width */ +#define GMAC_NCFGR_DBW(value) ((GMAC_NCFGR_DBW_Msk & ((value) << GMAC_NCFGR_DBW_Pos))) +#define GMAC_NCFGR_DCPF (0x1u << 23) /**< \brief (GMAC_NCFGR) Disable Copy of Pause Frames */ +#define GMAC_NCFGR_RXCOEN (0x1u << 24) /**< \brief (GMAC_NCFGR) Receive Checksum Offload Enable */ +#define GMAC_NCFGR_EFRHD (0x1u << 25) /**< \brief (GMAC_NCFGR) Enable Frames Received in Half Duplex */ +#define GMAC_NCFGR_IRXFCS (0x1u << 26) /**< \brief (GMAC_NCFGR) Ignore RX FCS */ +#define GMAC_NCFGR_IPGSEN (0x1u << 28) /**< \brief (GMAC_NCFGR) IP Stretch Enable */ +#define GMAC_NCFGR_RXBP (0x1u << 29) /**< \brief (GMAC_NCFGR) Receive Bad Preamble */ +#define GMAC_NCFGR_IRXER (0x1u << 30) /**< \brief (GMAC_NCFGR) Ignore IPG GRXER */ +/* -------- GMAC_NSR : (GMAC Offset: 0x008) Network Status Register -------- */ +#define GMAC_NSR_MDIO (0x1u << 1) /**< \brief (GMAC_NSR) MDIO Input Status */ +#define GMAC_NSR_IDLE (0x1u << 2) /**< \brief (GMAC_NSR) PHY Management Logic Idle */ +/* -------- GMAC_UR : (GMAC Offset: 0x00C) User Register -------- */ +#define GMAC_UR_RMII (0x1u << 0) /**< \brief (GMAC_UR) Reduced MII Mode */ +/* -------- GMAC_DCFGR : (GMAC Offset: 0x010) DMA Configuration Register -------- */ +#define GMAC_DCFGR_FBLDO_Pos 0 +#define GMAC_DCFGR_FBLDO_Msk (0x1fu << GMAC_DCFGR_FBLDO_Pos) /**< \brief (GMAC_DCFGR) Fixed Burst Length for DMA Data Operations: */ +#define GMAC_DCFGR_FBLDO(value) ((GMAC_DCFGR_FBLDO_Msk & ((value) << GMAC_DCFGR_FBLDO_Pos))) +#define GMAC_DCFGR_FBLDO_SINGLE (0x1u << 0) /**< \brief (GMAC_DCFGR) 00001: Always use SINGLE AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR4 (0x4u << 0) /**< \brief (GMAC_DCFGR) 001xx: Attempt to use INCR4 AHB bursts (Default) */ +#define GMAC_DCFGR_FBLDO_INCR8 (0x8u << 0) /**< \brief (GMAC_DCFGR) 01xxx: Attempt to use INCR8 AHB bursts */ +#define GMAC_DCFGR_FBLDO_INCR16 (0x10u << 0) /**< \brief (GMAC_DCFGR) 1xxxx: Attempt to use INCR16 AHB bursts */ +#define GMAC_DCFGR_ESMA (0x1u << 6) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Management Descriptor Accesses */ +#define GMAC_DCFGR_ESPA (0x1u << 7) /**< \brief (GMAC_DCFGR) Endian Swap Mode Enable for Packet Data Accesses */ +#define GMAC_DCFGR_RXBMS_Pos 8 +#define GMAC_DCFGR_RXBMS_Msk (0x3u << GMAC_DCFGR_RXBMS_Pos) /**< \brief (GMAC_DCFGR) Receiver Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_RXBMS(value) ((GMAC_DCFGR_RXBMS_Msk & ((value) << GMAC_DCFGR_RXBMS_Pos))) +#define GMAC_DCFGR_RXBMS_EIGHTH (0x0u << 8) /**< \brief (GMAC_DCFGR) 4/8 Kbyte Memory Size */ +#define GMAC_DCFGR_RXBMS_QUARTER (0x1u << 8) /**< \brief (GMAC_DCFGR) 4/4 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_HALF (0x2u << 8) /**< \brief (GMAC_DCFGR) 4/2 Kbytes Memory Size */ +#define GMAC_DCFGR_RXBMS_FULL (0x3u << 8) /**< \brief (GMAC_DCFGR) 4 Kbytes Memory Size */ +#define GMAC_DCFGR_TXPBMS (0x1u << 10) /**< \brief (GMAC_DCFGR) Transmitter Packet Buffer Memory Size Select */ +#define GMAC_DCFGR_TXCOEN (0x1u << 11) /**< \brief (GMAC_DCFGR) Transmitter Checksum Generation Offload Enable */ +#define GMAC_DCFGR_DRBS_Pos 16 +#define GMAC_DCFGR_DRBS_Msk (0xffu << GMAC_DCFGR_DRBS_Pos) /**< \brief (GMAC_DCFGR) DMA Receive Buffer Size */ +#define GMAC_DCFGR_DRBS(value) ((GMAC_DCFGR_DRBS_Msk & ((value) << GMAC_DCFGR_DRBS_Pos))) +#define GMAC_DCFGR_DDRP (0x1u << 24) /**< \brief (GMAC_DCFGR) DMA Discard Receive Packets */ +/* -------- GMAC_TSR : (GMAC Offset: 0x014) Transmit Status Register -------- */ +#define GMAC_TSR_UBR (0x1u << 0) /**< \brief (GMAC_TSR) Used Bit Read */ +#define GMAC_TSR_COL (0x1u << 1) /**< \brief (GMAC_TSR) Collision Occurred */ +#define GMAC_TSR_RLE (0x1u << 2) /**< \brief (GMAC_TSR) Retry Limit Exceeded */ +#define GMAC_TSR_TXGO (0x1u << 3) /**< \brief (GMAC_TSR) Transmit Go */ +#define GMAC_TSR_TFC (0x1u << 4) /**< \brief (GMAC_TSR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_TSR_TXCOMP (0x1u << 5) /**< \brief (GMAC_TSR) Transmit Complete */ +#define GMAC_TSR_HRESP (0x1u << 8) /**< \brief (GMAC_TSR) HRESP Not OK */ +/* -------- GMAC_RBQB : (GMAC Offset: 0x018) Receive Buffer Queue Base Address Register -------- */ +#define GMAC_RBQB_ADDR_Pos 2 +#define GMAC_RBQB_ADDR_Msk (0x3fffffffu << GMAC_RBQB_ADDR_Pos) /**< \brief (GMAC_RBQB) Receive Buffer Queue Base Address */ +#define GMAC_RBQB_ADDR(value) ((GMAC_RBQB_ADDR_Msk & ((value) << GMAC_RBQB_ADDR_Pos))) +/* -------- GMAC_TBQB : (GMAC Offset: 0x01C) Transmit Buffer Queue Base Address Register -------- */ +#define GMAC_TBQB_ADDR_Pos 2 +#define GMAC_TBQB_ADDR_Msk (0x3fffffffu << GMAC_TBQB_ADDR_Pos) /**< \brief (GMAC_TBQB) Transmit Buffer Queue Base Address */ +#define GMAC_TBQB_ADDR(value) ((GMAC_TBQB_ADDR_Msk & ((value) << GMAC_TBQB_ADDR_Pos))) +/* -------- GMAC_RSR : (GMAC Offset: 0x020) Receive Status Register -------- */ +#define GMAC_RSR_BNA (0x1u << 0) /**< \brief (GMAC_RSR) Buffer Not Available */ +#define GMAC_RSR_REC (0x1u << 1) /**< \brief (GMAC_RSR) Frame Received */ +#define GMAC_RSR_RXOVR (0x1u << 2) /**< \brief (GMAC_RSR) Receive Overrun */ +#define GMAC_RSR_HNO (0x1u << 3) /**< \brief (GMAC_RSR) HRESP Not OK */ +/* -------- GMAC_ISR : (GMAC Offset: 0x024) Interrupt Status Register -------- */ +#define GMAC_ISR_MFS (0x1u << 0) /**< \brief (GMAC_ISR) Management Frame Sent */ +#define GMAC_ISR_RCOMP (0x1u << 1) /**< \brief (GMAC_ISR) Receive Complete */ +#define GMAC_ISR_RXUBR (0x1u << 2) /**< \brief (GMAC_ISR) RX Used Bit Read */ +#define GMAC_ISR_TXUBR (0x1u << 3) /**< \brief (GMAC_ISR) TX Used Bit Read */ +#define GMAC_ISR_TUR (0x1u << 4) /**< \brief (GMAC_ISR) Transmit Underrun */ +#define GMAC_ISR_RLEX (0x1u << 5) /**< \brief (GMAC_ISR) Retry Limit Exceeded */ +#define GMAC_ISR_TFC (0x1u << 6) /**< \brief (GMAC_ISR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISR_TCOMP (0x1u << 7) /**< \brief (GMAC_ISR) Transmit Complete */ +#define GMAC_ISR_ROVR (0x1u << 10) /**< \brief (GMAC_ISR) Receive Overrun */ +#define GMAC_ISR_HRESP (0x1u << 11) /**< \brief (GMAC_ISR) HRESP Not OK */ +#define GMAC_ISR_PFNZ (0x1u << 12) /**< \brief (GMAC_ISR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_ISR_PTZ (0x1u << 13) /**< \brief (GMAC_ISR) Pause Time Zero */ +#define GMAC_ISR_PFTR (0x1u << 14) /**< \brief (GMAC_ISR) Pause Frame Transmitted */ +#define GMAC_ISR_DRQFR (0x1u << 18) /**< \brief (GMAC_ISR) PTP Delay Request Frame Received */ +#define GMAC_ISR_SFR (0x1u << 19) /**< \brief (GMAC_ISR) PTP Sync Frame Received */ +#define GMAC_ISR_DRQFT (0x1u << 20) /**< \brief (GMAC_ISR) PTP Delay Request Frame Transmitted */ +#define GMAC_ISR_SFT (0x1u << 21) /**< \brief (GMAC_ISR) PTP Sync Frame Transmitted */ +#define GMAC_ISR_PDRQFR (0x1u << 22) /**< \brief (GMAC_ISR) PDelay Request Frame Received */ +#define GMAC_ISR_PDRSFR (0x1u << 23) /**< \brief (GMAC_ISR) PDelay Response Frame Received */ +#define GMAC_ISR_PDRQFT (0x1u << 24) /**< \brief (GMAC_ISR) PDelay Request Frame Transmitted */ +#define GMAC_ISR_PDRSFT (0x1u << 25) /**< \brief (GMAC_ISR) PDelay Response Frame Transmitted */ +#define GMAC_ISR_SRI (0x1u << 26) /**< \brief (GMAC_ISR) TSU Seconds Register Increment */ +#define GMAC_ISR_LPI (0x1u << 27) /**< \brief (GMAC_ISR) RX LPI indication */ +#define GMAC_ISR_WOL (0x1u << 28) /**< \brief (GMAC_ISR) Wake On LAN */ +#define GMAC_ISR_TSU (0x1u << 29) /**< \brief (GMAC_ISR) TSU timer comparison interrupt */ +/* -------- GMAC_IER : (GMAC Offset: 0x028) Interrupt Enable Register -------- */ +#define GMAC_IER_MFS (0x1u << 0) /**< \brief (GMAC_IER) Management Frame Sent */ +#define GMAC_IER_RCOMP (0x1u << 1) /**< \brief (GMAC_IER) Receive Complete */ +#define GMAC_IER_RXUBR (0x1u << 2) /**< \brief (GMAC_IER) RX Used Bit Read */ +#define GMAC_IER_TXUBR (0x1u << 3) /**< \brief (GMAC_IER) TX Used Bit Read */ +#define GMAC_IER_TUR (0x1u << 4) /**< \brief (GMAC_IER) Transmit Underrun */ +#define GMAC_IER_RLEX (0x1u << 5) /**< \brief (GMAC_IER) Retry Limit Exceeded or Late Collision */ +#define GMAC_IER_TFC (0x1u << 6) /**< \brief (GMAC_IER) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IER_TCOMP (0x1u << 7) /**< \brief (GMAC_IER) Transmit Complete */ +#define GMAC_IER_ROVR (0x1u << 10) /**< \brief (GMAC_IER) Receive Overrun */ +#define GMAC_IER_HRESP (0x1u << 11) /**< \brief (GMAC_IER) HRESP Not OK */ +#define GMAC_IER_PFNZ (0x1u << 12) /**< \brief (GMAC_IER) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IER_PTZ (0x1u << 13) /**< \brief (GMAC_IER) Pause Time Zero */ +#define GMAC_IER_PFTR (0x1u << 14) /**< \brief (GMAC_IER) Pause Frame Transmitted */ +#define GMAC_IER_EXINT (0x1u << 15) /**< \brief (GMAC_IER) External Interrupt */ +#define GMAC_IER_DRQFR (0x1u << 18) /**< \brief (GMAC_IER) PTP Delay Request Frame Received */ +#define GMAC_IER_SFR (0x1u << 19) /**< \brief (GMAC_IER) PTP Sync Frame Received */ +#define GMAC_IER_DRQFT (0x1u << 20) /**< \brief (GMAC_IER) PTP Delay Request Frame Transmitted */ +#define GMAC_IER_SFT (0x1u << 21) /**< \brief (GMAC_IER) PTP Sync Frame Transmitted */ +#define GMAC_IER_PDRQFR (0x1u << 22) /**< \brief (GMAC_IER) PDelay Request Frame Received */ +#define GMAC_IER_PDRSFR (0x1u << 23) /**< \brief (GMAC_IER) PDelay Response Frame Received */ +#define GMAC_IER_PDRQFT (0x1u << 24) /**< \brief (GMAC_IER) PDelay Request Frame Transmitted */ +#define GMAC_IER_PDRSFT (0x1u << 25) /**< \brief (GMAC_IER) PDelay Response Frame Transmitted */ +#define GMAC_IER_SRI (0x1u << 26) /**< \brief (GMAC_IER) TSU Seconds Register Increment */ +#define GMAC_IER_LPI (0x1u << 27) /**< \brief (GMAC_IER) RX LPI indication */ +#define GMAC_IER_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +#define GMAC_IER_TSU (0x1u << 29) /**< \brief (GMAC_IER) TSU timer comparison interrupt*/ +/* -------- GMAC_IDR : (GMAC Offset: 0x02C) Interrupt Disable Register -------- */ +#define GMAC_IDR_MFS (0x1u << 0) /**< \brief (GMAC_IDR) Management Frame Sent */ +#define GMAC_IDR_RCOMP (0x1u << 1) /**< \brief (GMAC_IDR) Receive Complete */ +#define GMAC_IDR_RXUBR (0x1u << 2) /**< \brief (GMAC_IDR) RX Used Bit Read */ +#define GMAC_IDR_TXUBR (0x1u << 3) /**< \brief (GMAC_IDR) TX Used Bit Read */ +#define GMAC_IDR_TUR (0x1u << 4) /**< \brief (GMAC_IDR) Transmit Underrun */ +#define GMAC_IDR_RLEX (0x1u << 5) /**< \brief (GMAC_IDR) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDR_TFC (0x1u << 6) /**< \brief (GMAC_IDR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDR_TCOMP (0x1u << 7) /**< \brief (GMAC_IDR) Transmit Complete */ +#define GMAC_IDR_ROVR (0x1u << 10) /**< \brief (GMAC_IDR) Receive Overrun */ +#define GMAC_IDR_HRESP (0x1u << 11) /**< \brief (GMAC_IDR) HRESP Not OK */ +#define GMAC_IDR_PFNZ (0x1u << 12) /**< \brief (GMAC_IDR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IDR_PTZ (0x1u << 13) /**< \brief (GMAC_IDR) Pause Time Zero */ +#define GMAC_IDR_PFTR (0x1u << 14) /**< \brief (GMAC_IDR) Pause Frame Transmitted */ +#define GMAC_IDR_EXINT (0x1u << 15) /**< \brief (GMAC_IDR) External Interrupt */ +#define GMAC_IDR_DRQFR (0x1u << 18) /**< \brief (GMAC_IDR) PTP Delay Request Frame Received */ +#define GMAC_IDR_SFR (0x1u << 19) /**< \brief (GMAC_IDR) PTP Sync Frame Received */ +#define GMAC_IDR_DRQFT (0x1u << 20) /**< \brief (GMAC_IDR) PTP Delay Request Frame Transmitted */ +#define GMAC_IDR_SFT (0x1u << 21) /**< \brief (GMAC_IDR) PTP Sync Frame Transmitted */ +#define GMAC_IDR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IDR) PDelay Request Frame Received */ +#define GMAC_IDR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IDR) PDelay Response Frame Received */ +#define GMAC_IDR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IDR) PDelay Request Frame Transmitted */ +#define GMAC_IDR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IDR) PDelay Response Frame Transmitted */ +#define GMAC_IDR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IDR_LPI (0x1u << 27) /**< \brief (GMAC_IER) RX LPI indication */ +#define GMAC_IDR_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +#define GMAC_IDR_TSU (0x1u << 29) /**< \brief (GMAC_IER) TSU timer comparison interrupt*/ +/* -------- GMAC_IMR : (GMAC Offset: 0x030) Interrupt Mask Register -------- */ +#define GMAC_IMR_MFS (0x1u << 0) /**< \brief (GMAC_IMR) Management Frame Sent */ +#define GMAC_IMR_RCOMP (0x1u << 1) /**< \brief (GMAC_IMR) Receive Complete */ +#define GMAC_IMR_RXUBR (0x1u << 2) /**< \brief (GMAC_IMR) RX Used Bit Read */ +#define GMAC_IMR_TXUBR (0x1u << 3) /**< \brief (GMAC_IMR) TX Used Bit Read */ +#define GMAC_IMR_TUR (0x1u << 4) /**< \brief (GMAC_IMR) Transmit Underrun */ +#define GMAC_IMR_RLEX (0x1u << 5) /**< \brief (GMAC_IMR) Retry Limit Exceeded */ +#define GMAC_IMR_TFC (0x1u << 6) /**< \brief (GMAC_IMR) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IMR_TCOMP (0x1u << 7) /**< \brief (GMAC_IMR) Transmit Complete */ +#define GMAC_IMR_ROVR (0x1u << 10) /**< \brief (GMAC_IMR) Receive Overrun */ +#define GMAC_IMR_HRESP (0x1u << 11) /**< \brief (GMAC_IMR) HRESP Not OK */ +#define GMAC_IMR_PFNZ (0x1u << 12) /**< \brief (GMAC_IMR) Pause Frame with Non-zero Pause Quantum Received */ +#define GMAC_IMR_PTZ (0x1u << 13) /**< \brief (GMAC_IMR) Pause Time Zero */ +#define GMAC_IMR_PFTR (0x1u << 14) /**< \brief (GMAC_IMR) Pause Frame Transmitted */ +#define GMAC_IMR_EXINT (0x1u << 15) /**< \brief (GMAC_IMR) External Interrupt */ +#define GMAC_IMR_DRQFR (0x1u << 18) /**< \brief (GMAC_IMR) PTP Delay Request Frame Received */ +#define GMAC_IMR_SFR (0x1u << 19) /**< \brief (GMAC_IMR) PTP Sync Frame Received */ +#define GMAC_IMR_DRQFT (0x1u << 20) /**< \brief (GMAC_IMR) PTP Delay Request Frame Transmitted */ +#define GMAC_IMR_SFT (0x1u << 21) /**< \brief (GMAC_IMR) PTP Sync Frame Transmitted */ +#define GMAC_IMR_PDRQFR (0x1u << 22) /**< \brief (GMAC_IMR) PDelay Request Frame Received */ +#define GMAC_IMR_PDRSFR (0x1u << 23) /**< \brief (GMAC_IMR) PDelay Response Frame Received */ +#define GMAC_IMR_PDRQFT (0x1u << 24) /**< \brief (GMAC_IMR) PDelay Request Frame Transmitted */ +#define GMAC_IMR_PDRSFT (0x1u << 25) /**< \brief (GMAC_IMR) PDelay Response Frame Transmitted */ +#define GMAC_IMR_SRI (0x1u << 26) /**< \brief (GMAC_IDR) TSU Seconds Register Increment */ +#define GMAC_IMR_LPI (0x1u << 27) /**< \brief (GMAC_IER) RX LPI indication */ +#define GMAC_IMR_WOL (0x1u << 28) /**< \brief (GMAC_IER) Wake On LAN */ +#define GMAC_IMR_TSU (0x1u << 29) /**< \brief (GMAC_IER) TSU timer comparison interrupt*/ +/* -------- GMAC_MAN : (GMAC Offset: 0x034) PHY Maintenance Register -------- */ +#define GMAC_MAN_DATA_Pos 0 +#define GMAC_MAN_DATA_Msk (0xffffu << GMAC_MAN_DATA_Pos) /**< \brief (GMAC_MAN) PHY Data */ +#define GMAC_MAN_DATA(value) ((GMAC_MAN_DATA_Msk & ((value) << GMAC_MAN_DATA_Pos))) +#define GMAC_MAN_WTN_Pos 16 +#define GMAC_MAN_WTN_Msk (0x3u << GMAC_MAN_WTN_Pos) /**< \brief (GMAC_MAN) Write Ten */ +#define GMAC_MAN_WTN(value) ((GMAC_MAN_WTN_Msk & ((value) << GMAC_MAN_WTN_Pos))) +#define GMAC_MAN_REGA_Pos 18 +#define GMAC_MAN_REGA_Msk (0x1fu << GMAC_MAN_REGA_Pos) /**< \brief (GMAC_MAN) Register Address */ +#define GMAC_MAN_REGA(value) ((GMAC_MAN_REGA_Msk & ((value) << GMAC_MAN_REGA_Pos))) +#define GMAC_MAN_PHYA_Pos 23 +#define GMAC_MAN_PHYA_Msk (0x1fu << GMAC_MAN_PHYA_Pos) /**< \brief (GMAC_MAN) PHY Address */ +#define GMAC_MAN_PHYA(value) ((GMAC_MAN_PHYA_Msk & ((value) << GMAC_MAN_PHYA_Pos))) +#define GMAC_MAN_OP_Pos 28 +#define GMAC_MAN_OP_Msk (0x3u << GMAC_MAN_OP_Pos) /**< \brief (GMAC_MAN) Operation */ +#define GMAC_MAN_OP(value) ((GMAC_MAN_OP_Msk & ((value) << GMAC_MAN_OP_Pos))) +#define GMAC_MAN_CLTTO (0x1u << 30) /**< \brief (GMAC_MAN) Clause 22 Operation */ +#define GMAC_MAN_WZO (0x1u << 31) /**< \brief (GMAC_MAN) Write ZERO */ +/* -------- GMAC_RPQ : (GMAC Offset: 0x038) Received Pause Quantum Register -------- */ +#define GMAC_RPQ_RPQ_Pos 0 +#define GMAC_RPQ_RPQ_Msk (0xffffu << GMAC_RPQ_RPQ_Pos) /**< \brief (GMAC_RPQ) Received Pause Quantum */ +/* -------- GMAC_TPQ : (GMAC Offset: 0x03C) Transmit Pause Quantum Register -------- */ +#define GMAC_TPQ_TPQ_Pos 0 +#define GMAC_TPQ_TPQ_Msk (0xffffu << GMAC_TPQ_TPQ_Pos) /**< \brief (GMAC_TPQ) Transmit Pause Quantum */ +#define GMAC_TPQ_TPQ(value) ((GMAC_TPQ_TPQ_Msk & ((value) << GMAC_TPQ_TPQ_Pos))) +/* -------- GMAC_TPSF : (GMAC Offset: 0x040) TX Partial Store and Forward Register -------- */ +#define GMAC_TPSF_TPB1ADR_Pos 0 +#define GMAC_TPSF_TPB1ADR_Msk (0xfffu << GMAC_TPSF_TPB1ADR_Pos) /**< \brief (GMAC_TPSF) Transmit Partial Store and Forward Address */ +#define GMAC_TPSF_TPB1ADR(value) ((GMAC_TPSF_TPB1ADR_Msk & ((value) << GMAC_TPSF_TPB1ADR_Pos))) +#define GMAC_TPSF_ENTXP (0x1u << 31) /**< \brief (GMAC_TPSF) Enable TX Partial Store and Forward Operation */ +/* -------- GMAC_RPSF : (GMAC Offset: 0x044) RX Partial Store and Forward Register -------- */ +#define GMAC_RPSF_RPB1ADR_Pos 0 +#define GMAC_RPSF_RPB1ADR_Msk (0xfffu << GMAC_RPSF_RPB1ADR_Pos) /**< \brief (GMAC_RPSF) Receive Partial Store and Forward Address */ +#define GMAC_RPSF_RPB1ADR(value) ((GMAC_RPSF_RPB1ADR_Msk & ((value) << GMAC_RPSF_RPB1ADR_Pos))) +#define GMAC_RPSF_ENRXP (0x1u << 31) /**< \brief (GMAC_RPSF) Enable RX Partial Store and Forward Operation */ +/* -------- GMAC_RJFML : (GMAC Offset: 0x048) RX Jumbo Frame Max Length Register -------- */ +#define GMAC_RJFML_FML_Pos 0 +#define GMAC_RJFML_FML_Msk (0x3fffu << GMAC_RJFML_FML_Pos) /**< \brief (GMAC_RJFML) Frame Max Length */ +#define GMAC_RJFML_FML(value) ((GMAC_RJFML_FML_Msk & ((value) << GMAC_RJFML_FML_Pos))) +/* -------- GMAC_HRB : (GMAC Offset: 0x080) Hash Register Bottom -------- */ +#define GMAC_HRB_ADDR_Pos 0 +#define GMAC_HRB_ADDR_Msk (0xffffffffu << GMAC_HRB_ADDR_Pos) /**< \brief (GMAC_HRB) Hash Address */ +#define GMAC_HRB_ADDR(value) ((GMAC_HRB_ADDR_Msk & ((value) << GMAC_HRB_ADDR_Pos))) +/* -------- GMAC_HRT : (GMAC Offset: 0x084) Hash Register Top -------- */ +#define GMAC_HRT_ADDR_Pos 0 +#define GMAC_HRT_ADDR_Msk (0xffffffffu << GMAC_HRT_ADDR_Pos) /**< \brief (GMAC_HRT) Hash Address */ +#define GMAC_HRT_ADDR(value) ((GMAC_HRT_ADDR_Msk & ((value) << GMAC_HRT_ADDR_Pos))) +/* -------- GMAC_SAB : (GMAC Offset: N/A) Specific Address 1 Bottom Register -------- */ +#define GMAC_SAB_ADDR_Pos 0 +#define GMAC_SAB_ADDR_Msk (0xffffffffu << GMAC_SAB_ADDR_Pos) /**< \brief (GMAC_SAB) Specific Address 1 */ +#define GMAC_SAB_ADDR(value) ((GMAC_SAB_ADDR_Msk & ((value) << GMAC_SAB_ADDR_Pos))) +/* -------- GMAC_SAT : (GMAC Offset: N/A) Specific Address 1 Top Register -------- */ +#define GMAC_SAT_ADDR_Pos 0 +#define GMAC_SAT_ADDR_Msk (0xffffu << GMAC_SAT_ADDR_Pos) /**< \brief (GMAC_SAT) Specific Address 1 */ +#define GMAC_SAT_ADDR(value) ((GMAC_SAT_ADDR_Msk & ((value) << GMAC_SAT_ADDR_Pos))) +/* -------- GMAC_TIDM1 : (GMAC Offset: 0x0A8) Type ID Match 1 Register -------- */ +#define GMAC_TIDM1_TID_Pos 0 +#define GMAC_TIDM1_TID_Msk (0xffffu << GMAC_TIDM1_TID_Pos) /**< \brief (GMAC_TIDM1) Type ID Match 1 */ +#define GMAC_TIDM1_TID(value) ((GMAC_TIDM1_TID_Msk & ((value) << GMAC_TIDM1_TID_Pos))) +#define GMAC_TIDM1_ENID1 (0x1u << 31) /**< \brief (GMAC_TIDM1) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM2 : (GMAC Offset: 0x0AC) Type ID Match 2 Register -------- */ +#define GMAC_TIDM2_TID_Pos 0 +#define GMAC_TIDM2_TID_Msk (0xffffu << GMAC_TIDM2_TID_Pos) /**< \brief (GMAC_TIDM2) Type ID Match 2 */ +#define GMAC_TIDM2_TID(value) ((GMAC_TIDM2_TID_Msk & ((value) << GMAC_TIDM2_TID_Pos))) +#define GMAC_TIDM2_ENID2 (0x1u << 31) /**< \brief (GMAC_TIDM2) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM3 : (GMAC Offset: 0x0B0) Type ID Match 3 Register -------- */ +#define GMAC_TIDM3_TID_Pos 0 +#define GMAC_TIDM3_TID_Msk (0xffffu << GMAC_TIDM3_TID_Pos) /**< \brief (GMAC_TIDM3) Type ID Match 3 */ +#define GMAC_TIDM3_TID(value) ((GMAC_TIDM3_TID_Msk & ((value) << GMAC_TIDM3_TID_Pos))) +#define GMAC_TIDM3_ENID3 (0x1u << 31) /**< \brief (GMAC_TIDM3) Enable Copying of TID Matched Frames */ +/* -------- GMAC_TIDM4 : (GMAC Offset: 0x0B4) Type ID Match 4 Register -------- */ +#define GMAC_TIDM4_TID_Pos 0 +#define GMAC_TIDM4_TID_Msk (0xffffu << GMAC_TIDM4_TID_Pos) /**< \brief (GMAC_TIDM4) Type ID Match 4 */ +#define GMAC_TIDM4_TID(value) ((GMAC_TIDM4_TID_Msk & ((value) << GMAC_TIDM4_TID_Pos))) +#define GMAC_TIDM4_ENID4 (0x1u << 31) /**< \brief (GMAC_TIDM4) Enable Copying of TID Matched Frames */ +/* -------- GMAC_WOL : (GMAC Offset: 0x0B8) Wake on LAN Register -------- */ +#define GMAC_WOL_IP_Pos 0 +#define GMAC_WOL_IP_Msk (0xffffu << GMAC_WOL_IP_Pos) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_IP(value) ((GMAC_WOL_IP_Msk & ((value) << GMAC_WOL_IP_Pos))) +#define GMAC_WOL_MAG (0x1u << 16) /**< \brief (GMAC_WOL) Magic Packet Event Enable */ +#define GMAC_WOL_ARP (0x1u << 17) /**< \brief (GMAC_WOL) ARP Request IP Address */ +#define GMAC_WOL_SA1 (0x1u << 18) /**< \brief (GMAC_WOL) Specific Address Register 1 Event Enable */ +#define GMAC_WOL_MTI (0x1u << 19) /**< \brief (GMAC_WOL) Multicast Hash Event Enable */ +/* -------- GMAC_IPGS : (GMAC Offset: 0x0BC) IPG Stretch Register -------- */ +#define GMAC_IPGS_FL_Pos 0 +#define GMAC_IPGS_FL_Msk (0xffffu << GMAC_IPGS_FL_Pos) /**< \brief (GMAC_IPGS) Frame Length */ +#define GMAC_IPGS_FL(value) ((GMAC_IPGS_FL_Msk & ((value) << GMAC_IPGS_FL_Pos))) +/* -------- GMAC_SVLAN : (GMAC Offset: 0x0C0) Stacked VLAN Register -------- */ +#define GMAC_SVLAN_VLAN_TYPE_Pos 0 +#define GMAC_SVLAN_VLAN_TYPE_Msk (0xffffu << GMAC_SVLAN_VLAN_TYPE_Pos) /**< \brief (GMAC_SVLAN) User Defined VLAN_TYPE Field */ +#define GMAC_SVLAN_VLAN_TYPE(value) ((GMAC_SVLAN_VLAN_TYPE_Msk & ((value) << GMAC_SVLAN_VLAN_TYPE_Pos))) +#define GMAC_SVLAN_ESVLAN (0x1u << 31) /**< \brief (GMAC_SVLAN) Enable Stacked VLAN Processing Mode */ +/* -------- GMAC_TPFCP : (GMAC Offset: 0x0C4) Transmit PFC Pause Register -------- */ +#define GMAC_TPFCP_PEV_Pos 0 +#define GMAC_TPFCP_PEV_Msk (0xffu << GMAC_TPFCP_PEV_Pos) /**< \brief (GMAC_TPFCP) Priority Enable Vector */ +#define GMAC_TPFCP_PEV(value) ((GMAC_TPFCP_PEV_Msk & ((value) << GMAC_TPFCP_PEV_Pos))) +#define GMAC_TPFCP_PQ_Pos 8 +#define GMAC_TPFCP_PQ_Msk (0xffu << GMAC_TPFCP_PQ_Pos) /**< \brief (GMAC_TPFCP) Pause Quantum */ +#define GMAC_TPFCP_PQ(value) ((GMAC_TPFCP_PQ_Msk & ((value) << GMAC_TPFCP_PQ_Pos))) +/* -------- GMAC_SAMB1 : (GMAC Offset: 0x0C8) Specific Address 1 Mask Bottom Register -------- */ +#define GMAC_SAMB1_ADDR_Pos 0 +#define GMAC_SAMB1_ADDR_Msk (0xffffffffu << GMAC_SAMB1_ADDR_Pos) /**< \brief (GMAC_SAMB1) Specific Address 1 Mask */ +#define GMAC_SAMB1_ADDR(value) ((GMAC_SAMB1_ADDR_Msk & ((value) << GMAC_SAMB1_ADDR_Pos))) +/* -------- GMAC_SAMT1 : (GMAC Offset: 0x0CC) Specific Address 1 Mask Top Register -------- */ +#define GMAC_SAMT1_ADDR_Pos 0 +#define GMAC_SAMT1_ADDR_Msk (0xffffu << GMAC_SAMT1_ADDR_Pos) /**< \brief (GMAC_SAMT1) Specific Address 1 Mask */ +#define GMAC_SAMT1_ADDR(value) ((GMAC_SAMT1_ADDR_Msk & ((value) << GMAC_SAMT1_ADDR_Pos))) +/* -------- GMAC_NSC : (GMAC Offset: 0x0DC) 1588 Timer Nanosecond Comparison Register -------- */ +#define GMAC_NSC_NANOSEC_Pos 0 +#define GMAC_NSC_NANOSEC_Msk (0x3fffffu << GMAC_NSC_NANOSEC_Pos) /**< \brief (GMAC_NSC) 1588 Timer Nanosecond Comparison Value */ +#define GMAC_NSC_NANOSEC(value) ((GMAC_NSC_NANOSEC_Msk & ((value) << GMAC_NSC_NANOSEC_Pos))) +/* -------- GMAC_SCL : (GMAC Offset: 0x0E0) 1588 Timer Second Comparison Low Register -------- */ +#define GMAC_SCL_SEC_Pos 0 +#define GMAC_SCL_SEC_Msk (0xffffffffu << GMAC_SCL_SEC_Pos) /**< \brief (GMAC_SCL) 1588 Timer Second Comparison Value */ +#define GMAC_SCL_SEC(value) ((GMAC_SCL_SEC_Msk & ((value) << GMAC_SCL_SEC_Pos))) +/* -------- GMAC_SCH : (GMAC Offset: 0x0E4) 1588 Timer Second Comparison High Register -------- */ +#define GMAC_SCH_SEC_Pos 0 +#define GMAC_SCH_SEC_Msk (0xffffu << GMAC_SCH_SEC_Pos) /**< \brief (GMAC_SCH) 1588 Timer Second Comparison Value */ +#define GMAC_SCH_SEC(value) ((GMAC_SCH_SEC_Msk & ((value) << GMAC_SCH_SEC_Pos))) +/* -------- GMAC_EFTSH : (GMAC Offset: 0x0E8) PTP Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_EFTSH_RUD_Pos 0 +#define GMAC_EFTSH_RUD_Msk (0xffffu << GMAC_EFTSH_RUD_Pos) /**< \brief (GMAC_EFTSH) Register Update */ +/* -------- GMAC_EFRSH : (GMAC Offset: 0x0EC) PTP Event Frame Received Seconds High Register -------- */ +#define GMAC_EFRSH_RUD_Pos 0 +#define GMAC_EFRSH_RUD_Msk (0xffffu << GMAC_EFRSH_RUD_Pos) /**< \brief (GMAC_EFRSH) Register Update */ +/* -------- GMAC_PEFTSH : (GMAC Offset: 0x0F0) PTP Peer Event Frame Transmitted Seconds High Register -------- */ +#define GMAC_PEFTSH_RUD_Pos 0 +#define GMAC_PEFTSH_RUD_Msk (0xffffu << GMAC_PEFTSH_RUD_Pos) /**< \brief (GMAC_PEFTSH) Register Update */ +/* -------- GMAC_PEFRSH : (GMAC Offset: 0x0F4) PTP Peer Event Frame Received Seconds High Register -------- */ +#define GMAC_PEFRSH_RUD_Pos 0 +#define GMAC_PEFRSH_RUD_Msk (0xffffu << GMAC_PEFRSH_RUD_Pos) /**< \brief (GMAC_PEFRSH) Register Update */ +/* -------- GMAC_OTLO : (GMAC Offset: 0x100) Octets Transmitted Low Register -------- */ +#define GMAC_OTLO_TXO_Pos 0 +#define GMAC_OTLO_TXO_Msk (0xffffffffu << GMAC_OTLO_TXO_Pos) /**< \brief (GMAC_OTLO) Transmitted Octets */ +/* -------- GMAC_OTHI : (GMAC Offset: 0x104) Octets Transmitted High Register -------- */ +#define GMAC_OTHI_TXO_Pos 0 +#define GMAC_OTHI_TXO_Msk (0xffffu << GMAC_OTHI_TXO_Pos) /**< \brief (GMAC_OTHI) Transmitted Octets */ +/* -------- GMAC_FT : (GMAC Offset: 0x108) Frames Transmitted Register -------- */ +#define GMAC_FT_FTX_Pos 0 +#define GMAC_FT_FTX_Msk (0xffffffffu << GMAC_FT_FTX_Pos) /**< \brief (GMAC_FT) Frames Transmitted without Error */ +/* -------- GMAC_BCFT : (GMAC Offset: 0x10C) Broadcast Frames Transmitted Register -------- */ +#define GMAC_BCFT_BFTX_Pos 0 +#define GMAC_BCFT_BFTX_Msk (0xffffffffu << GMAC_BCFT_BFTX_Pos) /**< \brief (GMAC_BCFT) Broadcast Frames Transmitted without Error */ +/* -------- GMAC_MFT : (GMAC Offset: 0x110) Multicast Frames Transmitted Register -------- */ +#define GMAC_MFT_MFTX_Pos 0 +#define GMAC_MFT_MFTX_Msk (0xffffffffu << GMAC_MFT_MFTX_Pos) /**< \brief (GMAC_MFT) Multicast Frames Transmitted without Error */ +/* -------- GMAC_PFT : (GMAC Offset: 0x114) Pause Frames Transmitted Register -------- */ +#define GMAC_PFT_PFTX_Pos 0 +#define GMAC_PFT_PFTX_Msk (0xffffu << GMAC_PFT_PFTX_Pos) /**< \brief (GMAC_PFT) Pause Frames Transmitted Register */ +/* -------- GMAC_BFT64 : (GMAC Offset: 0x118) 64 Byte Frames Transmitted Register -------- */ +#define GMAC_BFT64_NFTX_Pos 0 +#define GMAC_BFT64_NFTX_Msk (0xffffffffu << GMAC_BFT64_NFTX_Pos) /**< \brief (GMAC_BFT64) 64 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT127 : (GMAC Offset: 0x11C) 65 to 127 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT127_NFTX_Pos 0 +#define GMAC_TBFT127_NFTX_Msk (0xffffffffu << GMAC_TBFT127_NFTX_Pos) /**< \brief (GMAC_TBFT127) 65 to 127 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT255 : (GMAC Offset: 0x120) 128 to 255 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT255_NFTX_Pos 0 +#define GMAC_TBFT255_NFTX_Msk (0xffffffffu << GMAC_TBFT255_NFTX_Pos) /**< \brief (GMAC_TBFT255) 128 to 255 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT511 : (GMAC Offset: 0x124) 256 to 511 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT511_NFTX_Pos 0 +#define GMAC_TBFT511_NFTX_Msk (0xffffffffu << GMAC_TBFT511_NFTX_Pos) /**< \brief (GMAC_TBFT511) 256 to 511 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1023 : (GMAC Offset: 0x128) 512 to 1023 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1023_NFTX_Pos 0 +#define GMAC_TBFT1023_NFTX_Msk (0xffffffffu << GMAC_TBFT1023_NFTX_Pos) /**< \brief (GMAC_TBFT1023) 512 to 1023 Byte Frames Transmitted without Error */ +/* -------- GMAC_TBFT1518 : (GMAC Offset: 0x12C) 1024 to 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_TBFT1518_NFTX_Pos 0 +#define GMAC_TBFT1518_NFTX_Msk (0xffffffffu << GMAC_TBFT1518_NFTX_Pos) /**< \brief (GMAC_TBFT1518) 1024 to 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_GTBFT1518 : (GMAC Offset: 0x130) Greater Than 1518 Byte Frames Transmitted Register -------- */ +#define GMAC_GTBFT1518_NFTX_Pos 0 +#define GMAC_GTBFT1518_NFTX_Msk (0xffffffffu << GMAC_GTBFT1518_NFTX_Pos) /**< \brief (GMAC_GTBFT1518) Greater than 1518 Byte Frames Transmitted without Error */ +/* -------- GMAC_TUR : (GMAC Offset: 0x134) Transmit Underruns Register -------- */ +#define GMAC_TUR_TXUNR_Pos 0 +#define GMAC_TUR_TXUNR_Msk (0x3ffu << GMAC_TUR_TXUNR_Pos) /**< \brief (GMAC_TUR) Transmit Underruns */ +/* -------- GMAC_SCF : (GMAC Offset: 0x138) Single Collision Frames Register -------- */ +#define GMAC_SCF_SCOL_Pos 0 +#define GMAC_SCF_SCOL_Msk (0x3ffffu << GMAC_SCF_SCOL_Pos) /**< \brief (GMAC_SCF) Single Collision */ +/* -------- GMAC_MCF : (GMAC Offset: 0x13C) Multiple Collision Frames Register -------- */ +#define GMAC_MCF_MCOL_Pos 0 +#define GMAC_MCF_MCOL_Msk (0x3ffffu << GMAC_MCF_MCOL_Pos) /**< \brief (GMAC_MCF) Multiple Collision */ +/* -------- GMAC_EC : (GMAC Offset: 0x140) Excessive Collisions Register -------- */ +#define GMAC_EC_XCOL_Pos 0 +#define GMAC_EC_XCOL_Msk (0x3ffu << GMAC_EC_XCOL_Pos) /**< \brief (GMAC_EC) Excessive Collisions */ +/* -------- GMAC_LC : (GMAC Offset: 0x144) Late Collisions Register -------- */ +#define GMAC_LC_LCOL_Pos 0 +#define GMAC_LC_LCOL_Msk (0x3ffu << GMAC_LC_LCOL_Pos) /**< \brief (GMAC_LC) Late Collisions */ +/* -------- GMAC_DTF : (GMAC Offset: 0x148) Deferred Transmission Frames Register -------- */ +#define GMAC_DTF_DEFT_Pos 0 +#define GMAC_DTF_DEFT_Msk (0x3ffffu << GMAC_DTF_DEFT_Pos) /**< \brief (GMAC_DTF) Deferred Transmission */ +/* -------- GMAC_CSE : (GMAC Offset: 0x14C) Carrier Sense Errors Register Register -------- */ +#define GMAC_CSE_CSR_Pos 0 +#define GMAC_CSE_CSR_Msk (0x3ffu << GMAC_CSE_CSR_Pos) /**< \brief (GMAC_CSE) Carrier Sense Error */ +/* -------- GMAC_ORLO : (GMAC Offset: 0x150) Octets Received Low Received Register -------- */ +#define GMAC_ORLO_RXO_Pos 0 +#define GMAC_ORLO_RXO_Msk (0xffffffffu << GMAC_ORLO_RXO_Pos) /**< \brief (GMAC_ORLO) Received Octets */ +/* -------- GMAC_ORHI : (GMAC Offset: 0x154) Octets Received High Received Register -------- */ +#define GMAC_ORHI_RXO_Pos 0 +#define GMAC_ORHI_RXO_Msk (0xffffu << GMAC_ORHI_RXO_Pos) /**< \brief (GMAC_ORHI) Received Octets */ +/* -------- GMAC_FR : (GMAC Offset: 0x158) Frames Received Register -------- */ +#define GMAC_FR_FRX_Pos 0 +#define GMAC_FR_FRX_Msk (0xffffffffu << GMAC_FR_FRX_Pos) /**< \brief (GMAC_FR) Frames Received without Error */ +/* -------- GMAC_BCFR : (GMAC Offset: 0x15C) Broadcast Frames Received Register -------- */ +#define GMAC_BCFR_BFRX_Pos 0 +#define GMAC_BCFR_BFRX_Msk (0xffffffffu << GMAC_BCFR_BFRX_Pos) /**< \brief (GMAC_BCFR) Broadcast Frames Received without Error */ +/* -------- GMAC_MFR : (GMAC Offset: 0x160) Multicast Frames Received Register -------- */ +#define GMAC_MFR_MFRX_Pos 0 +#define GMAC_MFR_MFRX_Msk (0xffffffffu << GMAC_MFR_MFRX_Pos) /**< \brief (GMAC_MFR) Multicast Frames Received without Error */ +/* -------- GMAC_PFR : (GMAC Offset: 0x164) Pause Frames Received Register -------- */ +#define GMAC_PFR_PFRX_Pos 0 +#define GMAC_PFR_PFRX_Msk (0xffffu << GMAC_PFR_PFRX_Pos) /**< \brief (GMAC_PFR) Pause Frames Received Register */ +/* -------- GMAC_BFR64 : (GMAC Offset: 0x168) 64 Byte Frames Received Register -------- */ +#define GMAC_BFR64_NFRX_Pos 0 +#define GMAC_BFR64_NFRX_Msk (0xffffffffu << GMAC_BFR64_NFRX_Pos) /**< \brief (GMAC_BFR64) 64 Byte Frames Received without Error */ +/* -------- GMAC_TBFR127 : (GMAC Offset: 0x16C) 65 to 127 Byte Frames Received Register -------- */ +#define GMAC_TBFR127_NFRX_Pos 0 +#define GMAC_TBFR127_NFRX_Msk (0xffffffffu << GMAC_TBFR127_NFRX_Pos) /**< \brief (GMAC_TBFR127) 65 to 127 Byte Frames Received without Error */ +/* -------- GMAC_TBFR255 : (GMAC Offset: 0x170) 128 to 255 Byte Frames Received Register -------- */ +#define GMAC_TBFR255_NFRX_Pos 0 +#define GMAC_TBFR255_NFRX_Msk (0xffffffffu << GMAC_TBFR255_NFRX_Pos) /**< \brief (GMAC_TBFR255) 128 to 255 Byte Frames Received without Error */ +/* -------- GMAC_TBFR511 : (GMAC Offset: 0x174) 256 to 511 Byte Frames Received Register -------- */ +#define GMAC_TBFR511_NFRX_Pos 0 +#define GMAC_TBFR511_NFRX_Msk (0xffffffffu << GMAC_TBFR511_NFRX_Pos) /**< \brief (GMAC_TBFR511) 256 to 511 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1023 : (GMAC Offset: 0x178) 512 to 1023 Byte Frames Received Register -------- */ +#define GMAC_TBFR1023_NFRX_Pos 0 +#define GMAC_TBFR1023_NFRX_Msk (0xffffffffu << GMAC_TBFR1023_NFRX_Pos) /**< \brief (GMAC_TBFR1023) 512 to 1023 Byte Frames Received without Error */ +/* -------- GMAC_TBFR1518 : (GMAC Offset: 0x17C) 1024 to 1518 Byte Frames Received Register -------- */ +#define GMAC_TBFR1518_NFRX_Pos 0 +#define GMAC_TBFR1518_NFRX_Msk (0xffffffffu << GMAC_TBFR1518_NFRX_Pos) /**< \brief (GMAC_TBFR1518) 1024 to 1518 Byte Frames Received without Error */ +/* -------- GMAC_TMXBFR : (GMAC Offset: 0x180) 1519 to Maximum Byte Frames Received Register -------- */ +#define GMAC_TMXBFR_NFRX_Pos 0 +#define GMAC_TMXBFR_NFRX_Msk (0xffffffffu << GMAC_TMXBFR_NFRX_Pos) /**< \brief (GMAC_TMXBFR) 1519 to Maximum Byte Frames Received without Error */ +/* -------- GMAC_UFR : (GMAC Offset: 0x184) Undersize Frames Received Register -------- */ +#define GMAC_UFR_UFRX_Pos 0 +#define GMAC_UFR_UFRX_Msk (0x3ffu << GMAC_UFR_UFRX_Pos) /**< \brief (GMAC_UFR) Undersize Frames Received */ +/* -------- GMAC_OFR : (GMAC Offset: 0x188) Oversize Frames Received Register -------- */ +#define GMAC_OFR_OFRX_Pos 0 +#define GMAC_OFR_OFRX_Msk (0x3ffu << GMAC_OFR_OFRX_Pos) /**< \brief (GMAC_OFR) Oversized Frames Received */ +/* -------- GMAC_JR : (GMAC Offset: 0x18C) Jabbers Received Register -------- */ +#define GMAC_JR_JRX_Pos 0 +#define GMAC_JR_JRX_Msk (0x3ffu << GMAC_JR_JRX_Pos) /**< \brief (GMAC_JR) Jabbers Received */ +/* -------- GMAC_FCSE : (GMAC Offset: 0x190) Frame Check Sequence Errors Register -------- */ +#define GMAC_FCSE_FCKR_Pos 0 +#define GMAC_FCSE_FCKR_Msk (0x3ffu << GMAC_FCSE_FCKR_Pos) /**< \brief (GMAC_FCSE) Frame Check Sequence Errors */ +/* -------- GMAC_LFFE : (GMAC Offset: 0x194) Length Field Frame Errors Register -------- */ +#define GMAC_LFFE_LFER_Pos 0 +#define GMAC_LFFE_LFER_Msk (0x3ffu << GMAC_LFFE_LFER_Pos) /**< \brief (GMAC_LFFE) Length Field Frame Errors */ +/* -------- GMAC_RSE : (GMAC Offset: 0x198) Receive Symbol Errors Register -------- */ +#define GMAC_RSE_RXSE_Pos 0 +#define GMAC_RSE_RXSE_Msk (0x3ffu << GMAC_RSE_RXSE_Pos) /**< \brief (GMAC_RSE) Receive Symbol Errors */ +/* -------- GMAC_AE : (GMAC Offset: 0x19C) Alignment Errors Register -------- */ +#define GMAC_AE_AER_Pos 0 +#define GMAC_AE_AER_Msk (0x3ffu << GMAC_AE_AER_Pos) /**< \brief (GMAC_AE) Alignment Errors */ +/* -------- GMAC_RRE : (GMAC Offset: 0x1A0) Receive Resource Errors Register -------- */ +#define GMAC_RRE_RXRER_Pos 0 +#define GMAC_RRE_RXRER_Msk (0x3ffffu << GMAC_RRE_RXRER_Pos) /**< \brief (GMAC_RRE) Receive Resource Errors */ +/* -------- GMAC_ROE : (GMAC Offset: 0x1A4) Receive Overrun Register -------- */ +#define GMAC_ROE_RXOVR_Pos 0 +#define GMAC_ROE_RXOVR_Msk (0x3ffu << GMAC_ROE_RXOVR_Pos) /**< \brief (GMAC_ROE) Receive Overruns */ +/* -------- GMAC_IHCE : (GMAC Offset: 0x1A8) IP Header Checksum Errors Register -------- */ +#define GMAC_IHCE_HCKER_Pos 0 +#define GMAC_IHCE_HCKER_Msk (0xffu << GMAC_IHCE_HCKER_Pos) /**< \brief (GMAC_IHCE) IP Header Checksum Errors */ +/* -------- GMAC_TCE : (GMAC Offset: 0x1AC) TCP Checksum Errors Register -------- */ +#define GMAC_TCE_TCKER_Pos 0 +#define GMAC_TCE_TCKER_Msk (0xffu << GMAC_TCE_TCKER_Pos) /**< \brief (GMAC_TCE) TCP Checksum Errors */ +/* -------- GMAC_UCE : (GMAC Offset: 0x1B0) UDP Checksum Errors Register -------- */ +#define GMAC_UCE_UCKER_Pos 0 +#define GMAC_UCE_UCKER_Msk (0xffu << GMAC_UCE_UCKER_Pos) /**< \brief (GMAC_UCE) UDP Checksum Errors */ +/* -------- GMAC_TISUBN : (GMAC Offset: 0x1BC) 1588 Timer Increment Sub-nanoseconds Register -------- */ +#define GMAC_TISUBN_LSBTIR_Pos 0 +#define GMAC_TISUBN_LSBTIR_Msk (0xffffu << GMAC_TISUBN_LSBTIR_Pos) /**< \brief (GMAC_TISUBN) Lower Significant Bits of Timer Increment Register */ +#define GMAC_TISUBN_LSBTIR(value) ((GMAC_TISUBN_LSBTIR_Msk & ((value) << GMAC_TISUBN_LSBTIR_Pos))) +/* -------- GMAC_TSH : (GMAC Offset: 0x1C0) 1588 Timer Seconds High Register -------- */ +#define GMAC_TSH_TCS_Pos 0 +#define GMAC_TSH_TCS_Msk (0xffffu << GMAC_TSH_TCS_Pos) /**< \brief (GMAC_TSH) Timer Count in Seconds */ +#define GMAC_TSH_TCS(value) ((GMAC_TSH_TCS_Msk & ((value) << GMAC_TSH_TCS_Pos))) +/* -------- GMAC_TSL : (GMAC Offset: 0x1D0) 1588 Timer Seconds Low Register -------- */ +#define GMAC_TSL_TCS_Pos 0 +#define GMAC_TSL_TCS_Msk (0xffffffffu << GMAC_TSL_TCS_Pos) /**< \brief (GMAC_TSL) Timer Count in Seconds */ +#define GMAC_TSL_TCS(value) ((GMAC_TSL_TCS_Msk & ((value) << GMAC_TSL_TCS_Pos))) +/* -------- GMAC_TN : (GMAC Offset: 0x1D4) 1588 Timer Nanoseconds Register -------- */ +#define GMAC_TN_TNS_Pos 0 +#define GMAC_TN_TNS_Msk (0x3fffffffu << GMAC_TN_TNS_Pos) /**< \brief (GMAC_TN) Timer Count in Nanoseconds */ +#define GMAC_TN_TNS(value) ((GMAC_TN_TNS_Msk & ((value) << GMAC_TN_TNS_Pos))) +/* -------- GMAC_TA : (GMAC Offset: 0x1D8) 1588 Timer Adjust Register -------- */ +#define GMAC_TA_ITDT_Pos 0 +#define GMAC_TA_ITDT_Msk (0x3fffffffu << GMAC_TA_ITDT_Pos) /**< \brief (GMAC_TA) Increment/Decrement */ +#define GMAC_TA_ITDT(value) ((GMAC_TA_ITDT_Msk & ((value) << GMAC_TA_ITDT_Pos))) +#define GMAC_TA_ADJ (0x1u << 31) /**< \brief (GMAC_TA) Adjust 1588 Timer */ +/* -------- GMAC_TI : (GMAC Offset: 0x1DC) 1588 Timer Increment Register -------- */ +#define GMAC_TI_CNS_Pos 0 +#define GMAC_TI_CNS_Msk (0xffu << GMAC_TI_CNS_Pos) /**< \brief (GMAC_TI) Count Nanoseconds */ +#define GMAC_TI_CNS(value) ((GMAC_TI_CNS_Msk & ((value) << GMAC_TI_CNS_Pos))) +#define GMAC_TI_ACNS_Pos 8 +#define GMAC_TI_ACNS_Msk (0xffu << GMAC_TI_ACNS_Pos) /**< \brief (GMAC_TI) Alternative Count Nanoseconds */ +#define GMAC_TI_ACNS(value) ((GMAC_TI_ACNS_Msk & ((value) << GMAC_TI_ACNS_Pos))) +#define GMAC_TI_NIT_Pos 16 +#define GMAC_TI_NIT_Msk (0xffu << GMAC_TI_NIT_Pos) /**< \brief (GMAC_TI) Number of Increments */ +#define GMAC_TI_NIT(value) ((GMAC_TI_NIT_Msk & ((value) << GMAC_TI_NIT_Pos))) +/* -------- GMAC_EFTSL : (GMAC Offset: 0x1E0) PTP Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_EFTSL_RUD_Pos 0 +#define GMAC_EFTSL_RUD_Msk (0xffffffffu << GMAC_EFTSL_RUD_Pos) /**< \brief (GMAC_EFTSL) Register Update */ +/* -------- GMAC_EFTN : (GMAC Offset: 0x1E4) PTP Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_EFTN_RUD_Pos 0 +#define GMAC_EFTN_RUD_Msk (0x3fffffffu << GMAC_EFTN_RUD_Pos) /**< \brief (GMAC_EFTN) Register Update */ +/* -------- GMAC_EFRSL : (GMAC Offset: 0x1E8) PTP Event Frame Received Seconds Low Register -------- */ +#define GMAC_EFRSL_RUD_Pos 0 +#define GMAC_EFRSL_RUD_Msk (0xffffffffu << GMAC_EFRSL_RUD_Pos) /**< \brief (GMAC_EFRSL) Register Update */ +/* -------- GMAC_EFRN : (GMAC Offset: 0x1EC) PTP Event Frame Received Nanoseconds Register -------- */ +#define GMAC_EFRN_RUD_Pos 0 +#define GMAC_EFRN_RUD_Msk (0x3fffffffu << GMAC_EFRN_RUD_Pos) /**< \brief (GMAC_EFRN) Register Update */ +/* -------- GMAC_PEFTSL : (GMAC Offset: 0x1F0) PTP Peer Event Frame Transmitted Seconds Low Register -------- */ +#define GMAC_PEFTSL_RUD_Pos 0 +#define GMAC_PEFTSL_RUD_Msk (0xffffffffu << GMAC_PEFTSL_RUD_Pos) /**< \brief (GMAC_PEFTSL) Register Update */ +/* -------- GMAC_PEFTN : (GMAC Offset: 0x1F4) PTP Peer Event Frame Transmitted Nanoseconds Register -------- */ +#define GMAC_PEFTN_RUD_Pos 0 +#define GMAC_PEFTN_RUD_Msk (0x3fffffffu << GMAC_PEFTN_RUD_Pos) /**< \brief (GMAC_PEFTN) Register Update */ +/* -------- GMAC_PEFRSL : (GMAC Offset: 0x1F8) PTP Peer Event Frame Received Seconds Low Register -------- */ +#define GMAC_PEFRSL_RUD_Pos 0 +#define GMAC_PEFRSL_RUD_Msk (0xffffffffu << GMAC_PEFRSL_RUD_Pos) /**< \brief (GMAC_PEFRSL) Register Update */ +/* -------- GMAC_PEFRN : (GMAC Offset: 0x1FC) PTP Peer Event Frame Received Nanoseconds Register -------- */ +#define GMAC_PEFRN_RUD_Pos 0 +#define GMAC_PEFRN_RUD_Msk (0x3fffffffu << GMAC_PEFRN_RUD_Pos) /**< \brief (GMAC_PEFRN) Register Update */ +/* -------- GMAC_ISRPQ[3] : (GMAC Offset: 0x400) Interrupt Status Register Priority Queue (index = 1) -------- */ +#define GMAC_ISRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_ISRPQ[3]) Receive Complete */ +#define GMAC_ISRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_ISRPQ[3]) RX Used Bit Read */ +#define GMAC_ISRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_ISRPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_ISRPQ_TFC (0x1u << 6) /**< \brief (GMAC_ISRPQ[3]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_ISRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_ISRPQ[3]) Transmit Complete */ +#define GMAC_ISRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_ISRPQ[3]) Receive Overrun */ +#define GMAC_ISRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_ISRPQ[3]) HRESP Not OK */ +/* -------- GMAC_TBQBAPQ[3] : (GMAC Offset: 0x440) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_TBQBAPQ_TXBQBA_Pos 2 +#define GMAC_TBQBAPQ_TXBQBA_Msk (0x3fu << GMAC_TBQBAPQ_TXBQBA_Pos) /**< \brief (GMAC_TBQBAPQ[3]) Transmit Buffer Queue Base Address */ +#define GMAC_TBQBAPQ_TXBQBA(value) ((GMAC_TBQBAPQ_TXBQBA_Msk & ((value) << GMAC_TBQBAPQ_TXBQBA_Pos))) +/* -------- GMAC_RBQBAPQ[3] : (GMAC Offset: 0x480) Receive Buffer Queue Base Address Register Priority Queue (index = 1) -------- */ +#define GMAC_RBQBAPQ_RXBQBA_Pos 2 +#define GMAC_RBQBAPQ_RXBQBA_Msk (0x3fu << GMAC_RBQBAPQ_RXBQBA_Pos) /**< \brief (GMAC_RBQBAPQ[3]) Receive Buffer Queue Base Address */ +#define GMAC_RBQBAPQ_RXBQBA(value) ((GMAC_RBQBAPQ_RXBQBA_Msk & ((value) << GMAC_RBQBAPQ_RXBQBA_Pos))) +/* -------- GMAC_RBSRPQ[3] : (GMAC Offset: 0x4A0) Receive Buffer Size Register Priority Queue (index = 1) -------- */ +#define GMAC_RBSRPQ_RBS_Pos 0 +#define GMAC_RBSRPQ_RBS_Msk (0xffffu << GMAC_RBSRPQ_RBS_Pos) /**< \brief (GMAC_RBSRPQ[3]) Receive Buffer Size */ +#define GMAC_RBSRPQ_RBS(value) ((GMAC_RBSRPQ_RBS_Msk & ((value) << GMAC_RBSRPQ_RBS_Pos))) +/* -------- GMAC_CBSCR : (GMAC Offset: 0x4BC) Credit-Based Shaping Control Register -------- */ +#define GMAC_CBSCR_QBE (0x1u << 0) /**< \brief (GMAC_CBSCR) Queue B CBS Enable */ +#define GMAC_CBSCR_QAE (0x1u << 1) /**< \brief (GMAC_CBSCR) Queue A CBS Enable */ +/* -------- GMAC_CBSISQA : (GMAC Offset: 0x4C0) Credit-Based Shaping IdleSlope Register for Queue A -------- */ +#define GMAC_CBSISQA_IS_Pos 0 +#define GMAC_CBSISQA_IS_Msk (0xffffffffu << GMAC_CBSISQA_IS_Pos) /**< \brief (GMAC_CBSISQA) IdleSlope */ +#define GMAC_CBSISQA_IS(value) ((GMAC_CBSISQA_IS_Msk & ((value) << GMAC_CBSISQA_IS_Pos))) +/* -------- GMAC_CBSISQB : (GMAC Offset: 0x4C4) Credit-Based Shaping IdleSlope Register for Queue B -------- */ +#define GMAC_CBSISQB_IS_Pos 0 +#define GMAC_CBSISQB_IS_Msk (0xffffffffu << GMAC_CBSISQB_IS_Pos) /**< \brief (GMAC_CBSISQB) IdleSlope */ +#define GMAC_CBSISQB_IS(value) ((GMAC_CBSISQB_IS_Msk & ((value) << GMAC_CBSISQB_IS_Pos))) +/* -------- GMAC_ST1RPQ[4] : (GMAC Offset: 0x500) Screening Type 1 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST1RPQ_QNB_Pos 0 +#define GMAC_ST1RPQ_QNB_Msk (0x7u << GMAC_ST1RPQ_QNB_Pos) /**< \brief (GMAC_ST1RPQ[4]) Queue Number (0-2) */ +#define GMAC_ST1RPQ_QNB(value) ((GMAC_ST1RPQ_QNB_Msk & ((value) << GMAC_ST1RPQ_QNB_Pos))) +#define GMAC_ST1RPQ_DSTCM_Pos 4 +#define GMAC_ST1RPQ_DSTCM_Msk (0xffu << GMAC_ST1RPQ_DSTCM_Pos) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match */ +#define GMAC_ST1RPQ_DSTCM(value) ((GMAC_ST1RPQ_DSTCM_Msk & ((value) << GMAC_ST1RPQ_DSTCM_Pos))) +#define GMAC_ST1RPQ_UDPM_Pos 12 +#define GMAC_ST1RPQ_UDPM_Msk (0xffffu << GMAC_ST1RPQ_UDPM_Pos) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match */ +#define GMAC_ST1RPQ_UDPM(value) ((GMAC_ST1RPQ_UDPM_Msk & ((value) << GMAC_ST1RPQ_UDPM_Pos))) +#define GMAC_ST1RPQ_DSTCE (0x1u << 28) /**< \brief (GMAC_ST1RPQ[4]) Differentiated Services or Traffic Class Match Enable */ +#define GMAC_ST1RPQ_UDPE (0x1u << 29) /**< \brief (GMAC_ST1RPQ[4]) UDP Port Match Enable */ +/* -------- GMAC_ST2RPQ[8] : (GMAC Offset: 0x540) Screening Type 2 Register Priority Queue (index = 0) -------- */ +#define GMAC_ST2RPQ_QNB_Pos 0 +#define GMAC_ST2RPQ_QNB_Msk (0x7u << GMAC_ST2RPQ_QNB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Queue Number (0-2) */ +#define GMAC_ST2RPQ_QNB(value) ((GMAC_ST2RPQ_QNB_Msk & ((value) << GMAC_ST2RPQ_QNB_Pos))) +#define GMAC_ST2RPQ_VLANP_Pos 4 +#define GMAC_ST2RPQ_VLANP_Msk (0x7u << GMAC_ST2RPQ_VLANP_Pos) /**< \brief (GMAC_ST2RPQ[8]) VLAN Priority */ +#define GMAC_ST2RPQ_VLANP(value) ((GMAC_ST2RPQ_VLANP_Msk & ((value) << GMAC_ST2RPQ_VLANP_Pos))) +#define GMAC_ST2RPQ_VLANE (0x1u << 8) /**< \brief (GMAC_ST2RPQ[8]) VLAN Enable */ +#define GMAC_ST2RPQ_I2ETH_Pos 9 +#define GMAC_ST2RPQ_I2ETH_Msk (0x7u << GMAC_ST2RPQ_I2ETH_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 EtherType register x */ +#define GMAC_ST2RPQ_I2ETH(value) ((GMAC_ST2RPQ_I2ETH_Msk & ((value) << GMAC_ST2RPQ_I2ETH_Pos))) +#define GMAC_ST2RPQ_ETHE (0x1u << 12) /**< \brief (GMAC_ST2RPQ[8]) EtherType Enable */ +#define GMAC_ST2RPQ_COMPA_Pos 13 +#define GMAC_ST2RPQ_COMPA_Msk (0x1fu << GMAC_ST2RPQ_COMPA_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPA(value) ((GMAC_ST2RPQ_COMPA_Msk & ((value) << GMAC_ST2RPQ_COMPA_Pos))) +#define GMAC_ST2RPQ_COMPAE (0x1u << 18) /**< \brief (GMAC_ST2RPQ[8]) Compare A Enable */ +#define GMAC_ST2RPQ_COMPB_Pos 19 +#define GMAC_ST2RPQ_COMPB_Msk (0x1fu << GMAC_ST2RPQ_COMPB_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPB(value) ((GMAC_ST2RPQ_COMPB_Msk & ((value) << GMAC_ST2RPQ_COMPB_Pos))) +#define GMAC_ST2RPQ_COMPBE (0x1u << 24) /**< \brief (GMAC_ST2RPQ[8]) Compare B Enable */ +#define GMAC_ST2RPQ_COMPC_Pos 25 +#define GMAC_ST2RPQ_COMPC_Msk (0x1fu << GMAC_ST2RPQ_COMPC_Pos) /**< \brief (GMAC_ST2RPQ[8]) Index of Screening Type 2 Compare Word 0/Word 1 register x */ +#define GMAC_ST2RPQ_COMPC(value) ((GMAC_ST2RPQ_COMPC_Msk & ((value) << GMAC_ST2RPQ_COMPC_Pos))) +#define GMAC_ST2RPQ_COMPCE (0x1u << 30) /**< \brief (GMAC_ST2RPQ[8]) Compare C Enable */ +/* -------- GMAC_IERPQ[3] : (GMAC Offset: 0x600) Interrupt Enable Register Priority Queue (index = 1) -------- */ +#define GMAC_IERPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IERPQ[3]) Receive Complete */ +#define GMAC_IERPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IERPQ[3]) RX Used Bit Read */ +#define GMAC_IERPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IERPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IERPQ_TFC (0x1u << 6) /**< \brief (GMAC_IERPQ[3]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IERPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IERPQ[3]) Transmit Complete */ +#define GMAC_IERPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IERPQ[3]) Receive Overrun */ +#define GMAC_IERPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IERPQ[3]) HRESP Not OK */ +/* -------- GMAC_IDRPQ[3] : (GMAC Offset: 0x620) Interrupt Disable Register Priority Queue (index = 1) -------- */ +#define GMAC_IDRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IDRPQ[3]) Receive Complete */ +#define GMAC_IDRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IDRPQ[3]) RX Used Bit Read */ +#define GMAC_IDRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IDRPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IDRPQ_TFC (0x1u << 6) /**< \brief (GMAC_IDRPQ[3]) Transmit Frame Corruption Due to AHB Error */ +#define GMAC_IDRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IDRPQ[3]) Transmit Complete */ +#define GMAC_IDRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IDRPQ[3]) Receive Overrun */ +#define GMAC_IDRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IDRPQ[3]) HRESP Not OK */ +/* -------- GMAC_IMRPQ[3] : (GMAC Offset: 0x640) Interrupt Mask Register Priority Queue (index = 1) -------- */ +#define GMAC_IMRPQ_RCOMP (0x1u << 1) /**< \brief (GMAC_IMRPQ[3]) Receive Complete */ +#define GMAC_IMRPQ_RXUBR (0x1u << 2) /**< \brief (GMAC_IMRPQ[3]) RX Used Bit Read */ +#define GMAC_IMRPQ_RLEX (0x1u << 5) /**< \brief (GMAC_IMRPQ[3]) Retry Limit Exceeded or Late Collision */ +#define GMAC_IMRPQ_AHB (0x1u << 6) /**< \brief (GMAC_IMRPQ[3]) AHB Error */ +#define GMAC_IMRPQ_TCOMP (0x1u << 7) /**< \brief (GMAC_IMRPQ[3]) Transmit Complete */ +#define GMAC_IMRPQ_ROVR (0x1u << 10) /**< \brief (GMAC_IMRPQ[3]) Receive Overrun */ +#define GMAC_IMRPQ_HRESP (0x1u << 11) /**< \brief (GMAC_IMRPQ[3]) HRESP Not OK */ +/* -------- GMAC_ST2ER[4] : (GMAC Offset: 0x6E0) Screening Type 2 Ethertype Register (index = 0) -------- */ +#define GMAC_ST2ER_COMPVAL_Pos 0 +#define GMAC_ST2ER_COMPVAL_Msk (0xffffu << GMAC_ST2ER_COMPVAL_Pos) /**< \brief (GMAC_ST2ER[4]) Ethertype Compare Value */ +#define GMAC_ST2ER_COMPVAL(value) ((GMAC_ST2ER_COMPVAL_Msk & ((value) << GMAC_ST2ER_COMPVAL_Pos))) + +/* -------- GMAC_ST2COM0[32] : (GMAC Offset: 0x700) Type2 Compare # x, Word 0 -------- */ +#define GMAC_ST2COM0_2BMASK_Pos 0 +#define GMAC_ST2COM0_2BMASK_Msk (0xffffu << GMAC_ST2COM0_2BMASK_Pos) /**< 2-byte Mask Value */ +#define GMAC_ST2COM0_2BMASK(value) ((GMAC_ST2COM0_2BMASK_Msk & ((value) << GMAC_ST2COM0_2BMASK_Pos))) +#define GMAC_ST2COM0_2BCOMP_Pos 16 +#define GMAC_ST2COM0_2BCOMP_Msk (0xffffu << GMAC_ST2COM0_2BCOMP_Pos) /**< 2-byte Compare Value */ +#define GMAC_ST2COM0_2BCOMP(value) ((GMAC_ST2COM0_2BCOMP_Msk & ((value) << GMAC_ST2COM0_2BCOMP_Pos))) +/* -------- GMAC_ST2COM1[32] : (GMAC Offset: 0x704) Type2 Compare # x, Word 1 -------- */ +#define GMAC_ST2COM1_OFFSET_Pos 0 +#define GMAC_ST2COM1_OFFSET_Msk (0x3fu << GMAC_ST2COM1_OFFSET_Pos) /**< Offset value in bytes */ +#define GMAC_ST2COM1_OFFSET(value) ((GMAC_ST2COM1_OFFSET_Msk & ((value) << GMAC_ST2COM1_OFFSET_Pos))) +#define GMAC_ST2COM1_OFFSET_TYPE_Pos 7 +#define GMAC_ST2COM1_OFFSET_TYPE_Msk (0x3u << GMAC_ST2COM1_OFFSET_TYPE_Pos) /**< Offset start location type */ +#define GMAC_ST2COM1_OFFSET_TYPE(value) ((GMAC_ST2COM1_OFFSET_TYPE_Msk & ((value) << GMAC_ST2COM1_OFFSET_TYPE_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_GMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_gpbr.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_gpbr.h new file mode 100644 index 000000000..76daa8605 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_gpbr.h @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GPBR_COMPONENT_ +#define _SAMV71_GPBR_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR General Purpose Backup Registers */ +/* ============================================================================= */ +/** \addtogroup SAMV71_GPBR General Purpose Backup Registers */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Gpbr hardware registers */ +typedef struct { + __IO uint32_t SYS_GPBR[8]; /**< \brief (Gpbr Offset: 0x0) General Purpose Backup Register */ +} Gpbr; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SYS_GPBR[8] : (GPBR Offset: 0x0) General Purpose Backup Register -------- */ +#define SYS_GPBR_GPBR_VALUE_Pos 0 +#define SYS_GPBR_GPBR_VALUE_Msk (0xffffffffu << SYS_GPBR_GPBR_VALUE_Pos) /**< \brief (SYS_GPBR[8]) Value of GPBR x */ +#define SYS_GPBR_GPBR_VALUE(value) ((SYS_GPBR_GPBR_VALUE_Msk & ((value) << SYS_GPBR_GPBR_VALUE_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_GPBR_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_hsmci.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_hsmci.h new file mode 100644 index 000000000..b25c9625e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_hsmci.h @@ -0,0 +1,335 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_HSMCI_COMPONENT_ +#define _SAMV71_HSMCI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR High Speed MultiMedia Card Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_HSMCI High Speed MultiMedia Card Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Hsmci hardware registers */ +typedef struct { + __O uint32_t HSMCI_CR; /**< \brief (Hsmci Offset: 0x00) Control Register */ + __IO uint32_t HSMCI_MR; /**< \brief (Hsmci Offset: 0x04) Mode Register */ + __IO uint32_t HSMCI_DTOR; /**< \brief (Hsmci Offset: 0x08) Data Timeout Register */ + __IO uint32_t HSMCI_SDCR; /**< \brief (Hsmci Offset: 0x0C) SD/SDIO Card Register */ + __IO uint32_t HSMCI_ARGR; /**< \brief (Hsmci Offset: 0x10) Argument Register */ + __O uint32_t HSMCI_CMDR; /**< \brief (Hsmci Offset: 0x14) Command Register */ + __IO uint32_t HSMCI_BLKR; /**< \brief (Hsmci Offset: 0x18) Block Register */ + __IO uint32_t HSMCI_CSTOR; /**< \brief (Hsmci Offset: 0x1C) Completion Signal Timeout Register */ + __I uint32_t HSMCI_RSPR[4]; /**< \brief (Hsmci Offset: 0x20) Response Register */ + __I uint32_t HSMCI_RDR; /**< \brief (Hsmci Offset: 0x30) Receive Data Register */ + __O uint32_t HSMCI_TDR; /**< \brief (Hsmci Offset: 0x34) Transmit Data Register */ + __I uint32_t Reserved1[2]; + __I uint32_t HSMCI_SR; /**< \brief (Hsmci Offset: 0x40) Status Register */ + __O uint32_t HSMCI_IER; /**< \brief (Hsmci Offset: 0x44) Interrupt Enable Register */ + __O uint32_t HSMCI_IDR; /**< \brief (Hsmci Offset: 0x48) Interrupt Disable Register */ + __I uint32_t HSMCI_IMR; /**< \brief (Hsmci Offset: 0x4C) Interrupt Mask Register */ + __IO uint32_t HSMCI_DMA; /**< \brief (Hsmci Offset: 0x50) DMA Configuration Register */ + __IO uint32_t HSMCI_CFG; /**< \brief (Hsmci Offset: 0x54) Configuration Register */ + __I uint32_t Reserved2[35]; + __IO uint32_t HSMCI_WPMR; /**< \brief (Hsmci Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t HSMCI_WPSR; /**< \brief (Hsmci Offset: 0xE8) Write Protection Status Register */ + __I uint32_t Reserved3[69]; + __IO uint32_t HSMCI_FIFO[256]; /**< \brief (Hsmci Offset: 0x200) FIFO Memory Aperture0 */ +} Hsmci; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- HSMCI_CR : (HSMCI Offset: 0x00) Control Register -------- */ +#define HSMCI_CR_MCIEN (0x1u << 0) /**< \brief (HSMCI_CR) Multi-Media Interface Enable */ +#define HSMCI_CR_MCIDIS (0x1u << 1) /**< \brief (HSMCI_CR) Multi-Media Interface Disable */ +#define HSMCI_CR_PWSEN (0x1u << 2) /**< \brief (HSMCI_CR) Power Save Mode Enable */ +#define HSMCI_CR_PWSDIS (0x1u << 3) /**< \brief (HSMCI_CR) Power Save Mode Disable */ +#define HSMCI_CR_SWRST (0x1u << 7) /**< \brief (HSMCI_CR) Software Reset */ +/* -------- HSMCI_MR : (HSMCI Offset: 0x04) Mode Register -------- */ +#define HSMCI_MR_CLKDIV_Pos 0 +#define HSMCI_MR_CLKDIV_Msk (0xffu << HSMCI_MR_CLKDIV_Pos) /**< \brief (HSMCI_MR) Clock Divider */ +#define HSMCI_MR_CLKDIV(value) ((HSMCI_MR_CLKDIV_Msk & ((value) << HSMCI_MR_CLKDIV_Pos))) +#define HSMCI_MR_PWSDIV_Pos 8 +#define HSMCI_MR_PWSDIV_Msk (0x7u << HSMCI_MR_PWSDIV_Pos) /**< \brief (HSMCI_MR) Power Saving Divider */ +#define HSMCI_MR_PWSDIV(value) ((HSMCI_MR_PWSDIV_Msk & ((value) << HSMCI_MR_PWSDIV_Pos))) +#define HSMCI_MR_RDPROOF (0x1u << 11) /**< \brief (HSMCI_MR) Read Proof Enable */ +#define HSMCI_MR_WRPROOF (0x1u << 12) /**< \brief (HSMCI_MR) Write Proof Enable */ +#define HSMCI_MR_FBYTE (0x1u << 13) /**< \brief (HSMCI_MR) Force Byte Transfer */ +#define HSMCI_MR_PADV (0x1u << 14) /**< \brief (HSMCI_MR) Padding Value */ +#define HSMCI_MR_CLKODD (0x1u << 16) /**< \brief (HSMCI_MR) Clock divider is odd */ +/* -------- HSMCI_DTOR : (HSMCI Offset: 0x08) Data Timeout Register -------- */ +#define HSMCI_DTOR_DTOCYC_Pos 0 +#define HSMCI_DTOR_DTOCYC_Msk (0xfu << HSMCI_DTOR_DTOCYC_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Cycle Number */ +#define HSMCI_DTOR_DTOCYC(value) ((HSMCI_DTOR_DTOCYC_Msk & ((value) << HSMCI_DTOR_DTOCYC_Pos))) +#define HSMCI_DTOR_DTOMUL_Pos 4 +#define HSMCI_DTOR_DTOMUL_Msk (0x7u << HSMCI_DTOR_DTOMUL_Pos) /**< \brief (HSMCI_DTOR) Data Timeout Multiplier */ +#define HSMCI_DTOR_DTOMUL(value) ((HSMCI_DTOR_DTOMUL_Msk & ((value) << HSMCI_DTOR_DTOMUL_Pos))) +#define HSMCI_DTOR_DTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_DTOR) DTOCYC */ +#define HSMCI_DTOR_DTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 16 */ +#define HSMCI_DTOR_DTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 128 */ +#define HSMCI_DTOR_DTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 256 */ +#define HSMCI_DTOR_DTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1024 */ +#define HSMCI_DTOR_DTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 4096 */ +#define HSMCI_DTOR_DTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 65536 */ +#define HSMCI_DTOR_DTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_DTOR) DTOCYC x 1048576 */ +/* -------- HSMCI_SDCR : (HSMCI Offset: 0x0C) SD/SDIO Card Register -------- */ +#define HSMCI_SDCR_SDCSEL_Pos 0 +#define HSMCI_SDCR_SDCSEL_Msk (0x3u << HSMCI_SDCR_SDCSEL_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Slot */ +#define HSMCI_SDCR_SDCSEL(value) ((HSMCI_SDCR_SDCSEL_Msk & ((value) << HSMCI_SDCR_SDCSEL_Pos))) +#define HSMCI_SDCR_SDCSEL_SLOTA (0x0u << 0) /**< \brief (HSMCI_SDCR) Slot A is selected. */ +#define HSMCI_SDCR_SDCBUS_Pos 6 +#define HSMCI_SDCR_SDCBUS_Msk (0x3u << HSMCI_SDCR_SDCBUS_Pos) /**< \brief (HSMCI_SDCR) SDCard/SDIO Bus Width */ +#define HSMCI_SDCR_SDCBUS(value) ((HSMCI_SDCR_SDCBUS_Msk & ((value) << HSMCI_SDCR_SDCBUS_Pos))) +#define HSMCI_SDCR_SDCBUS_1 (0x0u << 6) /**< \brief (HSMCI_SDCR) 1 bit */ +#define HSMCI_SDCR_SDCBUS_4 (0x2u << 6) /**< \brief (HSMCI_SDCR) 4 bits */ +#define HSMCI_SDCR_SDCBUS_8 (0x3u << 6) /**< \brief (HSMCI_SDCR) 8 bits */ +/* -------- HSMCI_ARGR : (HSMCI Offset: 0x10) Argument Register -------- */ +#define HSMCI_ARGR_ARG_Pos 0 +#define HSMCI_ARGR_ARG_Msk (0xffffffffu << HSMCI_ARGR_ARG_Pos) /**< \brief (HSMCI_ARGR) Command Argument */ +#define HSMCI_ARGR_ARG(value) ((HSMCI_ARGR_ARG_Msk & ((value) << HSMCI_ARGR_ARG_Pos))) +/* -------- HSMCI_CMDR : (HSMCI Offset: 0x14) Command Register -------- */ +#define HSMCI_CMDR_CMDNB_Pos 0 +#define HSMCI_CMDR_CMDNB_Msk (0x3fu << HSMCI_CMDR_CMDNB_Pos) /**< \brief (HSMCI_CMDR) Command Number */ +#define HSMCI_CMDR_CMDNB(value) ((HSMCI_CMDR_CMDNB_Msk & ((value) << HSMCI_CMDR_CMDNB_Pos))) +#define HSMCI_CMDR_RSPTYP_Pos 6 +#define HSMCI_CMDR_RSPTYP_Msk (0x3u << HSMCI_CMDR_RSPTYP_Pos) /**< \brief (HSMCI_CMDR) Response Type */ +#define HSMCI_CMDR_RSPTYP(value) ((HSMCI_CMDR_RSPTYP_Msk & ((value) << HSMCI_CMDR_RSPTYP_Pos))) +#define HSMCI_CMDR_RSPTYP_NORESP (0x0u << 6) /**< \brief (HSMCI_CMDR) No response */ +#define HSMCI_CMDR_RSPTYP_48_BIT (0x1u << 6) /**< \brief (HSMCI_CMDR) 48-bit response */ +#define HSMCI_CMDR_RSPTYP_136_BIT (0x2u << 6) /**< \brief (HSMCI_CMDR) 136-bit response */ +#define HSMCI_CMDR_RSPTYP_R1B (0x3u << 6) /**< \brief (HSMCI_CMDR) R1b response type */ +#define HSMCI_CMDR_SPCMD_Pos 8 +#define HSMCI_CMDR_SPCMD_Msk (0x7u << HSMCI_CMDR_SPCMD_Pos) /**< \brief (HSMCI_CMDR) Special Command */ +#define HSMCI_CMDR_SPCMD(value) ((HSMCI_CMDR_SPCMD_Msk & ((value) << HSMCI_CMDR_SPCMD_Pos))) +#define HSMCI_CMDR_SPCMD_STD (0x0u << 8) /**< \brief (HSMCI_CMDR) Not a special CMD. */ +#define HSMCI_CMDR_SPCMD_INIT (0x1u << 8) /**< \brief (HSMCI_CMDR) Initialization CMD: 74 clock cycles for initialization sequence. */ +#define HSMCI_CMDR_SPCMD_SYNC (0x2u << 8) /**< \brief (HSMCI_CMDR) Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. */ +#define HSMCI_CMDR_SPCMD_CE_ATA (0x3u << 8) /**< \brief (HSMCI_CMDR) CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. */ +#define HSMCI_CMDR_SPCMD_IT_CMD (0x4u << 8) /**< \brief (HSMCI_CMDR) Interrupt command: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_IT_RESP (0x5u << 8) /**< \brief (HSMCI_CMDR) Interrupt response: Corresponds to the Interrupt Mode (CMD40). */ +#define HSMCI_CMDR_SPCMD_BOR (0x6u << 8) /**< \brief (HSMCI_CMDR) Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. */ +#define HSMCI_CMDR_SPCMD_EBO (0x7u << 8) /**< \brief (HSMCI_CMDR) End Boot Operation. This command allows the host processor to terminate the boot operation mode. */ +#define HSMCI_CMDR_OPDCMD (0x1u << 11) /**< \brief (HSMCI_CMDR) Open Drain Command */ +#define HSMCI_CMDR_OPDCMD_PUSHPULL (0x0u << 11) /**< \brief (HSMCI_CMDR) Push pull command. */ +#define HSMCI_CMDR_OPDCMD_OPENDRAIN (0x1u << 11) /**< \brief (HSMCI_CMDR) Open drain command. */ +#define HSMCI_CMDR_MAXLAT (0x1u << 12) /**< \brief (HSMCI_CMDR) Max Latency for Command to Response */ +#define HSMCI_CMDR_MAXLAT_5 (0x0u << 12) /**< \brief (HSMCI_CMDR) 5-cycle max latency. */ +#define HSMCI_CMDR_MAXLAT_64 (0x1u << 12) /**< \brief (HSMCI_CMDR) 64-cycle max latency. */ +#define HSMCI_CMDR_TRCMD_Pos 16 +#define HSMCI_CMDR_TRCMD_Msk (0x3u << HSMCI_CMDR_TRCMD_Pos) /**< \brief (HSMCI_CMDR) Transfer Command */ +#define HSMCI_CMDR_TRCMD(value) ((HSMCI_CMDR_TRCMD_Msk & ((value) << HSMCI_CMDR_TRCMD_Pos))) +#define HSMCI_CMDR_TRCMD_NO_DATA (0x0u << 16) /**< \brief (HSMCI_CMDR) No data transfer */ +#define HSMCI_CMDR_TRCMD_START_DATA (0x1u << 16) /**< \brief (HSMCI_CMDR) Start data transfer */ +#define HSMCI_CMDR_TRCMD_STOP_DATA (0x2u << 16) /**< \brief (HSMCI_CMDR) Stop data transfer */ +#define HSMCI_CMDR_TRDIR (0x1u << 18) /**< \brief (HSMCI_CMDR) Transfer Direction */ +#define HSMCI_CMDR_TRDIR_WRITE (0x0u << 18) /**< \brief (HSMCI_CMDR) Write. */ +#define HSMCI_CMDR_TRDIR_READ (0x1u << 18) /**< \brief (HSMCI_CMDR) Read. */ +#define HSMCI_CMDR_TRTYP_Pos 19 +#define HSMCI_CMDR_TRTYP_Msk (0x7u << HSMCI_CMDR_TRTYP_Pos) /**< \brief (HSMCI_CMDR) Transfer Type */ +#define HSMCI_CMDR_TRTYP(value) ((HSMCI_CMDR_TRTYP_Msk & ((value) << HSMCI_CMDR_TRTYP_Pos))) +#define HSMCI_CMDR_TRTYP_SINGLE (0x0u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Single Block */ +#define HSMCI_CMDR_TRTYP_MULTIPLE (0x1u << 19) /**< \brief (HSMCI_CMDR) MMC/SD Card Multiple Block */ +#define HSMCI_CMDR_TRTYP_STREAM (0x2u << 19) /**< \brief (HSMCI_CMDR) MMC Stream */ +#define HSMCI_CMDR_TRTYP_BYTE (0x4u << 19) /**< \brief (HSMCI_CMDR) SDIO Byte */ +#define HSMCI_CMDR_TRTYP_BLOCK (0x5u << 19) /**< \brief (HSMCI_CMDR) SDIO Block */ +#define HSMCI_CMDR_IOSPCMD_Pos 24 +#define HSMCI_CMDR_IOSPCMD_Msk (0x3u << HSMCI_CMDR_IOSPCMD_Pos) /**< \brief (HSMCI_CMDR) SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD(value) ((HSMCI_CMDR_IOSPCMD_Msk & ((value) << HSMCI_CMDR_IOSPCMD_Pos))) +#define HSMCI_CMDR_IOSPCMD_STD (0x0u << 24) /**< \brief (HSMCI_CMDR) Not an SDIO Special Command */ +#define HSMCI_CMDR_IOSPCMD_SUSPEND (0x1u << 24) /**< \brief (HSMCI_CMDR) SDIO Suspend Command */ +#define HSMCI_CMDR_IOSPCMD_RESUME (0x2u << 24) /**< \brief (HSMCI_CMDR) SDIO Resume Command */ +#define HSMCI_CMDR_ATACS (0x1u << 26) /**< \brief (HSMCI_CMDR) ATA with Command Completion Signal */ +#define HSMCI_CMDR_ATACS_NORMAL (0x0u << 26) /**< \brief (HSMCI_CMDR) Normal operation mode. */ +#define HSMCI_CMDR_ATACS_COMPLETION (0x1u << 26) /**< \brief (HSMCI_CMDR) This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). */ +#define HSMCI_CMDR_BOOT_ACK (0x1u << 27) /**< \brief (HSMCI_CMDR) Boot Operation Acknowledge */ +/* -------- HSMCI_BLKR : (HSMCI Offset: 0x18) Block Register -------- */ +#define HSMCI_BLKR_BCNT_Pos 0 +#define HSMCI_BLKR_BCNT_Msk (0xffffu << HSMCI_BLKR_BCNT_Pos) /**< \brief (HSMCI_BLKR) MMC/SDIO Block Count - SDIO Byte Count */ +#define HSMCI_BLKR_BCNT(value) ((HSMCI_BLKR_BCNT_Msk & ((value) << HSMCI_BLKR_BCNT_Pos))) +#define HSMCI_BLKR_BLKLEN_Pos 16 +#define HSMCI_BLKR_BLKLEN_Msk (0xffffu << HSMCI_BLKR_BLKLEN_Pos) /**< \brief (HSMCI_BLKR) Data Block Length */ +#define HSMCI_BLKR_BLKLEN(value) ((HSMCI_BLKR_BLKLEN_Msk & ((value) << HSMCI_BLKR_BLKLEN_Pos))) +/* -------- HSMCI_CSTOR : (HSMCI Offset: 0x1C) Completion Signal Timeout Register -------- */ +#define HSMCI_CSTOR_CSTOCYC_Pos 0 +#define HSMCI_CSTOR_CSTOCYC_Msk (0xfu << HSMCI_CSTOR_CSTOCYC_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Cycle Number */ +#define HSMCI_CSTOR_CSTOCYC(value) ((HSMCI_CSTOR_CSTOCYC_Msk & ((value) << HSMCI_CSTOR_CSTOCYC_Pos))) +#define HSMCI_CSTOR_CSTOMUL_Pos 4 +#define HSMCI_CSTOR_CSTOMUL_Msk (0x7u << HSMCI_CSTOR_CSTOMUL_Pos) /**< \brief (HSMCI_CSTOR) Completion Signal Timeout Multiplier */ +#define HSMCI_CSTOR_CSTOMUL(value) ((HSMCI_CSTOR_CSTOMUL_Msk & ((value) << HSMCI_CSTOR_CSTOMUL_Pos))) +#define HSMCI_CSTOR_CSTOMUL_1 (0x0u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1 */ +#define HSMCI_CSTOR_CSTOMUL_16 (0x1u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 16 */ +#define HSMCI_CSTOR_CSTOMUL_128 (0x2u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 128 */ +#define HSMCI_CSTOR_CSTOMUL_256 (0x3u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 256 */ +#define HSMCI_CSTOR_CSTOMUL_1024 (0x4u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1024 */ +#define HSMCI_CSTOR_CSTOMUL_4096 (0x5u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 4096 */ +#define HSMCI_CSTOR_CSTOMUL_65536 (0x6u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 65536 */ +#define HSMCI_CSTOR_CSTOMUL_1048576 (0x7u << 4) /**< \brief (HSMCI_CSTOR) CSTOCYC x 1048576 */ +/* -------- HSMCI_RSPR[4] : (HSMCI Offset: 0x20) Response Register -------- */ +#define HSMCI_RSPR_RSP_Pos 0 +#define HSMCI_RSPR_RSP_Msk (0xffffffffu << HSMCI_RSPR_RSP_Pos) /**< \brief (HSMCI_RSPR[4]) Response */ +/* -------- HSMCI_RDR : (HSMCI Offset: 0x30) Receive Data Register -------- */ +#define HSMCI_RDR_DATA_Pos 0 +#define HSMCI_RDR_DATA_Msk (0xffffffffu << HSMCI_RDR_DATA_Pos) /**< \brief (HSMCI_RDR) Data to Read */ +/* -------- HSMCI_TDR : (HSMCI Offset: 0x34) Transmit Data Register -------- */ +#define HSMCI_TDR_DATA_Pos 0 +#define HSMCI_TDR_DATA_Msk (0xffffffffu << HSMCI_TDR_DATA_Pos) /**< \brief (HSMCI_TDR) Data to Write */ +#define HSMCI_TDR_DATA(value) ((HSMCI_TDR_DATA_Msk & ((value) << HSMCI_TDR_DATA_Pos))) +/* -------- HSMCI_SR : (HSMCI Offset: 0x40) Status Register -------- */ +#define HSMCI_SR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_SR) Command Ready (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RXRDY (0x1u << 1) /**< \brief (HSMCI_SR) Receiver Ready (cleared by reading HSMCI_RDR) */ +#define HSMCI_SR_TXRDY (0x1u << 2) /**< \brief (HSMCI_SR) Transmit Ready (cleared by writing in HSMCI_TDR) */ +#define HSMCI_SR_BLKE (0x1u << 3) /**< \brief (HSMCI_SR) Data Block Ended (cleared on read) */ +#define HSMCI_SR_DTIP (0x1u << 4) /**< \brief (HSMCI_SR) Data Transfer in Progress (cleared at the end of CRC16 calculation) */ +#define HSMCI_SR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_SR) HSMCI Not Busy */ +#define HSMCI_SR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_SR) SDIO Interrupt for Slot A (cleared on read) */ +#define HSMCI_SR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_SR) SDIO Read Wait Operation Status */ +#define HSMCI_SR_CSRCV (0x1u << 13) /**< \brief (HSMCI_SR) CE-ATA Completion Signal Received (cleared on read) */ +#define HSMCI_SR_RINDE (0x1u << 16) /**< \brief (HSMCI_SR) Response Index Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RDIRE (0x1u << 17) /**< \brief (HSMCI_SR) Response Direction Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RCRCE (0x1u << 18) /**< \brief (HSMCI_SR) Response CRC Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RENDE (0x1u << 19) /**< \brief (HSMCI_SR) Response End Bit Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_RTOE (0x1u << 20) /**< \brief (HSMCI_SR) Response Time-out Error (cleared by writing in HSMCI_CMDR) */ +#define HSMCI_SR_DCRCE (0x1u << 21) /**< \brief (HSMCI_SR) Data CRC Error (cleared on read) */ +#define HSMCI_SR_DTOE (0x1u << 22) /**< \brief (HSMCI_SR) Data Time-out Error (cleared on read) */ +#define HSMCI_SR_CSTOE (0x1u << 23) /**< \brief (HSMCI_SR) Completion Signal Time-out Error (cleared on read) */ +#define HSMCI_SR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_SR) DMA Block Overrun Error (cleared on read) */ +#define HSMCI_SR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_SR) FIFO empty flag */ +#define HSMCI_SR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_SR) Transfer Done flag */ +#define HSMCI_SR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Received (cleared on read) */ +#define HSMCI_SR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_SR) Boot Operation Acknowledge Error (cleared on read) */ +#define HSMCI_SR_OVRE (0x1u << 30) /**< \brief (HSMCI_SR) Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +#define HSMCI_SR_UNRE (0x1u << 31) /**< \brief (HSMCI_SR) Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) */ +/* -------- HSMCI_IER : (HSMCI Offset: 0x44) Interrupt Enable Register -------- */ +#define HSMCI_IER_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IER) Command Ready Interrupt Enable */ +#define HSMCI_IER_RXRDY (0x1u << 1) /**< \brief (HSMCI_IER) Receiver Ready Interrupt Enable */ +#define HSMCI_IER_TXRDY (0x1u << 2) /**< \brief (HSMCI_IER) Transmit Ready Interrupt Enable */ +#define HSMCI_IER_BLKE (0x1u << 3) /**< \brief (HSMCI_IER) Data Block Ended Interrupt Enable */ +#define HSMCI_IER_DTIP (0x1u << 4) /**< \brief (HSMCI_IER) Data Transfer in Progress Interrupt Enable */ +#define HSMCI_IER_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IER) Data Not Busy Interrupt Enable */ +#define HSMCI_IER_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IER) SDIO Interrupt for Slot A Interrupt Enable */ +#define HSMCI_IER_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IER) SDIO Read Wait Operation Status Interrupt Enable */ +#define HSMCI_IER_CSRCV (0x1u << 13) /**< \brief (HSMCI_IER) Completion Signal Received Interrupt Enable */ +#define HSMCI_IER_RINDE (0x1u << 16) /**< \brief (HSMCI_IER) Response Index Error Interrupt Enable */ +#define HSMCI_IER_RDIRE (0x1u << 17) /**< \brief (HSMCI_IER) Response Direction Error Interrupt Enable */ +#define HSMCI_IER_RCRCE (0x1u << 18) /**< \brief (HSMCI_IER) Response CRC Error Interrupt Enable */ +#define HSMCI_IER_RENDE (0x1u << 19) /**< \brief (HSMCI_IER) Response End Bit Error Interrupt Enable */ +#define HSMCI_IER_RTOE (0x1u << 20) /**< \brief (HSMCI_IER) Response Time-out Error Interrupt Enable */ +#define HSMCI_IER_DCRCE (0x1u << 21) /**< \brief (HSMCI_IER) Data CRC Error Interrupt Enable */ +#define HSMCI_IER_DTOE (0x1u << 22) /**< \brief (HSMCI_IER) Data Time-out Error Interrupt Enable */ +#define HSMCI_IER_CSTOE (0x1u << 23) /**< \brief (HSMCI_IER) Completion Signal Timeout Error Interrupt Enable */ +#define HSMCI_IER_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IER) DMA Block Overrun Error Interrupt Enable */ +#define HSMCI_IER_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IER) FIFO empty Interrupt enable */ +#define HSMCI_IER_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IER) Transfer Done Interrupt enable */ +#define HSMCI_IER_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IER) Boot Acknowledge Interrupt Enable */ +#define HSMCI_IER_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IER) Boot Acknowledge Error Interrupt Enable */ +#define HSMCI_IER_OVRE (0x1u << 30) /**< \brief (HSMCI_IER) Overrun Interrupt Enable */ +#define HSMCI_IER_UNRE (0x1u << 31) /**< \brief (HSMCI_IER) Underrun Interrupt Enable */ +/* -------- HSMCI_IDR : (HSMCI Offset: 0x48) Interrupt Disable Register -------- */ +#define HSMCI_IDR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IDR) Command Ready Interrupt Disable */ +#define HSMCI_IDR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IDR) Receiver Ready Interrupt Disable */ +#define HSMCI_IDR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IDR) Transmit Ready Interrupt Disable */ +#define HSMCI_IDR_BLKE (0x1u << 3) /**< \brief (HSMCI_IDR) Data Block Ended Interrupt Disable */ +#define HSMCI_IDR_DTIP (0x1u << 4) /**< \brief (HSMCI_IDR) Data Transfer in Progress Interrupt Disable */ +#define HSMCI_IDR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IDR) Data Not Busy Interrupt Disable */ +#define HSMCI_IDR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IDR) SDIO Interrupt for Slot A Interrupt Disable */ +#define HSMCI_IDR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IDR) SDIO Read Wait Operation Status Interrupt Disable */ +#define HSMCI_IDR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IDR) Completion Signal received interrupt Disable */ +#define HSMCI_IDR_RINDE (0x1u << 16) /**< \brief (HSMCI_IDR) Response Index Error Interrupt Disable */ +#define HSMCI_IDR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IDR) Response Direction Error Interrupt Disable */ +#define HSMCI_IDR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IDR) Response CRC Error Interrupt Disable */ +#define HSMCI_IDR_RENDE (0x1u << 19) /**< \brief (HSMCI_IDR) Response End Bit Error Interrupt Disable */ +#define HSMCI_IDR_RTOE (0x1u << 20) /**< \brief (HSMCI_IDR) Response Time-out Error Interrupt Disable */ +#define HSMCI_IDR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IDR) Data CRC Error Interrupt Disable */ +#define HSMCI_IDR_DTOE (0x1u << 22) /**< \brief (HSMCI_IDR) Data Time-out Error Interrupt Disable */ +#define HSMCI_IDR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IDR) Completion Signal Time out Error Interrupt Disable */ +#define HSMCI_IDR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IDR) DMA Block Overrun Error Interrupt Disable */ +#define HSMCI_IDR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IDR) FIFO empty Interrupt Disable */ +#define HSMCI_IDR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IDR) Transfer Done Interrupt Disable */ +#define HSMCI_IDR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IDR) Boot Acknowledge Interrupt Disable */ +#define HSMCI_IDR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IDR) Boot Acknowledge Error Interrupt Disable */ +#define HSMCI_IDR_OVRE (0x1u << 30) /**< \brief (HSMCI_IDR) Overrun Interrupt Disable */ +#define HSMCI_IDR_UNRE (0x1u << 31) /**< \brief (HSMCI_IDR) Underrun Interrupt Disable */ +/* -------- HSMCI_IMR : (HSMCI Offset: 0x4C) Interrupt Mask Register -------- */ +#define HSMCI_IMR_CMDRDY (0x1u << 0) /**< \brief (HSMCI_IMR) Command Ready Interrupt Mask */ +#define HSMCI_IMR_RXRDY (0x1u << 1) /**< \brief (HSMCI_IMR) Receiver Ready Interrupt Mask */ +#define HSMCI_IMR_TXRDY (0x1u << 2) /**< \brief (HSMCI_IMR) Transmit Ready Interrupt Mask */ +#define HSMCI_IMR_BLKE (0x1u << 3) /**< \brief (HSMCI_IMR) Data Block Ended Interrupt Mask */ +#define HSMCI_IMR_DTIP (0x1u << 4) /**< \brief (HSMCI_IMR) Data Transfer in Progress Interrupt Mask */ +#define HSMCI_IMR_NOTBUSY (0x1u << 5) /**< \brief (HSMCI_IMR) Data Not Busy Interrupt Mask */ +#define HSMCI_IMR_SDIOIRQA (0x1u << 8) /**< \brief (HSMCI_IMR) SDIO Interrupt for Slot A Interrupt Mask */ +#define HSMCI_IMR_SDIOWAIT (0x1u << 12) /**< \brief (HSMCI_IMR) SDIO Read Wait Operation Status Interrupt Mask */ +#define HSMCI_IMR_CSRCV (0x1u << 13) /**< \brief (HSMCI_IMR) Completion Signal Received Interrupt Mask */ +#define HSMCI_IMR_RINDE (0x1u << 16) /**< \brief (HSMCI_IMR) Response Index Error Interrupt Mask */ +#define HSMCI_IMR_RDIRE (0x1u << 17) /**< \brief (HSMCI_IMR) Response Direction Error Interrupt Mask */ +#define HSMCI_IMR_RCRCE (0x1u << 18) /**< \brief (HSMCI_IMR) Response CRC Error Interrupt Mask */ +#define HSMCI_IMR_RENDE (0x1u << 19) /**< \brief (HSMCI_IMR) Response End Bit Error Interrupt Mask */ +#define HSMCI_IMR_RTOE (0x1u << 20) /**< \brief (HSMCI_IMR) Response Time-out Error Interrupt Mask */ +#define HSMCI_IMR_DCRCE (0x1u << 21) /**< \brief (HSMCI_IMR) Data CRC Error Interrupt Mask */ +#define HSMCI_IMR_DTOE (0x1u << 22) /**< \brief (HSMCI_IMR) Data Time-out Error Interrupt Mask */ +#define HSMCI_IMR_CSTOE (0x1u << 23) /**< \brief (HSMCI_IMR) Completion Signal Time-out Error Interrupt Mask */ +#define HSMCI_IMR_BLKOVRE (0x1u << 24) /**< \brief (HSMCI_IMR) DMA Block Overrun Error Interrupt Mask */ +#define HSMCI_IMR_FIFOEMPTY (0x1u << 26) /**< \brief (HSMCI_IMR) FIFO Empty Interrupt Mask */ +#define HSMCI_IMR_XFRDONE (0x1u << 27) /**< \brief (HSMCI_IMR) Transfer Done Interrupt Mask */ +#define HSMCI_IMR_ACKRCV (0x1u << 28) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Received Interrupt Mask */ +#define HSMCI_IMR_ACKRCVE (0x1u << 29) /**< \brief (HSMCI_IMR) Boot Operation Acknowledge Error Interrupt Mask */ +#define HSMCI_IMR_OVRE (0x1u << 30) /**< \brief (HSMCI_IMR) Overrun Interrupt Mask */ +#define HSMCI_IMR_UNRE (0x1u << 31) /**< \brief (HSMCI_IMR) Underrun Interrupt Mask */ +/* -------- HSMCI_DMA : (HSMCI Offset: 0x50) DMA Configuration Register -------- */ +#define HSMCI_DMA_CHKSIZE_Pos 4 +#define HSMCI_DMA_CHKSIZE_Msk (0x7u << HSMCI_DMA_CHKSIZE_Pos) /**< \brief (HSMCI_DMA) DMA Channel Read and Write Chunk Size */ +#define HSMCI_DMA_CHKSIZE(value) ((HSMCI_DMA_CHKSIZE_Msk & ((value) << HSMCI_DMA_CHKSIZE_Pos))) +#define HSMCI_DMA_CHKSIZE_1 (0x0u << 4) /**< \brief (HSMCI_DMA) 1 data available */ +#define HSMCI_DMA_CHKSIZE_2 (0x1u << 4) /**< \brief (HSMCI_DMA) 2 data available */ +#define HSMCI_DMA_CHKSIZE_4 (0x2u << 4) /**< \brief (HSMCI_DMA) 4 data available */ +#define HSMCI_DMA_CHKSIZE_8 (0x3u << 4) /**< \brief (HSMCI_DMA) 8 data available */ +#define HSMCI_DMA_CHKSIZE_16 (0x4u << 4) /**< \brief (HSMCI_DMA) 16 data available */ +#define HSMCI_DMA_DMAEN (0x1u << 8) /**< \brief (HSMCI_DMA) DMA Hardware Handshaking Enable */ +/* -------- HSMCI_CFG : (HSMCI Offset: 0x54) Configuration Register -------- */ +#define HSMCI_CFG_FIFOMODE (0x1u << 0) /**< \brief (HSMCI_CFG) HSMCI Internal FIFO control mode */ +#define HSMCI_CFG_FERRCTRL (0x1u << 4) /**< \brief (HSMCI_CFG) Flow Error flag reset control mode */ +#define HSMCI_CFG_HSMODE (0x1u << 8) /**< \brief (HSMCI_CFG) High Speed Mode */ +#define HSMCI_CFG_LSYNC (0x1u << 12) /**< \brief (HSMCI_CFG) Synchronize on the last block */ +/* -------- HSMCI_WPMR : (HSMCI Offset: 0xE4) Write Protection Mode Register -------- */ +#define HSMCI_WPMR_WPEN (0x1u << 0) /**< \brief (HSMCI_WPMR) Write Protect Enable */ +#define HSMCI_WPMR_WPKEY_Pos 8 +#define HSMCI_WPMR_WPKEY_Msk (0xffffffu << HSMCI_WPMR_WPKEY_Pos) /**< \brief (HSMCI_WPMR) Write Protect Key */ +#define HSMCI_WPMR_WPKEY(value) ((HSMCI_WPMR_WPKEY_Msk & ((value) << HSMCI_WPMR_WPKEY_Pos))) +#define HSMCI_WPMR_WPKEY_PASSWD (0x4D4349u << 8) /**< \brief (HSMCI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- HSMCI_WPSR : (HSMCI Offset: 0xE8) Write Protection Status Register -------- */ +#define HSMCI_WPSR_WPVS (0x1u << 0) /**< \brief (HSMCI_WPSR) Write Protection Violation Status */ +#define HSMCI_WPSR_WPVSRC_Pos 8 +#define HSMCI_WPSR_WPVSRC_Msk (0xffffu << HSMCI_WPSR_WPVSRC_Pos) /**< \brief (HSMCI_WPSR) Write Protection Violation Source */ +/* -------- HSMCI_FIFO[256] : (HSMCI Offset: 0x200) FIFO Memory Aperture0 -------- */ +#define HSMCI_FIFO_DATA_Pos 0 +#define HSMCI_FIFO_DATA_Msk (0xffffffffu << HSMCI_FIFO_DATA_Pos) /**< \brief (HSMCI_FIFO[256]) Data to Read or Data to Write */ +#define HSMCI_FIFO_DATA(value) ((HSMCI_FIFO_DATA_Msk & ((value) << HSMCI_FIFO_DATA_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_HSMCI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_icm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_icm.h new file mode 100644 index 000000000..e022f7fa7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_icm.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ICM_COMPONENT_ +#define _SAMV71_ICM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Integrity Check Monitor */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ICM Integrity Check Monitor */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Icm hardware registers */ +typedef struct { + __IO uint32_t ICM_CFG; /**< \brief (Icm Offset: 0x00) Configuration Register */ + __O uint32_t ICM_CTRL; /**< \brief (Icm Offset: 0x04) Control Register */ + __O uint32_t ICM_SR; /**< \brief (Icm Offset: 0x08) Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t ICM_IER; /**< \brief (Icm Offset: 0x10) Interrupt Enable Register */ + __O uint32_t ICM_IDR; /**< \brief (Icm Offset: 0x14) Interrupt Disable Register */ + __I uint32_t ICM_IMR; /**< \brief (Icm Offset: 0x18) Interrupt Mask Register */ + __I uint32_t ICM_ISR; /**< \brief (Icm Offset: 0x1C) Interrupt Status Register */ + __I uint32_t ICM_UASR; /**< \brief (Icm Offset: 0x20) Undefined Access Status Register */ + __I uint32_t Reserved2[3]; + __IO uint32_t ICM_DSCR; /**< \brief (Icm Offset: 0x30) Region Descriptor Area Start Address Register */ + __IO uint32_t ICM_HASH; /**< \brief (Icm Offset: 0x34) Region Hash Area Start Address Register */ + __O uint32_t ICM_UIHVAL[8]; /**< \brief (Icm Offset: 0x38) User Initial Hash Value 0 Register */ +} Icm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ICM_CFG : (ICM Offset: 0x00) Configuration Register -------- */ +#define ICM_CFG_WBDIS (0x1u << 0) /**< \brief (ICM_CFG) Write Back Disable */ +#define ICM_CFG_EOMDIS (0x1u << 1) /**< \brief (ICM_CFG) End of Monitoring Disable */ +#define ICM_CFG_SLBDIS (0x1u << 2) /**< \brief (ICM_CFG) Secondary List Branching Disable */ +#define ICM_CFG_BBC_Pos 4 +#define ICM_CFG_BBC_Msk (0xfu << ICM_CFG_BBC_Pos) /**< \brief (ICM_CFG) Bus Burden Control */ +#define ICM_CFG_BBC(value) ((ICM_CFG_BBC_Msk & ((value) << ICM_CFG_BBC_Pos))) +#define ICM_CFG_ASCD (0x1u << 8) /**< \brief (ICM_CFG) Automatic Switch To Compare Digest */ +#define ICM_CFG_DUALBUFF (0x1u << 9) /**< \brief (ICM_CFG) Dual Input Buffer */ +#define ICM_CFG_UIHASH (0x1u << 12) /**< \brief (ICM_CFG) User Initial Hash Value */ +#define ICM_CFG_UALGO_Pos 13 +#define ICM_CFG_UALGO_Msk (0x7u << ICM_CFG_UALGO_Pos) /**< \brief (ICM_CFG) User SHA Algorithm */ +#define ICM_CFG_UALGO(value) ((ICM_CFG_UALGO_Msk & ((value) << ICM_CFG_UALGO_Pos))) +#define ICM_CFG_UALGO_SHA1 (0x0u << 13) /**< \brief (ICM_CFG) SHA1 algorithm processed */ +#define ICM_CFG_UALGO_SHA256 (0x1u << 13) /**< \brief (ICM_CFG) SHA256 algorithm processed */ +#define ICM_CFG_UALGO_SHA224 (0x4u << 13) /**< \brief (ICM_CFG) SHA224 algorithm processed */ +#define ICM_CFG_HAPROT_Pos 16 +#define ICM_CFG_HAPROT_Msk (0x3fu << ICM_CFG_HAPROT_Pos) /**< \brief (ICM_CFG) Region Hash Area Protection */ +#define ICM_CFG_HAPROT(value) ((ICM_CFG_HAPROT_Msk & ((value) << ICM_CFG_HAPROT_Pos))) +#define ICM_CFG_DAPROT_Pos 24 +#define ICM_CFG_DAPROT_Msk (0x3fu << ICM_CFG_DAPROT_Pos) /**< \brief (ICM_CFG) Region Descriptor Area Protection */ +#define ICM_CFG_DAPROT(value) ((ICM_CFG_DAPROT_Msk & ((value) << ICM_CFG_DAPROT_Pos))) +/* -------- ICM_CTRL : (ICM Offset: 0x04) Control Register -------- */ +#define ICM_CTRL_ENABLE (0x1u << 0) /**< \brief (ICM_CTRL) ICM Enable */ +#define ICM_CTRL_DISABLE (0x1u << 1) /**< \brief (ICM_CTRL) ICM Disable Register */ +#define ICM_CTRL_SWRST (0x1u << 2) /**< \brief (ICM_CTRL) Software Reset */ +#define ICM_CTRL_REHASH_Pos 4 +#define ICM_CTRL_REHASH_Msk (0xfu << ICM_CTRL_REHASH_Pos) /**< \brief (ICM_CTRL) Recompute Internal Hash */ +#define ICM_CTRL_REHASH(value) ((ICM_CTRL_REHASH_Msk & ((value) << ICM_CTRL_REHASH_Pos))) +#define ICM_CTRL_RMDIS_Pos 8 +#define ICM_CTRL_RMDIS_Msk (0xfu << ICM_CTRL_RMDIS_Pos) /**< \brief (ICM_CTRL) Region Monitoring Disable */ +#define ICM_CTRL_RMDIS(value) ((ICM_CTRL_RMDIS_Msk & ((value) << ICM_CTRL_RMDIS_Pos))) +#define ICM_CTRL_RMEN_Pos 12 +#define ICM_CTRL_RMEN_Msk (0xfu << ICM_CTRL_RMEN_Pos) /**< \brief (ICM_CTRL) Region Monitoring Enable */ +#define ICM_CTRL_RMEN(value) ((ICM_CTRL_RMEN_Msk & ((value) << ICM_CTRL_RMEN_Pos))) +/* -------- ICM_SR : (ICM Offset: 0x08) Status Register -------- */ +#define ICM_SR_ENABLE (0x1u << 0) /**< \brief (ICM_SR) ICM Controller Enable Register */ +#define ICM_SR_RAWRMDIS_Pos 8 +#define ICM_SR_RAWRMDIS_Msk (0xfu << ICM_SR_RAWRMDIS_Pos) /**< \brief (ICM_SR) RAW Region Monitoring Disabled Status */ +#define ICM_SR_RAWRMDIS(value) ((ICM_SR_RAWRMDIS_Msk & ((value) << ICM_SR_RAWRMDIS_Pos))) +#define ICM_SR_RMDIS_Pos 12 +#define ICM_SR_RMDIS_Msk (0xfu << ICM_SR_RMDIS_Pos) /**< \brief (ICM_SR) Region Monitoring Disabled Status */ +#define ICM_SR_RMDIS(value) ((ICM_SR_RMDIS_Msk & ((value) << ICM_SR_RMDIS_Pos))) +/* -------- ICM_IER : (ICM Offset: 0x10) Interrupt Enable Register -------- */ +#define ICM_IER_RHC_Pos 0 +#define ICM_IER_RHC_Msk (0xfu << ICM_IER_RHC_Pos) /**< \brief (ICM_IER) Region Hash Completed Interrupt Enable */ +#define ICM_IER_RHC(value) ((ICM_IER_RHC_Msk & ((value) << ICM_IER_RHC_Pos))) +#define ICM_IER_RDM_Pos 4 +#define ICM_IER_RDM_Msk (0xfu << ICM_IER_RDM_Pos) /**< \brief (ICM_IER) Region Digest Mismatch Interrupt Enable */ +#define ICM_IER_RDM(value) ((ICM_IER_RDM_Msk & ((value) << ICM_IER_RDM_Pos))) +#define ICM_IER_RBE_Pos 8 +#define ICM_IER_RBE_Msk (0xfu << ICM_IER_RBE_Pos) /**< \brief (ICM_IER) Region Bus Error Interrupt Enable */ +#define ICM_IER_RBE(value) ((ICM_IER_RBE_Msk & ((value) << ICM_IER_RBE_Pos))) +#define ICM_IER_RWC_Pos 12 +#define ICM_IER_RWC_Msk (0xfu << ICM_IER_RWC_Pos) /**< \brief (ICM_IER) Region Wrap Condition detected Interrupt Enable */ +#define ICM_IER_RWC(value) ((ICM_IER_RWC_Msk & ((value) << ICM_IER_RWC_Pos))) +#define ICM_IER_REC_Pos 16 +#define ICM_IER_REC_Msk (0xfu << ICM_IER_REC_Pos) /**< \brief (ICM_IER) Region End bit Condition Detected Interrupt Enable */ +#define ICM_IER_REC(value) ((ICM_IER_REC_Msk & ((value) << ICM_IER_REC_Pos))) +#define ICM_IER_RSU_Pos 20 +#define ICM_IER_RSU_Msk (0xfu << ICM_IER_RSU_Pos) /**< \brief (ICM_IER) Region Status Updated Interrupt Disable */ +#define ICM_IER_RSU(value) ((ICM_IER_RSU_Msk & ((value) << ICM_IER_RSU_Pos))) +#define ICM_IER_URAD (0x1u << 24) /**< \brief (ICM_IER) Undefined Register Access Detection Interrupt Enable */ +/* -------- ICM_IDR : (ICM Offset: 0x14) Interrupt Disable Register -------- */ +#define ICM_IDR_RHC_Pos 0 +#define ICM_IDR_RHC_Msk (0xfu << ICM_IDR_RHC_Pos) /**< \brief (ICM_IDR) Region Hash Completed Interrupt Disable */ +#define ICM_IDR_RHC(value) ((ICM_IDR_RHC_Msk & ((value) << ICM_IDR_RHC_Pos))) +#define ICM_IDR_RDM_Pos 4 +#define ICM_IDR_RDM_Msk (0xfu << ICM_IDR_RDM_Pos) /**< \brief (ICM_IDR) Region Digest Mismatch Interrupt Disable */ +#define ICM_IDR_RDM(value) ((ICM_IDR_RDM_Msk & ((value) << ICM_IDR_RDM_Pos))) +#define ICM_IDR_RBE_Pos 8 +#define ICM_IDR_RBE_Msk (0xfu << ICM_IDR_RBE_Pos) /**< \brief (ICM_IDR) Region Bus Error Interrupt Disable */ +#define ICM_IDR_RBE(value) ((ICM_IDR_RBE_Msk & ((value) << ICM_IDR_RBE_Pos))) +#define ICM_IDR_RWC_Pos 12 +#define ICM_IDR_RWC_Msk (0xfu << ICM_IDR_RWC_Pos) /**< \brief (ICM_IDR) Region Wrap Condition Detected Interrupt Disable */ +#define ICM_IDR_RWC(value) ((ICM_IDR_RWC_Msk & ((value) << ICM_IDR_RWC_Pos))) +#define ICM_IDR_REC_Pos 16 +#define ICM_IDR_REC_Msk (0xfu << ICM_IDR_REC_Pos) /**< \brief (ICM_IDR) Region End bit Condition detected Interrupt Disable */ +#define ICM_IDR_REC(value) ((ICM_IDR_REC_Msk & ((value) << ICM_IDR_REC_Pos))) +#define ICM_IDR_RSU_Pos 20 +#define ICM_IDR_RSU_Msk (0xfu << ICM_IDR_RSU_Pos) /**< \brief (ICM_IDR) Region Status Updated Interrupt Disable */ +#define ICM_IDR_RSU(value) ((ICM_IDR_RSU_Msk & ((value) << ICM_IDR_RSU_Pos))) +#define ICM_IDR_URAD (0x1u << 24) /**< \brief (ICM_IDR) Undefined Register Access Detection Interrupt Disable */ +/* -------- ICM_IMR : (ICM Offset: 0x18) Interrupt Mask Register -------- */ +#define ICM_IMR_RHC_Pos 0 +#define ICM_IMR_RHC_Msk (0xfu << ICM_IMR_RHC_Pos) /**< \brief (ICM_IMR) Region Hash Completed Interrupt Mask */ +#define ICM_IMR_RDM_Pos 4 +#define ICM_IMR_RDM_Msk (0xfu << ICM_IMR_RDM_Pos) /**< \brief (ICM_IMR) Region Digest Mismatch Interrupt Mask */ +#define ICM_IMR_RBE_Pos 8 +#define ICM_IMR_RBE_Msk (0xfu << ICM_IMR_RBE_Pos) /**< \brief (ICM_IMR) Region Bus Error Interrupt Mask */ +#define ICM_IMR_RWC_Pos 12 +#define ICM_IMR_RWC_Msk (0xfu << ICM_IMR_RWC_Pos) /**< \brief (ICM_IMR) Region Wrap Condition Detected Interrupt Mask */ +#define ICM_IMR_REC_Pos 16 +#define ICM_IMR_REC_Msk (0xfu << ICM_IMR_REC_Pos) /**< \brief (ICM_IMR) Region End bit Condition Detected Interrupt Mask */ +#define ICM_IMR_RSU_Pos 20 +#define ICM_IMR_RSU_Msk (0xfu << ICM_IMR_RSU_Pos) /**< \brief (ICM_IMR) Region Status Updated Interrupt Mask */ +#define ICM_IMR_URAD (0x1u << 24) /**< \brief (ICM_IMR) Undefined Register Access Detection Interrupt Mask */ +/* -------- ICM_ISR : (ICM Offset: 0x1C) Interrupt Status Register -------- */ +#define ICM_ISR_RHC_Pos 0 +#define ICM_ISR_RHC_Msk (0xfu << ICM_ISR_RHC_Pos) /**< \brief (ICM_ISR) Region Hash Completed */ +#define ICM_ISR_RDM_Pos 4 +#define ICM_ISR_RDM_Msk (0xfu << ICM_ISR_RDM_Pos) /**< \brief (ICM_ISR) Region Digest Mismatch */ +#define ICM_ISR_RBE_Pos 8 +#define ICM_ISR_RBE_Msk (0xfu << ICM_ISR_RBE_Pos) /**< \brief (ICM_ISR) Region Bus Error */ +#define ICM_ISR_RWC_Pos 12 +#define ICM_ISR_RWC_Msk (0xfu << ICM_ISR_RWC_Pos) /**< \brief (ICM_ISR) Region Wrap Condition Detected */ +#define ICM_ISR_REC_Pos 16 +#define ICM_ISR_REC_Msk (0xfu << ICM_ISR_REC_Pos) /**< \brief (ICM_ISR) Region End bit Condition Detected */ +#define ICM_ISR_RSU_Pos 20 +#define ICM_ISR_RSU_Msk (0xfu << ICM_ISR_RSU_Pos) /**< \brief (ICM_ISR) Region Status Updated Detected */ +#define ICM_ISR_URAD (0x1u << 24) /**< \brief (ICM_ISR) Undefined Register Access Detection Status */ +/* -------- ICM_UASR : (ICM Offset: 0x20) Undefined Access Status Register -------- */ +#define ICM_UASR_URAT_Pos 0 +#define ICM_UASR_URAT_Msk (0x7u << ICM_UASR_URAT_Pos) /**< \brief (ICM_UASR) Undefined Register Access Trace */ +#define ICM_UASR_URAT_UNSPEC_STRUCT_MEMBER (0x0u << 0) /**< \brief (ICM_UASR) Unspecified structure member set to one detected when the descriptor is loaded. */ +#define ICM_UASR_URAT_ICM_CFG_MODIFIED (0x1u << 0) /**< \brief (ICM_UASR) ICM_CFG modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_DSCR_MODIFIED (0x2u << 0) /**< \brief (ICM_UASR) ICM_DSCR modified during active monitoring. */ +#define ICM_UASR_URAT_ICM_HASH_MODIFIED (0x3u << 0) /**< \brief (ICM_UASR) ICM_HASH modified during active monitoring */ +#define ICM_UASR_URAT_READ_ACCESS (0x4u << 0) /**< \brief (ICM_UASR) Write-only register read access */ +/* -------- ICM_DSCR : (ICM Offset: 0x30) Region Descriptor Area Start Address Register -------- */ +#define ICM_DSCR_DASA_Pos 6 +#define ICM_DSCR_DASA_Msk (0x3ffffffu << ICM_DSCR_DASA_Pos) /**< \brief (ICM_DSCR) Descriptor Area Start Address */ +#define ICM_DSCR_DASA(value) ((ICM_DSCR_DASA_Msk & ((value) << ICM_DSCR_DASA_Pos))) +/* -------- ICM_HASH : (ICM Offset: 0x34) Region Hash Area Start Address Register -------- */ +#define ICM_HASH_HASA_Pos 7 +#define ICM_HASH_HASA_Msk (0x1ffffffu << ICM_HASH_HASA_Pos) /**< \brief (ICM_HASH) Hash Area Start Address */ +#define ICM_HASH_HASA(value) ((ICM_HASH_HASA_Msk & ((value) << ICM_HASH_HASA_Pos))) +/* -------- ICM_UIHVAL[8] : (ICM Offset: 0x38) User Initial Hash Value 0 Register -------- */ +#define ICM_UIHVAL_VAL_Pos 0 +#define ICM_UIHVAL_VAL_Msk (0xffffffffu << ICM_UIHVAL_VAL_Pos) /**< \brief (ICM_UIHVAL[8]) Initial Hash Value */ +#define ICM_UIHVAL_VAL(value) ((ICM_UIHVAL_VAL_Msk & ((value) << ICM_UIHVAL_VAL_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_ICM_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_isi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_isi.h new file mode 100644 index 000000000..5548f7b87 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_isi.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ISI_COMPONENT_ +#define _SAMV71_ISI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Image Sensor Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_ISI Image Sensor Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Isi hardware registers */ +typedef struct { + __IO uint32_t ISI_CFG1; /**< \brief (Isi Offset: 0x00) ISI Configuration 1 Register */ + __IO uint32_t ISI_CFG2; /**< \brief (Isi Offset: 0x04) ISI Configuration 2 Register */ + __IO uint32_t ISI_PSIZE; /**< \brief (Isi Offset: 0x08) ISI Preview Size Register */ + __IO uint32_t ISI_PDECF; /**< \brief (Isi Offset: 0x0C) ISI Preview Decimation Factor Register */ + __IO uint32_t ISI_Y2R_SET0; /**< \brief (Isi Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + __IO uint32_t ISI_Y2R_SET1; /**< \brief (Isi Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + __IO uint32_t ISI_R2Y_SET0; /**< \brief (Isi Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + __IO uint32_t ISI_R2Y_SET1; /**< \brief (Isi Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + __IO uint32_t ISI_R2Y_SET2; /**< \brief (Isi Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + __O uint32_t ISI_CR; /**< \brief (Isi Offset: 0x24) ISI Control Register */ + __I uint32_t ISI_SR; /**< \brief (Isi Offset: 0x28) ISI Status Register */ + __O uint32_t ISI_IER; /**< \brief (Isi Offset: 0x2C) ISI Interrupt Enable Register */ + __O uint32_t ISI_IDR; /**< \brief (Isi Offset: 0x30) ISI Interrupt Disable Register */ + __I uint32_t ISI_IMR; /**< \brief (Isi Offset: 0x34) ISI Interrupt Mask Register */ + __O uint32_t ISI_DMA_CHER; /**< \brief (Isi Offset: 0x38) DMA Channel Enable Register */ + __O uint32_t ISI_DMA_CHDR; /**< \brief (Isi Offset: 0x3C) DMA Channel Disable Register */ + __I uint32_t ISI_DMA_CHSR; /**< \brief (Isi Offset: 0x40) DMA Channel Status Register */ + __IO uint32_t ISI_DMA_P_ADDR; /**< \brief (Isi Offset: 0x44) DMA Preview Base Address Register */ + __IO uint32_t ISI_DMA_P_CTRL; /**< \brief (Isi Offset: 0x48) DMA Preview Control Register */ + __IO uint32_t ISI_DMA_P_DSCR; /**< \brief (Isi Offset: 0x4C) DMA Preview Descriptor Address Register */ + __IO uint32_t ISI_DMA_C_ADDR; /**< \brief (Isi Offset: 0x50) DMA Codec Base Address Register */ + __IO uint32_t ISI_DMA_C_CTRL; /**< \brief (Isi Offset: 0x54) DMA Codec Control Register */ + __IO uint32_t ISI_DMA_C_DSCR; /**< \brief (Isi Offset: 0x58) DMA Codec Descriptor Address Register */ + __I uint32_t Reserved1[34]; + __IO uint32_t ISI_WPMR; /**< \brief (Isi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t ISI_WPSR; /**< \brief (Isi Offset: 0xE8) Write Protection Status Register */ +} Isi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- ISI_CFG1 : (ISI Offset: 0x00) ISI Configuration 1 Register -------- */ +#define ISI_CFG1_HSYNC_POL (0x1u << 2) /**< \brief (ISI_CFG1) Horizontal Synchronization Polarity */ +#define ISI_CFG1_VSYNC_POL (0x1u << 3) /**< \brief (ISI_CFG1) Vertical Synchronization Polarity */ +#define ISI_CFG1_PIXCLK_POL (0x1u << 4) /**< \brief (ISI_CFG1) Pixel Clock Polarity */ +#define ISI_CFG1_EMB_SYNC (0x1u << 6) /**< \brief (ISI_CFG1) Embedded Synchronization */ +#define ISI_CFG1_CRC_SYNC (0x1u << 7) /**< \brief (ISI_CFG1) Embedded Synchronization Correction */ +#define ISI_CFG1_FRATE_Pos 8 +#define ISI_CFG1_FRATE_Msk (0x7u << ISI_CFG1_FRATE_Pos) /**< \brief (ISI_CFG1) Frame Rate [0..7] */ +#define ISI_CFG1_FRATE(value) ((ISI_CFG1_FRATE_Msk & ((value) << ISI_CFG1_FRATE_Pos))) +#define ISI_CFG1_DISCR (0x1u << 11) /**< \brief (ISI_CFG1) Disable Codec Request */ +#define ISI_CFG1_FULL (0x1u << 12) /**< \brief (ISI_CFG1) Full Mode is Allowed */ +#define ISI_CFG1_THMASK_Pos 13 +#define ISI_CFG1_THMASK_Msk (0x3u << ISI_CFG1_THMASK_Pos) /**< \brief (ISI_CFG1) Threshold Mask */ +#define ISI_CFG1_THMASK(value) ((ISI_CFG1_THMASK_Msk & ((value) << ISI_CFG1_THMASK_Pos))) +#define ISI_CFG1_THMASK_BEATS_4 (0x0u << 13) /**< \brief (ISI_CFG1) Only 4 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_8 (0x1u << 13) /**< \brief (ISI_CFG1) Only 4 and 8 beats AHB burst allowed */ +#define ISI_CFG1_THMASK_BEATS_16 (0x2u << 13) /**< \brief (ISI_CFG1) 4, 8 and 16 beats AHB burst allowed */ +#define ISI_CFG1_SLD_Pos 16 +#define ISI_CFG1_SLD_Msk (0xffu << ISI_CFG1_SLD_Pos) /**< \brief (ISI_CFG1) Start of Line Delay */ +#define ISI_CFG1_SLD(value) ((ISI_CFG1_SLD_Msk & ((value) << ISI_CFG1_SLD_Pos))) +#define ISI_CFG1_SFD_Pos 24 +#define ISI_CFG1_SFD_Msk (0xffu << ISI_CFG1_SFD_Pos) /**< \brief (ISI_CFG1) Start of Frame Delay */ +#define ISI_CFG1_SFD(value) ((ISI_CFG1_SFD_Msk & ((value) << ISI_CFG1_SFD_Pos))) +/* -------- ISI_CFG2 : (ISI Offset: 0x04) ISI Configuration 2 Register -------- */ +#define ISI_CFG2_IM_VSIZE_Pos 0 +#define ISI_CFG2_IM_VSIZE_Msk (0x7ffu << ISI_CFG2_IM_VSIZE_Pos) /**< \brief (ISI_CFG2) Vertical Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_VSIZE(value) ((ISI_CFG2_IM_VSIZE_Msk & ((value) << ISI_CFG2_IM_VSIZE_Pos))) +#define ISI_CFG2_GS_MODE (0x1u << 11) /**< \brief (ISI_CFG2) Grayscale Pixel Format Mode */ +#define ISI_CFG2_RGB_MODE (0x1u << 12) /**< \brief (ISI_CFG2) RGB Input Mode */ +#define ISI_CFG2_GRAYSCALE (0x1u << 13) /**< \brief (ISI_CFG2) Grayscale Mode Format Enable */ +#define ISI_CFG2_RGB_SWAP (0x1u << 14) /**< \brief (ISI_CFG2) RGB Format Swap Mode */ +#define ISI_CFG2_COL_SPACE (0x1u << 15) /**< \brief (ISI_CFG2) Color Space for the Image Data */ +#define ISI_CFG2_IM_HSIZE_Pos 16 +#define ISI_CFG2_IM_HSIZE_Msk (0x7ffu << ISI_CFG2_IM_HSIZE_Pos) /**< \brief (ISI_CFG2) Horizontal Size of the Image Sensor [0..2047] */ +#define ISI_CFG2_IM_HSIZE(value) ((ISI_CFG2_IM_HSIZE_Msk & ((value) << ISI_CFG2_IM_HSIZE_Pos))) +#define ISI_CFG2_YCC_SWAP_Pos 28 +#define ISI_CFG2_YCC_SWAP_Msk (0x3u << ISI_CFG2_YCC_SWAP_Pos) /**< \brief (ISI_CFG2) YCrCb Format Swap Mode */ +#define ISI_CFG2_YCC_SWAP(value) ((ISI_CFG2_YCC_SWAP_Msk & ((value) << ISI_CFG2_YCC_SWAP_Pos))) +#define ISI_CFG2_YCC_SWAP_DEFAULT (0x0u << 28) /**< \brief (ISI_CFG2) Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE1 (0x1u << 28) /**< \brief (ISI_CFG2) Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) */ +#define ISI_CFG2_YCC_SWAP_MODE2 (0x2u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) */ +#define ISI_CFG2_YCC_SWAP_MODE3 (0x3u << 28) /**< \brief (ISI_CFG2) Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) */ +#define ISI_CFG2_RGB_CFG_Pos 30 +#define ISI_CFG2_RGB_CFG_Msk (0x3u << ISI_CFG2_RGB_CFG_Pos) /**< \brief (ISI_CFG2) RGB Pixel Mapping Configuration */ +#define ISI_CFG2_RGB_CFG(value) ((ISI_CFG2_RGB_CFG_Msk & ((value) << ISI_CFG2_RGB_CFG_Pos))) +#define ISI_CFG2_RGB_CFG_DEFAULT (0x0u << 30) /**< \brief (ISI_CFG2) Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B */ +#define ISI_CFG2_RGB_CFG_MODE1 (0x1u << 30) /**< \brief (ISI_CFG2) Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R */ +#define ISI_CFG2_RGB_CFG_MODE2 (0x2u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) */ +#define ISI_CFG2_RGB_CFG_MODE3 (0x3u << 30) /**< \brief (ISI_CFG2) Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) */ +/* -------- ISI_PSIZE : (ISI Offset: 0x08) ISI Preview Size Register -------- */ +#define ISI_PSIZE_PREV_VSIZE_Pos 0 +#define ISI_PSIZE_PREV_VSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_VSIZE_Pos) /**< \brief (ISI_PSIZE) Vertical Size for the Preview Path */ +#define ISI_PSIZE_PREV_VSIZE(value) ((ISI_PSIZE_PREV_VSIZE_Msk & ((value) << ISI_PSIZE_PREV_VSIZE_Pos))) +#define ISI_PSIZE_PREV_HSIZE_Pos 16 +#define ISI_PSIZE_PREV_HSIZE_Msk (0x3ffu << ISI_PSIZE_PREV_HSIZE_Pos) /**< \brief (ISI_PSIZE) Horizontal Size for the Preview Path */ +#define ISI_PSIZE_PREV_HSIZE(value) ((ISI_PSIZE_PREV_HSIZE_Msk & ((value) << ISI_PSIZE_PREV_HSIZE_Pos))) +/* -------- ISI_PDECF : (ISI Offset: 0x0C) ISI Preview Decimation Factor Register -------- */ +#define ISI_PDECF_DEC_FACTOR_Pos 0 +#define ISI_PDECF_DEC_FACTOR_Msk (0xffu << ISI_PDECF_DEC_FACTOR_Pos) /**< \brief (ISI_PDECF) Decimation Factor */ +#define ISI_PDECF_DEC_FACTOR(value) ((ISI_PDECF_DEC_FACTOR_Msk & ((value) << ISI_PDECF_DEC_FACTOR_Pos))) +/* -------- ISI_Y2R_SET0 : (ISI Offset: 0x10) ISI Color Space Conversion YCrCb To RGB Set 0 Register -------- */ +#define ISI_Y2R_SET0_C0_Pos 0 +#define ISI_Y2R_SET0_C0_Msk (0xffu << ISI_Y2R_SET0_C0_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_Y2R_SET0_C0(value) ((ISI_Y2R_SET0_C0_Msk & ((value) << ISI_Y2R_SET0_C0_Pos))) +#define ISI_Y2R_SET0_C1_Pos 8 +#define ISI_Y2R_SET0_C1_Msk (0xffu << ISI_Y2R_SET0_C1_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_Y2R_SET0_C1(value) ((ISI_Y2R_SET0_C1_Msk & ((value) << ISI_Y2R_SET0_C1_Pos))) +#define ISI_Y2R_SET0_C2_Pos 16 +#define ISI_Y2R_SET0_C2_Msk (0xffu << ISI_Y2R_SET0_C2_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_Y2R_SET0_C2(value) ((ISI_Y2R_SET0_C2_Msk & ((value) << ISI_Y2R_SET0_C2_Pos))) +#define ISI_Y2R_SET0_C3_Pos 24 +#define ISI_Y2R_SET0_C3_Msk (0xffu << ISI_Y2R_SET0_C3_Pos) /**< \brief (ISI_Y2R_SET0) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_Y2R_SET0_C3(value) ((ISI_Y2R_SET0_C3_Msk & ((value) << ISI_Y2R_SET0_C3_Pos))) +/* -------- ISI_Y2R_SET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb To RGB Set 1 Register -------- */ +#define ISI_Y2R_SET1_C4_Pos 0 +#define ISI_Y2R_SET1_C4_Msk (0x1ffu << ISI_Y2R_SET1_C4_Pos) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_Y2R_SET1_C4(value) ((ISI_Y2R_SET1_C4_Msk & ((value) << ISI_Y2R_SET1_C4_Pos))) +#define ISI_Y2R_SET1_Yoff (0x1u << 12) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Luminance Default Offset */ +#define ISI_Y2R_SET1_Croff (0x1u << 13) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Red Chrominance Default Offset */ +#define ISI_Y2R_SET1_Cboff (0x1u << 14) /**< \brief (ISI_Y2R_SET1) Color Space Conversion Blue Chrominance Default Offset */ +/* -------- ISI_R2Y_SET0 : (ISI Offset: 0x18) ISI Color Space Conversion RGB To YCrCb Set 0 Register -------- */ +#define ISI_R2Y_SET0_C0_Pos 0 +#define ISI_R2Y_SET0_C0_Msk (0x7fu << ISI_R2Y_SET0_C0_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C0 */ +#define ISI_R2Y_SET0_C0(value) ((ISI_R2Y_SET0_C0_Msk & ((value) << ISI_R2Y_SET0_C0_Pos))) +#define ISI_R2Y_SET0_C1_Pos 8 +#define ISI_R2Y_SET0_C1_Msk (0x7fu << ISI_R2Y_SET0_C1_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C1 */ +#define ISI_R2Y_SET0_C1(value) ((ISI_R2Y_SET0_C1_Msk & ((value) << ISI_R2Y_SET0_C1_Pos))) +#define ISI_R2Y_SET0_C2_Pos 16 +#define ISI_R2Y_SET0_C2_Msk (0x7fu << ISI_R2Y_SET0_C2_Pos) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Matrix Coefficient C2 */ +#define ISI_R2Y_SET0_C2(value) ((ISI_R2Y_SET0_C2_Msk & ((value) << ISI_R2Y_SET0_C2_Pos))) +#define ISI_R2Y_SET0_Roff (0x1u << 24) /**< \brief (ISI_R2Y_SET0) Color Space Conversion Red Component Offset */ +/* -------- ISI_R2Y_SET1 : (ISI Offset: 0x1C) ISI Color Space Conversion RGB To YCrCb Set 1 Register -------- */ +#define ISI_R2Y_SET1_C3_Pos 0 +#define ISI_R2Y_SET1_C3_Msk (0x7fu << ISI_R2Y_SET1_C3_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C3 */ +#define ISI_R2Y_SET1_C3(value) ((ISI_R2Y_SET1_C3_Msk & ((value) << ISI_R2Y_SET1_C3_Pos))) +#define ISI_R2Y_SET1_C4_Pos 8 +#define ISI_R2Y_SET1_C4_Msk (0x7fu << ISI_R2Y_SET1_C4_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C4 */ +#define ISI_R2Y_SET1_C4(value) ((ISI_R2Y_SET1_C4_Msk & ((value) << ISI_R2Y_SET1_C4_Pos))) +#define ISI_R2Y_SET1_C5_Pos 16 +#define ISI_R2Y_SET1_C5_Msk (0x7fu << ISI_R2Y_SET1_C5_Pos) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Matrix Coefficient C5 */ +#define ISI_R2Y_SET1_C5(value) ((ISI_R2Y_SET1_C5_Msk & ((value) << ISI_R2Y_SET1_C5_Pos))) +#define ISI_R2Y_SET1_Goff (0x1u << 24) /**< \brief (ISI_R2Y_SET1) Color Space Conversion Green Component Offset */ +/* -------- ISI_R2Y_SET2 : (ISI Offset: 0x20) ISI Color Space Conversion RGB To YCrCb Set 2 Register -------- */ +#define ISI_R2Y_SET2_C6_Pos 0 +#define ISI_R2Y_SET2_C6_Msk (0x7fu << ISI_R2Y_SET2_C6_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C6 */ +#define ISI_R2Y_SET2_C6(value) ((ISI_R2Y_SET2_C6_Msk & ((value) << ISI_R2Y_SET2_C6_Pos))) +#define ISI_R2Y_SET2_C7_Pos 8 +#define ISI_R2Y_SET2_C7_Msk (0x7fu << ISI_R2Y_SET2_C7_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C7 */ +#define ISI_R2Y_SET2_C7(value) ((ISI_R2Y_SET2_C7_Msk & ((value) << ISI_R2Y_SET2_C7_Pos))) +#define ISI_R2Y_SET2_C8_Pos 16 +#define ISI_R2Y_SET2_C8_Msk (0x7fu << ISI_R2Y_SET2_C8_Pos) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Matrix Coefficient C8 */ +#define ISI_R2Y_SET2_C8(value) ((ISI_R2Y_SET2_C8_Msk & ((value) << ISI_R2Y_SET2_C8_Pos))) +#define ISI_R2Y_SET2_Boff (0x1u << 24) /**< \brief (ISI_R2Y_SET2) Color Space Conversion Blue Component Offset */ +/* -------- ISI_CR : (ISI Offset: 0x24) ISI Control Register -------- */ +#define ISI_CR_ISI_EN (0x1u << 0) /**< \brief (ISI_CR) ISI Module Enable Request */ +#define ISI_CR_ISI_DIS (0x1u << 1) /**< \brief (ISI_CR) ISI Module Disable Request */ +#define ISI_CR_ISI_SRST (0x1u << 2) /**< \brief (ISI_CR) ISI Software Reset Request */ +#define ISI_CR_ISI_CDC (0x1u << 8) /**< \brief (ISI_CR) ISI Codec Request */ +/* -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- */ +#define ISI_SR_ENABLE (0x1u << 0) /**< \brief (ISI_SR) Module Enable */ +#define ISI_SR_DIS_DONE (0x1u << 1) /**< \brief (ISI_SR) Module Disable Request has Terminated (cleared on read) */ +#define ISI_SR_SRST (0x1u << 2) /**< \brief (ISI_SR) Module Software Reset Request has Terminated (cleared on read) */ +#define ISI_SR_CDC_PND (0x1u << 8) /**< \brief (ISI_SR) Pending Codec Request */ +#define ISI_SR_VSYNC (0x1u << 10) /**< \brief (ISI_SR) Vertical Synchronization (cleared on read) */ +#define ISI_SR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_SR) Preview DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_SR) Codec DMA Transfer has Terminated (cleared on read) */ +#define ISI_SR_SIP (0x1u << 19) /**< \brief (ISI_SR) Synchronization in Progress */ +#define ISI_SR_P_OVR (0x1u << 24) /**< \brief (ISI_SR) Preview Datapath Overflow (cleared on read) */ +#define ISI_SR_C_OVR (0x1u << 25) /**< \brief (ISI_SR) Codec Datapath Overflow (cleared on read) */ +#define ISI_SR_CRC_ERR (0x1u << 26) /**< \brief (ISI_SR) CRC Synchronization Error (cleared on read) */ +#define ISI_SR_FR_OVR (0x1u << 27) /**< \brief (ISI_SR) Frame Rate Overrun (cleared on read) */ +/* -------- ISI_IER : (ISI Offset: 0x2C) ISI Interrupt Enable Register -------- */ +#define ISI_IER_DIS_DONE (0x1u << 1) /**< \brief (ISI_IER) Disable Done Interrupt Enable */ +#define ISI_IER_SRST (0x1u << 2) /**< \brief (ISI_IER) Software Reset Interrupt Enable */ +#define ISI_IER_VSYNC (0x1u << 10) /**< \brief (ISI_IER) Vertical Synchronization Interrupt Enable */ +#define ISI_IER_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IER) Preview DMA Transfer Done Interrupt Enable */ +#define ISI_IER_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IER) Codec DMA Transfer Done Interrupt Enable */ +#define ISI_IER_P_OVR (0x1u << 24) /**< \brief (ISI_IER) Preview Datapath Overflow Interrupt Enable */ +#define ISI_IER_C_OVR (0x1u << 25) /**< \brief (ISI_IER) Codec Datapath Overflow Interrupt Enable */ +#define ISI_IER_CRC_ERR (0x1u << 26) /**< \brief (ISI_IER) Embedded Synchronization CRC Error Interrupt Enable */ +#define ISI_IER_FR_OVR (0x1u << 27) /**< \brief (ISI_IER) Frame Rate Overflow Interrupt Enable */ +/* -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- */ +#define ISI_IDR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IDR) Disable Done Interrupt Disable */ +#define ISI_IDR_SRST (0x1u << 2) /**< \brief (ISI_IDR) Software Reset Interrupt Disable */ +#define ISI_IDR_VSYNC (0x1u << 10) /**< \brief (ISI_IDR) Vertical Synchronization Interrupt Disable */ +#define ISI_IDR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IDR) Preview DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IDR) Codec DMA Transfer Done Interrupt Disable */ +#define ISI_IDR_P_OVR (0x1u << 24) /**< \brief (ISI_IDR) Preview Datapath Overflow Interrupt Disable */ +#define ISI_IDR_C_OVR (0x1u << 25) /**< \brief (ISI_IDR) Codec Datapath Overflow Interrupt Disable */ +#define ISI_IDR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IDR) Embedded Synchronization CRC Error Interrupt Disable */ +#define ISI_IDR_FR_OVR (0x1u << 27) /**< \brief (ISI_IDR) Frame Rate Overflow Interrupt Disable */ +/* -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- */ +#define ISI_IMR_DIS_DONE (0x1u << 1) /**< \brief (ISI_IMR) Module Disable Operation Completed */ +#define ISI_IMR_SRST (0x1u << 2) /**< \brief (ISI_IMR) Software Reset Completed */ +#define ISI_IMR_VSYNC (0x1u << 10) /**< \brief (ISI_IMR) Vertical Synchronization */ +#define ISI_IMR_PXFR_DONE (0x1u << 16) /**< \brief (ISI_IMR) Preview DMA Transfer Completed */ +#define ISI_IMR_CXFR_DONE (0x1u << 17) /**< \brief (ISI_IMR) Codec DMA Transfer Completed */ +#define ISI_IMR_P_OVR (0x1u << 24) /**< \brief (ISI_IMR) Preview FIFO Overflow */ +#define ISI_IMR_C_OVR (0x1u << 25) /**< \brief (ISI_IMR) Codec FIFO Overflow */ +#define ISI_IMR_CRC_ERR (0x1u << 26) /**< \brief (ISI_IMR) CRC Synchronization Error */ +#define ISI_IMR_FR_OVR (0x1u << 27) /**< \brief (ISI_IMR) Frame Rate Overrun */ +/* -------- ISI_DMA_CHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- */ +#define ISI_DMA_CHER_P_CH_EN (0x1u << 0) /**< \brief (ISI_DMA_CHER) Preview Channel Enable */ +#define ISI_DMA_CHER_C_CH_EN (0x1u << 1) /**< \brief (ISI_DMA_CHER) Codec Channel Enable */ +/* -------- ISI_DMA_CHDR : (ISI Offset: 0x3C) DMA Channel Disable Register -------- */ +#define ISI_DMA_CHDR_P_CH_DIS (0x1u << 0) /**< \brief (ISI_DMA_CHDR) Preview Channel Disable Request */ +#define ISI_DMA_CHDR_C_CH_DIS (0x1u << 1) /**< \brief (ISI_DMA_CHDR) Codec Channel Disable Request */ +/* -------- ISI_DMA_CHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- */ +#define ISI_DMA_CHSR_P_CH_S (0x1u << 0) /**< \brief (ISI_DMA_CHSR) Preview DMA Channel Status */ +#define ISI_DMA_CHSR_C_CH_S (0x1u << 1) /**< \brief (ISI_DMA_CHSR) Code DMA Channel Status */ +/* -------- ISI_DMA_P_ADDR : (ISI Offset: 0x44) DMA Preview Base Address Register -------- */ +#define ISI_DMA_P_ADDR_P_ADDR_Pos 2 +#define ISI_DMA_P_ADDR_P_ADDR_Msk (0x3fffffffu << ISI_DMA_P_ADDR_P_ADDR_Pos) /**< \brief (ISI_DMA_P_ADDR) Preview Image Base Address */ +#define ISI_DMA_P_ADDR_P_ADDR(value) ((ISI_DMA_P_ADDR_P_ADDR_Msk & ((value) << ISI_DMA_P_ADDR_P_ADDR_Pos))) +/* -------- ISI_DMA_P_CTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- */ +#define ISI_DMA_P_CTRL_P_FETCH (0x1u << 0) /**< \brief (ISI_DMA_P_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_P_CTRL_P_WB (0x1u << 1) /**< \brief (ISI_DMA_P_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_P_CTRL_P_IEN (0x1u << 2) /**< \brief (ISI_DMA_P_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_P_CTRL_P_DONE (0x1u << 3) /**< \brief (ISI_DMA_P_CTRL) Preview Transfer Done */ +/* -------- ISI_DMA_P_DSCR : (ISI Offset: 0x4C) DMA Preview Descriptor Address Register -------- */ +#define ISI_DMA_P_DSCR_P_DSCR_Pos 2 +#define ISI_DMA_P_DSCR_P_DSCR_Msk (0x3fffffffu << ISI_DMA_P_DSCR_P_DSCR_Pos) /**< \brief (ISI_DMA_P_DSCR) Preview Descriptor Base Address */ +#define ISI_DMA_P_DSCR_P_DSCR(value) ((ISI_DMA_P_DSCR_P_DSCR_Msk & ((value) << ISI_DMA_P_DSCR_P_DSCR_Pos))) +/* -------- ISI_DMA_C_ADDR : (ISI Offset: 0x50) DMA Codec Base Address Register -------- */ +#define ISI_DMA_C_ADDR_C_ADDR_Pos 2 +#define ISI_DMA_C_ADDR_C_ADDR_Msk (0x3fffffffu << ISI_DMA_C_ADDR_C_ADDR_Pos) /**< \brief (ISI_DMA_C_ADDR) Codec Image Base Address */ +#define ISI_DMA_C_ADDR_C_ADDR(value) ((ISI_DMA_C_ADDR_C_ADDR_Msk & ((value) << ISI_DMA_C_ADDR_C_ADDR_Pos))) +/* -------- ISI_DMA_C_CTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- */ +#define ISI_DMA_C_CTRL_C_FETCH (0x1u << 0) /**< \brief (ISI_DMA_C_CTRL) Descriptor Fetch Control Bit */ +#define ISI_DMA_C_CTRL_C_WB (0x1u << 1) /**< \brief (ISI_DMA_C_CTRL) Descriptor Writeback Control Bit */ +#define ISI_DMA_C_CTRL_C_IEN (0x1u << 2) /**< \brief (ISI_DMA_C_CTRL) Transfer Done Flag Control */ +#define ISI_DMA_C_CTRL_C_DONE (0x1u << 3) /**< \brief (ISI_DMA_C_CTRL) Codec Transfer Done */ +/* -------- ISI_DMA_C_DSCR : (ISI Offset: 0x58) DMA Codec Descriptor Address Register -------- */ +#define ISI_DMA_C_DSCR_C_DSCR_Pos 2 +#define ISI_DMA_C_DSCR_C_DSCR_Msk (0x3fffffffu << ISI_DMA_C_DSCR_C_DSCR_Pos) /**< \brief (ISI_DMA_C_DSCR) Codec Descriptor Base Address */ +#define ISI_DMA_C_DSCR_C_DSCR(value) ((ISI_DMA_C_DSCR_C_DSCR_Msk & ((value) << ISI_DMA_C_DSCR_C_DSCR_Pos))) +/* -------- ISI_WPMR : (ISI Offset: 0xE4) Write Protection Mode Register -------- */ +#define ISI_WPMR_WPEN (0x1u << 0) /**< \brief (ISI_WPMR) Write Protection Enable */ +#define ISI_WPMR_WPKEY_Pos 8 +#define ISI_WPMR_WPKEY_Msk (0xffffffu << ISI_WPMR_WPKEY_Pos) /**< \brief (ISI_WPMR) Write Protection Key Password */ +#define ISI_WPMR_WPKEY(value) ((ISI_WPMR_WPKEY_Msk & ((value) << ISI_WPMR_WPKEY_Pos))) +#define ISI_WPMR_WPKEY_PASSWD (0x495349u << 8) /**< \brief (ISI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- ISI_WPSR : (ISI Offset: 0xE8) Write Protection Status Register -------- */ +#define ISI_WPSR_WPVS (0x1u << 0) /**< \brief (ISI_WPSR) Write Protection Violation Status */ +#define ISI_WPSR_WPVSRC_Pos 8 +#define ISI_WPSR_WPVSRC_Msk (0xffffu << ISI_WPSR_WPVSRC_Pos) /**< \brief (ISI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_ISI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_matrix.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_matrix.h new file mode 100644 index 000000000..caec597a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_matrix.h @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MATRIX_COMPONENT_ +#define _SAMV71_MATRIX_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR AHB Bus Matrix */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MATRIX AHB Bus Matrix */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief MatrixPr hardware registers */ +typedef struct { + __IO uint32_t MATRIX_PRAS; /**< \brief (MatrixPr Offset: 0x0) Priority Register A for Slave 0 */ + __IO uint32_t MATRIX_PRBS; /**< \brief (MatrixPr Offset: 0x4) Priority Register B for Slave 0 */ +} MatrixPr; +/** \brief Matrix hardware registers */ +#define MATRIXPR_NUMBER 9 +typedef struct { + __IO uint32_t MATRIX_MCFG[12]; /**< \brief (Matrix Offset: 0x0000) Master Configuration Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t MATRIX_SCFG[9]; /**< \brief (Matrix Offset: 0x0040) Slave Configuration Register */ + __I uint32_t Reserved2[7]; + MatrixPr MATRIX_PR[MATRIXPR_NUMBER]; /**< \brief (Matrix Offset: 0x0080) 0 .. 8 */ + __I uint32_t Reserved3[14]; + __IO uint32_t MATRIX_MRCR; /**< \brief (Matrix Offset: 0x0100) Master Remap Control Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t CCFG_CAN0; /**< \brief (Matrix Offset: 0x0110) CAN0 Configuration Register */ + __IO uint32_t CCFG_SYSIO; /**< \brief (Matrix Offset: 0x0114) System I/O and CAN1 Configuration Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t CCFG_SMCNFCS; /**< \brief (Matrix Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register */ + __I uint32_t Reserved6[47]; + __IO uint32_t MATRIX_WPMR; /**< \brief (Matrix Offset: 0x01E4) Write Protection Mode Register */ + __I uint32_t MATRIX_WPSR; /**< \brief (Matrix Offset: 0x01E8) Write Protection Status Register */ +} Matrix; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MATRIX_MCFG[12] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ +#define MATRIX_MCFG_ULBT_Pos 0 +#define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /**< \brief (MATRIX_MCFG[12]) Undefined Length Burst Type */ +#define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) +#define MATRIX_MCFG_ULBT_UNLTD_LENGTH (0x0u << 0) /**< \brief (MATRIX_MCFG[12]) Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. */ +#define MATRIX_MCFG_ULBT_SINGLE_ACCESS (0x1u << 0) /**< \brief (MATRIX_MCFG[12]) Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. */ +#define MATRIX_MCFG_ULBT_4BEAT_BURST (0x2u << 0) /**< \brief (MATRIX_MCFG[12]) 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. */ +#define MATRIX_MCFG_ULBT_8BEAT_BURST (0x3u << 0) /**< \brief (MATRIX_MCFG[12]) 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. */ +#define MATRIX_MCFG_ULBT_16BEAT_BURST (0x4u << 0) /**< \brief (MATRIX_MCFG[12]) 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. */ +#define MATRIX_MCFG_ULBT_32BEAT_BURST (0x5u << 0) /**< \brief (MATRIX_MCFG[12]) 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. */ +#define MATRIX_MCFG_ULBT_64BEAT_BURST (0x6u << 0) /**< \brief (MATRIX_MCFG[12]) 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. */ +#define MATRIX_MCFG_ULBT_128BEAT_BURST (0x7u << 0) /**< \brief (MATRIX_MCFG[12]) 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. */ +/* -------- MATRIX_SCFG[9] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ +#define MATRIX_SCFG_SLOT_CYCLE_Pos 0 +#define MATRIX_SCFG_SLOT_CYCLE_Msk (0x1ffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /**< \brief (MATRIX_SCFG[9]) Maximum Bus Grant Duration for Masters */ +#define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 +#define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /**< \brief (MATRIX_SCFG[9]) Default Master Type */ +#define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) +#define MATRIX_SCFG_DEFMSTR_TYPE_NONE (0x0u << 16) /**< \brief (MATRIX_SCFG[9]) No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_LAST (0x1u << 16) /**< \brief (MATRIX_SCFG[9]) Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. */ +#define MATRIX_SCFG_DEFMSTR_TYPE_FIXED (0x2u << 16) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. */ +#define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 +#define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0xfu << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /**< \brief (MATRIX_SCFG[9]) Fixed Default Master */ +#define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) +/* -------- MATRIX_PRAS : (MATRIX Offset: N/A) Priority Register A for Slave 0 -------- */ +#define MATRIX_PRAS_M0PR_Pos 0 +#define MATRIX_PRAS_M0PR_Msk (0x3u << MATRIX_PRAS_M0PR_Pos) /**< \brief (MATRIX_PRAS) Master 0 Priority */ +#define MATRIX_PRAS_M0PR(value) ((MATRIX_PRAS_M0PR_Msk & ((value) << MATRIX_PRAS_M0PR_Pos))) +#define MATRIX_PRAS_M1PR_Pos 4 +#define MATRIX_PRAS_M1PR_Msk (0x3u << MATRIX_PRAS_M1PR_Pos) /**< \brief (MATRIX_PRAS) Master 1 Priority */ +#define MATRIX_PRAS_M1PR(value) ((MATRIX_PRAS_M1PR_Msk & ((value) << MATRIX_PRAS_M1PR_Pos))) +#define MATRIX_PRAS_M2PR_Pos 8 +#define MATRIX_PRAS_M2PR_Msk (0x3u << MATRIX_PRAS_M2PR_Pos) /**< \brief (MATRIX_PRAS) Master 2 Priority */ +#define MATRIX_PRAS_M2PR(value) ((MATRIX_PRAS_M2PR_Msk & ((value) << MATRIX_PRAS_M2PR_Pos))) +#define MATRIX_PRAS_M3PR_Pos 12 +#define MATRIX_PRAS_M3PR_Msk (0x3u << MATRIX_PRAS_M3PR_Pos) /**< \brief (MATRIX_PRAS) Master 3 Priority */ +#define MATRIX_PRAS_M3PR(value) ((MATRIX_PRAS_M3PR_Msk & ((value) << MATRIX_PRAS_M3PR_Pos))) +#define MATRIX_PRAS_M4PR_Pos 16 +#define MATRIX_PRAS_M4PR_Msk (0x3u << MATRIX_PRAS_M4PR_Pos) /**< \brief (MATRIX_PRAS) Master 4 Priority */ +#define MATRIX_PRAS_M4PR(value) ((MATRIX_PRAS_M4PR_Msk & ((value) << MATRIX_PRAS_M4PR_Pos))) +#define MATRIX_PRAS_M5PR_Pos 20 +#define MATRIX_PRAS_M5PR_Msk (0x3u << MATRIX_PRAS_M5PR_Pos) /**< \brief (MATRIX_PRAS) Master 5 Priority */ +#define MATRIX_PRAS_M5PR(value) ((MATRIX_PRAS_M5PR_Msk & ((value) << MATRIX_PRAS_M5PR_Pos))) +#define MATRIX_PRAS_M6PR_Pos 24 +#define MATRIX_PRAS_M6PR_Msk (0x3u << MATRIX_PRAS_M6PR_Pos) /**< \brief (MATRIX_PRAS) Master 6 Priority */ +#define MATRIX_PRAS_M6PR(value) ((MATRIX_PRAS_M6PR_Msk & ((value) << MATRIX_PRAS_M6PR_Pos))) +#define MATRIX_PRAS_M7PR_Pos 28 +#define MATRIX_PRAS_M7PR_Msk (0x3u << MATRIX_PRAS_M7PR_Pos) /**< \brief (MATRIX_PRAS) Master 7 Priority */ +#define MATRIX_PRAS_M7PR(value) ((MATRIX_PRAS_M7PR_Msk & ((value) << MATRIX_PRAS_M7PR_Pos))) +/* -------- MATRIX_PRBS : (MATRIX Offset: N/A) Priority Register B for Slave 0 -------- */ +#define MATRIX_PRBS_M8PR_Pos 0 +#define MATRIX_PRBS_M8PR_Msk (0x3u << MATRIX_PRBS_M8PR_Pos) /**< \brief (MATRIX_PRBS) Master 8 Priority */ +#define MATRIX_PRBS_M8PR(value) ((MATRIX_PRBS_M8PR_Msk & ((value) << MATRIX_PRBS_M8PR_Pos))) +#define MATRIX_PRBS_M9PR_Pos 4 +#define MATRIX_PRBS_M9PR_Msk (0x3u << MATRIX_PRBS_M9PR_Pos) /**< \brief (MATRIX_PRBS) Master 9 Priority */ +#define MATRIX_PRBS_M9PR(value) ((MATRIX_PRBS_M9PR_Msk & ((value) << MATRIX_PRBS_M9PR_Pos))) +#define MATRIX_PRBS_M10PR_Pos 8 +#define MATRIX_PRBS_M10PR_Msk (0x3u << MATRIX_PRBS_M10PR_Pos) /**< \brief (MATRIX_PRBS) Master 10 Priority */ +#define MATRIX_PRBS_M10PR(value) ((MATRIX_PRBS_M10PR_Msk & ((value) << MATRIX_PRBS_M10PR_Pos))) +#define MATRIX_PRBS_M11PR_Pos 12 +#define MATRIX_PRBS_M11PR_Msk (0x3u << MATRIX_PRBS_M11PR_Pos) /**< \brief (MATRIX_PRBS) Master 11 Priority */ +#define MATRIX_PRBS_M11PR(value) ((MATRIX_PRBS_M11PR_Msk & ((value) << MATRIX_PRBS_M11PR_Pos))) +/* -------- MATRIX_MRCR : (MATRIX Offset: 0x0100) Master Remap Control Register -------- */ +#define MATRIX_MRCR_RCB0 (0x1u << 0) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 0 */ +#define MATRIX_MRCR_RCB1 (0x1u << 1) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 1 */ +#define MATRIX_MRCR_RCB2 (0x1u << 2) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 2 */ +#define MATRIX_MRCR_RCB3 (0x1u << 3) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 3 */ +#define MATRIX_MRCR_RCB4 (0x1u << 4) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 4 */ +#define MATRIX_MRCR_RCB5 (0x1u << 5) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 5 */ +#define MATRIX_MRCR_RCB6 (0x1u << 6) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 6 */ +#define MATRIX_MRCR_RCB7 (0x1u << 7) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 7 */ +#define MATRIX_MRCR_RCB8 (0x1u << 8) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 8 */ +#define MATRIX_MRCR_RCB9 (0x1u << 9) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 9 */ +#define MATRIX_MRCR_RCB10 (0x1u << 10) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 10 */ +#define MATRIX_MRCR_RCB11 (0x1u << 11) /**< \brief (MATRIX_MRCR) Remap Command Bit for Master 11 */ +/* -------- CCFG_CAN0 : (MATRIX Offset: 0x0110) CAN0 Configuration Register -------- */ +#define CCFG_CAN0_CAN0DMABA_Pos 16 +#define CCFG_CAN0_CAN0DMABA_Msk (0xffffu << CCFG_CAN0_CAN0DMABA_Pos) /**< \brief (CCFG_CAN0) CAN0 DMA Base Address */ +#define CCFG_CAN0_CAN0DMABA(value) ((CCFG_CAN0_CAN0DMABA_Msk & ((value) << CCFG_CAN0_CAN0DMABA_Pos))) +/* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O and CAN1 Configuration Register -------- */ +#define CCFG_SYSIO_SYSIO4 (0x1u << 4) /**< \brief (CCFG_SYSIO) PB4 or TDI Assignment */ +#define CCFG_SYSIO_SYSIO5 (0x1u << 5) /**< \brief (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ +#define CCFG_SYSIO_SYSIO6 (0x1u << 6) /**< \brief (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ +#define CCFG_SYSIO_SYSIO7 (0x1u << 7) /**< \brief (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ +#define CCFG_SYSIO_SYSIO12 (0x1u << 12) /**< \brief (CCFG_SYSIO) PB12 or ERASE Assignment */ +#define CCFG_SYSIO_CAN1DMABA_Pos 16 +#define CCFG_SYSIO_CAN1DMABA_Msk (0xffffu << CCFG_SYSIO_CAN1DMABA_Pos) /**< \brief (CCFG_SYSIO) CAN0 DMA Base Address */ +#define CCFG_SYSIO_CAN1DMABA(value) ((CCFG_SYSIO_CAN1DMABA_Msk & ((value) << CCFG_SYSIO_CAN1DMABA_Pos))) +/* -------- CCFG_SMCNFCS : (MATRIX Offset: 0x0124) SMC NAND Flash Chip Select Configuration Register -------- */ +#define CCFG_SMCNFCS_SMC_NFCS0 (0x1u << 0) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 0 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS1 (0x1u << 1) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 1 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS2 (0x1u << 2) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 2 Assignment */ +#define CCFG_SMCNFCS_SMC_NFCS3 (0x1u << 3) /**< \brief (CCFG_SMCNFCS) SMC NAND Flash Chip Select 3 Assignment */ +#define CCFG_SMCNFCS_SDRAMEN (0x1u << 4) /**< \brief (CCFG_SMCNFCS) SDRAM Enable */ +/* -------- MATRIX_WPMR : (MATRIX Offset: 0x01E4) Write Protection Mode Register -------- */ +#define MATRIX_WPMR_WPEN (0x1u << 0) /**< \brief (MATRIX_WPMR) Write Protection Enable */ +#define MATRIX_WPMR_WPKEY_Pos 8 +#define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /**< \brief (MATRIX_WPMR) Write Protection Key */ +#define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) +#define MATRIX_WPMR_WPKEY_PASSWD (0x4D4154u << 8) /**< \brief (MATRIX_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- MATRIX_WPSR : (MATRIX Offset: 0x01E8) Write Protection Status Register -------- */ +#define MATRIX_WPSR_WPVS (0x1u << 0) /**< \brief (MATRIX_WPSR) Write Protection Violation Status */ +#define MATRIX_WPSR_WPVSRC_Pos 8 +#define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /**< \brief (MATRIX_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_MATRIX_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_mcan.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_mcan.h new file mode 100644 index 000000000..033a4e2eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_mcan.h @@ -0,0 +1,845 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN_COMPONENT_ +#define _SAMV71_MCAN_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Controller Area Network */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MCAN Controller Area Network */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mcan hardware registers */ +typedef struct { + __I uint32_t Reserved1[2]; + __IO uint32_t MCAN_CUST; /**< \brief (Mcan Offset: 0x08) Customer Register */ + __IO uint32_t MCAN_FBTP; /**< \brief (Mcan Offset: 0x0C) Fast Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TEST; /**< \brief (Mcan Offset: 0x10) Test Register */ + __IO uint32_t MCAN_RWD; /**< \brief (Mcan Offset: 0x14) RAM Watchdog Register */ + __IO uint32_t MCAN_CCCR; /**< \brief (Mcan Offset: 0x18) CC Control Register */ + __IO uint32_t MCAN_BTP; /**< \brief (Mcan Offset: 0x1C) Bit Timing and Prescaler Register */ + __IO uint32_t MCAN_TSCC; /**< \brief (Mcan Offset: 0x20) Timestamp Counter Configuration Register */ + __IO uint32_t MCAN_TSCV; /**< \brief (Mcan Offset: 0x24) Timestamp Counter Value Register */ + __IO uint32_t MCAN_TOCC; /**< \brief (Mcan Offset: 0x28) Timeout Counter Configuration Register */ + __IO uint32_t MCAN_TOCV; /**< \brief (Mcan Offset: 0x2C) Timeout Counter Value Register */ + __I uint32_t Reserved2[4]; + __I uint32_t MCAN_ECR; /**< \brief (Mcan Offset: 0x40) Error Counter Register */ + __I uint32_t MCAN_PSR; /**< \brief (Mcan Offset: 0x44) Protocol Status Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MCAN_IR; /**< \brief (Mcan Offset: 0x50) Interrupt Register */ + __IO uint32_t MCAN_IE; /**< \brief (Mcan Offset: 0x54) Interrupt Enable Register */ + __IO uint32_t MCAN_ILS; /**< \brief (Mcan Offset: 0x58) Interrupt Line Select Register */ + __IO uint32_t MCAN_ILE; /**< \brief (Mcan Offset: 0x5C) Interrupt Line Enable Register */ + __I uint32_t Reserved4[8]; + __IO uint32_t MCAN_GFC; /**< \brief (Mcan Offset: 0x80) Global Filter Configuration Register */ + __IO uint32_t MCAN_SIDFC; /**< \brief (Mcan Offset: 0x84) Standard ID Filter Configuration Register */ + __IO uint32_t MCAN_XIDFC; /**< \brief (Mcan Offset: 0x88) Extended ID Filter Configuration Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t MCAN_XIDAM; /**< \brief (Mcan Offset: 0x90) Extended ID AND Mask Register */ + __I uint32_t MCAN_HPMS; /**< \brief (Mcan Offset: 0x94) High Priority Message Status Register */ + __IO uint32_t MCAN_NDAT1; /**< \brief (Mcan Offset: 0x98) New Data 1 Register */ + __IO uint32_t MCAN_NDAT2; /**< \brief (Mcan Offset: 0x9C) New Data 2 Register */ + __IO uint32_t MCAN_RXF0C; /**< \brief (Mcan Offset: 0xA0) Receive FIFO 0 Configuration Register */ + __I uint32_t MCAN_RXF0S; /**< \brief (Mcan Offset: 0xA4) Receive FIFO 0 Status Register */ + __IO uint32_t MCAN_RXF0A; /**< \brief (Mcan Offset: 0xA8) Receive FIFO 0 Acknowledge Register */ + __IO uint32_t MCAN_RXBC; /**< \brief (Mcan Offset: 0xAC) Receive Rx Buffer Configuration Register */ + __IO uint32_t MCAN_RXF1C; /**< \brief (Mcan Offset: 0xB0) Receive FIFO 1 Configuration Register */ + __I uint32_t MCAN_RXF1S; /**< \brief (Mcan Offset: 0xB4) Receive FIFO 1 Status Register */ + __IO uint32_t MCAN_RXF1A; /**< \brief (Mcan Offset: 0xB8) Receive FIFO 1 Acknowledge Register */ + __IO uint32_t MCAN_RXESC; /**< \brief (Mcan Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register */ + __IO uint32_t MCAN_TXBC; /**< \brief (Mcan Offset: 0xC0) Transmit Buffer Configuration Register */ + __I uint32_t MCAN_TXFQS; /**< \brief (Mcan Offset: 0xC4) Transmit FIFO/Queue Status Register */ + __IO uint32_t MCAN_TXESC; /**< \brief (Mcan Offset: 0xC8) Transmit Buffer Element Size Configuration Register */ + __I uint32_t MCAN_TXBRP; /**< \brief (Mcan Offset: 0xCC) Transmit Buffer Request Pending Register */ + __IO uint32_t MCAN_TXBAR; /**< \brief (Mcan Offset: 0xD0) Transmit Buffer Add Request Register */ + __IO uint32_t MCAN_TXBCR; /**< \brief (Mcan Offset: 0xD4) Transmit Buffer Cancellation Request Register */ + __I uint32_t MCAN_TXBTO; /**< \brief (Mcan Offset: 0xD8) Transmit Buffer Transmission Occurred Register */ + __I uint32_t MCAN_TXBCF; /**< \brief (Mcan Offset: 0xDC) Transmit Buffer Cancellation Finished Register */ + __IO uint32_t MCAN_TXBTIE; /**< \brief (Mcan Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register */ + __IO uint32_t MCAN_TXBCIE; /**< \brief (Mcan Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + __I uint32_t Reserved6[2]; + __IO uint32_t MCAN_TXEFC; /**< \brief (Mcan Offset: 0xF0) Transmit Event FIFO Configuration Register */ + __I uint32_t MCAN_TXEFS; /**< \brief (Mcan Offset: 0xF4) Transmit Event FIFO Status Register */ + __IO uint32_t MCAN_TXEFA; /**< \brief (Mcan Offset: 0xF8) Transmit Event FIFO Acknowledge Register */ +} Mcan; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MCAN_CUST : (MCAN Offset: 0x08) Customer Register -------- */ +#define MCAN_CUST_CSV_Pos 0 +#define MCAN_CUST_CSV_Msk (0xffffffffu << MCAN_CUST_CSV_Pos) /**< \brief (MCAN_CUST) Customer-specific Value */ +#define MCAN_CUST_CSV(value) ((MCAN_CUST_CSV_Msk & ((value) << MCAN_CUST_CSV_Pos))) +/* -------- MCAN_FBTP : (MCAN Offset: 0x0C) Fast Bit Timing and Prescaler Register -------- */ +#define MCAN_FBTP_FSJW_Pos 0 +#define MCAN_FBTP_FSJW_Msk (0x3u << MCAN_FBTP_FSJW_Pos) /**< \brief (MCAN_FBTP) Fast (Re) Synchronization Jump Width */ +#define MCAN_FBTP_FSJW(value) ((MCAN_FBTP_FSJW_Msk & ((value) << MCAN_FBTP_FSJW_Pos))) +#define MCAN_FBTP_FTSEG2_Pos 4 +#define MCAN_FBTP_FTSEG2_Msk (0x7u << MCAN_FBTP_FTSEG2_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment After Sample Point */ +#define MCAN_FBTP_FTSEG2(value) ((MCAN_FBTP_FTSEG2_Msk & ((value) << MCAN_FBTP_FTSEG2_Pos))) +#define MCAN_FBTP_FTSEG1_Pos 8 +#define MCAN_FBTP_FTSEG1_Msk (0xfu << MCAN_FBTP_FTSEG1_Pos) /**< \brief (MCAN_FBTP) Fast Time Segment Before Sample Point */ +#define MCAN_FBTP_FTSEG1(value) ((MCAN_FBTP_FTSEG1_Msk & ((value) << MCAN_FBTP_FTSEG1_Pos))) +#define MCAN_FBTP_FBRP_Pos 16 +#define MCAN_FBTP_FBRP_Msk (0x1fu << MCAN_FBTP_FBRP_Pos) /**< \brief (MCAN_FBTP) Fast Baud Rate Prescaler */ +#define MCAN_FBTP_FBRP(value) ((MCAN_FBTP_FBRP_Msk & ((value) << MCAN_FBTP_FBRP_Pos))) +#define MCAN_FBTP_TDC (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation */ +#define MCAN_FBTP_TDC_DISABLED (0x0u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation disabled. */ +#define MCAN_FBTP_TDC_ENABLED (0x1u << 23) /**< \brief (MCAN_FBTP) Transceiver Delay Compensation enabled. */ +#define MCAN_FBTP_TDCO_Pos 24 +#define MCAN_FBTP_TDCO_Msk (0x1fu << MCAN_FBTP_TDCO_Pos) /**< \brief (MCAN_FBTP) Transce iver Delay Compensation Offset */ +#define MCAN_FBTP_TDCO(value) ((MCAN_FBTP_TDCO_Msk & ((value) << MCAN_FBTP_TDCO_Pos))) +/* -------- MCAN_TEST : (MCAN Offset: 0x10) Test Register -------- */ +#define MCAN_TEST_LBCK (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back Mode (read/write) */ +#define MCAN_TEST_LBCK_DISABLED (0x0u << 4) /**< \brief (MCAN_TEST) Reset value. Loop Back mode is disabled. */ +#define MCAN_TEST_LBCK_ENABLED (0x1u << 4) /**< \brief (MCAN_TEST) Loop Back mode is enabled (see Section 6.1.9). */ +#define MCAN_TEST_TX_Pos 5 +#define MCAN_TEST_TX_Msk (0x3u << MCAN_TEST_TX_Pos) /**< \brief (MCAN_TEST) Control of Transmit Pin (read/write) */ +#define MCAN_TEST_TX(value) ((MCAN_TEST_TX_Msk & ((value) << MCAN_TEST_TX_Pos))) +#define MCAN_TEST_TX_RESET (0x0u << 5) /**< \brief (MCAN_TEST) Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. */ +#define MCAN_TEST_TX_SAMPLE_POINT_MONITORING (0x1u << 5) /**< \brief (MCAN_TEST) Sample Point can be monitored at pin CANTX. */ +#define MCAN_TEST_TX_DOMINANT (0x2u << 5) /**< \brief (MCAN_TEST) Dominant ('0') level at pin CANTX. */ +#define MCAN_TEST_TX_RECESSIVE (0x3u << 5) /**< \brief (MCAN_TEST) Recessive ('1') at pin CANTX. */ +#define MCAN_TEST_RX (0x1u << 7) /**< \brief (MCAN_TEST) Receive Pin (read-only) */ +#define MCAN_TEST_TDCV_Pos 8 +#define MCAN_TEST_TDCV_Msk (0x3fu << MCAN_TEST_TDCV_Pos) /**< \brief (MCAN_TEST) Transceiver Delay Compensation Value (read-only) */ +#define MCAN_TEST_TDCV(value) ((MCAN_TEST_TDCV_Msk & ((value) << MCAN_TEST_TDCV_Pos))) +/* -------- MCAN_RWD : (MCAN Offset: 0x14) RAM Watchdog Register -------- */ +#define MCAN_RWD_WDC_Pos 0 +#define MCAN_RWD_WDC_Msk (0xffu << MCAN_RWD_WDC_Pos) /**< \brief (MCAN_RWD) Watchdog Configuration (read/write) */ +#define MCAN_RWD_WDC(value) ((MCAN_RWD_WDC_Msk & ((value) << MCAN_RWD_WDC_Pos))) +#define MCAN_RWD_WDV_Pos 8 +#define MCAN_RWD_WDV_Msk (0xffu << MCAN_RWD_WDV_Pos) /**< \brief (MCAN_RWD) Watchdog Value (read-only) */ +#define MCAN_RWD_WDV(value) ((MCAN_RWD_WDV_Msk & ((value) << MCAN_RWD_WDV_Pos))) +/* -------- MCAN_CCCR : (MCAN Offset: 0x18) CC Control Register -------- */ +#define MCAN_CCCR_INIT (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization (read/write) */ +#define MCAN_CCCR_INIT_DISABLED (0x0u << 0) /**< \brief (MCAN_CCCR) Normal operation. */ +#define MCAN_CCCR_INIT_ENABLED (0x1u << 0) /**< \brief (MCAN_CCCR) Initialization is started. */ +#define MCAN_CCCR_CCE (0x1u << 1) /**< \brief (MCAN_CCCR) Configuration Change Enable (read/write, write protection) */ +#define MCAN_CCCR_CCE_PROTECTED (0x0u << 1) /**< \brief (MCAN_CCCR) The processor has no write access to the protected configuration registers. */ +#define MCAN_CCCR_CCE_CONFIGURABLE (0x1u << 1) /**< \brief (MCAN_CCCR) The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). */ +#define MCAN_CCCR_ASM (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted Operation Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_ASM_NORMAL (0x0u << 2) /**< \brief (MCAN_CCCR) Normal CAN operation. */ +#define MCAN_CCCR_ASM_RESTRICTED (0x1u << 2) /**< \brief (MCAN_CCCR) Restricted operation mode active. */ +#define MCAN_CCCR_CSA (0x1u << 3) /**< \brief (MCAN_CCCR) Clock Stop Acknowledge (read-only) */ +#define MCAN_CCCR_CSR (0x1u << 4) /**< \brief (MCAN_CCCR) Clock Stop Request (read/write) */ +#define MCAN_CCCR_CSR_NO_CLOCK_STOP (0x0u << 4) /**< \brief (MCAN_CCCR) No clock stop is requested. */ +#define MCAN_CCCR_CSR_CLOCK_STOP (0x1u << 4) /**< \brief (MCAN_CCCR) Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. */ +#define MCAN_CCCR_MON (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring Mode (read/write, write protection against '1') */ +#define MCAN_CCCR_MON_DISABLED (0x0u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is disabled. */ +#define MCAN_CCCR_MON_ENABLED (0x1u << 5) /**< \brief (MCAN_CCCR) Bus Monitoring mode is enabled. */ +#define MCAN_CCCR_DAR (0x1u << 6) /**< \brief (MCAN_CCCR) Disable Automatic Retransmission (read/write, write protection) */ +#define MCAN_CCCR_DAR_AUTO_RETX (0x0u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission of messages not transmitted successfully enabled. */ +#define MCAN_CCCR_DAR_NO_AUTO_RETX (0x1u << 6) /**< \brief (MCAN_CCCR) Automatic retransmission disabled. */ +#define MCAN_CCCR_TEST (0x1u << 7) /**< \brief (MCAN_CCCR) Test Mode Enable (read/write, write protection against '1') */ +#define MCAN_CCCR_TEST_DISABLED (0x0u << 7) /**< \brief (MCAN_CCCR) Normal operation, MCAN_TEST register holds reset values. */ +#define MCAN_CCCR_TEST_ENABLED (0x1u << 7) /**< \brief (MCAN_CCCR) Test mode, write access to MCAN_TEST register enabled. */ +#define MCAN_CCCR_CME_Pos 8 +#define MCAN_CCCR_CME_Msk (0x3u << MCAN_CCCR_CME_Pos) /**< \brief (MCAN_CCCR) CAN Mode Enable (read/write, write protection) */ +#define MCAN_CCCR_CME(value) ((MCAN_CCCR_CME_Msk & ((value) << MCAN_CCCR_CME_Pos))) +#define MCAN_CCCR_CME_ISO11898_1 (0x0u << 8) /**< \brief (MCAN_CCCR) CAN operation according to ISO11898-1 enabled */ +#define MCAN_CCCR_CME_FD (0x1u << 8) /**< \brief (MCAN_CCCR) CAN FD operation enabled */ +#define MCAN_CCCR_CMR_Pos 10 +#define MCAN_CCCR_CMR_Msk (0x3u << MCAN_CCCR_CMR_Pos) /**< \brief (MCAN_CCCR) CAN Mode Request (read/write) */ +#define MCAN_CCCR_CMR(value) ((MCAN_CCCR_CMR_Msk & ((value) << MCAN_CCCR_CMR_Pos))) +#define MCAN_CCCR_CMR_NO_CHANGE (0x0u << 10) /**< \brief (MCAN_CCCR) No mode change */ +#define MCAN_CCCR_CMR_FD (0x1u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation */ +#define MCAN_CCCR_CMR_FD_BITRATE_SWITCH (0x2u << 10) /**< \brief (MCAN_CCCR) Request CAN FD operation with bit rate switching */ +#define MCAN_CCCR_CMR_ISO11898_1 (0x3u << 10) /**< \brief (MCAN_CCCR) Request CAN operation according ISO11898-1 */ +#define MCAN_CCCR_FDO (0x1u << 12) /**< \brief (MCAN_CCCR) CAN FD Operation (read-only) */ +#define MCAN_CCCR_FDBS (0x1u << 13) /**< \brief (MCAN_CCCR) CAN FD Bit Rate Switching (read-only) */ +#define MCAN_CCCR_TXP (0x1u << 14) /**< \brief (MCAN_CCCR) Transmit Pause (read/write, write protection) */ +/* -------- MCAN_BTP : (MCAN Offset: 0x1C) Bit Timing and Prescaler Register -------- */ +#define MCAN_BTP_SJW_Pos 0 +#define MCAN_BTP_SJW_Msk (0xfu << MCAN_BTP_SJW_Pos) /**< \brief (MCAN_BTP) (Re) Synchronization Jump Width */ +#define MCAN_BTP_SJW(value) ((MCAN_BTP_SJW_Msk & ((value) << MCAN_BTP_SJW_Pos))) +#define MCAN_BTP_TSEG2_Pos 4 +#define MCAN_BTP_TSEG2_Msk (0xfu << MCAN_BTP_TSEG2_Pos) /**< \brief (MCAN_BTP) Time Segment After Sample Point */ +#define MCAN_BTP_TSEG2(value) ((MCAN_BTP_TSEG2_Msk & ((value) << MCAN_BTP_TSEG2_Pos))) +#define MCAN_BTP_TSEG1_Pos 8 +#define MCAN_BTP_TSEG1_Msk (0x3fu << MCAN_BTP_TSEG1_Pos) /**< \brief (MCAN_BTP) Time Segment Before Sample Point */ +#define MCAN_BTP_TSEG1(value) ((MCAN_BTP_TSEG1_Msk & ((value) << MCAN_BTP_TSEG1_Pos))) +#define MCAN_BTP_BRP_Pos 16 +#define MCAN_BTP_BRP_Msk (0x3ffu << MCAN_BTP_BRP_Pos) /**< \brief (MCAN_BTP) Baud Rate Prescaler */ +#define MCAN_BTP_BRP(value) ((MCAN_BTP_BRP_Msk & ((value) << MCAN_BTP_BRP_Pos))) +/* -------- MCAN_TSCC : (MCAN Offset: 0x20) Timestamp Counter Configuration Register -------- */ +#define MCAN_TSCC_TSS_Pos 0 +#define MCAN_TSCC_TSS_Msk (0x3u << MCAN_TSCC_TSS_Pos) /**< \brief (MCAN_TSCC) Timestamp Select */ +#define MCAN_TSCC_TSS(value) ((MCAN_TSCC_TSS_Msk & ((value) << MCAN_TSCC_TSS_Pos))) +#define MCAN_TSCC_TSS_ALWAYS_0 (0x0u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value always 0x0000 */ +#define MCAN_TSCC_TSS_TCP_INC (0x1u << 0) /**< \brief (MCAN_TSCC) Timestamp counter value incremented according to TCP */ +#define MCAN_TSCC_TSS_EXT_TIMESTAMP (0x2u << 0) /**< \brief (MCAN_TSCC) External timestamp counter value used */ +#define MCAN_TSCC_TCP_Pos 16 +#define MCAN_TSCC_TCP_Msk (0xfu << MCAN_TSCC_TCP_Pos) /**< \brief (MCAN_TSCC) Timestamp Counter Prescaler */ +#define MCAN_TSCC_TCP(value) ((MCAN_TSCC_TCP_Msk & ((value) << MCAN_TSCC_TCP_Pos))) +/* -------- MCAN_TSCV : (MCAN Offset: 0x24) Timestamp Counter Value Register -------- */ +#define MCAN_TSCV_TSC_Pos 0 +#define MCAN_TSCV_TSC_Msk (0xffffu << MCAN_TSCV_TSC_Pos) /**< \brief (MCAN_TSCV) Timestamp Counter (cleared on write) */ +#define MCAN_TSCV_TSC(value) ((MCAN_TSCV_TSC_Msk & ((value) << MCAN_TSCV_TSC_Pos))) +/* -------- MCAN_TOCC : (MCAN Offset: 0x28) Timeout Counter Configuration Register -------- */ +#define MCAN_TOCC_ETOC (0x1u << 0) /**< \brief (MCAN_TOCC) Enable Timeout Counter */ +#define MCAN_TOCC_ETOC_NO_TIMEOUT (0x0u << 0) /**< \brief (MCAN_TOCC) Timeout Counter disabled. */ +#define MCAN_TOCC_ETOC_TOS_CONTROLLED (0x1u << 0) /**< \brief (MCAN_TOCC) Timeout Counter enabled. */ +#define MCAN_TOCC_TOS_Pos 1 +#define MCAN_TOCC_TOS_Msk (0x3u << MCAN_TOCC_TOS_Pos) /**< \brief (MCAN_TOCC) Timeout Select */ +#define MCAN_TOCC_TOS(value) ((MCAN_TOCC_TOS_Msk & ((value) << MCAN_TOCC_TOS_Pos))) +#define MCAN_TOCC_TOS_CONTINUOUS (0x0u << 1) /**< \brief (MCAN_TOCC) Continuous operation */ +#define MCAN_TOCC_TOS_TX_EV_TIMEOUT (0x1u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Tx Event FIFO */ +#define MCAN_TOCC_TOS_RX0_EV_TIMEOUT (0x2u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 0 */ +#define MCAN_TOCC_TOS_RX1_EV_TIMEOUT (0x3u << 1) /**< \brief (MCAN_TOCC) Timeout controlled by Receive FIFO 1 */ +#define MCAN_TOCC_TOP_Pos 16 +#define MCAN_TOCC_TOP_Msk (0xffffu << MCAN_TOCC_TOP_Pos) /**< \brief (MCAN_TOCC) Timeout Period */ +#define MCAN_TOCC_TOP(value) ((MCAN_TOCC_TOP_Msk & ((value) << MCAN_TOCC_TOP_Pos))) +/* -------- MCAN_TOCV : (MCAN Offset: 0x2C) Timeout Counter Value Register -------- */ +#define MCAN_TOCV_TOC_Pos 0 +#define MCAN_TOCV_TOC_Msk (0xffffu << MCAN_TOCV_TOC_Pos) /**< \brief (MCAN_TOCV) Timeout Counter (cleared on write) */ +#define MCAN_TOCV_TOC(value) ((MCAN_TOCV_TOC_Msk & ((value) << MCAN_TOCV_TOC_Pos))) +/* -------- MCAN_ECR : (MCAN Offset: 0x40) Error Counter Register -------- */ +#define MCAN_ECR_TEC_Pos 0 +#define MCAN_ECR_TEC_Msk (0xffu << MCAN_ECR_TEC_Pos) /**< \brief (MCAN_ECR) Transmit Error Counter */ +#define MCAN_ECR_REC_Pos 8 +#define MCAN_ECR_REC_Msk (0x7fu << MCAN_ECR_REC_Pos) /**< \brief (MCAN_ECR) Receive Error Counter */ +#define MCAN_ECR_RP (0x1u << 15) /**< \brief (MCAN_ECR) Receive Error Passive */ +#define MCAN_ECR_CEL_Pos 16 +#define MCAN_ECR_CEL_Msk (0xffu << MCAN_ECR_CEL_Pos) /**< \brief (MCAN_ECR) CAN Error Logging (cleared on read) */ +/* -------- MCAN_PSR : (MCAN Offset: 0x44) Protocol Status Register -------- */ +#define MCAN_PSR_LEC_Pos 0 +#define MCAN_PSR_LEC_Msk (0x7u << MCAN_PSR_LEC_Pos) /**< \brief (MCAN_PSR) Last Error Code (set to 111 on read) */ +#define MCAN_PSR_LEC_NO_ERROR (0x0u << 0) /**< \brief (MCAN_PSR) No error occurred since LEC has been reset by successful reception or transmission. */ +#define MCAN_PSR_LEC_STUFF_ERROR (0x1u << 0) /**< \brief (MCAN_PSR) More than 5 equal bits in a sequence have occurred in a part of a received meSsage where this is not allowed. */ +#define MCAN_PSR_LEC_FORM_ERROR (0x2u << 0) /**< \brief (MCAN_PSR) A fixed format part of a received frame has the wrong format. */ +#define MCAN_PSR_LEC_ACK_ERROR (0x3u << 0) /**< \brief (MCAN_PSR) The message transmitted by the MCAN was not acknowledged by another node. */ +#define MCAN_PSR_LEC_BIT1_ERROR (0x4u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. */ +#define MCAN_PSR_LEC_BIT0_ERROR (0x5u << 0) /**< \brief (MCAN_PSR) During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). */ +#define MCAN_PSR_LEC_CRC_ERROR (0x6u << 0) /**< \brief (MCAN_PSR) The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. */ +#define MCAN_PSR_LEC_NO_CHANGE (0x7u << 0) /**< \brief (MCAN_PSR) Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. */ +#define MCAN_PSR_ACT_Pos 3 +#define MCAN_PSR_ACT_Msk (0x3u << MCAN_PSR_ACT_Pos) /**< \brief (MCAN_PSR) Activity */ +#define MCAN_PSR_ACT_SYNCHRONIZING (0x0u << 3) /**< \brief (MCAN_PSR) Node is synchronizing on CAN communication */ +#define MCAN_PSR_ACT_IDLE (0x1u << 3) /**< \brief (MCAN_PSR) Node is neither receiver nor transmitter */ +#define MCAN_PSR_ACT_RECEIVER (0x2u << 3) /**< \brief (MCAN_PSR) Node is operating as receiver */ +#define MCAN_PSR_ACT_TRANSMITTER (0x3u << 3) /**< \brief (MCAN_PSR) Node is operating as transmitter */ +#define MCAN_PSR_EP (0x1u << 5) /**< \brief (MCAN_PSR) Error Passive */ +#define MCAN_PSR_EW (0x1u << 6) /**< \brief (MCAN_PSR) Warning Status */ +#define MCAN_PSR_BO (0x1u << 7) /**< \brief (MCAN_PSR) Bus_Off Status */ +#define MCAN_PSR_FLEC_Pos 8 +#define MCAN_PSR_FLEC_Msk (0x7u << MCAN_PSR_FLEC_Pos) /**< \brief (MCAN_PSR) Fast Last Error Code (set to 111 on read) */ +#define MCAN_PSR_RESI (0x1u << 11) /**< \brief (MCAN_PSR) ESI Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_RBRS (0x1u << 12) /**< \brief (MCAN_PSR) BRS Flag of Last Received CAN FD Message (cleared on read) */ +#define MCAN_PSR_REDL (0x1u << 13) /**< \brief (MCAN_PSR) Received a CAN FD Message (cleared on read) */ +/* -------- MCAN_IR : (MCAN Offset: 0x50) Interrupt Register -------- */ +#define MCAN_IR_RF0N (0x1u << 0) /**< \brief (MCAN_IR) Receive FIFO 0 New Message */ +#define MCAN_IR_RF0W (0x1u << 1) /**< \brief (MCAN_IR) Receive FIFO 0 Watermark Reached */ +#define MCAN_IR_RF0F (0x1u << 2) /**< \brief (MCAN_IR) Receive FIFO 0 Full */ +#define MCAN_IR_RF0L (0x1u << 3) /**< \brief (MCAN_IR) Receive FIFO 0 Message Lost */ +#define MCAN_IR_RF1N (0x1u << 4) /**< \brief (MCAN_IR) Receive FIFO 1 New Message */ +#define MCAN_IR_RF1W (0x1u << 5) /**< \brief (MCAN_IR) Receive FIFO 1 Watermark Reached */ +#define MCAN_IR_RF1F (0x1u << 6) /**< \brief (MCAN_IR) Receive FIFO 1 Full */ +#define MCAN_IR_RF1L (0x1u << 7) /**< \brief (MCAN_IR) Receive FIFO 1 Message Lost */ +#define MCAN_IR_HPM (0x1u << 8) /**< \brief (MCAN_IR) High Priority Message */ +#define MCAN_IR_TC (0x1u << 9) /**< \brief (MCAN_IR) Transmission Completed */ +#define MCAN_IR_TCF (0x1u << 10) /**< \brief (MCAN_IR) Transmission Cancellation Finished */ +#define MCAN_IR_TFE (0x1u << 11) /**< \brief (MCAN_IR) Tx FIFO Empty */ +#define MCAN_IR_TEFN (0x1u << 12) /**< \brief (MCAN_IR) Tx Event FIFO New Entry */ +#define MCAN_IR_TEFW (0x1u << 13) /**< \brief (MCAN_IR) Tx Event FIFO Watermark Reached */ +#define MCAN_IR_TEFF (0x1u << 14) /**< \brief (MCAN_IR) Tx Event FIFO Full */ +#define MCAN_IR_TEFL (0x1u << 15) /**< \brief (MCAN_IR) Tx Event FIFO Element Lost */ +#define MCAN_IR_TSW (0x1u << 16) /**< \brief (MCAN_IR) Timestamp Wraparound */ +#define MCAN_IR_MRAF (0x1u << 17) /**< \brief (MCAN_IR) Message RAM Access Failure */ +#define MCAN_IR_TOO (0x1u << 18) /**< \brief (MCAN_IR) Timeout Occurred */ +#define MCAN_IR_DRX (0x1u << 19) /**< \brief (MCAN_IR) Message stored to Dedicated Receive Buffer */ +#define MCAN_IR_ELO (0x1u << 22) /**< \brief (MCAN_IR) Error Logging Overflow */ +#define MCAN_IR_EP (0x1u << 23) /**< \brief (MCAN_IR) Error Passive */ +#define MCAN_IR_EW (0x1u << 24) /**< \brief (MCAN_IR) Warning Status */ +#define MCAN_IR_BO (0x1u << 25) /**< \brief (MCAN_IR) Bus_Off Status */ +#define MCAN_IR_WDI (0x1u << 26) /**< \brief (MCAN_IR) Watchdog Interrupt */ +#define MCAN_IR_CRCE (0x1u << 27) /**< \brief (MCAN_IR) CRC Error */ +#define MCAN_IR_BE (0x1u << 28) /**< \brief (MCAN_IR) Bit Error */ +#define MCAN_IR_ACKE (0x1u << 29) /**< \brief (MCAN_IR) Acknowledge Error */ +#define MCAN_IR_FOE (0x1u << 30) /**< \brief (MCAN_IR) Format Error */ +#define MCAN_IR_STE (0x1u << 31) /**< \brief (MCAN_IR) Stuff Error */ +/* -------- MCAN_IE : (MCAN Offset: 0x54) Interrupt Enable Register -------- */ +#define MCAN_IE_RF0NE (0x1u << 0) /**< \brief (MCAN_IE) Receive FIFO 0 New Message Interrupt Enable */ +#define MCAN_IE_RF0WE (0x1u << 1) /**< \brief (MCAN_IE) Receive FIFO 0 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF0FE (0x1u << 2) /**< \brief (MCAN_IE) Receive FIFO 0 Full Interrupt Enable */ +#define MCAN_IE_RF0LE (0x1u << 3) /**< \brief (MCAN_IE) Receive FIFO 0 Message Lost Interrupt Enable */ +#define MCAN_IE_RF1NE (0x1u << 4) /**< \brief (MCAN_IE) Receive FIFO 1 New Message Interrupt Enable */ +#define MCAN_IE_RF1WE (0x1u << 5) /**< \brief (MCAN_IE) Receive FIFO 1 Watermark Reached Interrupt Enable */ +#define MCAN_IE_RF1FE (0x1u << 6) /**< \brief (MCAN_IE) Receive FIFO 1 Full Interrupt Enable */ +#define MCAN_IE_RF1LE (0x1u << 7) /**< \brief (MCAN_IE) Receive FIFO 1 Message Lost Interrupt Enable */ +#define MCAN_IE_HPME (0x1u << 8) /**< \brief (MCAN_IE) High Priority Message Interrupt Enable */ +#define MCAN_IE_TCE (0x1u << 9) /**< \brief (MCAN_IE) Transmission Completed Interrupt Enable */ +#define MCAN_IE_TCFE (0x1u << 10) /**< \brief (MCAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define MCAN_IE_TFEE (0x1u << 11) /**< \brief (MCAN_IE) Tx FIFO Empty Interrupt Enable */ +#define MCAN_IE_TEFNE (0x1u << 12) /**< \brief (MCAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define MCAN_IE_TEFWE (0x1u << 13) /**< \brief (MCAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define MCAN_IE_TEFFE (0x1u << 14) /**< \brief (MCAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define MCAN_IE_TEFLE (0x1u << 15) /**< \brief (MCAN_IE) Tx Event FIFO Event Lost Interrupt Enable */ +#define MCAN_IE_TSWE (0x1u << 16) /**< \brief (MCAN_IE) Timestamp Wraparound Interrupt Enable */ +#define MCAN_IE_MRAFE (0x1u << 17) /**< \brief (MCAN_IE) Message RAM Access Failure Interrupt Enable */ +#define MCAN_IE_TOOE (0x1u << 18) /**< \brief (MCAN_IE) Timeout Occurred Interrupt Enable */ +#define MCAN_IE_DRXE (0x1u << 19) /**< \brief (MCAN_IE) Message stored to Dedicated Receive Buffer Interrupt Enable */ +#define MCAN_IE_ELOE (0x1u << 22) /**< \brief (MCAN_IE) Error Logging Overflow Interrupt Enable */ +#define MCAN_IE_EPE (0x1u << 23) /**< \brief (MCAN_IE) Error Passive Interrupt Enable */ +#define MCAN_IE_EWE (0x1u << 24) /**< \brief (MCAN_IE) Warning Status Interrupt Enable */ +#define MCAN_IE_BOE (0x1u << 25) /**< \brief (MCAN_IE) Bus_Off Status Interrupt Enable */ +#define MCAN_IE_WDIE (0x1u << 26) /**< \brief (MCAN_IE) Watchdog Interrupt Enable */ +#define MCAN_IE_CRCEE (0x1u << 27) /**< \brief (MCAN_IE) CRC Error Interrupt Enable */ +#define MCAN_IE_BEE (0x1u << 28) /**< \brief (MCAN_IE) Bit Error Interrupt Enable */ +#define MCAN_IE_ACKEE (0x1u << 29) /**< \brief (MCAN_IE) Acknowledge Error Interrupt Enable */ +#define MCAN_IE_FOEE (0x1u << 30) /**< \brief (MCAN_IE) Format Error Interrupt Enable */ +#define MCAN_IE_STEE (0x1u << 31) /**< \brief (MCAN_IE) Stuff Error Interrupt Enable */ +/* -------- MCAN_ILS : (MCAN Offset: 0x58) Interrupt Line Select Register -------- */ +#define MCAN_ILS_RF0NL (0x1u << 0) /**< \brief (MCAN_ILS) Receive FIFO 0 New Message Interrupt Line */ +#define MCAN_ILS_RF0WL (0x1u << 1) /**< \brief (MCAN_ILS) Receive FIFO 0 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF0FL (0x1u << 2) /**< \brief (MCAN_ILS) Receive FIFO 0 Full Interrupt Line */ +#define MCAN_ILS_RF0LL (0x1u << 3) /**< \brief (MCAN_ILS) Receive FIFO 0 Message Lost Interrupt Line */ +#define MCAN_ILS_RF1NL (0x1u << 4) /**< \brief (MCAN_ILS) Receive FIFO 1 New Message Interrupt Line */ +#define MCAN_ILS_RF1WL (0x1u << 5) /**< \brief (MCAN_ILS) Receive FIFO 1 Watermark Reached Interrupt Line */ +#define MCAN_ILS_RF1FL (0x1u << 6) /**< \brief (MCAN_ILS) Receive FIFO 1 Full Interrupt Line */ +#define MCAN_ILS_RF1LL (0x1u << 7) /**< \brief (MCAN_ILS) Receive FIFO 1 Message Lost Interrupt Line */ +#define MCAN_ILS_HPML (0x1u << 8) /**< \brief (MCAN_ILS) High Priority Message Interrupt Line */ +#define MCAN_ILS_TCL (0x1u << 9) /**< \brief (MCAN_ILS) Transmission Completed Interrupt Line */ +#define MCAN_ILS_TCFL (0x1u << 10) /**< \brief (MCAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define MCAN_ILS_TFEL (0x1u << 11) /**< \brief (MCAN_ILS) Tx FIFO Empty Interrupt Line */ +#define MCAN_ILS_TEFNL (0x1u << 12) /**< \brief (MCAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define MCAN_ILS_TEFWL (0x1u << 13) /**< \brief (MCAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define MCAN_ILS_TEFFL (0x1u << 14) /**< \brief (MCAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define MCAN_ILS_TEFLL (0x1u << 15) /**< \brief (MCAN_ILS) Tx Event FIFO Event Lost Interrupt Line */ +#define MCAN_ILS_TSWL (0x1u << 16) /**< \brief (MCAN_ILS) Timestamp Wraparound Interrupt Line */ +#define MCAN_ILS_MRAFL (0x1u << 17) /**< \brief (MCAN_ILS) Message RAM Access Failure Interrupt Line */ +#define MCAN_ILS_TOOL (0x1u << 18) /**< \brief (MCAN_ILS) Timeout Occurred Interrupt Line */ +#define MCAN_ILS_DRXL (0x1u << 19) /**< \brief (MCAN_ILS) Message stored to Dedicated Receive Buffer Interrupt Line */ +#define MCAN_ILS_ELOL (0x1u << 22) /**< \brief (MCAN_ILS) Error Logging Overflow Interrupt Line */ +#define MCAN_ILS_EPL (0x1u << 23) /**< \brief (MCAN_ILS) Error Passive Interrupt Line */ +#define MCAN_ILS_EWL (0x1u << 24) /**< \brief (MCAN_ILS) Warning Status Interrupt Line */ +#define MCAN_ILS_BOL (0x1u << 25) /**< \brief (MCAN_ILS) Bus_Off Status Interrupt Line */ +#define MCAN_ILS_WDIL (0x1u << 26) /**< \brief (MCAN_ILS) Watchdog Interrupt Line */ +#define MCAN_ILS_CRCEL (0x1u << 27) /**< \brief (MCAN_ILS) CRC Error Interrupt Line */ +#define MCAN_ILS_BEL (0x1u << 28) /**< \brief (MCAN_ILS) Bit Error Interrupt Line */ +#define MCAN_ILS_ACKEL (0x1u << 29) /**< \brief (MCAN_ILS) Acknowledge Error Interrupt Line */ +#define MCAN_ILS_FOEL (0x1u << 30) /**< \brief (MCAN_ILS) Format Error Interrupt Line */ +#define MCAN_ILS_STEL (0x1u << 31) /**< \brief (MCAN_ILS) Stuff Error Interrupt Line */ +/* -------- MCAN_ILE : (MCAN Offset: 0x5C) Interrupt Line Enable Register -------- */ +#define MCAN_ILE_EINT0 (0x1u << 0) /**< \brief (MCAN_ILE) Enable Interrupt Line 0 */ +#define MCAN_ILE_EINT1 (0x1u << 1) /**< \brief (MCAN_ILE) Enable Interrupt Line 1 */ +/* -------- MCAN_GFC : (MCAN Offset: 0x80) Global Filter Configuration Register -------- */ +#define MCAN_GFC_RRFE (0x1u << 0) /**< \brief (MCAN_GFC) Reject Remote Frames Extended */ +#define MCAN_GFC_RRFE_FILTER (0x0u << 0) /**< \brief (MCAN_GFC) Filter remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFE_REJECT (0x1u << 0) /**< \brief (MCAN_GFC) Reject all remote frames with 29-bit extended IDs. */ +#define MCAN_GFC_RRFS (0x1u << 1) /**< \brief (MCAN_GFC) Reject Remote Frames Standard */ +#define MCAN_GFC_RRFS_FILTER (0x0u << 1) /**< \brief (MCAN_GFC) Filter remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_RRFS_REJECT (0x1u << 1) /**< \brief (MCAN_GFC) Reject all remote frames with 11-bit standard IDs. */ +#define MCAN_GFC_ANFE_Pos 2 +#define MCAN_GFC_ANFE_Msk (0x3u << MCAN_GFC_ANFE_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Extended */ +#define MCAN_GFC_ANFE(value) ((MCAN_GFC_ANFE_Msk & ((value) << MCAN_GFC_ANFE_Pos))) +#define MCAN_GFC_ANFE_RX_FIFO_0 (0x0u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFE_RX_FIFO_1 (0x1u << 2) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +#define MCAN_GFC_ANFS_Pos 4 +#define MCAN_GFC_ANFS_Msk (0x3u << MCAN_GFC_ANFS_Pos) /**< \brief (MCAN_GFC) Accept Non-matching Frames Standard */ +#define MCAN_GFC_ANFS(value) ((MCAN_GFC_ANFS_Msk & ((value) << MCAN_GFC_ANFS_Pos))) +#define MCAN_GFC_ANFS_RX_FIFO_0 (0x0u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 0 */ +#define MCAN_GFC_ANFS_RX_FIFO_1 (0x1u << 4) /**< \brief (MCAN_GFC) Message stored in Receive FIFO 1 */ +/* -------- MCAN_SIDFC : (MCAN Offset: 0x84) Standard ID Filter Configuration Register -------- */ +#define MCAN_SIDFC_FLSSA_Pos 2 +#define MCAN_SIDFC_FLSSA_Msk (0x3fffu << MCAN_SIDFC_FLSSA_Pos) /**< \brief (MCAN_SIDFC) Filter List Standard Start Address */ +#define MCAN_SIDFC_FLSSA(value) ((MCAN_SIDFC_FLSSA_Msk & ((value) << MCAN_SIDFC_FLSSA_Pos))) +#define MCAN_SIDFC_LSS_Pos 16 +#define MCAN_SIDFC_LSS_Msk (0xffu << MCAN_SIDFC_LSS_Pos) /**< \brief (MCAN_SIDFC) List Size Standard */ +#define MCAN_SIDFC_LSS(value) ((MCAN_SIDFC_LSS_Msk & ((value) << MCAN_SIDFC_LSS_Pos))) +/* -------- MCAN_XIDFC : (MCAN Offset: 0x88) Extended ID Filter Configuration Register -------- */ +#define MCAN_XIDFC_FLESA_Pos 2 +#define MCAN_XIDFC_FLESA_Msk (0x3fffu << MCAN_XIDFC_FLESA_Pos) /**< \brief (MCAN_XIDFC) Filter List Extended Start Address */ +#define MCAN_XIDFC_FLESA(value) ((MCAN_XIDFC_FLESA_Msk & ((value) << MCAN_XIDFC_FLESA_Pos))) +#define MCAN_XIDFC_LSE_Pos 16 +#define MCAN_XIDFC_LSE_Msk (0x7fu << MCAN_XIDFC_LSE_Pos) /**< \brief (MCAN_XIDFC) List Size Extended */ +#define MCAN_XIDFC_LSE(value) ((MCAN_XIDFC_LSE_Msk & ((value) << MCAN_XIDFC_LSE_Pos))) +/* -------- MCAN_XIDAM : (MCAN Offset: 0x90) Extended ID AND Mask Register -------- */ +#define MCAN_XIDAM_EIDM_Pos 0 +#define MCAN_XIDAM_EIDM_Msk (0x1fffffffu << MCAN_XIDAM_EIDM_Pos) /**< \brief (MCAN_XIDAM) Extended ID Mask */ +#define MCAN_XIDAM_EIDM(value) ((MCAN_XIDAM_EIDM_Msk & ((value) << MCAN_XIDAM_EIDM_Pos))) +/* -------- MCAN_HPMS : (MCAN Offset: 0x94) High Priority Message Status Register -------- */ +#define MCAN_HPMS_BIDX_Pos 0 +#define MCAN_HPMS_BIDX_Msk (0x3fu << MCAN_HPMS_BIDX_Pos) /**< \brief (MCAN_HPMS) Buffer Index */ +#define MCAN_HPMS_MSI_Pos 6 +#define MCAN_HPMS_MSI_Msk (0x3u << MCAN_HPMS_MSI_Pos) /**< \brief (MCAN_HPMS) Message Storage Indicator */ +#define MCAN_HPMS_MSI_NO_FIFO_SEL (0x0u << 6) /**< \brief (MCAN_HPMS) No FIFO selected. */ +#define MCAN_HPMS_MSI_LOST (0x1u << 6) /**< \brief (MCAN_HPMS) FIFO message. */ +#define MCAN_HPMS_MSI_FIFO_0 (0x2u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 0. */ +#define MCAN_HPMS_MSI_FIFO_1 (0x3u << 6) /**< \brief (MCAN_HPMS) Message stored in FIFO 1. */ +#define MCAN_HPMS_FIDX_Pos 8 +#define MCAN_HPMS_FIDX_Msk (0x7fu << MCAN_HPMS_FIDX_Pos) /**< \brief (MCAN_HPMS) Filter Index */ +#define MCAN_HPMS_FLST (0x1u << 15) /**< \brief (MCAN_HPMS) Filter List */ +/* -------- MCAN_NDAT1 : (MCAN Offset: 0x98) New Data 1 Register -------- */ +#define MCAN_NDAT1_ND0 (0x1u << 0) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND1 (0x1u << 1) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND2 (0x1u << 2) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND3 (0x1u << 3) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND4 (0x1u << 4) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND5 (0x1u << 5) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND6 (0x1u << 6) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND7 (0x1u << 7) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND8 (0x1u << 8) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND9 (0x1u << 9) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND10 (0x1u << 10) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND11 (0x1u << 11) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND12 (0x1u << 12) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND13 (0x1u << 13) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND14 (0x1u << 14) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND15 (0x1u << 15) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND16 (0x1u << 16) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND17 (0x1u << 17) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND18 (0x1u << 18) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND19 (0x1u << 19) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND20 (0x1u << 20) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND21 (0x1u << 21) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND22 (0x1u << 22) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND23 (0x1u << 23) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND24 (0x1u << 24) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND25 (0x1u << 25) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND26 (0x1u << 26) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND27 (0x1u << 27) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND28 (0x1u << 28) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND29 (0x1u << 29) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND30 (0x1u << 30) /**< \brief (MCAN_NDAT1) New Data */ +#define MCAN_NDAT1_ND31 (0x1u << 31) /**< \brief (MCAN_NDAT1) New Data */ +/* -------- MCAN_NDAT2 : (MCAN Offset: 0x9C) New Data 2 Register -------- */ +#define MCAN_NDAT2_ND32 (0x1u << 0) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND33 (0x1u << 1) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND34 (0x1u << 2) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND35 (0x1u << 3) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND36 (0x1u << 4) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND37 (0x1u << 5) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND38 (0x1u << 6) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND39 (0x1u << 7) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND40 (0x1u << 8) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND41 (0x1u << 9) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND42 (0x1u << 10) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND43 (0x1u << 11) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND44 (0x1u << 12) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND45 (0x1u << 13) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND46 (0x1u << 14) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND47 (0x1u << 15) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND48 (0x1u << 16) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND49 (0x1u << 17) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND50 (0x1u << 18) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND51 (0x1u << 19) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND52 (0x1u << 20) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND53 (0x1u << 21) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND54 (0x1u << 22) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND55 (0x1u << 23) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND56 (0x1u << 24) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND57 (0x1u << 25) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND58 (0x1u << 26) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND59 (0x1u << 27) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND60 (0x1u << 28) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND61 (0x1u << 29) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND62 (0x1u << 30) /**< \brief (MCAN_NDAT2) New Data */ +#define MCAN_NDAT2_ND63 (0x1u << 31) /**< \brief (MCAN_NDAT2) New Data */ +/* -------- MCAN_RXF0C : (MCAN Offset: 0xA0) Receive FIFO 0 Configuration Register -------- */ +#define MCAN_RXF0C_F0SA_Pos 2 +#define MCAN_RXF0C_F0SA_Msk (0x3fffu << MCAN_RXF0C_F0SA_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0SA(value) ((MCAN_RXF0C_F0SA_Msk & ((value) << MCAN_RXF0C_F0SA_Pos))) +#define MCAN_RXF0C_F0S_Pos 16 +#define MCAN_RXF0C_F0S_Msk (0x7fu << MCAN_RXF0C_F0S_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Start Address */ +#define MCAN_RXF0C_F0S(value) ((MCAN_RXF0C_F0S_Msk & ((value) << MCAN_RXF0C_F0S_Pos))) +#define MCAN_RXF0C_F0WM_Pos 24 +#define MCAN_RXF0C_F0WM_Msk (0x7fu << MCAN_RXF0C_F0WM_Pos) /**< \brief (MCAN_RXF0C) Receive FIFO 0 Watermark */ +#define MCAN_RXF0C_F0WM(value) ((MCAN_RXF0C_F0WM_Msk & ((value) << MCAN_RXF0C_F0WM_Pos))) +#define MCAN_RXF0C_F0OM (0x1u << 31) /**< \brief (MCAN_RXF0C) FIFO 0 Operation Mode */ +/* -------- MCAN_RXF0S : (MCAN Offset: 0xA4) Receive FIFO 0 Status Register -------- */ +#define MCAN_RXF0S_F0FL_Pos 0 +#define MCAN_RXF0S_F0FL_Msk (0x7fu << MCAN_RXF0S_F0FL_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_F0GI_Pos 8 +#define MCAN_RXF0S_F0GI_Msk (0x3fu << MCAN_RXF0S_F0GI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Get Index */ +#define MCAN_RXF0S_F0PI_Pos 16 +#define MCAN_RXF0S_F0PI_Msk (0x3fu << MCAN_RXF0S_F0PI_Pos) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Put Index */ +#define MCAN_RXF0S_F0F (0x1u << 24) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Fill Level */ +#define MCAN_RXF0S_RF0L (0x1u << 25) /**< \brief (MCAN_RXF0S) Receive FIFO 0 Message Lost */ +/* -------- MCAN_RXF0A : (MCAN Offset: 0xA8) Receive FIFO 0 Acknowledge Register -------- */ +#define MCAN_RXF0A_F0AI_Pos 0 +#define MCAN_RXF0A_F0AI_Msk (0x3fu << MCAN_RXF0A_F0AI_Pos) /**< \brief (MCAN_RXF0A) Receive FIFO 0 Acknowledge Index */ +#define MCAN_RXF0A_F0AI(value) ((MCAN_RXF0A_F0AI_Msk & ((value) << MCAN_RXF0A_F0AI_Pos))) +/* -------- MCAN_RXBC : (MCAN Offset: 0xAC) Receive Rx Buffer Configuration Register -------- */ +#define MCAN_RXBC_RBSA_Pos 2 +#define MCAN_RXBC_RBSA_Msk (0x3fffu << MCAN_RXBC_RBSA_Pos) /**< \brief (MCAN_RXBC) Receive Buffer Start Address */ +#define MCAN_RXBC_RBSA(value) ((MCAN_RXBC_RBSA_Msk & ((value) << MCAN_RXBC_RBSA_Pos))) +/* -------- MCAN_RXF1C : (MCAN Offset: 0xB0) Receive FIFO 1 Configuration Register -------- */ +#define MCAN_RXF1C_F1SA_Pos 2 +#define MCAN_RXF1C_F1SA_Msk (0x3fffu << MCAN_RXF1C_F1SA_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1SA(value) ((MCAN_RXF1C_F1SA_Msk & ((value) << MCAN_RXF1C_F1SA_Pos))) +#define MCAN_RXF1C_F1S_Pos 16 +#define MCAN_RXF1C_F1S_Msk (0x7fu << MCAN_RXF1C_F1S_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Start Address */ +#define MCAN_RXF1C_F1S(value) ((MCAN_RXF1C_F1S_Msk & ((value) << MCAN_RXF1C_F1S_Pos))) +#define MCAN_RXF1C_F1WM_Pos 24 +#define MCAN_RXF1C_F1WM_Msk (0x7fu << MCAN_RXF1C_F1WM_Pos) /**< \brief (MCAN_RXF1C) Receive FIFO 1 Watermark */ +#define MCAN_RXF1C_F1WM(value) ((MCAN_RXF1C_F1WM_Msk & ((value) << MCAN_RXF1C_F1WM_Pos))) +#define MCAN_RXF1C_F1OM (0x1u << 31) /**< \brief (MCAN_RXF1C) FIFO 1 Operation Mode */ +/* -------- MCAN_RXF1S : (MCAN Offset: 0xB4) Receive FIFO 1 Status Register -------- */ +#define MCAN_RXF1S_F1FL_Pos 0 +#define MCAN_RXF1S_F1FL_Msk (0x7fu << MCAN_RXF1S_F1FL_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_F1GI_Pos 8 +#define MCAN_RXF1S_F1GI_Msk (0x3fu << MCAN_RXF1S_F1GI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Get Index */ +#define MCAN_RXF1S_F1PI_Pos 16 +#define MCAN_RXF1S_F1PI_Msk (0x3fu << MCAN_RXF1S_F1PI_Pos) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Put Index */ +#define MCAN_RXF1S_F1F (0x1u << 24) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Fill Level */ +#define MCAN_RXF1S_RF1L (0x1u << 25) /**< \brief (MCAN_RXF1S) Receive FIFO 1 Message Lost */ +#define MCAN_RXF1S_DMS_Pos 30 +#define MCAN_RXF1S_DMS_Msk (0x3u << MCAN_RXF1S_DMS_Pos) /**< \brief (MCAN_RXF1S) Debug Message Status */ +#define MCAN_RXF1S_DMS_IDLE (0x0u << 30) /**< \brief (MCAN_RXF1S) Idle state, wait for reception of debug messages, DMA request is cleared. */ +#define MCAN_RXF1S_DMS_MSG_A (0x1u << 30) /**< \brief (MCAN_RXF1S) Debug message A received. */ +#define MCAN_RXF1S_DMS_MSG_AB (0x2u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B received. */ +#define MCAN_RXF1S_DMS_MSG_ABC (0x3u << 30) /**< \brief (MCAN_RXF1S) Debug messages A, B, C received, DMA request is set. */ +/* -------- MCAN_RXF1A : (MCAN Offset: 0xB8) Receive FIFO 1 Acknowledge Register -------- */ +#define MCAN_RXF1A_F1AI_Pos 0 +#define MCAN_RXF1A_F1AI_Msk (0x3fu << MCAN_RXF1A_F1AI_Pos) /**< \brief (MCAN_RXF1A) Receive FIFO 1 Acknowledge Index */ +#define MCAN_RXF1A_F1AI(value) ((MCAN_RXF1A_F1AI_Msk & ((value) << MCAN_RXF1A_F1AI_Pos))) +/* -------- MCAN_RXESC : (MCAN Offset: 0xBC) Receive Buffer / FIFO Element Size Configuration Register -------- */ +#define MCAN_RXESC_F0DS_Pos 0 +#define MCAN_RXESC_F0DS_Msk (0x7u << MCAN_RXESC_F0DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 0 Data Field Size */ +#define MCAN_RXESC_F0DS(value) ((MCAN_RXESC_F0DS_Msk & ((value) << MCAN_RXESC_F0DS_Pos))) +#define MCAN_RXESC_F0DS_8_BYTE (0x0u << 0) /**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_RXESC_F0DS_12_BYTE (0x1u << 0) /**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_RXESC_F0DS_16_BYTE (0x2u << 0) /**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_RXESC_F0DS_20_BYTE (0x3u << 0) /**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_RXESC_F0DS_24_BYTE (0x4u << 0) /**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_RXESC_F0DS_32_BYTE (0x5u << 0) /**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_RXESC_F0DS_48_BYTE (0x6u << 0) /**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_RXESC_F0DS_64_BYTE (0x7u << 0) /**< \brief (MCAN_RXESC) 64 byte data field */ +#define MCAN_RXESC_F1DS_Pos 4 +#define MCAN_RXESC_F1DS_Msk (0x7u << MCAN_RXESC_F1DS_Pos) /**< \brief (MCAN_RXESC) Receive FIFO 1 Data Field Size */ +#define MCAN_RXESC_F1DS(value) ((MCAN_RXESC_F1DS_Msk & ((value) << MCAN_RXESC_F1DS_Pos))) +#define MCAN_RXESC_F1DS_8_BYTE (0x0u << 4) /**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_RXESC_F1DS_12_BYTE (0x1u << 4) /**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_RXESC_F1DS_16_BYTE (0x2u << 4) /**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_RXESC_F1DS_20_BYTE (0x3u << 4) /**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_RXESC_F1DS_24_BYTE (0x4u << 4) /**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_RXESC_F1DS_32_BYTE (0x5u << 4) /**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_RXESC_F1DS_48_BYTE (0x6u << 4) /**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_RXESC_F1DS_64_BYTE (0x7u << 4) /**< \brief (MCAN_RXESC) 64 byte data field */ +#define MCAN_RXESC_RBDS_Pos 8 +#define MCAN_RXESC_RBDS_Msk (0x7u << MCAN_RXESC_RBDS_Pos) /**< \brief (MCAN_RXESC) Receive Buffer Data Field Size */ +#define MCAN_RXESC_RBDS(value) ((MCAN_RXESC_RBDS_Msk & ((value) << MCAN_RXESC_RBDS_Pos))) +#define MCAN_RXESC_RBDS_8_BYTE (0x0u << 8) /**< \brief (MCAN_RXESC) 8 byte data field */ +#define MCAN_RXESC_RBDS_12_BYTE (0x1u << 8) /**< \brief (MCAN_RXESC) 12 byte data field */ +#define MCAN_RXESC_RBDS_16_BYTE (0x2u << 8) /**< \brief (MCAN_RXESC) 16 byte data field */ +#define MCAN_RXESC_RBDS_20_BYTE (0x3u << 8) /**< \brief (MCAN_RXESC) 20 byte data field */ +#define MCAN_RXESC_RBDS_24_BYTE (0x4u << 8) /**< \brief (MCAN_RXESC) 24 byte data field */ +#define MCAN_RXESC_RBDS_32_BYTE (0x5u << 8) /**< \brief (MCAN_RXESC) 32 byte data field */ +#define MCAN_RXESC_RBDS_48_BYTE (0x6u << 8) /**< \brief (MCAN_RXESC) 48 byte data field */ +#define MCAN_RXESC_RBDS_64_BYTE (0x7u << 8) /**< \brief (MCAN_RXESC) 64 byte data field */ +/* -------- MCAN_TXBC : (MCAN Offset: 0xC0) Transmit Buffer Configuration Register -------- */ +#define MCAN_TXBC_TBSA_Pos 2 +#define MCAN_TXBC_TBSA_Msk (0x3fffu << MCAN_TXBC_TBSA_Pos) /**< \brief (MCAN_TXBC) Tx Buffers Start Address */ +#define MCAN_TXBC_TBSA(value) ((MCAN_TXBC_TBSA_Msk & ((value) << MCAN_TXBC_TBSA_Pos))) +#define MCAN_TXBC_NDTB_Pos 16 +#define MCAN_TXBC_NDTB_Msk (0x3fu << MCAN_TXBC_NDTB_Pos) /**< \brief (MCAN_TXBC) Number of Dedicated Transmit Buffers */ +#define MCAN_TXBC_NDTB(value) ((MCAN_TXBC_NDTB_Msk & ((value) << MCAN_TXBC_NDTB_Pos))) +#define MCAN_TXBC_TFQS_Pos 24 +#define MCAN_TXBC_TFQS_Msk (0x3fu << MCAN_TXBC_TFQS_Pos) /**< \brief (MCAN_TXBC) Transmit FIFO/Queue Size */ +#define MCAN_TXBC_TFQS(value) ((MCAN_TXBC_TFQS_Msk & ((value) << MCAN_TXBC_TFQS_Pos))) +#define MCAN_TXBC_TFQM (0x1u << 30) /**< \brief (MCAN_TXBC) Tx FIFO/Queue Mode */ +/* -------- MCAN_TXFQS : (MCAN Offset: 0xC4) Transmit FIFO/Queue Status Register -------- */ +#define MCAN_TXFQS_TFFL_Pos 0 +#define MCAN_TXFQS_TFFL_Msk (0x3fu << MCAN_TXFQS_TFFL_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Free Level */ +#define MCAN_TXFQS_TFGI_Pos 8 +#define MCAN_TXFQS_TFGI_Msk (0x1fu << MCAN_TXFQS_TFGI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO Get Index */ +#define MCAN_TXFQS_TFQPI_Pos 16 +#define MCAN_TXFQS_TFQPI_Msk (0x1fu << MCAN_TXFQS_TFQPI_Pos) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Put Index */ +#define MCAN_TXFQS_TFQF (0x1u << 21) /**< \brief (MCAN_TXFQS) Tx FIFO/Queue Full */ +/* -------- MCAN_TXESC : (MCAN Offset: 0xC8) Transmit Buffer Element Size Configuration Register -------- */ +#define MCAN_TXESC_TBDS_Pos 0 +#define MCAN_TXESC_TBDS_Msk (0x7u << MCAN_TXESC_TBDS_Pos) /**< \brief (MCAN_TXESC) Tx Buffer Data Field Size */ +#define MCAN_TXESC_TBDS(value) ((MCAN_TXESC_TBDS_Msk & ((value) << MCAN_TXESC_TBDS_Pos))) +#define MCAN_TXESC_TBDS_8_BYTE (0x0u << 0) /**< \brief (MCAN_TXESC) 8 byte data field */ +#define MCAN_TXESC_TBDS_12_BYTE (0x1u << 0) /**< \brief (MCAN_TXESC) 12 byte data field */ +#define MCAN_TXESC_TBDS_16_BYTE (0x2u << 0) /**< \brief (MCAN_TXESC) 16 byte data field */ +#define MCAN_TXESC_TBDS_20_BYTE (0x3u << 0) /**< \brief (MCAN_TXESC) 20 byte data field */ +#define MCAN_TXESC_TBDS_24_BYTE (0x4u << 0) /**< \brief (MCAN_TXESC) 24 byte data field */ +#define MCAN_TXESC_TBDS_32_BYTE (0x5u << 0) /**< \brief (MCAN_TXESC) 32 byte data field */ +#define MCAN_TXESC_TBDS_48_BYTE (0x6u << 0) /**< \brief (MCAN_TXESC) 48 byte data field */ +#define MCAN_TXESC_TBDS_64_BYTE (0x7u << 0) /**< \brief (MCAN_TXESC) 64 byte data field */ +/* -------- MCAN_TXBRP : (MCAN Offset: 0xCC) Transmit Buffer Request Pending Register -------- */ +#define MCAN_TXBRP_TRP0 (0x1u << 0) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 0 */ +#define MCAN_TXBRP_TRP1 (0x1u << 1) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 1 */ +#define MCAN_TXBRP_TRP2 (0x1u << 2) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 2 */ +#define MCAN_TXBRP_TRP3 (0x1u << 3) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 3 */ +#define MCAN_TXBRP_TRP4 (0x1u << 4) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 4 */ +#define MCAN_TXBRP_TRP5 (0x1u << 5) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 5 */ +#define MCAN_TXBRP_TRP6 (0x1u << 6) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 6 */ +#define MCAN_TXBRP_TRP7 (0x1u << 7) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 7 */ +#define MCAN_TXBRP_TRP8 (0x1u << 8) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 8 */ +#define MCAN_TXBRP_TRP9 (0x1u << 9) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 9 */ +#define MCAN_TXBRP_TRP10 (0x1u << 10) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 10 */ +#define MCAN_TXBRP_TRP11 (0x1u << 11) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 11 */ +#define MCAN_TXBRP_TRP12 (0x1u << 12) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 12 */ +#define MCAN_TXBRP_TRP13 (0x1u << 13) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 13 */ +#define MCAN_TXBRP_TRP14 (0x1u << 14) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 14 */ +#define MCAN_TXBRP_TRP15 (0x1u << 15) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 15 */ +#define MCAN_TXBRP_TRP16 (0x1u << 16) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 16 */ +#define MCAN_TXBRP_TRP17 (0x1u << 17) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 17 */ +#define MCAN_TXBRP_TRP18 (0x1u << 18) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 18 */ +#define MCAN_TXBRP_TRP19 (0x1u << 19) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 19 */ +#define MCAN_TXBRP_TRP20 (0x1u << 20) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 20 */ +#define MCAN_TXBRP_TRP21 (0x1u << 21) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 21 */ +#define MCAN_TXBRP_TRP22 (0x1u << 22) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 22 */ +#define MCAN_TXBRP_TRP23 (0x1u << 23) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 23 */ +#define MCAN_TXBRP_TRP24 (0x1u << 24) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 24 */ +#define MCAN_TXBRP_TRP25 (0x1u << 25) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 25 */ +#define MCAN_TXBRP_TRP26 (0x1u << 26) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 26 */ +#define MCAN_TXBRP_TRP27 (0x1u << 27) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 27 */ +#define MCAN_TXBRP_TRP28 (0x1u << 28) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 28 */ +#define MCAN_TXBRP_TRP29 (0x1u << 29) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 29 */ +#define MCAN_TXBRP_TRP30 (0x1u << 30) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 30 */ +#define MCAN_TXBRP_TRP31 (0x1u << 31) /**< \brief (MCAN_TXBRP) Transmission Request Pending for Buffer 31 */ +/* -------- MCAN_TXBAR : (MCAN Offset: 0xD0) Transmit Buffer Add Request Register -------- */ +#define MCAN_TXBAR_AR0 (0x1u << 0) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 0 */ +#define MCAN_TXBAR_AR1 (0x1u << 1) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 1 */ +#define MCAN_TXBAR_AR2 (0x1u << 2) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 2 */ +#define MCAN_TXBAR_AR3 (0x1u << 3) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 3 */ +#define MCAN_TXBAR_AR4 (0x1u << 4) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 4 */ +#define MCAN_TXBAR_AR5 (0x1u << 5) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 5 */ +#define MCAN_TXBAR_AR6 (0x1u << 6) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 6 */ +#define MCAN_TXBAR_AR7 (0x1u << 7) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 7 */ +#define MCAN_TXBAR_AR8 (0x1u << 8) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 8 */ +#define MCAN_TXBAR_AR9 (0x1u << 9) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 9 */ +#define MCAN_TXBAR_AR10 (0x1u << 10) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 10 */ +#define MCAN_TXBAR_AR11 (0x1u << 11) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 11 */ +#define MCAN_TXBAR_AR12 (0x1u << 12) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 12 */ +#define MCAN_TXBAR_AR13 (0x1u << 13) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 13 */ +#define MCAN_TXBAR_AR14 (0x1u << 14) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 14 */ +#define MCAN_TXBAR_AR15 (0x1u << 15) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 15 */ +#define MCAN_TXBAR_AR16 (0x1u << 16) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 16 */ +#define MCAN_TXBAR_AR17 (0x1u << 17) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 17 */ +#define MCAN_TXBAR_AR18 (0x1u << 18) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 18 */ +#define MCAN_TXBAR_AR19 (0x1u << 19) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 19 */ +#define MCAN_TXBAR_AR20 (0x1u << 20) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 20 */ +#define MCAN_TXBAR_AR21 (0x1u << 21) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 21 */ +#define MCAN_TXBAR_AR22 (0x1u << 22) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 22 */ +#define MCAN_TXBAR_AR23 (0x1u << 23) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 23 */ +#define MCAN_TXBAR_AR24 (0x1u << 24) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 24 */ +#define MCAN_TXBAR_AR25 (0x1u << 25) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 25 */ +#define MCAN_TXBAR_AR26 (0x1u << 26) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 26 */ +#define MCAN_TXBAR_AR27 (0x1u << 27) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 27 */ +#define MCAN_TXBAR_AR28 (0x1u << 28) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 28 */ +#define MCAN_TXBAR_AR29 (0x1u << 29) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 29 */ +#define MCAN_TXBAR_AR30 (0x1u << 30) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 30 */ +#define MCAN_TXBAR_AR31 (0x1u << 31) /**< \brief (MCAN_TXBAR) Add Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBCR : (MCAN Offset: 0xD4) Transmit Buffer Cancellation Request Register -------- */ +#define MCAN_TXBCR_CR0 (0x1u << 0) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 0 */ +#define MCAN_TXBCR_CR1 (0x1u << 1) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 1 */ +#define MCAN_TXBCR_CR2 (0x1u << 2) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 2 */ +#define MCAN_TXBCR_CR3 (0x1u << 3) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 3 */ +#define MCAN_TXBCR_CR4 (0x1u << 4) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 4 */ +#define MCAN_TXBCR_CR5 (0x1u << 5) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 5 */ +#define MCAN_TXBCR_CR6 (0x1u << 6) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 6 */ +#define MCAN_TXBCR_CR7 (0x1u << 7) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 7 */ +#define MCAN_TXBCR_CR8 (0x1u << 8) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 8 */ +#define MCAN_TXBCR_CR9 (0x1u << 9) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 9 */ +#define MCAN_TXBCR_CR10 (0x1u << 10) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 10 */ +#define MCAN_TXBCR_CR11 (0x1u << 11) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 11 */ +#define MCAN_TXBCR_CR12 (0x1u << 12) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 12 */ +#define MCAN_TXBCR_CR13 (0x1u << 13) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 13 */ +#define MCAN_TXBCR_CR14 (0x1u << 14) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 14 */ +#define MCAN_TXBCR_CR15 (0x1u << 15) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 15 */ +#define MCAN_TXBCR_CR16 (0x1u << 16) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 16 */ +#define MCAN_TXBCR_CR17 (0x1u << 17) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 17 */ +#define MCAN_TXBCR_CR18 (0x1u << 18) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 18 */ +#define MCAN_TXBCR_CR19 (0x1u << 19) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 19 */ +#define MCAN_TXBCR_CR20 (0x1u << 20) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 20 */ +#define MCAN_TXBCR_CR21 (0x1u << 21) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 21 */ +#define MCAN_TXBCR_CR22 (0x1u << 22) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 22 */ +#define MCAN_TXBCR_CR23 (0x1u << 23) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 23 */ +#define MCAN_TXBCR_CR24 (0x1u << 24) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 24 */ +#define MCAN_TXBCR_CR25 (0x1u << 25) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 25 */ +#define MCAN_TXBCR_CR26 (0x1u << 26) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 26 */ +#define MCAN_TXBCR_CR27 (0x1u << 27) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 27 */ +#define MCAN_TXBCR_CR28 (0x1u << 28) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 28 */ +#define MCAN_TXBCR_CR29 (0x1u << 29) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 29 */ +#define MCAN_TXBCR_CR30 (0x1u << 30) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 30 */ +#define MCAN_TXBCR_CR31 (0x1u << 31) /**< \brief (MCAN_TXBCR) Cancellation Request for Transmit Buffer 31 */ +/* -------- MCAN_TXBTO : (MCAN Offset: 0xD8) Transmit Buffer Transmission Occurred Register -------- */ +#define MCAN_TXBTO_TO0 (0x1u << 0) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 0 */ +#define MCAN_TXBTO_TO1 (0x1u << 1) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 1 */ +#define MCAN_TXBTO_TO2 (0x1u << 2) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 2 */ +#define MCAN_TXBTO_TO3 (0x1u << 3) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 3 */ +#define MCAN_TXBTO_TO4 (0x1u << 4) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 4 */ +#define MCAN_TXBTO_TO5 (0x1u << 5) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 5 */ +#define MCAN_TXBTO_TO6 (0x1u << 6) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 6 */ +#define MCAN_TXBTO_TO7 (0x1u << 7) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 7 */ +#define MCAN_TXBTO_TO8 (0x1u << 8) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 8 */ +#define MCAN_TXBTO_TO9 (0x1u << 9) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 9 */ +#define MCAN_TXBTO_TO10 (0x1u << 10) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 10 */ +#define MCAN_TXBTO_TO11 (0x1u << 11) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 11 */ +#define MCAN_TXBTO_TO12 (0x1u << 12) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 12 */ +#define MCAN_TXBTO_TO13 (0x1u << 13) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 13 */ +#define MCAN_TXBTO_TO14 (0x1u << 14) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 14 */ +#define MCAN_TXBTO_TO15 (0x1u << 15) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 15 */ +#define MCAN_TXBTO_TO16 (0x1u << 16) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 16 */ +#define MCAN_TXBTO_TO17 (0x1u << 17) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 17 */ +#define MCAN_TXBTO_TO18 (0x1u << 18) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 18 */ +#define MCAN_TXBTO_TO19 (0x1u << 19) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 19 */ +#define MCAN_TXBTO_TO20 (0x1u << 20) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 20 */ +#define MCAN_TXBTO_TO21 (0x1u << 21) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 21 */ +#define MCAN_TXBTO_TO22 (0x1u << 22) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 22 */ +#define MCAN_TXBTO_TO23 (0x1u << 23) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 23 */ +#define MCAN_TXBTO_TO24 (0x1u << 24) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 24 */ +#define MCAN_TXBTO_TO25 (0x1u << 25) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 25 */ +#define MCAN_TXBTO_TO26 (0x1u << 26) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 26 */ +#define MCAN_TXBTO_TO27 (0x1u << 27) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 27 */ +#define MCAN_TXBTO_TO28 (0x1u << 28) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 28 */ +#define MCAN_TXBTO_TO29 (0x1u << 29) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 29 */ +#define MCAN_TXBTO_TO30 (0x1u << 30) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 30 */ +#define MCAN_TXBTO_TO31 (0x1u << 31) /**< \brief (MCAN_TXBTO) Transmission Occurred for Buffer 31 */ +/* -------- MCAN_TXBCF : (MCAN Offset: 0xDC) Transmit Buffer Cancellation Finished Register -------- */ +#define MCAN_TXBCF_CF0 (0x1u << 0) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 0 */ +#define MCAN_TXBCF_CF1 (0x1u << 1) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 1 */ +#define MCAN_TXBCF_CF2 (0x1u << 2) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 2 */ +#define MCAN_TXBCF_CF3 (0x1u << 3) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 3 */ +#define MCAN_TXBCF_CF4 (0x1u << 4) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 4 */ +#define MCAN_TXBCF_CF5 (0x1u << 5) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 5 */ +#define MCAN_TXBCF_CF6 (0x1u << 6) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 6 */ +#define MCAN_TXBCF_CF7 (0x1u << 7) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 7 */ +#define MCAN_TXBCF_CF8 (0x1u << 8) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 8 */ +#define MCAN_TXBCF_CF9 (0x1u << 9) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 9 */ +#define MCAN_TXBCF_CF10 (0x1u << 10) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 10 */ +#define MCAN_TXBCF_CF11 (0x1u << 11) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 11 */ +#define MCAN_TXBCF_CF12 (0x1u << 12) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 12 */ +#define MCAN_TXBCF_CF13 (0x1u << 13) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 13 */ +#define MCAN_TXBCF_CF14 (0x1u << 14) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 14 */ +#define MCAN_TXBCF_CF15 (0x1u << 15) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 15 */ +#define MCAN_TXBCF_CF16 (0x1u << 16) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 16 */ +#define MCAN_TXBCF_CF17 (0x1u << 17) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 17 */ +#define MCAN_TXBCF_CF18 (0x1u << 18) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 18 */ +#define MCAN_TXBCF_CF19 (0x1u << 19) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 19 */ +#define MCAN_TXBCF_CF20 (0x1u << 20) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 20 */ +#define MCAN_TXBCF_CF21 (0x1u << 21) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 21 */ +#define MCAN_TXBCF_CF22 (0x1u << 22) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 22 */ +#define MCAN_TXBCF_CF23 (0x1u << 23) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 23 */ +#define MCAN_TXBCF_CF24 (0x1u << 24) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 24 */ +#define MCAN_TXBCF_CF25 (0x1u << 25) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 25 */ +#define MCAN_TXBCF_CF26 (0x1u << 26) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 26 */ +#define MCAN_TXBCF_CF27 (0x1u << 27) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 27 */ +#define MCAN_TXBCF_CF28 (0x1u << 28) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 28 */ +#define MCAN_TXBCF_CF29 (0x1u << 29) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 29 */ +#define MCAN_TXBCF_CF30 (0x1u << 30) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 30 */ +#define MCAN_TXBCF_CF31 (0x1u << 31) /**< \brief (MCAN_TXBCF) Cancellation Finished for Transmit Buffer 31 */ +/* -------- MCAN_TXBTIE : (MCAN Offset: 0xE0) Transmit Buffer Transmission Interrupt Enable Register -------- */ +#define MCAN_TXBTIE_TIE0 (0x1u << 0) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 0 */ +#define MCAN_TXBTIE_TIE1 (0x1u << 1) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 1 */ +#define MCAN_TXBTIE_TIE2 (0x1u << 2) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 2 */ +#define MCAN_TXBTIE_TIE3 (0x1u << 3) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 3 */ +#define MCAN_TXBTIE_TIE4 (0x1u << 4) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 4 */ +#define MCAN_TXBTIE_TIE5 (0x1u << 5) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 5 */ +#define MCAN_TXBTIE_TIE6 (0x1u << 6) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 6 */ +#define MCAN_TXBTIE_TIE7 (0x1u << 7) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 7 */ +#define MCAN_TXBTIE_TIE8 (0x1u << 8) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 8 */ +#define MCAN_TXBTIE_TIE9 (0x1u << 9) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 9 */ +#define MCAN_TXBTIE_TIE10 (0x1u << 10) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 10 */ +#define MCAN_TXBTIE_TIE11 (0x1u << 11) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 11 */ +#define MCAN_TXBTIE_TIE12 (0x1u << 12) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 12 */ +#define MCAN_TXBTIE_TIE13 (0x1u << 13) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 13 */ +#define MCAN_TXBTIE_TIE14 (0x1u << 14) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 14 */ +#define MCAN_TXBTIE_TIE15 (0x1u << 15) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 15 */ +#define MCAN_TXBTIE_TIE16 (0x1u << 16) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 16 */ +#define MCAN_TXBTIE_TIE17 (0x1u << 17) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 17 */ +#define MCAN_TXBTIE_TIE18 (0x1u << 18) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 18 */ +#define MCAN_TXBTIE_TIE19 (0x1u << 19) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 19 */ +#define MCAN_TXBTIE_TIE20 (0x1u << 20) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 20 */ +#define MCAN_TXBTIE_TIE21 (0x1u << 21) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 21 */ +#define MCAN_TXBTIE_TIE22 (0x1u << 22) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 22 */ +#define MCAN_TXBTIE_TIE23 (0x1u << 23) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 23 */ +#define MCAN_TXBTIE_TIE24 (0x1u << 24) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 24 */ +#define MCAN_TXBTIE_TIE25 (0x1u << 25) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 25 */ +#define MCAN_TXBTIE_TIE26 (0x1u << 26) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 26 */ +#define MCAN_TXBTIE_TIE27 (0x1u << 27) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 27 */ +#define MCAN_TXBTIE_TIE28 (0x1u << 28) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 28 */ +#define MCAN_TXBTIE_TIE29 (0x1u << 29) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 29 */ +#define MCAN_TXBTIE_TIE30 (0x1u << 30) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 30 */ +#define MCAN_TXBTIE_TIE31 (0x1u << 31) /**< \brief (MCAN_TXBTIE) Transmission Interrupt Enable for Buffer 31 */ +/* -------- MCAN_TXBCIE : (MCAN Offset: 0xE4) Transmit Buffer Cancellation Finished Interrupt Enable Register -------- */ +#define MCAN_TXBCIE_CFIE0 (0x1u << 0) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 0 */ +#define MCAN_TXBCIE_CFIE1 (0x1u << 1) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 1 */ +#define MCAN_TXBCIE_CFIE2 (0x1u << 2) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 2 */ +#define MCAN_TXBCIE_CFIE3 (0x1u << 3) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 3 */ +#define MCAN_TXBCIE_CFIE4 (0x1u << 4) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 4 */ +#define MCAN_TXBCIE_CFIE5 (0x1u << 5) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 5 */ +#define MCAN_TXBCIE_CFIE6 (0x1u << 6) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 6 */ +#define MCAN_TXBCIE_CFIE7 (0x1u << 7) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 7 */ +#define MCAN_TXBCIE_CFIE8 (0x1u << 8) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 8 */ +#define MCAN_TXBCIE_CFIE9 (0x1u << 9) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 9 */ +#define MCAN_TXBCIE_CFIE10 (0x1u << 10) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 10 */ +#define MCAN_TXBCIE_CFIE11 (0x1u << 11) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 11 */ +#define MCAN_TXBCIE_CFIE12 (0x1u << 12) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 12 */ +#define MCAN_TXBCIE_CFIE13 (0x1u << 13) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 13 */ +#define MCAN_TXBCIE_CFIE14 (0x1u << 14) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 14 */ +#define MCAN_TXBCIE_CFIE15 (0x1u << 15) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 15 */ +#define MCAN_TXBCIE_CFIE16 (0x1u << 16) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 16 */ +#define MCAN_TXBCIE_CFIE17 (0x1u << 17) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 17 */ +#define MCAN_TXBCIE_CFIE18 (0x1u << 18) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 18 */ +#define MCAN_TXBCIE_CFIE19 (0x1u << 19) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 19 */ +#define MCAN_TXBCIE_CFIE20 (0x1u << 20) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 20 */ +#define MCAN_TXBCIE_CFIE21 (0x1u << 21) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 21 */ +#define MCAN_TXBCIE_CFIE22 (0x1u << 22) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 22 */ +#define MCAN_TXBCIE_CFIE23 (0x1u << 23) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 23 */ +#define MCAN_TXBCIE_CFIE24 (0x1u << 24) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 24 */ +#define MCAN_TXBCIE_CFIE25 (0x1u << 25) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 25 */ +#define MCAN_TXBCIE_CFIE26 (0x1u << 26) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 26 */ +#define MCAN_TXBCIE_CFIE27 (0x1u << 27) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 27 */ +#define MCAN_TXBCIE_CFIE28 (0x1u << 28) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 28 */ +#define MCAN_TXBCIE_CFIE29 (0x1u << 29) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 29 */ +#define MCAN_TXBCIE_CFIE30 (0x1u << 30) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 30 */ +#define MCAN_TXBCIE_CFIE31 (0x1u << 31) /**< \brief (MCAN_TXBCIE) Cancellation Finished Interrupt Enable for Transmit Buffer 31 */ +/* -------- MCAN_TXEFC : (MCAN Offset: 0xF0) Transmit Event FIFO Configuration Register -------- */ +#define MCAN_TXEFC_EFSA_Pos 2 +#define MCAN_TXEFC_EFSA_Msk (0x3fffu << MCAN_TXEFC_EFSA_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Start Address */ +#define MCAN_TXEFC_EFSA(value) ((MCAN_TXEFC_EFSA_Msk & ((value) << MCAN_TXEFC_EFSA_Pos))) +#define MCAN_TXEFC_EFS_Pos 16 +#define MCAN_TXEFC_EFS_Msk (0x3fu << MCAN_TXEFC_EFS_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Size */ +#define MCAN_TXEFC_EFS(value) ((MCAN_TXEFC_EFS_Msk & ((value) << MCAN_TXEFC_EFS_Pos))) +#define MCAN_TXEFC_EFWM_Pos 24 +#define MCAN_TXEFC_EFWM_Msk (0x3fu << MCAN_TXEFC_EFWM_Pos) /**< \brief (MCAN_TXEFC) Event FIFO Watermark */ +#define MCAN_TXEFC_EFWM(value) ((MCAN_TXEFC_EFWM_Msk & ((value) << MCAN_TXEFC_EFWM_Pos))) +/* -------- MCAN_TXEFS : (MCAN Offset: 0xF4) Transmit Event FIFO Status Register -------- */ +#define MCAN_TXEFS_EFFL_Pos 0 +#define MCAN_TXEFS_EFFL_Msk (0x3fu << MCAN_TXEFS_EFFL_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Fill Level */ +#define MCAN_TXEFS_EFGI_Pos 8 +#define MCAN_TXEFS_EFGI_Msk (0x1fu << MCAN_TXEFS_EFGI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Get Index */ +#define MCAN_TXEFS_EFPI_Pos 16 +#define MCAN_TXEFS_EFPI_Msk (0x1fu << MCAN_TXEFS_EFPI_Pos) /**< \brief (MCAN_TXEFS) Event FIFO Put Index */ +#define MCAN_TXEFS_EFF (0x1u << 24) /**< \brief (MCAN_TXEFS) Event FIFO Full */ +#define MCAN_TXEFS_TEFL (0x1u << 25) /**< \brief (MCAN_TXEFS) Tx Event FIFO Element Lost */ +/* -------- MCAN_TXEFA : (MCAN Offset: 0xF8) Transmit Event FIFO Acknowledge Register -------- */ +#define MCAN_TXEFA_EFAI_Pos 0 +#define MCAN_TXEFA_EFAI_Msk (0x1fu << MCAN_TXEFA_EFAI_Pos) /**< \brief (MCAN_TXEFA) Event FIFO Acknowledge Index */ +#define MCAN_TXEFA_EFAI(value) ((MCAN_TXEFA_EFAI_Msk & ((value) << MCAN_TXEFA_EFAI_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MCAN_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_mlb.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_mlb.h new file mode 100644 index 000000000..6124aa833 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_mlb.h @@ -0,0 +1,192 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MLB_COMPONENT_ +#define _SAMV71_MLB_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Media LB */ +/* ============================================================================= */ +/** \addtogroup SAMV71_MLB Media LB */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Mlb hardware registers */ +typedef struct { + __IO uint32_t MLB_MLBC0; /**< \brief (Mlb Offset: 0x000) MediaLB Control 0 Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t MLB_MS0; /**< \brief (Mlb Offset: 0x00C) MediaLB Channel Status 0 Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t MLB_MS1; /**< \brief (Mlb Offset: 0x014) MediaLB Channel Status1 Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t MLB_MSS; /**< \brief (Mlb Offset: 0x020) MediaLB System Status Register */ + __I uint32_t MLB_MSD; /**< \brief (Mlb Offset: 0x024) MediaLB System Data Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t MLB_MIEN; /**< \brief (Mlb Offset: 0x02C) MediaLB Interrupt Enable Register */ + __I uint32_t Reserved5[3]; + __IO uint32_t MLB_MLBC1; /**< \brief (Mlb Offset: 0x03C) MediaLB Control 1 Register */ + __I uint32_t Reserved6[1]; + __I uint32_t Reserved7[15]; + __IO uint32_t MLB_HCTL; /**< \brief (Mlb Offset: 0x080) HBI Control Register */ + __I uint32_t Reserved8[1]; + __IO uint32_t MLB_HCMR[2]; /**< \brief (Mlb Offset: 0x088) HBI Channel Mask 0 Register */ + __I uint32_t MLB_HCER[2]; /**< \brief (Mlb Offset: 0x090) HBI Channel Error 0 Register */ + __I uint32_t MLB_HCBR[2]; /**< \brief (Mlb Offset: 0x098) HBI Channel Busy 0 Register */ + __I uint32_t Reserved9[8]; + __IO uint32_t MLB_MDAT[4]; /**< \brief (Mlb Offset: 0x0C0) MIF Data 0 Register */ + __IO uint32_t MLB_MDWE[4]; /**< \brief (Mlb Offset: 0x0D0) MIF Data Write Enable 0 Register */ + __IO uint32_t MLB_MCTL; /**< \brief (Mlb Offset: 0x0E0) MIF Control Register */ + __IO uint32_t MLB_MADR; /**< \brief (Mlb Offset: 0x0E4) MIF Address Register */ + __I uint32_t Reserved10[182]; + __IO uint32_t MLB_ACTL; /**< \brief (Mlb Offset: 0x3C0) AHB Control Register */ + __I uint32_t Reserved11[3]; + __IO uint32_t MLB_ACSR[2]; /**< \brief (Mlb Offset: 0x3D0) AHB Channel Status 0 Register */ + __IO uint32_t MLB_ACMR[2]; /**< \brief (Mlb Offset: 0x3D8) AHB Channel Mask 0 Register */ +} Mlb; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- MLB_MLBC0 : (MLB Offset: 0x000) MediaLB Control 0 Register -------- */ +#define MLB_MLBC0_MLBEN (0x1u << 0) /**< \brief (MLB_MLBC0) MediaLB Enable */ +#define MLB_MLBC0_MLBCLK_Pos 2 +#define MLB_MLBC0_MLBCLK_Msk (0x7u << MLB_MLBC0_MLBCLK_Pos) /**< \brief (MLB_MLBC0) MLB_CLK (MediaLB clock) speed select */ +#define MLB_MLBC0_MLBCLK(value) ((MLB_MLBC0_MLBCLK_Msk & ((value) << MLB_MLBC0_MLBCLK_Pos))) +#define MLB_MLBC0_MLBCLK_256_FS (0x0u << 2) /**< \brief (MLB_MLBC0) 256xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_512_FS (0x1u << 2) /**< \brief (MLB_MLBC0) 512xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_MLBCLK_1024_FS (0x2u << 2) /**< \brief (MLB_MLBC0) 1024xFs (for MLBPEN = 0) */ +#define MLB_MLBC0_ZERO (0x1u << 5) /**< \brief (MLB_MLBC0) Must be Written to 0 */ +#define MLB_MLBC0_MLBLK (0x1u << 7) /**< \brief (MLB_MLBC0) MediaLB Lock Status (read-only) */ +#define MLB_MLBC0_ASYRETRY (0x1u << 12) /**< \brief (MLB_MLBC0) Asynchronous Tx Packet Retry */ +#define MLB_MLBC0_CTLRETRY (0x1u << 14) /**< \brief (MLB_MLBC0) Control Tx Packet Retry */ +#define MLB_MLBC0_FCNT_Pos 15 +#define MLB_MLBC0_FCNT_Msk (0x7u << MLB_MLBC0_FCNT_Pos) /**< \brief (MLB_MLBC0) The number of frames per sub-buffer for synchronous channels */ +#define MLB_MLBC0_FCNT(value) ((MLB_MLBC0_FCNT_Msk & ((value) << MLB_MLBC0_FCNT_Pos))) +#define MLB_MLBC0_FCNT_1_FRAME (0x0u << 15) /**< \brief (MLB_MLBC0) 1 frame per sub-buffer (Operation is the same as Standard mode.) */ +#define MLB_MLBC0_FCNT_2_FRAMES (0x1u << 15) /**< \brief (MLB_MLBC0) 2 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_4_FRAMES (0x2u << 15) /**< \brief (MLB_MLBC0) 4 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_8_FRAMES (0x3u << 15) /**< \brief (MLB_MLBC0) 8 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_16_FRAMES (0x4u << 15) /**< \brief (MLB_MLBC0) 16 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_32_FRAMES (0x5u << 15) /**< \brief (MLB_MLBC0) 32 frames per sub-buffer */ +#define MLB_MLBC0_FCNT_64_FRAMES (0x6u << 15) /**< \brief (MLB_MLBC0) 64 frames per sub-buffer */ +/* -------- MLB_MS0 : (MLB Offset: 0x00C) MediaLB Channel Status 0 Register -------- */ +#define MLB_MS0_MCS_Pos 0 +#define MLB_MS0_MCS_Msk (0xffffffffu << MLB_MS0_MCS_Pos) /**< \brief (MLB_MS0) MediaLB Channel Status [31:0] (cleared by writing a 0) */ +#define MLB_MS0_MCS(value) ((MLB_MS0_MCS_Msk & ((value) << MLB_MS0_MCS_Pos))) +/* -------- MLB_MS1 : (MLB Offset: 0x014) MediaLB Channel Status1 Register -------- */ +#define MLB_MS1_MCS_Pos 0 +#define MLB_MS1_MCS_Msk (0xffffffffu << MLB_MS1_MCS_Pos) /**< \brief (MLB_MS1) MediaLB Channel Status [63:32] (cleared by writing a 0) */ +#define MLB_MS1_MCS(value) ((MLB_MS1_MCS_Msk & ((value) << MLB_MS1_MCS_Pos))) +/* -------- MLB_MSS : (MLB Offset: 0x020) MediaLB System Status Register -------- */ +#define MLB_MSS_RSTSYSCMD (0x1u << 0) /**< \brief (MLB_MSS) Reset System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_LKSYSCMD (0x1u << 1) /**< \brief (MLB_MSS) Network Lock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_ULKSYSCMD (0x1u << 2) /**< \brief (MLB_MSS) Network Unlock System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_CSSYSCMD (0x1u << 3) /**< \brief (MLB_MSS) Channel Scan System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SWSYSCMD (0x1u << 4) /**< \brief (MLB_MSS) Software System Command Detected in the System Quadlet (cleared by writing a 0) */ +#define MLB_MSS_SERVREQ (0x1u << 5) /**< \brief (MLB_MSS) Service Request Enabled */ +/* -------- MLB_MSD : (MLB Offset: 0x024) MediaLB System Data Register -------- */ +#define MLB_MSD_SD0_Pos 0 +#define MLB_MSD_SD0_Msk (0xffu << MLB_MSD_SD0_Pos) /**< \brief (MLB_MSD) System Data (Byte 0) */ +#define MLB_MSD_SD1_Pos 8 +#define MLB_MSD_SD1_Msk (0xffu << MLB_MSD_SD1_Pos) /**< \brief (MLB_MSD) System Data (Byte 1) */ +#define MLB_MSD_SD2_Pos 16 +#define MLB_MSD_SD2_Msk (0xffu << MLB_MSD_SD2_Pos) /**< \brief (MLB_MSD) System Data (Byte 2) */ +#define MLB_MSD_SD3_Pos 24 +#define MLB_MSD_SD3_Msk (0xffu << MLB_MSD_SD3_Pos) /**< \brief (MLB_MSD) System Data (Byte 3) */ +/* -------- MLB_MIEN : (MLB Offset: 0x02C) MediaLB Interrupt Enable Register -------- */ +#define MLB_MIEN_ISOC_PE (0x1u << 0) /**< \brief (MLB_MIEN) Isochronous Rx Protocol Error Enable */ +#define MLB_MIEN_ISOC_BUFO (0x1u << 1) /**< \brief (MLB_MIEN) Isochronous Rx Buffer Overflow Enable */ +#define MLB_MIEN_SYNC_PE (0x1u << 16) /**< \brief (MLB_MIEN) Synchronous Protocol Error Enable */ +#define MLB_MIEN_ARX_DONE (0x1u << 17) /**< \brief (MLB_MIEN) Asynchronous Rx Done Enable */ +#define MLB_MIEN_ARX_PE (0x1u << 18) /**< \brief (MLB_MIEN) Asynchronous Rx Protocol Error Enable */ +#define MLB_MIEN_ARX_BREAK (0x1u << 19) /**< \brief (MLB_MIEN) Asynchronous Rx Break Enable */ +#define MLB_MIEN_ATX_DONE (0x1u << 20) /**< \brief (MLB_MIEN) Asynchronous Tx Packet Done Enable */ +#define MLB_MIEN_ATX_PE (0x1u << 21) /**< \brief (MLB_MIEN) Asynchronous Tx Protocol Error Enable */ +#define MLB_MIEN_ATX_BREAK (0x1u << 22) /**< \brief (MLB_MIEN) Asynchronous Tx Break Enable */ +#define MLB_MIEN_CRX_DONE (0x1u << 24) /**< \brief (MLB_MIEN) Control Rx Packet Done Enable */ +#define MLB_MIEN_CRX_PE (0x1u << 25) /**< \brief (MLB_MIEN) Control Rx Protocol Error Enable */ +#define MLB_MIEN_CRX_BREAK (0x1u << 26) /**< \brief (MLB_MIEN) Control Rx Break Enable */ +#define MLB_MIEN_CTX_DONE (0x1u << 27) /**< \brief (MLB_MIEN) Control Tx Packet Done Enable */ +#define MLB_MIEN_CTX_PE (0x1u << 28) /**< \brief (MLB_MIEN) Control Tx Protocol Error Enable */ +#define MLB_MIEN_CTX_BREAK (0x1u << 29) /**< \brief (MLB_MIEN) Control Tx Break Enable */ +/* -------- MLB_MLBC1 : (MLB Offset: 0x03C) MediaLB Control 1 Register -------- */ +#define MLB_MLBC1_LOCK (0x1u << 6) /**< \brief (MLB_MLBC1) MediaLB Lock Error Status (cleared by writing a 0) */ +#define MLB_MLBC1_CLKM (0x1u << 7) /**< \brief (MLB_MLBC1) MediaLB Clock Missing Status (cleared by writing a 0) */ +#define MLB_MLBC1_NDA_Pos 8 +#define MLB_MLBC1_NDA_Msk (0xffu << MLB_MLBC1_NDA_Pos) /**< \brief (MLB_MLBC1) Node Device Address */ +#define MLB_MLBC1_NDA(value) ((MLB_MLBC1_NDA_Msk & ((value) << MLB_MLBC1_NDA_Pos))) +/* -------- MLB_HCTL : (MLB Offset: 0x080) HBI Control Register -------- */ +#define MLB_HCTL_RST0 (0x1u << 0) /**< \brief (MLB_HCTL) Address Generation Unit 0 Software Reset */ +#define MLB_HCTL_RST1 (0x1u << 1) /**< \brief (MLB_HCTL) Address Generation Unit 1 Software Reset */ +#define MLB_HCTL_EN (0x1u << 15) /**< \brief (MLB_HCTL) HBI Enable */ +/* -------- MLB_HCMR[2] : (MLB Offset: 0x088) HBI Channel Mask 0 Register -------- */ +#define MLB_HCMR_CHM_Pos 0 +#define MLB_HCMR_CHM_Msk (0xffffffffu << MLB_HCMR_CHM_Pos) /**< \brief (MLB_HCMR[2]) Bitwise Channel Mask Bit [31:0] */ +#define MLB_HCMR_CHM(value) ((MLB_HCMR_CHM_Msk & ((value) << MLB_HCMR_CHM_Pos))) +/* -------- MLB_HCER[2] : (MLB Offset: 0x090) HBI Channel Error 0 Register -------- */ +#define MLB_HCER_CERR_Pos 0 +#define MLB_HCER_CERR_Msk (0xffffffffu << MLB_HCER_CERR_Pos) /**< \brief (MLB_HCER[2]) Bitwise Channel Error Bit [31:0] */ +/* -------- MLB_HCBR[2] : (MLB Offset: 0x098) HBI Channel Busy 0 Register -------- */ +#define MLB_HCBR_CHB_Pos 0 +#define MLB_HCBR_CHB_Msk (0xffffffffu << MLB_HCBR_CHB_Pos) /**< \brief (MLB_HCBR[2]) Bitwise Channel Busy Bit [31:0] */ +/* -------- MLB_MDAT[4] : (MLB Offset: 0x0C0) MIF Data 0 Register -------- */ +#define MLB_MDAT_DATA_Pos 0 +#define MLB_MDAT_DATA_Msk (0xffffffffu << MLB_MDAT_DATA_Pos) /**< \brief (MLB_MDAT[4]) CRT or DBR Data */ +#define MLB_MDAT_DATA(value) ((MLB_MDAT_DATA_Msk & ((value) << MLB_MDAT_DATA_Pos))) +/* -------- MLB_MDWE[4] : (MLB Offset: 0x0D0) MIF Data Write Enable 0 Register -------- */ +#define MLB_MDWE_MASK_Pos 0 +#define MLB_MDWE_MASK_Msk (0xffffffffu << MLB_MDWE_MASK_Pos) /**< \brief (MLB_MDWE[4]) Bitwise write enable for CTR data - bits[31:0] */ +#define MLB_MDWE_MASK(value) ((MLB_MDWE_MASK_Msk & ((value) << MLB_MDWE_MASK_Pos))) +/* -------- MLB_MCTL : (MLB Offset: 0x0E0) MIF Control Register -------- */ +#define MLB_MCTL_XCMP (0x1u << 0) /**< \brief (MLB_MCTL) Transfer Complete (Write 0 to Clear) */ +/* -------- MLB_MADR : (MLB Offset: 0x0E4) MIF Address Register -------- */ +#define MLB_MADR_ADDR_Pos 0 +#define MLB_MADR_ADDR_Msk (0x3fffu << MLB_MADR_ADDR_Pos) /**< \brief (MLB_MADR) CTR or DBR Address */ +#define MLB_MADR_ADDR(value) ((MLB_MADR_ADDR_Msk & ((value) << MLB_MADR_ADDR_Pos))) +#define MLB_MADR_TB (0x1u << 30) /**< \brief (MLB_MADR) Target Location Bit */ +#define MLB_MADR_TB_CTR (0x0u << 30) /**< \brief (MLB_MADR) Selects CTR */ +#define MLB_MADR_TB_DBR (0x1u << 30) /**< \brief (MLB_MADR) Selects DBR */ +#define MLB_MADR_WNR (0x1u << 31) /**< \brief (MLB_MADR) Write-Not-Read Selection */ +/* -------- MLB_ACTL : (MLB Offset: 0x3C0) AHB Control Register -------- */ +#define MLB_ACTL_SCE (0x1u << 0) /**< \brief (MLB_ACTL) Software Clear Enable */ +#define MLB_ACTL_SMX (0x1u << 1) /**< \brief (MLB_ACTL) AHB Interrupt Mux Enable */ +#define MLB_ACTL_DMA_MODE (0x1u << 2) /**< \brief (MLB_ACTL) DMA Mode */ +#define MLB_ACTL_MPB (0x1u << 4) /**< \brief (MLB_ACTL) DMA Packet Buffering Mode */ +#define MLB_ACTL_MPB_SINGLE_PACKET (0x0u << 4) /**< \brief (MLB_ACTL) Single-packet mode */ +#define MLB_ACTL_MPB_MULTIPLE_PACKET (0x1u << 4) /**< \brief (MLB_ACTL) Multiple-packet mode */ +/* -------- MLB_ACSR[2] : (MLB Offset: 0x3D0) AHB Channel Status 0 Register -------- */ +#define MLB_ACSR_CHS_Pos 0 +#define MLB_ACSR_CHS_Msk (0xffffffffu << MLB_ACSR_CHS_Pos) /**< \brief (MLB_ACSR[2]) Interrupt Status for Logical Channels [31:0] (cleared by writing a 1) */ +#define MLB_ACSR_CHS(value) ((MLB_ACSR_CHS_Msk & ((value) << MLB_ACSR_CHS_Pos))) +/* -------- MLB_ACMR[2] : (MLB Offset: 0x3D8) AHB Channel Mask 0 Register -------- */ +#define MLB_ACMR_CHM_Pos 0 +#define MLB_ACMR_CHM_Msk (0xffffffffu << MLB_ACMR_CHM_Pos) /**< \brief (MLB_ACMR[2]) Bitwise Channel Mask Bits 31 to 0 */ +#define MLB_ACMR_CHM(value) ((MLB_ACMR_CHM_Msk & ((value) << MLB_ACMR_CHM_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_MLB_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pio.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pio.h new file mode 100644 index 000000000..3799b5349 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pio.h @@ -0,0 +1,1785 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIO_COMPONENT_ +#define _SAMV71_PIO_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Parallel Input/Output Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PIO Parallel Input/Output Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pio hardware registers */ +typedef struct { + __O uint32_t PIO_PER; /**< \brief (Pio Offset: 0x0000) PIO Enable Register */ + __O uint32_t PIO_PDR; /**< \brief (Pio Offset: 0x0004) PIO Disable Register */ + __I uint32_t PIO_PSR; /**< \brief (Pio Offset: 0x0008) PIO Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PIO_OER; /**< \brief (Pio Offset: 0x0010) Output Enable Register */ + __O uint32_t PIO_ODR; /**< \brief (Pio Offset: 0x0014) Output Disable Register */ + __I uint32_t PIO_OSR; /**< \brief (Pio Offset: 0x0018) Output Status Register */ + __I uint32_t Reserved2[1]; + __O uint32_t PIO_IFER; /**< \brief (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ + __O uint32_t PIO_IFDR; /**< \brief (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ + __I uint32_t PIO_IFSR; /**< \brief (Pio Offset: 0x0028) Glitch Input Filter Status Register */ + __I uint32_t Reserved3[1]; + __O uint32_t PIO_SODR; /**< \brief (Pio Offset: 0x0030) Set Output Data Register */ + __O uint32_t PIO_CODR; /**< \brief (Pio Offset: 0x0034) Clear Output Data Register */ + __IO uint32_t PIO_ODSR; /**< \brief (Pio Offset: 0x0038) Output Data Status Register */ + __I uint32_t PIO_PDSR; /**< \brief (Pio Offset: 0x003C) Pin Data Status Register */ + __O uint32_t PIO_IER; /**< \brief (Pio Offset: 0x0040) Interrupt Enable Register */ + __O uint32_t PIO_IDR; /**< \brief (Pio Offset: 0x0044) Interrupt Disable Register */ + __I uint32_t PIO_IMR; /**< \brief (Pio Offset: 0x0048) Interrupt Mask Register */ + __I uint32_t PIO_ISR; /**< \brief (Pio Offset: 0x004C) Interrupt Status Register */ + __O uint32_t PIO_MDER; /**< \brief (Pio Offset: 0x0050) Multi-driver Enable Register */ + __O uint32_t PIO_MDDR; /**< \brief (Pio Offset: 0x0054) Multi-driver Disable Register */ + __I uint32_t PIO_MDSR; /**< \brief (Pio Offset: 0x0058) Multi-driver Status Register */ + __I uint32_t Reserved4[1]; + __O uint32_t PIO_PUDR; /**< \brief (Pio Offset: 0x0060) Pull-up Disable Register */ + __O uint32_t PIO_PUER; /**< \brief (Pio Offset: 0x0064) Pull-up Enable Register */ + __I uint32_t PIO_PUSR; /**< \brief (Pio Offset: 0x0068) Pad Pull-up Status Register */ + __I uint32_t Reserved5[1]; + __IO uint32_t PIO_ABCDSR[2]; /**< \brief (Pio Offset: 0x0070) Peripheral Select Register */ + __I uint32_t Reserved6[2]; + __O uint32_t PIO_IFSCDR; /**< \brief (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ + __O uint32_t PIO_IFSCER; /**< \brief (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ + __I uint32_t PIO_IFSCSR; /**< \brief (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ + __IO uint32_t PIO_SCDR; /**< \brief (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ + __O uint32_t PIO_PPDDR; /**< \brief (Pio Offset: 0x0090) Pad Pull-down Disable Register */ + __O uint32_t PIO_PPDER; /**< \brief (Pio Offset: 0x0094) Pad Pull-down Enable Register */ + __I uint32_t PIO_PPDSR; /**< \brief (Pio Offset: 0x0098) Pad Pull-down Status Register */ + __I uint32_t Reserved7[1]; + __O uint32_t PIO_OWER; /**< \brief (Pio Offset: 0x00A0) Output Write Enable */ + __O uint32_t PIO_OWDR; /**< \brief (Pio Offset: 0x00A4) Output Write Disable */ + __I uint32_t PIO_OWSR; /**< \brief (Pio Offset: 0x00A8) Output Write Status Register */ + __I uint32_t Reserved8[1]; + __O uint32_t PIO_AIMER; /**< \brief (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ + __O uint32_t PIO_AIMDR; /**< \brief (Pio Offset: 0x00B4) Additional Interrupt Modes Disable Register */ + __I uint32_t PIO_AIMMR; /**< \brief (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ + __I uint32_t Reserved9[1]; + __O uint32_t PIO_ESR; /**< \brief (Pio Offset: 0x00C0) Edge Select Register */ + __O uint32_t PIO_LSR; /**< \brief (Pio Offset: 0x00C4) Level Select Register */ + __I uint32_t PIO_ELSR; /**< \brief (Pio Offset: 0x00C8) Edge/Level Status Register */ + __I uint32_t Reserved10[1]; + __O uint32_t PIO_FELLSR; /**< \brief (Pio Offset: 0x00D0) Falling Edge/Low-Level Select Register */ + __O uint32_t PIO_REHLSR; /**< \brief (Pio Offset: 0x00D4) Rising Edge/High-Level Select Register */ + __I uint32_t PIO_FRLHSR; /**< \brief (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ + __I uint32_t Reserved11[1]; + __I uint32_t PIO_LOCKSR; /**< \brief (Pio Offset: 0x00E0) Lock Status */ + __IO uint32_t PIO_WPMR; /**< \brief (Pio Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PIO_WPSR; /**< \brief (Pio Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved12[5]; + __IO uint32_t PIO_SCHMITT; /**< \brief (Pio Offset: 0x0100) Schmitt Trigger Register */ + __I uint32_t Reserved13[5]; + __IO uint32_t PIO_DRIVER; /**< \brief (Pio Offset: 0x0118) I/O Drive Register */ + __I uint32_t Reserved14[1]; + __IO uint32_t PIO_KER; /**< \brief (Pio Offset: 0x0120) Keypad Controller Enable Register */ + __IO uint32_t PIO_KRCR; /**< \brief (Pio Offset: 0x0124) Keypad Controller Row Column Register */ + __IO uint32_t PIO_KDR; /**< \brief (Pio Offset: 0x0128) Keypad Controller Debouncing Register */ + __I uint32_t Reserved15[1]; + __O uint32_t PIO_KIER; /**< \brief (Pio Offset: 0x0130) Keypad Controller Interrupt Enable Register */ + __O uint32_t PIO_KIDR; /**< \brief (Pio Offset: 0x0134) Keypad Controller Interrupt Disable Register */ + __I uint32_t PIO_KIMR; /**< \brief (Pio Offset: 0x0138) Keypad Controller Interrupt Mask Register */ + __I uint32_t PIO_KSR; /**< \brief (Pio Offset: 0x013C) Keypad Controller Status Register */ + __I uint32_t PIO_KKPR; /**< \brief (Pio Offset: 0x0140) Keypad Controller Key Press Register */ + __I uint32_t PIO_KKRR; /**< \brief (Pio Offset: 0x0144) Keypad Controller Key Release Register */ + __I uint32_t Reserved16[2]; + __IO uint32_t PIO_PCMR; /**< \brief (Pio Offset: 0x0150) Parallel Capture Mode Register */ + __O uint32_t PIO_PCIER; /**< \brief (Pio Offset: 0x0154) Parallel Capture Interrupt Enable Register */ + __O uint32_t PIO_PCIDR; /**< \brief (Pio Offset: 0x0158) Parallel Capture Interrupt Disable Register */ + __I uint32_t PIO_PCIMR; /**< \brief (Pio Offset: 0x015C) Parallel Capture Interrupt Mask Register */ + __I uint32_t PIO_PCISR; /**< \brief (Pio Offset: 0x0160) Parallel Capture Interrupt Status Register */ + __I uint32_t PIO_PCRHR; /**< \brief (Pio Offset: 0x0164) Parallel Capture Reception Holding Register */ +} Pio; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ +#define PIO_PER_P0 (0x1u << 0) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P1 (0x1u << 1) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P2 (0x1u << 2) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P3 (0x1u << 3) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P4 (0x1u << 4) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P5 (0x1u << 5) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P6 (0x1u << 6) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P7 (0x1u << 7) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P8 (0x1u << 8) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P9 (0x1u << 9) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P10 (0x1u << 10) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P11 (0x1u << 11) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P12 (0x1u << 12) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P13 (0x1u << 13) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P14 (0x1u << 14) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P15 (0x1u << 15) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P16 (0x1u << 16) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P17 (0x1u << 17) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P18 (0x1u << 18) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P19 (0x1u << 19) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P20 (0x1u << 20) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P21 (0x1u << 21) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P22 (0x1u << 22) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P23 (0x1u << 23) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P24 (0x1u << 24) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P25 (0x1u << 25) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P26 (0x1u << 26) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P27 (0x1u << 27) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P28 (0x1u << 28) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P29 (0x1u << 29) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P30 (0x1u << 30) /**< \brief (PIO_PER) PIO Enable */ +#define PIO_PER_P31 (0x1u << 31) /**< \brief (PIO_PER) PIO Enable */ +/* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ +#define PIO_PDR_P0 (0x1u << 0) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P1 (0x1u << 1) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P2 (0x1u << 2) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P3 (0x1u << 3) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P4 (0x1u << 4) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P5 (0x1u << 5) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P6 (0x1u << 6) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P7 (0x1u << 7) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P8 (0x1u << 8) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P9 (0x1u << 9) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P10 (0x1u << 10) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P11 (0x1u << 11) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P12 (0x1u << 12) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P13 (0x1u << 13) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P14 (0x1u << 14) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P15 (0x1u << 15) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P16 (0x1u << 16) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P17 (0x1u << 17) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P18 (0x1u << 18) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P19 (0x1u << 19) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P20 (0x1u << 20) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P21 (0x1u << 21) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P22 (0x1u << 22) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P23 (0x1u << 23) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P24 (0x1u << 24) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P25 (0x1u << 25) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P26 (0x1u << 26) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P27 (0x1u << 27) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P28 (0x1u << 28) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P29 (0x1u << 29) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P30 (0x1u << 30) /**< \brief (PIO_PDR) PIO Disable */ +#define PIO_PDR_P31 (0x1u << 31) /**< \brief (PIO_PDR) PIO Disable */ +/* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ +#define PIO_PSR_P0 (0x1u << 0) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P1 (0x1u << 1) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P2 (0x1u << 2) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P3 (0x1u << 3) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P4 (0x1u << 4) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P5 (0x1u << 5) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P6 (0x1u << 6) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P7 (0x1u << 7) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P8 (0x1u << 8) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P9 (0x1u << 9) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P10 (0x1u << 10) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P11 (0x1u << 11) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P12 (0x1u << 12) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P13 (0x1u << 13) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P14 (0x1u << 14) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P15 (0x1u << 15) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P16 (0x1u << 16) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P17 (0x1u << 17) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P18 (0x1u << 18) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P19 (0x1u << 19) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P20 (0x1u << 20) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P21 (0x1u << 21) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P22 (0x1u << 22) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P23 (0x1u << 23) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P24 (0x1u << 24) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P25 (0x1u << 25) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P26 (0x1u << 26) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P27 (0x1u << 27) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P28 (0x1u << 28) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P29 (0x1u << 29) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P30 (0x1u << 30) /**< \brief (PIO_PSR) PIO Status */ +#define PIO_PSR_P31 (0x1u << 31) /**< \brief (PIO_PSR) PIO Status */ +/* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ +#define PIO_OER_P0 (0x1u << 0) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P1 (0x1u << 1) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P2 (0x1u << 2) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P3 (0x1u << 3) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P4 (0x1u << 4) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P5 (0x1u << 5) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P6 (0x1u << 6) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P7 (0x1u << 7) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P8 (0x1u << 8) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P9 (0x1u << 9) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P10 (0x1u << 10) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P11 (0x1u << 11) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P12 (0x1u << 12) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P13 (0x1u << 13) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P14 (0x1u << 14) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P15 (0x1u << 15) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P16 (0x1u << 16) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P17 (0x1u << 17) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P18 (0x1u << 18) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P19 (0x1u << 19) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P20 (0x1u << 20) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P21 (0x1u << 21) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P22 (0x1u << 22) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P23 (0x1u << 23) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P24 (0x1u << 24) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P25 (0x1u << 25) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P26 (0x1u << 26) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P27 (0x1u << 27) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P28 (0x1u << 28) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P29 (0x1u << 29) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P30 (0x1u << 30) /**< \brief (PIO_OER) Output Enable */ +#define PIO_OER_P31 (0x1u << 31) /**< \brief (PIO_OER) Output Enable */ +/* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ +#define PIO_ODR_P0 (0x1u << 0) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P1 (0x1u << 1) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P2 (0x1u << 2) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P3 (0x1u << 3) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P4 (0x1u << 4) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P5 (0x1u << 5) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P6 (0x1u << 6) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P7 (0x1u << 7) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P8 (0x1u << 8) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P9 (0x1u << 9) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P10 (0x1u << 10) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P11 (0x1u << 11) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P12 (0x1u << 12) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P13 (0x1u << 13) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P14 (0x1u << 14) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P15 (0x1u << 15) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P16 (0x1u << 16) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P17 (0x1u << 17) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P18 (0x1u << 18) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P19 (0x1u << 19) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P20 (0x1u << 20) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P21 (0x1u << 21) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P22 (0x1u << 22) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P23 (0x1u << 23) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P24 (0x1u << 24) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P25 (0x1u << 25) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P26 (0x1u << 26) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P27 (0x1u << 27) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P28 (0x1u << 28) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P29 (0x1u << 29) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P30 (0x1u << 30) /**< \brief (PIO_ODR) Output Disable */ +#define PIO_ODR_P31 (0x1u << 31) /**< \brief (PIO_ODR) Output Disable */ +/* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ +#define PIO_OSR_P0 (0x1u << 0) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P1 (0x1u << 1) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P2 (0x1u << 2) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P3 (0x1u << 3) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P4 (0x1u << 4) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P5 (0x1u << 5) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P6 (0x1u << 6) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P7 (0x1u << 7) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P8 (0x1u << 8) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P9 (0x1u << 9) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P10 (0x1u << 10) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P11 (0x1u << 11) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P12 (0x1u << 12) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P13 (0x1u << 13) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P14 (0x1u << 14) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P15 (0x1u << 15) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P16 (0x1u << 16) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P17 (0x1u << 17) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P18 (0x1u << 18) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P19 (0x1u << 19) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P20 (0x1u << 20) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P21 (0x1u << 21) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P22 (0x1u << 22) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P23 (0x1u << 23) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P24 (0x1u << 24) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P25 (0x1u << 25) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P26 (0x1u << 26) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P27 (0x1u << 27) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P28 (0x1u << 28) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P29 (0x1u << 29) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P30 (0x1u << 30) /**< \brief (PIO_OSR) Output Status */ +#define PIO_OSR_P31 (0x1u << 31) /**< \brief (PIO_OSR) Output Status */ +/* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ +#define PIO_IFER_P0 (0x1u << 0) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P1 (0x1u << 1) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P2 (0x1u << 2) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P3 (0x1u << 3) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P4 (0x1u << 4) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P5 (0x1u << 5) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P6 (0x1u << 6) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P7 (0x1u << 7) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P8 (0x1u << 8) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P9 (0x1u << 9) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P10 (0x1u << 10) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P11 (0x1u << 11) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P12 (0x1u << 12) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P13 (0x1u << 13) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P14 (0x1u << 14) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P15 (0x1u << 15) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P16 (0x1u << 16) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P17 (0x1u << 17) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P18 (0x1u << 18) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P19 (0x1u << 19) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P20 (0x1u << 20) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P21 (0x1u << 21) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P22 (0x1u << 22) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P23 (0x1u << 23) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P24 (0x1u << 24) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P25 (0x1u << 25) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P26 (0x1u << 26) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P27 (0x1u << 27) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P28 (0x1u << 28) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P29 (0x1u << 29) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P30 (0x1u << 30) /**< \brief (PIO_IFER) Input Filter Enable */ +#define PIO_IFER_P31 (0x1u << 31) /**< \brief (PIO_IFER) Input Filter Enable */ +/* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ +#define PIO_IFDR_P0 (0x1u << 0) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P1 (0x1u << 1) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P2 (0x1u << 2) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P3 (0x1u << 3) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P4 (0x1u << 4) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P5 (0x1u << 5) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P6 (0x1u << 6) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P7 (0x1u << 7) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P8 (0x1u << 8) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P9 (0x1u << 9) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P10 (0x1u << 10) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P11 (0x1u << 11) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P12 (0x1u << 12) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P13 (0x1u << 13) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P14 (0x1u << 14) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P15 (0x1u << 15) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P16 (0x1u << 16) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P17 (0x1u << 17) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P18 (0x1u << 18) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P19 (0x1u << 19) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P20 (0x1u << 20) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P21 (0x1u << 21) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P22 (0x1u << 22) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P23 (0x1u << 23) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P24 (0x1u << 24) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P25 (0x1u << 25) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P26 (0x1u << 26) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P27 (0x1u << 27) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P28 (0x1u << 28) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P29 (0x1u << 29) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P30 (0x1u << 30) /**< \brief (PIO_IFDR) Input Filter Disable */ +#define PIO_IFDR_P31 (0x1u << 31) /**< \brief (PIO_IFDR) Input Filter Disable */ +/* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ +#define PIO_IFSR_P0 (0x1u << 0) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P1 (0x1u << 1) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P2 (0x1u << 2) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P3 (0x1u << 3) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P4 (0x1u << 4) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P5 (0x1u << 5) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P6 (0x1u << 6) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P7 (0x1u << 7) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P8 (0x1u << 8) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P9 (0x1u << 9) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P10 (0x1u << 10) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P11 (0x1u << 11) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P12 (0x1u << 12) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P13 (0x1u << 13) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P14 (0x1u << 14) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P15 (0x1u << 15) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P16 (0x1u << 16) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P17 (0x1u << 17) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P18 (0x1u << 18) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P19 (0x1u << 19) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P20 (0x1u << 20) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P21 (0x1u << 21) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P22 (0x1u << 22) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P23 (0x1u << 23) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P24 (0x1u << 24) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P25 (0x1u << 25) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P26 (0x1u << 26) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P27 (0x1u << 27) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P28 (0x1u << 28) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P29 (0x1u << 29) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P30 (0x1u << 30) /**< \brief (PIO_IFSR) Input Filter Status */ +#define PIO_IFSR_P31 (0x1u << 31) /**< \brief (PIO_IFSR) Input Filter Status */ +/* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ +#define PIO_SODR_P0 (0x1u << 0) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P1 (0x1u << 1) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P2 (0x1u << 2) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P3 (0x1u << 3) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P4 (0x1u << 4) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P5 (0x1u << 5) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P6 (0x1u << 6) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P7 (0x1u << 7) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P8 (0x1u << 8) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P9 (0x1u << 9) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P10 (0x1u << 10) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P11 (0x1u << 11) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P12 (0x1u << 12) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P13 (0x1u << 13) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P14 (0x1u << 14) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P15 (0x1u << 15) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P16 (0x1u << 16) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P17 (0x1u << 17) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P18 (0x1u << 18) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P19 (0x1u << 19) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P20 (0x1u << 20) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P21 (0x1u << 21) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P22 (0x1u << 22) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P23 (0x1u << 23) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P24 (0x1u << 24) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P25 (0x1u << 25) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P26 (0x1u << 26) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P27 (0x1u << 27) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P28 (0x1u << 28) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P29 (0x1u << 29) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P30 (0x1u << 30) /**< \brief (PIO_SODR) Set Output Data */ +#define PIO_SODR_P31 (0x1u << 31) /**< \brief (PIO_SODR) Set Output Data */ +/* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ +#define PIO_CODR_P0 (0x1u << 0) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P1 (0x1u << 1) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P2 (0x1u << 2) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P3 (0x1u << 3) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P4 (0x1u << 4) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P5 (0x1u << 5) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P6 (0x1u << 6) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P7 (0x1u << 7) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P8 (0x1u << 8) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P9 (0x1u << 9) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P10 (0x1u << 10) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P11 (0x1u << 11) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P12 (0x1u << 12) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P13 (0x1u << 13) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P14 (0x1u << 14) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P15 (0x1u << 15) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P16 (0x1u << 16) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P17 (0x1u << 17) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P18 (0x1u << 18) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P19 (0x1u << 19) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P20 (0x1u << 20) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P21 (0x1u << 21) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P22 (0x1u << 22) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P23 (0x1u << 23) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P24 (0x1u << 24) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P25 (0x1u << 25) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P26 (0x1u << 26) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P27 (0x1u << 27) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P28 (0x1u << 28) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P29 (0x1u << 29) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P30 (0x1u << 30) /**< \brief (PIO_CODR) Clear Output Data */ +#define PIO_CODR_P31 (0x1u << 31) /**< \brief (PIO_CODR) Clear Output Data */ +/* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ +#define PIO_ODSR_P0 (0x1u << 0) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P1 (0x1u << 1) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P2 (0x1u << 2) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P3 (0x1u << 3) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P4 (0x1u << 4) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P5 (0x1u << 5) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P6 (0x1u << 6) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P7 (0x1u << 7) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P8 (0x1u << 8) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P9 (0x1u << 9) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P10 (0x1u << 10) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P11 (0x1u << 11) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P12 (0x1u << 12) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P13 (0x1u << 13) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P14 (0x1u << 14) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P15 (0x1u << 15) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P16 (0x1u << 16) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P17 (0x1u << 17) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P18 (0x1u << 18) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P19 (0x1u << 19) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P20 (0x1u << 20) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P21 (0x1u << 21) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P22 (0x1u << 22) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P23 (0x1u << 23) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P24 (0x1u << 24) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P25 (0x1u << 25) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P26 (0x1u << 26) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P27 (0x1u << 27) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P28 (0x1u << 28) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P29 (0x1u << 29) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P30 (0x1u << 30) /**< \brief (PIO_ODSR) Output Data Status */ +#define PIO_ODSR_P31 (0x1u << 31) /**< \brief (PIO_ODSR) Output Data Status */ +/* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ +#define PIO_PDSR_P0 (0x1u << 0) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P1 (0x1u << 1) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P2 (0x1u << 2) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P3 (0x1u << 3) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P4 (0x1u << 4) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P5 (0x1u << 5) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P6 (0x1u << 6) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P7 (0x1u << 7) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P8 (0x1u << 8) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P9 (0x1u << 9) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P10 (0x1u << 10) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P11 (0x1u << 11) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P12 (0x1u << 12) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P13 (0x1u << 13) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P14 (0x1u << 14) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P15 (0x1u << 15) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P16 (0x1u << 16) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P17 (0x1u << 17) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P18 (0x1u << 18) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P19 (0x1u << 19) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P20 (0x1u << 20) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P21 (0x1u << 21) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P22 (0x1u << 22) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P23 (0x1u << 23) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P24 (0x1u << 24) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P25 (0x1u << 25) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P26 (0x1u << 26) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P27 (0x1u << 27) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P28 (0x1u << 28) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P29 (0x1u << 29) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P30 (0x1u << 30) /**< \brief (PIO_PDSR) Output Data Status */ +#define PIO_PDSR_P31 (0x1u << 31) /**< \brief (PIO_PDSR) Output Data Status */ +/* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ +#define PIO_IER_P0 (0x1u << 0) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P1 (0x1u << 1) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P2 (0x1u << 2) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P3 (0x1u << 3) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P4 (0x1u << 4) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P5 (0x1u << 5) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P6 (0x1u << 6) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P7 (0x1u << 7) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P8 (0x1u << 8) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P9 (0x1u << 9) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P10 (0x1u << 10) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P11 (0x1u << 11) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P12 (0x1u << 12) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P13 (0x1u << 13) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P14 (0x1u << 14) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P15 (0x1u << 15) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P16 (0x1u << 16) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P17 (0x1u << 17) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P18 (0x1u << 18) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P19 (0x1u << 19) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P20 (0x1u << 20) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P21 (0x1u << 21) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P22 (0x1u << 22) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P23 (0x1u << 23) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P24 (0x1u << 24) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P25 (0x1u << 25) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P26 (0x1u << 26) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P27 (0x1u << 27) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P28 (0x1u << 28) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P29 (0x1u << 29) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P30 (0x1u << 30) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +#define PIO_IER_P31 (0x1u << 31) /**< \brief (PIO_IER) Input Change Interrupt Enable */ +/* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ +#define PIO_IDR_P0 (0x1u << 0) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P1 (0x1u << 1) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P2 (0x1u << 2) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P3 (0x1u << 3) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P4 (0x1u << 4) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P5 (0x1u << 5) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P6 (0x1u << 6) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P7 (0x1u << 7) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P8 (0x1u << 8) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P9 (0x1u << 9) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P10 (0x1u << 10) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P11 (0x1u << 11) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P12 (0x1u << 12) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P13 (0x1u << 13) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P14 (0x1u << 14) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P15 (0x1u << 15) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P16 (0x1u << 16) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P17 (0x1u << 17) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P18 (0x1u << 18) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P19 (0x1u << 19) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P20 (0x1u << 20) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P21 (0x1u << 21) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P22 (0x1u << 22) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P23 (0x1u << 23) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P24 (0x1u << 24) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P25 (0x1u << 25) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P26 (0x1u << 26) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P27 (0x1u << 27) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P28 (0x1u << 28) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P29 (0x1u << 29) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P30 (0x1u << 30) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +#define PIO_IDR_P31 (0x1u << 31) /**< \brief (PIO_IDR) Input Change Interrupt Disable */ +/* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ +#define PIO_IMR_P0 (0x1u << 0) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P1 (0x1u << 1) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P2 (0x1u << 2) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P3 (0x1u << 3) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P4 (0x1u << 4) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P5 (0x1u << 5) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P6 (0x1u << 6) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P7 (0x1u << 7) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P8 (0x1u << 8) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P9 (0x1u << 9) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P10 (0x1u << 10) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P11 (0x1u << 11) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P12 (0x1u << 12) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P13 (0x1u << 13) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P14 (0x1u << 14) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P15 (0x1u << 15) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P16 (0x1u << 16) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P17 (0x1u << 17) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P18 (0x1u << 18) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P19 (0x1u << 19) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P20 (0x1u << 20) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P21 (0x1u << 21) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P22 (0x1u << 22) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P23 (0x1u << 23) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P24 (0x1u << 24) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P25 (0x1u << 25) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P26 (0x1u << 26) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P27 (0x1u << 27) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P28 (0x1u << 28) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P29 (0x1u << 29) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P30 (0x1u << 30) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +#define PIO_IMR_P31 (0x1u << 31) /**< \brief (PIO_IMR) Input Change Interrupt Mask */ +/* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ +#define PIO_ISR_P0 (0x1u << 0) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P1 (0x1u << 1) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P2 (0x1u << 2) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P3 (0x1u << 3) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P4 (0x1u << 4) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P5 (0x1u << 5) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P6 (0x1u << 6) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P7 (0x1u << 7) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P8 (0x1u << 8) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P9 (0x1u << 9) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P10 (0x1u << 10) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P11 (0x1u << 11) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P12 (0x1u << 12) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P13 (0x1u << 13) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P14 (0x1u << 14) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P15 (0x1u << 15) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P16 (0x1u << 16) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P17 (0x1u << 17) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P18 (0x1u << 18) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P19 (0x1u << 19) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P20 (0x1u << 20) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P21 (0x1u << 21) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P22 (0x1u << 22) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P23 (0x1u << 23) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P24 (0x1u << 24) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P25 (0x1u << 25) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P26 (0x1u << 26) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P27 (0x1u << 27) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P28 (0x1u << 28) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P29 (0x1u << 29) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P30 (0x1u << 30) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +#define PIO_ISR_P31 (0x1u << 31) /**< \brief (PIO_ISR) Input Change Interrupt Status */ +/* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ +#define PIO_MDER_P0 (0x1u << 0) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P1 (0x1u << 1) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P2 (0x1u << 2) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P3 (0x1u << 3) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P4 (0x1u << 4) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P5 (0x1u << 5) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P6 (0x1u << 6) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P7 (0x1u << 7) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P8 (0x1u << 8) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P9 (0x1u << 9) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P10 (0x1u << 10) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P11 (0x1u << 11) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P12 (0x1u << 12) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P13 (0x1u << 13) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P14 (0x1u << 14) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P15 (0x1u << 15) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P16 (0x1u << 16) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P17 (0x1u << 17) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P18 (0x1u << 18) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P19 (0x1u << 19) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P20 (0x1u << 20) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P21 (0x1u << 21) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P22 (0x1u << 22) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P23 (0x1u << 23) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P24 (0x1u << 24) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P25 (0x1u << 25) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P26 (0x1u << 26) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P27 (0x1u << 27) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P28 (0x1u << 28) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P29 (0x1u << 29) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P30 (0x1u << 30) /**< \brief (PIO_MDER) Multi-drive Enable */ +#define PIO_MDER_P31 (0x1u << 31) /**< \brief (PIO_MDER) Multi-drive Enable */ +/* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ +#define PIO_MDDR_P0 (0x1u << 0) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P1 (0x1u << 1) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P2 (0x1u << 2) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P3 (0x1u << 3) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P4 (0x1u << 4) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P5 (0x1u << 5) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P6 (0x1u << 6) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P7 (0x1u << 7) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P8 (0x1u << 8) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P9 (0x1u << 9) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P10 (0x1u << 10) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P11 (0x1u << 11) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P12 (0x1u << 12) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P13 (0x1u << 13) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P14 (0x1u << 14) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P15 (0x1u << 15) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P16 (0x1u << 16) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P17 (0x1u << 17) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P18 (0x1u << 18) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P19 (0x1u << 19) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P20 (0x1u << 20) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P21 (0x1u << 21) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P22 (0x1u << 22) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P23 (0x1u << 23) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P24 (0x1u << 24) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P25 (0x1u << 25) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P26 (0x1u << 26) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P27 (0x1u << 27) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P28 (0x1u << 28) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P29 (0x1u << 29) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P30 (0x1u << 30) /**< \brief (PIO_MDDR) Multi-drive Disable */ +#define PIO_MDDR_P31 (0x1u << 31) /**< \brief (PIO_MDDR) Multi-drive Disable */ +/* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ +#define PIO_MDSR_P0 (0x1u << 0) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P1 (0x1u << 1) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P2 (0x1u << 2) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P3 (0x1u << 3) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P4 (0x1u << 4) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P5 (0x1u << 5) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P6 (0x1u << 6) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P7 (0x1u << 7) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P8 (0x1u << 8) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P9 (0x1u << 9) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P10 (0x1u << 10) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P11 (0x1u << 11) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P12 (0x1u << 12) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P13 (0x1u << 13) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P14 (0x1u << 14) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P15 (0x1u << 15) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P16 (0x1u << 16) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P17 (0x1u << 17) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P18 (0x1u << 18) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P19 (0x1u << 19) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P20 (0x1u << 20) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P21 (0x1u << 21) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P22 (0x1u << 22) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P23 (0x1u << 23) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P24 (0x1u << 24) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P25 (0x1u << 25) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P26 (0x1u << 26) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P27 (0x1u << 27) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P28 (0x1u << 28) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P29 (0x1u << 29) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P30 (0x1u << 30) /**< \brief (PIO_MDSR) Multi-drive Status */ +#define PIO_MDSR_P31 (0x1u << 31) /**< \brief (PIO_MDSR) Multi-drive Status */ +/* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ +#define PIO_PUDR_P0 (0x1u << 0) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P1 (0x1u << 1) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P2 (0x1u << 2) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P3 (0x1u << 3) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P4 (0x1u << 4) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P5 (0x1u << 5) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P6 (0x1u << 6) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P7 (0x1u << 7) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P8 (0x1u << 8) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P9 (0x1u << 9) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P10 (0x1u << 10) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P11 (0x1u << 11) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P12 (0x1u << 12) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P13 (0x1u << 13) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P14 (0x1u << 14) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P15 (0x1u << 15) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P16 (0x1u << 16) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P17 (0x1u << 17) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P18 (0x1u << 18) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P19 (0x1u << 19) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P20 (0x1u << 20) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P21 (0x1u << 21) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P22 (0x1u << 22) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P23 (0x1u << 23) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P24 (0x1u << 24) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P25 (0x1u << 25) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P26 (0x1u << 26) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P27 (0x1u << 27) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P28 (0x1u << 28) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P29 (0x1u << 29) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P30 (0x1u << 30) /**< \brief (PIO_PUDR) Pull-Up Disable */ +#define PIO_PUDR_P31 (0x1u << 31) /**< \brief (PIO_PUDR) Pull-Up Disable */ +/* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ +#define PIO_PUER_P0 (0x1u << 0) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P1 (0x1u << 1) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P2 (0x1u << 2) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P3 (0x1u << 3) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P4 (0x1u << 4) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P5 (0x1u << 5) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P6 (0x1u << 6) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P7 (0x1u << 7) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P8 (0x1u << 8) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P9 (0x1u << 9) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P10 (0x1u << 10) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P11 (0x1u << 11) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P12 (0x1u << 12) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P13 (0x1u << 13) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P14 (0x1u << 14) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P15 (0x1u << 15) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P16 (0x1u << 16) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P17 (0x1u << 17) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P18 (0x1u << 18) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P19 (0x1u << 19) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P20 (0x1u << 20) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P21 (0x1u << 21) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P22 (0x1u << 22) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P23 (0x1u << 23) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P24 (0x1u << 24) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P25 (0x1u << 25) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P26 (0x1u << 26) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P27 (0x1u << 27) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P28 (0x1u << 28) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P29 (0x1u << 29) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P30 (0x1u << 30) /**< \brief (PIO_PUER) Pull-Up Enable */ +#define PIO_PUER_P31 (0x1u << 31) /**< \brief (PIO_PUER) Pull-Up Enable */ +/* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ +#define PIO_PUSR_P0 (0x1u << 0) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P1 (0x1u << 1) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P2 (0x1u << 2) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P3 (0x1u << 3) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P4 (0x1u << 4) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P5 (0x1u << 5) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P6 (0x1u << 6) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P7 (0x1u << 7) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P8 (0x1u << 8) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P9 (0x1u << 9) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P10 (0x1u << 10) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P11 (0x1u << 11) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P12 (0x1u << 12) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P13 (0x1u << 13) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P14 (0x1u << 14) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P15 (0x1u << 15) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P16 (0x1u << 16) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P17 (0x1u << 17) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P18 (0x1u << 18) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P19 (0x1u << 19) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P20 (0x1u << 20) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P21 (0x1u << 21) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P22 (0x1u << 22) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P23 (0x1u << 23) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P24 (0x1u << 24) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P25 (0x1u << 25) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P26 (0x1u << 26) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P27 (0x1u << 27) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P28 (0x1u << 28) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P29 (0x1u << 29) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P30 (0x1u << 30) /**< \brief (PIO_PUSR) Pull-Up Status */ +#define PIO_PUSR_P31 (0x1u << 31) /**< \brief (PIO_PUSR) Pull-Up Status */ +/* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ +#define PIO_ABCDSR_P0 (0x1u << 0) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P1 (0x1u << 1) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P2 (0x1u << 2) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P3 (0x1u << 3) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P4 (0x1u << 4) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P5 (0x1u << 5) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P6 (0x1u << 6) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P7 (0x1u << 7) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P8 (0x1u << 8) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P9 (0x1u << 9) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P10 (0x1u << 10) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P11 (0x1u << 11) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P12 (0x1u << 12) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P13 (0x1u << 13) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P14 (0x1u << 14) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P15 (0x1u << 15) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P16 (0x1u << 16) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P17 (0x1u << 17) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P18 (0x1u << 18) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P19 (0x1u << 19) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P20 (0x1u << 20) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P21 (0x1u << 21) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P22 (0x1u << 22) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P23 (0x1u << 23) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P24 (0x1u << 24) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P25 (0x1u << 25) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P26 (0x1u << 26) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P27 (0x1u << 27) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P28 (0x1u << 28) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P29 (0x1u << 29) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P30 (0x1u << 30) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +#define PIO_ABCDSR_P31 (0x1u << 31) /**< \brief (PIO_ABCDSR[2]) Peripheral Select */ +/* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ +#define PIO_IFSCDR_P0 (0x1u << 0) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P1 (0x1u << 1) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P2 (0x1u << 2) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P3 (0x1u << 3) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P4 (0x1u << 4) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P5 (0x1u << 5) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P6 (0x1u << 6) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P7 (0x1u << 7) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P8 (0x1u << 8) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P9 (0x1u << 9) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P10 (0x1u << 10) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P11 (0x1u << 11) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P12 (0x1u << 12) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P13 (0x1u << 13) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P14 (0x1u << 14) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P15 (0x1u << 15) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P16 (0x1u << 16) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P17 (0x1u << 17) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P18 (0x1u << 18) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P19 (0x1u << 19) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P20 (0x1u << 20) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P21 (0x1u << 21) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P22 (0x1u << 22) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P23 (0x1u << 23) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P24 (0x1u << 24) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P25 (0x1u << 25) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P26 (0x1u << 26) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P27 (0x1u << 27) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P28 (0x1u << 28) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P29 (0x1u << 29) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P30 (0x1u << 30) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +#define PIO_IFSCDR_P31 (0x1u << 31) /**< \brief (PIO_IFSCDR) Peripheral Clock Glitch Filtering Select */ +/* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ +#define PIO_IFSCER_P0 (0x1u << 0) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P1 (0x1u << 1) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P2 (0x1u << 2) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P3 (0x1u << 3) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P4 (0x1u << 4) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P5 (0x1u << 5) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P6 (0x1u << 6) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P7 (0x1u << 7) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P8 (0x1u << 8) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P9 (0x1u << 9) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P10 (0x1u << 10) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P11 (0x1u << 11) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P12 (0x1u << 12) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P13 (0x1u << 13) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P14 (0x1u << 14) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P15 (0x1u << 15) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P16 (0x1u << 16) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P17 (0x1u << 17) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P18 (0x1u << 18) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P19 (0x1u << 19) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P20 (0x1u << 20) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P21 (0x1u << 21) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P22 (0x1u << 22) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P23 (0x1u << 23) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P24 (0x1u << 24) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P25 (0x1u << 25) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P26 (0x1u << 26) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P27 (0x1u << 27) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P28 (0x1u << 28) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P29 (0x1u << 29) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P30 (0x1u << 30) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +#define PIO_IFSCER_P31 (0x1u << 31) /**< \brief (PIO_IFSCER) Slow Clock Debouncing Filtering Select */ +/* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ +#define PIO_IFSCSR_P0 (0x1u << 0) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P1 (0x1u << 1) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P2 (0x1u << 2) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P3 (0x1u << 3) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P4 (0x1u << 4) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P5 (0x1u << 5) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P6 (0x1u << 6) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P7 (0x1u << 7) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P8 (0x1u << 8) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P9 (0x1u << 9) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P10 (0x1u << 10) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P11 (0x1u << 11) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P12 (0x1u << 12) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P13 (0x1u << 13) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P14 (0x1u << 14) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P15 (0x1u << 15) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P16 (0x1u << 16) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P17 (0x1u << 17) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P18 (0x1u << 18) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P19 (0x1u << 19) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P20 (0x1u << 20) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P21 (0x1u << 21) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P22 (0x1u << 22) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P23 (0x1u << 23) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P24 (0x1u << 24) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P25 (0x1u << 25) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P26 (0x1u << 26) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P27 (0x1u << 27) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P28 (0x1u << 28) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P29 (0x1u << 29) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P30 (0x1u << 30) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +#define PIO_IFSCSR_P31 (0x1u << 31) /**< \brief (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ +/* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ +#define PIO_SCDR_DIV_Pos 0 +#define PIO_SCDR_DIV_Msk (0x3fffu << PIO_SCDR_DIV_Pos) /**< \brief (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ +#define PIO_SCDR_DIV(value) ((PIO_SCDR_DIV_Msk & ((value) << PIO_SCDR_DIV_Pos))) +/* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ +#define PIO_PPDDR_P0 (0x1u << 0) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P1 (0x1u << 1) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P2 (0x1u << 2) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P3 (0x1u << 3) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P4 (0x1u << 4) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P5 (0x1u << 5) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P6 (0x1u << 6) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P7 (0x1u << 7) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P8 (0x1u << 8) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P9 (0x1u << 9) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P10 (0x1u << 10) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P11 (0x1u << 11) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P12 (0x1u << 12) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P13 (0x1u << 13) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P14 (0x1u << 14) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P15 (0x1u << 15) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P16 (0x1u << 16) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P17 (0x1u << 17) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P18 (0x1u << 18) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P19 (0x1u << 19) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P20 (0x1u << 20) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P21 (0x1u << 21) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P22 (0x1u << 22) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P23 (0x1u << 23) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P24 (0x1u << 24) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P25 (0x1u << 25) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P26 (0x1u << 26) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P27 (0x1u << 27) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P28 (0x1u << 28) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P29 (0x1u << 29) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P30 (0x1u << 30) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +#define PIO_PPDDR_P31 (0x1u << 31) /**< \brief (PIO_PPDDR) Pull-Down Disable */ +/* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ +#define PIO_PPDER_P0 (0x1u << 0) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P1 (0x1u << 1) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P2 (0x1u << 2) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P3 (0x1u << 3) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P4 (0x1u << 4) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P5 (0x1u << 5) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P6 (0x1u << 6) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P7 (0x1u << 7) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P8 (0x1u << 8) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P9 (0x1u << 9) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P10 (0x1u << 10) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P11 (0x1u << 11) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P12 (0x1u << 12) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P13 (0x1u << 13) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P14 (0x1u << 14) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P15 (0x1u << 15) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P16 (0x1u << 16) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P17 (0x1u << 17) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P18 (0x1u << 18) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P19 (0x1u << 19) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P20 (0x1u << 20) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P21 (0x1u << 21) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P22 (0x1u << 22) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P23 (0x1u << 23) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P24 (0x1u << 24) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P25 (0x1u << 25) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P26 (0x1u << 26) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P27 (0x1u << 27) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P28 (0x1u << 28) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P29 (0x1u << 29) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P30 (0x1u << 30) /**< \brief (PIO_PPDER) Pull-Down Enable */ +#define PIO_PPDER_P31 (0x1u << 31) /**< \brief (PIO_PPDER) Pull-Down Enable */ +/* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ +#define PIO_PPDSR_P0 (0x1u << 0) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P1 (0x1u << 1) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P2 (0x1u << 2) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P3 (0x1u << 3) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P4 (0x1u << 4) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P5 (0x1u << 5) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P6 (0x1u << 6) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P7 (0x1u << 7) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P8 (0x1u << 8) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P9 (0x1u << 9) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P10 (0x1u << 10) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P11 (0x1u << 11) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P12 (0x1u << 12) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P13 (0x1u << 13) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P14 (0x1u << 14) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P15 (0x1u << 15) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P16 (0x1u << 16) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P17 (0x1u << 17) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P18 (0x1u << 18) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P19 (0x1u << 19) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P20 (0x1u << 20) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P21 (0x1u << 21) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P22 (0x1u << 22) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P23 (0x1u << 23) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P24 (0x1u << 24) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P25 (0x1u << 25) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P26 (0x1u << 26) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P27 (0x1u << 27) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P28 (0x1u << 28) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P29 (0x1u << 29) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P30 (0x1u << 30) /**< \brief (PIO_PPDSR) Pull-Down Status */ +#define PIO_PPDSR_P31 (0x1u << 31) /**< \brief (PIO_PPDSR) Pull-Down Status */ +/* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ +#define PIO_OWER_P0 (0x1u << 0) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P1 (0x1u << 1) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P2 (0x1u << 2) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P3 (0x1u << 3) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P4 (0x1u << 4) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P5 (0x1u << 5) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P6 (0x1u << 6) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P7 (0x1u << 7) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P8 (0x1u << 8) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P9 (0x1u << 9) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P10 (0x1u << 10) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P11 (0x1u << 11) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P12 (0x1u << 12) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P13 (0x1u << 13) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P14 (0x1u << 14) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P15 (0x1u << 15) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P16 (0x1u << 16) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P17 (0x1u << 17) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P18 (0x1u << 18) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P19 (0x1u << 19) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P20 (0x1u << 20) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P21 (0x1u << 21) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P22 (0x1u << 22) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P23 (0x1u << 23) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P24 (0x1u << 24) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P25 (0x1u << 25) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P26 (0x1u << 26) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P27 (0x1u << 27) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P28 (0x1u << 28) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P29 (0x1u << 29) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P30 (0x1u << 30) /**< \brief (PIO_OWER) Output Write Enable */ +#define PIO_OWER_P31 (0x1u << 31) /**< \brief (PIO_OWER) Output Write Enable */ +/* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ +#define PIO_OWDR_P0 (0x1u << 0) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P1 (0x1u << 1) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P2 (0x1u << 2) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P3 (0x1u << 3) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P4 (0x1u << 4) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P5 (0x1u << 5) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P6 (0x1u << 6) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P7 (0x1u << 7) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P8 (0x1u << 8) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P9 (0x1u << 9) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P10 (0x1u << 10) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P11 (0x1u << 11) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P12 (0x1u << 12) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P13 (0x1u << 13) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P14 (0x1u << 14) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P15 (0x1u << 15) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P16 (0x1u << 16) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P17 (0x1u << 17) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P18 (0x1u << 18) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P19 (0x1u << 19) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P20 (0x1u << 20) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P21 (0x1u << 21) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P22 (0x1u << 22) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P23 (0x1u << 23) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P24 (0x1u << 24) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P25 (0x1u << 25) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P26 (0x1u << 26) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P27 (0x1u << 27) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P28 (0x1u << 28) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P29 (0x1u << 29) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P30 (0x1u << 30) /**< \brief (PIO_OWDR) Output Write Disable */ +#define PIO_OWDR_P31 (0x1u << 31) /**< \brief (PIO_OWDR) Output Write Disable */ +/* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ +#define PIO_OWSR_P0 (0x1u << 0) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P1 (0x1u << 1) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P2 (0x1u << 2) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P3 (0x1u << 3) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P4 (0x1u << 4) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P5 (0x1u << 5) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P6 (0x1u << 6) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P7 (0x1u << 7) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P8 (0x1u << 8) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P9 (0x1u << 9) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P10 (0x1u << 10) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P11 (0x1u << 11) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P12 (0x1u << 12) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P13 (0x1u << 13) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P14 (0x1u << 14) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P15 (0x1u << 15) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P16 (0x1u << 16) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P17 (0x1u << 17) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P18 (0x1u << 18) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P19 (0x1u << 19) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P20 (0x1u << 20) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P21 (0x1u << 21) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P22 (0x1u << 22) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P23 (0x1u << 23) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P24 (0x1u << 24) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P25 (0x1u << 25) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P26 (0x1u << 26) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P27 (0x1u << 27) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P28 (0x1u << 28) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P29 (0x1u << 29) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P30 (0x1u << 30) /**< \brief (PIO_OWSR) Output Write Status */ +#define PIO_OWSR_P31 (0x1u << 31) /**< \brief (PIO_OWSR) Output Write Status */ +/* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ +#define PIO_AIMER_P0 (0x1u << 0) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P1 (0x1u << 1) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P2 (0x1u << 2) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P3 (0x1u << 3) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P4 (0x1u << 4) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P5 (0x1u << 5) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P6 (0x1u << 6) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P7 (0x1u << 7) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P8 (0x1u << 8) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P9 (0x1u << 9) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P10 (0x1u << 10) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P11 (0x1u << 11) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P12 (0x1u << 12) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P13 (0x1u << 13) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P14 (0x1u << 14) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P15 (0x1u << 15) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P16 (0x1u << 16) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P17 (0x1u << 17) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P18 (0x1u << 18) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P19 (0x1u << 19) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P20 (0x1u << 20) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P21 (0x1u << 21) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P22 (0x1u << 22) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P23 (0x1u << 23) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P24 (0x1u << 24) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P25 (0x1u << 25) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P26 (0x1u << 26) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P27 (0x1u << 27) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P28 (0x1u << 28) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P29 (0x1u << 29) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P30 (0x1u << 30) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +#define PIO_AIMER_P31 (0x1u << 31) /**< \brief (PIO_AIMER) Additional Interrupt Modes Enable */ +/* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disable Register -------- */ +#define PIO_AIMDR_P0 (0x1u << 0) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P1 (0x1u << 1) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P2 (0x1u << 2) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P3 (0x1u << 3) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P4 (0x1u << 4) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P5 (0x1u << 5) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P6 (0x1u << 6) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P7 (0x1u << 7) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P8 (0x1u << 8) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P9 (0x1u << 9) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P10 (0x1u << 10) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P11 (0x1u << 11) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P12 (0x1u << 12) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P13 (0x1u << 13) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P14 (0x1u << 14) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P15 (0x1u << 15) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P16 (0x1u << 16) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P17 (0x1u << 17) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P18 (0x1u << 18) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P19 (0x1u << 19) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P20 (0x1u << 20) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P21 (0x1u << 21) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P22 (0x1u << 22) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P23 (0x1u << 23) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P24 (0x1u << 24) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P25 (0x1u << 25) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P26 (0x1u << 26) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P27 (0x1u << 27) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P28 (0x1u << 28) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P29 (0x1u << 29) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P30 (0x1u << 30) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +#define PIO_AIMDR_P31 (0x1u << 31) /**< \brief (PIO_AIMDR) Additional Interrupt Modes Disable */ +/* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ +#define PIO_AIMMR_P0 (0x1u << 0) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P1 (0x1u << 1) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P2 (0x1u << 2) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P3 (0x1u << 3) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P4 (0x1u << 4) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P5 (0x1u << 5) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P6 (0x1u << 6) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P7 (0x1u << 7) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P8 (0x1u << 8) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P9 (0x1u << 9) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P10 (0x1u << 10) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P11 (0x1u << 11) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P12 (0x1u << 12) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P13 (0x1u << 13) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P14 (0x1u << 14) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P15 (0x1u << 15) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P16 (0x1u << 16) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P17 (0x1u << 17) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P18 (0x1u << 18) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P19 (0x1u << 19) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P20 (0x1u << 20) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P21 (0x1u << 21) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P22 (0x1u << 22) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P23 (0x1u << 23) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P24 (0x1u << 24) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P25 (0x1u << 25) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P26 (0x1u << 26) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P27 (0x1u << 27) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P28 (0x1u << 28) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P29 (0x1u << 29) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P30 (0x1u << 30) /**< \brief (PIO_AIMMR) IO Line Index */ +#define PIO_AIMMR_P31 (0x1u << 31) /**< \brief (PIO_AIMMR) IO Line Index */ +/* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ +#define PIO_ESR_P0 (0x1u << 0) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P1 (0x1u << 1) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P2 (0x1u << 2) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P3 (0x1u << 3) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P4 (0x1u << 4) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P5 (0x1u << 5) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P6 (0x1u << 6) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P7 (0x1u << 7) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P8 (0x1u << 8) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P9 (0x1u << 9) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P10 (0x1u << 10) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P11 (0x1u << 11) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P12 (0x1u << 12) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P13 (0x1u << 13) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P14 (0x1u << 14) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P15 (0x1u << 15) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P16 (0x1u << 16) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P17 (0x1u << 17) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P18 (0x1u << 18) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P19 (0x1u << 19) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P20 (0x1u << 20) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P21 (0x1u << 21) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P22 (0x1u << 22) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P23 (0x1u << 23) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P24 (0x1u << 24) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P25 (0x1u << 25) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P26 (0x1u << 26) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P27 (0x1u << 27) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P28 (0x1u << 28) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P29 (0x1u << 29) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P30 (0x1u << 30) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +#define PIO_ESR_P31 (0x1u << 31) /**< \brief (PIO_ESR) Edge Interrupt Selection */ +/* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ +#define PIO_LSR_P0 (0x1u << 0) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P1 (0x1u << 1) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P2 (0x1u << 2) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P3 (0x1u << 3) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P4 (0x1u << 4) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P5 (0x1u << 5) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P6 (0x1u << 6) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P7 (0x1u << 7) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P8 (0x1u << 8) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P9 (0x1u << 9) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P10 (0x1u << 10) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P11 (0x1u << 11) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P12 (0x1u << 12) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P13 (0x1u << 13) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P14 (0x1u << 14) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P15 (0x1u << 15) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P16 (0x1u << 16) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P17 (0x1u << 17) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P18 (0x1u << 18) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P19 (0x1u << 19) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P20 (0x1u << 20) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P21 (0x1u << 21) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P22 (0x1u << 22) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P23 (0x1u << 23) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P24 (0x1u << 24) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P25 (0x1u << 25) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P26 (0x1u << 26) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P27 (0x1u << 27) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P28 (0x1u << 28) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P29 (0x1u << 29) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P30 (0x1u << 30) /**< \brief (PIO_LSR) Level Interrupt Selection */ +#define PIO_LSR_P31 (0x1u << 31) /**< \brief (PIO_LSR) Level Interrupt Selection */ +/* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ +#define PIO_ELSR_P0 (0x1u << 0) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P1 (0x1u << 1) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P2 (0x1u << 2) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P3 (0x1u << 3) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P4 (0x1u << 4) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P5 (0x1u << 5) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P6 (0x1u << 6) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P7 (0x1u << 7) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P8 (0x1u << 8) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P9 (0x1u << 9) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P10 (0x1u << 10) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P11 (0x1u << 11) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P12 (0x1u << 12) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P13 (0x1u << 13) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P14 (0x1u << 14) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P15 (0x1u << 15) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P16 (0x1u << 16) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P17 (0x1u << 17) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P18 (0x1u << 18) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P19 (0x1u << 19) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P20 (0x1u << 20) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P21 (0x1u << 21) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P22 (0x1u << 22) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P23 (0x1u << 23) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P24 (0x1u << 24) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P25 (0x1u << 25) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P26 (0x1u << 26) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P27 (0x1u << 27) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P28 (0x1u << 28) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P29 (0x1u << 29) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P30 (0x1u << 30) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +#define PIO_ELSR_P31 (0x1u << 31) /**< \brief (PIO_ELSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low-Level Select Register -------- */ +#define PIO_FELLSR_P0 (0x1u << 0) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P1 (0x1u << 1) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P2 (0x1u << 2) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P3 (0x1u << 3) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P4 (0x1u << 4) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P5 (0x1u << 5) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P6 (0x1u << 6) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P7 (0x1u << 7) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P8 (0x1u << 8) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P9 (0x1u << 9) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P10 (0x1u << 10) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P11 (0x1u << 11) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P12 (0x1u << 12) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P13 (0x1u << 13) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P14 (0x1u << 14) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P15 (0x1u << 15) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P16 (0x1u << 16) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P17 (0x1u << 17) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P18 (0x1u << 18) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P19 (0x1u << 19) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P20 (0x1u << 20) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P21 (0x1u << 21) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P22 (0x1u << 22) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P23 (0x1u << 23) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P24 (0x1u << 24) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P25 (0x1u << 25) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P26 (0x1u << 26) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P27 (0x1u << 27) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P28 (0x1u << 28) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P29 (0x1u << 29) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P30 (0x1u << 30) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +#define PIO_FELLSR_P31 (0x1u << 31) /**< \brief (PIO_FELLSR) Falling Edge/Low-Level Interrupt Selection */ +/* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/High-Level Select Register -------- */ +#define PIO_REHLSR_P0 (0x1u << 0) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P1 (0x1u << 1) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P2 (0x1u << 2) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P3 (0x1u << 3) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P4 (0x1u << 4) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P5 (0x1u << 5) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P6 (0x1u << 6) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P7 (0x1u << 7) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P8 (0x1u << 8) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P9 (0x1u << 9) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P10 (0x1u << 10) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P11 (0x1u << 11) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P12 (0x1u << 12) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P13 (0x1u << 13) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P14 (0x1u << 14) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P15 (0x1u << 15) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P16 (0x1u << 16) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P17 (0x1u << 17) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P18 (0x1u << 18) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P19 (0x1u << 19) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P20 (0x1u << 20) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P21 (0x1u << 21) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P22 (0x1u << 22) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P23 (0x1u << 23) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P24 (0x1u << 24) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P25 (0x1u << 25) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P26 (0x1u << 26) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P27 (0x1u << 27) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P28 (0x1u << 28) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P29 (0x1u << 29) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P30 (0x1u << 30) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +#define PIO_REHLSR_P31 (0x1u << 31) /**< \brief (PIO_REHLSR) Rising Edge/High-Level Interrupt Selection */ +/* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ +#define PIO_FRLHSR_P0 (0x1u << 0) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P1 (0x1u << 1) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P2 (0x1u << 2) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P3 (0x1u << 3) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P4 (0x1u << 4) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P5 (0x1u << 5) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P6 (0x1u << 6) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P7 (0x1u << 7) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P8 (0x1u << 8) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P9 (0x1u << 9) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P10 (0x1u << 10) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P11 (0x1u << 11) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P12 (0x1u << 12) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P13 (0x1u << 13) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P14 (0x1u << 14) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P15 (0x1u << 15) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P16 (0x1u << 16) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P17 (0x1u << 17) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P18 (0x1u << 18) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P19 (0x1u << 19) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P20 (0x1u << 20) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P21 (0x1u << 21) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P22 (0x1u << 22) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P23 (0x1u << 23) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P24 (0x1u << 24) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P25 (0x1u << 25) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P26 (0x1u << 26) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P27 (0x1u << 27) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P28 (0x1u << 28) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P29 (0x1u << 29) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P30 (0x1u << 30) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +#define PIO_FRLHSR_P31 (0x1u << 31) /**< \brief (PIO_FRLHSR) Edge/Level Interrupt Source Selection */ +/* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ +#define PIO_LOCKSR_P0 (0x1u << 0) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P1 (0x1u << 1) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P2 (0x1u << 2) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P3 (0x1u << 3) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P4 (0x1u << 4) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P5 (0x1u << 5) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P6 (0x1u << 6) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P7 (0x1u << 7) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P8 (0x1u << 8) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P9 (0x1u << 9) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P10 (0x1u << 10) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P11 (0x1u << 11) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P12 (0x1u << 12) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P13 (0x1u << 13) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P14 (0x1u << 14) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P15 (0x1u << 15) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P16 (0x1u << 16) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P17 (0x1u << 17) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P18 (0x1u << 18) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P19 (0x1u << 19) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P20 (0x1u << 20) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P21 (0x1u << 21) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P22 (0x1u << 22) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P23 (0x1u << 23) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P24 (0x1u << 24) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P25 (0x1u << 25) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P26 (0x1u << 26) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P27 (0x1u << 27) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P28 (0x1u << 28) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P29 (0x1u << 29) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P30 (0x1u << 30) /**< \brief (PIO_LOCKSR) Lock Status */ +#define PIO_LOCKSR_P31 (0x1u << 31) /**< \brief (PIO_LOCKSR) Lock Status */ +/* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PIO_WPMR_WPEN (0x1u << 0) /**< \brief (PIO_WPMR) Write Protection Enable */ +#define PIO_WPMR_WPKEY_Pos 8 +#define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /**< \brief (PIO_WPMR) Write Protection Key */ +#define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) +#define PIO_WPMR_WPKEY_PASSWD (0x50494Fu << 8) /**< \brief (PIO_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protection Status Register -------- */ +#define PIO_WPSR_WPVS (0x1u << 0) /**< \brief (PIO_WPSR) Write Protection Violation Status */ +#define PIO_WPSR_WPVSRC_Pos 8 +#define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /**< \brief (PIO_WPSR) Write Protection Violation Source */ +/* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ +#define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +#define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /**< \brief (PIO_SCHMITT) Schmitt Trigger Control */ +/* -------- PIO_DRIVER : (PIO Offset: 0x0118) I/O Drive Register -------- */ +#define PIO_DRIVER_LINE0 (0x1u << 0) /**< \brief (PIO_DRIVER) Drive of PIO Line 0 */ +#define PIO_DRIVER_LINE0_LOW_DRIVE (0x0u << 0) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE0_HIGH_DRIVE (0x1u << 0) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE1 (0x1u << 1) /**< \brief (PIO_DRIVER) Drive of PIO Line 1 */ +#define PIO_DRIVER_LINE1_LOW_DRIVE (0x0u << 1) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE1_HIGH_DRIVE (0x1u << 1) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE2 (0x1u << 2) /**< \brief (PIO_DRIVER) Drive of PIO Line 2 */ +#define PIO_DRIVER_LINE2_LOW_DRIVE (0x0u << 2) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE2_HIGH_DRIVE (0x1u << 2) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE3 (0x1u << 3) /**< \brief (PIO_DRIVER) Drive of PIO Line 3 */ +#define PIO_DRIVER_LINE3_LOW_DRIVE (0x0u << 3) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE3_HIGH_DRIVE (0x1u << 3) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE4 (0x1u << 4) /**< \brief (PIO_DRIVER) Drive of PIO Line 4 */ +#define PIO_DRIVER_LINE4_LOW_DRIVE (0x0u << 4) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE4_HIGH_DRIVE (0x1u << 4) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE5 (0x1u << 5) /**< \brief (PIO_DRIVER) Drive of PIO Line 5 */ +#define PIO_DRIVER_LINE5_LOW_DRIVE (0x0u << 5) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE5_HIGH_DRIVE (0x1u << 5) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE6 (0x1u << 6) /**< \brief (PIO_DRIVER) Drive of PIO Line 6 */ +#define PIO_DRIVER_LINE6_LOW_DRIVE (0x0u << 6) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE6_HIGH_DRIVE (0x1u << 6) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE7 (0x1u << 7) /**< \brief (PIO_DRIVER) Drive of PIO Line 7 */ +#define PIO_DRIVER_LINE7_LOW_DRIVE (0x0u << 7) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE7_HIGH_DRIVE (0x1u << 7) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE8 (0x1u << 8) /**< \brief (PIO_DRIVER) Drive of PIO Line 8 */ +#define PIO_DRIVER_LINE8_LOW_DRIVE (0x0u << 8) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE8_HIGH_DRIVE (0x1u << 8) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE9 (0x1u << 9) /**< \brief (PIO_DRIVER) Drive of PIO Line 9 */ +#define PIO_DRIVER_LINE9_LOW_DRIVE (0x0u << 9) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE9_HIGH_DRIVE (0x1u << 9) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE10 (0x1u << 10) /**< \brief (PIO_DRIVER) Drive of PIO Line 10 */ +#define PIO_DRIVER_LINE10_LOW_DRIVE (0x0u << 10) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE10_HIGH_DRIVE (0x1u << 10) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE11 (0x1u << 11) /**< \brief (PIO_DRIVER) Drive of PIO Line 11 */ +#define PIO_DRIVER_LINE11_LOW_DRIVE (0x0u << 11) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE11_HIGH_DRIVE (0x1u << 11) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE12 (0x1u << 12) /**< \brief (PIO_DRIVER) Drive of PIO Line 12 */ +#define PIO_DRIVER_LINE12_LOW_DRIVE (0x0u << 12) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE12_HIGH_DRIVE (0x1u << 12) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE13 (0x1u << 13) /**< \brief (PIO_DRIVER) Drive of PIO Line 13 */ +#define PIO_DRIVER_LINE13_LOW_DRIVE (0x0u << 13) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE13_HIGH_DRIVE (0x1u << 13) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE14 (0x1u << 14) /**< \brief (PIO_DRIVER) Drive of PIO Line 14 */ +#define PIO_DRIVER_LINE14_LOW_DRIVE (0x0u << 14) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE14_HIGH_DRIVE (0x1u << 14) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE15 (0x1u << 15) /**< \brief (PIO_DRIVER) Drive of PIO Line 15 */ +#define PIO_DRIVER_LINE15_LOW_DRIVE (0x0u << 15) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE15_HIGH_DRIVE (0x1u << 15) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE16 (0x1u << 16) /**< \brief (PIO_DRIVER) Drive of PIO Line 16 */ +#define PIO_DRIVER_LINE16_LOW_DRIVE (0x0u << 16) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE16_HIGH_DRIVE (0x1u << 16) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE17 (0x1u << 17) /**< \brief (PIO_DRIVER) Drive of PIO Line 17 */ +#define PIO_DRIVER_LINE17_LOW_DRIVE (0x0u << 17) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE17_HIGH_DRIVE (0x1u << 17) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE18 (0x1u << 18) /**< \brief (PIO_DRIVER) Drive of PIO Line 18 */ +#define PIO_DRIVER_LINE18_LOW_DRIVE (0x0u << 18) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE18_HIGH_DRIVE (0x1u << 18) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE19 (0x1u << 19) /**< \brief (PIO_DRIVER) Drive of PIO Line 19 */ +#define PIO_DRIVER_LINE19_LOW_DRIVE (0x0u << 19) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE19_HIGH_DRIVE (0x1u << 19) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE20 (0x1u << 20) /**< \brief (PIO_DRIVER) Drive of PIO Line 20 */ +#define PIO_DRIVER_LINE20_LOW_DRIVE (0x0u << 20) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE20_HIGH_DRIVE (0x1u << 20) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE21 (0x1u << 21) /**< \brief (PIO_DRIVER) Drive of PIO Line 21 */ +#define PIO_DRIVER_LINE21_LOW_DRIVE (0x0u << 21) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE21_HIGH_DRIVE (0x1u << 21) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE22 (0x1u << 22) /**< \brief (PIO_DRIVER) Drive of PIO Line 22 */ +#define PIO_DRIVER_LINE22_LOW_DRIVE (0x0u << 22) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE22_HIGH_DRIVE (0x1u << 22) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE23 (0x1u << 23) /**< \brief (PIO_DRIVER) Drive of PIO Line 23 */ +#define PIO_DRIVER_LINE23_LOW_DRIVE (0x0u << 23) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE23_HIGH_DRIVE (0x1u << 23) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE24 (0x1u << 24) /**< \brief (PIO_DRIVER) Drive of PIO Line 24 */ +#define PIO_DRIVER_LINE24_LOW_DRIVE (0x0u << 24) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE24_HIGH_DRIVE (0x1u << 24) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE25 (0x1u << 25) /**< \brief (PIO_DRIVER) Drive of PIO Line 25 */ +#define PIO_DRIVER_LINE25_LOW_DRIVE (0x0u << 25) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE25_HIGH_DRIVE (0x1u << 25) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE26 (0x1u << 26) /**< \brief (PIO_DRIVER) Drive of PIO Line 26 */ +#define PIO_DRIVER_LINE26_LOW_DRIVE (0x0u << 26) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE26_HIGH_DRIVE (0x1u << 26) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE27 (0x1u << 27) /**< \brief (PIO_DRIVER) Drive of PIO Line 27 */ +#define PIO_DRIVER_LINE27_LOW_DRIVE (0x0u << 27) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE27_HIGH_DRIVE (0x1u << 27) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE28 (0x1u << 28) /**< \brief (PIO_DRIVER) Drive of PIO Line 28 */ +#define PIO_DRIVER_LINE28_LOW_DRIVE (0x0u << 28) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE28_HIGH_DRIVE (0x1u << 28) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE29 (0x1u << 29) /**< \brief (PIO_DRIVER) Drive of PIO Line 29 */ +#define PIO_DRIVER_LINE29_LOW_DRIVE (0x0u << 29) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE29_HIGH_DRIVE (0x1u << 29) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE30 (0x1u << 30) /**< \brief (PIO_DRIVER) Drive of PIO Line 30 */ +#define PIO_DRIVER_LINE30_LOW_DRIVE (0x0u << 30) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE30_HIGH_DRIVE (0x1u << 30) /**< \brief (PIO_DRIVER) Highest drive */ +#define PIO_DRIVER_LINE31 (0x1u << 31) /**< \brief (PIO_DRIVER) Drive of PIO Line 31 */ +#define PIO_DRIVER_LINE31_LOW_DRIVE (0x0u << 31) /**< \brief (PIO_DRIVER) Lowest drive */ +#define PIO_DRIVER_LINE31_HIGH_DRIVE (0x1u << 31) /**< \brief (PIO_DRIVER) Highest drive */ +/* -------- PIO_KER : (PIO Offset: 0x0120) Keypad Controller Enable Register -------- */ +#define PIO_KER_KCE (0x1u << 0) /**< \brief (PIO_KER) Keypad Controller Enable */ +/* -------- PIO_KRCR : (PIO Offset: 0x0124) Keypad Controller Row Column Register -------- */ +#define PIO_KRCR_NBR_Pos 0 +#define PIO_KRCR_NBR_Msk (0x7u << PIO_KRCR_NBR_Pos) /**< \brief (PIO_KRCR) Number of Columns of the Keypad Matrix */ +#define PIO_KRCR_NBR(value) ((PIO_KRCR_NBR_Msk & ((value) << PIO_KRCR_NBR_Pos))) +#define PIO_KRCR_NBC_Pos 8 +#define PIO_KRCR_NBC_Msk (0x7u << PIO_KRCR_NBC_Pos) /**< \brief (PIO_KRCR) Number of Rows of the Keypad Matrix */ +#define PIO_KRCR_NBC(value) ((PIO_KRCR_NBC_Msk & ((value) << PIO_KRCR_NBC_Pos))) +/* -------- PIO_KDR : (PIO Offset: 0x0128) Keypad Controller Debouncing Register -------- */ +#define PIO_KDR_DBC_Pos 0 +#define PIO_KDR_DBC_Msk (0x3ffu << PIO_KDR_DBC_Pos) /**< \brief (PIO_KDR) Debouncing Value */ +#define PIO_KDR_DBC(value) ((PIO_KDR_DBC_Msk & ((value) << PIO_KDR_DBC_Pos))) +/* -------- PIO_KIER : (PIO Offset: 0x0130) Keypad Controller Interrupt Enable Register -------- */ +#define PIO_KIER_KPR (0x1u << 0) /**< \brief (PIO_KIER) Key Press Interrupt Enable */ +#define PIO_KIER_KRL (0x1u << 1) /**< \brief (PIO_KIER) Key Release Interrupt Enable */ +/* -------- PIO_KIDR : (PIO Offset: 0x0134) Keypad Controller Interrupt Disable Register -------- */ +#define PIO_KIDR_KPR (0x1u << 0) /**< \brief (PIO_KIDR) Key Press Interrupt Disable */ +#define PIO_KIDR_KRL (0x1u << 1) /**< \brief (PIO_KIDR) Key Release Interrupt Disable */ +/* -------- PIO_KIMR : (PIO Offset: 0x0138) Keypad Controller Interrupt Mask Register -------- */ +#define PIO_KIMR_KPR (0x1u << 0) /**< \brief (PIO_KIMR) Key Press Interrupt Mask */ +#define PIO_KIMR_KRL (0x1u << 1) /**< \brief (PIO_KIMR) Key Release Interrupt Mask */ +/* -------- PIO_KSR : (PIO Offset: 0x013C) Keypad Controller Status Register -------- */ +#define PIO_KSR_KPR (0x1u << 0) /**< \brief (PIO_KSR) Key Press Status */ +#define PIO_KSR_KRL (0x1u << 1) /**< \brief (PIO_KSR) Key Release Status */ +#define PIO_KSR_NBKPR_Pos 8 +#define PIO_KSR_NBKPR_Msk (0x3u << PIO_KSR_NBKPR_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Presses */ +#define PIO_KSR_NBKRL_Pos 16 +#define PIO_KSR_NBKRL_Msk (0x3u << PIO_KSR_NBKRL_Pos) /**< \brief (PIO_KSR) Number of Simultaneous Key Releases */ +/* -------- PIO_KKPR : (PIO Offset: 0x0140) Keypad Controller Key Press Register -------- */ +#define PIO_KKPR_KEY0ROW_Pos 0 +#define PIO_KKPR_KEY0ROW_Msk (0x7u << PIO_KKPR_KEY0ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the First Detected Key Press */ +#define PIO_KKPR_KEY0COL_Pos 4 +#define PIO_KKPR_KEY0COL_Msk (0x7u << PIO_KKPR_KEY0COL_Pos) /**< \brief (PIO_KKPR) Column Index of the First Detected Key Press */ +#define PIO_KKPR_KEY1ROW_Pos 8 +#define PIO_KKPR_KEY1ROW_Msk (0x7u << PIO_KKPR_KEY1ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Second Detected Key Press */ +#define PIO_KKPR_KEY1COL_Pos 12 +#define PIO_KKPR_KEY1COL_Msk (0x7u << PIO_KKPR_KEY1COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Second Detected Key Press */ +#define PIO_KKPR_KEY2ROW_Pos 16 +#define PIO_KKPR_KEY2ROW_Msk (0x7u << PIO_KKPR_KEY2ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Third Detected Key Press */ +#define PIO_KKPR_KEY2COL_Pos 20 +#define PIO_KKPR_KEY2COL_Msk (0x7u << PIO_KKPR_KEY2COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Third Detected Key Press */ +#define PIO_KKPR_KEY3ROW_Pos 24 +#define PIO_KKPR_KEY3ROW_Msk (0x7u << PIO_KKPR_KEY3ROW_Pos) /**< \brief (PIO_KKPR) Row Index of the Fourth Detected Key Press */ +#define PIO_KKPR_KEY3COL_Pos 28 +#define PIO_KKPR_KEY3COL_Msk (0x7u << PIO_KKPR_KEY3COL_Pos) /**< \brief (PIO_KKPR) Column Index of the Fourth Detected Key Press */ +/* -------- PIO_KKRR : (PIO Offset: 0x0144) Keypad Controller Key Release Register -------- */ +#define PIO_KKRR_KEY0ROW_Pos 0 +#define PIO_KKRR_KEY0ROW_Msk (0x7u << PIO_KKRR_KEY0ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the First Detected Key Release */ +#define PIO_KKRR_KEY0COL_Pos 4 +#define PIO_KKRR_KEY0COL_Msk (0x7u << PIO_KKRR_KEY0COL_Pos) /**< \brief (PIO_KKRR) Column Index of the First Detected Key Release */ +#define PIO_KKRR_KEY1ROW_Pos 8 +#define PIO_KKRR_KEY1ROW_Msk (0x7u << PIO_KKRR_KEY1ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Second Detected Key Release */ +#define PIO_KKRR_KEY1COL_Pos 12 +#define PIO_KKRR_KEY1COL_Msk (0x7u << PIO_KKRR_KEY1COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Second Detected Key Release */ +#define PIO_KKRR_KEY2ROW_Pos 16 +#define PIO_KKRR_KEY2ROW_Msk (0x7u << PIO_KKRR_KEY2ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Third Detected Key Release */ +#define PIO_KKRR_KEY2COL_Pos 20 +#define PIO_KKRR_KEY2COL_Msk (0x7u << PIO_KKRR_KEY2COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Third Detected Key Release */ +#define PIO_KKRR_KEY3ROW_Pos 24 +#define PIO_KKRR_KEY3ROW_Msk (0x7u << PIO_KKRR_KEY3ROW_Pos) /**< \brief (PIO_KKRR) Row Index of the Fourth Detected Key Release */ +#define PIO_KKRR_KEY3COL_Pos 28 +#define PIO_KKRR_KEY3COL_Msk (0x7u << PIO_KKRR_KEY3COL_Pos) /**< \brief (PIO_KKRR) Column Index of the Fourth Detected Key Release */ +/* -------- PIO_PCMR : (PIO Offset: 0x0150) Parallel Capture Mode Register -------- */ +#define PIO_PCMR_PCEN (0x1u << 0) /**< \brief (PIO_PCMR) Parallel Capture Mode Enable */ +#define PIO_PCMR_DSIZE_Pos 4 +#define PIO_PCMR_DSIZE_Msk (0x3u << PIO_PCMR_DSIZE_Pos) /**< \brief (PIO_PCMR) Parallel Capture Mode Data Size */ +#define PIO_PCMR_DSIZE(value) ((PIO_PCMR_DSIZE_Msk & ((value) << PIO_PCMR_DSIZE_Pos))) +#define PIO_PCMR_DSIZE_BYTE (0x0u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a byte (8-bit) */ +#define PIO_PCMR_DSIZE_HALFWORD (0x1u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a half-word (16-bit) */ +#define PIO_PCMR_DSIZE_WORD (0x2u << 4) /**< \brief (PIO_PCMR) The reception data in the PIO_PCRHR is a word (32-bit) */ +#define PIO_PCMR_ALWYS (0x1u << 9) /**< \brief (PIO_PCMR) Parallel Capture Mode Always Sampling */ +#define PIO_PCMR_HALFS (0x1u << 10) /**< \brief (PIO_PCMR) Parallel Capture Mode Half Sampling */ +#define PIO_PCMR_FRSTS (0x1u << 11) /**< \brief (PIO_PCMR) Parallel Capture Mode First Sample */ +/* -------- PIO_PCIER : (PIO Offset: 0x0154) Parallel Capture Interrupt Enable Register -------- */ +#define PIO_PCIER_DRDY (0x1u << 0) /**< \brief (PIO_PCIER) Parallel Capture Mode Data Ready Interrupt Enable */ +#define PIO_PCIER_OVRE (0x1u << 1) /**< \brief (PIO_PCIER) Parallel Capture Mode Overrun Error Interrupt Enable */ +#define PIO_PCIER_ENDRX (0x1u << 2) /**< \brief (PIO_PCIER) End of Reception Transfer Interrupt Enable */ +#define PIO_PCIER_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIER) Reception Buffer Full Interrupt Enable */ +/* -------- PIO_PCIDR : (PIO Offset: 0x0158) Parallel Capture Interrupt Disable Register -------- */ +#define PIO_PCIDR_DRDY (0x1u << 0) /**< \brief (PIO_PCIDR) Parallel Capture Mode Data Ready Interrupt Disable */ +#define PIO_PCIDR_OVRE (0x1u << 1) /**< \brief (PIO_PCIDR) Parallel Capture Mode Overrun Error Interrupt Disable */ +#define PIO_PCIDR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIDR) End of Reception Transfer Interrupt Disable */ +#define PIO_PCIDR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIDR) Reception Buffer Full Interrupt Disable */ +/* -------- PIO_PCIMR : (PIO Offset: 0x015C) Parallel Capture Interrupt Mask Register -------- */ +#define PIO_PCIMR_DRDY (0x1u << 0) /**< \brief (PIO_PCIMR) Parallel Capture Mode Data Ready Interrupt Mask */ +#define PIO_PCIMR_OVRE (0x1u << 1) /**< \brief (PIO_PCIMR) Parallel Capture Mode Overrun Error Interrupt Mask */ +#define PIO_PCIMR_ENDRX (0x1u << 2) /**< \brief (PIO_PCIMR) End of Reception Transfer Interrupt Mask */ +#define PIO_PCIMR_RXBUFF (0x1u << 3) /**< \brief (PIO_PCIMR) Reception Buffer Full Interrupt Mask */ +/* -------- PIO_PCISR : (PIO Offset: 0x0160) Parallel Capture Interrupt Status Register -------- */ +#define PIO_PCISR_DRDY (0x1u << 0) /**< \brief (PIO_PCISR) Parallel Capture Mode Data Ready */ +#define PIO_PCISR_OVRE (0x1u << 1) /**< \brief (PIO_PCISR) Parallel Capture Mode Overrun Error */ +/* -------- PIO_PCRHR : (PIO Offset: 0x0164) Parallel Capture Reception Holding Register -------- */ +#define PIO_PCRHR_RDATA_Pos 0 +#define PIO_PCRHR_RDATA_Msk (0xffffffffu << PIO_PCRHR_RDATA_Pos) /**< \brief (PIO_PCRHR) Parallel Capture Mode Reception Data */ + +/*@}*/ + + +#endif /* _SAMV71_PIO_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pmc.h new file mode 100644 index 000000000..11ed6780a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pmc.h @@ -0,0 +1,721 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PMC_COMPONENT_ +#define _SAMV71_PMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Power Management Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PMC Power Management Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Pmc hardware registers */ +typedef struct { + __O uint32_t PMC_SCER; /**< \brief (Pmc Offset: 0x0000) System Clock Enable Register */ + __O uint32_t PMC_SCDR; /**< \brief (Pmc Offset: 0x0004) System Clock Disable Register */ + __I uint32_t PMC_SCSR; /**< \brief (Pmc Offset: 0x0008) System Clock Status Register */ + __I uint32_t Reserved1[1]; + __O uint32_t PMC_PCER0; /**< \brief (Pmc Offset: 0x0010) Peripheral Clock Enable Register 0 */ + __O uint32_t PMC_PCDR0; /**< \brief (Pmc Offset: 0x0014) Peripheral Clock Disable Register 0 */ + __I uint32_t PMC_PCSR0; /**< \brief (Pmc Offset: 0x0018) Peripheral Clock Status Register 0 */ + __IO uint32_t CKGR_UCKR; /**< \brief (Pmc Offset: 0x001C) UTMI Clock Register */ + __IO uint32_t CKGR_MOR; /**< \brief (Pmc Offset: 0x0020) Main Oscillator Register */ + __IO uint32_t CKGR_MCFR; /**< \brief (Pmc Offset: 0x0024) Main Clock Frequency Register */ + __IO uint32_t CKGR_PLLAR; /**< \brief (Pmc Offset: 0x0028) PLLA Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PMC_MCKR; /**< \brief (Pmc Offset: 0x0030) Master Clock Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t PMC_USB; /**< \brief (Pmc Offset: 0x0038) USB Clock Register */ + __I uint32_t Reserved4[1]; + __IO uint32_t PMC_PCK[7]; /**< \brief (Pmc Offset: 0x0040) Programmable Clock 0 Register */ + __I uint32_t Reserved5[1]; + __O uint32_t PMC_IER; /**< \brief (Pmc Offset: 0x0060) Interrupt Enable Register */ + __O uint32_t PMC_IDR; /**< \brief (Pmc Offset: 0x0064) Interrupt Disable Register */ + __I uint32_t PMC_SR; /**< \brief (Pmc Offset: 0x0068) Status Register */ + __I uint32_t PMC_IMR; /**< \brief (Pmc Offset: 0x006C) Interrupt Mask Register */ + __IO uint32_t PMC_FSMR; /**< \brief (Pmc Offset: 0x0070) Fast Startup Mode Register */ + __IO uint32_t PMC_FSPR; /**< \brief (Pmc Offset: 0x0074) Fast Startup Polarity Register */ + __O uint32_t PMC_FOCR; /**< \brief (Pmc Offset: 0x0078) Fault Output Clear Register */ + __I uint32_t Reserved6[26]; + __IO uint32_t PMC_WPMR; /**< \brief (Pmc Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t PMC_WPSR; /**< \brief (Pmc Offset: 0x00E8) Write Protection Status Register */ + __I uint32_t Reserved7[5]; + __O uint32_t PMC_PCER1; /**< \brief (Pmc Offset: 0x0100) Peripheral Clock Enable Register 1 */ + __O uint32_t PMC_PCDR1; /**< \brief (Pmc Offset: 0x0104) Peripheral Clock Disable Register 1 */ + __I uint32_t PMC_PCSR1; /**< \brief (Pmc Offset: 0x0108) Peripheral Clock Status Register 1 */ + __IO uint32_t PMC_PCR; /**< \brief (Pmc Offset: 0x010C) Peripheral Control Register */ + __IO uint32_t PMC_OCR; /**< \brief (Pmc Offset: 0x0110) Oscillator Calibration Register */ + __O uint32_t PMC_SLPWK_ER0; /**< \brief (Pmc Offset: 0x0114) SleepWalking Enable Register 0 */ + __O uint32_t PMC_SLPWK_DR0; /**< \brief (Pmc Offset: 0x0118) SleepWalking Disable Register 0 */ + __I uint32_t PMC_SLPWK_SR0; /**< \brief (Pmc Offset: 0x011C) SleepWalking Status Register 0 */ + __I uint32_t PMC_SLPWK_ASR0; /**< \brief (Pmc Offset: 0x0120) SleepWalking Activity Status Register 0 */ + __I uint32_t Reserved8[4]; + __O uint32_t PMC_SLPWK_ER1; /**< \brief (Pmc Offset: 0x0134) SleepWalking Enable Register 1 */ + __O uint32_t PMC_SLPWK_DR1; /**< \brief (Pmc Offset: 0x0138) SleepWalking Disable Register 1 */ + __I uint32_t PMC_SLPWK_SR1; /**< \brief (Pmc Offset: 0x013C) SleepWalking Status Register 1 */ + __I uint32_t PMC_SLPWK_ASR1; /**< \brief (Pmc Offset: 0x0140) SleepWalking Activity Status Register 1 */ + __I uint32_t PMC_SLPWK_AIPR; /**< \brief (Pmc Offset: 0x0144) SleepWalking Activity In Progress Register */ +} Pmc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */ +#define PMC_SCER_USBCLK (0x1u << 5) /**< \brief (PMC_SCER) Enable USB FS Clock */ +#define PMC_SCER_PCK0 (0x1u << 8) /**< \brief (PMC_SCER) Programmable Clock 0 Output Enable */ +#define PMC_SCER_PCK1 (0x1u << 9) /**< \brief (PMC_SCER) Programmable Clock 1 Output Enable */ +#define PMC_SCER_PCK2 (0x1u << 10) /**< \brief (PMC_SCER) Programmable Clock 2 Output Enable */ +#define PMC_SCER_PCK3 (0x1u << 11) /**< \brief (PMC_SCER) Programmable Clock 3 Output Enable */ +#define PMC_SCER_PCK4 (0x1u << 12) /**< \brief (PMC_SCER) Programmable Clock 4 Output Enable */ +#define PMC_SCER_PCK5 (0x1u << 13) /**< \brief (PMC_SCER) Programmable Clock 5 Output Enable */ +#define PMC_SCER_PCK6 (0x1u << 14) /**< \brief (PMC_SCER) Programmable Clock 6 Output Enable */ +/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */ +#define PMC_SCDR_USBCLK (0x1u << 5) /**< \brief (PMC_SCDR) Disable USB FS Clock */ +#define PMC_SCDR_PCK0 (0x1u << 8) /**< \brief (PMC_SCDR) Programmable Clock 0 Output Disable */ +#define PMC_SCDR_PCK1 (0x1u << 9) /**< \brief (PMC_SCDR) Programmable Clock 1 Output Disable */ +#define PMC_SCDR_PCK2 (0x1u << 10) /**< \brief (PMC_SCDR) Programmable Clock 2 Output Disable */ +#define PMC_SCDR_PCK3 (0x1u << 11) /**< \brief (PMC_SCDR) Programmable Clock 3 Output Disable */ +#define PMC_SCDR_PCK4 (0x1u << 12) /**< \brief (PMC_SCDR) Programmable Clock 4 Output Disable */ +#define PMC_SCDR_PCK5 (0x1u << 13) /**< \brief (PMC_SCDR) Programmable Clock 5 Output Disable */ +#define PMC_SCDR_PCK6 (0x1u << 14) /**< \brief (PMC_SCDR) Programmable Clock 6 Output Disable */ +/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */ +#define PMC_SCSR_USBCLK (0x1u << 5) /**< \brief (PMC_SCSR) USB FS Clock Status */ +#define PMC_SCSR_PCK0 (0x1u << 8) /**< \brief (PMC_SCSR) Programmable Clock 0 Output Status */ +#define PMC_SCSR_PCK1 (0x1u << 9) /**< \brief (PMC_SCSR) Programmable Clock 1 Output Status */ +#define PMC_SCSR_PCK2 (0x1u << 10) /**< \brief (PMC_SCSR) Programmable Clock 2 Output Status */ +#define PMC_SCSR_PCK3 (0x1u << 11) /**< \brief (PMC_SCSR) Programmable Clock 3 Output Status */ +#define PMC_SCSR_PCK4 (0x1u << 12) /**< \brief (PMC_SCSR) Programmable Clock 4 Output Status */ +#define PMC_SCSR_PCK5 (0x1u << 13) /**< \brief (PMC_SCSR) Programmable Clock 5 Output Status */ +#define PMC_SCSR_PCK6 (0x1u << 14) /**< \brief (PMC_SCSR) Programmable Clock 6 Output Status */ +/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */ +#define PMC_PCER0_PID7 (0x1u << 7) /**< \brief (PMC_PCER0) Peripheral Clock 7 Enable */ +#define PMC_PCER0_PID8 (0x1u << 8) /**< \brief (PMC_PCER0) Peripheral Clock 8 Enable */ +#define PMC_PCER0_PID9 (0x1u << 9) /**< \brief (PMC_PCER0) Peripheral Clock 9 Enable */ +#define PMC_PCER0_PID10 (0x1u << 10) /**< \brief (PMC_PCER0) Peripheral Clock 10 Enable */ +#define PMC_PCER0_PID11 (0x1u << 11) /**< \brief (PMC_PCER0) Peripheral Clock 11 Enable */ +#define PMC_PCER0_PID12 (0x1u << 12) /**< \brief (PMC_PCER0) Peripheral Clock 12 Enable */ +#define PMC_PCER0_PID13 (0x1u << 13) /**< \brief (PMC_PCER0) Peripheral Clock 13 Enable */ +#define PMC_PCER0_PID14 (0x1u << 14) /**< \brief (PMC_PCER0) Peripheral Clock 14 Enable */ +#define PMC_PCER0_PID15 (0x1u << 15) /**< \brief (PMC_PCER0) Peripheral Clock 15 Enable */ +#define PMC_PCER0_PID16 (0x1u << 16) /**< \brief (PMC_PCER0) Peripheral Clock 16 Enable */ +#define PMC_PCER0_PID17 (0x1u << 17) /**< \brief (PMC_PCER0) Peripheral Clock 17 Enable */ +#define PMC_PCER0_PID18 (0x1u << 18) /**< \brief (PMC_PCER0) Peripheral Clock 18 Enable */ +#define PMC_PCER0_PID19 (0x1u << 19) /**< \brief (PMC_PCER0) Peripheral Clock 19 Enable */ +#define PMC_PCER0_PID20 (0x1u << 20) /**< \brief (PMC_PCER0) Peripheral Clock 20 Enable */ +#define PMC_PCER0_PID21 (0x1u << 21) /**< \brief (PMC_PCER0) Peripheral Clock 21 Enable */ +#define PMC_PCER0_PID22 (0x1u << 22) /**< \brief (PMC_PCER0) Peripheral Clock 22 Enable */ +#define PMC_PCER0_PID23 (0x1u << 23) /**< \brief (PMC_PCER0) Peripheral Clock 23 Enable */ +#define PMC_PCER0_PID24 (0x1u << 24) /**< \brief (PMC_PCER0) Peripheral Clock 24 Enable */ +#define PMC_PCER0_PID25 (0x1u << 25) /**< \brief (PMC_PCER0) Peripheral Clock 25 Enable */ +#define PMC_PCER0_PID26 (0x1u << 26) /**< \brief (PMC_PCER0) Peripheral Clock 26 Enable */ +#define PMC_PCER0_PID27 (0x1u << 27) /**< \brief (PMC_PCER0) Peripheral Clock 27 Enable */ +#define PMC_PCER0_PID28 (0x1u << 28) /**< \brief (PMC_PCER0) Peripheral Clock 28 Enable */ +#define PMC_PCER0_PID29 (0x1u << 29) /**< \brief (PMC_PCER0) Peripheral Clock 29 Enable */ +#define PMC_PCER0_PID30 (0x1u << 30) /**< \brief (PMC_PCER0) Peripheral Clock 30 Enable */ +#define PMC_PCER0_PID31 (0x1u << 31) /**< \brief (PMC_PCER0) Peripheral Clock 31 Enable */ +/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */ +#define PMC_PCDR0_PID7 (0x1u << 7) /**< \brief (PMC_PCDR0) Peripheral Clock 7 Disable */ +#define PMC_PCDR0_PID8 (0x1u << 8) /**< \brief (PMC_PCDR0) Peripheral Clock 8 Disable */ +#define PMC_PCDR0_PID9 (0x1u << 9) /**< \brief (PMC_PCDR0) Peripheral Clock 9 Disable */ +#define PMC_PCDR0_PID10 (0x1u << 10) /**< \brief (PMC_PCDR0) Peripheral Clock 10 Disable */ +#define PMC_PCDR0_PID11 (0x1u << 11) /**< \brief (PMC_PCDR0) Peripheral Clock 11 Disable */ +#define PMC_PCDR0_PID12 (0x1u << 12) /**< \brief (PMC_PCDR0) Peripheral Clock 12 Disable */ +#define PMC_PCDR0_PID13 (0x1u << 13) /**< \brief (PMC_PCDR0) Peripheral Clock 13 Disable */ +#define PMC_PCDR0_PID14 (0x1u << 14) /**< \brief (PMC_PCDR0) Peripheral Clock 14 Disable */ +#define PMC_PCDR0_PID15 (0x1u << 15) /**< \brief (PMC_PCDR0) Peripheral Clock 15 Disable */ +#define PMC_PCDR0_PID16 (0x1u << 16) /**< \brief (PMC_PCDR0) Peripheral Clock 16 Disable */ +#define PMC_PCDR0_PID17 (0x1u << 17) /**< \brief (PMC_PCDR0) Peripheral Clock 17 Disable */ +#define PMC_PCDR0_PID18 (0x1u << 18) /**< \brief (PMC_PCDR0) Peripheral Clock 18 Disable */ +#define PMC_PCDR0_PID19 (0x1u << 19) /**< \brief (PMC_PCDR0) Peripheral Clock 19 Disable */ +#define PMC_PCDR0_PID20 (0x1u << 20) /**< \brief (PMC_PCDR0) Peripheral Clock 20 Disable */ +#define PMC_PCDR0_PID21 (0x1u << 21) /**< \brief (PMC_PCDR0) Peripheral Clock 21 Disable */ +#define PMC_PCDR0_PID22 (0x1u << 22) /**< \brief (PMC_PCDR0) Peripheral Clock 22 Disable */ +#define PMC_PCDR0_PID23 (0x1u << 23) /**< \brief (PMC_PCDR0) Peripheral Clock 23 Disable */ +#define PMC_PCDR0_PID24 (0x1u << 24) /**< \brief (PMC_PCDR0) Peripheral Clock 24 Disable */ +#define PMC_PCDR0_PID25 (0x1u << 25) /**< \brief (PMC_PCDR0) Peripheral Clock 25 Disable */ +#define PMC_PCDR0_PID26 (0x1u << 26) /**< \brief (PMC_PCDR0) Peripheral Clock 26 Disable */ +#define PMC_PCDR0_PID27 (0x1u << 27) /**< \brief (PMC_PCDR0) Peripheral Clock 27 Disable */ +#define PMC_PCDR0_PID28 (0x1u << 28) /**< \brief (PMC_PCDR0) Peripheral Clock 28 Disable */ +#define PMC_PCDR0_PID29 (0x1u << 29) /**< \brief (PMC_PCDR0) Peripheral Clock 29 Disable */ +#define PMC_PCDR0_PID30 (0x1u << 30) /**< \brief (PMC_PCDR0) Peripheral Clock 30 Disable */ +#define PMC_PCDR0_PID31 (0x1u << 31) /**< \brief (PMC_PCDR0) Peripheral Clock 31 Disable */ +/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */ +#define PMC_PCSR0_PID7 (0x1u << 7) /**< \brief (PMC_PCSR0) Peripheral Clock 7 Status */ +#define PMC_PCSR0_PID8 (0x1u << 8) /**< \brief (PMC_PCSR0) Peripheral Clock 8 Status */ +#define PMC_PCSR0_PID9 (0x1u << 9) /**< \brief (PMC_PCSR0) Peripheral Clock 9 Status */ +#define PMC_PCSR0_PID10 (0x1u << 10) /**< \brief (PMC_PCSR0) Peripheral Clock 10 Status */ +#define PMC_PCSR0_PID11 (0x1u << 11) /**< \brief (PMC_PCSR0) Peripheral Clock 11 Status */ +#define PMC_PCSR0_PID12 (0x1u << 12) /**< \brief (PMC_PCSR0) Peripheral Clock 12 Status */ +#define PMC_PCSR0_PID13 (0x1u << 13) /**< \brief (PMC_PCSR0) Peripheral Clock 13 Status */ +#define PMC_PCSR0_PID14 (0x1u << 14) /**< \brief (PMC_PCSR0) Peripheral Clock 14 Status */ +#define PMC_PCSR0_PID15 (0x1u << 15) /**< \brief (PMC_PCSR0) Peripheral Clock 15 Status */ +#define PMC_PCSR0_PID16 (0x1u << 16) /**< \brief (PMC_PCSR0) Peripheral Clock 16 Status */ +#define PMC_PCSR0_PID17 (0x1u << 17) /**< \brief (PMC_PCSR0) Peripheral Clock 17 Status */ +#define PMC_PCSR0_PID18 (0x1u << 18) /**< \brief (PMC_PCSR0) Peripheral Clock 18 Status */ +#define PMC_PCSR0_PID19 (0x1u << 19) /**< \brief (PMC_PCSR0) Peripheral Clock 19 Status */ +#define PMC_PCSR0_PID20 (0x1u << 20) /**< \brief (PMC_PCSR0) Peripheral Clock 20 Status */ +#define PMC_PCSR0_PID21 (0x1u << 21) /**< \brief (PMC_PCSR0) Peripheral Clock 21 Status */ +#define PMC_PCSR0_PID22 (0x1u << 22) /**< \brief (PMC_PCSR0) Peripheral Clock 22 Status */ +#define PMC_PCSR0_PID23 (0x1u << 23) /**< \brief (PMC_PCSR0) Peripheral Clock 23 Status */ +#define PMC_PCSR0_PID24 (0x1u << 24) /**< \brief (PMC_PCSR0) Peripheral Clock 24 Status */ +#define PMC_PCSR0_PID25 (0x1u << 25) /**< \brief (PMC_PCSR0) Peripheral Clock 25 Status */ +#define PMC_PCSR0_PID26 (0x1u << 26) /**< \brief (PMC_PCSR0) Peripheral Clock 26 Status */ +#define PMC_PCSR0_PID27 (0x1u << 27) /**< \brief (PMC_PCSR0) Peripheral Clock 27 Status */ +#define PMC_PCSR0_PID28 (0x1u << 28) /**< \brief (PMC_PCSR0) Peripheral Clock 28 Status */ +#define PMC_PCSR0_PID29 (0x1u << 29) /**< \brief (PMC_PCSR0) Peripheral Clock 29 Status */ +#define PMC_PCSR0_PID30 (0x1u << 30) /**< \brief (PMC_PCSR0) Peripheral Clock 30 Status */ +#define PMC_PCSR0_PID31 (0x1u << 31) /**< \brief (PMC_PCSR0) Peripheral Clock 31 Status */ +/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */ +#define CKGR_UCKR_UPLLEN (0x1u << 16) /**< \brief (CKGR_UCKR) UTMI PLL Enable */ +#define CKGR_UCKR_UPLLCOUNT_Pos 20 +#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) /**< \brief (CKGR_UCKR) UTMI PLL Start-up Time */ +#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) +/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */ +#define CKGR_MOR_MOSCXTEN (0x1u << 0) /**< \brief (CKGR_MOR) Main Crystal Oscillator Enable */ +#define CKGR_MOR_MOSCXTBY (0x1u << 1) /**< \brief (CKGR_MOR) Main Crystal Oscillator Bypass */ +#define CKGR_MOR_WAITMODE (0x1u << 2) /**< \brief (CKGR_MOR) Wait Mode Command (Write-only) */ +#define CKGR_MOR_MOSCRCEN (0x1u << 3) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Enable */ +#define CKGR_MOR_MOSCRCF_Pos 4 +#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) /**< \brief (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection */ +#define CKGR_MOR_MOSCRCF(value) ((CKGR_MOR_MOSCRCF_Msk & ((value) << CKGR_MOR_MOSCRCF_Pos))) +#define CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 4 MHz (default) */ +#define CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 8 MHz */ +#define CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) /**< \brief (CKGR_MOR) Fast RC oscillator frequency is at 12 MHz */ +#define CKGR_MOR_MOSCXTST_Pos 8 +#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) /**< \brief (CKGR_MOR) Main Crystal Oscillator Start-up Time */ +#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) +#define CKGR_MOR_KEY_Pos 16 +#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) /**< \brief (CKGR_MOR) Write Access Password */ +#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) +#define CKGR_MOR_KEY_PASSWD (0x37u << 16) /**< \brief (CKGR_MOR) Writing any other value in this field aborts the write operation.Always reads as 0. */ +#define CKGR_MOR_MOSCSEL (0x1u << 24) /**< \brief (CKGR_MOR) Main Oscillator Selection */ +#define CKGR_MOR_CFDEN (0x1u << 25) /**< \brief (CKGR_MOR) Clock Failure Detector Enable */ +#define CKGR_MOR_XT32KFME (0x1u << 26) /**< \brief (CKGR_MOR) Slow Crystal Oscillator Frequency Monitoring Enable */ +/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */ +#define CKGR_MCFR_MAINF_Pos 0 +#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) /**< \brief (CKGR_MCFR) Main Clock Frequency */ +#define CKGR_MCFR_MAINF(value) ((CKGR_MCFR_MAINF_Msk & ((value) << CKGR_MCFR_MAINF_Pos))) +#define CKGR_MCFR_MAINFRDY (0x1u << 16) /**< \brief (CKGR_MCFR) Main Clock Frequency Measure Ready */ +#define CKGR_MCFR_RCMEAS (0x1u << 20) /**< \brief (CKGR_MCFR) RC Oscillator Frequency Measure (write-only) */ +#define CKGR_MCFR_CCSS (0x1u << 24) /**< \brief (CKGR_MCFR) Counter Clock Source Selection */ +/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */ +#define CKGR_PLLAR_DIVA_Pos 0 +#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) /**< \brief (CKGR_PLLAR) PLLA Front End Divider */ +#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) +#define CKGR_PLLAR_DIVA_0 (0x0u << 0) /**< \brief (CKGR_PLLAR) Divider output is 0 and PLLA is disabled. */ +#define CKGR_PLLAR_DIVA_BYPASS (0x1u << 0) /**< \brief (CKGR_PLLAR) Divider is bypassed (divide by 1) and PLLA is enabled. */ +#define CKGR_PLLAR_PLLACOUNT_Pos 8 +#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) /**< \brief (CKGR_PLLAR) PLLA Counter */ +#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) +#define CKGR_PLLAR_MULA_Pos 16 +#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) /**< \brief (CKGR_PLLAR) PLLA Multiplier */ +#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) +#define CKGR_PLLAR_ONE (0x1u << 29) /**< \brief (CKGR_PLLAR) Must Be Set to 1 */ +/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */ +#define PMC_MCKR_CSS_Pos 0 +#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) /**< \brief (PMC_MCKR) Master Clock Source Selection */ +#define PMC_MCKR_CSS(value) ((PMC_MCKR_CSS_Msk & ((value) << PMC_MCKR_CSS_Pos))) +#define PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_MCKR) Slow Clock is selected */ +#define PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_MCKR) Main Clock is selected */ +#define PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_MCKR) PLLA Clock is selected */ +#define PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_MCKR) Divided UPLL Clock is selected */ +#define PMC_MCKR_PRES_Pos 4 +#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) /**< \brief (PMC_MCKR) Processor Clock Prescaler */ +#define PMC_MCKR_PRES(value) ((PMC_MCKR_PRES_Msk & ((value) << PMC_MCKR_PRES_Pos))) +#define PMC_MCKR_PRES_CLK_1 (0x0u << 4) /**< \brief (PMC_MCKR) Selected clock */ +#define PMC_MCKR_PRES_CLK_2 (0x1u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 2 */ +#define PMC_MCKR_PRES_CLK_4 (0x2u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 4 */ +#define PMC_MCKR_PRES_CLK_8 (0x3u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 8 */ +#define PMC_MCKR_PRES_CLK_16 (0x4u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 16 */ +#define PMC_MCKR_PRES_CLK_32 (0x5u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 32 */ +#define PMC_MCKR_PRES_CLK_64 (0x6u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 64 */ +#define PMC_MCKR_PRES_CLK_3 (0x7u << 4) /**< \brief (PMC_MCKR) Selected clock divided by 3 */ +#define PMC_MCKR_MDIV_Pos 8 +#define PMC_MCKR_MDIV_Msk (0x3u << PMC_MCKR_MDIV_Pos) /**< \brief (PMC_MCKR) Master Clock Division */ +#define PMC_MCKR_MDIV(value) ((PMC_MCKR_MDIV_Msk & ((value) << PMC_MCKR_MDIV_Pos))) +#define PMC_MCKR_MDIV_EQ_PCK (0x0u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 1. */ +#define PMC_MCKR_MDIV_PCK_DIV2 (0x1u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 2. */ +#define PMC_MCKR_MDIV_PCK_DIV4 (0x2u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 4. */ +#define PMC_MCKR_MDIV_PCK_DIV3 (0x3u << 8) /**< \brief (PMC_MCKR) Master Clock is Prescaler Output Clock divided by 3. */ +#define PMC_MCKR_UPLLDIV2 (0x1u << 13) /**< \brief (PMC_MCKR) UPLL Divisor by 2 */ +/* -------- PMC_USB : (PMC Offset: 0x0038) USB Clock Register -------- */ +#define PMC_USB_USBS (0x1u << 0) /**< \brief (PMC_USB) USB Input Clock Selection */ +#define PMC_USB_USBDIV_Pos 8 +#define PMC_USB_USBDIV_Msk (0xfu << PMC_USB_USBDIV_Pos) /**< \brief (PMC_USB) Divider for USB Clock */ +#define PMC_USB_USBDIV(value) ((PMC_USB_USBDIV_Msk & ((value) << PMC_USB_USBDIV_Pos))) +/* -------- PMC_PCK[7] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */ +#define PMC_PCK_CSS_Pos 0 +#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) /**< \brief (PMC_PCK[7]) Master Clock Source Selection */ +#define PMC_PCK_CSS(value) ((PMC_PCK_CSS_Msk & ((value) << PMC_PCK_CSS_Pos))) +#define PMC_PCK_CSS_SLOW_CLK (0x0u << 0) /**< \brief (PMC_PCK[7]) Slow Clock is selected */ +#define PMC_PCK_CSS_MAIN_CLK (0x1u << 0) /**< \brief (PMC_PCK[7]) Main Clock is selected */ +#define PMC_PCK_CSS_PLLA_CLK (0x2u << 0) /**< \brief (PMC_PCK[7]) PLLA Clock is selected */ +#define PMC_PCK_CSS_UPLL_CLK (0x3u << 0) /**< \brief (PMC_PCK[7]) Divided UPLL Clock is selected */ +#define PMC_PCK_CSS_MCK (0x4u << 0) /**< \brief (PMC_PCK[7]) Master Clock is selected */ +#define PMC_PCK_PRES_Pos 4 +#define PMC_PCK_PRES_Msk (0xffu << PMC_PCK_PRES_Pos) /**< \brief (PMC_PCK[7]) Programmable Clock Prescaler */ +#define PMC_PCK_PRES(value) ((PMC_PCK_PRES_Msk & ((value) << PMC_PCK_PRES_Pos))) +/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */ +#define PMC_IER_MOSCXTS (0x1u << 0) /**< \brief (PMC_IER) Main Crystal Oscillator Status Interrupt Enable */ +#define PMC_IER_LOCKA (0x1u << 1) /**< \brief (PMC_IER) PLLA Lock Interrupt Enable */ +#define PMC_IER_MCKRDY (0x1u << 3) /**< \brief (PMC_IER) Master Clock Ready Interrupt Enable */ +#define PMC_IER_LOCKU (0x1u << 6) /**< \brief (PMC_IER) UTMI PLL Lock Interrupt Enable */ +#define PMC_IER_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IER) Programmable Clock Ready 0 Interrupt Enable */ +#define PMC_IER_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IER) Programmable Clock Ready 1 Interrupt Enable */ +#define PMC_IER_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IER) Programmable Clock Ready 2 Interrupt Enable */ +#define PMC_IER_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IER) Programmable Clock Ready 3 Interrupt Enable */ +#define PMC_IER_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IER) Programmable Clock Ready 4 Interrupt Enable */ +#define PMC_IER_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IER) Programmable Clock Ready 5 Interrupt Enable */ +#define PMC_IER_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IER) Programmable Clock Ready 6 Interrupt Enable */ +#define PMC_IER_MOSCSELS (0x1u << 16) /**< \brief (PMC_IER) Main Oscillator Selection Status Interrupt Enable */ +#define PMC_IER_MOSCRCS (0x1u << 17) /**< \brief (PMC_IER) Main On-Chip RC Status Interrupt Enable */ +#define PMC_IER_CFDEV (0x1u << 18) /**< \brief (PMC_IER) Clock Failure Detector Event Interrupt Enable */ +#define PMC_IER_XT32KERR (0x1u << 21) /**< \brief (PMC_IER) Slow Crystal Oscillator Error Interrupt Enable */ +/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */ +#define PMC_IDR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable */ +#define PMC_IDR_LOCKA (0x1u << 1) /**< \brief (PMC_IDR) PLLA Lock Interrupt Disable */ +#define PMC_IDR_MCKRDY (0x1u << 3) /**< \brief (PMC_IDR) Master Clock Ready Interrupt Disable */ +#define PMC_IDR_LOCKU (0x1u << 6) /**< \brief (PMC_IDR) UTMI PLL Lock Interrupt Disable */ +#define PMC_IDR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable */ +#define PMC_IDR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable */ +#define PMC_IDR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable */ +#define PMC_IDR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_IDR) Programmable Clock Ready 3 Interrupt Disable */ +#define PMC_IDR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_IDR) Programmable Clock Ready 4 Interrupt Disable */ +#define PMC_IDR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_IDR) Programmable Clock Ready 5 Interrupt Disable */ +#define PMC_IDR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_IDR) Programmable Clock Ready 6 Interrupt Disable */ +#define PMC_IDR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IDR) Main Oscillator Selection Status Interrupt Disable */ +#define PMC_IDR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IDR) Main On-Chip RC Status Interrupt Disable */ +#define PMC_IDR_CFDEV (0x1u << 18) /**< \brief (PMC_IDR) Clock Failure Detector Event Interrupt Disable */ +#define PMC_IDR_XT32KERR (0x1u << 21) /**< \brief (PMC_IDR) Slow Crystal Oscillator Error Interrupt Disable */ +/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */ +#define PMC_SR_MOSCXTS (0x1u << 0) /**< \brief (PMC_SR) Main Crystal Oscillator Status */ +#define PMC_SR_LOCKA (0x1u << 1) /**< \brief (PMC_SR) PLLA Lock Status */ +#define PMC_SR_MCKRDY (0x1u << 3) /**< \brief (PMC_SR) Master Clock Status */ +#define PMC_SR_LOCKU (0x1u << 6) /**< \brief (PMC_SR) UTMI PLL Lock Status */ +#define PMC_SR_OSCSELS (0x1u << 7) /**< \brief (PMC_SR) Slow Clock Oscillator Selection */ +#define PMC_SR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY3 (0x1u << 11) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY4 (0x1u << 12) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY5 (0x1u << 13) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_PCKRDY6 (0x1u << 14) /**< \brief (PMC_SR) Programmable Clock Ready Status */ +#define PMC_SR_MOSCSELS (0x1u << 16) /**< \brief (PMC_SR) Main Oscillator Selection Status */ +#define PMC_SR_MOSCRCS (0x1u << 17) /**< \brief (PMC_SR) Main On-Chip RC Oscillator Status */ +#define PMC_SR_CFDEV (0x1u << 18) /**< \brief (PMC_SR) Clock Failure Detector Event */ +#define PMC_SR_CFDS (0x1u << 19) /**< \brief (PMC_SR) Clock Failure Detector Status */ +#define PMC_SR_FOS (0x1u << 20) /**< \brief (PMC_SR) Clock Failure Detector Fault Output Status */ +#define PMC_SR_XT32KERR (0x1u << 21) /**< \brief (PMC_SR) Slow Crystal Oscillator Error */ +/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */ +#define PMC_IMR_MOSCXTS (0x1u << 0) /**< \brief (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask */ +#define PMC_IMR_LOCKA (0x1u << 1) /**< \brief (PMC_IMR) PLLA Lock Interrupt Mask */ +#define PMC_IMR_MCKRDY (0x1u << 3) /**< \brief (PMC_IMR) Master Clock Ready Interrupt Mask */ +#define PMC_IMR_LOCKU (0x1u << 6) /**< \brief (PMC_IMR) UTMI PLL Lock Interrupt Mask */ +#define PMC_IMR_PCKRDY0 (0x1u << 8) /**< \brief (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask */ +#define PMC_IMR_PCKRDY1 (0x1u << 9) /**< \brief (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask */ +#define PMC_IMR_PCKRDY2 (0x1u << 10) /**< \brief (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask */ +#define PMC_IMR_MOSCSELS (0x1u << 16) /**< \brief (PMC_IMR) Main Oscillator Selection Status Interrupt Mask */ +#define PMC_IMR_MOSCRCS (0x1u << 17) /**< \brief (PMC_IMR) Main On-Chip RC Status Interrupt Mask */ +#define PMC_IMR_CFDEV (0x1u << 18) /**< \brief (PMC_IMR) Clock Failure Detector Event Interrupt Mask */ +#define PMC_IMR_XT32KERR (0x1u << 21) /**< \brief (PMC_IMR) Slow Crystal Oscillator Error Interrupt Mask */ +/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */ +#define PMC_FSMR_FSTT0 (0x1u << 0) /**< \brief (PMC_FSMR) Fast Startup Input Enable 0 */ +#define PMC_FSMR_FSTT1 (0x1u << 1) /**< \brief (PMC_FSMR) Fast Startup Input Enable 1 */ +#define PMC_FSMR_FSTT2 (0x1u << 2) /**< \brief (PMC_FSMR) Fast Startup Input Enable 2 */ +#define PMC_FSMR_FSTT3 (0x1u << 3) /**< \brief (PMC_FSMR) Fast Startup Input Enable 3 */ +#define PMC_FSMR_FSTT4 (0x1u << 4) /**< \brief (PMC_FSMR) Fast Startup Input Enable 4 */ +#define PMC_FSMR_FSTT5 (0x1u << 5) /**< \brief (PMC_FSMR) Fast Startup Input Enable 5 */ +#define PMC_FSMR_FSTT6 (0x1u << 6) /**< \brief (PMC_FSMR) Fast Startup Input Enable 6 */ +#define PMC_FSMR_FSTT7 (0x1u << 7) /**< \brief (PMC_FSMR) Fast Startup Input Enable 7 */ +#define PMC_FSMR_FSTT8 (0x1u << 8) /**< \brief (PMC_FSMR) Fast Startup Input Enable 8 */ +#define PMC_FSMR_FSTT9 (0x1u << 9) /**< \brief (PMC_FSMR) Fast Startup Input Enable 9 */ +#define PMC_FSMR_FSTT10 (0x1u << 10) /**< \brief (PMC_FSMR) Fast Startup Input Enable 10 */ +#define PMC_FSMR_FSTT11 (0x1u << 11) /**< \brief (PMC_FSMR) Fast Startup Input Enable 11 */ +#define PMC_FSMR_FSTT12 (0x1u << 12) /**< \brief (PMC_FSMR) Fast Startup Input Enable 12 */ +#define PMC_FSMR_FSTT13 (0x1u << 13) /**< \brief (PMC_FSMR) Fast Startup Input Enable 13 */ +#define PMC_FSMR_FSTT14 (0x1u << 14) /**< \brief (PMC_FSMR) Fast Startup Input Enable 14 */ +#define PMC_FSMR_FSTT15 (0x1u << 15) /**< \brief (PMC_FSMR) Fast Startup Input Enable 15 */ +#define PMC_FSMR_RTTAL (0x1u << 16) /**< \brief (PMC_FSMR) RTT Alarm Enable */ +#define PMC_FSMR_RTCAL (0x1u << 17) /**< \brief (PMC_FSMR) RTC Alarm Enable */ +#define PMC_FSMR_USBAL (0x1u << 18) /**< \brief (PMC_FSMR) USB Alarm Enable */ +#define PMC_FSMR_LPM (0x1u << 20) /**< \brief (PMC_FSMR) Low-power Mode */ +#define PMC_FSMR_FLPM_Pos 21 +#define PMC_FSMR_FLPM_Msk (0x3u << PMC_FSMR_FLPM_Pos) /**< \brief (PMC_FSMR) Flash Low-power Mode */ +#define PMC_FSMR_FLPM(value) ((PMC_FSMR_FLPM_Msk & ((value) << PMC_FSMR_FLPM_Pos))) +#define PMC_FSMR_FLPM_FLASH_STANDBY (0x0u << 21) /**< \brief (PMC_FSMR) Flash is in Standby Mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_DEEP_POWERDOWN (0x1u << 21) /**< \brief (PMC_FSMR) Flash is in Deep-power-down mode when system enters Wait Mode */ +#define PMC_FSMR_FLPM_FLASH_IDLE (0x2u << 21) /**< \brief (PMC_FSMR) Idle mode */ +#define PMC_FSMR_FFLPM (0x1u << 23) /**< \brief (PMC_FSMR) Force Flash Low-power Mode */ +/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */ +#define PMC_FSPR_FSTP0 (0x1u << 0) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 0 */ +#define PMC_FSPR_FSTP1 (0x1u << 1) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 1 */ +#define PMC_FSPR_FSTP2 (0x1u << 2) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 2 */ +#define PMC_FSPR_FSTP3 (0x1u << 3) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 3 */ +#define PMC_FSPR_FSTP4 (0x1u << 4) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 4 */ +#define PMC_FSPR_FSTP5 (0x1u << 5) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 5 */ +#define PMC_FSPR_FSTP6 (0x1u << 6) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 6 */ +#define PMC_FSPR_FSTP7 (0x1u << 7) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 7 */ +#define PMC_FSPR_FSTP8 (0x1u << 8) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 8 */ +#define PMC_FSPR_FSTP9 (0x1u << 9) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 9 */ +#define PMC_FSPR_FSTP10 (0x1u << 10) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 10 */ +#define PMC_FSPR_FSTP11 (0x1u << 11) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 11 */ +#define PMC_FSPR_FSTP12 (0x1u << 12) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 12 */ +#define PMC_FSPR_FSTP13 (0x1u << 13) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 13 */ +#define PMC_FSPR_FSTP14 (0x1u << 14) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 14 */ +#define PMC_FSPR_FSTP15 (0x1u << 15) /**< \brief (PMC_FSPR) Fast Startup Input Polarity 15 */ +/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */ +#define PMC_FOCR_FOCLR (0x1u << 0) /**< \brief (PMC_FOCR) Fault Output Clear */ +/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protection Mode Register -------- */ +#define PMC_WPMR_WPEN (0x1u << 0) /**< \brief (PMC_WPMR) Write Protection Enable */ +#define PMC_WPMR_WPKEY_Pos 8 +#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) /**< \brief (PMC_WPMR) Write Protection Key */ +#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) +#define PMC_WPMR_WPKEY_PASSWD (0x504D43u << 8) /**< \brief (PMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protection Status Register -------- */ +#define PMC_WPSR_WPVS (0x1u << 0) /**< \brief (PMC_WPSR) Write Protection Violation Status */ +#define PMC_WPSR_WPVSRC_Pos 8 +#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) /**< \brief (PMC_WPSR) Write Protection Violation Source */ +/* -------- PMC_PCER1 : (PMC Offset: 0x0100) Peripheral Clock Enable Register 1 -------- */ +#define PMC_PCER1_PID32 (0x1u << 0) /**< \brief (PMC_PCER1) Peripheral Clock 32 Enable */ +#define PMC_PCER1_PID33 (0x1u << 1) /**< \brief (PMC_PCER1) Peripheral Clock 33 Enable */ +#define PMC_PCER1_PID34 (0x1u << 2) /**< \brief (PMC_PCER1) Peripheral Clock 34 Enable */ +#define PMC_PCER1_PID35 (0x1u << 3) /**< \brief (PMC_PCER1) Peripheral Clock 35 Enable */ +#define PMC_PCER1_PID37 (0x1u << 5) /**< \brief (PMC_PCER1) Peripheral Clock 37 Enable */ +#define PMC_PCER1_PID39 (0x1u << 7) /**< \brief (PMC_PCER1) Peripheral Clock 39 Enable */ +#define PMC_PCER1_PID40 (0x1u << 8) /**< \brief (PMC_PCER1) Peripheral Clock 40 Enable */ +#define PMC_PCER1_PID41 (0x1u << 9) /**< \brief (PMC_PCER1) Peripheral Clock 41 Enable */ +#define PMC_PCER1_PID42 (0x1u << 10) /**< \brief (PMC_PCER1) Peripheral Clock 42 Enable */ +#define PMC_PCER1_PID43 (0x1u << 11) /**< \brief (PMC_PCER1) Peripheral Clock 43 Enable */ +#define PMC_PCER1_PID44 (0x1u << 12) /**< \brief (PMC_PCER1) Peripheral Clock 44 Enable */ +#define PMC_PCER1_PID45 (0x1u << 13) /**< \brief (PMC_PCER1) Peripheral Clock 45 Enable */ +#define PMC_PCER1_PID46 (0x1u << 14) /**< \brief (PMC_PCER1) Peripheral Clock 46 Enable */ +#define PMC_PCER1_PID47 (0x1u << 15) /**< \brief (PMC_PCER1) Peripheral Clock 47 Enable */ +#define PMC_PCER1_PID48 (0x1u << 16) /**< \brief (PMC_PCER1) Peripheral Clock 48 Enable */ +#define PMC_PCER1_PID49 (0x1u << 17) /**< \brief (PMC_PCER1) Peripheral Clock 49 Enable */ +#define PMC_PCER1_PID50 (0x1u << 18) /**< \brief (PMC_PCER1) Peripheral Clock 50 Enable */ +#define PMC_PCER1_PID51 (0x1u << 19) /**< \brief (PMC_PCER1) Peripheral Clock 51 Enable */ +#define PMC_PCER1_PID52 (0x1u << 20) /**< \brief (PMC_PCER1) Peripheral Clock 52 Enable */ +#define PMC_PCER1_PID53 (0x1u << 21) /**< \brief (PMC_PCER1) Peripheral Clock 53 Enable */ +#define PMC_PCER1_PID56 (0x1u << 24) /**< \brief (PMC_PCER1) Peripheral Clock 56 Enable */ +#define PMC_PCER1_PID57 (0x1u << 25) /**< \brief (PMC_PCER1) Peripheral Clock 57 Enable */ +#define PMC_PCER1_PID58 (0x1u << 26) /**< \brief (PMC_PCER1) Peripheral Clock 58 Enable */ +#define PMC_PCER1_PID59 (0x1u << 27) /**< \brief (PMC_PCER1) Peripheral Clock 59 Enable */ +#define PMC_PCER1_PID60 (0x1u << 28) /**< \brief (PMC_PCER1) Peripheral Clock 60 Enable */ +/* -------- PMC_PCDR1 : (PMC Offset: 0x0104) Peripheral Clock Disable Register 1 -------- */ +#define PMC_PCDR1_PID32 (0x1u << 0) /**< \brief (PMC_PCDR1) Peripheral Clock 32 Disable */ +#define PMC_PCDR1_PID33 (0x1u << 1) /**< \brief (PMC_PCDR1) Peripheral Clock 33 Disable */ +#define PMC_PCDR1_PID34 (0x1u << 2) /**< \brief (PMC_PCDR1) Peripheral Clock 34 Disable */ +#define PMC_PCDR1_PID35 (0x1u << 3) /**< \brief (PMC_PCDR1) Peripheral Clock 35 Disable */ +#define PMC_PCDR1_PID37 (0x1u << 5) /**< \brief (PMC_PCDR1) Peripheral Clock 37 Disable */ +#define PMC_PCDR1_PID39 (0x1u << 7) /**< \brief (PMC_PCDR1) Peripheral Clock 39 Disable */ +#define PMC_PCDR1_PID40 (0x1u << 8) /**< \brief (PMC_PCDR1) Peripheral Clock 40 Disable */ +#define PMC_PCDR1_PID41 (0x1u << 9) /**< \brief (PMC_PCDR1) Peripheral Clock 41 Disable */ +#define PMC_PCDR1_PID42 (0x1u << 10) /**< \brief (PMC_PCDR1) Peripheral Clock 42 Disable */ +#define PMC_PCDR1_PID43 (0x1u << 11) /**< \brief (PMC_PCDR1) Peripheral Clock 43 Disable */ +#define PMC_PCDR1_PID44 (0x1u << 12) /**< \brief (PMC_PCDR1) Peripheral Clock 44 Disable */ +#define PMC_PCDR1_PID45 (0x1u << 13) /**< \brief (PMC_PCDR1) Peripheral Clock 45 Disable */ +#define PMC_PCDR1_PID46 (0x1u << 14) /**< \brief (PMC_PCDR1) Peripheral Clock 46 Disable */ +#define PMC_PCDR1_PID47 (0x1u << 15) /**< \brief (PMC_PCDR1) Peripheral Clock 47 Disable */ +#define PMC_PCDR1_PID48 (0x1u << 16) /**< \brief (PMC_PCDR1) Peripheral Clock 48 Disable */ +#define PMC_PCDR1_PID49 (0x1u << 17) /**< \brief (PMC_PCDR1) Peripheral Clock 49 Disable */ +#define PMC_PCDR1_PID50 (0x1u << 18) /**< \brief (PMC_PCDR1) Peripheral Clock 50 Disable */ +#define PMC_PCDR1_PID51 (0x1u << 19) /**< \brief (PMC_PCDR1) Peripheral Clock 51 Disable */ +#define PMC_PCDR1_PID52 (0x1u << 20) /**< \brief (PMC_PCDR1) Peripheral Clock 52 Disable */ +#define PMC_PCDR1_PID53 (0x1u << 21) /**< \brief (PMC_PCDR1) Peripheral Clock 53 Disable */ +#define PMC_PCDR1_PID56 (0x1u << 24) /**< \brief (PMC_PCDR1) Peripheral Clock 56 Disable */ +#define PMC_PCDR1_PID57 (0x1u << 25) /**< \brief (PMC_PCDR1) Peripheral Clock 57 Disable */ +#define PMC_PCDR1_PID58 (0x1u << 26) /**< \brief (PMC_PCDR1) Peripheral Clock 58 Disable */ +#define PMC_PCDR1_PID59 (0x1u << 27) /**< \brief (PMC_PCDR1) Peripheral Clock 59 Disable */ +#define PMC_PCDR1_PID60 (0x1u << 28) /**< \brief (PMC_PCDR1) Peripheral Clock 60 Disable */ +/* -------- PMC_PCSR1 : (PMC Offset: 0x0108) Peripheral Clock Status Register 1 -------- */ +#define PMC_PCSR1_PID32 (0x1u << 0) /**< \brief (PMC_PCSR1) Peripheral Clock 32 Status */ +#define PMC_PCSR1_PID33 (0x1u << 1) /**< \brief (PMC_PCSR1) Peripheral Clock 33 Status */ +#define PMC_PCSR1_PID34 (0x1u << 2) /**< \brief (PMC_PCSR1) Peripheral Clock 34 Status */ +#define PMC_PCSR1_PID35 (0x1u << 3) /**< \brief (PMC_PCSR1) Peripheral Clock 35 Status */ +#define PMC_PCSR1_PID37 (0x1u << 5) /**< \brief (PMC_PCSR1) Peripheral Clock 37 Status */ +#define PMC_PCSR1_PID39 (0x1u << 7) /**< \brief (PMC_PCSR1) Peripheral Clock 39 Status */ +#define PMC_PCSR1_PID40 (0x1u << 8) /**< \brief (PMC_PCSR1) Peripheral Clock 40 Status */ +#define PMC_PCSR1_PID41 (0x1u << 9) /**< \brief (PMC_PCSR1) Peripheral Clock 41 Status */ +#define PMC_PCSR1_PID42 (0x1u << 10) /**< \brief (PMC_PCSR1) Peripheral Clock 42 Status */ +#define PMC_PCSR1_PID43 (0x1u << 11) /**< \brief (PMC_PCSR1) Peripheral Clock 43 Status */ +#define PMC_PCSR1_PID44 (0x1u << 12) /**< \brief (PMC_PCSR1) Peripheral Clock 44 Status */ +#define PMC_PCSR1_PID45 (0x1u << 13) /**< \brief (PMC_PCSR1) Peripheral Clock 45 Status */ +#define PMC_PCSR1_PID46 (0x1u << 14) /**< \brief (PMC_PCSR1) Peripheral Clock 46 Status */ +#define PMC_PCSR1_PID47 (0x1u << 15) /**< \brief (PMC_PCSR1) Peripheral Clock 47 Status */ +#define PMC_PCSR1_PID48 (0x1u << 16) /**< \brief (PMC_PCSR1) Peripheral Clock 48 Status */ +#define PMC_PCSR1_PID49 (0x1u << 17) /**< \brief (PMC_PCSR1) Peripheral Clock 49 Status */ +#define PMC_PCSR1_PID50 (0x1u << 18) /**< \brief (PMC_PCSR1) Peripheral Clock 50 Status */ +#define PMC_PCSR1_PID51 (0x1u << 19) /**< \brief (PMC_PCSR1) Peripheral Clock 51 Status */ +#define PMC_PCSR1_PID52 (0x1u << 20) /**< \brief (PMC_PCSR1) Peripheral Clock 52 Status */ +#define PMC_PCSR1_PID53 (0x1u << 21) /**< \brief (PMC_PCSR1) Peripheral Clock 53 Status */ +#define PMC_PCSR1_PID56 (0x1u << 24) /**< \brief (PMC_PCSR1) Peripheral Clock 56 Status */ +#define PMC_PCSR1_PID57 (0x1u << 25) /**< \brief (PMC_PCSR1) Peripheral Clock 57 Status */ +#define PMC_PCSR1_PID58 (0x1u << 26) /**< \brief (PMC_PCSR1) Peripheral Clock 58 Status */ +#define PMC_PCSR1_PID59 (0x1u << 27) /**< \brief (PMC_PCSR1) Peripheral Clock 59 Status */ +#define PMC_PCSR1_PID60 (0x1u << 28) /**< \brief (PMC_PCSR1) Peripheral Clock 60 Status */ +/* -------- PMC_PCR : (PMC Offset: 0x010C) Peripheral Control Register -------- */ +#define PMC_PCR_PID_Pos 0 +#define PMC_PCR_PID_Msk (0x3fu << PMC_PCR_PID_Pos) /**< \brief (PMC_PCR) Peripheral ID */ +#define PMC_PCR_PID(value) ((PMC_PCR_PID_Msk & ((value) << PMC_PCR_PID_Pos))) +#define PMC_PCR_CMD (0x1u << 12) /**< \brief (PMC_PCR) Command */ +#define PMC_PCR_DIV_Pos 16 +#define PMC_PCR_DIV_Msk (0x3u << PMC_PCR_DIV_Pos) /**< \brief (PMC_PCR) Divisor Value */ +#define PMC_PCR_DIV(value) ((PMC_PCR_DIV_Msk & ((value) << PMC_PCR_DIV_Pos))) +#define PMC_PCR_DIV_PERIPH_DIV_MCK (0x0u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK */ +#define PMC_PCR_DIV_PERIPH_DIV2_MCK (0x1u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/2 */ +#define PMC_PCR_DIV_PERIPH_DIV4_MCK (0x2u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/4 */ +#define PMC_PCR_DIV_PERIPH_DIV8_MCK (0x3u << 16) /**< \brief (PMC_PCR) Peripheral clock is MCK/8 */ +#define PMC_PCR_EN (0x1u << 28) /**< \brief (PMC_PCR) Enable */ +/* -------- PMC_OCR : (PMC Offset: 0x0110) Oscillator Calibration Register -------- */ +#define PMC_OCR_CAL4_Pos 0 +#define PMC_OCR_CAL4_Msk (0x7fu << PMC_OCR_CAL4_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL4(value) ((PMC_OCR_CAL4_Msk & ((value) << PMC_OCR_CAL4_Pos))) +#define PMC_OCR_SEL4 (0x1u << 7) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 4 MHz */ +#define PMC_OCR_CAL8_Pos 8 +#define PMC_OCR_CAL8_Msk (0x7fu << PMC_OCR_CAL8_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL8(value) ((PMC_OCR_CAL8_Msk & ((value) << PMC_OCR_CAL8_Pos))) +#define PMC_OCR_SEL8 (0x1u << 15) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 8 MHz */ +#define PMC_OCR_CAL12_Pos 16 +#define PMC_OCR_CAL12_Msk (0x7fu << PMC_OCR_CAL12_Pos) /**< \brief (PMC_OCR) RC Oscillator Calibration bits for 12 MHz */ +#define PMC_OCR_CAL12(value) ((PMC_OCR_CAL12_Msk & ((value) << PMC_OCR_CAL12_Pos))) +#define PMC_OCR_SEL12 (0x1u << 23) /**< \brief (PMC_OCR) Selection of RC Oscillator Calibration bits for 12 MHz */ +/* -------- PMC_SLPWK_ER0 : (PMC Offset: 0x0114) SleepWalking Enable Register 0 -------- */ +#define PMC_SLPWK_ER0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ER0) Peripheral 7 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ER0) Peripheral 8 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ER0) Peripheral 9 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ER0) Peripheral 10 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ER0) Peripheral 11 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ER0) Peripheral 12 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ER0) Peripheral 13 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ER0) Peripheral 14 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ER0) Peripheral 15 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ER0) Peripheral 16 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ER0) Peripheral 17 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ER0) Peripheral 18 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ER0) Peripheral 19 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ER0) Peripheral 20 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ER0) Peripheral 21 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ER0) Peripheral 22 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ER0) Peripheral 23 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ER0) Peripheral 24 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ER0) Peripheral 25 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ER0) Peripheral 26 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ER0) Peripheral 27 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ER0) Peripheral 28 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ER0) Peripheral 29 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ER0) Peripheral 30 SleepWalking Enable */ +#define PMC_SLPWK_ER0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ER0) Peripheral 31 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR0 : (PMC Offset: 0x0118) SleepWalking Disable Register 0 -------- */ +#define PMC_SLPWK_DR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_DR0) Peripheral 7 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_DR0) Peripheral 8 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_DR0) Peripheral 9 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_DR0) Peripheral 10 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_DR0) Peripheral 11 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_DR0) Peripheral 12 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_DR0) Peripheral 13 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_DR0) Peripheral 14 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_DR0) Peripheral 15 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_DR0) Peripheral 16 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_DR0) Peripheral 17 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_DR0) Peripheral 18 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_DR0) Peripheral 19 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_DR0) Peripheral 20 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_DR0) Peripheral 21 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_DR0) Peripheral 22 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_DR0) Peripheral 23 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_DR0) Peripheral 24 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_DR0) Peripheral 25 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_DR0) Peripheral 26 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_DR0) Peripheral 27 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_DR0) Peripheral 28 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_DR0) Peripheral 29 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_DR0) Peripheral 30 SleepWalking Disable */ +#define PMC_SLPWK_DR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_DR0) Peripheral 31 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR0 : (PMC Offset: 0x011C) SleepWalking Status Register 0 -------- */ +#define PMC_SLPWK_SR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_SR0) Peripheral 7 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_SR0) Peripheral 8 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_SR0) Peripheral 9 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_SR0) Peripheral 10 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_SR0) Peripheral 11 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_SR0) Peripheral 12 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_SR0) Peripheral 13 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_SR0) Peripheral 14 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_SR0) Peripheral 15 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_SR0) Peripheral 16 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_SR0) Peripheral 17 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_SR0) Peripheral 18 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_SR0) Peripheral 19 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_SR0) Peripheral 20 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_SR0) Peripheral 21 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_SR0) Peripheral 22 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_SR0) Peripheral 23 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_SR0) Peripheral 24 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_SR0) Peripheral 25 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_SR0) Peripheral 26 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_SR0) Peripheral 27 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_SR0) Peripheral 28 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_SR0) Peripheral 29 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_SR0) Peripheral 30 SleepWalking Status */ +#define PMC_SLPWK_SR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_SR0) Peripheral 31 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR0 : (PMC Offset: 0x0120) SleepWalking Activity Status Register 0 -------- */ +#define PMC_SLPWK_ASR0_PID7 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR0) Peripheral 7 Activity Status */ +#define PMC_SLPWK_ASR0_PID8 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR0) Peripheral 8 Activity Status */ +#define PMC_SLPWK_ASR0_PID9 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR0) Peripheral 9 Activity Status */ +#define PMC_SLPWK_ASR0_PID10 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR0) Peripheral 10 Activity Status */ +#define PMC_SLPWK_ASR0_PID11 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR0) Peripheral 11 Activity Status */ +#define PMC_SLPWK_ASR0_PID12 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR0) Peripheral 12 Activity Status */ +#define PMC_SLPWK_ASR0_PID13 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR0) Peripheral 13 Activity Status */ +#define PMC_SLPWK_ASR0_PID14 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR0) Peripheral 14 Activity Status */ +#define PMC_SLPWK_ASR0_PID15 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR0) Peripheral 15 Activity Status */ +#define PMC_SLPWK_ASR0_PID16 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR0) Peripheral 16 Activity Status */ +#define PMC_SLPWK_ASR0_PID17 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR0) Peripheral 17 Activity Status */ +#define PMC_SLPWK_ASR0_PID18 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR0) Peripheral 18 Activity Status */ +#define PMC_SLPWK_ASR0_PID19 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR0) Peripheral 19 Activity Status */ +#define PMC_SLPWK_ASR0_PID20 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR0) Peripheral 20 Activity Status */ +#define PMC_SLPWK_ASR0_PID21 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR0) Peripheral 21 Activity Status */ +#define PMC_SLPWK_ASR0_PID22 (0x1u << 22) /**< \brief (PMC_SLPWK_ASR0) Peripheral 22 Activity Status */ +#define PMC_SLPWK_ASR0_PID23 (0x1u << 23) /**< \brief (PMC_SLPWK_ASR0) Peripheral 23 Activity Status */ +#define PMC_SLPWK_ASR0_PID24 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR0) Peripheral 24 Activity Status */ +#define PMC_SLPWK_ASR0_PID25 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR0) Peripheral 25 Activity Status */ +#define PMC_SLPWK_ASR0_PID26 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR0) Peripheral 26 Activity Status */ +#define PMC_SLPWK_ASR0_PID27 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR0) Peripheral 27 Activity Status */ +#define PMC_SLPWK_ASR0_PID28 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR0) Peripheral 28 Activity Status */ +#define PMC_SLPWK_ASR0_PID29 (0x1u << 29) /**< \brief (PMC_SLPWK_ASR0) Peripheral 29 Activity Status */ +#define PMC_SLPWK_ASR0_PID30 (0x1u << 30) /**< \brief (PMC_SLPWK_ASR0) Peripheral 30 Activity Status */ +#define PMC_SLPWK_ASR0_PID31 (0x1u << 31) /**< \brief (PMC_SLPWK_ASR0) Peripheral 31 Activity Status */ +/* -------- PMC_SLPWK_ER1 : (PMC Offset: 0x0134) SleepWalking Enable Register 1 -------- */ +#define PMC_SLPWK_ER1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ER1) Peripheral 32 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ER1) Peripheral 33 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ER1) Peripheral 34 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ER1) Peripheral 35 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ER1) Peripheral 37 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ER1) Peripheral 39 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ER1) Peripheral 40 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ER1) Peripheral 41 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ER1) Peripheral 42 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ER1) Peripheral 43 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ER1) Peripheral 44 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ER1) Peripheral 45 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ER1) Peripheral 46 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ER1) Peripheral 47 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ER1) Peripheral 48 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ER1) Peripheral 49 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ER1) Peripheral 50 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ER1) Peripheral 51 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ER1) Peripheral 52 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ER1) Peripheral 53 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ER1) Peripheral 56 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ER1) Peripheral 57 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ER1) Peripheral 58 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ER1) Peripheral 59 SleepWalking Enable */ +#define PMC_SLPWK_ER1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ER1) Peripheral 60 SleepWalking Enable */ +/* -------- PMC_SLPWK_DR1 : (PMC Offset: 0x0138) SleepWalking Disable Register 1 -------- */ +#define PMC_SLPWK_DR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_DR1) Peripheral 32 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_DR1) Peripheral 33 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_DR1) Peripheral 34 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_DR1) Peripheral 35 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_DR1) Peripheral 37 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_DR1) Peripheral 39 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_DR1) Peripheral 40 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_DR1) Peripheral 41 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_DR1) Peripheral 42 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_DR1) Peripheral 43 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_DR1) Peripheral 44 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_DR1) Peripheral 45 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_DR1) Peripheral 46 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_DR1) Peripheral 47 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_DR1) Peripheral 48 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_DR1) Peripheral 49 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_DR1) Peripheral 50 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_DR1) Peripheral 51 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_DR1) Peripheral 52 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_DR1) Peripheral 53 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_DR1) Peripheral 56 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_DR1) Peripheral 57 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_DR1) Peripheral 58 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_DR1) Peripheral 59 SleepWalking Disable */ +#define PMC_SLPWK_DR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_DR1) Peripheral 60 SleepWalking Disable */ +/* -------- PMC_SLPWK_SR1 : (PMC Offset: 0x013C) SleepWalking Status Register 1 -------- */ +#define PMC_SLPWK_SR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_SR1) Peripheral 32 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_SR1) Peripheral 33 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_SR1) Peripheral 34 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_SR1) Peripheral 35 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_SR1) Peripheral 37 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_SR1) Peripheral 39 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_SR1) Peripheral 40 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_SR1) Peripheral 41 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_SR1) Peripheral 42 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_SR1) Peripheral 43 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_SR1) Peripheral 44 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_SR1) Peripheral 45 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_SR1) Peripheral 46 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_SR1) Peripheral 47 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_SR1) Peripheral 48 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_SR1) Peripheral 49 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_SR1) Peripheral 50 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_SR1) Peripheral 51 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_SR1) Peripheral 52 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_SR1) Peripheral 53 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_SR1) Peripheral 56 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_SR1) Peripheral 57 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_SR1) Peripheral 58 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_SR1) Peripheral 59 SleepWalking Status */ +#define PMC_SLPWK_SR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_SR1) Peripheral 60 SleepWalking Status */ +/* -------- PMC_SLPWK_ASR1 : (PMC Offset: 0x0140) SleepWalking Activity Status Register 1 -------- */ +#define PMC_SLPWK_ASR1_PID32 (0x1u << 0) /**< \brief (PMC_SLPWK_ASR1) Peripheral 32 Activity Status */ +#define PMC_SLPWK_ASR1_PID33 (0x1u << 1) /**< \brief (PMC_SLPWK_ASR1) Peripheral 33 Activity Status */ +#define PMC_SLPWK_ASR1_PID34 (0x1u << 2) /**< \brief (PMC_SLPWK_ASR1) Peripheral 34 Activity Status */ +#define PMC_SLPWK_ASR1_PID35 (0x1u << 3) /**< \brief (PMC_SLPWK_ASR1) Peripheral 35 Activity Status */ +#define PMC_SLPWK_ASR1_PID37 (0x1u << 5) /**< \brief (PMC_SLPWK_ASR1) Peripheral 37 Activity Status */ +#define PMC_SLPWK_ASR1_PID39 (0x1u << 7) /**< \brief (PMC_SLPWK_ASR1) Peripheral 39 Activity Status */ +#define PMC_SLPWK_ASR1_PID40 (0x1u << 8) /**< \brief (PMC_SLPWK_ASR1) Peripheral 40 Activity Status */ +#define PMC_SLPWK_ASR1_PID41 (0x1u << 9) /**< \brief (PMC_SLPWK_ASR1) Peripheral 41 Activity Status */ +#define PMC_SLPWK_ASR1_PID42 (0x1u << 10) /**< \brief (PMC_SLPWK_ASR1) Peripheral 42 Activity Status */ +#define PMC_SLPWK_ASR1_PID43 (0x1u << 11) /**< \brief (PMC_SLPWK_ASR1) Peripheral 43 Activity Status */ +#define PMC_SLPWK_ASR1_PID44 (0x1u << 12) /**< \brief (PMC_SLPWK_ASR1) Peripheral 44 Activity Status */ +#define PMC_SLPWK_ASR1_PID45 (0x1u << 13) /**< \brief (PMC_SLPWK_ASR1) Peripheral 45 Activity Status */ +#define PMC_SLPWK_ASR1_PID46 (0x1u << 14) /**< \brief (PMC_SLPWK_ASR1) Peripheral 46 Activity Status */ +#define PMC_SLPWK_ASR1_PID47 (0x1u << 15) /**< \brief (PMC_SLPWK_ASR1) Peripheral 47 Activity Status */ +#define PMC_SLPWK_ASR1_PID48 (0x1u << 16) /**< \brief (PMC_SLPWK_ASR1) Peripheral 48 Activity Status */ +#define PMC_SLPWK_ASR1_PID49 (0x1u << 17) /**< \brief (PMC_SLPWK_ASR1) Peripheral 49 Activity Status */ +#define PMC_SLPWK_ASR1_PID50 (0x1u << 18) /**< \brief (PMC_SLPWK_ASR1) Peripheral 50 Activity Status */ +#define PMC_SLPWK_ASR1_PID51 (0x1u << 19) /**< \brief (PMC_SLPWK_ASR1) Peripheral 51 Activity Status */ +#define PMC_SLPWK_ASR1_PID52 (0x1u << 20) /**< \brief (PMC_SLPWK_ASR1) Peripheral 52 Activity Status */ +#define PMC_SLPWK_ASR1_PID53 (0x1u << 21) /**< \brief (PMC_SLPWK_ASR1) Peripheral 53 Activity Status */ +#define PMC_SLPWK_ASR1_PID56 (0x1u << 24) /**< \brief (PMC_SLPWK_ASR1) Peripheral 56 Activity Status */ +#define PMC_SLPWK_ASR1_PID57 (0x1u << 25) /**< \brief (PMC_SLPWK_ASR1) Peripheral 57 Activity Status */ +#define PMC_SLPWK_ASR1_PID58 (0x1u << 26) /**< \brief (PMC_SLPWK_ASR1) Peripheral 58 Activity Status */ +#define PMC_SLPWK_ASR1_PID59 (0x1u << 27) /**< \brief (PMC_SLPWK_ASR1) Peripheral 59 Activity Status */ +#define PMC_SLPWK_ASR1_PID60 (0x1u << 28) /**< \brief (PMC_SLPWK_ASR1) Peripheral 60 Activity Status */ +/* -------- PMC_SLPWK_AIPR : (PMC Offset: 0x0144) SleepWalking Activity In Progress Register -------- */ +#define PMC_SLPWK_AIPR_AIP (0x1u << 0) /**< \brief (PMC_SLPWK_AIPR) Activity In Progress */ + +/*@}*/ + + +#endif /* _SAMV71_PMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pwm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pwm.h new file mode 100644 index 000000000..ebb69dc26 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_pwm.h @@ -0,0 +1,700 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM_COMPONENT_ +#define _SAMV71_PWM_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_PWM Pulse Width Modulation Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief PwmCh_num hardware registers */ +typedef struct { + __IO uint32_t PWM_CMR; /**< \brief (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ + __IO uint32_t PWM_CDTY; /**< \brief (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ + __O uint32_t PWM_CDTYUPD; /**< \brief (PwmCh_num Offset: 0x8) PWM Channel Duty Cycle Update Register */ + __IO uint32_t PWM_CPRD; /**< \brief (PwmCh_num Offset: 0xC) PWM Channel Period Register */ + __O uint32_t PWM_CPRDUPD; /**< \brief (PwmCh_num Offset: 0x10) PWM Channel Period Update Register */ + __I uint32_t PWM_CCNT; /**< \brief (PwmCh_num Offset: 0x14) PWM Channel Counter Register */ + __IO uint32_t PWM_DT; /**< \brief (PwmCh_num Offset: 0x18) PWM Channel Dead Time Register */ + __O uint32_t PWM_DTUPD; /**< \brief (PwmCh_num Offset: 0x1C) PWM Channel Dead Time Update Register */ +} PwmCh_num; +/** \brief PwmCmp hardware registers */ +typedef struct { + __IO uint32_t PWM_CMPV; /**< \brief (PwmCmp Offset: 0x0) PWM Comparison 0 Value Register */ + __O uint32_t PWM_CMPVUPD; /**< \brief (PwmCmp Offset: 0x4) PWM Comparison 0 Value Update Register */ + __IO uint32_t PWM_CMPM; /**< \brief (PwmCmp Offset: 0x8) PWM Comparison 0 Mode Register */ + __O uint32_t PWM_CMPMUPD; /**< \brief (PwmCmp Offset: 0xC) PWM Comparison 0 Mode Update Register */ +} PwmCmp; +/** \brief Pwm hardware registers */ +#define PWMCMP_NUMBER 8 +#define PWMCH_NUM_NUMBER 4 +typedef struct { + __IO uint32_t PWM_CLK; /**< \brief (Pwm Offset: 0x00) PWM Clock Register */ + __O uint32_t PWM_ENA; /**< \brief (Pwm Offset: 0x04) PWM Enable Register */ + __O uint32_t PWM_DIS; /**< \brief (Pwm Offset: 0x08) PWM Disable Register */ + __I uint32_t PWM_SR; /**< \brief (Pwm Offset: 0x0C) PWM Status Register */ + __O uint32_t PWM_IER1; /**< \brief (Pwm Offset: 0x10) PWM Interrupt Enable Register 1 */ + __O uint32_t PWM_IDR1; /**< \brief (Pwm Offset: 0x14) PWM Interrupt Disable Register 1 */ + __I uint32_t PWM_IMR1; /**< \brief (Pwm Offset: 0x18) PWM Interrupt Mask Register 1 */ + __I uint32_t PWM_ISR1; /**< \brief (Pwm Offset: 0x1C) PWM Interrupt Status Register 1 */ + __IO uint32_t PWM_SCM; /**< \brief (Pwm Offset: 0x20) PWM Sync Channels Mode Register */ + __O uint32_t PWM_DMAR; /**< \brief (Pwm Offset: 0x24) PWM DMA Register */ + __IO uint32_t PWM_SCUC; /**< \brief (Pwm Offset: 0x28) PWM Sync Channels Update Control Register */ + __IO uint32_t PWM_SCUP; /**< \brief (Pwm Offset: 0x2C) PWM Sync Channels Update Period Register */ + __O uint32_t PWM_SCUPUPD; /**< \brief (Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register */ + __O uint32_t PWM_IER2; /**< \brief (Pwm Offset: 0x34) PWM Interrupt Enable Register 2 */ + __O uint32_t PWM_IDR2; /**< \brief (Pwm Offset: 0x38) PWM Interrupt Disable Register 2 */ + __I uint32_t PWM_IMR2; /**< \brief (Pwm Offset: 0x3C) PWM Interrupt Mask Register 2 */ + __I uint32_t PWM_ISR2; /**< \brief (Pwm Offset: 0x40) PWM Interrupt Status Register 2 */ + __IO uint32_t PWM_OOV; /**< \brief (Pwm Offset: 0x44) PWM Output Override Value Register */ + __IO uint32_t PWM_OS; /**< \brief (Pwm Offset: 0x48) PWM Output Selection Register */ + __O uint32_t PWM_OSS; /**< \brief (Pwm Offset: 0x4C) PWM Output Selection Set Register */ + __O uint32_t PWM_OSC; /**< \brief (Pwm Offset: 0x50) PWM Output Selection Clear Register */ + __O uint32_t PWM_OSSUPD; /**< \brief (Pwm Offset: 0x54) PWM Output Selection Set Update Register */ + __O uint32_t PWM_OSCUPD; /**< \brief (Pwm Offset: 0x58) PWM Output Selection Clear Update Register */ + __IO uint32_t PWM_FMR; /**< \brief (Pwm Offset: 0x5C) PWM Fault Mode Register */ + __I uint32_t PWM_FSR; /**< \brief (Pwm Offset: 0x60) PWM Fault Status Register */ + __O uint32_t PWM_FCR; /**< \brief (Pwm Offset: 0x64) PWM Fault Clear Register */ + __IO uint32_t PWM_FPV1; /**< \brief (Pwm Offset: 0x68) PWM Fault Protection Value Register 1 */ + __IO uint32_t PWM_FPE; /**< \brief (Pwm Offset: 0x6C) PWM Fault Protection Enable Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t PWM_ELMR[8]; /**< \brief (Pwm Offset: 0x7C) PWM Event Line 0 Mode Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t PWM_SSPR; /**< \brief (Pwm Offset: 0xA0) PWM Spread Spectrum Register */ + __O uint32_t PWM_SSPUP; /**< \brief (Pwm Offset: 0xA4) PWM Spread Spectrum Update Register */ + __I uint32_t Reserved3[2]; + __IO uint32_t PWM_SMMR; /**< \brief (Pwm Offset: 0xB0) PWM Stepper Motor Mode Register */ + __I uint32_t Reserved4[3]; + __IO uint32_t PWM_FPV2; /**< \brief (Pwm Offset: 0xC0) PWM Fault Protection Value 2 Register */ + __I uint32_t Reserved5[8]; + __O uint32_t PWM_WPCR; /**< \brief (Pwm Offset: 0xE4) PWM Write Protection Control Register */ + __I uint32_t PWM_WPSR; /**< \brief (Pwm Offset: 0xE8) PWM Write Protection Status Register */ + __I uint32_t Reserved6[17]; + PwmCmp PWM_CMP[PWMCMP_NUMBER]; /**< \brief (Pwm Offset: 0x130) 0 .. 7 */ + __I uint32_t Reserved7[20]; + PwmCh_num PWM_CH_NUM[PWMCH_NUM_NUMBER]; /**< \brief (Pwm Offset: 0x200) ch_num = 0 .. 3 */ + __I uint32_t Reserved8[96]; + __O uint32_t PWM_CMUPD0; /**< \brief (Pwm Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) */ + __I uint32_t Reserved9[7]; + __O uint32_t PWM_CMUPD1; /**< \brief (Pwm Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) */ + __I uint32_t Reserved10[2]; + __IO uint32_t PWM_ETRG1; /**< \brief (Pwm Offset: 0x42C) PWM External Trigger Register (trg_num = 1) */ + __IO uint32_t PWM_LEBR1; /**< \brief (Pwm Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) */ + __I uint32_t Reserved11[3]; + __O uint32_t PWM_CMUPD2; /**< \brief (Pwm Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) */ + __I uint32_t Reserved12[2]; + __IO uint32_t PWM_ETRG2; /**< \brief (Pwm Offset: 0x44C) PWM External Trigger Register (trg_num = 2) */ + __IO uint32_t PWM_LEBR2; /**< \brief (Pwm Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) */ + __I uint32_t Reserved13[3]; + __O uint32_t PWM_CMUPD3; /**< \brief (Pwm Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) */ + __I uint32_t Reserved14[2]; + __IO uint32_t PWM_ETRG3; /**< \brief (Pwm Offset: 0x46C) PWM External Trigger Register (trg_num = 3) */ + __IO uint32_t PWM_LEBR3; /**< \brief (Pwm Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) */ + __I uint32_t Reserved15[6]; + __IO uint32_t PWM_ETRG4; /**< \brief (Pwm Offset: 0x48C) PWM External Trigger Register (trg_num = 4) */ + __IO uint32_t PWM_LEBR4; /**< \brief (Pwm Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) */ +} Pwm; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- PWM_CLK : (PWM Offset: 0x00) PWM Clock Register -------- */ +#define PWM_CLK_DIVA_Pos 0 +#define PWM_CLK_DIVA_Msk (0xffu << PWM_CLK_DIVA_Pos) /**< \brief (PWM_CLK) CLKA Divide Factor */ +#define PWM_CLK_DIVA(value) ((PWM_CLK_DIVA_Msk & ((value) << PWM_CLK_DIVA_Pos))) +#define PWM_CLK_DIVA_CLKA_POFF (0x0u << 0) /**< \brief (PWM_CLK) CLKA clock is turned off */ +#define PWM_CLK_DIVA_PREA (0x1u << 0) /**< \brief (PWM_CLK) CLKA clock is clock selected by PREA */ +#define PWM_CLK_PREA_Pos 8 +#define PWM_CLK_PREA_Msk (0xfu << PWM_CLK_PREA_Pos) /**< \brief (PWM_CLK) CLKA Source Clock Selection */ +#define PWM_CLK_PREA(value) ((PWM_CLK_PREA_Msk & ((value) << PWM_CLK_PREA_Pos))) +#define PWM_CLK_PREA_CLK (0x0u << 8) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREA_CLK_DIV2 (0x1u << 8) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREA_CLK_DIV4 (0x2u << 8) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREA_CLK_DIV8 (0x3u << 8) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREA_CLK_DIV16 (0x4u << 8) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREA_CLK_DIV32 (0x5u << 8) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREA_CLK_DIV64 (0x6u << 8) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREA_CLK_DIV128 (0x7u << 8) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREA_CLK_DIV256 (0x8u << 8) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREA_CLK_DIV512 (0x9u << 8) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREA_CLK_DIV1024 (0xAu << 8) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +#define PWM_CLK_DIVB_Pos 16 +#define PWM_CLK_DIVB_Msk (0xffu << PWM_CLK_DIVB_Pos) /**< \brief (PWM_CLK) CLKB Divide Factor */ +#define PWM_CLK_DIVB(value) ((PWM_CLK_DIVB_Msk & ((value) << PWM_CLK_DIVB_Pos))) +#define PWM_CLK_DIVB_CLKB_POFF (0x0u << 16) /**< \brief (PWM_CLK) CLKB clock is turned off */ +#define PWM_CLK_DIVB_PREB (0x1u << 16) /**< \brief (PWM_CLK) CLKB clock is clock selected by PREB */ +#define PWM_CLK_PREB_Pos 24 +#define PWM_CLK_PREB_Msk (0xfu << PWM_CLK_PREB_Pos) /**< \brief (PWM_CLK) CLKB Source Clock Selection */ +#define PWM_CLK_PREB(value) ((PWM_CLK_PREB_Msk & ((value) << PWM_CLK_PREB_Pos))) +#define PWM_CLK_PREB_CLK (0x0u << 24) /**< \brief (PWM_CLK) Peripheral clock */ +#define PWM_CLK_PREB_CLK_DIV2 (0x1u << 24) /**< \brief (PWM_CLK) Peripheral clock/2 */ +#define PWM_CLK_PREB_CLK_DIV4 (0x2u << 24) /**< \brief (PWM_CLK) Peripheral clock/4 */ +#define PWM_CLK_PREB_CLK_DIV8 (0x3u << 24) /**< \brief (PWM_CLK) Peripheral clock/8 */ +#define PWM_CLK_PREB_CLK_DIV16 (0x4u << 24) /**< \brief (PWM_CLK) Peripheral clock/16 */ +#define PWM_CLK_PREB_CLK_DIV32 (0x5u << 24) /**< \brief (PWM_CLK) Peripheral clock/32 */ +#define PWM_CLK_PREB_CLK_DIV64 (0x6u << 24) /**< \brief (PWM_CLK) Peripheral clock/64 */ +#define PWM_CLK_PREB_CLK_DIV128 (0x7u << 24) /**< \brief (PWM_CLK) Peripheral clock/128 */ +#define PWM_CLK_PREB_CLK_DIV256 (0x8u << 24) /**< \brief (PWM_CLK) Peripheral clock/256 */ +#define PWM_CLK_PREB_CLK_DIV512 (0x9u << 24) /**< \brief (PWM_CLK) Peripheral clock/512 */ +#define PWM_CLK_PREB_CLK_DIV1024 (0xAu << 24) /**< \brief (PWM_CLK) Peripheral clock/1024 */ +/* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ +#define PWM_ENA_CHID0 (0x1u << 0) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID1 (0x1u << 1) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID2 (0x1u << 2) /**< \brief (PWM_ENA) Channel ID */ +#define PWM_ENA_CHID3 (0x1u << 3) /**< \brief (PWM_ENA) Channel ID */ +/* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ +#define PWM_DIS_CHID0 (0x1u << 0) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID1 (0x1u << 1) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID2 (0x1u << 2) /**< \brief (PWM_DIS) Channel ID */ +#define PWM_DIS_CHID3 (0x1u << 3) /**< \brief (PWM_DIS) Channel ID */ +/* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ +#define PWM_SR_CHID0 (0x1u << 0) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID1 (0x1u << 1) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID2 (0x1u << 2) /**< \brief (PWM_SR) Channel ID */ +#define PWM_SR_CHID3 (0x1u << 3) /**< \brief (PWM_SR) Channel ID */ +/* -------- PWM_IER1 : (PWM Offset: 0x10) PWM Interrupt Enable Register 1 -------- */ +#define PWM_IER1_CHID0 (0x1u << 0) /**< \brief (PWM_IER1) Counter Event on Channel 0 Interrupt Enable */ +#define PWM_IER1_CHID1 (0x1u << 1) /**< \brief (PWM_IER1) Counter Event on Channel 1 Interrupt Enable */ +#define PWM_IER1_CHID2 (0x1u << 2) /**< \brief (PWM_IER1) Counter Event on Channel 2 Interrupt Enable */ +#define PWM_IER1_CHID3 (0x1u << 3) /**< \brief (PWM_IER1) Counter Event on Channel 3 Interrupt Enable */ +#define PWM_IER1_FCHID0 (0x1u << 16) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 0 Interrupt Enable */ +#define PWM_IER1_FCHID1 (0x1u << 17) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 1 Interrupt Enable */ +#define PWM_IER1_FCHID2 (0x1u << 18) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 2 Interrupt Enable */ +#define PWM_IER1_FCHID3 (0x1u << 19) /**< \brief (PWM_IER1) Fault Protection Trigger on Channel 3 Interrupt Enable */ +/* -------- PWM_IDR1 : (PWM Offset: 0x14) PWM Interrupt Disable Register 1 -------- */ +#define PWM_IDR1_CHID0 (0x1u << 0) /**< \brief (PWM_IDR1) Counter Event on Channel 0 Interrupt Disable */ +#define PWM_IDR1_CHID1 (0x1u << 1) /**< \brief (PWM_IDR1) Counter Event on Channel 1 Interrupt Disable */ +#define PWM_IDR1_CHID2 (0x1u << 2) /**< \brief (PWM_IDR1) Counter Event on Channel 2 Interrupt Disable */ +#define PWM_IDR1_CHID3 (0x1u << 3) /**< \brief (PWM_IDR1) Counter Event on Channel 3 Interrupt Disable */ +#define PWM_IDR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 0 Interrupt Disable */ +#define PWM_IDR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 1 Interrupt Disable */ +#define PWM_IDR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 2 Interrupt Disable */ +#define PWM_IDR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IDR1) Fault Protection Trigger on Channel 3 Interrupt Disable */ +/* -------- PWM_IMR1 : (PWM Offset: 0x18) PWM Interrupt Mask Register 1 -------- */ +#define PWM_IMR1_CHID0 (0x1u << 0) /**< \brief (PWM_IMR1) Counter Event on Channel 0 Interrupt Mask */ +#define PWM_IMR1_CHID1 (0x1u << 1) /**< \brief (PWM_IMR1) Counter Event on Channel 1 Interrupt Mask */ +#define PWM_IMR1_CHID2 (0x1u << 2) /**< \brief (PWM_IMR1) Counter Event on Channel 2 Interrupt Mask */ +#define PWM_IMR1_CHID3 (0x1u << 3) /**< \brief (PWM_IMR1) Counter Event on Channel 3 Interrupt Mask */ +#define PWM_IMR1_FCHID0 (0x1u << 16) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 0 Interrupt Mask */ +#define PWM_IMR1_FCHID1 (0x1u << 17) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 1 Interrupt Mask */ +#define PWM_IMR1_FCHID2 (0x1u << 18) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 2 Interrupt Mask */ +#define PWM_IMR1_FCHID3 (0x1u << 19) /**< \brief (PWM_IMR1) Fault Protection Trigger on Channel 3 Interrupt Mask */ +/* -------- PWM_ISR1 : (PWM Offset: 0x1C) PWM Interrupt Status Register 1 -------- */ +#define PWM_ISR1_CHID0 (0x1u << 0) /**< \brief (PWM_ISR1) Counter Event on Channel 0 */ +#define PWM_ISR1_CHID1 (0x1u << 1) /**< \brief (PWM_ISR1) Counter Event on Channel 1 */ +#define PWM_ISR1_CHID2 (0x1u << 2) /**< \brief (PWM_ISR1) Counter Event on Channel 2 */ +#define PWM_ISR1_CHID3 (0x1u << 3) /**< \brief (PWM_ISR1) Counter Event on Channel 3 */ +#define PWM_ISR1_FCHID0 (0x1u << 16) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 0 */ +#define PWM_ISR1_FCHID1 (0x1u << 17) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 1 */ +#define PWM_ISR1_FCHID2 (0x1u << 18) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 2 */ +#define PWM_ISR1_FCHID3 (0x1u << 19) /**< \brief (PWM_ISR1) Fault Protection Trigger on Channel 3 */ +/* -------- PWM_SCM : (PWM Offset: 0x20) PWM Sync Channels Mode Register -------- */ +#define PWM_SCM_SYNC0 (0x1u << 0) /**< \brief (PWM_SCM) Synchronous Channel 0 */ +#define PWM_SCM_SYNC1 (0x1u << 1) /**< \brief (PWM_SCM) Synchronous Channel 1 */ +#define PWM_SCM_SYNC2 (0x1u << 2) /**< \brief (PWM_SCM) Synchronous Channel 2 */ +#define PWM_SCM_SYNC3 (0x1u << 3) /**< \brief (PWM_SCM) Synchronous Channel 3 */ +#define PWM_SCM_UPDM_Pos 16 +#define PWM_SCM_UPDM_Msk (0x3u << PWM_SCM_UPDM_Pos) /**< \brief (PWM_SCM) Synchronous Channels Update Mode */ +#define PWM_SCM_UPDM(value) ((PWM_SCM_UPDM_Msk & ((value) << PWM_SCM_UPDM_Pos))) +#define PWM_SCM_UPDM_MODE0 (0x0u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and manual update of synchronous channels */ +#define PWM_SCM_UPDM_MODE1 (0x1u << 16) /**< \brief (PWM_SCM) Manual write of double buffer registers and automatic update of synchronous channels */ +#define PWM_SCM_UPDM_MODE2 (0x2u << 16) /**< \brief (PWM_SCM) Automatic write of duty-cycle update registers by the DMA and automatic update of synchronous channels */ +#define PWM_SCM_PTRM (0x1u << 20) /**< \brief (PWM_SCM) DMA Transfer Request Mode */ +#define PWM_SCM_PTRCS_Pos 21 +#define PWM_SCM_PTRCS_Msk (0x7u << PWM_SCM_PTRCS_Pos) /**< \brief (PWM_SCM) DMA Transfer Request Comparison Selection */ +#define PWM_SCM_PTRCS(value) ((PWM_SCM_PTRCS_Msk & ((value) << PWM_SCM_PTRCS_Pos))) +/* -------- PWM_DMAR : (PWM Offset: 0x24) PWM DMA Register -------- */ +#define PWM_DMAR_DMADUTY_Pos 0 +#define PWM_DMAR_DMADUTY_Msk (0xffffffu << PWM_DMAR_DMADUTY_Pos) /**< \brief (PWM_DMAR) Duty-Cycle Holding Register for DMA Access */ +#define PWM_DMAR_DMADUTY(value) ((PWM_DMAR_DMADUTY_Msk & ((value) << PWM_DMAR_DMADUTY_Pos))) +/* -------- PWM_SCUC : (PWM Offset: 0x28) PWM Sync Channels Update Control Register -------- */ +#define PWM_SCUC_UPDULOCK (0x1u << 0) /**< \brief (PWM_SCUC) Synchronous Channels Update Unlock */ +/* -------- PWM_SCUP : (PWM Offset: 0x2C) PWM Sync Channels Update Period Register -------- */ +#define PWM_SCUP_UPR_Pos 0 +#define PWM_SCUP_UPR_Msk (0xfu << PWM_SCUP_UPR_Pos) /**< \brief (PWM_SCUP) Update Period */ +#define PWM_SCUP_UPR(value) ((PWM_SCUP_UPR_Msk & ((value) << PWM_SCUP_UPR_Pos))) +#define PWM_SCUP_UPRCNT_Pos 4 +#define PWM_SCUP_UPRCNT_Msk (0xfu << PWM_SCUP_UPRCNT_Pos) /**< \brief (PWM_SCUP) Update Period Counter */ +#define PWM_SCUP_UPRCNT(value) ((PWM_SCUP_UPRCNT_Msk & ((value) << PWM_SCUP_UPRCNT_Pos))) +/* -------- PWM_SCUPUPD : (PWM Offset: 0x30) PWM Sync Channels Update Period Update Register -------- */ +#define PWM_SCUPUPD_UPRUPD_Pos 0 +#define PWM_SCUPUPD_UPRUPD_Msk (0xfu << PWM_SCUPUPD_UPRUPD_Pos) /**< \brief (PWM_SCUPUPD) Update Period Update */ +#define PWM_SCUPUPD_UPRUPD(value) ((PWM_SCUPUPD_UPRUPD_Msk & ((value) << PWM_SCUPUPD_UPRUPD_Pos))) +/* -------- PWM_IER2 : (PWM Offset: 0x34) PWM Interrupt Enable Register 2 -------- */ +#define PWM_IER2_WRDY (0x1u << 0) /**< \brief (PWM_IER2) Write Ready for Synchronous Channels Update Interrupt Enable */ +#define PWM_IER2_UNRE (0x1u << 3) /**< \brief (PWM_IER2) Synchronous Channels Update Underrun Error Interrupt Enable */ +#define PWM_IER2_CMPM0 (0x1u << 8) /**< \brief (PWM_IER2) Comparison 0 Match Interrupt Enable */ +#define PWM_IER2_CMPM1 (0x1u << 9) /**< \brief (PWM_IER2) Comparison 1 Match Interrupt Enable */ +#define PWM_IER2_CMPM2 (0x1u << 10) /**< \brief (PWM_IER2) Comparison 2 Match Interrupt Enable */ +#define PWM_IER2_CMPM3 (0x1u << 11) /**< \brief (PWM_IER2) Comparison 3 Match Interrupt Enable */ +#define PWM_IER2_CMPM4 (0x1u << 12) /**< \brief (PWM_IER2) Comparison 4 Match Interrupt Enable */ +#define PWM_IER2_CMPM5 (0x1u << 13) /**< \brief (PWM_IER2) Comparison 5 Match Interrupt Enable */ +#define PWM_IER2_CMPM6 (0x1u << 14) /**< \brief (PWM_IER2) Comparison 6 Match Interrupt Enable */ +#define PWM_IER2_CMPM7 (0x1u << 15) /**< \brief (PWM_IER2) Comparison 7 Match Interrupt Enable */ +#define PWM_IER2_CMPU0 (0x1u << 16) /**< \brief (PWM_IER2) Comparison 0 Update Interrupt Enable */ +#define PWM_IER2_CMPU1 (0x1u << 17) /**< \brief (PWM_IER2) Comparison 1 Update Interrupt Enable */ +#define PWM_IER2_CMPU2 (0x1u << 18) /**< \brief (PWM_IER2) Comparison 2 Update Interrupt Enable */ +#define PWM_IER2_CMPU3 (0x1u << 19) /**< \brief (PWM_IER2) Comparison 3 Update Interrupt Enable */ +#define PWM_IER2_CMPU4 (0x1u << 20) /**< \brief (PWM_IER2) Comparison 4 Update Interrupt Enable */ +#define PWM_IER2_CMPU5 (0x1u << 21) /**< \brief (PWM_IER2) Comparison 5 Update Interrupt Enable */ +#define PWM_IER2_CMPU6 (0x1u << 22) /**< \brief (PWM_IER2) Comparison 6 Update Interrupt Enable */ +#define PWM_IER2_CMPU7 (0x1u << 23) /**< \brief (PWM_IER2) Comparison 7 Update Interrupt Enable */ +/* -------- PWM_IDR2 : (PWM Offset: 0x38) PWM Interrupt Disable Register 2 -------- */ +#define PWM_IDR2_WRDY (0x1u << 0) /**< \brief (PWM_IDR2) Write Ready for Synchronous Channels Update Interrupt Disable */ +#define PWM_IDR2_UNRE (0x1u << 3) /**< \brief (PWM_IDR2) Synchronous Channels Update Underrun Error Interrupt Disable */ +#define PWM_IDR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IDR2) Comparison 0 Match Interrupt Disable */ +#define PWM_IDR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IDR2) Comparison 1 Match Interrupt Disable */ +#define PWM_IDR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IDR2) Comparison 2 Match Interrupt Disable */ +#define PWM_IDR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IDR2) Comparison 3 Match Interrupt Disable */ +#define PWM_IDR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IDR2) Comparison 4 Match Interrupt Disable */ +#define PWM_IDR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IDR2) Comparison 5 Match Interrupt Disable */ +#define PWM_IDR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IDR2) Comparison 6 Match Interrupt Disable */ +#define PWM_IDR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IDR2) Comparison 7 Match Interrupt Disable */ +#define PWM_IDR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IDR2) Comparison 0 Update Interrupt Disable */ +#define PWM_IDR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IDR2) Comparison 1 Update Interrupt Disable */ +#define PWM_IDR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IDR2) Comparison 2 Update Interrupt Disable */ +#define PWM_IDR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IDR2) Comparison 3 Update Interrupt Disable */ +#define PWM_IDR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IDR2) Comparison 4 Update Interrupt Disable */ +#define PWM_IDR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IDR2) Comparison 5 Update Interrupt Disable */ +#define PWM_IDR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IDR2) Comparison 6 Update Interrupt Disable */ +#define PWM_IDR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IDR2) Comparison 7 Update Interrupt Disable */ +/* -------- PWM_IMR2 : (PWM Offset: 0x3C) PWM Interrupt Mask Register 2 -------- */ +#define PWM_IMR2_WRDY (0x1u << 0) /**< \brief (PWM_IMR2) Write Ready for Synchronous Channels Update Interrupt Mask */ +#define PWM_IMR2_UNRE (0x1u << 3) /**< \brief (PWM_IMR2) Synchronous Channels Update Underrun Error Interrupt Mask */ +#define PWM_IMR2_CMPM0 (0x1u << 8) /**< \brief (PWM_IMR2) Comparison 0 Match Interrupt Mask */ +#define PWM_IMR2_CMPM1 (0x1u << 9) /**< \brief (PWM_IMR2) Comparison 1 Match Interrupt Mask */ +#define PWM_IMR2_CMPM2 (0x1u << 10) /**< \brief (PWM_IMR2) Comparison 2 Match Interrupt Mask */ +#define PWM_IMR2_CMPM3 (0x1u << 11) /**< \brief (PWM_IMR2) Comparison 3 Match Interrupt Mask */ +#define PWM_IMR2_CMPM4 (0x1u << 12) /**< \brief (PWM_IMR2) Comparison 4 Match Interrupt Mask */ +#define PWM_IMR2_CMPM5 (0x1u << 13) /**< \brief (PWM_IMR2) Comparison 5 Match Interrupt Mask */ +#define PWM_IMR2_CMPM6 (0x1u << 14) /**< \brief (PWM_IMR2) Comparison 6 Match Interrupt Mask */ +#define PWM_IMR2_CMPM7 (0x1u << 15) /**< \brief (PWM_IMR2) Comparison 7 Match Interrupt Mask */ +#define PWM_IMR2_CMPU0 (0x1u << 16) /**< \brief (PWM_IMR2) Comparison 0 Update Interrupt Mask */ +#define PWM_IMR2_CMPU1 (0x1u << 17) /**< \brief (PWM_IMR2) Comparison 1 Update Interrupt Mask */ +#define PWM_IMR2_CMPU2 (0x1u << 18) /**< \brief (PWM_IMR2) Comparison 2 Update Interrupt Mask */ +#define PWM_IMR2_CMPU3 (0x1u << 19) /**< \brief (PWM_IMR2) Comparison 3 Update Interrupt Mask */ +#define PWM_IMR2_CMPU4 (0x1u << 20) /**< \brief (PWM_IMR2) Comparison 4 Update Interrupt Mask */ +#define PWM_IMR2_CMPU5 (0x1u << 21) /**< \brief (PWM_IMR2) Comparison 5 Update Interrupt Mask */ +#define PWM_IMR2_CMPU6 (0x1u << 22) /**< \brief (PWM_IMR2) Comparison 6 Update Interrupt Mask */ +#define PWM_IMR2_CMPU7 (0x1u << 23) /**< \brief (PWM_IMR2) Comparison 7 Update Interrupt Mask */ +/* -------- PWM_ISR2 : (PWM Offset: 0x40) PWM Interrupt Status Register 2 -------- */ +#define PWM_ISR2_WRDY (0x1u << 0) /**< \brief (PWM_ISR2) Write Ready for Synchronous Channels Update */ +#define PWM_ISR2_UNRE (0x1u << 3) /**< \brief (PWM_ISR2) Synchronous Channels Update Underrun Error */ +#define PWM_ISR2_CMPM0 (0x1u << 8) /**< \brief (PWM_ISR2) Comparison 0 Match */ +#define PWM_ISR2_CMPM1 (0x1u << 9) /**< \brief (PWM_ISR2) Comparison 1 Match */ +#define PWM_ISR2_CMPM2 (0x1u << 10) /**< \brief (PWM_ISR2) Comparison 2 Match */ +#define PWM_ISR2_CMPM3 (0x1u << 11) /**< \brief (PWM_ISR2) Comparison 3 Match */ +#define PWM_ISR2_CMPM4 (0x1u << 12) /**< \brief (PWM_ISR2) Comparison 4 Match */ +#define PWM_ISR2_CMPM5 (0x1u << 13) /**< \brief (PWM_ISR2) Comparison 5 Match */ +#define PWM_ISR2_CMPM6 (0x1u << 14) /**< \brief (PWM_ISR2) Comparison 6 Match */ +#define PWM_ISR2_CMPM7 (0x1u << 15) /**< \brief (PWM_ISR2) Comparison 7 Match */ +#define PWM_ISR2_CMPU0 (0x1u << 16) /**< \brief (PWM_ISR2) Comparison 0 Update */ +#define PWM_ISR2_CMPU1 (0x1u << 17) /**< \brief (PWM_ISR2) Comparison 1 Update */ +#define PWM_ISR2_CMPU2 (0x1u << 18) /**< \brief (PWM_ISR2) Comparison 2 Update */ +#define PWM_ISR2_CMPU3 (0x1u << 19) /**< \brief (PWM_ISR2) Comparison 3 Update */ +#define PWM_ISR2_CMPU4 (0x1u << 20) /**< \brief (PWM_ISR2) Comparison 4 Update */ +#define PWM_ISR2_CMPU5 (0x1u << 21) /**< \brief (PWM_ISR2) Comparison 5 Update */ +#define PWM_ISR2_CMPU6 (0x1u << 22) /**< \brief (PWM_ISR2) Comparison 6 Update */ +#define PWM_ISR2_CMPU7 (0x1u << 23) /**< \brief (PWM_ISR2) Comparison 7 Update */ +/* -------- PWM_OOV : (PWM Offset: 0x44) PWM Output Override Value Register -------- */ +#define PWM_OOV_OOVH0 (0x1u << 0) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 0 */ +#define PWM_OOV_OOVH1 (0x1u << 1) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 1 */ +#define PWM_OOV_OOVH2 (0x1u << 2) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 2 */ +#define PWM_OOV_OOVH3 (0x1u << 3) /**< \brief (PWM_OOV) Output Override Value for PWMH output of the channel 3 */ +#define PWM_OOV_OOVL0 (0x1u << 16) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 0 */ +#define PWM_OOV_OOVL1 (0x1u << 17) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 1 */ +#define PWM_OOV_OOVL2 (0x1u << 18) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 2 */ +#define PWM_OOV_OOVL3 (0x1u << 19) /**< \brief (PWM_OOV) Output Override Value for PWML output of the channel 3 */ +/* -------- PWM_OS : (PWM Offset: 0x48) PWM Output Selection Register -------- */ +#define PWM_OS_OSH0 (0x1u << 0) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 0 */ +#define PWM_OS_OSH1 (0x1u << 1) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 1 */ +#define PWM_OS_OSH2 (0x1u << 2) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 2 */ +#define PWM_OS_OSH3 (0x1u << 3) /**< \brief (PWM_OS) Output Selection for PWMH output of the channel 3 */ +#define PWM_OS_OSL0 (0x1u << 16) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 0 */ +#define PWM_OS_OSL1 (0x1u << 17) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 1 */ +#define PWM_OS_OSL2 (0x1u << 18) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 2 */ +#define PWM_OS_OSL3 (0x1u << 19) /**< \brief (PWM_OS) Output Selection for PWML output of the channel 3 */ +/* -------- PWM_OSS : (PWM Offset: 0x4C) PWM Output Selection Set Register -------- */ +#define PWM_OSS_OSSH0 (0x1u << 0) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSS_OSSH1 (0x1u << 1) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSS_OSSH2 (0x1u << 2) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSS_OSSH3 (0x1u << 3) /**< \brief (PWM_OSS) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSS_OSSL0 (0x1u << 16) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSS_OSSL1 (0x1u << 17) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSS_OSSL2 (0x1u << 18) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSS_OSSL3 (0x1u << 19) /**< \brief (PWM_OSS) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSC : (PWM Offset: 0x50) PWM Output Selection Clear Register -------- */ +#define PWM_OSC_OSCH0 (0x1u << 0) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSC_OSCH1 (0x1u << 1) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSC_OSCH2 (0x1u << 2) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSC_OSCH3 (0x1u << 3) /**< \brief (PWM_OSC) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSC_OSCL0 (0x1u << 16) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSC_OSCL1 (0x1u << 17) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSC_OSCL2 (0x1u << 18) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSC_OSCL3 (0x1u << 19) /**< \brief (PWM_OSC) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_OSSUPD : (PWM Offset: 0x54) PWM Output Selection Set Update Register -------- */ +#define PWM_OSSUPD_OSSUPH0 (0x1u << 0) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 0 */ +#define PWM_OSSUPD_OSSUPH1 (0x1u << 1) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 1 */ +#define PWM_OSSUPD_OSSUPH2 (0x1u << 2) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 2 */ +#define PWM_OSSUPD_OSSUPH3 (0x1u << 3) /**< \brief (PWM_OSSUPD) Output Selection Set for PWMH output of the channel 3 */ +#define PWM_OSSUPD_OSSUPL0 (0x1u << 16) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 0 */ +#define PWM_OSSUPD_OSSUPL1 (0x1u << 17) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 1 */ +#define PWM_OSSUPD_OSSUPL2 (0x1u << 18) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 2 */ +#define PWM_OSSUPD_OSSUPL3 (0x1u << 19) /**< \brief (PWM_OSSUPD) Output Selection Set for PWML output of the channel 3 */ +/* -------- PWM_OSCUPD : (PWM Offset: 0x58) PWM Output Selection Clear Update Register -------- */ +#define PWM_OSCUPD_OSCUPH0 (0x1u << 0) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 0 */ +#define PWM_OSCUPD_OSCUPH1 (0x1u << 1) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 1 */ +#define PWM_OSCUPD_OSCUPH2 (0x1u << 2) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 2 */ +#define PWM_OSCUPD_OSCUPH3 (0x1u << 3) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWMH output of the channel 3 */ +#define PWM_OSCUPD_OSCUPL0 (0x1u << 16) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 0 */ +#define PWM_OSCUPD_OSCUPL1 (0x1u << 17) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 1 */ +#define PWM_OSCUPD_OSCUPL2 (0x1u << 18) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 2 */ +#define PWM_OSCUPD_OSCUPL3 (0x1u << 19) /**< \brief (PWM_OSCUPD) Output Selection Clear for PWML output of the channel 3 */ +/* -------- PWM_FMR : (PWM Offset: 0x5C) PWM Fault Mode Register -------- */ +#define PWM_FMR_FPOL_Pos 0 +#define PWM_FMR_FPOL_Msk (0xffu << PWM_FMR_FPOL_Pos) /**< \brief (PWM_FMR) Fault Polarity */ +#define PWM_FMR_FPOL(value) ((PWM_FMR_FPOL_Msk & ((value) << PWM_FMR_FPOL_Pos))) +#define PWM_FMR_FMOD_Pos 8 +#define PWM_FMR_FMOD_Msk (0xffu << PWM_FMR_FMOD_Pos) /**< \brief (PWM_FMR) Fault Activation Mode */ +#define PWM_FMR_FMOD(value) ((PWM_FMR_FMOD_Msk & ((value) << PWM_FMR_FMOD_Pos))) +#define PWM_FMR_FFIL_Pos 16 +#define PWM_FMR_FFIL_Msk (0xffu << PWM_FMR_FFIL_Pos) /**< \brief (PWM_FMR) Fault Filtering */ +#define PWM_FMR_FFIL(value) ((PWM_FMR_FFIL_Msk & ((value) << PWM_FMR_FFIL_Pos))) +/* -------- PWM_FSR : (PWM Offset: 0x60) PWM Fault Status Register -------- */ +#define PWM_FSR_FIV_Pos 0 +#define PWM_FSR_FIV_Msk (0xffu << PWM_FSR_FIV_Pos) /**< \brief (PWM_FSR) Fault Input Value */ +#define PWM_FSR_FS_Pos 8 +#define PWM_FSR_FS_Msk (0xffu << PWM_FSR_FS_Pos) /**< \brief (PWM_FSR) Fault Status */ +/* -------- PWM_FCR : (PWM Offset: 0x64) PWM Fault Clear Register -------- */ +#define PWM_FCR_FCLR_Pos 0 +#define PWM_FCR_FCLR_Msk (0xffu << PWM_FCR_FCLR_Pos) /**< \brief (PWM_FCR) Fault Clear */ +#define PWM_FCR_FCLR(value) ((PWM_FCR_FCLR_Msk & ((value) << PWM_FCR_FCLR_Pos))) +/* -------- PWM_FPV1 : (PWM Offset: 0x68) PWM Fault Protection Value Register 1 -------- */ +#define PWM_FPV1_FPVH0 (0x1u << 0) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 0 */ +#define PWM_FPV1_FPVH1 (0x1u << 1) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 1 */ +#define PWM_FPV1_FPVH2 (0x1u << 2) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 2 */ +#define PWM_FPV1_FPVH3 (0x1u << 3) /**< \brief (PWM_FPV1) Fault Protection Value for PWMH output on channel 3 */ +#define PWM_FPV1_FPVL0 (0x1u << 16) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 0 */ +#define PWM_FPV1_FPVL1 (0x1u << 17) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 1 */ +#define PWM_FPV1_FPVL2 (0x1u << 18) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 2 */ +#define PWM_FPV1_FPVL3 (0x1u << 19) /**< \brief (PWM_FPV1) Fault Protection Value for PWML output on channel 3 */ +/* -------- PWM_FPE : (PWM Offset: 0x6C) PWM Fault Protection Enable Register -------- */ +#define PWM_FPE_FPE0_Pos 0 +#define PWM_FPE_FPE0_Msk (0xffu << PWM_FPE_FPE0_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 0 */ +#define PWM_FPE_FPE0(value) ((PWM_FPE_FPE0_Msk & ((value) << PWM_FPE_FPE0_Pos))) +#define PWM_FPE_FPE1_Pos 8 +#define PWM_FPE_FPE1_Msk (0xffu << PWM_FPE_FPE1_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 1 */ +#define PWM_FPE_FPE1(value) ((PWM_FPE_FPE1_Msk & ((value) << PWM_FPE_FPE1_Pos))) +#define PWM_FPE_FPE2_Pos 16 +#define PWM_FPE_FPE2_Msk (0xffu << PWM_FPE_FPE2_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 2 */ +#define PWM_FPE_FPE2(value) ((PWM_FPE_FPE2_Msk & ((value) << PWM_FPE_FPE2_Pos))) +#define PWM_FPE_FPE3_Pos 24 +#define PWM_FPE_FPE3_Msk (0xffu << PWM_FPE_FPE3_Pos) /**< \brief (PWM_FPE) Fault Protection Enable for channel 3 */ +#define PWM_FPE_FPE3(value) ((PWM_FPE_FPE3_Msk & ((value) << PWM_FPE_FPE3_Pos))) +/* -------- PWM_ELMR[8] : (PWM Offset: 0x7C) PWM Event Line 0 Mode Register -------- */ +#define PWM_ELMR_CSEL0 (0x1u << 0) /**< \brief (PWM_ELMR[8]) Comparison 0 Selection */ +#define PWM_ELMR_CSEL1 (0x1u << 1) /**< \brief (PWM_ELMR[8]) Comparison 1 Selection */ +#define PWM_ELMR_CSEL2 (0x1u << 2) /**< \brief (PWM_ELMR[8]) Comparison 2 Selection */ +#define PWM_ELMR_CSEL3 (0x1u << 3) /**< \brief (PWM_ELMR[8]) Comparison 3 Selection */ +#define PWM_ELMR_CSEL4 (0x1u << 4) /**< \brief (PWM_ELMR[8]) Comparison 4 Selection */ +#define PWM_ELMR_CSEL5 (0x1u << 5) /**< \brief (PWM_ELMR[8]) Comparison 5 Selection */ +#define PWM_ELMR_CSEL6 (0x1u << 6) /**< \brief (PWM_ELMR[8]) Comparison 6 Selection */ +#define PWM_ELMR_CSEL7 (0x1u << 7) /**< \brief (PWM_ELMR[8]) Comparison 7 Selection */ +/* -------- PWM_SSPR : (PWM Offset: 0xA0) PWM Spread Spectrum Register -------- */ +#define PWM_SSPR_SPRD_Pos 0 +#define PWM_SSPR_SPRD_Msk (0xffffffu << PWM_SSPR_SPRD_Pos) /**< \brief (PWM_SSPR) Spread Spectrum Limit Value */ +#define PWM_SSPR_SPRD(value) ((PWM_SSPR_SPRD_Msk & ((value) << PWM_SSPR_SPRD_Pos))) +#define PWM_SSPR_SPRDM (0x1u << 24) /**< \brief (PWM_SSPR) Spread Spectrum Counter Mode */ +/* -------- PWM_SSPUP : (PWM Offset: 0xA4) PWM Spread Spectrum Update Register -------- */ +#define PWM_SSPUP_SPRDUP_Pos 0 +#define PWM_SSPUP_SPRDUP_Msk (0xffffffu << PWM_SSPUP_SPRDUP_Pos) /**< \brief (PWM_SSPUP) Spread Spectrum Limit Value Update */ +#define PWM_SSPUP_SPRDUP(value) ((PWM_SSPUP_SPRDUP_Msk & ((value) << PWM_SSPUP_SPRDUP_Pos))) +/* -------- PWM_SMMR : (PWM Offset: 0xB0) PWM Stepper Motor Mode Register -------- */ +#define PWM_SMMR_GCEN0 (0x1u << 0) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_GCEN1 (0x1u << 1) /**< \brief (PWM_SMMR) Gray Count ENable */ +#define PWM_SMMR_DOWN0 (0x1u << 16) /**< \brief (PWM_SMMR) DOWN Count */ +#define PWM_SMMR_DOWN1 (0x1u << 17) /**< \brief (PWM_SMMR) DOWN Count */ +/* -------- PWM_FPV2 : (PWM Offset: 0xC0) PWM Fault Protection Value 2 Register -------- */ +#define PWM_FPV2_FPZH0 (0x1u << 0) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 0 */ +#define PWM_FPV2_FPZH1 (0x1u << 1) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 1 */ +#define PWM_FPV2_FPZH2 (0x1u << 2) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 2 */ +#define PWM_FPV2_FPZH3 (0x1u << 3) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWMH output on channel 3 */ +#define PWM_FPV2_FPZL0 (0x1u << 16) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 0 */ +#define PWM_FPV2_FPZL1 (0x1u << 17) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 1 */ +#define PWM_FPV2_FPZL2 (0x1u << 18) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 2 */ +#define PWM_FPV2_FPZL3 (0x1u << 19) /**< \brief (PWM_FPV2) Fault Protection to Hi-Z for PWML output on channel 3 */ +/* -------- PWM_WPCR : (PWM Offset: 0xE4) PWM Write Protection Control Register -------- */ +#define PWM_WPCR_WPCMD_Pos 0 +#define PWM_WPCR_WPCMD_Msk (0x3u << PWM_WPCR_WPCMD_Pos) /**< \brief (PWM_WPCR) Write Protection Command */ +#define PWM_WPCR_WPCMD(value) ((PWM_WPCR_WPCMD_Msk & ((value) << PWM_WPCR_WPCMD_Pos))) +#define PWM_WPCR_WPCMD_DISABLE_SW_PROT (0x0u << 0) /**< \brief (PWM_WPCR) Disables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_SW_PROT (0x1u << 0) /**< \brief (PWM_WPCR) Enables the software write protection of the register groups of which the bit WPRGx is at '1'. */ +#define PWM_WPCR_WPCMD_ENABLE_HW_PROT (0x2u << 0) /**< \brief (PWM_WPCR) Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. */ +#define PWM_WPCR_WPRG0 (0x1u << 2) /**< \brief (PWM_WPCR) Write Protection Register Group 0 */ +#define PWM_WPCR_WPRG1 (0x1u << 3) /**< \brief (PWM_WPCR) Write Protection Register Group 1 */ +#define PWM_WPCR_WPRG2 (0x1u << 4) /**< \brief (PWM_WPCR) Write Protection Register Group 2 */ +#define PWM_WPCR_WPRG3 (0x1u << 5) /**< \brief (PWM_WPCR) Write Protection Register Group 3 */ +#define PWM_WPCR_WPRG4 (0x1u << 6) /**< \brief (PWM_WPCR) Write Protection Register Group 4 */ +#define PWM_WPCR_WPRG5 (0x1u << 7) /**< \brief (PWM_WPCR) Write Protection Register Group 5 */ +#define PWM_WPCR_WPKEY_Pos 8 +#define PWM_WPCR_WPKEY_Msk (0xffffffu << PWM_WPCR_WPKEY_Pos) /**< \brief (PWM_WPCR) Write Protection Key */ +#define PWM_WPCR_WPKEY(value) ((PWM_WPCR_WPKEY_Msk & ((value) << PWM_WPCR_WPKEY_Pos))) +#define PWM_WPCR_WPKEY_PASSWD (0x50574Du << 8) /**< \brief (PWM_WPCR) Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 */ +/* -------- PWM_WPSR : (PWM Offset: 0xE8) PWM Write Protection Status Register -------- */ +#define PWM_WPSR_WPSWS0 (0x1u << 0) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS1 (0x1u << 1) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS2 (0x1u << 2) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS3 (0x1u << 3) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS4 (0x1u << 4) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPSWS5 (0x1u << 5) /**< \brief (PWM_WPSR) Write Protect SW Status */ +#define PWM_WPSR_WPVS (0x1u << 7) /**< \brief (PWM_WPSR) Write Protect Violation Status */ +#define PWM_WPSR_WPHWS0 (0x1u << 8) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS1 (0x1u << 9) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS2 (0x1u << 10) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS3 (0x1u << 11) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS4 (0x1u << 12) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPHWS5 (0x1u << 13) /**< \brief (PWM_WPSR) Write Protect HW Status */ +#define PWM_WPSR_WPVSRC_Pos 16 +#define PWM_WPSR_WPVSRC_Msk (0xffffu << PWM_WPSR_WPVSRC_Pos) /**< \brief (PWM_WPSR) Write Protect Violation Source */ +/* -------- PWM_CMPV : (PWM Offset: N/A) PWM Comparison 0 Value Register -------- */ +#define PWM_CMPV_CV_Pos 0 +#define PWM_CMPV_CV_Msk (0xffffffu << PWM_CMPV_CV_Pos) /**< \brief (PWM_CMPV) Comparison x Value */ +#define PWM_CMPV_CV(value) ((PWM_CMPV_CV_Msk & ((value) << PWM_CMPV_CV_Pos))) +#define PWM_CMPV_CVM (0x1u << 24) /**< \brief (PWM_CMPV) Comparison x Value Mode */ +/* -------- PWM_CMPVUPD : (PWM Offset: N/A) PWM Comparison 0 Value Update Register -------- */ +#define PWM_CMPVUPD_CVUPD_Pos 0 +#define PWM_CMPVUPD_CVUPD_Msk (0xffffffu << PWM_CMPVUPD_CVUPD_Pos) /**< \brief (PWM_CMPVUPD) Comparison x Value Update */ +#define PWM_CMPVUPD_CVUPD(value) ((PWM_CMPVUPD_CVUPD_Msk & ((value) << PWM_CMPVUPD_CVUPD_Pos))) +#define PWM_CMPVUPD_CVMUPD (0x1u << 24) /**< \brief (PWM_CMPVUPD) Comparison x Value Mode Update */ +/* -------- PWM_CMPM : (PWM Offset: N/A) PWM Comparison 0 Mode Register -------- */ +#define PWM_CMPM_CEN (0x1u << 0) /**< \brief (PWM_CMPM) Comparison x Enable */ +#define PWM_CMPM_CTR_Pos 4 +#define PWM_CMPM_CTR_Msk (0xfu << PWM_CMPM_CTR_Pos) /**< \brief (PWM_CMPM) Comparison x Trigger */ +#define PWM_CMPM_CTR(value) ((PWM_CMPM_CTR_Msk & ((value) << PWM_CMPM_CTR_Pos))) +#define PWM_CMPM_CPR_Pos 8 +#define PWM_CMPM_CPR_Msk (0xfu << PWM_CMPM_CPR_Pos) /**< \brief (PWM_CMPM) Comparison x Period */ +#define PWM_CMPM_CPR(value) ((PWM_CMPM_CPR_Msk & ((value) << PWM_CMPM_CPR_Pos))) +#define PWM_CMPM_CPRCNT_Pos 12 +#define PWM_CMPM_CPRCNT_Msk (0xfu << PWM_CMPM_CPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Period Counter */ +#define PWM_CMPM_CPRCNT(value) ((PWM_CMPM_CPRCNT_Msk & ((value) << PWM_CMPM_CPRCNT_Pos))) +#define PWM_CMPM_CUPR_Pos 16 +#define PWM_CMPM_CUPR_Msk (0xfu << PWM_CMPM_CUPR_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period */ +#define PWM_CMPM_CUPR(value) ((PWM_CMPM_CUPR_Msk & ((value) << PWM_CMPM_CUPR_Pos))) +#define PWM_CMPM_CUPRCNT_Pos 20 +#define PWM_CMPM_CUPRCNT_Msk (0xfu << PWM_CMPM_CUPRCNT_Pos) /**< \brief (PWM_CMPM) Comparison x Update Period Counter */ +#define PWM_CMPM_CUPRCNT(value) ((PWM_CMPM_CUPRCNT_Msk & ((value) << PWM_CMPM_CUPRCNT_Pos))) +/* -------- PWM_CMPMUPD : (PWM Offset: N/A) PWM Comparison 0 Mode Update Register -------- */ +#define PWM_CMPMUPD_CENUPD (0x1u << 0) /**< \brief (PWM_CMPMUPD) Comparison x Enable Update */ +#define PWM_CMPMUPD_CTRUPD_Pos 4 +#define PWM_CMPMUPD_CTRUPD_Msk (0xfu << PWM_CMPMUPD_CTRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Trigger Update */ +#define PWM_CMPMUPD_CTRUPD(value) ((PWM_CMPMUPD_CTRUPD_Msk & ((value) << PWM_CMPMUPD_CTRUPD_Pos))) +#define PWM_CMPMUPD_CPRUPD_Pos 8 +#define PWM_CMPMUPD_CPRUPD_Msk (0xfu << PWM_CMPMUPD_CPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Period Update */ +#define PWM_CMPMUPD_CPRUPD(value) ((PWM_CMPMUPD_CPRUPD_Msk & ((value) << PWM_CMPMUPD_CPRUPD_Pos))) +#define PWM_CMPMUPD_CUPRUPD_Pos 16 +#define PWM_CMPMUPD_CUPRUPD_Msk (0xfu << PWM_CMPMUPD_CUPRUPD_Pos) /**< \brief (PWM_CMPMUPD) Comparison x Update Period Update */ +#define PWM_CMPMUPD_CUPRUPD(value) ((PWM_CMPMUPD_CUPRUPD_Msk & ((value) << PWM_CMPMUPD_CUPRUPD_Pos))) +/* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ +#define PWM_CMR_CPRE_Pos 0 +#define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /**< \brief (PWM_CMR) Channel Pre-scaler */ +#define PWM_CMR_CPRE(value) ((PWM_CMR_CPRE_Msk & ((value) << PWM_CMR_CPRE_Pos))) +#define PWM_CMR_CPRE_MCK (0x0u << 0) /**< \brief (PWM_CMR) Peripheral clock */ +#define PWM_CMR_CPRE_MCK_DIV_2 (0x1u << 0) /**< \brief (PWM_CMR) Peripheral clock/2 */ +#define PWM_CMR_CPRE_MCK_DIV_4 (0x2u << 0) /**< \brief (PWM_CMR) Peripheral clock/4 */ +#define PWM_CMR_CPRE_MCK_DIV_8 (0x3u << 0) /**< \brief (PWM_CMR) Peripheral clock/8 */ +#define PWM_CMR_CPRE_MCK_DIV_16 (0x4u << 0) /**< \brief (PWM_CMR) Peripheral clock/16 */ +#define PWM_CMR_CPRE_MCK_DIV_32 (0x5u << 0) /**< \brief (PWM_CMR) Peripheral clock/32 */ +#define PWM_CMR_CPRE_MCK_DIV_64 (0x6u << 0) /**< \brief (PWM_CMR) Peripheral clock/64 */ +#define PWM_CMR_CPRE_MCK_DIV_128 (0x7u << 0) /**< \brief (PWM_CMR) Peripheral clock/128 */ +#define PWM_CMR_CPRE_MCK_DIV_256 (0x8u << 0) /**< \brief (PWM_CMR) Peripheral clock/256 */ +#define PWM_CMR_CPRE_MCK_DIV_512 (0x9u << 0) /**< \brief (PWM_CMR) Peripheral clock/512 */ +#define PWM_CMR_CPRE_MCK_DIV_1024 (0xAu << 0) /**< \brief (PWM_CMR) Peripheral clock/1024 */ +#define PWM_CMR_CPRE_CLKA (0xBu << 0) /**< \brief (PWM_CMR) Clock A */ +#define PWM_CMR_CPRE_CLKB (0xCu << 0) /**< \brief (PWM_CMR) Clock B */ +#define PWM_CMR_CALG (0x1u << 8) /**< \brief (PWM_CMR) Channel Alignment */ +#define PWM_CMR_CPOL (0x1u << 9) /**< \brief (PWM_CMR) Channel Polarity */ +#define PWM_CMR_CES (0x1u << 10) /**< \brief (PWM_CMR) Counter Event Selection */ +#define PWM_CMR_UPDS (0x1u << 11) /**< \brief (PWM_CMR) Update Selection */ +#define PWM_CMR_DPOLI (0x1u << 12) /**< \brief (PWM_CMR) Disabled Polarity Inverted */ +#define PWM_CMR_TCTS (0x1u << 13) /**< \brief (PWM_CMR) Timer Counter Trigger Selection */ +#define PWM_CMR_DTE (0x1u << 16) /**< \brief (PWM_CMR) Dead-Time Generator Enable */ +#define PWM_CMR_DTHI (0x1u << 17) /**< \brief (PWM_CMR) Dead-Time PWMHx Output Inverted */ +#define PWM_CMR_DTLI (0x1u << 18) /**< \brief (PWM_CMR) Dead-Time PWMLx Output Inverted */ +#define PWM_CMR_PPM (0x1u << 19) /**< \brief (PWM_CMR) Push-Pull Mode */ +/* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ +#define PWM_CDTY_CDTY_Pos 0 +#define PWM_CDTY_CDTY_Msk (0xffffffu << PWM_CDTY_CDTY_Pos) /**< \brief (PWM_CDTY) Channel Duty-Cycle */ +#define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) +/* -------- PWM_CDTYUPD : (PWM Offset: N/A) PWM Channel Duty Cycle Update Register -------- */ +#define PWM_CDTYUPD_CDTYUPD_Pos 0 +#define PWM_CDTYUPD_CDTYUPD_Msk (0xffffffu << PWM_CDTYUPD_CDTYUPD_Pos) /**< \brief (PWM_CDTYUPD) Channel Duty-Cycle Update */ +#define PWM_CDTYUPD_CDTYUPD(value) ((PWM_CDTYUPD_CDTYUPD_Msk & ((value) << PWM_CDTYUPD_CDTYUPD_Pos))) +/* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ +#define PWM_CPRD_CPRD_Pos 0 +#define PWM_CPRD_CPRD_Msk (0xffffffu << PWM_CPRD_CPRD_Pos) /**< \brief (PWM_CPRD) Channel Period */ +#define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) +/* -------- PWM_CPRDUPD : (PWM Offset: N/A) PWM Channel Period Update Register -------- */ +#define PWM_CPRDUPD_CPRDUPD_Pos 0 +#define PWM_CPRDUPD_CPRDUPD_Msk (0xffffffu << PWM_CPRDUPD_CPRDUPD_Pos) /**< \brief (PWM_CPRDUPD) Channel Period Update */ +#define PWM_CPRDUPD_CPRDUPD(value) ((PWM_CPRDUPD_CPRDUPD_Msk & ((value) << PWM_CPRDUPD_CPRDUPD_Pos))) +/* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ +#define PWM_CCNT_CNT_Pos 0 +#define PWM_CCNT_CNT_Msk (0xffffffu << PWM_CCNT_CNT_Pos) /**< \brief (PWM_CCNT) Channel Counter Register */ +/* -------- PWM_DT : (PWM Offset: N/A) PWM Channel Dead Time Register -------- */ +#define PWM_DT_DTH_Pos 0 +#define PWM_DT_DTH_Msk (0xffffu << PWM_DT_DTH_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMHx Output */ +#define PWM_DT_DTH(value) ((PWM_DT_DTH_Msk & ((value) << PWM_DT_DTH_Pos))) +#define PWM_DT_DTL_Pos 16 +#define PWM_DT_DTL_Msk (0xffffu << PWM_DT_DTL_Pos) /**< \brief (PWM_DT) Dead-Time Value for PWMLx Output */ +#define PWM_DT_DTL(value) ((PWM_DT_DTL_Msk & ((value) << PWM_DT_DTL_Pos))) +/* -------- PWM_DTUPD : (PWM Offset: N/A) PWM Channel Dead Time Update Register -------- */ +#define PWM_DTUPD_DTHUPD_Pos 0 +#define PWM_DTUPD_DTHUPD_Msk (0xffffu << PWM_DTUPD_DTHUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMHx Output */ +#define PWM_DTUPD_DTHUPD(value) ((PWM_DTUPD_DTHUPD_Msk & ((value) << PWM_DTUPD_DTHUPD_Pos))) +#define PWM_DTUPD_DTLUPD_Pos 16 +#define PWM_DTUPD_DTLUPD_Msk (0xffffu << PWM_DTUPD_DTLUPD_Pos) /**< \brief (PWM_DTUPD) Dead-Time Value Update for PWMLx Output */ +#define PWM_DTUPD_DTLUPD(value) ((PWM_DTUPD_DTLUPD_Msk & ((value) << PWM_DTUPD_DTLUPD_Pos))) +/* -------- PWM_CMUPD0 : (PWM Offset: 0x400) PWM Channel Mode Update Register (ch_num = 0) -------- */ +#define PWM_CMUPD0_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD0) Channel Polarity Update */ +#define PWM_CMUPD0_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD0) Channel Polarity Inversion Update */ +/* -------- PWM_CMUPD1 : (PWM Offset: 0x420) PWM Channel Mode Update Register (ch_num = 1) -------- */ +#define PWM_CMUPD1_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD1) Channel Polarity Update */ +#define PWM_CMUPD1_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD1) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG1 : (PWM Offset: 0x42C) PWM External Trigger Register (trg_num = 1) -------- */ +#define PWM_ETRG1_MAXCNT_Pos 0 +#define PWM_ETRG1_MAXCNT_Msk (0xffffffu << PWM_ETRG1_MAXCNT_Pos) /**< \brief (PWM_ETRG1) Maximum Counter value */ +#define PWM_ETRG1_MAXCNT(value) ((PWM_ETRG1_MAXCNT_Msk & ((value) << PWM_ETRG1_MAXCNT_Pos))) +#define PWM_ETRG1_TRGMODE_Pos 24 +#define PWM_ETRG1_TRGMODE_Msk (0x3u << PWM_ETRG1_TRGMODE_Pos) /**< \brief (PWM_ETRG1) External Trigger Mode */ +#define PWM_ETRG1_TRGMODE(value) ((PWM_ETRG1_TRGMODE_Msk & ((value) << PWM_ETRG1_TRGMODE_Pos))) +#define PWM_ETRG1_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG1) External trigger is not enabled. */ +#define PWM_ETRG1_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG1) External PWM Reset Mode */ +#define PWM_ETRG1_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG1) External PWM Start Mode */ +#define PWM_ETRG1_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG1) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG1_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG1) Edge Selection */ +#define PWM_ETRG1_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG1_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG1) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG1_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG1) Filtered input */ +#define PWM_ETRG1_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG1) Trigger Source */ +#define PWM_ETRG1_RFEN (0x1u << 31) /**< \brief (PWM_ETRG1) Recoverable Fault Enable */ +/* -------- PWM_LEBR1 : (PWM Offset: 0x430) PWM Leading-Edge Blanking Register (trg_num = 1) -------- */ +#define PWM_LEBR1_LEBDELAY_Pos 0 +#define PWM_LEBR1_LEBDELAY_Msk (0x7fu << PWM_LEBR1_LEBDELAY_Pos) /**< \brief (PWM_LEBR1) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR1_LEBDELAY(value) ((PWM_LEBR1_LEBDELAY_Msk & ((value) << PWM_LEBR1_LEBDELAY_Pos))) +#define PWM_LEBR1_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR1) PWML Falling Edge Enable */ +#define PWM_LEBR1_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR1) PWML Rising Edge Enable */ +#define PWM_LEBR1_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR1) PWMH Falling Edge Enable */ +#define PWM_LEBR1_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR1) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD2 : (PWM Offset: 0x440) PWM Channel Mode Update Register (ch_num = 2) -------- */ +#define PWM_CMUPD2_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD2) Channel Polarity Update */ +#define PWM_CMUPD2_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD2) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG2 : (PWM Offset: 0x44C) PWM External Trigger Register (trg_num = 2) -------- */ +#define PWM_ETRG2_MAXCNT_Pos 0 +#define PWM_ETRG2_MAXCNT_Msk (0xffffffu << PWM_ETRG2_MAXCNT_Pos) /**< \brief (PWM_ETRG2) Maximum Counter value */ +#define PWM_ETRG2_MAXCNT(value) ((PWM_ETRG2_MAXCNT_Msk & ((value) << PWM_ETRG2_MAXCNT_Pos))) +#define PWM_ETRG2_TRGMODE_Pos 24 +#define PWM_ETRG2_TRGMODE_Msk (0x3u << PWM_ETRG2_TRGMODE_Pos) /**< \brief (PWM_ETRG2) External Trigger Mode */ +#define PWM_ETRG2_TRGMODE(value) ((PWM_ETRG2_TRGMODE_Msk & ((value) << PWM_ETRG2_TRGMODE_Pos))) +#define PWM_ETRG2_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG2) External trigger is not enabled. */ +#define PWM_ETRG2_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG2) External PWM Reset Mode */ +#define PWM_ETRG2_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG2) External PWM Start Mode */ +#define PWM_ETRG2_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG2) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG2_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG2) Edge Selection */ +#define PWM_ETRG2_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG2_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG2) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG2_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG2) Filtered input */ +#define PWM_ETRG2_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG2) Trigger Source */ +#define PWM_ETRG2_RFEN (0x1u << 31) /**< \brief (PWM_ETRG2) Recoverable Fault Enable */ +/* -------- PWM_LEBR2 : (PWM Offset: 0x450) PWM Leading-Edge Blanking Register (trg_num = 2) -------- */ +#define PWM_LEBR2_LEBDELAY_Pos 0 +#define PWM_LEBR2_LEBDELAY_Msk (0x7fu << PWM_LEBR2_LEBDELAY_Pos) /**< \brief (PWM_LEBR2) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR2_LEBDELAY(value) ((PWM_LEBR2_LEBDELAY_Msk & ((value) << PWM_LEBR2_LEBDELAY_Pos))) +#define PWM_LEBR2_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR2) PWML Falling Edge Enable */ +#define PWM_LEBR2_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR2) PWML Rising Edge Enable */ +#define PWM_LEBR2_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR2) PWMH Falling Edge Enable */ +#define PWM_LEBR2_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR2) PWMH Rising Edge Enable */ +/* -------- PWM_CMUPD3 : (PWM Offset: 0x460) PWM Channel Mode Update Register (ch_num = 3) -------- */ +#define PWM_CMUPD3_CPOLUP (0x1u << 9) /**< \brief (PWM_CMUPD3) Channel Polarity Update */ +#define PWM_CMUPD3_CPOLINVUP (0x1u << 13) /**< \brief (PWM_CMUPD3) Channel Polarity Inversion Update */ +/* -------- PWM_ETRG3 : (PWM Offset: 0x46C) PWM External Trigger Register (trg_num = 3) -------- */ +#define PWM_ETRG3_MAXCNT_Pos 0 +#define PWM_ETRG3_MAXCNT_Msk (0xffffffu << PWM_ETRG3_MAXCNT_Pos) /**< \brief (PWM_ETRG3) Maximum Counter value */ +#define PWM_ETRG3_MAXCNT(value) ((PWM_ETRG3_MAXCNT_Msk & ((value) << PWM_ETRG3_MAXCNT_Pos))) +#define PWM_ETRG3_TRGMODE_Pos 24 +#define PWM_ETRG3_TRGMODE_Msk (0x3u << PWM_ETRG3_TRGMODE_Pos) /**< \brief (PWM_ETRG3) External Trigger Mode */ +#define PWM_ETRG3_TRGMODE(value) ((PWM_ETRG3_TRGMODE_Msk & ((value) << PWM_ETRG3_TRGMODE_Pos))) +#define PWM_ETRG3_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG3) External trigger is not enabled. */ +#define PWM_ETRG3_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG3) External PWM Reset Mode */ +#define PWM_ETRG3_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG3) External PWM Start Mode */ +#define PWM_ETRG3_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG3) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG3_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG3) Edge Selection */ +#define PWM_ETRG3_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG3_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG3) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG3_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG3) Filtered input */ +#define PWM_ETRG3_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG3) Trigger Source */ +#define PWM_ETRG3_RFEN (0x1u << 31) /**< \brief (PWM_ETRG3) Recoverable Fault Enable */ +/* -------- PWM_LEBR3 : (PWM Offset: 0x470) PWM Leading-Edge Blanking Register (trg_num = 3) -------- */ +#define PWM_LEBR3_LEBDELAY_Pos 0 +#define PWM_LEBR3_LEBDELAY_Msk (0x7fu << PWM_LEBR3_LEBDELAY_Pos) /**< \brief (PWM_LEBR3) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR3_LEBDELAY(value) ((PWM_LEBR3_LEBDELAY_Msk & ((value) << PWM_LEBR3_LEBDELAY_Pos))) +#define PWM_LEBR3_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR3) PWML Falling Edge Enable */ +#define PWM_LEBR3_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR3) PWML Rising Edge Enable */ +#define PWM_LEBR3_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR3) PWMH Falling Edge Enable */ +#define PWM_LEBR3_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR3) PWMH Rising Edge Enable */ +/* -------- PWM_ETRG4 : (PWM Offset: 0x48C) PWM External Trigger Register (trg_num = 4) -------- */ +#define PWM_ETRG4_MAXCNT_Pos 0 +#define PWM_ETRG4_MAXCNT_Msk (0xffffffu << PWM_ETRG4_MAXCNT_Pos) /**< \brief (PWM_ETRG4) Maximum Counter value */ +#define PWM_ETRG4_MAXCNT(value) ((PWM_ETRG4_MAXCNT_Msk & ((value) << PWM_ETRG4_MAXCNT_Pos))) +#define PWM_ETRG4_TRGMODE_Pos 24 +#define PWM_ETRG4_TRGMODE_Msk (0x3u << PWM_ETRG4_TRGMODE_Pos) /**< \brief (PWM_ETRG4) External Trigger Mode */ +#define PWM_ETRG4_TRGMODE(value) ((PWM_ETRG4_TRGMODE_Msk & ((value) << PWM_ETRG4_TRGMODE_Pos))) +#define PWM_ETRG4_TRGMODE_OFF (0x0u << 24) /**< \brief (PWM_ETRG4) External trigger is not enabled. */ +#define PWM_ETRG4_TRGMODE_MODE1 (0x1u << 24) /**< \brief (PWM_ETRG4) External PWM Reset Mode */ +#define PWM_ETRG4_TRGMODE_MODE2 (0x2u << 24) /**< \brief (PWM_ETRG4) External PWM Start Mode */ +#define PWM_ETRG4_TRGMODE_MODE3 (0x3u << 24) /**< \brief (PWM_ETRG4) Cycle-by-cycle Duty Mode */ +#define PWM_ETRG4_TRGEDGE (0x1u << 28) /**< \brief (PWM_ETRG4) Edge Selection */ +#define PWM_ETRG4_TRGEDGE_FALLING_ZERO (0x0u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 */ +#define PWM_ETRG4_TRGEDGE_RISING_ONE (0x1u << 28) /**< \brief (PWM_ETRG4) TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 */ +#define PWM_ETRG4_TRGFILT (0x1u << 29) /**< \brief (PWM_ETRG4) Filtered input */ +#define PWM_ETRG4_TRGSRC (0x1u << 30) /**< \brief (PWM_ETRG4) Trigger Source */ +#define PWM_ETRG4_RFEN (0x1u << 31) /**< \brief (PWM_ETRG4) Recoverable Fault Enable */ +/* -------- PWM_LEBR4 : (PWM Offset: 0x490) PWM Leading-Edge Blanking Register (trg_num = 4) -------- */ +#define PWM_LEBR4_LEBDELAY_Pos 0 +#define PWM_LEBR4_LEBDELAY_Msk (0x7fu << PWM_LEBR4_LEBDELAY_Pos) /**< \brief (PWM_LEBR4) Leading-Edge Blanking Delay for TRGINx */ +#define PWM_LEBR4_LEBDELAY(value) ((PWM_LEBR4_LEBDELAY_Msk & ((value) << PWM_LEBR4_LEBDELAY_Pos))) +#define PWM_LEBR4_PWMLFEN (0x1u << 16) /**< \brief (PWM_LEBR4) PWML Falling Edge Enable */ +#define PWM_LEBR4_PWMLREN (0x1u << 17) /**< \brief (PWM_LEBR4) PWML Rising Edge Enable */ +#define PWM_LEBR4_PWMHFEN (0x1u << 18) /**< \brief (PWM_LEBR4) PWMH Falling Edge Enable */ +#define PWM_LEBR4_PWMHREN (0x1u << 19) /**< \brief (PWM_LEBR4) PWMH Rising Edge Enable */ + +/*@}*/ + + +#endif /* _SAMV71_PWM_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_qspi.h new file mode 100644 index 000000000..ff5df2c3f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_qspi.h @@ -0,0 +1,223 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_QSPI_COMPONENT_ +#define _SAMV71_QSPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Quad Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_QSPI Quad Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Qspi hardware registers */ +typedef struct { + __O uint32_t QSPI_CR; /**< \brief (Qspi Offset: 0x00) Control Register */ + __IO uint32_t QSPI_MR; /**< \brief (Qspi Offset: 0x04) Mode Register */ + __I uint32_t QSPI_RDR; /**< \brief (Qspi Offset: 0x08) Receive Data Register */ + __O uint32_t QSPI_TDR; /**< \brief (Qspi Offset: 0x0C) Transmit Data Register */ + __I uint32_t QSPI_SR; /**< \brief (Qspi Offset: 0x10) Status Register */ + __O uint32_t QSPI_IER; /**< \brief (Qspi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t QSPI_IDR; /**< \brief (Qspi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t QSPI_IMR; /**< \brief (Qspi Offset: 0x1C) Interrupt Mask Register */ + __IO uint32_t QSPI_SCR; /**< \brief (Qspi Offset: 0x20) Serial Clock Register */ + __I uint32_t Reserved1[3]; + __IO uint32_t QSPI_IAR; /**< \brief (Qspi Offset: 0x30) Instruction Address Register */ + __IO uint32_t QSPI_ICR; /**< \brief (Qspi Offset: 0x34) Instruction Code Register */ + __IO uint32_t QSPI_IFR; /**< \brief (Qspi Offset: 0x38) Instruction Frame Register */ + __I uint32_t Reserved2[1]; + __IO uint32_t QSPI_SMR; /**< \brief (Qspi Offset: 0x40) Scrambling Mode Register */ + __O uint32_t QSPI_SKR; /**< \brief (Qspi Offset: 0x44) Scrambling Key Register */ + __I uint32_t Reserved3[39]; + __IO uint32_t QSPI_WPMR; /**< \brief (Qspi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t QSPI_WPSR; /**< \brief (Qspi Offset: 0xE8) Write Protection Status Register */ +} Qspi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- QSPI_CR : (QSPI Offset: 0x00) Control Register -------- */ +#define QSPI_CR_QSPIEN (0x1u << 0) /**< \brief (QSPI_CR) QSPI Enable */ +#define QSPI_CR_QSPIDIS (0x1u << 1) /**< \brief (QSPI_CR) QSPI Disable */ +#define QSPI_CR_SWRST (0x1u << 7) /**< \brief (QSPI_CR) QSPI Software Reset */ +#define QSPI_CR_LASTXFER (0x1u << 24) /**< \brief (QSPI_CR) Last Transfer */ +/* -------- QSPI_MR : (QSPI Offset: 0x04) Mode Register -------- */ +#define QSPI_MR_SMM (0x1u << 0) /**< \brief (QSPI_MR) Serial Memory Mode */ +#define QSPI_MR_SMM_SPI (0x0u << 0) /**< \brief (QSPI_MR) The QSPI is in SPI mode. */ +#define QSPI_MR_SMM_MEMORY (0x1u << 0) /**< \brief (QSPI_MR) The QSPI is in Serial Memory mode. */ +#define QSPI_MR_LLB (0x1u << 1) /**< \brief (QSPI_MR) Local Loopback Enable */ +#define QSPI_MR_LLB_DISABLED (0x0u << 1) /**< \brief (QSPI_MR) Local loopback path disabled. */ +#define QSPI_MR_LLB_ENABLED (0x1u << 1) /**< \brief (QSPI_MR) Local loopback path enabled. */ +#define QSPI_MR_WDRBT (0x1u << 2) /**< \brief (QSPI_MR) Wait Data Read Before Transfer */ +#define QSPI_MR_WDRBT_DISABLED (0x0u << 2) /**< \brief (QSPI_MR) No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. */ +#define QSPI_MR_WDRBT_ENABLED (0x1u << 2) /**< \brief (QSPI_MR) In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. */ +#define QSPI_MR_CSMODE_Pos 4 +#define QSPI_MR_CSMODE_Msk (0x3u << QSPI_MR_CSMODE_Pos) /**< \brief (QSPI_MR) Chip Select Mode */ +#define QSPI_MR_CSMODE(value) ((QSPI_MR_CSMODE_Msk & ((value) << QSPI_MR_CSMODE_Pos))) +#define QSPI_MR_CSMODE_NOT_RELOADED (0x0u << 4) /**< \brief (QSPI_MR) The chip select is deasserted if TD has not been reloaded before the end of the current transfer. */ +#define QSPI_MR_CSMODE_LASTXFER (0x1u << 4) /**< \brief (QSPI_MR) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. */ +#define QSPI_MR_CSMODE_SYSTEMATICALLY (0x2u << 4) /**< \brief (QSPI_MR) The chip select is deasserted systematically after each transfer. */ +#define QSPI_MR_NBBITS_Pos 8 +#define QSPI_MR_NBBITS_Msk (0xfu << QSPI_MR_NBBITS_Pos) /**< \brief (QSPI_MR) Number Of Bits Per Transfer */ +#define QSPI_MR_NBBITS(value) ((QSPI_MR_NBBITS_Msk & ((value) << QSPI_MR_NBBITS_Pos))) +#define QSPI_MR_NBBITS_8_BIT (0x0u << 8) /**< \brief (QSPI_MR) 8 bits for transfer */ +#define QSPI_MR_NBBITS_9_BIT (0x1u << 8) /**< \brief (QSPI_MR) 9 bits for transfer */ +#define QSPI_MR_NBBITS_10_BIT (0x2u << 8) /**< \brief (QSPI_MR) 10 bits for transfer */ +#define QSPI_MR_NBBITS_11_BIT (0x3u << 8) /**< \brief (QSPI_MR) 11 bits for transfer */ +#define QSPI_MR_NBBITS_12_BIT (0x4u << 8) /**< \brief (QSPI_MR) 12 bits for transfer */ +#define QSPI_MR_NBBITS_13_BIT (0x5u << 8) /**< \brief (QSPI_MR) 13 bits for transfer */ +#define QSPI_MR_NBBITS_14_BIT (0x6u << 8) /**< \brief (QSPI_MR) 14 bits for transfer */ +#define QSPI_MR_NBBITS_15_BIT (0x7u << 8) /**< \brief (QSPI_MR) 15 bits for transfer */ +#define QSPI_MR_NBBITS_16_BIT (0x8u << 8) /**< \brief (QSPI_MR) 16 bits for transfer */ +#define QSPI_MR_DLYBCT_Pos 16 +#define QSPI_MR_DLYBCT_Msk (0xffu << QSPI_MR_DLYBCT_Pos) /**< \brief (QSPI_MR) Delay Between Consecutive Transfers */ +#define QSPI_MR_DLYBCT(value) ((QSPI_MR_DLYBCT_Msk & ((value) << QSPI_MR_DLYBCT_Pos))) +#define QSPI_MR_DLYCS_Pos 24 +#define QSPI_MR_DLYCS_Msk (0xffu << QSPI_MR_DLYCS_Pos) /**< \brief (QSPI_MR) Minimum Inactive QCS Delay */ +#define QSPI_MR_DLYCS(value) ((QSPI_MR_DLYCS_Msk & ((value) << QSPI_MR_DLYCS_Pos))) +/* -------- QSPI_RDR : (QSPI Offset: 0x08) Receive Data Register -------- */ +#define QSPI_RDR_RD_Pos 0 +#define QSPI_RDR_RD_Msk (0xffffu << QSPI_RDR_RD_Pos) /**< \brief (QSPI_RDR) Receive Data */ +/* -------- QSPI_TDR : (QSPI Offset: 0x0C) Transmit Data Register -------- */ +#define QSPI_TDR_TD_Pos 0 +#define QSPI_TDR_TD_Msk (0xffffu << QSPI_TDR_TD_Pos) /**< \brief (QSPI_TDR) Transmit Data */ +#define QSPI_TDR_TD(value) ((QSPI_TDR_TD_Msk & ((value) << QSPI_TDR_TD_Pos))) +/* -------- QSPI_SR : (QSPI Offset: 0x10) Status Register -------- */ +#define QSPI_SR_RDRF (0x1u << 0) /**< \brief (QSPI_SR) Receive Data Register Full */ +#define QSPI_SR_TDRE (0x1u << 1) /**< \brief (QSPI_SR) Transmit Data Register Empty */ +#define QSPI_SR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_SR) Transmission Registers Empty */ +#define QSPI_SR_OVRES (0x1u << 3) /**< \brief (QSPI_SR) Overrun Error Status */ +#define QSPI_SR_CSR (0x1u << 8) /**< \brief (QSPI_SR) Chip Select Rise */ +#define QSPI_SR_CSS (0x1u << 9) /**< \brief (QSPI_SR) Chip Select Status */ +#define QSPI_SR_INSTRE (0x1u << 10) /**< \brief (QSPI_SR) Instruction End Status */ +#define QSPI_SR_QSPIENS (0x1u << 24) /**< \brief (QSPI_SR) QSPI Enable Status */ +/* -------- QSPI_IER : (QSPI Offset: 0x14) Interrupt Enable Register -------- */ +#define QSPI_IER_RDRF (0x1u << 0) /**< \brief (QSPI_IER) Receive Data Register Full Interrupt Enable */ +#define QSPI_IER_TDRE (0x1u << 1) /**< \brief (QSPI_IER) Transmit Data Register Empty Interrupt Enable */ +#define QSPI_IER_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IER) Transmission Registers Empty Enable */ +#define QSPI_IER_OVRES (0x1u << 3) /**< \brief (QSPI_IER) Overrun Error Interrupt Enable */ +#define QSPI_IER_CSR (0x1u << 8) /**< \brief (QSPI_IER) Chip Select Rise Interrupt Enable */ +#define QSPI_IER_CSS (0x1u << 9) /**< \brief (QSPI_IER) Chip Select Status Interrupt Enable */ +#define QSPI_IER_INSTRE (0x1u << 10) /**< \brief (QSPI_IER) Instruction End Interrupt Enable */ +/* -------- QSPI_IDR : (QSPI Offset: 0x18) Interrupt Disable Register -------- */ +#define QSPI_IDR_RDRF (0x1u << 0) /**< \brief (QSPI_IDR) Receive Data Register Full Interrupt Disable */ +#define QSPI_IDR_TDRE (0x1u << 1) /**< \brief (QSPI_IDR) Transmit Data Register Empty Interrupt Disable */ +#define QSPI_IDR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IDR) Transmission Registers Empty Disable */ +#define QSPI_IDR_OVRES (0x1u << 3) /**< \brief (QSPI_IDR) Overrun Error Interrupt Disable */ +#define QSPI_IDR_CSR (0x1u << 8) /**< \brief (QSPI_IDR) Chip Select Rise Interrupt Disable */ +#define QSPI_IDR_CSS (0x1u << 9) /**< \brief (QSPI_IDR) Chip Select Status Interrupt Disable */ +#define QSPI_IDR_INSTRE (0x1u << 10) /**< \brief (QSPI_IDR) Instruction End Interrupt Disable */ +/* -------- QSPI_IMR : (QSPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define QSPI_IMR_RDRF (0x1u << 0) /**< \brief (QSPI_IMR) Receive Data Register Full Interrupt Mask */ +#define QSPI_IMR_TDRE (0x1u << 1) /**< \brief (QSPI_IMR) Transmit Data Register Empty Interrupt Mask */ +#define QSPI_IMR_TXEMPTY (0x1u << 2) /**< \brief (QSPI_IMR) Transmission Registers Empty Mask */ +#define QSPI_IMR_OVRES (0x1u << 3) /**< \brief (QSPI_IMR) Overrun Error Interrupt Mask */ +#define QSPI_IMR_CSR (0x1u << 8) /**< \brief (QSPI_IMR) Chip Select Rise Interrupt Mask */ +#define QSPI_IMR_CSS (0x1u << 9) /**< \brief (QSPI_IMR) Chip Select Status Interrupt Mask */ +#define QSPI_IMR_INSTRE (0x1u << 10) /**< \brief (QSPI_IMR) Instruction End Interrupt Mask */ +/* -------- QSPI_SCR : (QSPI Offset: 0x20) Serial Clock Register -------- */ +#define QSPI_SCR_CPOL (0x1u << 0) /**< \brief (QSPI_SCR) Clock Polarity */ +#define QSPI_SCR_CPHA (0x1u << 1) /**< \brief (QSPI_SCR) Clock Phase */ +#define QSPI_SCR_SCBR_Pos 8 +#define QSPI_SCR_SCBR_Msk (0xffu << QSPI_SCR_SCBR_Pos) /**< \brief (QSPI_SCR) Serial Clock Baud Rate */ +#define QSPI_SCR_SCBR(value) ((QSPI_SCR_SCBR_Msk & ((value) << QSPI_SCR_SCBR_Pos))) +#define QSPI_SCR_DLYBS_Pos 16 +#define QSPI_SCR_DLYBS_Msk (0xffu << QSPI_SCR_DLYBS_Pos) /**< \brief (QSPI_SCR) Delay Before QSCK */ +#define QSPI_SCR_DLYBS(value) ((QSPI_SCR_DLYBS_Msk & ((value) << QSPI_SCR_DLYBS_Pos))) +/* -------- QSPI_IAR : (QSPI Offset: 0x30) Instruction Address Register -------- */ +#define QSPI_IAR_ADDR_Pos 0 +#define QSPI_IAR_ADDR_Msk (0xffffffffu << QSPI_IAR_ADDR_Pos) /**< \brief (QSPI_IAR) Address */ +#define QSPI_IAR_ADDR(value) ((QSPI_IAR_ADDR_Msk & ((value) << QSPI_IAR_ADDR_Pos))) +/* -------- QSPI_ICR : (QSPI Offset: 0x34) Instruction Code Register -------- */ +#define QSPI_ICR_INST_Pos 0 +#define QSPI_ICR_INST_Msk (0xffu << QSPI_ICR_INST_Pos) /**< \brief (QSPI_ICR) Instruction Code */ +#define QSPI_ICR_INST(value) ((QSPI_ICR_INST_Msk & ((value) << QSPI_ICR_INST_Pos))) +#define QSPI_ICR_OPT_Pos 16 +#define QSPI_ICR_OPT_Msk (0xffu << QSPI_ICR_OPT_Pos) /**< \brief (QSPI_ICR) Option Code */ +#define QSPI_ICR_OPT(value) ((QSPI_ICR_OPT_Msk & ((value) << QSPI_ICR_OPT_Pos))) +/* -------- QSPI_IFR : (QSPI Offset: 0x38) Instruction Frame Register -------- */ +#define QSPI_IFR_WIDTH_Pos 0 +#define QSPI_IFR_WIDTH_Msk (0x7u << QSPI_IFR_WIDTH_Pos) /**< \brief (QSPI_IFR) Width of Instruction Code, Address, Option Code and Data */ +#define QSPI_IFR_WIDTH(value) ((QSPI_IFR_WIDTH_Msk & ((value) << QSPI_IFR_WIDTH_Pos))) +#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0x0u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI */ +#define QSPI_IFR_WIDTH_DUAL_OUTPUT (0x1u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_OUTPUT (0x2u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_IO (0x3u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_IO (0x4u << 0) /**< \brief (QSPI_IFR) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_WIDTH_DUAL_CMD (0x5u << 0) /**< \brief (QSPI_IFR) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI */ +#define QSPI_IFR_WIDTH_QUAD_CMD (0x6u << 0) /**< \brief (QSPI_IFR) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI */ +#define QSPI_IFR_INSTEN (0x1u << 4) /**< \brief (QSPI_IFR) Instruction Enable */ +#define QSPI_IFR_ADDREN (0x1u << 5) /**< \brief (QSPI_IFR) Address Enable */ +#define QSPI_IFR_OPTEN (0x1u << 6) /**< \brief (QSPI_IFR) Option Enable */ +#define QSPI_IFR_DATAEN (0x1u << 7) /**< \brief (QSPI_IFR) Data Enable */ +#define QSPI_IFR_OPTL_Pos 8 +#define QSPI_IFR_OPTL_Msk (0x3u << QSPI_IFR_OPTL_Pos) /**< \brief (QSPI_IFR) Option Code Length */ +#define QSPI_IFR_OPTL(value) ((QSPI_IFR_OPTL_Msk & ((value) << QSPI_IFR_OPTL_Pos))) +#define QSPI_IFR_OPTL_OPTION_1BIT (0x0u << 8) /**< \brief (QSPI_IFR) The option code is 1 bit long. */ +#define QSPI_IFR_OPTL_OPTION_2BIT (0x1u << 8) /**< \brief (QSPI_IFR) The option code is 2 bits long. */ +#define QSPI_IFR_OPTL_OPTION_4BIT (0x2u << 8) /**< \brief (QSPI_IFR) The option code is 4 bits long. */ +#define QSPI_IFR_OPTL_OPTION_8BIT (0x3u << 8) /**< \brief (QSPI_IFR) The option code is 8 bits long. */ +#define QSPI_IFR_ADDRL (0x1u << 10) /**< \brief (QSPI_IFR) Address Length */ +#define QSPI_IFR_ADDRL_24_BIT (0x0u << 10) /**< \brief (QSPI_IFR) The address is 24 bits long. */ +#define QSPI_IFR_ADDRL_32_BIT (0x1u << 10) /**< \brief (QSPI_IFR) The address is 32 bits long. */ +#define QSPI_IFR_TFRTYP_Pos 12 +#define QSPI_IFR_TFRTYP_Msk (0x3u << QSPI_IFR_TFRTYP_Pos) /**< \brief (QSPI_IFR) Data Transfer Type */ +#define QSPI_IFR_TFRTYP(value) ((QSPI_IFR_TFRTYP_Msk & ((value) << QSPI_IFR_TFRTYP_Pos))) +#define QSPI_IFR_TFRTYP_TRSFR_READ (0x0u << 12) /**< \brief (QSPI_IFR) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_READ_MEMORY (0x1u << 12) /**< \brief (QSPI_IFR) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE (0x2u << 12) /**< \brief (QSPI_IFR) Write transfer into the serial memory.Scrambling is not performed. */ +#define QSPI_IFR_TFRTYP_TRSFR_WRITE_MEMORY (0x3u << 12) /**< \brief (QSPI_IFR) Write data transfer into the serial memory.If enabled, scrambling is performed. */ +#define QSPI_IFR_CRM (0x1u << 14) /**< \brief (QSPI_IFR) Continuous Read Mode */ +#define QSPI_IFR_CRM_DISABLED (0x0u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is disabled. */ +#define QSPI_IFR_CRM_ENABLED (0x1u << 14) /**< \brief (QSPI_IFR) The Continuous Read mode is enabled. */ +#define QSPI_IFR_NBDUM_Pos 16 +#define QSPI_IFR_NBDUM_Msk (0x1fu << QSPI_IFR_NBDUM_Pos) /**< \brief (QSPI_IFR) Number Of Dummy Cycles */ +#define QSPI_IFR_NBDUM(value) ((QSPI_IFR_NBDUM_Msk & ((value) << QSPI_IFR_NBDUM_Pos))) +/* -------- QSPI_SMR : (QSPI Offset: 0x40) Scrambling Mode Register -------- */ +#define QSPI_SMR_SCREN (0x1u << 0) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Enable */ +#define QSPI_SMR_SCREN_DISABLED (0x0u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is disabled. */ +#define QSPI_SMR_SCREN_ENABLED (0x1u << 0) /**< \brief (QSPI_SMR) The scrambling/unscrambling is enabled. */ +#define QSPI_SMR_RVDIS (0x1u << 1) /**< \brief (QSPI_SMR) Scrambling/Unscrambling Random Value Disable */ +/* -------- QSPI_SKR : (QSPI Offset: 0x44) Scrambling Key Register -------- */ +#define QSPI_SKR_USRK_Pos 0 +#define QSPI_SKR_USRK_Msk (0xffffffffu << QSPI_SKR_USRK_Pos) /**< \brief (QSPI_SKR) Scrambling User Key */ +#define QSPI_SKR_USRK(value) ((QSPI_SKR_USRK_Msk & ((value) << QSPI_SKR_USRK_Pos))) +/* -------- QSPI_WPMR : (QSPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define QSPI_WPMR_WPEN (0x1u << 0) /**< \brief (QSPI_WPMR) Write Protection Enable */ +#define QSPI_WPMR_WPKEY_Pos 8 +#define QSPI_WPMR_WPKEY_Msk (0xffffffu << QSPI_WPMR_WPKEY_Pos) /**< \brief (QSPI_WPMR) Write Protection Key */ +#define QSPI_WPMR_WPKEY(value) ((QSPI_WPMR_WPKEY_Msk & ((value) << QSPI_WPMR_WPKEY_Pos))) +#define QSPI_WPMR_WPKEY_PASSWD (0x515350u << 8) /**< \brief (QSPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- QSPI_WPSR : (QSPI Offset: 0xE8) Write Protection Status Register -------- */ +#define QSPI_WPSR_WPVS (0x1u << 0) /**< \brief (QSPI_WPSR) Write Protection Violation Status */ +#define QSPI_WPSR_WPVSRC_Pos 8 +#define QSPI_WPSR_WPVSRC_Msk (0xffu << QSPI_WPSR_WPVSRC_Pos) /**< \brief (QSPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_QSPI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rstc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rstc.h new file mode 100644 index 000000000..e11a7c76c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rstc.h @@ -0,0 +1,79 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSTC_COMPONENT_ +#define _SAMV71_RSTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reset Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSTC Reset Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rstc hardware registers */ +typedef struct { + __O uint32_t RSTC_CR; /**< \brief (Rstc Offset: 0x00) Control Register */ + __I uint32_t RSTC_SR; /**< \brief (Rstc Offset: 0x04) Status Register */ + __IO uint32_t RSTC_MR; /**< \brief (Rstc Offset: 0x08) Mode Register */ +} Rstc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ +#define RSTC_CR_PROCRST (0x1u << 0) /**< \brief (RSTC_CR) Processor Reset */ +#define RSTC_CR_EXTRST (0x1u << 3) /**< \brief (RSTC_CR) External Reset */ +#define RSTC_CR_KEY_Pos 24 +#define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /**< \brief (RSTC_CR) System Reset Key */ +#define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) +#define RSTC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ +#define RSTC_SR_URSTS (0x1u << 0) /**< \brief (RSTC_SR) User Reset Status */ +#define RSTC_SR_RSTTYP_Pos 8 +#define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /**< \brief (RSTC_SR) Reset Type */ +#define RSTC_SR_RSTTYP_GENERAL_RST (0x0u << 8) /**< \brief (RSTC_SR) First power-up reset */ +#define RSTC_SR_RSTTYP_BACKUP_RST (0x1u << 8) /**< \brief (RSTC_SR) Return from Backup Mode */ +#define RSTC_SR_RSTTYP_WDT_RST (0x2u << 8) /**< \brief (RSTC_SR) Watchdog fault occurred */ +#define RSTC_SR_RSTTYP_SOFT_RST (0x3u << 8) /**< \brief (RSTC_SR) Processor reset required by the software */ +#define RSTC_SR_RSTTYP_USER_RST (0x4u << 8) /**< \brief (RSTC_SR) NRST pin detected low */ +#define RSTC_SR_NRSTL (0x1u << 16) /**< \brief (RSTC_SR) NRST Pin Level */ +#define RSTC_SR_SRCMP (0x1u << 17) /**< \brief (RSTC_SR) Software Reset Command in Progress */ +/* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ +#define RSTC_MR_URSTEN (0x1u << 0) /**< \brief (RSTC_MR) User Reset Enable */ +#define RSTC_MR_URSTIEN (0x1u << 4) /**< \brief (RSTC_MR) User Reset Interrupt Enable */ +#define RSTC_MR_ERSTL_Pos 8 +#define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /**< \brief (RSTC_MR) External Reset Length */ +#define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) +#define RSTC_MR_KEY_Pos 24 +#define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /**< \brief (RSTC_MR) Write Access Password */ +#define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) +#define RSTC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_RSTC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rswdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rswdt.h new file mode 100644 index 000000000..d3f96091e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rswdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSWDT_COMPONENT_ +#define _SAMV71_RSWDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Reinforced Safety Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RSWDT Reinforced Safety Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rswdt hardware registers */ +typedef struct { + __O uint32_t RSWDT_CR; /**< \brief (Rswdt Offset: 0x00) Control Register */ + __IO uint32_t RSWDT_MR; /**< \brief (Rswdt Offset: 0x04) Mode Register */ + __I uint32_t RSWDT_SR; /**< \brief (Rswdt Offset: 0x08) Status Register */ +} Rswdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RSWDT_CR : (RSWDT Offset: 0x00) Control Register -------- */ +#define RSWDT_CR_WDRSTT (0x1u << 0) /**< \brief (RSWDT_CR) Watchdog Restart */ +#define RSWDT_CR_KEY_Pos 24 +#define RSWDT_CR_KEY_Msk (0xffu << RSWDT_CR_KEY_Pos) /**< \brief (RSWDT_CR) Password */ +#define RSWDT_CR_KEY(value) ((RSWDT_CR_KEY_Msk & ((value) << RSWDT_CR_KEY_Pos))) +#define RSWDT_CR_KEY_PASSWD (0xC4u << 24) /**< \brief (RSWDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- RSWDT_MR : (RSWDT Offset: 0x04) Mode Register -------- */ +#define RSWDT_MR_WDV_Pos 0 +#define RSWDT_MR_WDV_Msk (0xfffu << RSWDT_MR_WDV_Pos) /**< \brief (RSWDT_MR) Watchdog Counter Value */ +#define RSWDT_MR_WDV(value) ((RSWDT_MR_WDV_Msk & ((value) << RSWDT_MR_WDV_Pos))) +#define RSWDT_MR_WDFIEN (0x1u << 12) /**< \brief (RSWDT_MR) Watchdog Fault Interrupt Enable */ +#define RSWDT_MR_WDRSTEN (0x1u << 13) /**< \brief (RSWDT_MR) Watchdog Reset Enable */ +#define RSWDT_MR_WDRPROC (0x1u << 14) /**< \brief (RSWDT_MR) Watchdog Reset Processor */ +#define RSWDT_MR_WDDIS (0x1u << 15) /**< \brief (RSWDT_MR) Watchdog Disable */ +#define RSWDT_MR_ALLONES_Pos 16 +#define RSWDT_MR_ALLONES_Msk (0xfffu << RSWDT_MR_ALLONES_Pos) /**< \brief (RSWDT_MR) Must Always Be Written with 0xFFF */ +#define RSWDT_MR_ALLONES(value) ((RSWDT_MR_ALLONES_Msk & ((value) << RSWDT_MR_ALLONES_Pos))) +#define RSWDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (RSWDT_MR) Watchdog Debug Halt */ +#define RSWDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (RSWDT_MR) Watchdog Idle Halt */ +/* -------- RSWDT_SR : (RSWDT Offset: 0x08) Status Register -------- */ +#define RSWDT_SR_WDUNF (0x1u << 0) /**< \brief (RSWDT_SR) Watchdog Underflow */ + +/*@}*/ + + +#endif /* _SAMV71_RSWDT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rtc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rtc.h new file mode 100644 index 000000000..c4245753c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rtc.h @@ -0,0 +1,226 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTC_COMPONENT_ +#define _SAMV71_RTC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Clock */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTC Real-time Clock */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtc hardware registers */ +typedef struct { + __IO uint32_t RTC_CR; /**< \brief (Rtc Offset: 0x00) Control Register */ + __IO uint32_t RTC_MR; /**< \brief (Rtc Offset: 0x04) Mode Register */ + __IO uint32_t RTC_TIMR; /**< \brief (Rtc Offset: 0x08) Time Register */ + __IO uint32_t RTC_CALR; /**< \brief (Rtc Offset: 0x0C) Calendar Register */ + __IO uint32_t RTC_TIMALR; /**< \brief (Rtc Offset: 0x10) Time Alarm Register */ + __IO uint32_t RTC_CALALR; /**< \brief (Rtc Offset: 0x14) Calendar Alarm Register */ + __I uint32_t RTC_SR; /**< \brief (Rtc Offset: 0x18) Status Register */ + __O uint32_t RTC_SCCR; /**< \brief (Rtc Offset: 0x1C) Status Clear Command Register */ + __O uint32_t RTC_IER; /**< \brief (Rtc Offset: 0x20) Interrupt Enable Register */ + __O uint32_t RTC_IDR; /**< \brief (Rtc Offset: 0x24) Interrupt Disable Register */ + __I uint32_t RTC_IMR; /**< \brief (Rtc Offset: 0x28) Interrupt Mask Register */ + __I uint32_t RTC_VER; /**< \brief (Rtc Offset: 0x2C) Valid Entry Register */ +} Rtc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ +#define RTC_CR_UPDTIM (0x1u << 0) /**< \brief (RTC_CR) Update Request Time Register */ +#define RTC_CR_UPDCAL (0x1u << 1) /**< \brief (RTC_CR) Update Request Calendar Register */ +#define RTC_CR_TIMEVSEL_Pos 8 +#define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /**< \brief (RTC_CR) Time Event Selection */ +#define RTC_CR_TIMEVSEL(value) ((RTC_CR_TIMEVSEL_Msk & ((value) << RTC_CR_TIMEVSEL_Pos))) +#define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /**< \brief (RTC_CR) Minute change */ +#define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /**< \brief (RTC_CR) Hour change */ +#define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /**< \brief (RTC_CR) Every day at midnight */ +#define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /**< \brief (RTC_CR) Every day at noon */ +#define RTC_CR_CALEVSEL_Pos 16 +#define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /**< \brief (RTC_CR) Calendar Event Selection */ +#define RTC_CR_CALEVSEL(value) ((RTC_CR_CALEVSEL_Msk & ((value) << RTC_CR_CALEVSEL_Pos))) +#define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /**< \brief (RTC_CR) Week change (every Monday at time 00:00:00) */ +#define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /**< \brief (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ +#define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /**< \brief (RTC_CR) Year change (every January 1 at time 00:00:00) */ +/* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ +#define RTC_MR_HRMOD (0x1u << 0) /**< \brief (RTC_MR) 12-/24-hour Mode */ +#define RTC_MR_PERSIAN (0x1u << 1) /**< \brief (RTC_MR) PERSIAN Calendar */ +#define RTC_MR_NEGPPM (0x1u << 4) /**< \brief (RTC_MR) NEGative PPM Correction */ +#define RTC_MR_CORRECTION_Pos 8 +#define RTC_MR_CORRECTION_Msk (0x7fu << RTC_MR_CORRECTION_Pos) /**< \brief (RTC_MR) Slow Clock Correction */ +#define RTC_MR_CORRECTION(value) ((RTC_MR_CORRECTION_Msk & ((value) << RTC_MR_CORRECTION_Pos))) +#define RTC_MR_HIGHPPM (0x1u << 15) /**< \brief (RTC_MR) HIGH PPM Correction */ +#define RTC_MR_OUT0_Pos 16 +#define RTC_MR_OUT0_Msk (0x7u << RTC_MR_OUT0_Pos) /**< \brief (RTC_MR) RTCOUT0 OutputSource Selection */ +#define RTC_MR_OUT0(value) ((RTC_MR_OUT0_Msk & ((value) << RTC_MR_OUT0_Pos))) +#define RTC_MR_OUT0_NO_WAVE (0x0u << 16) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT0_FREQ1HZ (0x1u << 16) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT0_FREQ32HZ (0x2u << 16) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT0_FREQ64HZ (0x3u << 16) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT0_FREQ512HZ (0x4u << 16) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT0_ALARM_TOGGLE (0x5u << 16) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT0_ALARM_FLAG (0x6u << 16) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT0_PROG_PULSE (0x7u << 16) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_OUT1_Pos 20 +#define RTC_MR_OUT1_Msk (0x7u << RTC_MR_OUT1_Pos) /**< \brief (RTC_MR) RTCOUT1 Output Source Selection */ +#define RTC_MR_OUT1(value) ((RTC_MR_OUT1_Msk & ((value) << RTC_MR_OUT1_Pos))) +#define RTC_MR_OUT1_NO_WAVE (0x0u << 20) /**< \brief (RTC_MR) No waveform, stuck at '0' */ +#define RTC_MR_OUT1_FREQ1HZ (0x1u << 20) /**< \brief (RTC_MR) 1 Hz square wave */ +#define RTC_MR_OUT1_FREQ32HZ (0x2u << 20) /**< \brief (RTC_MR) 32 Hz square wave */ +#define RTC_MR_OUT1_FREQ64HZ (0x3u << 20) /**< \brief (RTC_MR) 64 Hz square wave */ +#define RTC_MR_OUT1_FREQ512HZ (0x4u << 20) /**< \brief (RTC_MR) 512 Hz square wave */ +#define RTC_MR_OUT1_ALARM_TOGGLE (0x5u << 20) /**< \brief (RTC_MR) Output toggles when alarm flag rises */ +#define RTC_MR_OUT1_ALARM_FLAG (0x6u << 20) /**< \brief (RTC_MR) Output is a copy of the alarm flag */ +#define RTC_MR_OUT1_PROG_PULSE (0x7u << 20) /**< \brief (RTC_MR) Duty cycle programmable pulse */ +#define RTC_MR_THIGH_Pos 24 +#define RTC_MR_THIGH_Msk (0x7u << RTC_MR_THIGH_Pos) /**< \brief (RTC_MR) High Duration of the Output Pulse */ +#define RTC_MR_THIGH(value) ((RTC_MR_THIGH_Msk & ((value) << RTC_MR_THIGH_Pos))) +#define RTC_MR_THIGH_H_31MS (0x0u << 24) /**< \brief (RTC_MR) 31.2 ms */ +#define RTC_MR_THIGH_H_16MS (0x1u << 24) /**< \brief (RTC_MR) 15.6 ms */ +#define RTC_MR_THIGH_H_4MS (0x2u << 24) /**< \brief (RTC_MR) 3.91 ms */ +#define RTC_MR_THIGH_H_976US (0x3u << 24) /**< \brief (RTC_MR) 976 us */ +#define RTC_MR_THIGH_H_488US (0x4u << 24) /**< \brief (RTC_MR) 488 us */ +#define RTC_MR_THIGH_H_122US (0x5u << 24) /**< \brief (RTC_MR) 122 us */ +#define RTC_MR_THIGH_H_30US (0x6u << 24) /**< \brief (RTC_MR) 30.5 us */ +#define RTC_MR_THIGH_H_15US (0x7u << 24) /**< \brief (RTC_MR) 15.2 us */ +#define RTC_MR_TPERIOD_Pos 28 +#define RTC_MR_TPERIOD_Msk (0x3u << RTC_MR_TPERIOD_Pos) /**< \brief (RTC_MR) Period of the Output Pulse */ +#define RTC_MR_TPERIOD(value) ((RTC_MR_TPERIOD_Msk & ((value) << RTC_MR_TPERIOD_Pos))) +#define RTC_MR_TPERIOD_P_1S (0x0u << 28) /**< \brief (RTC_MR) 1 second */ +#define RTC_MR_TPERIOD_P_500MS (0x1u << 28) /**< \brief (RTC_MR) 500 ms */ +#define RTC_MR_TPERIOD_P_250MS (0x2u << 28) /**< \brief (RTC_MR) 250 ms */ +#define RTC_MR_TPERIOD_P_125MS (0x3u << 28) /**< \brief (RTC_MR) 125 ms */ +/* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ +#define RTC_TIMR_SEC_Pos 0 +#define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /**< \brief (RTC_TIMR) Current Second */ +#define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) +#define RTC_TIMR_MIN_Pos 8 +#define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /**< \brief (RTC_TIMR) Current Minute */ +#define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) +#define RTC_TIMR_HOUR_Pos 16 +#define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /**< \brief (RTC_TIMR) Current Hour */ +#define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) +#define RTC_TIMR_AMPM (0x1u << 22) /**< \brief (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ +/* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ +#define RTC_CALR_CENT_Pos 0 +#define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /**< \brief (RTC_CALR) Current Century */ +#define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) +#define RTC_CALR_YEAR_Pos 8 +#define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /**< \brief (RTC_CALR) Current Year */ +#define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) +#define RTC_CALR_MONTH_Pos 16 +#define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /**< \brief (RTC_CALR) Current Month */ +#define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) +#define RTC_CALR_DAY_Pos 21 +#define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /**< \brief (RTC_CALR) Current Day in Current Week */ +#define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) +#define RTC_CALR_DATE_Pos 24 +#define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /**< \brief (RTC_CALR) Current Day in Current Month */ +#define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) +/* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ +#define RTC_TIMALR_SEC_Pos 0 +#define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /**< \brief (RTC_TIMALR) Second Alarm */ +#define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) +#define RTC_TIMALR_SECEN (0x1u << 7) /**< \brief (RTC_TIMALR) Second Alarm Enable */ +#define RTC_TIMALR_MIN_Pos 8 +#define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /**< \brief (RTC_TIMALR) Minute Alarm */ +#define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) +#define RTC_TIMALR_MINEN (0x1u << 15) /**< \brief (RTC_TIMALR) Minute Alarm Enable */ +#define RTC_TIMALR_HOUR_Pos 16 +#define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /**< \brief (RTC_TIMALR) Hour Alarm */ +#define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) +#define RTC_TIMALR_AMPM (0x1u << 22) /**< \brief (RTC_TIMALR) AM/PM Indicator */ +#define RTC_TIMALR_HOUREN (0x1u << 23) /**< \brief (RTC_TIMALR) Hour Alarm Enable */ +/* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ +#define RTC_CALALR_MONTH_Pos 16 +#define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /**< \brief (RTC_CALALR) Month Alarm */ +#define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) +#define RTC_CALALR_MTHEN (0x1u << 23) /**< \brief (RTC_CALALR) Month Alarm Enable */ +#define RTC_CALALR_DATE_Pos 24 +#define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /**< \brief (RTC_CALALR) Date Alarm */ +#define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) +#define RTC_CALALR_DATEEN (0x1u << 31) /**< \brief (RTC_CALALR) Date Alarm Enable */ +/* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ +#define RTC_SR_ACKUPD (0x1u << 0) /**< \brief (RTC_SR) Acknowledge for Update */ +#define RTC_SR_ACKUPD_FREERUN (0x0u << 0) /**< \brief (RTC_SR) Time and calendar registers cannot be updated. */ +#define RTC_SR_ACKUPD_UPDATE (0x1u << 0) /**< \brief (RTC_SR) Time and calendar registers can be updated. */ +#define RTC_SR_ALARM (0x1u << 1) /**< \brief (RTC_SR) Alarm Flag */ +#define RTC_SR_ALARM_NO_ALARMEVENT (0x0u << 1) /**< \brief (RTC_SR) No alarm matching condition occurred. */ +#define RTC_SR_ALARM_ALARMEVENT (0x1u << 1) /**< \brief (RTC_SR) An alarm matching condition has occurred. */ +#define RTC_SR_SEC (0x1u << 2) /**< \brief (RTC_SR) Second Event */ +#define RTC_SR_SEC_NO_SECEVENT (0x0u << 2) /**< \brief (RTC_SR) No second event has occurred since the last clear. */ +#define RTC_SR_SEC_SECEVENT (0x1u << 2) /**< \brief (RTC_SR) At least one second event has occurred since the last clear. */ +#define RTC_SR_TIMEV (0x1u << 3) /**< \brief (RTC_SR) Time Event */ +#define RTC_SR_TIMEV_NO_TIMEVENT (0x0u << 3) /**< \brief (RTC_SR) No time event has occurred since the last clear. */ +#define RTC_SR_TIMEV_TIMEVENT (0x1u << 3) /**< \brief (RTC_SR) At least one time event has occurred since the last clear. */ +#define RTC_SR_CALEV (0x1u << 4) /**< \brief (RTC_SR) Calendar Event */ +#define RTC_SR_CALEV_NO_CALEVENT (0x0u << 4) /**< \brief (RTC_SR) No calendar event has occurred since the last clear. */ +#define RTC_SR_CALEV_CALEVENT (0x1u << 4) /**< \brief (RTC_SR) At least one calendar event has occurred since the last clear. */ +#define RTC_SR_TDERR (0x1u << 5) /**< \brief (RTC_SR) Time and/or Date Free Running Error */ +#define RTC_SR_TDERR_CORRECT (0x0u << 5) /**< \brief (RTC_SR) The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). */ +#define RTC_SR_TDERR_ERR_TIMEDATE (0x1u << 5) /**< \brief (RTC_SR) The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. */ +/* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ +#define RTC_SCCR_ACKCLR (0x1u << 0) /**< \brief (RTC_SCCR) Acknowledge Clear */ +#define RTC_SCCR_ALRCLR (0x1u << 1) /**< \brief (RTC_SCCR) Alarm Clear */ +#define RTC_SCCR_SECCLR (0x1u << 2) /**< \brief (RTC_SCCR) Second Clear */ +#define RTC_SCCR_TIMCLR (0x1u << 3) /**< \brief (RTC_SCCR) Time Clear */ +#define RTC_SCCR_CALCLR (0x1u << 4) /**< \brief (RTC_SCCR) Calendar Clear */ +#define RTC_SCCR_TDERRCLR (0x1u << 5) /**< \brief (RTC_SCCR) Time and/or Date Free Running Error Clear */ +/* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ +#define RTC_IER_ACKEN (0x1u << 0) /**< \brief (RTC_IER) Acknowledge Update Interrupt Enable */ +#define RTC_IER_ALREN (0x1u << 1) /**< \brief (RTC_IER) Alarm Interrupt Enable */ +#define RTC_IER_SECEN (0x1u << 2) /**< \brief (RTC_IER) Second Event Interrupt Enable */ +#define RTC_IER_TIMEN (0x1u << 3) /**< \brief (RTC_IER) Time Event Interrupt Enable */ +#define RTC_IER_CALEN (0x1u << 4) /**< \brief (RTC_IER) Calendar Event Interrupt Enable */ +#define RTC_IER_TDERREN (0x1u << 5) /**< \brief (RTC_IER) Time and/or Date Error Interrupt Enable */ +/* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ +#define RTC_IDR_ACKDIS (0x1u << 0) /**< \brief (RTC_IDR) Acknowledge Update Interrupt Disable */ +#define RTC_IDR_ALRDIS (0x1u << 1) /**< \brief (RTC_IDR) Alarm Interrupt Disable */ +#define RTC_IDR_SECDIS (0x1u << 2) /**< \brief (RTC_IDR) Second Event Interrupt Disable */ +#define RTC_IDR_TIMDIS (0x1u << 3) /**< \brief (RTC_IDR) Time Event Interrupt Disable */ +#define RTC_IDR_CALDIS (0x1u << 4) /**< \brief (RTC_IDR) Calendar Event Interrupt Disable */ +#define RTC_IDR_TDERRDIS (0x1u << 5) /**< \brief (RTC_IDR) Time and/or Date Error Interrupt Disable */ +/* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ +#define RTC_IMR_ACK (0x1u << 0) /**< \brief (RTC_IMR) Acknowledge Update Interrupt Mask */ +#define RTC_IMR_ALR (0x1u << 1) /**< \brief (RTC_IMR) Alarm Interrupt Mask */ +#define RTC_IMR_SEC (0x1u << 2) /**< \brief (RTC_IMR) Second Event Interrupt Mask */ +#define RTC_IMR_TIM (0x1u << 3) /**< \brief (RTC_IMR) Time Event Interrupt Mask */ +#define RTC_IMR_CAL (0x1u << 4) /**< \brief (RTC_IMR) Calendar Event Interrupt Mask */ +#define RTC_IMR_TDERR (0x1u << 5) /**< \brief (RTC_IMR) Time and/or Date Error Mask */ +/* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ +#define RTC_VER_NVTIM (0x1u << 0) /**< \brief (RTC_VER) Non-valid Time */ +#define RTC_VER_NVCAL (0x1u << 1) /**< \brief (RTC_VER) Non-valid Calendar */ +#define RTC_VER_NVTIMALR (0x1u << 2) /**< \brief (RTC_VER) Non-valid Time Alarm */ +#define RTC_VER_NVCALALR (0x1u << 3) /**< \brief (RTC_VER) Non-valid Calendar Alarm */ + +/*@}*/ + + +#endif /* _SAMV71_RTC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rtt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rtt.h new file mode 100644 index 000000000..e0bc5c6c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_rtt.h @@ -0,0 +1,71 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTT_COMPONENT_ +#define _SAMV71_RTT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Real-time Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_RTT Real-time Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Rtt hardware registers */ +typedef struct { + __IO uint32_t RTT_MR; /**< \brief (Rtt Offset: 0x00) Mode Register */ + __IO uint32_t RTT_AR; /**< \brief (Rtt Offset: 0x04) Alarm Register */ + __I uint32_t RTT_VR; /**< \brief (Rtt Offset: 0x08) Value Register */ + __I uint32_t RTT_SR; /**< \brief (Rtt Offset: 0x0C) Status Register */ +} Rtt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ +#define RTT_MR_RTPRES_Pos 0 +#define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /**< \brief (RTT_MR) Real-time Timer Prescaler Value */ +#define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) +#define RTT_MR_ALMIEN (0x1u << 16) /**< \brief (RTT_MR) Alarm Interrupt Enable */ +#define RTT_MR_RTTINCIEN (0x1u << 17) /**< \brief (RTT_MR) Real-time Timer Increment Interrupt Enable */ +#define RTT_MR_RTTRST (0x1u << 18) /**< \brief (RTT_MR) Real-time Timer Restart */ +#define RTT_MR_RTTDIS (0x1u << 20) /**< \brief (RTT_MR) Real-time Timer Disable */ +#define RTT_MR_RTC1HZ (0x1u << 24) /**< \brief (RTT_MR) Real-Time Clock 1Hz Clock Selection */ +/* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ +#define RTT_AR_ALMV_Pos 0 +#define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /**< \brief (RTT_AR) Alarm Value */ +#define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) +/* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ +#define RTT_VR_CRTV_Pos 0 +#define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /**< \brief (RTT_VR) Current Real-time Value */ +/* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ +#define RTT_SR_ALMS (0x1u << 0) /**< \brief (RTT_SR) Real-time Alarm Status (cleared on read) */ +#define RTT_SR_RTTINC (0x1u << 1) /**< \brief (RTT_SR) Prescaler Roll-over Status (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_RTT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_sdramc.h new file mode 100644 index 000000000..6ea4c012d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_sdramc.h @@ -0,0 +1,173 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SDRAMC_COMPONENT_ +#define _SAMV71_SDRAMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR SDRAM Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SDRAMC SDRAM Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Sdramc hardware registers */ +typedef struct { + __IO uint32_t SDRAMC_MR; /**< \brief (Sdramc Offset: 0x00) SDRAMC Mode Register */ + __IO uint32_t SDRAMC_TR; /**< \brief (Sdramc Offset: 0x04) SDRAMC Refresh Timer Register */ + __IO uint32_t SDRAMC_CR; /**< \brief (Sdramc Offset: 0x08) SDRAMC Configuration Register */ + __I uint32_t Reserved1[1]; + __IO uint32_t SDRAMC_LPR; /**< \brief (Sdramc Offset: 0x10) SDRAMC Low Power Register */ + __O uint32_t SDRAMC_IER; /**< \brief (Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register */ + __O uint32_t SDRAMC_IDR; /**< \brief (Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register */ + __I uint32_t SDRAMC_IMR; /**< \brief (Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register */ + __I uint32_t SDRAMC_ISR; /**< \brief (Sdramc Offset: 0x20) SDRAMC Interrupt Status Register */ + __IO uint32_t SDRAMC_MDR; /**< \brief (Sdramc Offset: 0x24) SDRAMC Memory Device Register */ + __IO uint32_t SDRAMC_CFR1; /**< \brief (Sdramc Offset: 0x28) SDRAMC Configuration Register 1 */ + __IO uint32_t SDRAMC_OCMS; /**< \brief (Sdramc Offset: 0x2C) SDRAMC OCMS Register */ + __O uint32_t SDRAMC_OCMS_KEY1; /**< \brief (Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register */ + __O uint32_t SDRAMC_OCMS_KEY2; /**< \brief (Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register */ +} Sdramc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SDRAMC_MR : (SDRAMC Offset: 0x00) SDRAMC Mode Register -------- */ +#define SDRAMC_MR_MODE_Pos 0 +#define SDRAMC_MR_MODE_Msk (0x7u << SDRAMC_MR_MODE_Pos) /**< \brief (SDRAMC_MR) SDRAMC Command Mode */ +#define SDRAMC_MR_MODE(value) ((SDRAMC_MR_MODE_Msk & ((value) << SDRAMC_MR_MODE_Pos))) +#define SDRAMC_MR_MODE_NORMAL (0x0u << 0) /**< \brief (SDRAMC_MR) Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_NOP (0x1u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE (0x2u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_LOAD_MODEREG (0x3u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_AUTO_REFRESH (0x4u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. */ +#define SDRAMC_MR_MODE_EXT_LOAD_MODEREG (0x5u << 0) /**< \brief (SDRAMC_MR) The SDRAMC issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. */ +#define SDRAMC_MR_MODE_DEEP_POWERDOWN (0x6u << 0) /**< \brief (SDRAMC_MR) Deep power-down mode. Enters deep power-down mode. */ +/* -------- SDRAMC_TR : (SDRAMC Offset: 0x04) SDRAMC Refresh Timer Register -------- */ +#define SDRAMC_TR_COUNT_Pos 0 +#define SDRAMC_TR_COUNT_Msk (0xfffu << SDRAMC_TR_COUNT_Pos) /**< \brief (SDRAMC_TR) SDRAMC Refresh Timer Count */ +#define SDRAMC_TR_COUNT(value) ((SDRAMC_TR_COUNT_Msk & ((value) << SDRAMC_TR_COUNT_Pos))) +/* -------- SDRAMC_CR : (SDRAMC Offset: 0x08) SDRAMC Configuration Register -------- */ +#define SDRAMC_CR_NC_Pos 0 +#define SDRAMC_CR_NC_Msk (0x3u << SDRAMC_CR_NC_Pos) /**< \brief (SDRAMC_CR) Number of Column Bits */ +#define SDRAMC_CR_NC(value) ((SDRAMC_CR_NC_Msk & ((value) << SDRAMC_CR_NC_Pos))) +#define SDRAMC_CR_NC_COL8 (0x0u << 0) /**< \brief (SDRAMC_CR) 8 column bits */ +#define SDRAMC_CR_NC_COL9 (0x1u << 0) /**< \brief (SDRAMC_CR) 9 column bits */ +#define SDRAMC_CR_NC_COL10 (0x2u << 0) /**< \brief (SDRAMC_CR) 10 column bits */ +#define SDRAMC_CR_NC_COL11 (0x3u << 0) /**< \brief (SDRAMC_CR) 11 column bits */ +#define SDRAMC_CR_NR_Pos 2 +#define SDRAMC_CR_NR_Msk (0x3u << SDRAMC_CR_NR_Pos) /**< \brief (SDRAMC_CR) Number of Row Bits */ +#define SDRAMC_CR_NR(value) ((SDRAMC_CR_NR_Msk & ((value) << SDRAMC_CR_NR_Pos))) +#define SDRAMC_CR_NR_ROW11 (0x0u << 2) /**< \brief (SDRAMC_CR) 11 row bits */ +#define SDRAMC_CR_NR_ROW12 (0x1u << 2) /**< \brief (SDRAMC_CR) 12 row bits */ +#define SDRAMC_CR_NR_ROW13 (0x2u << 2) /**< \brief (SDRAMC_CR) 13 row bits */ +#define SDRAMC_CR_NB (0x1u << 4) /**< \brief (SDRAMC_CR) Number of Banks */ +#define SDRAMC_CR_NB_BANK2 (0x0u << 4) /**< \brief (SDRAMC_CR) 2 banks */ +#define SDRAMC_CR_NB_BANK4 (0x1u << 4) /**< \brief (SDRAMC_CR) 4 banks */ +#define SDRAMC_CR_CAS_Pos 5 +#define SDRAMC_CR_CAS_Msk (0x3u << SDRAMC_CR_CAS_Pos) /**< \brief (SDRAMC_CR) CAS Latency */ +#define SDRAMC_CR_CAS(value) ((SDRAMC_CR_CAS_Msk & ((value) << SDRAMC_CR_CAS_Pos))) +#define SDRAMC_CR_CAS_LATENCY1 (0x0u << 5) /**< \brief (SDRAMC_CR) 1 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY2 (0x1u << 5) /**< \brief (SDRAMC_CR) 2 cycle CAS latency */ +#define SDRAMC_CR_CAS_LATENCY3 (0x2u << 5) /**< \brief (SDRAMC_CR) 3 cycle CAS latency */ +#define SDRAMC_CR_DBW (0x1u << 7) /**< \brief (SDRAMC_CR) Data Bus Width */ +#define SDRAMC_CR_TWR_Pos 8 +#define SDRAMC_CR_TWR_Msk (0xfu << SDRAMC_CR_TWR_Pos) /**< \brief (SDRAMC_CR) Write Recovery Delay */ +#define SDRAMC_CR_TWR(value) ((SDRAMC_CR_TWR_Msk & ((value) << SDRAMC_CR_TWR_Pos))) +#define SDRAMC_CR_TRC_TRFC_Pos 12 +#define SDRAMC_CR_TRC_TRFC_Msk (0xfu << SDRAMC_CR_TRC_TRFC_Pos) /**< \brief (SDRAMC_CR) Row Cycle Delay and Row Refresh Cycle */ +#define SDRAMC_CR_TRC_TRFC(value) ((SDRAMC_CR_TRC_TRFC_Msk & ((value) << SDRAMC_CR_TRC_TRFC_Pos))) +#define SDRAMC_CR_TRP_Pos 16 +#define SDRAMC_CR_TRP_Msk (0xfu << SDRAMC_CR_TRP_Pos) /**< \brief (SDRAMC_CR) Row Precharge Delay */ +#define SDRAMC_CR_TRP(value) ((SDRAMC_CR_TRP_Msk & ((value) << SDRAMC_CR_TRP_Pos))) +#define SDRAMC_CR_TRCD_Pos 20 +#define SDRAMC_CR_TRCD_Msk (0xfu << SDRAMC_CR_TRCD_Pos) /**< \brief (SDRAMC_CR) Row to Column Delay */ +#define SDRAMC_CR_TRCD(value) ((SDRAMC_CR_TRCD_Msk & ((value) << SDRAMC_CR_TRCD_Pos))) +#define SDRAMC_CR_TRAS_Pos 24 +#define SDRAMC_CR_TRAS_Msk (0xfu << SDRAMC_CR_TRAS_Pos) /**< \brief (SDRAMC_CR) Active to Precharge Delay */ +#define SDRAMC_CR_TRAS(value) ((SDRAMC_CR_TRAS_Msk & ((value) << SDRAMC_CR_TRAS_Pos))) +#define SDRAMC_CR_TXSR_Pos 28 +#define SDRAMC_CR_TXSR_Msk (0xfu << SDRAMC_CR_TXSR_Pos) /**< \brief (SDRAMC_CR) Exit Self Refresh to Active Delay */ +#define SDRAMC_CR_TXSR(value) ((SDRAMC_CR_TXSR_Msk & ((value) << SDRAMC_CR_TXSR_Pos))) +/* -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAMC Low Power Register -------- */ +#define SDRAMC_LPR_LPCB_Pos 0 +#define SDRAMC_LPR_LPCB_Msk (0x3u << SDRAMC_LPR_LPCB_Pos) /**< \brief (SDRAMC_LPR) Low-power Configuration Bits */ +#define SDRAMC_LPR_LPCB(value) ((SDRAMC_LPR_LPCB_Msk & ((value) << SDRAMC_LPR_LPCB_Pos))) +#define SDRAMC_LPR_LPCB_DISABLED (0x0u << 0) /**< \brief (SDRAMC_LPR) Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. */ +#define SDRAMC_LPR_LPCB_SELF_REFRESH (0x1u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Self-refresh command to the SDRAM device, the SDCK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_POWER_DOWN (0x2u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. */ +#define SDRAMC_LPR_LPCB_DEEP_POWER_DOWN (0x3u << 0) /**< \brief (SDRAMC_LPR) The SDRAMC issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM. */ +#define SDRAMC_LPR_PASR_Pos 4 +#define SDRAMC_LPR_PASR_Msk (0x7u << SDRAMC_LPR_PASR_Pos) /**< \brief (SDRAMC_LPR) Partial Array Self-refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_PASR(value) ((SDRAMC_LPR_PASR_Msk & ((value) << SDRAMC_LPR_PASR_Pos))) +#define SDRAMC_LPR_TCSR_Pos 8 +#define SDRAMC_LPR_TCSR_Msk (0x3u << SDRAMC_LPR_TCSR_Pos) /**< \brief (SDRAMC_LPR) Temperature Compensated Self-Refresh (only for low-power SDRAM) */ +#define SDRAMC_LPR_TCSR(value) ((SDRAMC_LPR_TCSR_Msk & ((value) << SDRAMC_LPR_TCSR_Pos))) +#define SDRAMC_LPR_DS_Pos 10 +#define SDRAMC_LPR_DS_Msk (0x3u << SDRAMC_LPR_DS_Pos) /**< \brief (SDRAMC_LPR) Drive Strength (only for low-power SDRAM) */ +#define SDRAMC_LPR_DS(value) ((SDRAMC_LPR_DS_Msk & ((value) << SDRAMC_LPR_DS_Pos))) +#define SDRAMC_LPR_TIMEOUT_Pos 12 +#define SDRAMC_LPR_TIMEOUT_Msk (0x3u << SDRAMC_LPR_TIMEOUT_Pos) /**< \brief (SDRAMC_LPR) Time to Define When Low-power Mode Is Enabled */ +#define SDRAMC_LPR_TIMEOUT(value) ((SDRAMC_LPR_TIMEOUT_Msk & ((value) << SDRAMC_LPR_TIMEOUT_Pos))) +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER (0x0u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode immediately after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_64 (0x1u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. */ +#define SDRAMC_LPR_TIMEOUT_LP_LAST_XFER_128 (0x2u << 12) /**< \brief (SDRAMC_LPR) The SDRAMC activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. */ +/* -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAMC Interrupt Enable Register -------- */ +#define SDRAMC_IER_RES (0x1u << 0) /**< \brief (SDRAMC_IER) Refresh Error Status */ +/* -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAMC Interrupt Disable Register -------- */ +#define SDRAMC_IDR_RES (0x1u << 0) /**< \brief (SDRAMC_IDR) Refresh Error Status */ +/* -------- SDRAMC_IMR : (SDRAMC Offset: 0x1C) SDRAMC Interrupt Mask Register -------- */ +#define SDRAMC_IMR_RES (0x1u << 0) /**< \brief (SDRAMC_IMR) Refresh Error Status */ +/* -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAMC Interrupt Status Register -------- */ +#define SDRAMC_ISR_RES (0x1u << 0) /**< \brief (SDRAMC_ISR) Refresh Error Status (cleared on read) */ +/* -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAMC Memory Device Register -------- */ +#define SDRAMC_MDR_MD_Pos 0 +#define SDRAMC_MDR_MD_Msk (0x3u << SDRAMC_MDR_MD_Pos) /**< \brief (SDRAMC_MDR) Memory Device Type */ +#define SDRAMC_MDR_MD(value) ((SDRAMC_MDR_MD_Msk & ((value) << SDRAMC_MDR_MD_Pos))) +#define SDRAMC_MDR_MD_SDRAM (0x0u << 0) /**< \brief (SDRAMC_MDR) SDRAM */ +#define SDRAMC_MDR_MD_LPSDRAM (0x1u << 0) /**< \brief (SDRAMC_MDR) Low-power SDRAM */ +/* -------- SDRAMC_CFR1 : (SDRAMC Offset: 0x28) SDRAMC Configuration Register 1 -------- */ +#define SDRAMC_CFR1_TMRD_Pos 0 +#define SDRAMC_CFR1_TMRD_Msk (0xfu << SDRAMC_CFR1_TMRD_Pos) /**< \brief (SDRAMC_CFR1) Load Mode Register Command to Active or Refresh Command */ +#define SDRAMC_CFR1_TMRD(value) ((SDRAMC_CFR1_TMRD_Msk & ((value) << SDRAMC_CFR1_TMRD_Pos))) +#define SDRAMC_CFR1_UNAL (0x1u << 8) /**< \brief (SDRAMC_CFR1) Support Unaligned Access */ +#define SDRAMC_CFR1_UNAL_UNSUPPORTED (0x0u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is not supported. */ +#define SDRAMC_CFR1_UNAL_SUPPORTED (0x1u << 8) /**< \brief (SDRAMC_CFR1) Unaligned access is supported. */ +/* -------- SDRAMC_OCMS : (SDRAMC Offset: 0x2C) SDRAMC OCMS Register -------- */ +#define SDRAMC_OCMS_SDR_SE (0x1u << 0) /**< \brief (SDRAMC_OCMS) SDRAM Memory Controller Scrambling Enable */ +/* -------- SDRAMC_OCMS_KEY1 : (SDRAMC Offset: 0x30) SDRAMC OCMS KEY1 Register -------- */ +#define SDRAMC_OCMS_KEY1_KEY1_Pos 0 +#define SDRAMC_OCMS_KEY1_KEY1_Msk (0xffffffffu << SDRAMC_OCMS_KEY1_KEY1_Pos) /**< \brief (SDRAMC_OCMS_KEY1) Off-chip Memory Scrambling (OCMS) Key Part 1 */ +#define SDRAMC_OCMS_KEY1_KEY1(value) ((SDRAMC_OCMS_KEY1_KEY1_Msk & ((value) << SDRAMC_OCMS_KEY1_KEY1_Pos))) +/* -------- SDRAMC_OCMS_KEY2 : (SDRAMC Offset: 0x34) SDRAMC OCMS KEY2 Register -------- */ +#define SDRAMC_OCMS_KEY2_KEY2_Pos 0 +#define SDRAMC_OCMS_KEY2_KEY2_Msk (0xffffffffu << SDRAMC_OCMS_KEY2_KEY2_Pos) /**< \brief (SDRAMC_OCMS_KEY2) Off-chip Memory Scrambling (OCMS) Key Part 2 */ +#define SDRAMC_OCMS_KEY2_KEY2(value) ((SDRAMC_OCMS_KEY2_KEY2_Msk & ((value) << SDRAMC_OCMS_KEY2_KEY2_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_SDRAMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_smc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_smc.h new file mode 100644 index 000000000..7ff678b40 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_smc.h @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SMC_COMPONENT_ +#define _SAMV71_SMC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Static Memory Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SMC Static Memory Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief SmcCs_number hardware registers */ +typedef struct { + __IO uint32_t SMC_SETUP; /**< \brief (SmcCs_number Offset: 0x0) SMC Setup Register */ + __IO uint32_t SMC_PULSE; /**< \brief (SmcCs_number Offset: 0x4) SMC Pulse Register */ + __IO uint32_t SMC_CYCLE; /**< \brief (SmcCs_number Offset: 0x8) SMC Cycle Register */ + __IO uint32_t SMC_MODE; /**< \brief (SmcCs_number Offset: 0xC) SMC MODE Register */ +} SmcCs_number; +/** \brief Smc hardware registers */ +#define SMCCS_NUMBER_NUMBER 4 +typedef struct { + SmcCs_number SMC_CS_NUMBER[SMCCS_NUMBER_NUMBER]; /**< \brief (Smc Offset: 0x0) CS_number = 0 .. 3 */ + __I uint32_t Reserved1[16]; + __IO uint32_t SMC_OCMS; /**< \brief (Smc Offset: 0x80) SMC OCMS MODE Register */ + __O uint32_t SMC_KEY1; /**< \brief (Smc Offset: 0x84) SMC OCMS KEY1 Register */ + __O uint32_t SMC_KEY2; /**< \brief (Smc Offset: 0x88) SMC OCMS KEY2 Register */ + __I uint32_t Reserved2[22]; + __IO uint32_t SMC_WPMR; /**< \brief (Smc Offset: 0xE4) SMC Write Protection Mode Register */ + __I uint32_t SMC_WPSR; /**< \brief (Smc Offset: 0xE8) SMC Write Protection Status Register */ +} Smc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SMC_SETUP : (SMC Offset: N/A) SMC Setup Register -------- */ +#define SMC_SETUP_NWE_SETUP_Pos 0 +#define SMC_SETUP_NWE_SETUP_Msk (0x3fu << SMC_SETUP_NWE_SETUP_Pos) /**< \brief (SMC_SETUP) NWE Setup Length */ +#define SMC_SETUP_NWE_SETUP(value) ((SMC_SETUP_NWE_SETUP_Msk & ((value) << SMC_SETUP_NWE_SETUP_Pos))) +#define SMC_SETUP_NCS_WR_SETUP_Pos 8 +#define SMC_SETUP_NCS_WR_SETUP_Msk (0x3fu << SMC_SETUP_NCS_WR_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in WRITE Access */ +#define SMC_SETUP_NCS_WR_SETUP(value) ((SMC_SETUP_NCS_WR_SETUP_Msk & ((value) << SMC_SETUP_NCS_WR_SETUP_Pos))) +#define SMC_SETUP_NRD_SETUP_Pos 16 +#define SMC_SETUP_NRD_SETUP_Msk (0x3fu << SMC_SETUP_NRD_SETUP_Pos) /**< \brief (SMC_SETUP) NRD Setup Length */ +#define SMC_SETUP_NRD_SETUP(value) ((SMC_SETUP_NRD_SETUP_Msk & ((value) << SMC_SETUP_NRD_SETUP_Pos))) +#define SMC_SETUP_NCS_RD_SETUP_Pos 24 +#define SMC_SETUP_NCS_RD_SETUP_Msk (0x3fu << SMC_SETUP_NCS_RD_SETUP_Pos) /**< \brief (SMC_SETUP) NCS Setup Length in READ Access */ +#define SMC_SETUP_NCS_RD_SETUP(value) ((SMC_SETUP_NCS_RD_SETUP_Msk & ((value) << SMC_SETUP_NCS_RD_SETUP_Pos))) +/* -------- SMC_PULSE : (SMC Offset: N/A) SMC Pulse Register -------- */ +#define SMC_PULSE_NWE_PULSE_Pos 0 +#define SMC_PULSE_NWE_PULSE_Msk (0x7fu << SMC_PULSE_NWE_PULSE_Pos) /**< \brief (SMC_PULSE) NWE Pulse Length */ +#define SMC_PULSE_NWE_PULSE(value) ((SMC_PULSE_NWE_PULSE_Msk & ((value) << SMC_PULSE_NWE_PULSE_Pos))) +#define SMC_PULSE_NCS_WR_PULSE_Pos 8 +#define SMC_PULSE_NCS_WR_PULSE_Msk (0x7fu << SMC_PULSE_NCS_WR_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in WRITE Access */ +#define SMC_PULSE_NCS_WR_PULSE(value) ((SMC_PULSE_NCS_WR_PULSE_Msk & ((value) << SMC_PULSE_NCS_WR_PULSE_Pos))) +#define SMC_PULSE_NRD_PULSE_Pos 16 +#define SMC_PULSE_NRD_PULSE_Msk (0x7fu << SMC_PULSE_NRD_PULSE_Pos) /**< \brief (SMC_PULSE) NRD Pulse Length */ +#define SMC_PULSE_NRD_PULSE(value) ((SMC_PULSE_NRD_PULSE_Msk & ((value) << SMC_PULSE_NRD_PULSE_Pos))) +#define SMC_PULSE_NCS_RD_PULSE_Pos 24 +#define SMC_PULSE_NCS_RD_PULSE_Msk (0x7fu << SMC_PULSE_NCS_RD_PULSE_Pos) /**< \brief (SMC_PULSE) NCS Pulse Length in READ Access */ +#define SMC_PULSE_NCS_RD_PULSE(value) ((SMC_PULSE_NCS_RD_PULSE_Msk & ((value) << SMC_PULSE_NCS_RD_PULSE_Pos))) +/* -------- SMC_CYCLE : (SMC Offset: N/A) SMC Cycle Register -------- */ +#define SMC_CYCLE_NWE_CYCLE_Pos 0 +#define SMC_CYCLE_NWE_CYCLE_Msk (0x1ffu << SMC_CYCLE_NWE_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Write Cycle Length */ +#define SMC_CYCLE_NWE_CYCLE(value) ((SMC_CYCLE_NWE_CYCLE_Msk & ((value) << SMC_CYCLE_NWE_CYCLE_Pos))) +#define SMC_CYCLE_NRD_CYCLE_Pos 16 +#define SMC_CYCLE_NRD_CYCLE_Msk (0x1ffu << SMC_CYCLE_NRD_CYCLE_Pos) /**< \brief (SMC_CYCLE) Total Read Cycle Length */ +#define SMC_CYCLE_NRD_CYCLE(value) ((SMC_CYCLE_NRD_CYCLE_Msk & ((value) << SMC_CYCLE_NRD_CYCLE_Pos))) +/* -------- SMC_MODE : (SMC Offset: N/A) SMC MODE Register -------- */ +#define SMC_MODE_READ_MODE (0x1u << 0) /**< \brief (SMC_MODE) Read Mode */ +#define SMC_MODE_WRITE_MODE (0x1u << 1) /**< \brief (SMC_MODE) Write Mode */ +#define SMC_MODE_EXNW_MODE_Pos 4 +#define SMC_MODE_EXNW_MODE_Msk (0x3u << SMC_MODE_EXNW_MODE_Pos) /**< \brief (SMC_MODE) NWAIT Mode */ +#define SMC_MODE_EXNW_MODE(value) ((SMC_MODE_EXNW_MODE_Msk & ((value) << SMC_MODE_EXNW_MODE_Pos))) +#define SMC_MODE_EXNW_MODE_DISABLED (0x0u << 4) /**< \brief (SMC_MODE) Disabled */ +#define SMC_MODE_EXNW_MODE_FROZEN (0x2u << 4) /**< \brief (SMC_MODE) Frozen Mode */ +#define SMC_MODE_EXNW_MODE_READY (0x3u << 4) /**< \brief (SMC_MODE) Ready Mode */ +#define SMC_MODE_BAT (0x1u << 8) /**< \brief (SMC_MODE) Byte Access Type */ +#define SMC_MODE_BAT_BYTE_SELECT (0x0u << 8) /**< \brief (SMC_MODE) Byte select access type:- Write operation is controlled using NCS, NWE, NBS0, NBS1.- Read operation is controlled using NCS, NRD, NBS0, NBS1. */ +#define SMC_MODE_BAT_BYTE_WRITE (0x1u << 8) /**< \brief (SMC_MODE) Byte write access type:- Write operation is controlled using NCS, NWR0, NWR1.- Read operation is controlled using NCS and NRD. */ +#define SMC_MODE_DBW (0x1u << 12) /**< \brief (SMC_MODE) Data Bus Width */ +#define SMC_MODE_DBW_8_BIT (0x0u << 12) /**< \brief (SMC_MODE) 8-bit Data Bus */ +#define SMC_MODE_DBW_16_BIT (0x1u << 12) /**< \brief (SMC_MODE) 16-bit Data Bus */ +#define SMC_MODE_TDF_CYCLES_Pos 16 +#define SMC_MODE_TDF_CYCLES_Msk (0xfu << SMC_MODE_TDF_CYCLES_Pos) /**< \brief (SMC_MODE) Data Float Time */ +#define SMC_MODE_TDF_CYCLES(value) ((SMC_MODE_TDF_CYCLES_Msk & ((value) << SMC_MODE_TDF_CYCLES_Pos))) +#define SMC_MODE_TDF_MODE (0x1u << 20) /**< \brief (SMC_MODE) TDF Optimization */ +#define SMC_MODE_PMEN (0x1u << 24) /**< \brief (SMC_MODE) Page Mode Enabled */ +#define SMC_MODE_PS_Pos 28 +#define SMC_MODE_PS_Msk (0x3u << SMC_MODE_PS_Pos) /**< \brief (SMC_MODE) Page Size */ +#define SMC_MODE_PS(value) ((SMC_MODE_PS_Msk & ((value) << SMC_MODE_PS_Pos))) +#define SMC_MODE_PS_4_BYTE (0x0u << 28) /**< \brief (SMC_MODE) 4-byte page */ +#define SMC_MODE_PS_8_BYTE (0x1u << 28) /**< \brief (SMC_MODE) 8-byte page */ +#define SMC_MODE_PS_16_BYTE (0x2u << 28) /**< \brief (SMC_MODE) 16-byte page */ +#define SMC_MODE_PS_32_BYTE (0x3u << 28) /**< \brief (SMC_MODE) 32-byte page */ +/* -------- SMC_OCMS : (SMC Offset: 0x80) SMC OCMS MODE Register -------- */ +#define SMC_OCMS_SMSE (0x1u << 0) /**< \brief (SMC_OCMS) Static Memory Controller Scrambling Enable */ +/* -------- SMC_KEY1 : (SMC Offset: 0x84) SMC OCMS KEY1 Register -------- */ +#define SMC_KEY1_KEY1_Pos 0 +#define SMC_KEY1_KEY1_Msk (0xffffffffu << SMC_KEY1_KEY1_Pos) /**< \brief (SMC_KEY1) Off Chip Memory Scrambling (OCMS) Key Part 1 */ +#define SMC_KEY1_KEY1(value) ((SMC_KEY1_KEY1_Msk & ((value) << SMC_KEY1_KEY1_Pos))) +/* -------- SMC_KEY2 : (SMC Offset: 0x88) SMC OCMS KEY2 Register -------- */ +#define SMC_KEY2_KEY2_Pos 0 +#define SMC_KEY2_KEY2_Msk (0xffffffffu << SMC_KEY2_KEY2_Pos) /**< \brief (SMC_KEY2) Off Chip Memory Scrambling (OCMS) Key Part 2 */ +#define SMC_KEY2_KEY2(value) ((SMC_KEY2_KEY2_Msk & ((value) << SMC_KEY2_KEY2_Pos))) +/* -------- SMC_WPMR : (SMC Offset: 0xE4) SMC Write Protection Mode Register -------- */ +#define SMC_WPMR_WPEN (0x1u << 0) /**< \brief (SMC_WPMR) Write Protect Enable */ +#define SMC_WPMR_WPKEY_Pos 8 +#define SMC_WPMR_WPKEY_Msk (0xffffffu << SMC_WPMR_WPKEY_Pos) /**< \brief (SMC_WPMR) Write Protection Key */ +#define SMC_WPMR_WPKEY(value) ((SMC_WPMR_WPKEY_Msk & ((value) << SMC_WPMR_WPKEY_Pos))) +#define SMC_WPMR_WPKEY_PASSWD (0x534D43u << 8) /**< \brief (SMC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- SMC_WPSR : (SMC Offset: 0xE8) SMC Write Protection Status Register -------- */ +#define SMC_WPSR_WPVS (0x1u << 0) /**< \brief (SMC_WPSR) Write Protection Violation Status */ +#define SMC_WPSR_WPVSRC_Pos 8 +#define SMC_WPSR_WPVSRC_Msk (0xffffu << SMC_WPSR_WPVSRC_Pos) /**< \brief (SMC_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_SMC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_spi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_spi.h new file mode 100644 index 000000000..fd7511022 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_spi.h @@ -0,0 +1,161 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI_COMPONENT_ +#define _SAMV71_SPI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SPI Serial Peripheral Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Spi hardware registers */ +typedef struct { + __O uint32_t SPI_CR; /**< \brief (Spi Offset: 0x00) Control Register */ + __IO uint32_t SPI_MR; /**< \brief (Spi Offset: 0x04) Mode Register */ + __I uint32_t SPI_RDR; /**< \brief (Spi Offset: 0x08) Receive Data Register */ + __O uint32_t SPI_TDR; /**< \brief (Spi Offset: 0x0C) Transmit Data Register */ + __I uint32_t SPI_SR; /**< \brief (Spi Offset: 0x10) Status Register */ + __O uint32_t SPI_IER; /**< \brief (Spi Offset: 0x14) Interrupt Enable Register */ + __O uint32_t SPI_IDR; /**< \brief (Spi Offset: 0x18) Interrupt Disable Register */ + __I uint32_t SPI_IMR; /**< \brief (Spi Offset: 0x1C) Interrupt Mask Register */ + __I uint32_t Reserved1[4]; + __IO uint32_t SPI_CSR[4]; /**< \brief (Spi Offset: 0x30) Chip Select Register */ + __I uint32_t Reserved2[41]; + __IO uint32_t SPI_WPMR; /**< \brief (Spi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SPI_WPSR; /**< \brief (Spi Offset: 0xE8) Write Protection Status Register */ +} Spi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ +#define SPI_CR_SPIEN (0x1u << 0) /**< \brief (SPI_CR) SPI Enable */ +#define SPI_CR_SPIDIS (0x1u << 1) /**< \brief (SPI_CR) SPI Disable */ +#define SPI_CR_SWRST (0x1u << 7) /**< \brief (SPI_CR) SPI Software Reset */ +#define SPI_CR_LASTXFER (0x1u << 24) /**< \brief (SPI_CR) Last Transfer */ +/* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ +#define SPI_MR_MSTR (0x1u << 0) /**< \brief (SPI_MR) Master/Slave Mode */ +#define SPI_MR_PS (0x1u << 1) /**< \brief (SPI_MR) Peripheral Select */ +#define SPI_MR_PCSDEC (0x1u << 2) /**< \brief (SPI_MR) Chip Select Decode */ +#define SPI_MR_MODFDIS (0x1u << 4) /**< \brief (SPI_MR) Mode Fault Detection */ +#define SPI_MR_WDRBT (0x1u << 5) /**< \brief (SPI_MR) Wait Data Read Before Transfer */ +#define SPI_MR_LLB (0x1u << 7) /**< \brief (SPI_MR) Local Loopback Enable */ +#define SPI_MR_PCS_Pos 16 +#define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /**< \brief (SPI_MR) Peripheral Chip Select */ +#define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) +#define SPI_MR_DLYBCS_Pos 24 +#define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /**< \brief (SPI_MR) Delay Between Chip Selects */ +#define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) +/* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ +#define SPI_RDR_RD_Pos 0 +#define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /**< \brief (SPI_RDR) Receive Data */ +#define SPI_RDR_PCS_Pos 16 +#define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /**< \brief (SPI_RDR) Peripheral Chip Select */ +/* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ +#define SPI_TDR_TD_Pos 0 +#define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /**< \brief (SPI_TDR) Transmit Data */ +#define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) +#define SPI_TDR_PCS_Pos 16 +#define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /**< \brief (SPI_TDR) Peripheral Chip Select */ +#define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) +#define SPI_TDR_LASTXFER (0x1u << 24) /**< \brief (SPI_TDR) Last Transfer */ +/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ +#define SPI_SR_RDRF (0x1u << 0) /**< \brief (SPI_SR) Receive Data Register Full (cleared by reading SPI_RDR) */ +#define SPI_SR_TDRE (0x1u << 1) /**< \brief (SPI_SR) Transmit Data Register Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_MODF (0x1u << 2) /**< \brief (SPI_SR) Mode Fault Error (cleared on read) */ +#define SPI_SR_OVRES (0x1u << 3) /**< \brief (SPI_SR) Overrun Error Status (cleared on read) */ +#define SPI_SR_NSSR (0x1u << 8) /**< \brief (SPI_SR) NSS Rising (cleared on read) */ +#define SPI_SR_TXEMPTY (0x1u << 9) /**< \brief (SPI_SR) Transmission Registers Empty (cleared by writing SPI_TDR) */ +#define SPI_SR_UNDES (0x1u << 10) /**< \brief (SPI_SR) Underrun Error Status (Slave mode only) (cleared on read) */ +#define SPI_SR_SPIENS (0x1u << 16) /**< \brief (SPI_SR) SPI Enable Status */ +/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ +#define SPI_IER_RDRF (0x1u << 0) /**< \brief (SPI_IER) Receive Data Register Full Interrupt Enable */ +#define SPI_IER_TDRE (0x1u << 1) /**< \brief (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ +#define SPI_IER_MODF (0x1u << 2) /**< \brief (SPI_IER) Mode Fault Error Interrupt Enable */ +#define SPI_IER_OVRES (0x1u << 3) /**< \brief (SPI_IER) Overrun Error Interrupt Enable */ +#define SPI_IER_NSSR (0x1u << 8) /**< \brief (SPI_IER) NSS Rising Interrupt Enable */ +#define SPI_IER_TXEMPTY (0x1u << 9) /**< \brief (SPI_IER) Transmission Registers Empty Enable */ +#define SPI_IER_UNDES (0x1u << 10) /**< \brief (SPI_IER) Underrun Error Interrupt Enable */ +/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ +#define SPI_IDR_RDRF (0x1u << 0) /**< \brief (SPI_IDR) Receive Data Register Full Interrupt Disable */ +#define SPI_IDR_TDRE (0x1u << 1) /**< \brief (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ +#define SPI_IDR_MODF (0x1u << 2) /**< \brief (SPI_IDR) Mode Fault Error Interrupt Disable */ +#define SPI_IDR_OVRES (0x1u << 3) /**< \brief (SPI_IDR) Overrun Error Interrupt Disable */ +#define SPI_IDR_NSSR (0x1u << 8) /**< \brief (SPI_IDR) NSS Rising Interrupt Disable */ +#define SPI_IDR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IDR) Transmission Registers Empty Disable */ +#define SPI_IDR_UNDES (0x1u << 10) /**< \brief (SPI_IDR) Underrun Error Interrupt Disable */ +/* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ +#define SPI_IMR_RDRF (0x1u << 0) /**< \brief (SPI_IMR) Receive Data Register Full Interrupt Mask */ +#define SPI_IMR_TDRE (0x1u << 1) /**< \brief (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ +#define SPI_IMR_MODF (0x1u << 2) /**< \brief (SPI_IMR) Mode Fault Error Interrupt Mask */ +#define SPI_IMR_OVRES (0x1u << 3) /**< \brief (SPI_IMR) Overrun Error Interrupt Mask */ +#define SPI_IMR_NSSR (0x1u << 8) /**< \brief (SPI_IMR) NSS Rising Interrupt Mask */ +#define SPI_IMR_TXEMPTY (0x1u << 9) /**< \brief (SPI_IMR) Transmission Registers Empty Mask */ +#define SPI_IMR_UNDES (0x1u << 10) /**< \brief (SPI_IMR) Underrun Error Interrupt Mask */ +/* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ +#define SPI_CSR_CPOL (0x1u << 0) /**< \brief (SPI_CSR[4]) Clock Polarity */ +#define SPI_CSR_NCPHA (0x1u << 1) /**< \brief (SPI_CSR[4]) Clock Phase */ +#define SPI_CSR_CSNAAT (0x1u << 2) /**< \brief (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ +#define SPI_CSR_CSAAT (0x1u << 3) /**< \brief (SPI_CSR[4]) Chip Select Active After Transfer */ +#define SPI_CSR_BITS_Pos 4 +#define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /**< \brief (SPI_CSR[4]) Bits Per Transfer */ +#define SPI_CSR_BITS(value) ((SPI_CSR_BITS_Msk & ((value) << SPI_CSR_BITS_Pos))) +#define SPI_CSR_BITS_8_BIT (0x0u << 4) /**< \brief (SPI_CSR[4]) 8 bits for transfer */ +#define SPI_CSR_BITS_9_BIT (0x1u << 4) /**< \brief (SPI_CSR[4]) 9 bits for transfer */ +#define SPI_CSR_BITS_10_BIT (0x2u << 4) /**< \brief (SPI_CSR[4]) 10 bits for transfer */ +#define SPI_CSR_BITS_11_BIT (0x3u << 4) /**< \brief (SPI_CSR[4]) 11 bits for transfer */ +#define SPI_CSR_BITS_12_BIT (0x4u << 4) /**< \brief (SPI_CSR[4]) 12 bits for transfer */ +#define SPI_CSR_BITS_13_BIT (0x5u << 4) /**< \brief (SPI_CSR[4]) 13 bits for transfer */ +#define SPI_CSR_BITS_14_BIT (0x6u << 4) /**< \brief (SPI_CSR[4]) 14 bits for transfer */ +#define SPI_CSR_BITS_15_BIT (0x7u << 4) /**< \brief (SPI_CSR[4]) 15 bits for transfer */ +#define SPI_CSR_BITS_16_BIT (0x8u << 4) /**< \brief (SPI_CSR[4]) 16 bits for transfer */ +#define SPI_CSR_SCBR_Pos 8 +#define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /**< \brief (SPI_CSR[4]) Serial Clock Bit Rate */ +#define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) +#define SPI_CSR_DLYBS_Pos 16 +#define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /**< \brief (SPI_CSR[4]) Delay Before SPCK */ +#define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) +#define SPI_CSR_DLYBCT_Pos 24 +#define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /**< \brief (SPI_CSR[4]) Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) +/* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Mode Register -------- */ +#define SPI_WPMR_WPEN (0x1u << 0) /**< \brief (SPI_WPMR) Write Protection Enable */ +#define SPI_WPMR_WPKEY_Pos 8 +#define SPI_WPMR_WPKEY_Msk (0xffffffu << SPI_WPMR_WPKEY_Pos) /**< \brief (SPI_WPMR) Write Protection Key */ +#define SPI_WPMR_WPKEY(value) ((SPI_WPMR_WPKEY_Msk & ((value) << SPI_WPMR_WPKEY_Pos))) +#define SPI_WPMR_WPKEY_PASSWD (0x535049u << 8) /**< \brief (SPI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ +#define SPI_WPSR_WPVS (0x1u << 0) /**< \brief (SPI_WPSR) Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_Pos 8 +#define SPI_WPSR_WPVSRC_Msk (0xffu << SPI_WPSR_WPVSRC_Pos) /**< \brief (SPI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_SPI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_ssc.h new file mode 100644 index 000000000..cc24217fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_ssc.h @@ -0,0 +1,280 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SSC_COMPONENT_ +#define _SAMV71_SSC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Synchronous Serial Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SSC Synchronous Serial Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Ssc hardware registers */ +typedef struct { + __O uint32_t SSC_CR; /**< \brief (Ssc Offset: 0x0) Control Register */ + __IO uint32_t SSC_CMR; /**< \brief (Ssc Offset: 0x4) Clock Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t SSC_RCMR; /**< \brief (Ssc Offset: 0x10) Receive Clock Mode Register */ + __IO uint32_t SSC_RFMR; /**< \brief (Ssc Offset: 0x14) Receive Frame Mode Register */ + __IO uint32_t SSC_TCMR; /**< \brief (Ssc Offset: 0x18) Transmit Clock Mode Register */ + __IO uint32_t SSC_TFMR; /**< \brief (Ssc Offset: 0x1C) Transmit Frame Mode Register */ + __I uint32_t SSC_RHR; /**< \brief (Ssc Offset: 0x20) Receive Holding Register */ + __O uint32_t SSC_THR; /**< \brief (Ssc Offset: 0x24) Transmit Holding Register */ + __I uint32_t Reserved2[2]; + __I uint32_t SSC_RSHR; /**< \brief (Ssc Offset: 0x30) Receive Sync. Holding Register */ + __IO uint32_t SSC_TSHR; /**< \brief (Ssc Offset: 0x34) Transmit Sync. Holding Register */ + __IO uint32_t SSC_RC0R; /**< \brief (Ssc Offset: 0x38) Receive Compare 0 Register */ + __IO uint32_t SSC_RC1R; /**< \brief (Ssc Offset: 0x3C) Receive Compare 1 Register */ + __I uint32_t SSC_SR; /**< \brief (Ssc Offset: 0x40) Status Register */ + __O uint32_t SSC_IER; /**< \brief (Ssc Offset: 0x44) Interrupt Enable Register */ + __O uint32_t SSC_IDR; /**< \brief (Ssc Offset: 0x48) Interrupt Disable Register */ + __I uint32_t SSC_IMR; /**< \brief (Ssc Offset: 0x4C) Interrupt Mask Register */ + __I uint32_t Reserved3[37]; + __IO uint32_t SSC_WPMR; /**< \brief (Ssc Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t SSC_WPSR; /**< \brief (Ssc Offset: 0xE8) Write Protection Status Register */ +} Ssc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SSC_CR : (SSC Offset: 0x0) Control Register -------- */ +#define SSC_CR_RXEN (0x1u << 0) /**< \brief (SSC_CR) Receive Enable */ +#define SSC_CR_RXDIS (0x1u << 1) /**< \brief (SSC_CR) Receive Disable */ +#define SSC_CR_TXEN (0x1u << 8) /**< \brief (SSC_CR) Transmit Enable */ +#define SSC_CR_TXDIS (0x1u << 9) /**< \brief (SSC_CR) Transmit Disable */ +#define SSC_CR_SWRST (0x1u << 15) /**< \brief (SSC_CR) Software Reset */ +/* -------- SSC_CMR : (SSC Offset: 0x4) Clock Mode Register -------- */ +#define SSC_CMR_DIV_Pos 0 +#define SSC_CMR_DIV_Msk (0xfffu << SSC_CMR_DIV_Pos) /**< \brief (SSC_CMR) Clock Divider */ +#define SSC_CMR_DIV(value) ((SSC_CMR_DIV_Msk & ((value) << SSC_CMR_DIV_Pos))) +/* -------- SSC_RCMR : (SSC Offset: 0x10) Receive Clock Mode Register -------- */ +#define SSC_RCMR_CKS_Pos 0 +#define SSC_RCMR_CKS_Msk (0x3u << SSC_RCMR_CKS_Pos) /**< \brief (SSC_RCMR) Receive Clock Selection */ +#define SSC_RCMR_CKS(value) ((SSC_RCMR_CKS_Msk & ((value) << SSC_RCMR_CKS_Pos))) +#define SSC_RCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_RCMR) Divided Clock */ +#define SSC_RCMR_CKS_TK (0x1u << 0) /**< \brief (SSC_RCMR) TK Clock signal */ +#define SSC_RCMR_CKS_RK (0x2u << 0) /**< \brief (SSC_RCMR) RK pin */ +#define SSC_RCMR_CKO_Pos 2 +#define SSC_RCMR_CKO_Msk (0x7u << SSC_RCMR_CKO_Pos) /**< \brief (SSC_RCMR) Receive Clock Output Mode Selection */ +#define SSC_RCMR_CKO(value) ((SSC_RCMR_CKO_Msk & ((value) << SSC_RCMR_CKO_Pos))) +#define SSC_RCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_RCMR) None, RK pin is an input */ +#define SSC_RCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_RCMR) Continuous Receive Clock, RK pin is an output */ +#define SSC_RCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_RCMR) Receive Clock only during data transfers, RK pin is an output */ +#define SSC_RCMR_CKI (0x1u << 5) /**< \brief (SSC_RCMR) Receive Clock Inversion */ +#define SSC_RCMR_CKG_Pos 6 +#define SSC_RCMR_CKG_Msk (0x3u << SSC_RCMR_CKG_Pos) /**< \brief (SSC_RCMR) Receive Clock Gating Selection */ +#define SSC_RCMR_CKG(value) ((SSC_RCMR_CKG_Msk & ((value) << SSC_RCMR_CKG_Pos))) +#define SSC_RCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_RCMR) None */ +#define SSC_RCMR_CKG_EN_RF_LOW (0x1u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF Low */ +#define SSC_RCMR_CKG_EN_RF_HIGH (0x2u << 6) /**< \brief (SSC_RCMR) Receive Clock enabled only if RF High */ +#define SSC_RCMR_START_Pos 8 +#define SSC_RCMR_START_Msk (0xfu << SSC_RCMR_START_Pos) /**< \brief (SSC_RCMR) Receive Start Selection */ +#define SSC_RCMR_START(value) ((SSC_RCMR_START_Msk & ((value) << SSC_RCMR_START_Pos))) +#define SSC_RCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_RCMR) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. */ +#define SSC_RCMR_START_TRANSMIT (0x1u << 8) /**< \brief (SSC_RCMR) Transmit start */ +#define SSC_RCMR_START_RF_LOW (0x2u << 8) /**< \brief (SSC_RCMR) Detection of a low level on RF signal */ +#define SSC_RCMR_START_RF_HIGH (0x3u << 8) /**< \brief (SSC_RCMR) Detection of a high level on RF signal */ +#define SSC_RCMR_START_RF_FALLING (0x4u << 8) /**< \brief (SSC_RCMR) Detection of a falling edge on RF signal */ +#define SSC_RCMR_START_RF_RISING (0x5u << 8) /**< \brief (SSC_RCMR) Detection of a rising edge on RF signal */ +#define SSC_RCMR_START_RF_LEVEL (0x6u << 8) /**< \brief (SSC_RCMR) Detection of any level change on RF signal */ +#define SSC_RCMR_START_RF_EDGE (0x7u << 8) /**< \brief (SSC_RCMR) Detection of any edge on RF signal */ +#define SSC_RCMR_START_CMP_0 (0x8u << 8) /**< \brief (SSC_RCMR) Compare 0 */ +#define SSC_RCMR_STOP (0x1u << 12) /**< \brief (SSC_RCMR) Receive Stop Selection */ +#define SSC_RCMR_STTDLY_Pos 16 +#define SSC_RCMR_STTDLY_Msk (0xffu << SSC_RCMR_STTDLY_Pos) /**< \brief (SSC_RCMR) Receive Start Delay */ +#define SSC_RCMR_STTDLY(value) ((SSC_RCMR_STTDLY_Msk & ((value) << SSC_RCMR_STTDLY_Pos))) +#define SSC_RCMR_PERIOD_Pos 24 +#define SSC_RCMR_PERIOD_Msk (0xffu << SSC_RCMR_PERIOD_Pos) /**< \brief (SSC_RCMR) Receive Period Divider Selection */ +#define SSC_RCMR_PERIOD(value) ((SSC_RCMR_PERIOD_Msk & ((value) << SSC_RCMR_PERIOD_Pos))) +/* -------- SSC_RFMR : (SSC Offset: 0x14) Receive Frame Mode Register -------- */ +#define SSC_RFMR_DATLEN_Pos 0 +#define SSC_RFMR_DATLEN_Msk (0x1fu << SSC_RFMR_DATLEN_Pos) /**< \brief (SSC_RFMR) Data Length */ +#define SSC_RFMR_DATLEN(value) ((SSC_RFMR_DATLEN_Msk & ((value) << SSC_RFMR_DATLEN_Pos))) +#define SSC_RFMR_LOOP (0x1u << 5) /**< \brief (SSC_RFMR) Loop Mode */ +#define SSC_RFMR_MSBF (0x1u << 7) /**< \brief (SSC_RFMR) Most Significant Bit First */ +#define SSC_RFMR_DATNB_Pos 8 +#define SSC_RFMR_DATNB_Msk (0xfu << SSC_RFMR_DATNB_Pos) /**< \brief (SSC_RFMR) Data Number per Frame */ +#define SSC_RFMR_DATNB(value) ((SSC_RFMR_DATNB_Msk & ((value) << SSC_RFMR_DATNB_Pos))) +#define SSC_RFMR_FSLEN_Pos 16 +#define SSC_RFMR_FSLEN_Msk (0xfu << SSC_RFMR_FSLEN_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Length */ +#define SSC_RFMR_FSLEN(value) ((SSC_RFMR_FSLEN_Msk & ((value) << SSC_RFMR_FSLEN_Pos))) +#define SSC_RFMR_FSOS_Pos 20 +#define SSC_RFMR_FSOS_Msk (0x7u << SSC_RFMR_FSOS_Pos) /**< \brief (SSC_RFMR) Receive Frame Sync Output Selection */ +#define SSC_RFMR_FSOS(value) ((SSC_RFMR_FSOS_Msk & ((value) << SSC_RFMR_FSOS_Pos))) +#define SSC_RFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_RFMR) None, RF pin is an input */ +#define SSC_RFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_RFMR) Negative Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_RFMR) Positive Pulse, RF pin is an output */ +#define SSC_RFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_RFMR) Driven Low during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_RFMR) Driven High during data transfer, RF pin is an output */ +#define SSC_RFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_RFMR) Toggling at each start of data transfer, RF pin is an output */ +#define SSC_RFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_RFMR) Frame Sync Edge Detection */ +#define SSC_RFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_RFMR) Positive Edge Detection */ +#define SSC_RFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_RFMR) Negative Edge Detection */ +#define SSC_RFMR_FSLEN_EXT_Pos 28 +#define SSC_RFMR_FSLEN_EXT_Msk (0xfu << SSC_RFMR_FSLEN_EXT_Pos) /**< \brief (SSC_RFMR) FSLEN Field Extension */ +#define SSC_RFMR_FSLEN_EXT(value) ((SSC_RFMR_FSLEN_EXT_Msk & ((value) << SSC_RFMR_FSLEN_EXT_Pos))) +/* -------- SSC_TCMR : (SSC Offset: 0x18) Transmit Clock Mode Register -------- */ +#define SSC_TCMR_CKS_Pos 0 +#define SSC_TCMR_CKS_Msk (0x3u << SSC_TCMR_CKS_Pos) /**< \brief (SSC_TCMR) Transmit Clock Selection */ +#define SSC_TCMR_CKS(value) ((SSC_TCMR_CKS_Msk & ((value) << SSC_TCMR_CKS_Pos))) +#define SSC_TCMR_CKS_MCK (0x0u << 0) /**< \brief (SSC_TCMR) Divided Clock */ +#define SSC_TCMR_CKS_RK (0x1u << 0) /**< \brief (SSC_TCMR) RK Clock signal */ +#define SSC_TCMR_CKS_TK (0x2u << 0) /**< \brief (SSC_TCMR) TK pin */ +#define SSC_TCMR_CKO_Pos 2 +#define SSC_TCMR_CKO_Msk (0x7u << SSC_TCMR_CKO_Pos) /**< \brief (SSC_TCMR) Transmit Clock Output Mode Selection */ +#define SSC_TCMR_CKO(value) ((SSC_TCMR_CKO_Msk & ((value) << SSC_TCMR_CKO_Pos))) +#define SSC_TCMR_CKO_NONE (0x0u << 2) /**< \brief (SSC_TCMR) None, TK pin is an input */ +#define SSC_TCMR_CKO_CONTINUOUS (0x1u << 2) /**< \brief (SSC_TCMR) Continuous Transmit Clock, TK pin is an output */ +#define SSC_TCMR_CKO_TRANSFER (0x2u << 2) /**< \brief (SSC_TCMR) Transmit Clock only during data transfers, TK pin is an output */ +#define SSC_TCMR_CKI (0x1u << 5) /**< \brief (SSC_TCMR) Transmit Clock Inversion */ +#define SSC_TCMR_CKG_Pos 6 +#define SSC_TCMR_CKG_Msk (0x3u << SSC_TCMR_CKG_Pos) /**< \brief (SSC_TCMR) Transmit Clock Gating Selection */ +#define SSC_TCMR_CKG(value) ((SSC_TCMR_CKG_Msk & ((value) << SSC_TCMR_CKG_Pos))) +#define SSC_TCMR_CKG_CONTINUOUS (0x0u << 6) /**< \brief (SSC_TCMR) None */ +#define SSC_TCMR_CKG_EN_TF_LOW (0x1u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF Low */ +#define SSC_TCMR_CKG_EN_TF_HIGH (0x2u << 6) /**< \brief (SSC_TCMR) Transmit Clock enabled only if TF High */ +#define SSC_TCMR_START_Pos 8 +#define SSC_TCMR_START_Msk (0xfu << SSC_TCMR_START_Pos) /**< \brief (SSC_TCMR) Transmit Start Selection */ +#define SSC_TCMR_START(value) ((SSC_TCMR_START_Msk & ((value) << SSC_TCMR_START_Pos))) +#define SSC_TCMR_START_CONTINUOUS (0x0u << 8) /**< \brief (SSC_TCMR) Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data */ +#define SSC_TCMR_START_RECEIVE (0x1u << 8) /**< \brief (SSC_TCMR) Receive start */ +#define SSC_TCMR_START_TF_LOW (0x2u << 8) /**< \brief (SSC_TCMR) Detection of a low level on TF signal */ +#define SSC_TCMR_START_TF_HIGH (0x3u << 8) /**< \brief (SSC_TCMR) Detection of a high level on TF signal */ +#define SSC_TCMR_START_TF_FALLING (0x4u << 8) /**< \brief (SSC_TCMR) Detection of a falling edge on TF signal */ +#define SSC_TCMR_START_TF_RISING (0x5u << 8) /**< \brief (SSC_TCMR) Detection of a rising edge on TF signal */ +#define SSC_TCMR_START_TF_LEVEL (0x6u << 8) /**< \brief (SSC_TCMR) Detection of any level change on TF signal */ +#define SSC_TCMR_START_TF_EDGE (0x7u << 8) /**< \brief (SSC_TCMR) Detection of any edge on TF signal */ +#define SSC_TCMR_STTDLY_Pos 16 +#define SSC_TCMR_STTDLY_Msk (0xffu << SSC_TCMR_STTDLY_Pos) /**< \brief (SSC_TCMR) Transmit Start Delay */ +#define SSC_TCMR_STTDLY(value) ((SSC_TCMR_STTDLY_Msk & ((value) << SSC_TCMR_STTDLY_Pos))) +#define SSC_TCMR_PERIOD_Pos 24 +#define SSC_TCMR_PERIOD_Msk (0xffu << SSC_TCMR_PERIOD_Pos) /**< \brief (SSC_TCMR) Transmit Period Divider Selection */ +#define SSC_TCMR_PERIOD(value) ((SSC_TCMR_PERIOD_Msk & ((value) << SSC_TCMR_PERIOD_Pos))) +/* -------- SSC_TFMR : (SSC Offset: 0x1C) Transmit Frame Mode Register -------- */ +#define SSC_TFMR_DATLEN_Pos 0 +#define SSC_TFMR_DATLEN_Msk (0x1fu << SSC_TFMR_DATLEN_Pos) /**< \brief (SSC_TFMR) Data Length */ +#define SSC_TFMR_DATLEN(value) ((SSC_TFMR_DATLEN_Msk & ((value) << SSC_TFMR_DATLEN_Pos))) +#define SSC_TFMR_DATDEF (0x1u << 5) /**< \brief (SSC_TFMR) Data Default Value */ +#define SSC_TFMR_MSBF (0x1u << 7) /**< \brief (SSC_TFMR) Most Significant Bit First */ +#define SSC_TFMR_DATNB_Pos 8 +#define SSC_TFMR_DATNB_Msk (0xfu << SSC_TFMR_DATNB_Pos) /**< \brief (SSC_TFMR) Data Number per Frame */ +#define SSC_TFMR_DATNB(value) ((SSC_TFMR_DATNB_Msk & ((value) << SSC_TFMR_DATNB_Pos))) +#define SSC_TFMR_FSLEN_Pos 16 +#define SSC_TFMR_FSLEN_Msk (0xfu << SSC_TFMR_FSLEN_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Length */ +#define SSC_TFMR_FSLEN(value) ((SSC_TFMR_FSLEN_Msk & ((value) << SSC_TFMR_FSLEN_Pos))) +#define SSC_TFMR_FSOS_Pos 20 +#define SSC_TFMR_FSOS_Msk (0x7u << SSC_TFMR_FSOS_Pos) /**< \brief (SSC_TFMR) Transmit Frame Sync Output Selection */ +#define SSC_TFMR_FSOS(value) ((SSC_TFMR_FSOS_Msk & ((value) << SSC_TFMR_FSOS_Pos))) +#define SSC_TFMR_FSOS_NONE (0x0u << 20) /**< \brief (SSC_TFMR) None, TF pin is an input */ +#define SSC_TFMR_FSOS_NEGATIVE (0x1u << 20) /**< \brief (SSC_TFMR) Negative Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_POSITIVE (0x2u << 20) /**< \brief (SSC_TFMR) Positive Pulse, TF pin is an output */ +#define SSC_TFMR_FSOS_LOW (0x3u << 20) /**< \brief (SSC_TFMR) Driven Low during data transfer */ +#define SSC_TFMR_FSOS_HIGH (0x4u << 20) /**< \brief (SSC_TFMR) Driven High during data transfer */ +#define SSC_TFMR_FSOS_TOGGLING (0x5u << 20) /**< \brief (SSC_TFMR) Toggling at each start of data transfer */ +#define SSC_TFMR_FSDEN (0x1u << 23) /**< \brief (SSC_TFMR) Frame Sync Data Enable */ +#define SSC_TFMR_FSEDGE (0x1u << 24) /**< \brief (SSC_TFMR) Frame Sync Edge Detection */ +#define SSC_TFMR_FSEDGE_POSITIVE (0x0u << 24) /**< \brief (SSC_TFMR) Positive Edge Detection */ +#define SSC_TFMR_FSEDGE_NEGATIVE (0x1u << 24) /**< \brief (SSC_TFMR) Negative Edge Detection */ +#define SSC_TFMR_FSLEN_EXT_Pos 28 +#define SSC_TFMR_FSLEN_EXT_Msk (0xfu << SSC_TFMR_FSLEN_EXT_Pos) /**< \brief (SSC_TFMR) FSLEN Field Extension */ +#define SSC_TFMR_FSLEN_EXT(value) ((SSC_TFMR_FSLEN_EXT_Msk & ((value) << SSC_TFMR_FSLEN_EXT_Pos))) +/* -------- SSC_RHR : (SSC Offset: 0x20) Receive Holding Register -------- */ +#define SSC_RHR_RDAT_Pos 0 +#define SSC_RHR_RDAT_Msk (0xffffffffu << SSC_RHR_RDAT_Pos) /**< \brief (SSC_RHR) Receive Data */ +/* -------- SSC_THR : (SSC Offset: 0x24) Transmit Holding Register -------- */ +#define SSC_THR_TDAT_Pos 0 +#define SSC_THR_TDAT_Msk (0xffffffffu << SSC_THR_TDAT_Pos) /**< \brief (SSC_THR) Transmit Data */ +#define SSC_THR_TDAT(value) ((SSC_THR_TDAT_Msk & ((value) << SSC_THR_TDAT_Pos))) +/* -------- SSC_RSHR : (SSC Offset: 0x30) Receive Sync. Holding Register -------- */ +#define SSC_RSHR_RSDAT_Pos 0 +#define SSC_RSHR_RSDAT_Msk (0xffffu << SSC_RSHR_RSDAT_Pos) /**< \brief (SSC_RSHR) Receive Synchronization Data */ +/* -------- SSC_TSHR : (SSC Offset: 0x34) Transmit Sync. Holding Register -------- */ +#define SSC_TSHR_TSDAT_Pos 0 +#define SSC_TSHR_TSDAT_Msk (0xffffu << SSC_TSHR_TSDAT_Pos) /**< \brief (SSC_TSHR) Transmit Synchronization Data */ +#define SSC_TSHR_TSDAT(value) ((SSC_TSHR_TSDAT_Msk & ((value) << SSC_TSHR_TSDAT_Pos))) +/* -------- SSC_RC0R : (SSC Offset: 0x38) Receive Compare 0 Register -------- */ +#define SSC_RC0R_CP0_Pos 0 +#define SSC_RC0R_CP0_Msk (0xffffu << SSC_RC0R_CP0_Pos) /**< \brief (SSC_RC0R) Receive Compare Data 0 */ +#define SSC_RC0R_CP0(value) ((SSC_RC0R_CP0_Msk & ((value) << SSC_RC0R_CP0_Pos))) +/* -------- SSC_RC1R : (SSC Offset: 0x3C) Receive Compare 1 Register -------- */ +#define SSC_RC1R_CP1_Pos 0 +#define SSC_RC1R_CP1_Msk (0xffffu << SSC_RC1R_CP1_Pos) /**< \brief (SSC_RC1R) Receive Compare Data 1 */ +#define SSC_RC1R_CP1(value) ((SSC_RC1R_CP1_Msk & ((value) << SSC_RC1R_CP1_Pos))) +/* -------- SSC_SR : (SSC Offset: 0x40) Status Register -------- */ +#define SSC_SR_TXRDY (0x1u << 0) /**< \brief (SSC_SR) Transmit Ready */ +#define SSC_SR_TXEMPTY (0x1u << 1) /**< \brief (SSC_SR) Transmit Empty */ +#define SSC_SR_RXRDY (0x1u << 4) /**< \brief (SSC_SR) Receive Ready */ +#define SSC_SR_OVRUN (0x1u << 5) /**< \brief (SSC_SR) Receive Overrun */ +#define SSC_SR_CP0 (0x1u << 8) /**< \brief (SSC_SR) Compare 0 */ +#define SSC_SR_CP1 (0x1u << 9) /**< \brief (SSC_SR) Compare 1 */ +#define SSC_SR_TXSYN (0x1u << 10) /**< \brief (SSC_SR) Transmit Sync */ +#define SSC_SR_RXSYN (0x1u << 11) /**< \brief (SSC_SR) Receive Sync */ +#define SSC_SR_TXEN (0x1u << 16) /**< \brief (SSC_SR) Transmit Enable */ +#define SSC_SR_RXEN (0x1u << 17) /**< \brief (SSC_SR) Receive Enable */ +/* -------- SSC_IER : (SSC Offset: 0x44) Interrupt Enable Register -------- */ +#define SSC_IER_TXRDY (0x1u << 0) /**< \brief (SSC_IER) Transmit Ready Interrupt Enable */ +#define SSC_IER_TXEMPTY (0x1u << 1) /**< \brief (SSC_IER) Transmit Empty Interrupt Enable */ +#define SSC_IER_RXRDY (0x1u << 4) /**< \brief (SSC_IER) Receive Ready Interrupt Enable */ +#define SSC_IER_OVRUN (0x1u << 5) /**< \brief (SSC_IER) Receive Overrun Interrupt Enable */ +#define SSC_IER_CP0 (0x1u << 8) /**< \brief (SSC_IER) Compare 0 Interrupt Enable */ +#define SSC_IER_CP1 (0x1u << 9) /**< \brief (SSC_IER) Compare 1 Interrupt Enable */ +#define SSC_IER_TXSYN (0x1u << 10) /**< \brief (SSC_IER) Tx Sync Interrupt Enable */ +#define SSC_IER_RXSYN (0x1u << 11) /**< \brief (SSC_IER) Rx Sync Interrupt Enable */ +/* -------- SSC_IDR : (SSC Offset: 0x48) Interrupt Disable Register -------- */ +#define SSC_IDR_TXRDY (0x1u << 0) /**< \brief (SSC_IDR) Transmit Ready Interrupt Disable */ +#define SSC_IDR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IDR) Transmit Empty Interrupt Disable */ +#define SSC_IDR_RXRDY (0x1u << 4) /**< \brief (SSC_IDR) Receive Ready Interrupt Disable */ +#define SSC_IDR_OVRUN (0x1u << 5) /**< \brief (SSC_IDR) Receive Overrun Interrupt Disable */ +#define SSC_IDR_CP0 (0x1u << 8) /**< \brief (SSC_IDR) Compare 0 Interrupt Disable */ +#define SSC_IDR_CP1 (0x1u << 9) /**< \brief (SSC_IDR) Compare 1 Interrupt Disable */ +#define SSC_IDR_TXSYN (0x1u << 10) /**< \brief (SSC_IDR) Tx Sync Interrupt Enable */ +#define SSC_IDR_RXSYN (0x1u << 11) /**< \brief (SSC_IDR) Rx Sync Interrupt Enable */ +/* -------- SSC_IMR : (SSC Offset: 0x4C) Interrupt Mask Register -------- */ +#define SSC_IMR_TXRDY (0x1u << 0) /**< \brief (SSC_IMR) Transmit Ready Interrupt Mask */ +#define SSC_IMR_TXEMPTY (0x1u << 1) /**< \brief (SSC_IMR) Transmit Empty Interrupt Mask */ +#define SSC_IMR_RXRDY (0x1u << 4) /**< \brief (SSC_IMR) Receive Ready Interrupt Mask */ +#define SSC_IMR_OVRUN (0x1u << 5) /**< \brief (SSC_IMR) Receive Overrun Interrupt Mask */ +#define SSC_IMR_CP0 (0x1u << 8) /**< \brief (SSC_IMR) Compare 0 Interrupt Mask */ +#define SSC_IMR_CP1 (0x1u << 9) /**< \brief (SSC_IMR) Compare 1 Interrupt Mask */ +#define SSC_IMR_TXSYN (0x1u << 10) /**< \brief (SSC_IMR) Tx Sync Interrupt Mask */ +#define SSC_IMR_RXSYN (0x1u << 11) /**< \brief (SSC_IMR) Rx Sync Interrupt Mask */ +/* -------- SSC_WPMR : (SSC Offset: 0xE4) Write Protection Mode Register -------- */ +#define SSC_WPMR_WPEN (0x1u << 0) /**< \brief (SSC_WPMR) Write Protection Enable */ +#define SSC_WPMR_WPKEY_Pos 8 +#define SSC_WPMR_WPKEY_Msk (0xffffffu << SSC_WPMR_WPKEY_Pos) /**< \brief (SSC_WPMR) Write Protection Key */ +#define SSC_WPMR_WPKEY(value) ((SSC_WPMR_WPKEY_Msk & ((value) << SSC_WPMR_WPKEY_Pos))) +#define SSC_WPMR_WPKEY_PASSWD (0x535343u << 8) /**< \brief (SSC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ +/* -------- SSC_WPSR : (SSC Offset: 0xE8) Write Protection Status Register -------- */ +#define SSC_WPSR_WPVS (0x1u << 0) /**< \brief (SSC_WPSR) Write Protection Violation Status */ +#define SSC_WPSR_WPVSRC_Pos 8 +#define SSC_WPSR_WPVSRC_Msk (0xffffu << SSC_WPSR_WPVSRC_Pos) /**< \brief (SSC_WPSR) Write Protect Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_SSC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_supc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_supc.h new file mode 100644 index 000000000..6c34da96b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_supc.h @@ -0,0 +1,295 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SUPC_COMPONENT_ +#define _SAMV71_SUPC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Supply Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_SUPC Supply Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Supc hardware registers */ +typedef struct { + __O uint32_t SUPC_CR; /**< \brief (Supc Offset: 0x00) Supply Controller Control Register */ + __IO uint32_t SUPC_SMMR; /**< \brief (Supc Offset: 0x04) Supply Controller Supply Monitor Mode Register */ + __IO uint32_t SUPC_MR; /**< \brief (Supc Offset: 0x08) Supply Controller Mode Register */ + __IO uint32_t SUPC_WUMR; /**< \brief (Supc Offset: 0x0C) Supply Controller Wake-up Mode Register */ + __IO uint32_t SUPC_WUIR; /**< \brief (Supc Offset: 0x10) Supply Controller Wake-up Inputs Register */ + __I uint32_t SUPC_SR; /**< \brief (Supc Offset: 0x14) Supply Controller Status Register */ +} Supc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- SUPC_CR : (SUPC Offset: 0x00) Supply Controller Control Register -------- */ +#define SUPC_CR_VROFF (0x1u << 2) /**< \brief (SUPC_CR) Voltage Regulator Off */ +#define SUPC_CR_VROFF_NO_EFFECT (0x0u << 2) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_VROFF_STOP_VREG (0x1u << 2) /**< \brief (SUPC_CR) If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. */ +#define SUPC_CR_XTALSEL (0x1u << 3) /**< \brief (SUPC_CR) Crystal Oscillator Select */ +#define SUPC_CR_XTALSEL_NO_EFFECT (0x0u << 3) /**< \brief (SUPC_CR) No effect. */ +#define SUPC_CR_XTALSEL_CRYSTAL_SEL (0x1u << 3) /**< \brief (SUPC_CR) If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. */ +#define SUPC_CR_KEY_Pos 24 +#define SUPC_CR_KEY_Msk (0xffu << SUPC_CR_KEY_Pos) /**< \brief (SUPC_CR) Password */ +#define SUPC_CR_KEY(value) ((SUPC_CR_KEY_Msk & ((value) << SUPC_CR_KEY_Pos))) +#define SUPC_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_CR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_SMMR : (SUPC Offset: 0x04) Supply Controller Supply Monitor Mode Register -------- */ +#define SUPC_SMMR_SMTH_Pos 0 +#define SUPC_SMMR_SMTH_Msk (0xfu << SUPC_SMMR_SMTH_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Threshold */ +#define SUPC_SMMR_SMTH(value) ((SUPC_SMMR_SMTH_Msk & ((value) << SUPC_SMMR_SMTH_Pos))) +#define SUPC_SMMR_SMSMPL_Pos 8 +#define SUPC_SMMR_SMSMPL_Msk (0x7u << SUPC_SMMR_SMSMPL_Pos) /**< \brief (SUPC_SMMR) Supply Monitor Sampling Period */ +#define SUPC_SMMR_SMSMPL(value) ((SUPC_SMMR_SMSMPL_Msk & ((value) << SUPC_SMMR_SMSMPL_Pos))) +#define SUPC_SMMR_SMSMPL_SMD (0x0u << 8) /**< \brief (SUPC_SMMR) Supply Monitor disabled */ +#define SUPC_SMMR_SMSMPL_CSM (0x1u << 8) /**< \brief (SUPC_SMMR) Continuous Supply Monitor */ +#define SUPC_SMMR_SMSMPL_32SLCK (0x2u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 32 SLCK periods */ +#define SUPC_SMMR_SMSMPL_256SLCK (0x3u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 256 SLCK periods */ +#define SUPC_SMMR_SMSMPL_2048SLCK (0x4u << 8) /**< \brief (SUPC_SMMR) Supply Monitor enabled one SLCK period every 2,048 SLCK periods */ +#define SUPC_SMMR_SMRSTEN (0x1u << 12) /**< \brief (SUPC_SMMR) Supply Monitor Reset Enable */ +#define SUPC_SMMR_SMRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_SMMR) The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_SMMR) The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN (0x1u << 13) /**< \brief (SUPC_SMMR) Supply Monitor Interrupt Enable */ +#define SUPC_SMMR_SMIEN_NOT_ENABLE (0x0u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is not affected when a supply monitor detection occurs. */ +#define SUPC_SMMR_SMIEN_ENABLE (0x1u << 13) /**< \brief (SUPC_SMMR) The SUPC interrupt signal is asserted when a supply monitor detection occurs. */ +/* -------- SUPC_MR : (SUPC Offset: 0x08) Supply Controller Mode Register -------- */ +#define SUPC_MR_BODRSTEN (0x1u << 12) /**< \brief (SUPC_MR) Brownout Detector Reset Enable */ +#define SUPC_MR_BODRSTEN_NOT_ENABLE (0x0u << 12) /**< \brief (SUPC_MR) The core reset signal vddcore_nreset is not affected when a brownout detection occurs. */ +#define SUPC_MR_BODRSTEN_ENABLE (0x1u << 12) /**< \brief (SUPC_MR) The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. */ +#define SUPC_MR_BODDIS (0x1u << 13) /**< \brief (SUPC_MR) Brownout Detector Disable */ +#define SUPC_MR_BODDIS_ENABLE (0x0u << 13) /**< \brief (SUPC_MR) The core brownout detector is enabled. */ +#define SUPC_MR_BODDIS_DISABLE (0x1u << 13) /**< \brief (SUPC_MR) The core brownout detector is disabled. */ +#define SUPC_MR_ONREG (0x1u << 14) /**< \brief (SUPC_MR) Voltage Regulator Enable */ +#define SUPC_MR_ONREG_ONREG_UNUSED (0x0u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is not used (external power supply is used). */ +#define SUPC_MR_ONREG_ONREG_USED (0x1u << 14) /**< \brief (SUPC_MR) Internal voltage regulator is used. */ +#define SUPC_MR_BKUPRETON (0x1u << 17) /**< \brief (SUPC_MR) SRAM On In Backup Mode */ +#define SUPC_MR_OSCBYPASS (0x1u << 20) /**< \brief (SUPC_MR) Oscillator Bypass */ +#define SUPC_MR_OSCBYPASS_NO_EFFECT (0x0u << 20) /**< \brief (SUPC_MR) No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). */ +#define SUPC_MR_OSCBYPASS_BYPASS (0x1u << 20) /**< \brief (SUPC_MR) The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. */ +#define SUPC_MR_KEY_Pos 24 +#define SUPC_MR_KEY_Msk (0xffu << SUPC_MR_KEY_Pos) /**< \brief (SUPC_MR) Password Key */ +#define SUPC_MR_KEY(value) ((SUPC_MR_KEY_Msk & ((value) << SUPC_MR_KEY_Pos))) +#define SUPC_MR_KEY_PASSWD (0xA5u << 24) /**< \brief (SUPC_MR) Writing any other value in this field aborts the write operation. */ +/* -------- SUPC_WUMR : (SUPC Offset: 0x0C) Supply Controller Wake-up Mode Register -------- */ +#define SUPC_WUMR_SMEN (0x1u << 1) /**< \brief (SUPC_WUMR) Supply Monitor Wake-up Enable */ +#define SUPC_WUMR_SMEN_NOT_ENABLE (0x0u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection has no wake-up effect. */ +#define SUPC_WUMR_SMEN_ENABLE (0x1u << 1) /**< \brief (SUPC_WUMR) The supply monitor detection forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTTEN (0x1u << 2) /**< \brief (SUPC_WUMR) Real-time Timer Wake-up Enable */ +#define SUPC_WUMR_RTTEN_NOT_ENABLE (0x0u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTTEN_ENABLE (0x1u << 2) /**< \brief (SUPC_WUMR) The RTT alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_RTCEN (0x1u << 3) /**< \brief (SUPC_WUMR) Real-time Clock Wake-up Enable */ +#define SUPC_WUMR_RTCEN_NOT_ENABLE (0x0u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal has no wake-up effect. */ +#define SUPC_WUMR_RTCEN_ENABLE (0x1u << 3) /**< \brief (SUPC_WUMR) The RTC alarm signal forces the wake-up of the core power supply. */ +#define SUPC_WUMR_LPDBCEN0 (0x1u << 5) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP0 */ +#define SUPC_WUMR_LPDBCEN0_NOT_ENABLE (0x0u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN0_ENABLE (0x1u << 5) /**< \brief (SUPC_WUMR) The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCEN1 (0x1u << 6) /**< \brief (SUPC_WUMR) Low-power Debouncer Enable WKUP1 */ +#define SUPC_WUMR_LPDBCEN1_NOT_ENABLE (0x0u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is not connected to the low-power debouncer. */ +#define SUPC_WUMR_LPDBCEN1_ENABLE (0x1u << 6) /**< \brief (SUPC_WUMR) The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. */ +#define SUPC_WUMR_LPDBCCLR (0x1u << 7) /**< \brief (SUPC_WUMR) Low-power Debouncer Clear */ +#define SUPC_WUMR_LPDBCCLR_NOT_ENABLE (0x0u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event does not create an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_LPDBCCLR_ENABLE (0x1u << 7) /**< \brief (SUPC_WUMR) A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. */ +#define SUPC_WUMR_WKUPDBC_Pos 12 +#define SUPC_WUMR_WKUPDBC_Msk (0x7u << SUPC_WUMR_WKUPDBC_Pos) /**< \brief (SUPC_WUMR) Wake-up Inputs Debouncer Period */ +#define SUPC_WUMR_WKUPDBC(value) ((SUPC_WUMR_WKUPDBC_Msk & ((value) << SUPC_WUMR_WKUPDBC_Pos))) +#define SUPC_WUMR_WKUPDBC_IMMEDIATE (0x0u << 12) /**< \brief (SUPC_WUMR) Immediate, no debouncing, detected active at least on one Slow Clock edge. */ +#define SUPC_WUMR_WKUPDBC_3_SLCK (0x1u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 3 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32_SLCK (0x2u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_512_SLCK (0x3u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 512 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_4096_SLCK (0x4u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 4,096 SLCK periods */ +#define SUPC_WUMR_WKUPDBC_32768_SLCK (0x5u << 12) /**< \brief (SUPC_WUMR) WKUPx shall be in its active state for at least 32,768 SLCK periods */ +#define SUPC_WUMR_LPDBC_Pos 16 +#define SUPC_WUMR_LPDBC_Msk (0x7u << SUPC_WUMR_LPDBC_Pos) /**< \brief (SUPC_WUMR) Low-power Debouncer Period */ +#define SUPC_WUMR_LPDBC(value) ((SUPC_WUMR_LPDBC_Msk & ((value) << SUPC_WUMR_LPDBC_Pos))) +#define SUPC_WUMR_LPDBC_DISABLE (0x0u << 16) /**< \brief (SUPC_WUMR) Disable the low-power debouncers. */ +#define SUPC_WUMR_LPDBC_2_RTCOUT (0x1u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 2 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_3_RTCOUT (0x2u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 3 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_4_RTCOUT (0x3u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 4 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_5_RTCOUT (0x4u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 5 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_6_RTCOUT (0x5u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 6 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_7_RTCOUT (0x6u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 7 RTCOUTx clock periods */ +#define SUPC_WUMR_LPDBC_8_RTCOUT (0x7u << 16) /**< \brief (SUPC_WUMR) WKUP0/1 in active state for at least 8 RTCOUTx clock periods */ +/* -------- SUPC_WUIR : (SUPC Offset: 0x10) Supply Controller Wake-up Inputs Register -------- */ +#define SUPC_WUIR_WKUPEN0 (0x1u << 0) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 0 */ +#define SUPC_WUIR_WKUPEN0_DISABLE (0x0u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN0_ENABLE (0x1u << 0) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN1 (0x1u << 1) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 1 */ +#define SUPC_WUIR_WKUPEN1_DISABLE (0x0u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN1_ENABLE (0x1u << 1) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN2 (0x1u << 2) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 2 */ +#define SUPC_WUIR_WKUPEN2_DISABLE (0x0u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN2_ENABLE (0x1u << 2) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN3 (0x1u << 3) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 3 */ +#define SUPC_WUIR_WKUPEN3_DISABLE (0x0u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN3_ENABLE (0x1u << 3) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN4 (0x1u << 4) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 4 */ +#define SUPC_WUIR_WKUPEN4_DISABLE (0x0u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN4_ENABLE (0x1u << 4) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN5 (0x1u << 5) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 5 */ +#define SUPC_WUIR_WKUPEN5_DISABLE (0x0u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN5_ENABLE (0x1u << 5) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN6 (0x1u << 6) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 6 */ +#define SUPC_WUIR_WKUPEN6_DISABLE (0x0u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN6_ENABLE (0x1u << 6) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN7 (0x1u << 7) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 7 */ +#define SUPC_WUIR_WKUPEN7_DISABLE (0x0u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN7_ENABLE (0x1u << 7) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN8 (0x1u << 8) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 8 */ +#define SUPC_WUIR_WKUPEN8_DISABLE (0x0u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN8_ENABLE (0x1u << 8) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN9 (0x1u << 9) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 9 */ +#define SUPC_WUIR_WKUPEN9_DISABLE (0x0u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN9_ENABLE (0x1u << 9) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN10 (0x1u << 10) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 10 */ +#define SUPC_WUIR_WKUPEN10_DISABLE (0x0u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN10_ENABLE (0x1u << 10) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN11 (0x1u << 11) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 11 */ +#define SUPC_WUIR_WKUPEN11_DISABLE (0x0u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN11_ENABLE (0x1u << 11) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN12 (0x1u << 12) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 12 */ +#define SUPC_WUIR_WKUPEN12_DISABLE (0x0u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN12_ENABLE (0x1u << 12) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPEN13 (0x1u << 13) /**< \brief (SUPC_WUIR) Wake-up Input Enable 0 to 13 */ +#define SUPC_WUIR_WKUPEN13_DISABLE (0x0u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input has no wake-up effect. */ +#define SUPC_WUIR_WKUPEN13_ENABLE (0x1u << 13) /**< \brief (SUPC_WUIR) The corresponding wake-up input is enabled for a wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0 (0x1u << 16) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 0 */ +#define SUPC_WUIR_WKUPT0_LOW (0x0u << 16) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT0_HIGH (0x1u << 16) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1 (0x1u << 17) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 1 */ +#define SUPC_WUIR_WKUPT1_LOW (0x0u << 17) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT1_HIGH (0x1u << 17) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2 (0x1u << 18) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 2 */ +#define SUPC_WUIR_WKUPT2_LOW (0x0u << 18) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT2_HIGH (0x1u << 18) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3 (0x1u << 19) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 3 */ +#define SUPC_WUIR_WKUPT3_LOW (0x0u << 19) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT3_HIGH (0x1u << 19) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4 (0x1u << 20) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 4 */ +#define SUPC_WUIR_WKUPT4_LOW (0x0u << 20) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT4_HIGH (0x1u << 20) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5 (0x1u << 21) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 5 */ +#define SUPC_WUIR_WKUPT5_LOW (0x0u << 21) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT5_HIGH (0x1u << 21) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6 (0x1u << 22) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 6 */ +#define SUPC_WUIR_WKUPT6_LOW (0x0u << 22) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT6_HIGH (0x1u << 22) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7 (0x1u << 23) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 7 */ +#define SUPC_WUIR_WKUPT7_LOW (0x0u << 23) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT7_HIGH (0x1u << 23) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8 (0x1u << 24) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 8 */ +#define SUPC_WUIR_WKUPT8_LOW (0x0u << 24) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT8_HIGH (0x1u << 24) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9 (0x1u << 25) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 9 */ +#define SUPC_WUIR_WKUPT9_LOW (0x0u << 25) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT9_HIGH (0x1u << 25) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10 (0x1u << 26) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 10 */ +#define SUPC_WUIR_WKUPT10_LOW (0x0u << 26) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT10_HIGH (0x1u << 26) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11 (0x1u << 27) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 11 */ +#define SUPC_WUIR_WKUPT11_LOW (0x0u << 27) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT11_HIGH (0x1u << 27) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12 (0x1u << 28) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 12 */ +#define SUPC_WUIR_WKUPT12_LOW (0x0u << 28) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT12_HIGH (0x1u << 28) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13 (0x1u << 29) /**< \brief (SUPC_WUIR) Wake-up Input Type 0 to 13 */ +#define SUPC_WUIR_WKUPT13_LOW (0x0u << 29) /**< \brief (SUPC_WUIR) A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. */ +#define SUPC_WUIR_WKUPT13_HIGH (0x1u << 29) /**< \brief (SUPC_WUIR) A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. */ +/* -------- SUPC_SR : (SUPC Offset: 0x14) Supply Controller Status Register -------- */ +#define SUPC_SR_WKUPS (0x1u << 1) /**< \brief (SUPC_SR) WKUP Wake-up Status (cleared on read) */ +#define SUPC_SR_WKUPS_NO (0x0u << 1) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPS_PRESENT (0x1u << 1) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS (0x1u << 2) /**< \brief (SUPC_SR) Supply Monitor Detection Wake-up Status (cleared on read) */ +#define SUPC_SR_SMWS_NO (0x0u << 2) /**< \brief (SUPC_SR) No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_SMWS_PRESENT (0x1u << 2) /**< \brief (SUPC_SR) At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_BODRSTS (0x1u << 3) /**< \brief (SUPC_SR) Brownout Detector Reset Status (cleared on read) */ +#define SUPC_SR_BODRSTS_NO (0x0u << 3) /**< \brief (SUPC_SR) No core brownout rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_BODRSTS_PRESENT (0x1u << 3) /**< \brief (SUPC_SR) At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS (0x1u << 4) /**< \brief (SUPC_SR) Supply Monitor Reset Status (cleared on read) */ +#define SUPC_SR_SMRSTS_NO (0x0u << 4) /**< \brief (SUPC_SR) No supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMRSTS_PRESENT (0x1u << 4) /**< \brief (SUPC_SR) At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. */ +#define SUPC_SR_SMS (0x1u << 5) /**< \brief (SUPC_SR) Supply Monitor Status (cleared on read) */ +#define SUPC_SR_SMS_NO (0x0u << 5) /**< \brief (SUPC_SR) No supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMS_PRESENT (0x1u << 5) /**< \brief (SUPC_SR) At least one supply monitor detection since the last read of SUPC_SR. */ +#define SUPC_SR_SMOS (0x1u << 6) /**< \brief (SUPC_SR) Supply Monitor Output Status */ +#define SUPC_SR_SMOS_HIGH (0x0u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO higher than its threshold at its last measurement. */ +#define SUPC_SR_SMOS_LOW (0x1u << 6) /**< \brief (SUPC_SR) The supply monitor detected VDDIO lower than its threshold at its last measurement. */ +#define SUPC_SR_OSCSEL (0x1u << 7) /**< \brief (SUPC_SR) 32-kHz Oscillator Selection Status */ +#define SUPC_SR_OSCSEL_RC (0x0u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. */ +#define SUPC_SR_OSCSEL_CRYST (0x1u << 7) /**< \brief (SUPC_SR) The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. */ +#define SUPC_SR_LPDBCS0 (0x1u << 13) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) */ +#define SUPC_SR_LPDBCS0_NO (0x0u << 13) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS0_PRESENT (0x1u << 13) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1 (0x1u << 14) /**< \brief (SUPC_SR) Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) */ +#define SUPC_SR_LPDBCS1_NO (0x0u << 14) /**< \brief (SUPC_SR) No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_LPDBCS1_PRESENT (0x1u << 14) /**< \brief (SUPC_SR) At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS0 (0x1u << 16) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS0_DIS (0x0u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS0_EN (0x1u << 16) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS1 (0x1u << 17) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS1_DIS (0x0u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS1_EN (0x1u << 17) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS2 (0x1u << 18) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS2_DIS (0x0u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS2_EN (0x1u << 18) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS3 (0x1u << 19) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS3_DIS (0x0u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS3_EN (0x1u << 19) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS4 (0x1u << 20) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS4_DIS (0x0u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS4_EN (0x1u << 20) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS5 (0x1u << 21) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS5_DIS (0x0u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS5_EN (0x1u << 21) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS6 (0x1u << 22) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS6_DIS (0x0u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS6_EN (0x1u << 22) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS7 (0x1u << 23) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS7_DIS (0x0u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS7_EN (0x1u << 23) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS8 (0x1u << 24) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS8_DIS (0x0u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS8_EN (0x1u << 24) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS9 (0x1u << 25) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS9_DIS (0x0u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS9_EN (0x1u << 25) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS10 (0x1u << 26) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS10_DIS (0x0u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS10_EN (0x1u << 26) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS11 (0x1u << 27) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS11_DIS (0x0u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS11_EN (0x1u << 27) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS12 (0x1u << 28) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS12_DIS (0x0u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS12_EN (0x1u << 28) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ +#define SUPC_SR_WKUPIS13 (0x1u << 29) /**< \brief (SUPC_SR) WKUPx Input Status (cleared on read) */ +#define SUPC_SR_WKUPIS13_DIS (0x0u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. */ +#define SUPC_SR_WKUPIS13_EN (0x1u << 29) /**< \brief (SUPC_SR) The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. */ + +/*@}*/ + + +#endif /* _SAMV71_SUPC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_tc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_tc.h new file mode 100644 index 000000000..c9c675ad7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_tc.h @@ -0,0 +1,346 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC_COMPONENT_ +#define _SAMV71_TC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Timer Counter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TC Timer Counter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief TcChannel hardware registers */ +typedef struct { + __O uint32_t TC_CCR; /**< \brief (TcChannel Offset: 0x0) Channel Control Register */ + __IO uint32_t TC_CMR; /**< \brief (TcChannel Offset: 0x4) Channel Mode Register */ + __IO uint32_t TC_SMMR; /**< \brief (TcChannel Offset: 0x8) Stepper Motor Mode Register */ + __I uint32_t TC_RAB; /**< \brief (TcChannel Offset: 0xC) Register AB */ + __I uint32_t TC_CV; /**< \brief (TcChannel Offset: 0x10) Counter Value */ + __IO uint32_t TC_RA; /**< \brief (TcChannel Offset: 0x14) Register A */ + __IO uint32_t TC_RB; /**< \brief (TcChannel Offset: 0x18) Register B */ + __IO uint32_t TC_RC; /**< \brief (TcChannel Offset: 0x1C) Register C */ + __I uint32_t TC_SR; /**< \brief (TcChannel Offset: 0x20) Status Register */ + __O uint32_t TC_IER; /**< \brief (TcChannel Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TC_IDR; /**< \brief (TcChannel Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TC_IMR; /**< \brief (TcChannel Offset: 0x2C) Interrupt Mask Register */ + __IO uint32_t TC_EMR; /**< \brief (TcChannel Offset: 0x30) Extended Mode Register */ + __I uint32_t Reserved1[3]; +} TcChannel; +/** \brief Tc hardware registers */ +#define TCCHANNEL_NUMBER 3 +typedef struct { + TcChannel TC_CHANNEL[TCCHANNEL_NUMBER]; /**< \brief (Tc Offset: 0x0) channel = 0 .. 2 */ + __O uint32_t TC_BCR; /**< \brief (Tc Offset: 0xC0) Block Control Register */ + __IO uint32_t TC_BMR; /**< \brief (Tc Offset: 0xC4) Block Mode Register */ + __O uint32_t TC_QIER; /**< \brief (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ + __O uint32_t TC_QIDR; /**< \brief (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ + __I uint32_t TC_QIMR; /**< \brief (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ + __I uint32_t TC_QISR; /**< \brief (Tc Offset: 0xD4) QDEC Interrupt Status Register */ + __IO uint32_t TC_FMR; /**< \brief (Tc Offset: 0xD8) Fault Mode Register */ + __I uint32_t Reserved1[2]; + __IO uint32_t TC_WPMR; /**< \brief (Tc Offset: 0xE4) Write Protection Mode Register */ +} Tc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ +#define TC_CCR_CLKEN (0x1u << 0) /**< \brief (TC_CCR) Counter Clock Enable Command */ +#define TC_CCR_CLKDIS (0x1u << 1) /**< \brief (TC_CCR) Counter Clock Disable Command */ +#define TC_CCR_SWTRG (0x1u << 2) /**< \brief (TC_CCR) Software Trigger Command */ +/* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ +#define TC_CMR_TCCLKS_Pos 0 +#define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /**< \brief (TC_CMR) Clock Selection */ +#define TC_CMR_TCCLKS(value) ((TC_CMR_TCCLKS_Msk & ((value) << TC_CMR_TCCLKS_Pos))) +#define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /**< \brief (TC_CMR) Clock selected: internal PCK6 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/8 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/32 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /**< \brief (TC_CMR) Clock selected: internal MCK/128 clock signal (from PMC) */ +#define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /**< \brief (TC_CMR) Clock selected: internal SLCK clock signal (from PMC) */ +#define TC_CMR_TCCLKS_XC0 (0x5u << 0) /**< \brief (TC_CMR) Clock selected: XC0 */ +#define TC_CMR_TCCLKS_XC1 (0x6u << 0) /**< \brief (TC_CMR) Clock selected: XC1 */ +#define TC_CMR_TCCLKS_XC2 (0x7u << 0) /**< \brief (TC_CMR) Clock selected: XC2 */ +#define TC_CMR_CLKI (0x1u << 3) /**< \brief (TC_CMR) Clock Invert */ +#define TC_CMR_BURST_Pos 4 +#define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /**< \brief (TC_CMR) Burst Signal Selection */ +#define TC_CMR_BURST(value) ((TC_CMR_BURST_Msk & ((value) << TC_CMR_BURST_Pos))) +#define TC_CMR_BURST_NONE (0x0u << 4) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_BURST_XC0 (0x1u << 4) /**< \brief (TC_CMR) XC0 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC1 (0x2u << 4) /**< \brief (TC_CMR) XC1 is ANDed with the selected clock. */ +#define TC_CMR_BURST_XC2 (0x3u << 4) /**< \brief (TC_CMR) XC2 is ANDed with the selected clock. */ +#define TC_CMR_LDBSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RB Loading */ +#define TC_CMR_LDBDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RB Loading */ +#define TC_CMR_ETRGEDG_Pos 8 +#define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /**< \brief (TC_CMR) External Trigger Edge Selection */ +#define TC_CMR_ETRGEDG(value) ((TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos))) +#define TC_CMR_ETRGEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_ABETRG (0x1u << 10) /**< \brief (TC_CMR) TIOA or TIOB External Trigger Selection */ +#define TC_CMR_CPCTRG (0x1u << 14) /**< \brief (TC_CMR) RC Compare Trigger Enable */ +#define TC_CMR_WAVE (0x1u << 15) /**< \brief (TC_CMR) Waveform Mode */ +#define TC_CMR_LDRA_Pos 16 +#define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /**< \brief (TC_CMR) RA Loading Edge Selection */ +#define TC_CMR_LDRA(value) ((TC_CMR_LDRA_Msk & ((value) << TC_CMR_LDRA_Pos))) +#define TC_CMR_LDRA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRA_RISING (0x1u << 16) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRA_FALLING (0x2u << 16) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRA_EDGE (0x3u << 16) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_LDRB_Pos 18 +#define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /**< \brief (TC_CMR) RB Loading Edge Selection */ +#define TC_CMR_LDRB(value) ((TC_CMR_LDRB_Msk & ((value) << TC_CMR_LDRB_Pos))) +#define TC_CMR_LDRB_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_LDRB_RISING (0x1u << 18) /**< \brief (TC_CMR) Rising edge of TIOA */ +#define TC_CMR_LDRB_FALLING (0x2u << 18) /**< \brief (TC_CMR) Falling edge of TIOA */ +#define TC_CMR_LDRB_EDGE (0x3u << 18) /**< \brief (TC_CMR) Each edge of TIOA */ +#define TC_CMR_SBSMPLR_Pos 20 +#define TC_CMR_SBSMPLR_Msk (0x7u << TC_CMR_SBSMPLR_Pos) /**< \brief (TC_CMR) Loading Edge Subsampling Ratio */ +#define TC_CMR_SBSMPLR(value) ((TC_CMR_SBSMPLR_Msk & ((value) << TC_CMR_SBSMPLR_Pos))) +#define TC_CMR_SBSMPLR_ONE (0x0u << 20) /**< \brief (TC_CMR) Load a Capture Register each selected edge */ +#define TC_CMR_SBSMPLR_HALF (0x1u << 20) /**< \brief (TC_CMR) Load a Capture Register every 2 selected edges */ +#define TC_CMR_SBSMPLR_FOURTH (0x2u << 20) /**< \brief (TC_CMR) Load a Capture Register every 4 selected edges */ +#define TC_CMR_SBSMPLR_EIGHTH (0x3u << 20) /**< \brief (TC_CMR) Load a Capture Register every 8 selected edges */ +#define TC_CMR_SBSMPLR_SIXTEENTH (0x4u << 20) /**< \brief (TC_CMR) Load a Capture Register every 16 selected edges */ +#define TC_CMR_CPCSTOP (0x1u << 6) /**< \brief (TC_CMR) Counter Clock Stopped with RC Compare */ +#define TC_CMR_CPCDIS (0x1u << 7) /**< \brief (TC_CMR) Counter Clock Disable with RC Compare */ +#define TC_CMR_EEVTEDG_Pos 8 +#define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /**< \brief (TC_CMR) External Event Edge Selection */ +#define TC_CMR_EEVTEDG(value) ((TC_CMR_EEVTEDG_Msk & ((value) << TC_CMR_EEVTEDG_Pos))) +#define TC_CMR_EEVTEDG_NONE (0x0u << 8) /**< \brief (TC_CMR) None */ +#define TC_CMR_EEVTEDG_RISING (0x1u << 8) /**< \brief (TC_CMR) Rising edge */ +#define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /**< \brief (TC_CMR) Falling edge */ +#define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /**< \brief (TC_CMR) Each edge */ +#define TC_CMR_EEVT_Pos 10 +#define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /**< \brief (TC_CMR) External Event Selection */ +#define TC_CMR_EEVT(value) ((TC_CMR_EEVT_Msk & ((value) << TC_CMR_EEVT_Pos))) +#define TC_CMR_EEVT_TIOB (0x0u << 10) /**< \brief (TC_CMR) TIOB */ +#define TC_CMR_EEVT_XC0 (0x1u << 10) /**< \brief (TC_CMR) XC0 */ +#define TC_CMR_EEVT_XC1 (0x2u << 10) /**< \brief (TC_CMR) XC1 */ +#define TC_CMR_EEVT_XC2 (0x3u << 10) /**< \brief (TC_CMR) XC2 */ +#define TC_CMR_ENETRG (0x1u << 12) /**< \brief (TC_CMR) External Event Trigger Enable */ +#define TC_CMR_WAVSEL_Pos 13 +#define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /**< \brief (TC_CMR) Waveform Selection */ +#define TC_CMR_WAVSEL(value) ((TC_CMR_WAVSEL_Msk & ((value) << TC_CMR_WAVSEL_Pos))) +#define TC_CMR_WAVSEL_UP (0x0u << 13) /**< \brief (TC_CMR) UP mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /**< \brief (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /**< \brief (TC_CMR) UP mode with automatic trigger on RC Compare */ +#define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /**< \brief (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ +#define TC_CMR_ACPA_Pos 16 +#define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /**< \brief (TC_CMR) RA Compare Effect on TIOA */ +#define TC_CMR_ACPA(value) ((TC_CMR_ACPA_Msk & ((value) << TC_CMR_ACPA_Pos))) +#define TC_CMR_ACPA_NONE (0x0u << 16) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPA_SET (0x1u << 16) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPA_CLEAR (0x2u << 16) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPA_TOGGLE (0x3u << 16) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ACPC_Pos 18 +#define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOA */ +#define TC_CMR_ACPC(value) ((TC_CMR_ACPC_Msk & ((value) << TC_CMR_ACPC_Pos))) +#define TC_CMR_ACPC_NONE (0x0u << 18) /**< \brief (TC_CMR) None */ +#define TC_CMR_ACPC_SET (0x1u << 18) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ACPC_CLEAR (0x2u << 18) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ACPC_TOGGLE (0x3u << 18) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_AEEVT_Pos 20 +#define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOA */ +#define TC_CMR_AEEVT(value) ((TC_CMR_AEEVT_Msk & ((value) << TC_CMR_AEEVT_Pos))) +#define TC_CMR_AEEVT_NONE (0x0u << 20) /**< \brief (TC_CMR) None */ +#define TC_CMR_AEEVT_SET (0x1u << 20) /**< \brief (TC_CMR) Set */ +#define TC_CMR_AEEVT_CLEAR (0x2u << 20) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_ASWTRG_Pos 22 +#define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOA */ +#define TC_CMR_ASWTRG(value) ((TC_CMR_ASWTRG_Msk & ((value) << TC_CMR_ASWTRG_Pos))) +#define TC_CMR_ASWTRG_NONE (0x0u << 22) /**< \brief (TC_CMR) None */ +#define TC_CMR_ASWTRG_SET (0x1u << 22) /**< \brief (TC_CMR) Set */ +#define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPB_Pos 24 +#define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /**< \brief (TC_CMR) RB Compare Effect on TIOB */ +#define TC_CMR_BCPB(value) ((TC_CMR_BCPB_Msk & ((value) << TC_CMR_BCPB_Pos))) +#define TC_CMR_BCPB_NONE (0x0u << 24) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPB_SET (0x1u << 24) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPB_CLEAR (0x2u << 24) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPB_TOGGLE (0x3u << 24) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BCPC_Pos 26 +#define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /**< \brief (TC_CMR) RC Compare Effect on TIOB */ +#define TC_CMR_BCPC(value) ((TC_CMR_BCPC_Msk & ((value) << TC_CMR_BCPC_Pos))) +#define TC_CMR_BCPC_NONE (0x0u << 26) /**< \brief (TC_CMR) None */ +#define TC_CMR_BCPC_SET (0x1u << 26) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BCPC_CLEAR (0x2u << 26) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BCPC_TOGGLE (0x3u << 26) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BEEVT_Pos 28 +#define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /**< \brief (TC_CMR) External Event Effect on TIOB */ +#define TC_CMR_BEEVT(value) ((TC_CMR_BEEVT_Msk & ((value) << TC_CMR_BEEVT_Pos))) +#define TC_CMR_BEEVT_NONE (0x0u << 28) /**< \brief (TC_CMR) None */ +#define TC_CMR_BEEVT_SET (0x1u << 28) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BEEVT_CLEAR (0x2u << 28) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /**< \brief (TC_CMR) Toggle */ +#define TC_CMR_BSWTRG_Pos 30 +#define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /**< \brief (TC_CMR) Software Trigger Effect on TIOB */ +#define TC_CMR_BSWTRG(value) ((TC_CMR_BSWTRG_Msk & ((value) << TC_CMR_BSWTRG_Pos))) +#define TC_CMR_BSWTRG_NONE (0x0u << 30) /**< \brief (TC_CMR) None */ +#define TC_CMR_BSWTRG_SET (0x1u << 30) /**< \brief (TC_CMR) Set */ +#define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /**< \brief (TC_CMR) Clear */ +#define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /**< \brief (TC_CMR) Toggle */ +/* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ +#define TC_SMMR_GCEN (0x1u << 0) /**< \brief (TC_SMMR) Gray Count Enable */ +#define TC_SMMR_DOWN (0x1u << 1) /**< \brief (TC_SMMR) Down Count */ +/* -------- TC_RAB : (TC Offset: N/A) Register AB -------- */ +#define TC_RAB_RAB_Pos 0 +#define TC_RAB_RAB_Msk (0xffffffffu << TC_RAB_RAB_Pos) /**< \brief (TC_RAB) Register A or Register B */ +/* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ +#define TC_CV_CV_Pos 0 +#define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /**< \brief (TC_CV) Counter Value */ +/* -------- TC_RA : (TC Offset: N/A) Register A -------- */ +#define TC_RA_RA_Pos 0 +#define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /**< \brief (TC_RA) Register A */ +#define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) +/* -------- TC_RB : (TC Offset: N/A) Register B -------- */ +#define TC_RB_RB_Pos 0 +#define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /**< \brief (TC_RB) Register B */ +#define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) +/* -------- TC_RC : (TC Offset: N/A) Register C -------- */ +#define TC_RC_RC_Pos 0 +#define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /**< \brief (TC_RC) Register C */ +#define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) +/* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ +#define TC_SR_COVFS (0x1u << 0) /**< \brief (TC_SR) Counter Overflow Status (cleared on read) */ +#define TC_SR_LOVRS (0x1u << 1) /**< \brief (TC_SR) Load Overrun Status (cleared on read) */ +#define TC_SR_CPAS (0x1u << 2) /**< \brief (TC_SR) RA Compare Status (cleared on read) */ +#define TC_SR_CPBS (0x1u << 3) /**< \brief (TC_SR) RB Compare Status (cleared on read) */ +#define TC_SR_CPCS (0x1u << 4) /**< \brief (TC_SR) RC Compare Status (cleared on read) */ +#define TC_SR_LDRAS (0x1u << 5) /**< \brief (TC_SR) RA Loading Status (cleared on read) */ +#define TC_SR_LDRBS (0x1u << 6) /**< \brief (TC_SR) RB Loading Status (cleared on read) */ +#define TC_SR_ETRGS (0x1u << 7) /**< \brief (TC_SR) External Trigger Status (cleared on read) */ +#define TC_SR_CLKSTA (0x1u << 16) /**< \brief (TC_SR) Clock Enabling Status */ +#define TC_SR_MTIOA (0x1u << 17) /**< \brief (TC_SR) TIOA Mirror */ +#define TC_SR_MTIOB (0x1u << 18) /**< \brief (TC_SR) TIOB Mirror */ +/* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ +#define TC_IER_COVFS (0x1u << 0) /**< \brief (TC_IER) Counter Overflow */ +#define TC_IER_LOVRS (0x1u << 1) /**< \brief (TC_IER) Load Overrun */ +#define TC_IER_CPAS (0x1u << 2) /**< \brief (TC_IER) RA Compare */ +#define TC_IER_CPBS (0x1u << 3) /**< \brief (TC_IER) RB Compare */ +#define TC_IER_CPCS (0x1u << 4) /**< \brief (TC_IER) RC Compare */ +#define TC_IER_LDRAS (0x1u << 5) /**< \brief (TC_IER) RA Loading */ +#define TC_IER_LDRBS (0x1u << 6) /**< \brief (TC_IER) RB Loading */ +#define TC_IER_ETRGS (0x1u << 7) /**< \brief (TC_IER) External Trigger */ +/* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ +#define TC_IDR_COVFS (0x1u << 0) /**< \brief (TC_IDR) Counter Overflow */ +#define TC_IDR_LOVRS (0x1u << 1) /**< \brief (TC_IDR) Load Overrun */ +#define TC_IDR_CPAS (0x1u << 2) /**< \brief (TC_IDR) RA Compare */ +#define TC_IDR_CPBS (0x1u << 3) /**< \brief (TC_IDR) RB Compare */ +#define TC_IDR_CPCS (0x1u << 4) /**< \brief (TC_IDR) RC Compare */ +#define TC_IDR_LDRAS (0x1u << 5) /**< \brief (TC_IDR) RA Loading */ +#define TC_IDR_LDRBS (0x1u << 6) /**< \brief (TC_IDR) RB Loading */ +#define TC_IDR_ETRGS (0x1u << 7) /**< \brief (TC_IDR) External Trigger */ +/* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ +#define TC_IMR_COVFS (0x1u << 0) /**< \brief (TC_IMR) Counter Overflow */ +#define TC_IMR_LOVRS (0x1u << 1) /**< \brief (TC_IMR) Load Overrun */ +#define TC_IMR_CPAS (0x1u << 2) /**< \brief (TC_IMR) RA Compare */ +#define TC_IMR_CPBS (0x1u << 3) /**< \brief (TC_IMR) RB Compare */ +#define TC_IMR_CPCS (0x1u << 4) /**< \brief (TC_IMR) RC Compare */ +#define TC_IMR_LDRAS (0x1u << 5) /**< \brief (TC_IMR) RA Loading */ +#define TC_IMR_LDRBS (0x1u << 6) /**< \brief (TC_IMR) RB Loading */ +#define TC_IMR_ETRGS (0x1u << 7) /**< \brief (TC_IMR) External Trigger */ +/* -------- TC_EMR : (TC Offset: N/A) Extended Mode Register -------- */ +#define TC_EMR_TRIGSRCA_Pos 0 +#define TC_EMR_TRIGSRCA_Msk (0x3u << TC_EMR_TRIGSRCA_Pos) /**< \brief (TC_EMR) Trigger Source for Input A */ +#define TC_EMR_TRIGSRCA(value) ((TC_EMR_TRIGSRCA_Msk & ((value) << TC_EMR_TRIGSRCA_Pos))) +#define TC_EMR_TRIGSRCA_EXTERNAL_TIOAx (0x0u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven by external pin TIOAx */ +#define TC_EMR_TRIGSRCA_PWMx (0x1u << 0) /**< \brief (TC_EMR) The trigger/capture input A is driven internally by PWMx */ +#define TC_EMR_TRIGSRCB_Pos 4 +#define TC_EMR_TRIGSRCB_Msk (0x3u << TC_EMR_TRIGSRCB_Pos) /**< \brief (TC_EMR) Trigger Source for Input B */ +#define TC_EMR_TRIGSRCB(value) ((TC_EMR_TRIGSRCB_Msk & ((value) << TC_EMR_TRIGSRCB_Pos))) +#define TC_EMR_TRIGSRCB_EXTERNAL_TIOBx (0x0u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven by external pin TIOBx */ +#define TC_EMR_TRIGSRCB_PWMx (0x1u << 4) /**< \brief (TC_EMR) The trigger/capture input B is driven internally by PWMx */ +#define TC_EMR_NODIVCLK (0x1u << 8) /**< \brief (TC_EMR) No Divided Clock */ +/* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ +#define TC_BCR_SYNC (0x1u << 0) /**< \brief (TC_BCR) Synchro Command */ +/* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ +#define TC_BMR_TC0XC0S_Pos 0 +#define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /**< \brief (TC_BMR) External Clock Signal 0 Selection */ +#define TC_BMR_TC0XC0S(value) ((TC_BMR_TC0XC0S_Msk & ((value) << TC_BMR_TC0XC0S_Pos))) +#define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TCLK0 */ +#define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA1 */ +#define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /**< \brief (TC_BMR) Signal connected to XC0: TIOA2 */ +#define TC_BMR_TC1XC1S_Pos 2 +#define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /**< \brief (TC_BMR) External Clock Signal 1 Selection */ +#define TC_BMR_TC1XC1S(value) ((TC_BMR_TC1XC1S_Msk & ((value) << TC_BMR_TC1XC1S_Pos))) +#define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TCLK1 */ +#define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA0 */ +#define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /**< \brief (TC_BMR) Signal connected to XC1: TIOA2 */ +#define TC_BMR_TC2XC2S_Pos 4 +#define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /**< \brief (TC_BMR) External Clock Signal 2 Selection */ +#define TC_BMR_TC2XC2S(value) ((TC_BMR_TC2XC2S_Msk & ((value) << TC_BMR_TC2XC2S_Pos))) +#define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TCLK2 */ +#define TC_BMR_TC2XC2S_TIOA0 (0x2u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA0 */ +#define TC_BMR_TC2XC2S_TIOA1 (0x3u << 4) /**< \brief (TC_BMR) Signal connected to XC2: TIOA1 */ +#define TC_BMR_QDEN (0x1u << 8) /**< \brief (TC_BMR) Quadrature Decoder Enabled */ +#define TC_BMR_POSEN (0x1u << 9) /**< \brief (TC_BMR) Position Enabled */ +#define TC_BMR_SPEEDEN (0x1u << 10) /**< \brief (TC_BMR) Speed Enabled */ +#define TC_BMR_QDTRANS (0x1u << 11) /**< \brief (TC_BMR) Quadrature Decoding Transparent */ +#define TC_BMR_EDGPHA (0x1u << 12) /**< \brief (TC_BMR) Edge on PHA Count Mode */ +#define TC_BMR_INVA (0x1u << 13) /**< \brief (TC_BMR) Inverted PHA */ +#define TC_BMR_INVB (0x1u << 14) /**< \brief (TC_BMR) Inverted PHB */ +#define TC_BMR_INVIDX (0x1u << 15) /**< \brief (TC_BMR) Inverted Index */ +#define TC_BMR_SWAP (0x1u << 16) /**< \brief (TC_BMR) Swap PHA and PHB */ +#define TC_BMR_IDXPHB (0x1u << 17) /**< \brief (TC_BMR) Index Pin is PHB Pin */ +#define TC_BMR_MAXFILT_Pos 20 +#define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /**< \brief (TC_BMR) Maximum Filter */ +#define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) +/* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ +#define TC_QIER_IDX (0x1u << 0) /**< \brief (TC_QIER) Index */ +#define TC_QIER_DIRCHG (0x1u << 1) /**< \brief (TC_QIER) Direction Change */ +#define TC_QIER_QERR (0x1u << 2) /**< \brief (TC_QIER) Quadrature Error */ +/* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ +#define TC_QIDR_IDX (0x1u << 0) /**< \brief (TC_QIDR) Index */ +#define TC_QIDR_DIRCHG (0x1u << 1) /**< \brief (TC_QIDR) Direction Change */ +#define TC_QIDR_QERR (0x1u << 2) /**< \brief (TC_QIDR) Quadrature Error */ +/* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ +#define TC_QIMR_IDX (0x1u << 0) /**< \brief (TC_QIMR) Index */ +#define TC_QIMR_DIRCHG (0x1u << 1) /**< \brief (TC_QIMR) Direction Change */ +#define TC_QIMR_QERR (0x1u << 2) /**< \brief (TC_QIMR) Quadrature Error */ +/* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ +#define TC_QISR_IDX (0x1u << 0) /**< \brief (TC_QISR) Index */ +#define TC_QISR_DIRCHG (0x1u << 1) /**< \brief (TC_QISR) Direction Change */ +#define TC_QISR_QERR (0x1u << 2) /**< \brief (TC_QISR) Quadrature Error */ +#define TC_QISR_DIR (0x1u << 8) /**< \brief (TC_QISR) Direction */ +/* -------- TC_FMR : (TC Offset: 0xD8) Fault Mode Register -------- */ +#define TC_FMR_ENCF0 (0x1u << 0) /**< \brief (TC_FMR) Enable Compare Fault Channel 0 */ +#define TC_FMR_ENCF1 (0x1u << 1) /**< \brief (TC_FMR) Enable Compare Fault Channel 1 */ +/* -------- TC_WPMR : (TC Offset: 0xE4) Write Protection Mode Register -------- */ +#define TC_WPMR_WPEN (0x1u << 0) /**< \brief (TC_WPMR) Write Protection Enable */ +#define TC_WPMR_WPKEY_Pos 8 +#define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /**< \brief (TC_WPMR) Write Protection Key */ +#define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) +#define TC_WPMR_WPKEY_PASSWD (0x54494Du << 8) /**< \brief (TC_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_TC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_trng.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_trng.h new file mode 100644 index 000000000..bfe569bd6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_trng.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TRNG_COMPONENT_ +#define _SAMV71_TRNG_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR True Random Number Generator */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TRNG True Random Number Generator */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Trng hardware registers */ +typedef struct { + __O uint32_t TRNG_CR; /**< \brief (Trng Offset: 0x00) Control Register */ + __I uint32_t Reserved1[3]; + __O uint32_t TRNG_IER; /**< \brief (Trng Offset: 0x10) Interrupt Enable Register */ + __O uint32_t TRNG_IDR; /**< \brief (Trng Offset: 0x14) Interrupt Disable Register */ + __I uint32_t TRNG_IMR; /**< \brief (Trng Offset: 0x18) Interrupt Mask Register */ + __I uint32_t TRNG_ISR; /**< \brief (Trng Offset: 0x1C) Interrupt Status Register */ + __I uint32_t Reserved2[12]; + __I uint32_t TRNG_ODATA; /**< \brief (Trng Offset: 0x50) Output Data Register */ +} Trng; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TRNG_CR : (TRNG Offset: 0x00) Control Register -------- */ +#define TRNG_CR_ENABLE (0x1u << 0) /**< \brief (TRNG_CR) Enables the TRNG to provide random values */ +#define TRNG_CR_KEY_Pos 8 +#define TRNG_CR_KEY_Msk (0xffffffu << TRNG_CR_KEY_Pos) /**< \brief (TRNG_CR) Security Key. */ +#define TRNG_CR_KEY(value) ((TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))) +#define TRNG_CR_KEY_PASSWD (0x524E47u << 8) /**< \brief (TRNG_CR) Writing any other value in this field aborts the write operation. */ +/* -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- */ +#define TRNG_IER_DATRDY (0x1u << 0) /**< \brief (TRNG_IER) Data Ready Interrupt Enable */ +/* -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- */ +#define TRNG_IDR_DATRDY (0x1u << 0) /**< \brief (TRNG_IDR) Data Ready Interrupt Disable */ +/* -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- */ +#define TRNG_IMR_DATRDY (0x1u << 0) /**< \brief (TRNG_IMR) Data Ready Interrupt Mask */ +/* -------- TRNG_ISR : (TRNG Offset: 0x1C) Interrupt Status Register -------- */ +#define TRNG_ISR_DATRDY (0x1u << 0) /**< \brief (TRNG_ISR) Data Ready */ +/* -------- TRNG_ODATA : (TRNG Offset: 0x50) Output Data Register -------- */ +#define TRNG_ODATA_ODATA_Pos 0 +#define TRNG_ODATA_ODATA_Msk (0xffffffffu << TRNG_ODATA_ODATA_Pos) /**< \brief (TRNG_ODATA) Output Data */ + +/*@}*/ + + +#endif /* _SAMV71_TRNG_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_twi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_twi.h new file mode 100644 index 000000000..9a40cd38b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_twi.h @@ -0,0 +1,165 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM_TWI_COMPONENT_ +#define _SAM_TWI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface */ +/* ============================================================================= */ +/** \addtogroup SAM_TWI Two-wire Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twi hardware registers */ +typedef struct { + __O uint32_t TWI_CR; /**< \brief (Twi Offset: 0x00) Control Register */ + __IO uint32_t TWI_MMR; /**< \brief (Twi Offset: 0x04) Master Mode Register */ + __IO uint32_t TWI_SMR; /**< \brief (Twi Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWI_IADR; /**< \brief (Twi Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWI_CWGR; /**< \brief (Twi Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWI_SR; /**< \brief (Twi Offset: 0x20) Status Register */ + __O uint32_t TWI_IER; /**< \brief (Twi Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWI_IDR; /**< \brief (Twi Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWI_IMR; /**< \brief (Twi Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWI_RHR; /**< \brief (Twi Offset: 0x30) Receive Holding Register */ + __O uint32_t TWI_THR; /**< \brief (Twi Offset: 0x34) Transmit Holding Register */ + __I uint32_t Reserved2[43]; + __IO uint32_t TWI_WPMR; /**< \brief (Twi Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWI_WPSR; /**< \brief (Twi Offset: 0xE8) Write Protection Status Register */ +} Twi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ +#define TWI_CR_START (0x1u << 0) /**< \brief (TWI_CR) Send a START Condition */ +#define TWI_CR_STOP (0x1u << 1) /**< \brief (TWI_CR) Send a STOP Condition */ +#define TWI_CR_MSEN (0x1u << 2) /**< \brief (TWI_CR) TWI Master Mode Enabled */ +#define TWI_CR_MSDIS (0x1u << 3) /**< \brief (TWI_CR) TWI Master Mode Disabled */ +#define TWI_CR_SVEN (0x1u << 4) /**< \brief (TWI_CR) TWI Slave Mode Enabled */ +#define TWI_CR_SVDIS (0x1u << 5) /**< \brief (TWI_CR) TWI Slave Mode Disabled */ +#define TWI_CR_QUICK (0x1u << 6) /**< \brief (TWI_CR) SMBUS Quick Command */ +#define TWI_CR_SWRST (0x1u << 7) /**< \brief (TWI_CR) Software Reset */ +/* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ +#define TWI_MMR_IADRSZ_Pos 8 +#define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /**< \brief (TWI_MMR) Internal Device Address Size */ +#define TWI_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWI_MMR) No internal device address */ +#define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWI_MMR) One-byte internal device address */ +#define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWI_MMR) Two-byte internal device address */ +#define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWI_MMR) Three-byte internal device address */ +#define TWI_MMR_MREAD (0x1u << 12) /**< \brief (TWI_MMR) Master Read Direction */ +#define TWI_MMR_DADR_Pos 16 +#define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /**< \brief (TWI_MMR) Device Address */ +#define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) +/* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ +#define TWI_SMR_SADR_Pos 16 +#define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /**< \brief (TWI_SMR) Slave Address */ +#define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) +/* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ +#define TWI_IADR_IADR_Pos 0 +#define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /**< \brief (TWI_IADR) Internal Address */ +#define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) +/* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWI_CWGR_CLDIV_Pos 0 +#define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /**< \brief (TWI_CWGR) Clock Low Divider */ +#define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) +#define TWI_CWGR_CHDIV_Pos 8 +#define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /**< \brief (TWI_CWGR) Clock High Divider */ +#define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) +#define TWI_CWGR_CKDIV_Pos 16 +#define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /**< \brief (TWI_CWGR) Clock Divider */ +#define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) +#define TWI_CWGR_HOLD_Pos 24 +#define TWI_CWGR_HOLD_Msk (0x1fu << TWI_CWGR_HOLD_Pos) /**< \brief (TWI_CWGR) TWD Hold Time versus TWCK falling */ +#define TWI_CWGR_HOLD(value) ((TWI_CWGR_HOLD_Msk & ((value) << TWI_CWGR_HOLD_Pos))) +/* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ +#define TWI_SR_TXCOMP (0x1u << 0) /**< \brief (TWI_SR) Transmission Completed (automatically set / reset) */ +#define TWI_SR_RXRDY (0x1u << 1) /**< \brief (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ +#define TWI_SR_TXRDY (0x1u << 2) /**< \brief (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ +#define TWI_SR_SVREAD (0x1u << 3) /**< \brief (TWI_SR) Slave Read (automatically set / reset) */ +#define TWI_SR_SVACC (0x1u << 4) /**< \brief (TWI_SR) Slave Access (automatically set / reset) */ +#define TWI_SR_GACC (0x1u << 5) /**< \brief (TWI_SR) General Call Access (clear on read) */ +#define TWI_SR_OVRE (0x1u << 6) /**< \brief (TWI_SR) Overrun Error (clear on read) */ +#define TWI_SR_NACK (0x1u << 8) /**< \brief (TWI_SR) Not Acknowledged (clear on read) */ +#define TWI_SR_ARBLST (0x1u << 9) /**< \brief (TWI_SR) Arbitration Lost (clear on read) */ +#define TWI_SR_SCLWS (0x1u << 10) /**< \brief (TWI_SR) Clock Wait State (automatically set / reset) */ +#define TWI_SR_EOSACC (0x1u << 11) /**< \brief (TWI_SR) End Of Slave Access (clear on read) */ +/* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ +#define TWI_IER_TXCOMP (0x1u << 0) /**< \brief (TWI_IER) Transmission Completed Interrupt Enable */ +#define TWI_IER_RXRDY (0x1u << 1) /**< \brief (TWI_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWI_IER_TXRDY (0x1u << 2) /**< \brief (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWI_IER_SVACC (0x1u << 4) /**< \brief (TWI_IER) Slave Access Interrupt Enable */ +#define TWI_IER_GACC (0x1u << 5) /**< \brief (TWI_IER) General Call Access Interrupt Enable */ +#define TWI_IER_OVRE (0x1u << 6) /**< \brief (TWI_IER) Overrun Error Interrupt Enable */ +#define TWI_IER_NACK (0x1u << 8) /**< \brief (TWI_IER) Not Acknowledge Interrupt Enable */ +#define TWI_IER_ARBLST (0x1u << 9) /**< \brief (TWI_IER) Arbitration Lost Interrupt Enable */ +#define TWI_IER_SCL_WS (0x1u << 10) /**< \brief (TWI_IER) Clock Wait State Interrupt Enable */ +#define TWI_IER_EOSACC (0x1u << 11) /**< \brief (TWI_IER) End Of Slave Access Interrupt Enable */ +/* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ +#define TWI_IDR_TXCOMP (0x1u << 0) /**< \brief (TWI_IDR) Transmission Completed Interrupt Disable */ +#define TWI_IDR_RXRDY (0x1u << 1) /**< \brief (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWI_IDR_TXRDY (0x1u << 2) /**< \brief (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWI_IDR_SVACC (0x1u << 4) /**< \brief (TWI_IDR) Slave Access Interrupt Disable */ +#define TWI_IDR_GACC (0x1u << 5) /**< \brief (TWI_IDR) General Call Access Interrupt Disable */ +#define TWI_IDR_OVRE (0x1u << 6) /**< \brief (TWI_IDR) Overrun Error Interrupt Disable */ +#define TWI_IDR_NACK (0x1u << 8) /**< \brief (TWI_IDR) Not Acknowledge Interrupt Disable */ +#define TWI_IDR_ARBLST (0x1u << 9) /**< \brief (TWI_IDR) Arbitration Lost Interrupt Disable */ +#define TWI_IDR_SCL_WS (0x1u << 10) /**< \brief (TWI_IDR) Clock Wait State Interrupt Disable */ +#define TWI_IDR_EOSACC (0x1u << 11) /**< \brief (TWI_IDR) End Of Slave Access Interrupt Disable */ +/* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWI_IMR_TXCOMP (0x1u << 0) /**< \brief (TWI_IMR) Transmission Completed Interrupt Mask */ +#define TWI_IMR_RXRDY (0x1u << 1) /**< \brief (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWI_IMR_TXRDY (0x1u << 2) /**< \brief (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWI_IMR_SVACC (0x1u << 4) /**< \brief (TWI_IMR) Slave Access Interrupt Mask */ +#define TWI_IMR_GACC (0x1u << 5) /**< \brief (TWI_IMR) General Call Access Interrupt Mask */ +#define TWI_IMR_OVRE (0x1u << 6) /**< \brief (TWI_IMR) Overrun Error Interrupt Mask */ +#define TWI_IMR_NACK (0x1u << 8) /**< \brief (TWI_IMR) Not Acknowledge Interrupt Mask */ +#define TWI_IMR_ARBLST (0x1u << 9) /**< \brief (TWI_IMR) Arbitration Lost Interrupt Mask */ +#define TWI_IMR_SCL_WS (0x1u << 10) /**< \brief (TWI_IMR) Clock Wait State Interrupt Mask */ +#define TWI_IMR_EOSACC (0x1u << 11) /**< \brief (TWI_IMR) End Of Slave Access Interrupt Mask */ +/* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ +#define TWI_RHR_RXDATA_Pos 0 +#define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /**< \brief (TWI_RHR) Master or Slave Receive Holding Data */ +/* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ +#define TWI_THR_TXDATA_Pos 0 +#define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /**< \brief (TWI_THR) Master or Slave Transmit Holding Data */ +#define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) +/* -------- TWI_WPMR : (TWI Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWI_WPMR_WPEN (0x1u << 0) /**< \brief (TWI_WPMR) Write Protection Enable */ +#define TWI_WPMR_WPKEY_Pos 8 +#define TWI_WPMR_WPKEY_Msk (0xffffffu << TWI_WPMR_WPKEY_Pos) /**< \brief (TWI_WPMR) Write Protection Key */ +#define TWI_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWI_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWI_WPSR : (TWI Offset: 0xE8) Write Protection Status Register -------- */ +#define TWI_WPSR_WPVS (0x1u << 0) /**< \brief (TWI_WPSR) Write Protection Violation Status */ +#define TWI_WPSR_WPVSRC_Pos 8 +#define TWI_WPSR_WPVSRC_Msk (0xffffffu << TWI_WPSR_WPVSRC_Pos) /**< \brief (TWI_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAM_TWI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_twihs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_twihs.h new file mode 100644 index 000000000..cb81b0251 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_twihs.h @@ -0,0 +1,250 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS_COMPONENT_ +#define _SAMV71_TWIHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Two-wire Interface High Speed */ +/* ============================================================================= */ +/** \addtogroup SAMV71_TWIHS Two-wire Interface High Speed */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Twihs hardware registers */ +typedef struct { + __O uint32_t TWIHS_CR; /**< \brief (Twihs Offset: 0x00) Control Register */ + __IO uint32_t TWIHS_MMR; /**< \brief (Twihs Offset: 0x04) Master Mode Register */ + __IO uint32_t TWIHS_SMR; /**< \brief (Twihs Offset: 0x08) Slave Mode Register */ + __IO uint32_t TWIHS_IADR; /**< \brief (Twihs Offset: 0x0C) Internal Address Register */ + __IO uint32_t TWIHS_CWGR; /**< \brief (Twihs Offset: 0x10) Clock Waveform Generator Register */ + __I uint32_t Reserved1[3]; + __I uint32_t TWIHS_SR; /**< \brief (Twihs Offset: 0x20) Status Register */ + __O uint32_t TWIHS_IER; /**< \brief (Twihs Offset: 0x24) Interrupt Enable Register */ + __O uint32_t TWIHS_IDR; /**< \brief (Twihs Offset: 0x28) Interrupt Disable Register */ + __I uint32_t TWIHS_IMR; /**< \brief (Twihs Offset: 0x2C) Interrupt Mask Register */ + __I uint32_t TWIHS_RHR; /**< \brief (Twihs Offset: 0x30) Receive Holding Register */ + __O uint32_t TWIHS_THR; /**< \brief (Twihs Offset: 0x34) Transmit Holding Register */ + __IO uint32_t TWIHS_SMBTR; /**< \brief (Twihs Offset: 0x38) SMBus Timing Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t TWIHS_FILTR; /**< \brief (Twihs Offset: 0x44) Filter Register */ + __I uint32_t Reserved3[1]; + __IO uint32_t TWIHS_SWMR; /**< \brief (Twihs Offset: 0x4C) SleepWalking Matching Register */ + __I uint32_t Reserved4[37]; + __IO uint32_t TWIHS_WPMR; /**< \brief (Twihs Offset: 0xE4) Write Protection Mode Register */ + __I uint32_t TWIHS_WPSR; /**< \brief (Twihs Offset: 0xE8) Write Protection Status Register */ +} Twihs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- TWIHS_CR : (TWIHS Offset: 0x00) Control Register -------- */ +#define TWIHS_CR_START (0x1u << 0) /**< \brief (TWIHS_CR) Send a START Condition */ +#define TWIHS_CR_STOP (0x1u << 1) /**< \brief (TWIHS_CR) Send a STOP Condition */ +#define TWIHS_CR_MSEN (0x1u << 2) /**< \brief (TWIHS_CR) TWIHS Master Mode Enabled */ +#define TWIHS_CR_MSDIS (0x1u << 3) /**< \brief (TWIHS_CR) TWIHS Master Mode Disabled */ +#define TWIHS_CR_SVEN (0x1u << 4) /**< \brief (TWIHS_CR) TWIHS Slave Mode Enabled */ +#define TWIHS_CR_SVDIS (0x1u << 5) /**< \brief (TWIHS_CR) TWIHS Slave Mode Disabled */ +#define TWIHS_CR_QUICK (0x1u << 6) /**< \brief (TWIHS_CR) SMBus Quick Command */ +#define TWIHS_CR_SWRST (0x1u << 7) /**< \brief (TWIHS_CR) Software Reset */ +#define TWIHS_CR_HSEN (0x1u << 8) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Enabled */ +#define TWIHS_CR_HSDIS (0x1u << 9) /**< \brief (TWIHS_CR) TWIHS High-Speed Mode Disabled */ +#define TWIHS_CR_SMBEN (0x1u << 10) /**< \brief (TWIHS_CR) SMBus Mode Enabled */ +#define TWIHS_CR_SMBDIS (0x1u << 11) /**< \brief (TWIHS_CR) SMBus Mode Disabled */ +#define TWIHS_CR_PECEN (0x1u << 12) /**< \brief (TWIHS_CR) Packet Error Checking Enable */ +#define TWIHS_CR_PECDIS (0x1u << 13) /**< \brief (TWIHS_CR) Packet Error Checking Disable */ +#define TWIHS_CR_PECRQ (0x1u << 14) /**< \brief (TWIHS_CR) PEC Request */ +#define TWIHS_CR_CLEAR (0x1u << 15) /**< \brief (TWIHS_CR) Bus CLEAR Command */ +/* -------- TWIHS_MMR : (TWIHS Offset: 0x04) Master Mode Register -------- */ +#define TWIHS_MMR_IADRSZ_Pos 8 +#define TWIHS_MMR_IADRSZ_Msk (0x3u << TWIHS_MMR_IADRSZ_Pos) /**< \brief (TWIHS_MMR) Internal Device Address Size */ +#define TWIHS_MMR_IADRSZ(value) ((TWIHS_MMR_IADRSZ_Msk & ((value) << TWIHS_MMR_IADRSZ_Pos))) +#define TWIHS_MMR_IADRSZ_NONE (0x0u << 8) /**< \brief (TWIHS_MMR) No internal device address */ +#define TWIHS_MMR_IADRSZ_1_BYTE (0x1u << 8) /**< \brief (TWIHS_MMR) One-byte internal device address */ +#define TWIHS_MMR_IADRSZ_2_BYTE (0x2u << 8) /**< \brief (TWIHS_MMR) Two-byte internal device address */ +#define TWIHS_MMR_IADRSZ_3_BYTE (0x3u << 8) /**< \brief (TWIHS_MMR) Three-byte internal device address */ +#define TWIHS_MMR_MREAD (0x1u << 12) /**< \brief (TWIHS_MMR) Master Read Direction */ +#define TWIHS_MMR_DADR_Pos 16 +#define TWIHS_MMR_DADR_Msk (0x7fu << TWIHS_MMR_DADR_Pos) /**< \brief (TWIHS_MMR) Device Address */ +#define TWIHS_MMR_DADR(value) ((TWIHS_MMR_DADR_Msk & ((value) << TWIHS_MMR_DADR_Pos))) +/* -------- TWIHS_SMR : (TWIHS Offset: 0x08) Slave Mode Register -------- */ +#define TWIHS_SMR_NACKEN (0x1u << 0) /**< \brief (TWIHS_SMR) Slave Receiver Data Phase NACK enable */ +#define TWIHS_SMR_SMDA (0x1u << 2) /**< \brief (TWIHS_SMR) SMBus Default Address */ +#define TWIHS_SMR_SMHH (0x1u << 3) /**< \brief (TWIHS_SMR) SMBus Host Header */ +#define TWIHS_SMR_SCLWSDIS (0x1u << 6) /**< \brief (TWIHS_SMR) Clock Wait State Disable */ +#define TWIHS_SMR_MASK_Pos 8 +#define TWIHS_SMR_MASK_Msk (0x7fu << TWIHS_SMR_MASK_Pos) /**< \brief (TWIHS_SMR) Slave Address Mask */ +#define TWIHS_SMR_MASK(value) ((TWIHS_SMR_MASK_Msk & ((value) << TWIHS_SMR_MASK_Pos))) +#define TWIHS_SMR_SADR_Pos 16 +#define TWIHS_SMR_SADR_Msk (0x7fu << TWIHS_SMR_SADR_Pos) /**< \brief (TWIHS_SMR) Slave Address */ +#define TWIHS_SMR_SADR(value) ((TWIHS_SMR_SADR_Msk & ((value) << TWIHS_SMR_SADR_Pos))) +#define TWIHS_SMR_SADR1EN (0x1u << 28) /**< \brief (TWIHS_SMR) Slave Address 1 Enable */ +#define TWIHS_SMR_SADR2EN (0x1u << 29) /**< \brief (TWIHS_SMR) Slave Address 2 Enable */ +#define TWIHS_SMR_SADR3EN (0x1u << 30) /**< \brief (TWIHS_SMR) Slave Address 3 Enable */ +#define TWIHS_SMR_DATAMEN (0x1u << 31) /**< \brief (TWIHS_SMR) Data Matching Enable */ +/* -------- TWIHS_IADR : (TWIHS Offset: 0x0C) Internal Address Register -------- */ +#define TWIHS_IADR_IADR_Pos 0 +#define TWIHS_IADR_IADR_Msk (0xffffffu << TWIHS_IADR_IADR_Pos) /**< \brief (TWIHS_IADR) Internal Address */ +#define TWIHS_IADR_IADR(value) ((TWIHS_IADR_IADR_Msk & ((value) << TWIHS_IADR_IADR_Pos))) +/* -------- TWIHS_CWGR : (TWIHS Offset: 0x10) Clock Waveform Generator Register -------- */ +#define TWIHS_CWGR_CLDIV_Pos 0 +#define TWIHS_CWGR_CLDIV_Msk (0xffu << TWIHS_CWGR_CLDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Low Divider */ +#define TWIHS_CWGR_CLDIV(value) ((TWIHS_CWGR_CLDIV_Msk & ((value) << TWIHS_CWGR_CLDIV_Pos))) +#define TWIHS_CWGR_CHDIV_Pos 8 +#define TWIHS_CWGR_CHDIV_Msk (0xffu << TWIHS_CWGR_CHDIV_Pos) /**< \brief (TWIHS_CWGR) Clock High Divider */ +#define TWIHS_CWGR_CHDIV(value) ((TWIHS_CWGR_CHDIV_Msk & ((value) << TWIHS_CWGR_CHDIV_Pos))) +#define TWIHS_CWGR_CKDIV_Pos 16 +#define TWIHS_CWGR_CKDIV_Msk (0x7u << TWIHS_CWGR_CKDIV_Pos) /**< \brief (TWIHS_CWGR) Clock Divider */ +#define TWIHS_CWGR_CKDIV(value) ((TWIHS_CWGR_CKDIV_Msk & ((value) << TWIHS_CWGR_CKDIV_Pos))) +#define TWIHS_CWGR_HOLD_Pos 24 +#define TWIHS_CWGR_HOLD_Msk (0x1fu << TWIHS_CWGR_HOLD_Pos) /**< \brief (TWIHS_CWGR) TWD Hold Time Versus TWCK Falling */ +#define TWIHS_CWGR_HOLD(value) ((TWIHS_CWGR_HOLD_Msk & ((value) << TWIHS_CWGR_HOLD_Pos))) +/* -------- TWIHS_SR : (TWIHS Offset: 0x20) Status Register -------- */ +#define TWIHS_SR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_SR) Transmission Completed (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_RXRDY (0x1u << 1) /**< \brief (TWIHS_SR) Receive Holding Register Ready (cleared by reading TWIHS_RHR) */ +#define TWIHS_SR_TXRDY (0x1u << 2) /**< \brief (TWIHS_SR) Transmit Holding Register Ready (cleared by writing TWIHS_THR) */ +#define TWIHS_SR_SVREAD (0x1u << 3) /**< \brief (TWIHS_SR) Slave Read */ +#define TWIHS_SR_SVACC (0x1u << 4) /**< \brief (TWIHS_SR) Slave Access */ +#define TWIHS_SR_GACC (0x1u << 5) /**< \brief (TWIHS_SR) General Call Access (cleared on read) */ +#define TWIHS_SR_OVRE (0x1u << 6) /**< \brief (TWIHS_SR) Overrun Error (cleared on read) */ +#define TWIHS_SR_UNRE (0x1u << 7) /**< \brief (TWIHS_SR) Underrun Error (cleared on read) */ +#define TWIHS_SR_NACK (0x1u << 8) /**< \brief (TWIHS_SR) Not Acknowledged (cleared on read) */ +#define TWIHS_SR_ARBLST (0x1u << 9) /**< \brief (TWIHS_SR) Arbitration Lost (cleared on read) */ +#define TWIHS_SR_SCLWS (0x1u << 10) /**< \brief (TWIHS_SR) Clock Wait State */ +#define TWIHS_SR_EOSACC (0x1u << 11) /**< \brief (TWIHS_SR) End Of Slave Access (cleared on read) */ +#define TWIHS_SR_MCACK (0x1u << 16) /**< \brief (TWIHS_SR) Master Code Acknowledge (cleared on read) */ +#define TWIHS_SR_TOUT (0x1u << 18) /**< \brief (TWIHS_SR) Timeout Error (cleared on read) */ +#define TWIHS_SR_PECERR (0x1u << 19) /**< \brief (TWIHS_SR) PEC Error (cleared on read) */ +#define TWIHS_SR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_SR) SMBus Default Address Match (cleared on read) */ +#define TWIHS_SR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_SR) SMBus Host Header Address Match (cleared on read) */ +#define TWIHS_SR_SCL (0x1u << 24) /**< \brief (TWIHS_SR) SCL line value */ +#define TWIHS_SR_SDA (0x1u << 25) /**< \brief (TWIHS_SR) SDA line value */ +/* -------- TWIHS_IER : (TWIHS Offset: 0x24) Interrupt Enable Register -------- */ +#define TWIHS_IER_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IER) Transmission Completed Interrupt Enable */ +#define TWIHS_IER_RXRDY (0x1u << 1) /**< \brief (TWIHS_IER) Receive Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_TXRDY (0x1u << 2) /**< \brief (TWIHS_IER) Transmit Holding Register Ready Interrupt Enable */ +#define TWIHS_IER_SVACC (0x1u << 4) /**< \brief (TWIHS_IER) Slave Access Interrupt Enable */ +#define TWIHS_IER_GACC (0x1u << 5) /**< \brief (TWIHS_IER) General Call Access Interrupt Enable */ +#define TWIHS_IER_OVRE (0x1u << 6) /**< \brief (TWIHS_IER) Overrun Error Interrupt Enable */ +#define TWIHS_IER_UNRE (0x1u << 7) /**< \brief (TWIHS_IER) Underrun Error Interrupt Enable */ +#define TWIHS_IER_NACK (0x1u << 8) /**< \brief (TWIHS_IER) Not Acknowledge Interrupt Enable */ +#define TWIHS_IER_ARBLST (0x1u << 9) /**< \brief (TWIHS_IER) Arbitration Lost Interrupt Enable */ +#define TWIHS_IER_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IER) Clock Wait State Interrupt Enable */ +#define TWIHS_IER_EOSACC (0x1u << 11) /**< \brief (TWIHS_IER) End Of Slave Access Interrupt Enable */ +#define TWIHS_IER_MCACK (0x1u << 16) /**< \brief (TWIHS_IER) Master Code Acknowledge Interrupt Enable */ +#define TWIHS_IER_TOUT (0x1u << 18) /**< \brief (TWIHS_IER) Timeout Error Interrupt Enable */ +#define TWIHS_IER_PECERR (0x1u << 19) /**< \brief (TWIHS_IER) PEC Error Interrupt Enable */ +#define TWIHS_IER_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IER) SMBus Default Address Match Interrupt Enable */ +#define TWIHS_IER_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IER) SMBus Host Header Address Match Interrupt Enable */ +/* -------- TWIHS_IDR : (TWIHS Offset: 0x28) Interrupt Disable Register -------- */ +#define TWIHS_IDR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IDR) Transmission Completed Interrupt Disable */ +#define TWIHS_IDR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IDR) Receive Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IDR) Transmit Holding Register Ready Interrupt Disable */ +#define TWIHS_IDR_SVACC (0x1u << 4) /**< \brief (TWIHS_IDR) Slave Access Interrupt Disable */ +#define TWIHS_IDR_GACC (0x1u << 5) /**< \brief (TWIHS_IDR) General Call Access Interrupt Disable */ +#define TWIHS_IDR_OVRE (0x1u << 6) /**< \brief (TWIHS_IDR) Overrun Error Interrupt Disable */ +#define TWIHS_IDR_UNRE (0x1u << 7) /**< \brief (TWIHS_IDR) Underrun Error Interrupt Disable */ +#define TWIHS_IDR_NACK (0x1u << 8) /**< \brief (TWIHS_IDR) Not Acknowledge Interrupt Disable */ +#define TWIHS_IDR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IDR) Arbitration Lost Interrupt Disable */ +#define TWIHS_IDR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IDR) Clock Wait State Interrupt Disable */ +#define TWIHS_IDR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IDR) End Of Slave Access Interrupt Disable */ +#define TWIHS_IDR_MCACK (0x1u << 16) /**< \brief (TWIHS_IDR) Master Code Acknowledge Interrupt Disable */ +#define TWIHS_IDR_TOUT (0x1u << 18) /**< \brief (TWIHS_IDR) Timeout Error Interrupt Disable */ +#define TWIHS_IDR_PECERR (0x1u << 19) /**< \brief (TWIHS_IDR) PEC Error Interrupt Disable */ +#define TWIHS_IDR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IDR) SMBus Default Address Match Interrupt Disable */ +#define TWIHS_IDR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IDR) SMBus Host Header Address Match Interrupt Disable */ +/* -------- TWIHS_IMR : (TWIHS Offset: 0x2C) Interrupt Mask Register -------- */ +#define TWIHS_IMR_TXCOMP (0x1u << 0) /**< \brief (TWIHS_IMR) Transmission Completed Interrupt Mask */ +#define TWIHS_IMR_RXRDY (0x1u << 1) /**< \brief (TWIHS_IMR) Receive Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_TXRDY (0x1u << 2) /**< \brief (TWIHS_IMR) Transmit Holding Register Ready Interrupt Mask */ +#define TWIHS_IMR_SVACC (0x1u << 4) /**< \brief (TWIHS_IMR) Slave Access Interrupt Mask */ +#define TWIHS_IMR_GACC (0x1u << 5) /**< \brief (TWIHS_IMR) General Call Access Interrupt Mask */ +#define TWIHS_IMR_OVRE (0x1u << 6) /**< \brief (TWIHS_IMR) Overrun Error Interrupt Mask */ +#define TWIHS_IMR_UNRE (0x1u << 7) /**< \brief (TWIHS_IMR) Underrun Error Interrupt Mask */ +#define TWIHS_IMR_NACK (0x1u << 8) /**< \brief (TWIHS_IMR) Not Acknowledge Interrupt Mask */ +#define TWIHS_IMR_ARBLST (0x1u << 9) /**< \brief (TWIHS_IMR) Arbitration Lost Interrupt Mask */ +#define TWIHS_IMR_SCL_WS (0x1u << 10) /**< \brief (TWIHS_IMR) Clock Wait State Interrupt Mask */ +#define TWIHS_IMR_EOSACC (0x1u << 11) /**< \brief (TWIHS_IMR) End Of Slave Access Interrupt Mask */ +#define TWIHS_IMR_MCACK (0x1u << 16) /**< \brief (TWIHS_IMR) Master Code Acknowledge Interrupt Mask */ +#define TWIHS_IMR_TOUT (0x1u << 18) /**< \brief (TWIHS_IMR) Timeout Error Interrupt Mask */ +#define TWIHS_IMR_PECERR (0x1u << 19) /**< \brief (TWIHS_IMR) PEC Error Interrupt Mask */ +#define TWIHS_IMR_SMBDAM (0x1u << 20) /**< \brief (TWIHS_IMR) SMBus Default Address Match Interrupt Mask */ +#define TWIHS_IMR_SMBHHM (0x1u << 21) /**< \brief (TWIHS_IMR) SMBus Host Header Address Match Interrupt Mask */ +/* -------- TWIHS_RHR : (TWIHS Offset: 0x30) Receive Holding Register -------- */ +#define TWIHS_RHR_RXDATA_Pos 0 +#define TWIHS_RHR_RXDATA_Msk (0xffu << TWIHS_RHR_RXDATA_Pos) /**< \brief (TWIHS_RHR) Master or Slave Receive Holding Data */ +/* -------- TWIHS_THR : (TWIHS Offset: 0x34) Transmit Holding Register -------- */ +#define TWIHS_THR_TXDATA_Pos 0 +#define TWIHS_THR_TXDATA_Msk (0xffu << TWIHS_THR_TXDATA_Pos) /**< \brief (TWIHS_THR) Master or Slave Transmit Holding Data */ +#define TWIHS_THR_TXDATA(value) ((TWIHS_THR_TXDATA_Msk & ((value) << TWIHS_THR_TXDATA_Pos))) +/* -------- TWIHS_SMBTR : (TWIHS Offset: 0x38) SMBus Timing Register -------- */ +#define TWIHS_SMBTR_PRESC_Pos 0 +#define TWIHS_SMBTR_PRESC_Msk (0xfu << TWIHS_SMBTR_PRESC_Pos) /**< \brief (TWIHS_SMBTR) SMBus Clock Prescaler */ +#define TWIHS_SMBTR_PRESC(value) ((TWIHS_SMBTR_PRESC_Msk & ((value) << TWIHS_SMBTR_PRESC_Pos))) +#define TWIHS_SMBTR_TLOWS_Pos 8 +#define TWIHS_SMBTR_TLOWS_Msk (0xffu << TWIHS_SMBTR_TLOWS_Pos) /**< \brief (TWIHS_SMBTR) Slave Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWS(value) ((TWIHS_SMBTR_TLOWS_Msk & ((value) << TWIHS_SMBTR_TLOWS_Pos))) +#define TWIHS_SMBTR_TLOWM_Pos 16 +#define TWIHS_SMBTR_TLOWM_Msk (0xffu << TWIHS_SMBTR_TLOWM_Pos) /**< \brief (TWIHS_SMBTR) Master Clock Stretch Maximum Cycles */ +#define TWIHS_SMBTR_TLOWM(value) ((TWIHS_SMBTR_TLOWM_Msk & ((value) << TWIHS_SMBTR_TLOWM_Pos))) +#define TWIHS_SMBTR_THMAX_Pos 24 +#define TWIHS_SMBTR_THMAX_Msk (0xffu << TWIHS_SMBTR_THMAX_Pos) /**< \brief (TWIHS_SMBTR) Clock High Maximum Cycles */ +#define TWIHS_SMBTR_THMAX(value) ((TWIHS_SMBTR_THMAX_Msk & ((value) << TWIHS_SMBTR_THMAX_Pos))) +/* -------- TWIHS_FILTR : (TWIHS Offset: 0x44) Filter Register -------- */ +#define TWIHS_FILTR_FILT (0x1u << 0) /**< \brief (TWIHS_FILTR) RX Digital Filter */ +#define TWIHS_FILTR_PADFEN (0x1u << 1) /**< \brief (TWIHS_FILTR) PAD Filter Enable */ +#define TWIHS_FILTR_PADFCFG (0x1u << 2) /**< \brief (TWIHS_FILTR) PAD Filter Config */ +#define TWIHS_FILTR_THRES_Pos 8 +#define TWIHS_FILTR_THRES_Msk (0x7u << TWIHS_FILTR_THRES_Pos) /**< \brief (TWIHS_FILTR) Digital Filter Threshold */ +#define TWIHS_FILTR_THRES(value) ((TWIHS_FILTR_THRES_Msk & ((value) << TWIHS_FILTR_THRES_Pos))) +/* -------- TWIHS_SWMR : (TWIHS Offset: 0x4C) SleepWalking Matching Register -------- */ +#define TWIHS_SWMR_SADR1_Pos 0 +#define TWIHS_SWMR_SADR1_Msk (0x7fu << TWIHS_SWMR_SADR1_Pos) /**< \brief (TWIHS_SWMR) Slave Address 1 */ +#define TWIHS_SWMR_SADR1(value) ((TWIHS_SWMR_SADR1_Msk & ((value) << TWIHS_SWMR_SADR1_Pos))) +#define TWIHS_SWMR_SADR2_Pos 8 +#define TWIHS_SWMR_SADR2_Msk (0x7fu << TWIHS_SWMR_SADR2_Pos) /**< \brief (TWIHS_SWMR) Slave Address 2 */ +#define TWIHS_SWMR_SADR2(value) ((TWIHS_SWMR_SADR2_Msk & ((value) << TWIHS_SWMR_SADR2_Pos))) +#define TWIHS_SWMR_SADR3_Pos 16 +#define TWIHS_SWMR_SADR3_Msk (0x7fu << TWIHS_SWMR_SADR3_Pos) /**< \brief (TWIHS_SWMR) Slave Address 3 */ +#define TWIHS_SWMR_SADR3(value) ((TWIHS_SWMR_SADR3_Msk & ((value) << TWIHS_SWMR_SADR3_Pos))) +#define TWIHS_SWMR_DATAM_Pos 24 +#define TWIHS_SWMR_DATAM_Msk (0xffu << TWIHS_SWMR_DATAM_Pos) /**< \brief (TWIHS_SWMR) Data Match */ +#define TWIHS_SWMR_DATAM(value) ((TWIHS_SWMR_DATAM_Msk & ((value) << TWIHS_SWMR_DATAM_Pos))) +/* -------- TWIHS_WPMR : (TWIHS Offset: 0xE4) Write Protection Mode Register -------- */ +#define TWIHS_WPMR_WPEN (0x1u << 0) /**< \brief (TWIHS_WPMR) Write Protection Enable */ +#define TWIHS_WPMR_WPKEY_Pos 8 +#define TWIHS_WPMR_WPKEY_Msk (0xffffffu << TWIHS_WPMR_WPKEY_Pos) /**< \brief (TWIHS_WPMR) Write Protection Key */ +#define TWIHS_WPMR_WPKEY(value) ((TWIHS_WPMR_WPKEY_Msk & ((value) << TWIHS_WPMR_WPKEY_Pos))) +#define TWIHS_WPMR_WPKEY_PASSWD (0x545749u << 8) /**< \brief (TWIHS_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 */ +/* -------- TWIHS_WPSR : (TWIHS Offset: 0xE8) Write Protection Status Register -------- */ +#define TWIHS_WPSR_WPVS (0x1u << 0) /**< \brief (TWIHS_WPSR) Write Protection Violation Status */ +#define TWIHS_WPSR_WPVSRC_Pos 8 +#define TWIHS_WPSR_WPVSRC_Msk (0xffffffu << TWIHS_WPSR_WPVSRC_Pos) /**< \brief (TWIHS_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_TWIHS_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_uart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_uart.h new file mode 100644 index 000000000..114980c75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_uart.h @@ -0,0 +1,151 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART_COMPONENT_ +#define _SAMV71_UART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UART Universal Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Uart hardware registers */ +typedef struct { + __O uint32_t UART_CR; /**< \brief (Uart Offset: 0x0000) Control Register */ + __IO uint32_t UART_MR; /**< \brief (Uart Offset: 0x0004) Mode Register */ + __O uint32_t UART_IER; /**< \brief (Uart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t UART_IDR; /**< \brief (Uart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t UART_IMR; /**< \brief (Uart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t UART_SR; /**< \brief (Uart Offset: 0x0014) Status Register */ + __I uint32_t UART_RHR; /**< \brief (Uart Offset: 0x0018) Receive Holding Register */ + __O uint32_t UART_THR; /**< \brief (Uart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t UART_BRGR; /**< \brief (Uart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t UART_CMPR; /**< \brief (Uart Offset: 0x0024) Comparison Register */ + __I uint32_t Reserved1[47]; + __IO uint32_t UART_WPMR; /**< \brief (Uart Offset: 0x00E4) Write Protection Mode Register */ +} Uart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */ +#define UART_CR_RSTRX (0x1u << 2) /**< \brief (UART_CR) Reset Receiver */ +#define UART_CR_RSTTX (0x1u << 3) /**< \brief (UART_CR) Reset Transmitter */ +#define UART_CR_RXEN (0x1u << 4) /**< \brief (UART_CR) Receiver Enable */ +#define UART_CR_RXDIS (0x1u << 5) /**< \brief (UART_CR) Receiver Disable */ +#define UART_CR_TXEN (0x1u << 6) /**< \brief (UART_CR) Transmitter Enable */ +#define UART_CR_TXDIS (0x1u << 7) /**< \brief (UART_CR) Transmitter Disable */ +#define UART_CR_RSTSTA (0x1u << 8) /**< \brief (UART_CR) Reset Status */ +#define UART_CR_REQCLR (0x1u << 12) /**< \brief (UART_CR) Request Clear */ +/* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */ +#define UART_MR_FILTER (0x1u << 4) /**< \brief (UART_MR) Receiver Digital Filter */ +#define UART_MR_FILTER_DISABLED (0x0u << 4) /**< \brief (UART_MR) UART does not filter the receive line. */ +#define UART_MR_FILTER_ENABLED (0x1u << 4) /**< \brief (UART_MR) UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). */ +#define UART_MR_PAR_Pos 9 +#define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) /**< \brief (UART_MR) Parity Type */ +#define UART_MR_PAR(value) ((UART_MR_PAR_Msk & ((value) << UART_MR_PAR_Pos))) +#define UART_MR_PAR_EVEN (0x0u << 9) /**< \brief (UART_MR) Even Parity */ +#define UART_MR_PAR_ODD (0x1u << 9) /**< \brief (UART_MR) Odd Parity */ +#define UART_MR_PAR_SPACE (0x2u << 9) /**< \brief (UART_MR) Space: parity forced to 0 */ +#define UART_MR_PAR_MARK (0x3u << 9) /**< \brief (UART_MR) Mark: parity forced to 1 */ +#define UART_MR_PAR_NO (0x4u << 9) /**< \brief (UART_MR) No parity */ +#define UART_MR_BRSRCCK (0x1u << 12) /**< \brief (UART_MR) Baud Rate Source Clock */ +#define UART_MR_BRSRCCK_PERIPH_CLK (0x0u << 12) /**< \brief (UART_MR) The baud rate is driven by the peripheral clock */ +#define UART_MR_BRSRCCK_PMC_PCK (0x1u << 12) /**< \brief (UART_MR) The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). */ +#define UART_MR_CHMODE_Pos 14 +#define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) /**< \brief (UART_MR) Channel Mode */ +#define UART_MR_CHMODE(value) ((UART_MR_CHMODE_Msk & ((value) << UART_MR_CHMODE_Pos))) +#define UART_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (UART_MR) Normal mode */ +#define UART_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (UART_MR) Automatic echo */ +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (UART_MR) Local loopback */ +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (UART_MR) Remote loopback */ +/* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */ +#define UART_IER_RXRDY (0x1u << 0) /**< \brief (UART_IER) Enable RXRDY Interrupt */ +#define UART_IER_TXRDY (0x1u << 1) /**< \brief (UART_IER) Enable TXRDY Interrupt */ +#define UART_IER_OVRE (0x1u << 5) /**< \brief (UART_IER) Enable Overrun Error Interrupt */ +#define UART_IER_FRAME (0x1u << 6) /**< \brief (UART_IER) Enable Framing Error Interrupt */ +#define UART_IER_PARE (0x1u << 7) /**< \brief (UART_IER) Enable Parity Error Interrupt */ +#define UART_IER_TXEMPTY (0x1u << 9) /**< \brief (UART_IER) Enable TXEMPTY Interrupt */ +#define UART_IER_CMP (0x1u << 15) /**< \brief (UART_IER) Enable Comparison Interrupt */ +/* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */ +#define UART_IDR_RXRDY (0x1u << 0) /**< \brief (UART_IDR) Disable RXRDY Interrupt */ +#define UART_IDR_TXRDY (0x1u << 1) /**< \brief (UART_IDR) Disable TXRDY Interrupt */ +#define UART_IDR_OVRE (0x1u << 5) /**< \brief (UART_IDR) Disable Overrun Error Interrupt */ +#define UART_IDR_FRAME (0x1u << 6) /**< \brief (UART_IDR) Disable Framing Error Interrupt */ +#define UART_IDR_PARE (0x1u << 7) /**< \brief (UART_IDR) Disable Parity Error Interrupt */ +#define UART_IDR_TXEMPTY (0x1u << 9) /**< \brief (UART_IDR) Disable TXEMPTY Interrupt */ +#define UART_IDR_CMP (0x1u << 15) /**< \brief (UART_IDR) Disable Comparison Interrupt */ +/* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */ +#define UART_IMR_RXRDY (0x1u << 0) /**< \brief (UART_IMR) Mask RXRDY Interrupt */ +#define UART_IMR_TXRDY (0x1u << 1) /**< \brief (UART_IMR) Disable TXRDY Interrupt */ +#define UART_IMR_OVRE (0x1u << 5) /**< \brief (UART_IMR) Mask Overrun Error Interrupt */ +#define UART_IMR_FRAME (0x1u << 6) /**< \brief (UART_IMR) Mask Framing Error Interrupt */ +#define UART_IMR_PARE (0x1u << 7) /**< \brief (UART_IMR) Mask Parity Error Interrupt */ +#define UART_IMR_TXEMPTY (0x1u << 9) /**< \brief (UART_IMR) Mask TXEMPTY Interrupt */ +#define UART_IMR_CMP (0x1u << 15) /**< \brief (UART_IMR) Mask Comparison Interrupt */ +/* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */ +#define UART_SR_RXRDY (0x1u << 0) /**< \brief (UART_SR) Receiver Ready */ +#define UART_SR_TXRDY (0x1u << 1) /**< \brief (UART_SR) Transmitter Ready */ +#define UART_SR_OVRE (0x1u << 5) /**< \brief (UART_SR) Overrun Error */ +#define UART_SR_FRAME (0x1u << 6) /**< \brief (UART_SR) Framing Error */ +#define UART_SR_PARE (0x1u << 7) /**< \brief (UART_SR) Parity Error */ +#define UART_SR_TXEMPTY (0x1u << 9) /**< \brief (UART_SR) Transmitter Empty */ +#define UART_SR_CMP (0x1u << 15) /**< \brief (UART_SR) Comparison Match */ +/* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */ +#define UART_RHR_RXCHR_Pos 0 +#define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) /**< \brief (UART_RHR) Received Character */ +/* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */ +#define UART_THR_TXCHR_Pos 0 +#define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) /**< \brief (UART_THR) Character to be Transmitted */ +#define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) +/* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define UART_BRGR_CD_Pos 0 +#define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) /**< \brief (UART_BRGR) Clock Divisor */ +#define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) +/* -------- UART_CMPR : (UART Offset: 0x0024) Comparison Register -------- */ +#define UART_CMPR_VAL1_Pos 0 +#define UART_CMPR_VAL1_Msk (0xffu << UART_CMPR_VAL1_Pos) /**< \brief (UART_CMPR) First Comparison Value for Received Character */ +#define UART_CMPR_VAL1(value) ((UART_CMPR_VAL1_Msk & ((value) << UART_CMPR_VAL1_Pos))) +#define UART_CMPR_CMPMODE (0x1u << 12) /**< \brief (UART_CMPR) Comparison Mode */ +#define UART_CMPR_CMPMODE_FLAG_ONLY (0x0u << 12) /**< \brief (UART_CMPR) Any character is received and comparison function drives CMP flag. */ +#define UART_CMPR_CMPMODE_START_CONDITION (0x1u << 12) /**< \brief (UART_CMPR) Comparison condition must be met to start reception. */ +#define UART_CMPR_CMPPAR (0x1u << 14) /**< \brief (UART_CMPR) Compare Parity */ +#define UART_CMPR_VAL2_Pos 16 +#define UART_CMPR_VAL2_Msk (0xffu << UART_CMPR_VAL2_Pos) /**< \brief (UART_CMPR) Second Comparison Value for Received Character */ +#define UART_CMPR_VAL2(value) ((UART_CMPR_VAL2_Msk & ((value) << UART_CMPR_VAL2_Pos))) +/* -------- UART_WPMR : (UART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define UART_WPMR_WPEN (0x1u << 0) /**< \brief (UART_WPMR) Write Protection Enable */ +#define UART_WPMR_WPKEY_Pos 8 +#define UART_WPMR_WPKEY_Msk (0xffffffu << UART_WPMR_WPKEY_Pos) /**< \brief (UART_WPMR) Write Protection Key */ +#define UART_WPMR_WPKEY(value) ((UART_WPMR_WPKEY_Msk & ((value) << UART_WPMR_WPKEY_Pos))) +#define UART_WPMR_WPKEY_PASSWD (0x554152u << 8) /**< \brief (UART_WPMR) Writing any other value in this field aborts the write operation.Always reads as 0. */ + +/*@}*/ + + +#endif /* _SAMV71_UART_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_uotghs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_uotghs.h new file mode 100644 index 000000000..884a668dd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_uotghs.h @@ -0,0 +1,1033 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAM_UOTGHS_COMPONENT_ +#define _SAM_UOTGHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB On-The-Go Interface */ +/* ============================================================================= */ +/** \addtogroup SAM_UOTGHS USB On-The-Go Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UotghsDevdma hardware registers */ +typedef struct { + __IO uint32_t UOTGHS_DEVDMANXTDSC; /**< \brief (UotghsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t UOTGHS_DEVDMAADDRESS; /**< \brief (UotghsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t UOTGHS_DEVDMACONTROL; /**< \brief (UotghsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t UOTGHS_DEVDMASTATUS; /**< \brief (UotghsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UotghsDevdma; +/** \brief UotghsHstdma hardware registers */ +typedef struct { + __IO uint32_t UOTGHS_HSTDMANXTDSC; /**< \brief (UotghsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t UOTGHS_HSTDMAADDRESS; /**< \brief (UotghsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t UOTGHS_HSTDMACONTROL; /**< \brief (UotghsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t UOTGHS_HSTDMASTATUS; /**< \brief (UotghsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UotghsHstdma; +/** \brief Uotghs hardware registers */ +#define UOTGHSDEVDMA_NUMBER 7 +#define UOTGHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t UOTGHS_DEVCTRL; /**< \brief (Uotghs Offset: 0x0000) Device General Control Register */ + __I uint32_t UOTGHS_DEVISR; /**< \brief (Uotghs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t UOTGHS_DEVICR; /**< \brief (Uotghs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t UOTGHS_DEVIFR; /**< \brief (Uotghs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t UOTGHS_DEVIMR; /**< \brief (Uotghs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t UOTGHS_DEVIDR; /**< \brief (Uotghs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t UOTGHS_DEVIER; /**< \brief (Uotghs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t UOTGHS_DEVEPT; /**< \brief (Uotghs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t UOTGHS_DEVFNUM; /**< \brief (Uotghs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t UOTGHS_DEVEPTCFG[12]; /**< \brief (Uotghs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t UOTGHS_DEVEPTISR[12]; /**< \brief (Uotghs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTICR[12]; /**< \brief (Uotghs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTIFR[12]; /**< \brief (Uotghs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t UOTGHS_DEVEPTIMR[12]; /**< \brief (Uotghs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTIER[12]; /**< \brief (Uotghs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __O uint32_t UOTGHS_DEVEPTIDR[12]; /**< \brief (Uotghs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved2[48]; + UotghsDevdma UOTGHS_DEVDMA[UOTGHSDEVDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved3[32]; + __IO uint32_t UOTGHS_HSTCTRL; /**< \brief (Uotghs Offset: 0x0400) Host General Control Register */ + __I uint32_t UOTGHS_HSTISR; /**< \brief (Uotghs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t UOTGHS_HSTICR; /**< \brief (Uotghs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t UOTGHS_HSTIFR; /**< \brief (Uotghs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t UOTGHS_HSTIMR; /**< \brief (Uotghs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t UOTGHS_HSTIDR; /**< \brief (Uotghs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t UOTGHS_HSTIER; /**< \brief (Uotghs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t UOTGHS_HSTPIP; /**< \brief (Uotghs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t UOTGHS_HSTFNUM; /**< \brief (Uotghs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t UOTGHS_HSTADDR1; /**< \brief (Uotghs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t UOTGHS_HSTADDR2; /**< \brief (Uotghs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t UOTGHS_HSTADDR3; /**< \brief (Uotghs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved4[52]; + __IO uint32_t UOTGHS_HSTPIPCFG[12]; /**< \brief (Uotghs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t UOTGHS_HSTPIPISR[12]; /**< \brief (Uotghs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPICR[12]; /**< \brief (Uotghs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPIFR[12]; /**< \brief (Uotghs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t UOTGHS_HSTPIPIMR[12]; /**< \brief (Uotghs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPIER[12]; /**< \brief (Uotghs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __O uint32_t UOTGHS_HSTPIPIDR[12]; /**< \brief (Uotghs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __IO uint32_t UOTGHS_HSTPIPINRQ[12]; /**< \brief (Uotghs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __IO uint32_t UOTGHS_HSTPIPERR[12]; /**< \brief (Uotghs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved5[24]; + UotghsHstdma UOTGHS_HSTDMA[UOTGHSHSTDMA_NUMBER]; /**< \brief (Uotghs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved6[32]; + __IO uint32_t UOTGHS_CTRL; /**< \brief (Uotghs Offset: 0x0800) General Control Register */ + __I uint32_t UOTGHS_SR; /**< \brief (Uotghs Offset: 0x0804) General Status Register */ + __O uint32_t UOTGHS_SCR; /**< \brief (Uotghs Offset: 0x0808) General Status Clear Register */ + __O uint32_t UOTGHS_SFR; /**< \brief (Uotghs Offset: 0x080C) General Status Set Register */ + __IO uint32_t UOTGHS_TSTA1; /**< \brief (Uotghs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t UOTGHS_TSTA2; /**< \brief (Uotghs Offset: 0x0814) General Test A2 Register */ + __I uint32_t UOTGHS_VERSION; /**< \brief (Uotghs Offset: 0x0818) General Version Register */ + __I uint32_t UOTGHS_FEATURES; /**< \brief (Uotghs Offset: 0x081C) General Features Register */ + __I uint32_t UOTGHS_ADDRSIZE; /**< \brief (Uotghs Offset: 0x0820) General APB Address Size Register */ + __I uint32_t UOTGHS_IPNAME1; /**< \brief (Uotghs Offset: 0x0824) General Name Register 1 */ + __I uint32_t UOTGHS_IPNAME2; /**< \brief (Uotghs Offset: 0x0828) General Name Register 2 */ + __I uint32_t UOTGHS_FSM; /**< \brief (Uotghs Offset: 0x082C) General Finite State Machine Register */ +} Uotghs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UOTGHS_DEVCTRL : (UOTGHS Offset: 0x0000) Device General Control Register -------- */ +#define UOTGHS_DEVCTRL_UADD_Pos 0 +#define UOTGHS_DEVCTRL_UADD_Msk (0x7fu << UOTGHS_DEVCTRL_UADD_Pos) /**< \brief (UOTGHS_DEVCTRL) USB Address */ +#define UOTGHS_DEVCTRL_UADD(value) ((UOTGHS_DEVCTRL_UADD_Msk & ((value) << UOTGHS_DEVCTRL_UADD_Pos))) +#define UOTGHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (UOTGHS_DEVCTRL) Address Enable */ +#define UOTGHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (UOTGHS_DEVCTRL) Detach */ +#define UOTGHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (UOTGHS_DEVCTRL) Remote Wake-Up */ +#define UOTGHS_DEVCTRL_SPDCONF_Pos 10 +#define UOTGHS_DEVCTRL_SPDCONF_Msk (0x3u << UOTGHS_DEVCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_DEVCTRL) Mode Configuration */ +#define UOTGHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the host is high-speed capable. */ +#define UOTGHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (UOTGHS_DEVCTRL) For a better consumption, if high-speed is not needed. */ +#define UOTGHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (UOTGHS_DEVCTRL) Forced high speed. */ +#define UOTGHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (UOTGHS_DEVCTRL) The peripheral remains in full-speed mode whatever the host speed capability. */ +#define UOTGHS_DEVCTRL_LS (0x1u << 12) /**< \brief (UOTGHS_DEVCTRL) Low-Speed Mode Force */ +#define UOTGHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (UOTGHS_DEVCTRL) Test mode J */ +#define UOTGHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (UOTGHS_DEVCTRL) Test mode K */ +#define UOTGHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (UOTGHS_DEVCTRL) Test packet mode */ +#define UOTGHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (UOTGHS_DEVCTRL) Specific Operational mode */ +/* -------- UOTGHS_DEVISR : (UOTGHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define UOTGHS_DEVISR_SUSP (0x1u << 0) /**< \brief (UOTGHS_DEVISR) Suspend Interrupt */ +#define UOTGHS_DEVISR_MSOF (0x1u << 1) /**< \brief (UOTGHS_DEVISR) Micro Start of Frame Interrupt */ +#define UOTGHS_DEVISR_SOF (0x1u << 2) /**< \brief (UOTGHS_DEVISR) Start of Frame Interrupt */ +#define UOTGHS_DEVISR_EORST (0x1u << 3) /**< \brief (UOTGHS_DEVISR) End of Reset Interrupt */ +#define UOTGHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (UOTGHS_DEVISR) Wake-Up Interrupt */ +#define UOTGHS_DEVISR_EORSM (0x1u << 5) /**< \brief (UOTGHS_DEVISR) End of Resume Interrupt */ +#define UOTGHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (UOTGHS_DEVISR) Upstream Resume Interrupt */ +#define UOTGHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVISR) Endpoint 0 Interrupt */ +#define UOTGHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVISR) Endpoint 1 Interrupt */ +#define UOTGHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVISR) Endpoint 2 Interrupt */ +#define UOTGHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVISR) Endpoint 3 Interrupt */ +#define UOTGHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVISR) Endpoint 4 Interrupt */ +#define UOTGHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVISR) Endpoint 5 Interrupt */ +#define UOTGHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVISR) Endpoint 6 Interrupt */ +#define UOTGHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVISR) Endpoint 7 Interrupt */ +#define UOTGHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVISR) Endpoint 8 Interrupt */ +#define UOTGHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVISR) Endpoint 9 Interrupt */ +#define UOTGHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVISR) Endpoint 10 Interrupt */ +#define UOTGHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVISR) Endpoint 11 Interrupt */ +#define UOTGHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVISR) DMA Channel 1 Interrupt */ +#define UOTGHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVISR) DMA Channel 2 Interrupt */ +#define UOTGHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVISR) DMA Channel 3 Interrupt */ +#define UOTGHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVISR) DMA Channel 4 Interrupt */ +#define UOTGHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVISR) DMA Channel 5 Interrupt */ +#define UOTGHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVISR) DMA Channel 6 Interrupt */ +#define UOTGHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- UOTGHS_DEVICR : (UOTGHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define UOTGHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (UOTGHS_DEVICR) Suspend Interrupt Clear */ +#define UOTGHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (UOTGHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define UOTGHS_DEVICR_SOFC (0x1u << 2) /**< \brief (UOTGHS_DEVICR) Start of Frame Interrupt Clear */ +#define UOTGHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (UOTGHS_DEVICR) End of Reset Interrupt Clear */ +#define UOTGHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (UOTGHS_DEVICR) Wake-Up Interrupt Clear */ +#define UOTGHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (UOTGHS_DEVICR) End of Resume Interrupt Clear */ +#define UOTGHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (UOTGHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- UOTGHS_DEVIFR : (UOTGHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define UOTGHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (UOTGHS_DEVIFR) Suspend Interrupt Set */ +#define UOTGHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (UOTGHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define UOTGHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (UOTGHS_DEVIFR) Start of Frame Interrupt Set */ +#define UOTGHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (UOTGHS_DEVIFR) End of Reset Interrupt Set */ +#define UOTGHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (UOTGHS_DEVIFR) Wake-Up Interrupt Set */ +#define UOTGHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (UOTGHS_DEVIFR) End of Resume Interrupt Set */ +#define UOTGHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (UOTGHS_DEVIFR) Upstream Resume Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define UOTGHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- UOTGHS_DEVIMR : (UOTGHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define UOTGHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (UOTGHS_DEVIMR) Suspend Interrupt Mask */ +#define UOTGHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (UOTGHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define UOTGHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (UOTGHS_DEVIMR) Start of Frame Interrupt Mask */ +#define UOTGHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (UOTGHS_DEVIMR) End of Reset Interrupt Mask */ +#define UOTGHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (UOTGHS_DEVIMR) Wake-Up Interrupt Mask */ +#define UOTGHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (UOTGHS_DEVIMR) End of Resume Interrupt Mask */ +#define UOTGHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (UOTGHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define UOTGHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define UOTGHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- UOTGHS_DEVIDR : (UOTGHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define UOTGHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (UOTGHS_DEVIDR) Suspend Interrupt Disable */ +#define UOTGHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (UOTGHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define UOTGHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (UOTGHS_DEVIDR) Start of Frame Interrupt Disable */ +#define UOTGHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (UOTGHS_DEVIDR) End of Reset Interrupt Disable */ +#define UOTGHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (UOTGHS_DEVIDR) Wake-Up Interrupt Disable */ +#define UOTGHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (UOTGHS_DEVIDR) End of Resume Interrupt Disable */ +#define UOTGHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (UOTGHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define UOTGHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define UOTGHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- UOTGHS_DEVIER : (UOTGHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define UOTGHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (UOTGHS_DEVIER) Suspend Interrupt Enable */ +#define UOTGHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (UOTGHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define UOTGHS_DEVIER_SOFES (0x1u << 2) /**< \brief (UOTGHS_DEVIER) Start of Frame Interrupt Enable */ +#define UOTGHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (UOTGHS_DEVIER) End of Reset Interrupt Enable */ +#define UOTGHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (UOTGHS_DEVIER) Wake-Up Interrupt Enable */ +#define UOTGHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (UOTGHS_DEVIER) End of Resume Interrupt Enable */ +#define UOTGHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (UOTGHS_DEVIER) Upstream Resume Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (UOTGHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (UOTGHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (UOTGHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (UOTGHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (UOTGHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (UOTGHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (UOTGHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (UOTGHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (UOTGHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (UOTGHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (UOTGHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define UOTGHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (UOTGHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define UOTGHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- UOTGHS_DEVEPT : (UOTGHS Offset: 0x001C) Device Endpoint Register -------- */ +#define UOTGHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Enable */ +#define UOTGHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Enable */ +#define UOTGHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Enable */ +#define UOTGHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Enable */ +#define UOTGHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Enable */ +#define UOTGHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Enable */ +#define UOTGHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Enable */ +#define UOTGHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Enable */ +#define UOTGHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Enable */ +#define UOTGHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (UOTGHS_DEVEPT) Endpoint 0 Reset */ +#define UOTGHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (UOTGHS_DEVEPT) Endpoint 1 Reset */ +#define UOTGHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (UOTGHS_DEVEPT) Endpoint 2 Reset */ +#define UOTGHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (UOTGHS_DEVEPT) Endpoint 3 Reset */ +#define UOTGHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (UOTGHS_DEVEPT) Endpoint 4 Reset */ +#define UOTGHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (UOTGHS_DEVEPT) Endpoint 5 Reset */ +#define UOTGHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (UOTGHS_DEVEPT) Endpoint 6 Reset */ +#define UOTGHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (UOTGHS_DEVEPT) Endpoint 7 Reset */ +#define UOTGHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (UOTGHS_DEVEPT) Endpoint 8 Reset */ +/* -------- UOTGHS_DEVFNUM : (UOTGHS Offset: 0x0020) Device Frame Number Register -------- */ +#define UOTGHS_DEVFNUM_MFNUM_Pos 0 +#define UOTGHS_DEVFNUM_MFNUM_Msk (0x7u << UOTGHS_DEVFNUM_MFNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Micro Frame Number */ +#define UOTGHS_DEVFNUM_FNUM_Pos 3 +#define UOTGHS_DEVFNUM_FNUM_Msk (0x7ffu << UOTGHS_DEVFNUM_FNUM_Pos) /**< \brief (UOTGHS_DEVFNUM) Frame Number */ +#define UOTGHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (UOTGHS_DEVFNUM) Frame Number CRC Error */ +/* -------- UOTGHS_DEVEPTCFG[12] : (UOTGHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define UOTGHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Memory Allocate */ +#define UOTGHS_DEVEPTCFG_EPBK_Pos 2 +#define UOTGHS_DEVEPTCFG_EPBK_Msk (0x3u << UOTGHS_DEVEPTCFG_EPBK_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Banks */ +#define UOTGHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Single-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Double-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_DEVEPTCFG[12]) Triple-bank endpoint */ +#define UOTGHS_DEVEPTCFG_EPSIZE_Pos 4 +#define UOTGHS_DEVEPTCFG_EPSIZE_Msk (0x7u << UOTGHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Size */ +#define UOTGHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 8 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 16 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 32 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 64 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 128 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 256 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 512 bytes */ +#define UOTGHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_DEVEPTCFG[12]) 1024 bytes */ +#define UOTGHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Direction */ +#define UOTGHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is OUT. */ +#define UOTGHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (UOTGHS_DEVEPTCFG[12]) The endpoint direction is IN (nor for control endpoints). */ +#define UOTGHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (UOTGHS_DEVEPTCFG[12]) Automatic Switch */ +#define UOTGHS_DEVEPTCFG_EPTYPE_Pos 11 +#define UOTGHS_DEVEPTCFG_EPTYPE_Msk (0x3u << UOTGHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Endpoint Type */ +#define UOTGHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Control */ +#define UOTGHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Isochronous */ +#define UOTGHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Bulk */ +#define UOTGHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (UOTGHS_DEVEPTCFG[12]) Interrupt */ +#define UOTGHS_DEVEPTCFG_NBTRANS_Pos 13 +#define UOTGHS_DEVEPTCFG_NBTRANS_Msk (0x3u << UOTGHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (UOTGHS_DEVEPTCFG[12]) Number of transaction per microframe for isochronous endpoint */ +#define UOTGHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) default value: one transaction per micro-frame. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 2 transactions per micro-frame. This endpoint should be configured as double-bank. */ +#define UOTGHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (UOTGHS_DEVEPTCFG[12]) 3 transactions per micro-frame. This endpoint should be configured as triple-bank. */ +/* -------- UOTGHS_DEVEPTISR[12] : (UOTGHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define UOTGHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (UOTGHS_DEVEPTISR[12]) Transmitted IN Data Interrupt */ +#define UOTGHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (UOTGHS_DEVEPTISR[12]) Received OUT Data Interrupt */ +#define UOTGHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Received SETUP Interrupt */ +#define UOTGHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed OUT Interrupt */ +#define UOTGHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) NAKed IN Interrupt */ +#define UOTGHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_DEVEPTISR[12]) Overflow Interrupt */ +#define UOTGHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) STALLed Interrupt */ +#define UOTGHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (UOTGHS_DEVEPTISR[12]) Short Packet Interrupt */ +#define UOTGHS_DEVEPTISR_DTSEQ_Pos 8 +#define UOTGHS_DEVEPTISR_DTSEQ_Msk (0x3u << UOTGHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Data Toggle Sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data0 toggle sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Data1 toggle sequence */ +#define UOTGHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */ +#define UOTGHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (UOTGHS_DEVEPTISR[12]) Reserved for high-bandwidth isochronous endpoint */ +#define UOTGHS_DEVEPTISR_NBUSYBK_Pos 12 +#define UOTGHS_DEVEPTISR_NBUSYBK_Msk (0x3u << UOTGHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Number of Busy Banks */ +#define UOTGHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 0 busy bank (all banks free) */ +#define UOTGHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 1 busy bank */ +#define UOTGHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 2 busy banks */ +#define UOTGHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_DEVEPTISR[12]) 3 busy banks */ +#define UOTGHS_DEVEPTISR_CURRBK_Pos 14 +#define UOTGHS_DEVEPTISR_CURRBK_Msk (0x3u << UOTGHS_DEVEPTISR_CURRBK_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Current Bank */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank0 */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank1 */ +#define UOTGHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_DEVEPTISR[12]) Current bank is bank2 */ +#define UOTGHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_DEVEPTISR[12]) Read-write Allowed */ +#define UOTGHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (UOTGHS_DEVEPTISR[12]) Control Direction */ +#define UOTGHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_DEVEPTISR[12]) Configuration OK Status */ +#define UOTGHS_DEVEPTISR_BYCT_Pos 20 +#define UOTGHS_DEVEPTISR_BYCT_Msk (0x7ffu << UOTGHS_DEVEPTISR_BYCT_Pos) /**< \brief (UOTGHS_DEVEPTISR[12]) Byte Count */ +#define UOTGHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_DEVEPTISR[12]) Underflow Interrupt */ +#define UOTGHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define UOTGHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (UOTGHS_DEVEPTISR[12]) High Bandwidth Isochronous IN Flush Interrupt */ +#define UOTGHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_DEVEPTISR[12]) CRC Error Interrupt */ +#define UOTGHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (UOTGHS_DEVEPTISR[12]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- UOTGHS_DEVEPTICR[12] : (UOTGHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define UOTGHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTICR[12]) Transmitted IN Data Interrupt Clear */ +#define UOTGHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTICR[12]) Received OUT Data Interrupt Clear */ +#define UOTGHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Received SETUP Interrupt Clear */ +#define UOTGHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed OUT Interrupt Clear */ +#define UOTGHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) NAKed IN Interrupt Clear */ +#define UOTGHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTICR[12]) Overflow Interrupt Clear */ +#define UOTGHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) STALLed Interrupt Clear */ +#define UOTGHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTICR[12]) Short Packet Interrupt Clear */ +#define UOTGHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTICR[12]) Underflow Interrupt Clear */ +#define UOTGHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTICR[12]) High bandwidth isochronous IN Underflow Error Interrupt Clear */ +#define UOTGHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTICR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define UOTGHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTICR[12]) CRC Error Interrupt Clear */ +/* -------- UOTGHS_DEVEPTIFR[12] : (UOTGHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIFR[12]) Transmitted IN Data Interrupt Set */ +#define UOTGHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received OUT Data Interrupt Set */ +#define UOTGHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Received SETUP Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed OUT Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) NAKed IN Interrupt Set */ +#define UOTGHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIFR[12]) Overflow Interrupt Set */ +#define UOTGHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) STALLed Interrupt Set */ +#define UOTGHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIFR[12]) Short Packet Interrupt Set */ +#define UOTGHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIFR[12]) Number of Busy Banks Interrupt Set */ +#define UOTGHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIFR[12]) Underflow Interrupt Set */ +#define UOTGHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIFR[12]) High bandwidth isochronous IN Underflow Error Interrupt Set */ +#define UOTGHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIFR[12]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define UOTGHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIFR[12]) CRC Error Interrupt Set */ +/* -------- UOTGHS_DEVEPTIMR[12] : (UOTGHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transmitted IN Data Interrupt */ +#define UOTGHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received OUT Data Interrupt */ +#define UOTGHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Received SETUP Interrupt */ +#define UOTGHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed OUT Interrupt */ +#define UOTGHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) NAKed IN Interrupt */ +#define UOTGHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIMR[12]) Overflow Interrupt */ +#define UOTGHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALLed Interrupt */ +#define UOTGHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIMR[12]) Short Packet Interrupt */ +#define UOTGHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIMR[12]) Number of Busy Banks Interrupt */ +#define UOTGHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIMR[12]) Kill IN Bank */ +#define UOTGHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIMR[12]) FIFO Control */ +#define UOTGHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIMR[12]) Endpoint Interrupts Disable HDMA Request */ +#define UOTGHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIMR[12]) NYET Token Disable */ +#define UOTGHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIMR[12]) Reset Data Toggle */ +#define UOTGHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIMR[12]) STALL Request */ +#define UOTGHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIMR[12]) Underflow Interrupt */ +#define UOTGHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Error Interrupt */ +#define UOTGHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIMR[12]) High Bandwidth Isochronous IN Flush Interrupt */ +#define UOTGHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIMR[12]) CRC Error Interrupt */ +#define UOTGHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIMR[12]) MData Interrupt */ +#define UOTGHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIMR[12]) DataX Interrupt */ +#define UOTGHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIMR[12]) Transaction Error Interrupt */ +/* -------- UOTGHS_DEVEPTIER[12] : (UOTGHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIER[12]) Transmitted IN Data Interrupt Enable */ +#define UOTGHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIER[12]) Received OUT Data Interrupt Enable */ +#define UOTGHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Received SETUP Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed OUT Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) NAKed IN Interrupt Enable */ +#define UOTGHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIER[12]) Overflow Interrupt Enable */ +#define UOTGHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) STALLed Interrupt Enable */ +#define UOTGHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIER[12]) Short Packet Interrupt Enable */ +#define UOTGHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIER[12]) Number of Busy Banks Interrupt Enable */ +#define UOTGHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (UOTGHS_DEVEPTIER[12]) Kill IN Bank */ +#define UOTGHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIER[12]) FIFO Control */ +#define UOTGHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIER[12]) Endpoint Interrupts Disable HDMA Request Enable */ +#define UOTGHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIER[12]) NYET Token Disable Enable */ +#define UOTGHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_DEVEPTIER[12]) Reset Data Toggle Enable */ +#define UOTGHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIER[12]) STALL Request Enable */ +#define UOTGHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIER[12]) Underflow Interrupt Enable */ +#define UOTGHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIER[12]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define UOTGHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIER[12]) CRC Error Interrupt Enable */ +#define UOTGHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIER[12]) MData Interrupt Enable */ +#define UOTGHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIER[12]) DataX Interrupt Enable */ +#define UOTGHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIER[12]) Transaction Error Interrupt Enable */ +/* -------- UOTGHS_DEVEPTIDR[12] : (UOTGHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define UOTGHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transmitted IN Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received OUT Data Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Received SETUP Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed OUT Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) NAKed IN Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (UOTGHS_DEVEPTIDR[12]) Overflow Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALLed Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (UOTGHS_DEVEPTIDR[12]) Shortpacket Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_DEVEPTIDR[12]) Number of Busy Banks Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_DEVEPTIDR[12]) FIFO Control Clear */ +#define UOTGHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_DEVEPTIDR[12]) Endpoint Interrupts Disable HDMA Request Clear */ +#define UOTGHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (UOTGHS_DEVEPTIDR[12]) NYET Token Disable Clear */ +#define UOTGHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (UOTGHS_DEVEPTIDR[12]) STALL Request Clear */ +#define UOTGHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (UOTGHS_DEVEPTIDR[12]) Underflow Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (UOTGHS_DEVEPTIDR[12]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_DEVEPTIDR[12]) CRC Error Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (UOTGHS_DEVEPTIDR[12]) MData Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (UOTGHS_DEVEPTIDR[12]) DataX Interrupt Clear */ +#define UOTGHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (UOTGHS_DEVEPTIDR[12]) Transaction Error Interrupt Clear */ +/* -------- UOTGHS_DEVDMANXTDSC : (UOTGHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_DEVDMANXTDSC) Next Descriptor Address */ +#define UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UOTGHS_DEVDMAADDRESS : (UOTGHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_DEVDMAADDRESS) Buffer Address */ +#define UOTGHS_DEVDMAADDRESS_BUFF_ADD(value) ((UOTGHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- UOTGHS_DEVDMACONTROL : (UOTGHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define UOTGHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMACONTROL) Channel Enable Command */ +#define UOTGHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define UOTGHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Enable Control */ +#define UOTGHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define UOTGHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UOTGHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_DEVDMACONTROL) Burst Lock Enable */ +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define UOTGHS_DEVDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UOTGHS_DEVDMASTATUS : (UOTGHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define UOTGHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Enable Status */ +#define UOTGHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_DEVDMASTATUS) Channel Active Status */ +#define UOTGHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define UOTGHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define UOTGHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_DEVDMASTATUS) Buffer Byte Count */ +#define UOTGHS_DEVDMASTATUS_BUFF_COUNT(value) ((UOTGHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- UOTGHS_HSTCTRL : (UOTGHS Offset: 0x0400) Host General Control Register -------- */ +#define UOTGHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (UOTGHS_HSTCTRL) Start of Frame Generation Enable */ +#define UOTGHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (UOTGHS_HSTCTRL) Send USB Reset */ +#define UOTGHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (UOTGHS_HSTCTRL) Send USB Resume */ +#define UOTGHS_HSTCTRL_SPDCONF_Pos 12 +#define UOTGHS_HSTCTRL_SPDCONF_Msk (0x3u << UOTGHS_HSTCTRL_SPDCONF_Pos) /**< \brief (UOTGHS_HSTCTRL) Mode Configuration */ +#define UOTGHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (UOTGHS_HSTCTRL) The host starts in full-speed mode and performs a high-speed reset to switch to the high-speed mode if the downstream peripheral is high-speed capable. */ +#define UOTGHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (UOTGHS_HSTCTRL) For a better consumption, if high-speed is not needed. */ +#define UOTGHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (UOTGHS_HSTCTRL) Forced high speed. */ +#define UOTGHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (UOTGHS_HSTCTRL) The host remains to full-speed mode whatever the peripheral speed capability. */ +/* -------- UOTGHS_HSTISR : (UOTGHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define UOTGHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (UOTGHS_HSTISR) Device Connection Interrupt */ +#define UOTGHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (UOTGHS_HSTISR) Device Disconnection Interrupt */ +#define UOTGHS_HSTISR_RSTI (0x1u << 2) /**< \brief (UOTGHS_HSTISR) USB Reset Sent Interrupt */ +#define UOTGHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (UOTGHS_HSTISR) Downstream Resume Sent Interrupt */ +#define UOTGHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (UOTGHS_HSTISR) Upstream Resume Received Interrupt */ +#define UOTGHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (UOTGHS_HSTISR) Host Start of Frame Interrupt */ +#define UOTGHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (UOTGHS_HSTISR) Host Wake-Up Interrupt */ +#define UOTGHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTISR) Pipe 0 Interrupt */ +#define UOTGHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTISR) Pipe 1 Interrupt */ +#define UOTGHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTISR) Pipe 2 Interrupt */ +#define UOTGHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTISR) Pipe 3 Interrupt */ +#define UOTGHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTISR) Pipe 4 Interrupt */ +#define UOTGHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTISR) Pipe 5 Interrupt */ +#define UOTGHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTISR) Pipe 6 Interrupt */ +#define UOTGHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTISR) Pipe 7 Interrupt */ +#define UOTGHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTISR) Pipe 8 Interrupt */ +#define UOTGHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTISR) Pipe 9 Interrupt */ +#define UOTGHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTISR) Pipe 10 Interrupt */ +#define UOTGHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTISR) Pipe 11 Interrupt */ +#define UOTGHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTISR) DMA Channel 1 Interrupt */ +#define UOTGHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTISR) DMA Channel 2 Interrupt */ +#define UOTGHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTISR) DMA Channel 3 Interrupt */ +#define UOTGHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTISR) DMA Channel 4 Interrupt */ +#define UOTGHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTISR) DMA Channel 5 Interrupt */ +#define UOTGHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTISR) DMA Channel 6 Interrupt */ +#define UOTGHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- UOTGHS_HSTICR : (UOTGHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define UOTGHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (UOTGHS_HSTICR) Device Connection Interrupt Clear */ +#define UOTGHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (UOTGHS_HSTICR) Device Disconnection Interrupt Clear */ +#define UOTGHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (UOTGHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define UOTGHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (UOTGHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define UOTGHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (UOTGHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define UOTGHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (UOTGHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define UOTGHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (UOTGHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- UOTGHS_HSTIFR : (UOTGHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define UOTGHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (UOTGHS_HSTIFR) Device Connection Interrupt Set */ +#define UOTGHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (UOTGHS_HSTIFR) Device Disconnection Interrupt Set */ +#define UOTGHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (UOTGHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define UOTGHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (UOTGHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define UOTGHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (UOTGHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define UOTGHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (UOTGHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define UOTGHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (UOTGHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define UOTGHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- UOTGHS_HSTIMR : (UOTGHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define UOTGHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (UOTGHS_HSTIMR) Device Connection Interrupt Enable */ +#define UOTGHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (UOTGHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define UOTGHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (UOTGHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define UOTGHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (UOTGHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define UOTGHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (UOTGHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define UOTGHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (UOTGHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define UOTGHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (UOTGHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define UOTGHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define UOTGHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- UOTGHS_HSTIDR : (UOTGHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define UOTGHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (UOTGHS_HSTIDR) Device Connection Interrupt Disable */ +#define UOTGHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (UOTGHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define UOTGHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (UOTGHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define UOTGHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (UOTGHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define UOTGHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (UOTGHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define UOTGHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define UOTGHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (UOTGHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define UOTGHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define UOTGHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- UOTGHS_HSTIER : (UOTGHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define UOTGHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (UOTGHS_HSTIER) Device Connection Interrupt Enable */ +#define UOTGHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (UOTGHS_HSTIER) Device Disconnection Interrupt Enable */ +#define UOTGHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (UOTGHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define UOTGHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (UOTGHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define UOTGHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (UOTGHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define UOTGHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (UOTGHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define UOTGHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (UOTGHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (UOTGHS_HSTIER) Pipe 0 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (UOTGHS_HSTIER) Pipe 1 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (UOTGHS_HSTIER) Pipe 2 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (UOTGHS_HSTIER) Pipe 3 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (UOTGHS_HSTIER) Pipe 4 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (UOTGHS_HSTIER) Pipe 5 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (UOTGHS_HSTIER) Pipe 6 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (UOTGHS_HSTIER) Pipe 7 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (UOTGHS_HSTIER) Pipe 8 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (UOTGHS_HSTIER) Pipe 9 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (UOTGHS_HSTIER) Pipe 10 Interrupt Enable */ +#define UOTGHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (UOTGHS_HSTIER) Pipe 11 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (UOTGHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (UOTGHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (UOTGHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (UOTGHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (UOTGHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (UOTGHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define UOTGHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (UOTGHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- UOTGHS_HSTPIP : (UOTGHS Offset: 0x0041C) Host Pipe Register -------- */ +#define UOTGHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Enable */ +#define UOTGHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Enable */ +#define UOTGHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Enable */ +#define UOTGHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Enable */ +#define UOTGHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Enable */ +#define UOTGHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Enable */ +#define UOTGHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Enable */ +#define UOTGHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Enable */ +#define UOTGHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Enable */ +#define UOTGHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (UOTGHS_HSTPIP) Pipe 0 Reset */ +#define UOTGHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (UOTGHS_HSTPIP) Pipe 1 Reset */ +#define UOTGHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (UOTGHS_HSTPIP) Pipe 2 Reset */ +#define UOTGHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (UOTGHS_HSTPIP) Pipe 3 Reset */ +#define UOTGHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (UOTGHS_HSTPIP) Pipe 4 Reset */ +#define UOTGHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (UOTGHS_HSTPIP) Pipe 5 Reset */ +#define UOTGHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (UOTGHS_HSTPIP) Pipe 6 Reset */ +#define UOTGHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (UOTGHS_HSTPIP) Pipe 7 Reset */ +#define UOTGHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (UOTGHS_HSTPIP) Pipe 8 Reset */ +/* -------- UOTGHS_HSTFNUM : (UOTGHS Offset: 0x0420) Host Frame Number Register -------- */ +#define UOTGHS_HSTFNUM_MFNUM_Pos 0 +#define UOTGHS_HSTFNUM_MFNUM_Msk (0x7u << UOTGHS_HSTFNUM_MFNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Micro Frame Number */ +#define UOTGHS_HSTFNUM_MFNUM(value) ((UOTGHS_HSTFNUM_MFNUM_Msk & ((value) << UOTGHS_HSTFNUM_MFNUM_Pos))) +#define UOTGHS_HSTFNUM_FNUM_Pos 3 +#define UOTGHS_HSTFNUM_FNUM_Msk (0x7ffu << UOTGHS_HSTFNUM_FNUM_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Number */ +#define UOTGHS_HSTFNUM_FNUM(value) ((UOTGHS_HSTFNUM_FNUM_Msk & ((value) << UOTGHS_HSTFNUM_FNUM_Pos))) +#define UOTGHS_HSTFNUM_FLENHIGH_Pos 16 +#define UOTGHS_HSTFNUM_FLENHIGH_Msk (0xffu << UOTGHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (UOTGHS_HSTFNUM) Frame Length */ +#define UOTGHS_HSTFNUM_FLENHIGH(value) ((UOTGHS_HSTFNUM_FLENHIGH_Msk & ((value) << UOTGHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- UOTGHS_HSTADDR1 : (UOTGHS Offset: 0x0424) Host Address 1 Register -------- */ +#define UOTGHS_HSTADDR1_HSTADDRP0_Pos 0 +#define UOTGHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP0(value) ((UOTGHS_HSTADDR1_HSTADDRP0_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP0_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP1_Pos 8 +#define UOTGHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP1(value) ((UOTGHS_HSTADDR1_HSTADDRP1_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP1_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP2_Pos 16 +#define UOTGHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP2(value) ((UOTGHS_HSTADDR1_HSTADDRP2_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP2_Pos))) +#define UOTGHS_HSTADDR1_HSTADDRP3_Pos 24 +#define UOTGHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << UOTGHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (UOTGHS_HSTADDR1) USB Host Address */ +#define UOTGHS_HSTADDR1_HSTADDRP3(value) ((UOTGHS_HSTADDR1_HSTADDRP3_Msk & ((value) << UOTGHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- UOTGHS_HSTADDR2 : (UOTGHS Offset: 0x0428) Host Address 2 Register -------- */ +#define UOTGHS_HSTADDR2_HSTADDRP4_Pos 0 +#define UOTGHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP4(value) ((UOTGHS_HSTADDR2_HSTADDRP4_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP4_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP5_Pos 8 +#define UOTGHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP5(value) ((UOTGHS_HSTADDR2_HSTADDRP5_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP5_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP6_Pos 16 +#define UOTGHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP6(value) ((UOTGHS_HSTADDR2_HSTADDRP6_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP6_Pos))) +#define UOTGHS_HSTADDR2_HSTADDRP7_Pos 24 +#define UOTGHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << UOTGHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (UOTGHS_HSTADDR2) USB Host Address */ +#define UOTGHS_HSTADDR2_HSTADDRP7(value) ((UOTGHS_HSTADDR2_HSTADDRP7_Msk & ((value) << UOTGHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- UOTGHS_HSTADDR3 : (UOTGHS Offset: 0x042C) Host Address 3 Register -------- */ +#define UOTGHS_HSTADDR3_HSTADDRP8_Pos 0 +#define UOTGHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ +#define UOTGHS_HSTADDR3_HSTADDRP8(value) ((UOTGHS_HSTADDR3_HSTADDRP8_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP8_Pos))) +#define UOTGHS_HSTADDR3_HSTADDRP9_Pos 8 +#define UOTGHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << UOTGHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (UOTGHS_HSTADDR3) USB Host Address */ +#define UOTGHS_HSTADDR3_HSTADDRP9(value) ((UOTGHS_HSTADDR3_HSTADDRP9_Msk & ((value) << UOTGHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- UOTGHS_HSTPIPCFG[12] : (UOTGHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define UOTGHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Memory Allocate */ +#define UOTGHS_HSTPIPCFG_PBK_Pos 2 +#define UOTGHS_HSTPIPCFG_PBK_Msk (0x3u << UOTGHS_HSTPIPCFG_PBK_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Banks */ +#define UOTGHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Single-bank pipe */ +#define UOTGHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Double-bank pipe */ +#define UOTGHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (UOTGHS_HSTPIPCFG[12]) Triple-bank pipe */ +#define UOTGHS_HSTPIPCFG_PSIZE_Pos 4 +#define UOTGHS_HSTPIPCFG_PSIZE_Msk (0x7u << UOTGHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Size */ +#define UOTGHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 8 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 16 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 32 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 64 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 128 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 256 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 512 bytes */ +#define UOTGHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (UOTGHS_HSTPIPCFG[12]) 1024 bytes */ +#define UOTGHS_HSTPIPCFG_PTOKEN_Pos 8 +#define UOTGHS_HSTPIPCFG_PTOKEN_Msk (0x3u << UOTGHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Token */ +#define UOTGHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) SETUP */ +#define UOTGHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) IN */ +#define UOTGHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (UOTGHS_HSTPIPCFG[12]) OUT */ +#define UOTGHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (UOTGHS_HSTPIPCFG[12]) Automatic Switch */ +#define UOTGHS_HSTPIPCFG_PTYPE_Pos 12 +#define UOTGHS_HSTPIPCFG_PTYPE_Msk (0x3u << UOTGHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Type */ +#define UOTGHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Control */ +#define UOTGHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Isochronous */ +#define UOTGHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Bulk */ +#define UOTGHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (UOTGHS_HSTPIPCFG[12]) Interrupt */ +#define UOTGHS_HSTPIPCFG_PEPNUM_Pos 16 +#define UOTGHS_HSTPIPCFG_PEPNUM_Msk (0xfu << UOTGHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Endpoint Number */ +#define UOTGHS_HSTPIPCFG_PEPNUM(value) ((UOTGHS_HSTPIPCFG_PEPNUM_Msk & ((value) << UOTGHS_HSTPIPCFG_PEPNUM_Pos))) +#define UOTGHS_HSTPIPCFG_INTFRQ_Pos 24 +#define UOTGHS_HSTPIPCFG_INTFRQ_Msk (0xffu << UOTGHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Pipe Interrupt Request Frequency */ +#define UOTGHS_HSTPIPCFG_INTFRQ(value) ((UOTGHS_HSTPIPCFG_INTFRQ_Msk & ((value) << UOTGHS_HSTPIPCFG_INTFRQ_Pos))) +#define UOTGHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (UOTGHS_HSTPIPCFG[12]) Ping Enable */ +#define UOTGHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define UOTGHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << UOTGHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (UOTGHS_HSTPIPCFG[12]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define UOTGHS_HSTPIPCFG_BINTERVAL(value) ((UOTGHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << UOTGHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- UOTGHS_HSTPIPISR[12] : (UOTGHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define UOTGHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (UOTGHS_HSTPIPISR[12]) Received IN Data Interrupt */ +#define UOTGHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted OUT Data Interrupt */ +#define UOTGHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Transmitted SETUP Interrupt */ +#define UOTGHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Error Interrupt */ +#define UOTGHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (UOTGHS_HSTPIPISR[12]) NAKed Interrupt */ +#define UOTGHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (UOTGHS_HSTPIPISR[12]) Overflow Interrupt */ +#define UOTGHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) Received STALLed Interrupt */ +#define UOTGHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (UOTGHS_HSTPIPISR[12]) Short Packet Interrupt */ +#define UOTGHS_HSTPIPISR_DTSEQ_Pos 8 +#define UOTGHS_HSTPIPISR_DTSEQ_Msk (0x3u << UOTGHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Data Toggle Sequence */ +#define UOTGHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data0 toggle sequence */ +#define UOTGHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (UOTGHS_HSTPIPISR[12]) Data1 toggle sequence */ +#define UOTGHS_HSTPIPISR_NBUSYBK_Pos 12 +#define UOTGHS_HSTPIPISR_NBUSYBK_Msk (0x3u << UOTGHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Number of Busy Banks */ +#define UOTGHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 0 busy bank (all banks free) */ +#define UOTGHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 1 busy bank */ +#define UOTGHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 2 busy banks */ +#define UOTGHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (UOTGHS_HSTPIPISR[12]) 3 busy banks */ +#define UOTGHS_HSTPIPISR_CURRBK_Pos 14 +#define UOTGHS_HSTPIPISR_CURRBK_Msk (0x3u << UOTGHS_HSTPIPISR_CURRBK_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Current Bank */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank0 */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank1 */ +#define UOTGHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (UOTGHS_HSTPIPISR[12]) Current bank is bank2 */ +#define UOTGHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (UOTGHS_HSTPIPISR[12]) Read-write Allowed */ +#define UOTGHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (UOTGHS_HSTPIPISR[12]) Configuration OK Status */ +#define UOTGHS_HSTPIPISR_PBYCT_Pos 20 +#define UOTGHS_HSTPIPISR_PBYCT_Msk (0x7ffu << UOTGHS_HSTPIPISR_PBYCT_Pos) /**< \brief (UOTGHS_HSTPIPISR[12]) Pipe Byte Count */ +#define UOTGHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (UOTGHS_HSTPIPISR[12]) Underflow Interrupt */ +#define UOTGHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (UOTGHS_HSTPIPISR[12]) CRC Error Interrupt */ +/* -------- UOTGHS_HSTPIPICR[12] : (UOTGHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define UOTGHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPICR[12]) Received IN Data Interrupt Clear */ +#define UOTGHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted OUT Data Interrupt Clear */ +#define UOTGHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Transmitted SETUP Interrupt Clear */ +#define UOTGHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPICR[12]) NAKed Interrupt Clear */ +#define UOTGHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPICR[12]) Overflow Interrupt Clear */ +#define UOTGHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) Received STALLed Interrupt Clear */ +#define UOTGHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPICR[12]) Short Packet Interrupt Clear */ +#define UOTGHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPICR[12]) Underflow Interrupt Clear */ +#define UOTGHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPICR[12]) CRC Error Interrupt Clear */ +/* -------- UOTGHS_HSTPIPIFR[12] : (UOTGHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received IN Data Interrupt Set */ +#define UOTGHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted OUT Data Interrupt Set */ +#define UOTGHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Transmitted SETUP Interrupt Set */ +#define UOTGHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIFR[12]) Pipe Error Interrupt Set */ +#define UOTGHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIFR[12]) NAKed Interrupt Set */ +#define UOTGHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIFR[12]) Overflow Interrupt Set */ +#define UOTGHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) Received STALLed Interrupt Set */ +#define UOTGHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIFR[12]) Short Packet Interrupt Set */ +#define UOTGHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIFR[12]) Number of Busy Banks Set */ +#define UOTGHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIFR[12]) Underflow Interrupt Set */ +#define UOTGHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIFR[12]) CRC Error Interrupt Set */ +/* -------- UOTGHS_HSTPIPIMR[12] : (UOTGHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received IN Data Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted OUT Data Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Transmitted SETUP Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Error Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIMR[12]) NAKed Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIMR[12]) Overflow Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) Received STALLed Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIMR[12]) Short Packet Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIMR[12]) Number of Busy Banks Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIMR[12]) FIFO Control */ +#define UOTGHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Interrupts Disable HDMA Request Enable */ +#define UOTGHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIMR[12]) Pipe Freeze */ +#define UOTGHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIMR[12]) Reset Data Toggle */ +#define UOTGHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIMR[12]) Underflow Interrupt Enable */ +#define UOTGHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIMR[12]) CRC Error Interrupt Enable */ +/* -------- UOTGHS_HSTPIPIER[12] : (UOTGHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIER[12]) Received IN Data Interrupt Enable */ +#define UOTGHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted OUT Data Interrupt Enable */ +#define UOTGHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Transmitted SETUP Interrupt Enable */ +#define UOTGHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Error Interrupt Enable */ +#define UOTGHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIER[12]) NAKed Interrupt Enable */ +#define UOTGHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIER[12]) Overflow Interrupt Enable */ +#define UOTGHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) Received STALLed Interrupt Enable */ +#define UOTGHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIER[12]) Short Packet Interrupt Enable */ +#define UOTGHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIER[12]) Number of Busy Banks Enable */ +#define UOTGHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Interrupts Disable HDMA Request Enable */ +#define UOTGHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIER[12]) Pipe Freeze Enable */ +#define UOTGHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (UOTGHS_HSTPIPIER[12]) Reset Data Toggle Enable */ +#define UOTGHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIER[12]) Underflow Interrupt Enable */ +#define UOTGHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIER[12]) CRC Error Interrupt Enable */ +/* -------- UOTGHS_HSTPIPIDR[12] : (UOTGHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define UOTGHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received IN Data Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted OUT Data Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Transmitted SETUP Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Error Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (UOTGHS_HSTPIPIDR[12]) NAKed Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (UOTGHS_HSTPIPIDR[12]) Overflow Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) Received STALLed Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (UOTGHS_HSTPIPIDR[12]) Short Packet Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (UOTGHS_HSTPIPIDR[12]) Number of Busy Banks Disable */ +#define UOTGHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (UOTGHS_HSTPIPIDR[12]) FIFO Control Disable */ +#define UOTGHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Interrupts Disable HDMA Request Disable */ +#define UOTGHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (UOTGHS_HSTPIPIDR[12]) Pipe Freeze Disable */ +#define UOTGHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (UOTGHS_HSTPIPIDR[12]) Underflow Interrupt Disable */ +#define UOTGHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (UOTGHS_HSTPIPIDR[12]) CRC Error Interrupt Disable */ +/* -------- UOTGHS_HSTPIPINRQ[12] : (UOTGHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define UOTGHS_HSTPIPINRQ_INRQ_Pos 0 +#define UOTGHS_HSTPIPINRQ_INRQ_Msk (0xffu << UOTGHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Number before Freeze */ +#define UOTGHS_HSTPIPINRQ_INRQ(value) ((UOTGHS_HSTPIPINRQ_INRQ_Msk & ((value) << UOTGHS_HSTPIPINRQ_INRQ_Pos))) +#define UOTGHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (UOTGHS_HSTPIPINRQ[12]) IN Request Mode */ +/* -------- UOTGHS_HSTPIPERR[12] : (UOTGHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define UOTGHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (UOTGHS_HSTPIPERR[12]) Data Toggle Error */ +#define UOTGHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (UOTGHS_HSTPIPERR[12]) Data PID Error */ +#define UOTGHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (UOTGHS_HSTPIPERR[12]) PID Error */ +#define UOTGHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (UOTGHS_HSTPIPERR[12]) Time-Out Error */ +#define UOTGHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (UOTGHS_HSTPIPERR[12]) CRC16 Error */ +#define UOTGHS_HSTPIPERR_COUNTER_Pos 5 +#define UOTGHS_HSTPIPERR_COUNTER_Msk (0x3u << UOTGHS_HSTPIPERR_COUNTER_Pos) /**< \brief (UOTGHS_HSTPIPERR[12]) Error Counter */ +#define UOTGHS_HSTPIPERR_COUNTER(value) ((UOTGHS_HSTPIPERR_COUNTER_Msk & ((value) << UOTGHS_HSTPIPERR_COUNTER_Pos))) +/* -------- UOTGHS_HSTDMANXTDSC : (UOTGHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (UOTGHS_HSTDMANXTDSC) Next Descriptor Address */ +#define UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << UOTGHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- UOTGHS_HSTDMAADDRESS : (UOTGHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (UOTGHS_HSTDMAADDRESS) Buffer Address */ +#define UOTGHS_HSTDMAADDRESS_BUFF_ADD(value) ((UOTGHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << UOTGHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- UOTGHS_HSTDMACONTROL : (UOTGHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define UOTGHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMACONTROL) Channel Enable Command */ +#define UOTGHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (UOTGHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define UOTGHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Enable (Control) */ +#define UOTGHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define UOTGHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (UOTGHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (UOTGHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (UOTGHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define UOTGHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (UOTGHS_HSTDMACONTROL) Burst Lock Enable */ +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (UOTGHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define UOTGHS_HSTDMACONTROL_BUFF_LENGTH(value) ((UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << UOTGHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- UOTGHS_HSTDMASTATUS : (UOTGHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define UOTGHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Enable Status */ +#define UOTGHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (UOTGHS_HSTDMASTATUS) Channel Active Status */ +#define UOTGHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define UOTGHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (UOTGHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define UOTGHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (UOTGHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (UOTGHS_HSTDMASTATUS) Buffer Byte Count */ +#define UOTGHS_HSTDMASTATUS_BUFF_COUNT(value) ((UOTGHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << UOTGHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- UOTGHS_CTRL : (UOTGHS Offset: 0x0800) General Control Register -------- */ +#define UOTGHS_CTRL_IDTE (0x1u << 0) /**< \brief (UOTGHS_CTRL) ID Transition Interrupt Enable */ +#define UOTGHS_CTRL_VBUSTE (0x1u << 1) /**< \brief (UOTGHS_CTRL) VBus Transition Interrupt Enable */ +#define UOTGHS_CTRL_SRPE (0x1u << 2) /**< \brief (UOTGHS_CTRL) SRP Interrupt Enable */ +#define UOTGHS_CTRL_VBERRE (0x1u << 3) /**< \brief (UOTGHS_CTRL) VBus Error Interrupt Enable */ +#define UOTGHS_CTRL_BCERRE (0x1u << 4) /**< \brief (UOTGHS_CTRL) B-Connection Error Interrupt Enable */ +#define UOTGHS_CTRL_ROLEEXE (0x1u << 5) /**< \brief (UOTGHS_CTRL) Role Exchange Interrupt Enable */ +#define UOTGHS_CTRL_HNPERRE (0x1u << 6) /**< \brief (UOTGHS_CTRL) HNP Error Interrupt Enable */ +#define UOTGHS_CTRL_STOE (0x1u << 7) /**< \brief (UOTGHS_CTRL) Suspend Time-Out Interrupt Enable */ +#define UOTGHS_CTRL_VBUSHWC (0x1u << 8) /**< \brief (UOTGHS_CTRL) VBus Hardware Control */ +#define UOTGHS_CTRL_SRPSEL (0x1u << 9) /**< \brief (UOTGHS_CTRL) SRP Selection */ +#define UOTGHS_CTRL_SRPREQ (0x1u << 10) /**< \brief (UOTGHS_CTRL) SRP Request */ +#define UOTGHS_CTRL_HNPREQ (0x1u << 11) /**< \brief (UOTGHS_CTRL) HNP Request */ +#define UOTGHS_CTRL_OTGPADE (0x1u << 12) /**< \brief (UOTGHS_CTRL) OTG Pad Enable */ +#define UOTGHS_CTRL_VBUSPO (0x1u << 13) /**< \brief (UOTGHS_CTRL) VBus Polarity Off */ +#define UOTGHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (UOTGHS_CTRL) Freeze USB Clock */ +#define UOTGHS_CTRL_USBE (0x1u << 15) /**< \brief (UOTGHS_CTRL) UOTGHS Enable */ +#define UOTGHS_CTRL_TIMVALUE_Pos 16 +#define UOTGHS_CTRL_TIMVALUE_Msk (0x3u << UOTGHS_CTRL_TIMVALUE_Pos) /**< \brief (UOTGHS_CTRL) Timer Value */ +#define UOTGHS_CTRL_TIMVALUE(value) ((UOTGHS_CTRL_TIMVALUE_Msk & ((value) << UOTGHS_CTRL_TIMVALUE_Pos))) +#define UOTGHS_CTRL_TIMPAGE_Pos 20 +#define UOTGHS_CTRL_TIMPAGE_Msk (0x3u << UOTGHS_CTRL_TIMPAGE_Pos) /**< \brief (UOTGHS_CTRL) Timer Page */ +#define UOTGHS_CTRL_TIMPAGE(value) ((UOTGHS_CTRL_TIMPAGE_Msk & ((value) << UOTGHS_CTRL_TIMPAGE_Pos))) +#define UOTGHS_CTRL_UNLOCK (0x1u << 22) /**< \brief (UOTGHS_CTRL) Timer Access Unlock */ +#define UOTGHS_CTRL_UIDE (0x1u << 24) /**< \brief (UOTGHS_CTRL) UOTGID Pin Enable */ +#define UOTGHS_CTRL_UIDE_UIMOD (0x0u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UIMOD bit. */ +#define UOTGHS_CTRL_UIDE_UOTGID (0x1u << 24) /**< \brief (UOTGHS_CTRL) The USB mode (device/host) is selected from the UOTGID input pin. */ +#define UOTGHS_CTRL_UIMOD (0x1u << 25) /**< \brief (UOTGHS_CTRL) UOTGHS Mode */ +#define UOTGHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB host mode. */ +#define UOTGHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (UOTGHS_CTRL) The module is in USB device mode. */ +/* -------- UOTGHS_SR : (UOTGHS Offset: 0x0804) General Status Register -------- */ +#define UOTGHS_SR_IDTI (0x1u << 0) /**< \brief (UOTGHS_SR) ID Transition Interrupt */ +#define UOTGHS_SR_VBUSTI (0x1u << 1) /**< \brief (UOTGHS_SR) VBus Transition Interrupt */ +#define UOTGHS_SR_SRPI (0x1u << 2) /**< \brief (UOTGHS_SR) SRP Interrupt */ +#define UOTGHS_SR_VBERRI (0x1u << 3) /**< \brief (UOTGHS_SR) VBus Error Interrupt */ +#define UOTGHS_SR_BCERRI (0x1u << 4) /**< \brief (UOTGHS_SR) B-Connection Error Interrupt */ +#define UOTGHS_SR_ROLEEXI (0x1u << 5) /**< \brief (UOTGHS_SR) Role Exchange Interrupt */ +#define UOTGHS_SR_HNPERRI (0x1u << 6) /**< \brief (UOTGHS_SR) HNP Error Interrupt */ +#define UOTGHS_SR_STOI (0x1u << 7) /**< \brief (UOTGHS_SR) Suspend Time-Out Interrupt */ +#define UOTGHS_SR_VBUSRQ (0x1u << 9) /**< \brief (UOTGHS_SR) VBus Request */ +#define UOTGHS_SR_ID (0x1u << 10) /**< \brief (UOTGHS_SR) UOTGID Pin State */ +#define UOTGHS_SR_VBUS (0x1u << 11) /**< \brief (UOTGHS_SR) VBus Level */ +#define UOTGHS_SR_SPEED_Pos 12 +#define UOTGHS_SR_SPEED_Msk (0x3u << UOTGHS_SR_SPEED_Pos) /**< \brief (UOTGHS_SR) Speed Status */ +#define UOTGHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (UOTGHS_SR) Full-Speed mode */ +#define UOTGHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (UOTGHS_SR) High-Speed mode */ +#define UOTGHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (UOTGHS_SR) Low-Speed mode */ +#define UOTGHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (UOTGHS_SR) UTMI Clock Usable */ +/* -------- UOTGHS_SCR : (UOTGHS Offset: 0x0808) General Status Clear Register -------- */ +#define UOTGHS_SCR_IDTIC (0x1u << 0) /**< \brief (UOTGHS_SCR) ID Transition Interrupt Clear */ +#define UOTGHS_SCR_VBUSTIC (0x1u << 1) /**< \brief (UOTGHS_SCR) VBus Transition Interrupt Clear */ +#define UOTGHS_SCR_SRPIC (0x1u << 2) /**< \brief (UOTGHS_SCR) SRP Interrupt Clear */ +#define UOTGHS_SCR_VBERRIC (0x1u << 3) /**< \brief (UOTGHS_SCR) VBus Error Interrupt Clear */ +#define UOTGHS_SCR_BCERRIC (0x1u << 4) /**< \brief (UOTGHS_SCR) B-Connection Error Interrupt Clear */ +#define UOTGHS_SCR_ROLEEXIC (0x1u << 5) /**< \brief (UOTGHS_SCR) Role Exchange Interrupt Clear */ +#define UOTGHS_SCR_HNPERRIC (0x1u << 6) /**< \brief (UOTGHS_SCR) HNP Error Interrupt Clear */ +#define UOTGHS_SCR_STOIC (0x1u << 7) /**< \brief (UOTGHS_SCR) Suspend Time-Out Interrupt Clear */ +#define UOTGHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (UOTGHS_SCR) VBus Request Clear */ +/* -------- UOTGHS_SFR : (UOTGHS Offset: 0x080C) General Status Set Register -------- */ +#define UOTGHS_SFR_IDTIS (0x1u << 0) /**< \brief (UOTGHS_SFR) ID Transition Interrupt Set */ +#define UOTGHS_SFR_VBUSTIS (0x1u << 1) /**< \brief (UOTGHS_SFR) VBus Transition Interrupt Set */ +#define UOTGHS_SFR_SRPIS (0x1u << 2) /**< \brief (UOTGHS_SFR) SRP Interrupt Set */ +#define UOTGHS_SFR_VBERRIS (0x1u << 3) /**< \brief (UOTGHS_SFR) VBus Error Interrupt Set */ +#define UOTGHS_SFR_BCERRIS (0x1u << 4) /**< \brief (UOTGHS_SFR) B-Connection Error Interrupt Set */ +#define UOTGHS_SFR_ROLEEXIS (0x1u << 5) /**< \brief (UOTGHS_SFR) Role Exchange Interrupt Set */ +#define UOTGHS_SFR_HNPERRIS (0x1u << 6) /**< \brief (UOTGHS_SFR) HNP Error Interrupt Set */ +#define UOTGHS_SFR_STOIS (0x1u << 7) /**< \brief (UOTGHS_SFR) Suspend Time-Out Interrupt Set */ +#define UOTGHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (UOTGHS_SFR) VBus Request Set */ +/* -------- UOTGHS_TSTA1 : (UOTGHS Offset: 0x0810) General Test A1 Register -------- */ +#define UOTGHS_TSTA1_CounterA_Pos 0 +#define UOTGHS_TSTA1_CounterA_Msk (0x7fffu << UOTGHS_TSTA1_CounterA_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterA */ +#define UOTGHS_TSTA1_CounterA(value) ((UOTGHS_TSTA1_CounterA_Msk & ((value) << UOTGHS_TSTA1_CounterA_Pos))) +#define UOTGHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (UOTGHS_TSTA1) Load CounterA */ +#define UOTGHS_TSTA1_CounterB_Pos 16 +#define UOTGHS_TSTA1_CounterB_Msk (0x3fu << UOTGHS_TSTA1_CounterB_Pos) /**< \brief (UOTGHS_TSTA1) Load CounterB */ +#define UOTGHS_TSTA1_CounterB(value) ((UOTGHS_TSTA1_CounterB_Msk & ((value) << UOTGHS_TSTA1_CounterB_Pos))) +#define UOTGHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (UOTGHS_TSTA1) Load CounterB */ +#define UOTGHS_TSTA1_SOFCntMa1_Pos 24 +#define UOTGHS_TSTA1_SOFCntMa1_Msk (0x7fu << UOTGHS_TSTA1_SOFCntMa1_Pos) /**< \brief (UOTGHS_TSTA1) SOF Counter Max */ +#define UOTGHS_TSTA1_SOFCntMa1(value) ((UOTGHS_TSTA1_SOFCntMa1_Msk & ((value) << UOTGHS_TSTA1_SOFCntMa1_Pos))) +#define UOTGHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (UOTGHS_TSTA1) Load SOF Counter */ +/* -------- UOTGHS_TSTA2 : (UOTGHS Offset: 0x0814) General Test A2 Register -------- */ +#define UOTGHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (UOTGHS_TSTA2) Full Detach Enable */ +#define UOTGHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (UOTGHS_TSTA2) HS Serial Mode */ +#define UOTGHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (UOTGHS_TSTA2) Loop-back Mode */ +#define UOTGHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (UOTGHS_TSTA2) Disable Gated Clock */ +#define UOTGHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (UOTGHS_TSTA2) Force SuspendM to 1 */ +#define UOTGHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (UOTGHS_TSTA2) Bypass DPLL */ +#define UOTGHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (UOTGHS_TSTA2) Host HS Disconnect Disable */ +#define UOTGHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (UOTGHS_TSTA2) Force HS Reset to 50 ms */ +#define UOTGHS_TSTA2_UTMIReset (0x1u << 8) /**< \brief (UOTGHS_TSTA2) UTMI Reset */ +#define UOTGHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (UOTGHS_TSTA2) Remove Pull-up When TX */ +/* -------- UOTGHS_VERSION : (UOTGHS Offset: 0x0818) General Version Register -------- */ +#define UOTGHS_VERSION_VERSION_Pos 0 +#define UOTGHS_VERSION_VERSION_Msk (0xfffu << UOTGHS_VERSION_VERSION_Pos) /**< \brief (UOTGHS_VERSION) Version Number */ +#define UOTGHS_VERSION_VARIANT_Pos 16 +#define UOTGHS_VERSION_VARIANT_Msk (0xfu << UOTGHS_VERSION_VARIANT_Pos) /**< \brief (UOTGHS_VERSION) Variant Number */ +/* -------- UOTGHS_FEATURES : (UOTGHS Offset: 0x081C) General Features Register -------- */ +#define UOTGHS_FEATURES_EPTNBRMAX_Pos 0 +#define UOTGHS_FEATURES_EPTNBRMAX_Msk (0xfu << UOTGHS_FEATURES_EPTNBRMAX_Pos) /**< \brief (UOTGHS_FEATURES) Maximal Number of Pipes/Endpoints */ +#define UOTGHS_FEATURES_EPTNBRMAX_16_P_E (0x0u << 0) /**< \brief (UOTGHS_FEATURES) 16 pipes/endpoints */ +#define UOTGHS_FEATURES_EPTNBRMAX_1_P_E (0x1u << 0) /**< \brief (UOTGHS_FEATURES) 1 pipe/endpoint */ +#define UOTGHS_FEATURES_EPTNBRMAX_2_P_E (0x2u << 0) /**< \brief (UOTGHS_FEATURES) 2 pipes/endpoints */ +#define UOTGHS_FEATURES_EPTNBRMAX_15_P_E (0xFu << 0) /**< \brief (UOTGHS_FEATURES) 15 pipes/endpoints */ +#define UOTGHS_FEATURES_DMACHANNELNBR_Pos 4 +#define UOTGHS_FEATURES_DMACHANNELNBR_Msk (0x7u << UOTGHS_FEATURES_DMACHANNELNBR_Pos) /**< \brief (UOTGHS_FEATURES) Number of DMA Channels */ +#define UOTGHS_FEATURES_DMACHANNELNBR_1_DMA_CH (0x1u << 4) /**< \brief (UOTGHS_FEATURES) 1 DMA channel */ +#define UOTGHS_FEATURES_DMACHANNELNBR_2_DMA_CH (0x2u << 4) /**< \brief (UOTGHS_FEATURES) 2 DMA channels */ +#define UOTGHS_FEATURES_DMACHANNELNBR_7_DMA_CH (0x7u << 4) /**< \brief (UOTGHS_FEATURES) 7 DMA channels */ +#define UOTGHS_FEATURES_DMABUFFERSIZE (0x1u << 7) /**< \brief (UOTGHS_FEATURES) DMA Buffer Size */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos 8 +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Msk (0xfu << UOTGHS_FEATURES_DMAFIFOWORDDEPTH_Pos) /**< \brief (UOTGHS_FEATURES) DMA FIFO Depth in Words */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_16_DMA_F_D (0x0u << 8) /**< \brief (UOTGHS_FEATURES) 16 DMA FIFO depth */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_1_DMA_F_D (0x1u << 8) /**< \brief (UOTGHS_FEATURES) 1 DMA FIFO depth */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_2_DMA_F_D (0x2u << 8) /**< \brief (UOTGHS_FEATURES) 2 DMA FIFO depth */ +#define UOTGHS_FEATURES_DMAFIFOWORDDEPTH_15_DMA_F_D (0xFu << 8) /**< \brief (UOTGHS_FEATURES) 15 DMA FIFO depth */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_Pos 12 +#define UOTGHS_FEATURES_FIFOMAXSIZE_Msk (0x7u << UOTGHS_FEATURES_FIFOMAXSIZE_Pos) /**< \brief (UOTGHS_FEATURES) Maximal FIFO Size */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_256_BYTE (0x0u << 12) /**< \brief (UOTGHS_FEATURES) < 256 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_512_BYTE (0x1u << 12) /**< \brief (UOTGHS_FEATURES) < 512 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_1024_BYTE (0x2u << 12) /**< \brief (UOTGHS_FEATURES) < 1024 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_2048_BYTE (0x3u << 12) /**< \brief (UOTGHS_FEATURES) < 2048 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_4096_BYTE (0x4u << 12) /**< \brief (UOTGHS_FEATURES) < 4096 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_8192_BYTE (0x5u << 12) /**< \brief (UOTGHS_FEATURES) < 8192 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_16384_BYTE (0x6u << 12) /**< \brief (UOTGHS_FEATURES) < 16384 bytes */ +#define UOTGHS_FEATURES_FIFOMAXSIZE_P16384_BYTE (0x7u << 12) /**< \brief (UOTGHS_FEATURES) >= 16384 bytes */ +#define UOTGHS_FEATURES_BYTEWRITEDPRAM (0x1u << 15) /**< \brief (UOTGHS_FEATURES) DPRAM Byte-Write Capability */ +#define UOTGHS_FEATURES_DATABUS (0x1u << 16) /**< \brief (UOTGHS_FEATURES) Data Bus 16-8 */ +#define UOTGHS_FEATURES_ENHBISO1 (0x1u << 17) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 1 */ +#define UOTGHS_FEATURES_ENHBISO2 (0x1u << 18) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 2 */ +#define UOTGHS_FEATURES_ENHBISO3 (0x1u << 19) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 3 */ +#define UOTGHS_FEATURES_ENHBISO4 (0x1u << 20) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 4 */ +#define UOTGHS_FEATURES_ENHBISO5 (0x1u << 21) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 5 */ +#define UOTGHS_FEATURES_ENHBISO6 (0x1u << 22) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 6 */ +#define UOTGHS_FEATURES_ENHBISO7 (0x1u << 23) /**< \brief (UOTGHS_FEATURES) High Bandwidth Isochronous Feature for Endpoint 7 */ +/* -------- UOTGHS_ADDRSIZE : (UOTGHS Offset: 0x0820) General APB Address Size Register -------- */ +#define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos 0 +#define UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Msk (0xffffffffu << UOTGHS_ADDRSIZE_UOTGHS_ADDRSIZE_Pos) /**< \brief (UOTGHS_ADDRSIZE) IP APB Address Size */ +/* -------- UOTGHS_IPNAME1 : (UOTGHS Offset: 0x0824) General Name Register 1 -------- */ +#define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos 0 +#define UOTGHS_IPNAME1_UOTGHS_IPNAME1_Msk (0xffffffffu << UOTGHS_IPNAME1_UOTGHS_IPNAME1_Pos) /**< \brief (UOTGHS_IPNAME1) IP Name Part One */ +/* -------- UOTGHS_IPNAME2 : (UOTGHS Offset: 0x0828) General Name Register 2 -------- */ +#define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos 0 +#define UOTGHS_IPNAME2_UOTGHS_IPNAME2_Msk (0xffffffffu << UOTGHS_IPNAME2_UOTGHS_IPNAME2_Pos) /**< \brief (UOTGHS_IPNAME2) IP Name Part Two */ +/* -------- UOTGHS_FSM : (UOTGHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define UOTGHS_FSM_DRDSTATE_Pos 0 +#define UOTGHS_FSM_DRDSTATE_Msk (0xfu << UOTGHS_FSM_DRDSTATE_Pos) /**< \brief (UOTGHS_FSM) Dual Role Device State */ +#define UOTGHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (UOTGHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define UOTGHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define UOTGHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (UOTGHS_FSM) The A-device operating as a host is in the suspend mode. */ +#define UOTGHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (UOTGHS_FSM) The A-device operates as a peripheral. */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define UOTGHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define UOTGHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (UOTGHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define UOTGHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (UOTGHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define UOTGHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the peripheral. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device is in suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us) before becoming Host. */ +#define UOTGHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define UOTGHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device acts as the Host. */ +#define UOTGHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (UOTGHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAM_UOTGHS_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_usart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_usart.h new file mode 100644 index 000000000..f7112474c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_usart.h @@ -0,0 +1,425 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART_COMPONENT_ +#define _SAMV71_USART_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Universal Synchronous Asynchronous Receiver Transmitter */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USART Universal Synchronous Asynchronous Receiver Transmitter */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Usart hardware registers */ +typedef struct { + __O uint32_t US_CR; /**< \brief (Usart Offset: 0x0000) Control Register */ + __IO uint32_t US_MR; /**< \brief (Usart Offset: 0x0004) Mode Register */ + __O uint32_t US_IER; /**< \brief (Usart Offset: 0x0008) Interrupt Enable Register */ + __O uint32_t US_IDR; /**< \brief (Usart Offset: 0x000C) Interrupt Disable Register */ + __I uint32_t US_IMR; /**< \brief (Usart Offset: 0x0010) Interrupt Mask Register */ + __I uint32_t US_CSR; /**< \brief (Usart Offset: 0x0014) Channel Status Register */ + __I uint32_t US_RHR; /**< \brief (Usart Offset: 0x0018) Receive Holding Register */ + __O uint32_t US_THR; /**< \brief (Usart Offset: 0x001C) Transmit Holding Register */ + __IO uint32_t US_BRGR; /**< \brief (Usart Offset: 0x0020) Baud Rate Generator Register */ + __IO uint32_t US_RTOR; /**< \brief (Usart Offset: 0x0024) Receiver Time-out Register */ + __IO uint32_t US_TTGR; /**< \brief (Usart Offset: 0x0028) Transmitter Timeguard Register */ + __I uint32_t Reserved1[5]; + __IO uint32_t US_FIDI; /**< \brief (Usart Offset: 0x0040) FI DI Ratio Register */ + __I uint32_t US_NER; /**< \brief (Usart Offset: 0x0044) Number of Errors Register */ + __I uint32_t Reserved2[2]; + __IO uint32_t US_MAN; /**< \brief (Usart Offset: 0x0050) Manchester Configuration Register */ + __IO uint32_t US_LINMR; /**< \brief (Usart Offset: 0x0054) LIN Mode Register */ + __IO uint32_t US_LINIR; /**< \brief (Usart Offset: 0x0058) LIN Identifier Register */ + __I uint32_t US_LINBRR; /**< \brief (Usart Offset: 0x005C) LIN Baud Rate Register */ + __IO uint32_t US_LONMR; /**< \brief (Usart Offset: 0x0060) LON Mode Register */ + __IO uint32_t US_LONPR; /**< \brief (Usart Offset: 0x0064) LON Preamble Register */ + __IO uint32_t US_LONDL; /**< \brief (Usart Offset: 0x0068) LON Data Length Register */ + __IO uint32_t US_LONL2HDR; /**< \brief (Usart Offset: 0x006C) LON L2HDR Register */ + __I uint32_t US_LONBL; /**< \brief (Usart Offset: 0x0070) LON Backlog Register */ + __IO uint32_t US_LONB1TX; /**< \brief (Usart Offset: 0x0074) LON Beta1 Tx Register */ + __IO uint32_t US_LONB1RX; /**< \brief (Usart Offset: 0x0078) LON Beta1 Rx Register */ + __IO uint32_t US_LONPRIO; /**< \brief (Usart Offset: 0x007C) LON Priority Register */ + __IO uint32_t US_IDTTX; /**< \brief (Usart Offset: 0x0080) LON IDT Tx Register */ + __IO uint32_t US_IDTRX; /**< \brief (Usart Offset: 0x0084) LON IDT Rx Register */ + __IO uint32_t US_ICDIFF; /**< \brief (Usart Offset: 0x0088) IC DIFF Register */ + __I uint32_t Reserved3[22]; + __IO uint32_t US_WPMR; /**< \brief (Usart Offset: 0x00E4) Write Protection Mode Register */ + __I uint32_t US_WPSR; /**< \brief (Usart Offset: 0x00E8) Write Protection Status Register */ +} Usart; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- US_CR : (USART Offset: 0x0000) Control Register -------- */ +#define US_CR_RSTRX (0x1u << 2) /**< \brief (US_CR) Reset Receiver */ +#define US_CR_RSTTX (0x1u << 3) /**< \brief (US_CR) Reset Transmitter */ +#define US_CR_RXEN (0x1u << 4) /**< \brief (US_CR) Receiver Enable */ +#define US_CR_RXDIS (0x1u << 5) /**< \brief (US_CR) Receiver Disable */ +#define US_CR_TXEN (0x1u << 6) /**< \brief (US_CR) Transmitter Enable */ +#define US_CR_TXDIS (0x1u << 7) /**< \brief (US_CR) Transmitter Disable */ +#define US_CR_RSTSTA (0x1u << 8) /**< \brief (US_CR) Reset Status Bits */ +#define US_CR_STTBRK (0x1u << 9) /**< \brief (US_CR) Start Break */ +#define US_CR_STPBRK (0x1u << 10) /**< \brief (US_CR) Stop Break */ +#define US_CR_STTTO (0x1u << 11) /**< \brief (US_CR) Clear TIMEOUT Flag and Start Time-out After Next Character Received */ +#define US_CR_SENDA (0x1u << 12) /**< \brief (US_CR) Send Address */ +#define US_CR_RSTIT (0x1u << 13) /**< \brief (US_CR) Reset Iterations */ +#define US_CR_RSTNACK (0x1u << 14) /**< \brief (US_CR) Reset Non Acknowledge */ +#define US_CR_RETTO (0x1u << 15) /**< \brief (US_CR) Start Time-out Immediately */ +#define US_CR_RTSEN (0x1u << 18) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_RTSDIS (0x1u << 19) /**< \brief (US_CR) Request to Send Pin Control */ +#define US_CR_LINABT (0x1u << 20) /**< \brief (US_CR) Abort LIN Transmission */ +#define US_CR_LINWKUP (0x1u << 21) /**< \brief (US_CR) Send LIN Wakeup Signal */ +#define US_CR_FCS (0x1u << 18) /**< \brief (US_CR) Force SPI Chip Select */ +#define US_CR_RCS (0x1u << 19) /**< \brief (US_CR) Release SPI Chip Select */ +/* -------- US_MR : (USART Offset: 0x0004) Mode Register -------- */ +#define US_MR_USART_MODE_Pos 0 +#define US_MR_USART_MODE_Msk (0xfu << US_MR_USART_MODE_Pos) /**< \brief (US_MR) USART Mode of Operation */ +#define US_MR_USART_MODE(value) ((US_MR_USART_MODE_Msk & ((value) << US_MR_USART_MODE_Pos))) +#define US_MR_USART_MODE_NORMAL (0x0u << 0) /**< \brief (US_MR) Normal mode */ +#define US_MR_USART_MODE_RS485 (0x1u << 0) /**< \brief (US_MR) RS485 */ +#define US_MR_USART_MODE_HW_HANDSHAKING (0x2u << 0) /**< \brief (US_MR) Hardware Handshaking */ +#define US_MR_USART_MODE_IS07816_T_0 (0x4u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 0 */ +#define US_MR_USART_MODE_IS07816_T_1 (0x6u << 0) /**< \brief (US_MR) IS07816 Protocol: T = 1 */ +#define US_MR_USART_MODE_LON (0x9u << 0) /**< \brief (US_MR) LON */ +#define US_MR_USART_MODE_SPI_MASTER (0xEu << 0) /**< \brief (US_MR) SPI master */ +#define US_MR_USART_MODE_SPI_SLAVE (0xFu << 0) /**< \brief (US_MR) SPI Slave */ +#define US_MR_USCLKS_Pos 4 +#define US_MR_USCLKS_Msk (0x3u << US_MR_USCLKS_Pos) /**< \brief (US_MR) Clock Selection */ +#define US_MR_USCLKS(value) ((US_MR_USCLKS_Msk & ((value) << US_MR_USCLKS_Pos))) +#define US_MR_USCLKS_MCK (0x0u << 4) /**< \brief (US_MR) Peripheral clock is selected */ +#define US_MR_USCLKS_DIV (0x1u << 4) /**< \brief (US_MR) Peripheral clock divided (DIV=DIV=8) is selected */ +#define US_MR_USCLKS_PCK (0x2u << 4) /**< \brief (US_MR) PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. */ +#define US_MR_USCLKS_SCK (0x3u << 4) /**< \brief (US_MR) Serial clock (SCK) is selected */ +#define US_MR_CHRL_Pos 6 +#define US_MR_CHRL_Msk (0x3u << US_MR_CHRL_Pos) /**< \brief (US_MR) Character Length */ +#define US_MR_CHRL(value) ((US_MR_CHRL_Msk & ((value) << US_MR_CHRL_Pos))) +#define US_MR_CHRL_5_BIT (0x0u << 6) /**< \brief (US_MR) Character length is 5 bits */ +#define US_MR_CHRL_6_BIT (0x1u << 6) /**< \brief (US_MR) Character length is 6 bits */ +#define US_MR_CHRL_7_BIT (0x2u << 6) /**< \brief (US_MR) Character length is 7 bits */ +#define US_MR_CHRL_8_BIT (0x3u << 6) /**< \brief (US_MR) Character length is 8 bits */ +#define US_MR_SYNC (0x1u << 8) /**< \brief (US_MR) Synchronous Mode Select */ +#define US_MR_PAR_Pos 9 +#define US_MR_PAR_Msk (0x7u << US_MR_PAR_Pos) /**< \brief (US_MR) Parity Type */ +#define US_MR_PAR(value) ((US_MR_PAR_Msk & ((value) << US_MR_PAR_Pos))) +#define US_MR_PAR_EVEN (0x0u << 9) /**< \brief (US_MR) Even parity */ +#define US_MR_PAR_ODD (0x1u << 9) /**< \brief (US_MR) Odd parity */ +#define US_MR_PAR_SPACE (0x2u << 9) /**< \brief (US_MR) Parity forced to 0 (Space) */ +#define US_MR_PAR_MARK (0x3u << 9) /**< \brief (US_MR) Parity forced to 1 (Mark) */ +#define US_MR_PAR_NO (0x4u << 9) /**< \brief (US_MR) No parity */ +#define US_MR_PAR_MULTIDROP (0x6u << 9) /**< \brief (US_MR) Multidrop mode */ +#define US_MR_NBSTOP_Pos 12 +#define US_MR_NBSTOP_Msk (0x3u << US_MR_NBSTOP_Pos) /**< \brief (US_MR) Number of Stop Bits */ +#define US_MR_NBSTOP(value) ((US_MR_NBSTOP_Msk & ((value) << US_MR_NBSTOP_Pos))) +#define US_MR_NBSTOP_1_BIT (0x0u << 12) /**< \brief (US_MR) 1 stop bit */ +#define US_MR_NBSTOP_1_5_BIT (0x1u << 12) /**< \brief (US_MR) 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) */ +#define US_MR_NBSTOP_2_BIT (0x2u << 12) /**< \brief (US_MR) 2 stop bits */ +#define US_MR_CHMODE_Pos 14 +#define US_MR_CHMODE_Msk (0x3u << US_MR_CHMODE_Pos) /**< \brief (US_MR) Channel Mode */ +#define US_MR_CHMODE(value) ((US_MR_CHMODE_Msk & ((value) << US_MR_CHMODE_Pos))) +#define US_MR_CHMODE_NORMAL (0x0u << 14) /**< \brief (US_MR) Normal mode */ +#define US_MR_CHMODE_AUTOMATIC (0x1u << 14) /**< \brief (US_MR) Automatic Echo. Receiver input is connected to the TXD pin. */ +#define US_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) /**< \brief (US_MR) Local Loopback. Transmitter output is connected to the Receiver Input. */ +#define US_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) /**< \brief (US_MR) Remote Loopback. RXD pin is internally connected to the TXD pin. */ +#define US_MR_MODE9 (0x1u << 17) /**< \brief (US_MR) 9-bit Character Length */ +#define US_MR_CLKO (0x1u << 18) /**< \brief (US_MR) Clock Output Select */ +#define US_MR_OVER (0x1u << 19) /**< \brief (US_MR) Oversampling Mode */ +#define US_MR_VAR_SYNC (0x1u << 22) /**< \brief (US_MR) Variable Synchronization of Command/Data Sync Start Frame Delimiter */ +#define US_MR_FILTER (0x1u << 28) /**< \brief (US_MR) Receive Line Filter */ +#define US_MR_MAN (0x1u << 29) /**< \brief (US_MR) Manchester Encoder/Decoder Enable */ +#define US_MR_MODSYNC (0x1u << 30) /**< \brief (US_MR) Manchester Synchronization Mode */ +#define US_MR_ONEBIT (0x1u << 31) /**< \brief (US_MR) Start Frame Delimiter Selector */ +#define US_MR_CPHA (0x1u << 8) /**< \brief (US_MR) SPI Clock Phase */ +#define US_MR_CPOL (0x1u << 16) /**< \brief (US_MR) SPI Clock Polarity */ +#define US_MR_WRDBT (0x1u << 20) /**< \brief (US_MR) Wait Read Data Before Transfer */ +/* -------- US_IER : (USART Offset: 0x0008) Interrupt Enable Register -------- */ +#define US_IER_RXRDY (0x1u << 0) /**< \brief (US_IER) RXRDY Interrupt Enable */ +#define US_IER_TXRDY (0x1u << 1) /**< \brief (US_IER) TXRDY Interrupt Enable */ +#define US_IER_RXBRK (0x1u << 2) /**< \brief (US_IER) Receiver Break Interrupt Enable */ +#define US_IER_OVRE (0x1u << 5) /**< \brief (US_IER) Overrun Error Interrupt Enable */ +#define US_IER_FRAME (0x1u << 6) /**< \brief (US_IER) Framing Error Interrupt Enable */ +#define US_IER_PARE (0x1u << 7) /**< \brief (US_IER) Parity Error Interrupt Enable */ +#define US_IER_TIMEOUT (0x1u << 8) /**< \brief (US_IER) Time-out Interrupt Enable */ +#define US_IER_TXEMPTY (0x1u << 9) /**< \brief (US_IER) TXEMPTY Interrupt Enable */ +#define US_IER_CTSIC (0x1u << 19) /**< \brief (US_IER) Clear to Send Input Change Interrupt Enable */ +#define US_IER_MANE (0x1u << 24) /**< \brief (US_IER) Manchester Error Interrupt Enable */ +#define US_IER_UNRE (0x1u << 10) /**< \brief (US_IER) SPI Underrun Error Interrupt Enable */ +#define US_IER_LINBK (0x1u << 13) /**< \brief (US_IER) LIN Break Sent or LIN Break Received Interrupt Enable */ +#define US_IER_LINID (0x1u << 14) /**< \brief (US_IER) LIN Identifier Sent or LIN Identifier Received Interrupt Enable */ +#define US_IER_LINTC (0x1u << 15) /**< \brief (US_IER) LIN Transfer Completed Interrupt Enable */ +#define US_IER_LINBE (0x1u << 25) /**< \brief (US_IER) LIN Bus Error Interrupt Enable */ +#define US_IER_LINISFE (0x1u << 26) /**< \brief (US_IER) LIN Inconsistent Synch Field Error Interrupt Enable */ +#define US_IER_LINIPE (0x1u << 27) /**< \brief (US_IER) LIN Identifier Parity Interrupt Enable */ +#define US_IER_LINCE (0x1u << 28) /**< \brief (US_IER) LIN Checksum Error Interrupt Enable */ +#define US_IER_LINSNRE (0x1u << 29) /**< \brief (US_IER) LIN Slave Not Responding Error Interrupt Enable */ +#define US_IER_LINSTE (0x1u << 30) /**< \brief (US_IER) LIN Synch Tolerance Error Interrupt Enable */ +#define US_IER_LINHTE (0x1u << 31) /**< \brief (US_IER) LIN Header Timeout Error Interrupt Enable */ +#define US_IER_LSFE (0x1u << 6) /**< \brief (US_IER) LON Short Frame Error Interrupt Enable */ +#define US_IER_LCRCE (0x1u << 7) /**< \brief (US_IER) LON CRC Error Interrupt Enable */ +#define US_IER_LTXD (0x1u << 24) /**< \brief (US_IER) LON Transmission Done Interrupt Enable */ +#define US_IER_LCOL (0x1u << 25) /**< \brief (US_IER) LON Collision Interrupt Enable */ +#define US_IER_LFET (0x1u << 26) /**< \brief (US_IER) LON Frame Early Termination Interrupt Enable */ +#define US_IER_LRXD (0x1u << 27) /**< \brief (US_IER) LON Reception Done Interrupt Enable */ +#define US_IER_LBLOVFE (0x1u << 28) /**< \brief (US_IER) LON Backlog Overflow Error Interrupt Enable */ +/* -------- US_IDR : (USART Offset: 0x000C) Interrupt Disable Register -------- */ +#define US_IDR_RXRDY (0x1u << 0) /**< \brief (US_IDR) RXRDY Interrupt Disable */ +#define US_IDR_TXRDY (0x1u << 1) /**< \brief (US_IDR) TXRDY Interrupt Disable */ +#define US_IDR_RXBRK (0x1u << 2) /**< \brief (US_IDR) Receiver Break Interrupt Disable */ +#define US_IDR_OVRE (0x1u << 5) /**< \brief (US_IDR) Overrun Error Interrupt Enable */ +#define US_IDR_FRAME (0x1u << 6) /**< \brief (US_IDR) Framing Error Interrupt Disable */ +#define US_IDR_PARE (0x1u << 7) /**< \brief (US_IDR) Parity Error Interrupt Disable */ +#define US_IDR_TIMEOUT (0x1u << 8) /**< \brief (US_IDR) Time-out Interrupt Disable */ +#define US_IDR_TXEMPTY (0x1u << 9) /**< \brief (US_IDR) TXEMPTY Interrupt Disable */ +#define US_IDR_CTSIC (0x1u << 19) /**< \brief (US_IDR) Clear to Send Input Change Interrupt Disable */ +#define US_IDR_MANE (0x1u << 24) /**< \brief (US_IDR) Manchester Error Interrupt Disable */ +#define US_IDR_UNRE (0x1u << 10) /**< \brief (US_IDR) SPI Underrun Error Interrupt Disable */ +#define US_IDR_LINBK (0x1u << 13) /**< \brief (US_IDR) LIN Break Sent or LIN Break Received Interrupt Disable */ +#define US_IDR_LINID (0x1u << 14) /**< \brief (US_IDR) LIN Identifier Sent or LIN Identifier Received Interrupt Disable */ +#define US_IDR_LINTC (0x1u << 15) /**< \brief (US_IDR) LIN Transfer Completed Interrupt Disable */ +#define US_IDR_LINBE (0x1u << 25) /**< \brief (US_IDR) LIN Bus Error Interrupt Disable */ +#define US_IDR_LINISFE (0x1u << 26) /**< \brief (US_IDR) LIN Inconsistent Synch Field Error Interrupt Disable */ +#define US_IDR_LINIPE (0x1u << 27) /**< \brief (US_IDR) LIN Identifier Parity Interrupt Disable */ +#define US_IDR_LINCE (0x1u << 28) /**< \brief (US_IDR) LIN Checksum Error Interrupt Disable */ +#define US_IDR_LINSNRE (0x1u << 29) /**< \brief (US_IDR) LIN Slave Not Responding Error Interrupt Disable */ +#define US_IDR_LINSTE (0x1u << 30) /**< \brief (US_IDR) LIN Synch Tolerance Error Interrupt Disable */ +#define US_IDR_LINHTE (0x1u << 31) /**< \brief (US_IDR) LIN Header Timeout Error Interrupt Disable */ +#define US_IDR_LSFE (0x1u << 6) /**< \brief (US_IDR) LON Short Frame Error Interrupt Disable */ +#define US_IDR_LCRCE (0x1u << 7) /**< \brief (US_IDR) LON CRC Error Interrupt Disable */ +#define US_IDR_LTXD (0x1u << 24) /**< \brief (US_IDR) LON Transmission Done Interrupt Disable */ +#define US_IDR_LCOL (0x1u << 25) /**< \brief (US_IDR) LON Collision Interrupt Disable */ +#define US_IDR_LFET (0x1u << 26) /**< \brief (US_IDR) LON Frame Early Termination Interrupt Disable */ +#define US_IDR_LRXD (0x1u << 27) /**< \brief (US_IDR) LON Reception Done Interrupt Disable */ +#define US_IDR_LBLOVFE (0x1u << 28) /**< \brief (US_IDR) LON Backlog Overflow Error Interrupt Disable */ +/* -------- US_IMR : (USART Offset: 0x0010) Interrupt Mask Register -------- */ +#define US_IMR_RXRDY (0x1u << 0) /**< \brief (US_IMR) RXRDY Interrupt Mask */ +#define US_IMR_TXRDY (0x1u << 1) /**< \brief (US_IMR) TXRDY Interrupt Mask */ +#define US_IMR_RXBRK (0x1u << 2) /**< \brief (US_IMR) Receiver Break Interrupt Mask */ +#define US_IMR_OVRE (0x1u << 5) /**< \brief (US_IMR) Overrun Error Interrupt Mask */ +#define US_IMR_FRAME (0x1u << 6) /**< \brief (US_IMR) Framing Error Interrupt Mask */ +#define US_IMR_PARE (0x1u << 7) /**< \brief (US_IMR) Parity Error Interrupt Mask */ +#define US_IMR_TIMEOUT (0x1u << 8) /**< \brief (US_IMR) Time-out Interrupt Mask */ +#define US_IMR_TXEMPTY (0x1u << 9) /**< \brief (US_IMR) TXEMPTY Interrupt Mask */ +#define US_IMR_CTSIC (0x1u << 19) /**< \brief (US_IMR) Clear to Send Input Change Interrupt Mask */ +#define US_IMR_MANE (0x1u << 24) /**< \brief (US_IMR) Manchester Error Interrupt Mask */ +#define US_IMR_UNRE (0x1u << 10) /**< \brief (US_IMR) SPI Underrun Error Interrupt Mask */ +#define US_IMR_LINBK (0x1u << 13) /**< \brief (US_IMR) LIN Break Sent or LIN Break Received Interrupt Mask */ +#define US_IMR_LINID (0x1u << 14) /**< \brief (US_IMR) LIN Identifier Sent or LIN Identifier Received Interrupt Mask */ +#define US_IMR_LINTC (0x1u << 15) /**< \brief (US_IMR) LIN Transfer Completed Interrupt Mask */ +#define US_IMR_LINBE (0x1u << 25) /**< \brief (US_IMR) LIN Bus Error Interrupt Mask */ +#define US_IMR_LINISFE (0x1u << 26) /**< \brief (US_IMR) LIN Inconsistent Synch Field Error Interrupt Mask */ +#define US_IMR_LINIPE (0x1u << 27) /**< \brief (US_IMR) LIN Identifier Parity Interrupt Mask */ +#define US_IMR_LINCE (0x1u << 28) /**< \brief (US_IMR) LIN Checksum Error Interrupt Mask */ +#define US_IMR_LINSNRE (0x1u << 29) /**< \brief (US_IMR) LIN Slave Not Responding Error Interrupt Mask */ +#define US_IMR_LINSTE (0x1u << 30) /**< \brief (US_IMR) LIN Synch Tolerance Error Interrupt Mask */ +#define US_IMR_LINHTE (0x1u << 31) /**< \brief (US_IMR) LIN Header Timeout Error Interrupt Mask */ +#define US_IMR_LSFE (0x1u << 6) /**< \brief (US_IMR) LON Short Frame Error Interrupt Mask */ +#define US_IMR_LCRCE (0x1u << 7) /**< \brief (US_IMR) LON CRC Error Interrupt Mask */ +#define US_IMR_LTXD (0x1u << 24) /**< \brief (US_IMR) LON Transmission Done Interrupt Mask */ +#define US_IMR_LCOL (0x1u << 25) /**< \brief (US_IMR) LON Collision Interrupt Mask */ +#define US_IMR_LFET (0x1u << 26) /**< \brief (US_IMR) LON Frame Early Termination Interrupt Mask */ +#define US_IMR_LRXD (0x1u << 27) /**< \brief (US_IMR) LON Reception Done Interrupt Mask */ +#define US_IMR_LBLOVFE (0x1u << 28) /**< \brief (US_IMR) LON Backlog Overflow Error Interrupt Mask */ +/* -------- US_CSR : (USART Offset: 0x0014) Channel Status Register -------- */ +#define US_CSR_RXRDY (0x1u << 0) /**< \brief (US_CSR) Receiver Ready (cleared by reading US_RHR) */ +#define US_CSR_TXRDY (0x1u << 1) /**< \brief (US_CSR) Transmitter Ready (cleared by writing US_THR) */ +#define US_CSR_RXBRK (0x1u << 2) /**< \brief (US_CSR) Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_OVRE (0x1u << 5) /**< \brief (US_CSR) Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_FRAME (0x1u << 6) /**< \brief (US_CSR) Framing Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_PARE (0x1u << 7) /**< \brief (US_CSR) Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_TIMEOUT (0x1u << 8) /**< \brief (US_CSR) Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) */ +#define US_CSR_TXEMPTY (0x1u << 9) /**< \brief (US_CSR) Transmitter Empty (cleared by writing US_THR) */ +#define US_CSR_NACK (0x1u << 13) /**< \brief (US_CSR) Non AcknowledgeInterrupt */ +#define US_CSR_CTSIC (0x1u << 19) /**< \brief (US_CSR) Clear to Send Input Change Flag (cleared on read) */ +#define US_CSR_CTS (0x1u << 23) /**< \brief (US_CSR) Image of CTS Input */ +#define US_CSR_MANERR (0x1u << 24) /**< \brief (US_CSR) Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) */ +#define US_CSR_UNRE (0x1u << 10) /**< \brief (US_CSR) Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBK (0x1u << 13) /**< \brief (US_CSR) LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINID (0x1u << 14) /**< \brief (US_CSR) LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINTC (0x1u << 15) /**< \brief (US_CSR) LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINBLS (0x1u << 23) /**< \brief (US_CSR) LIN Bus Line Status */ +#define US_CSR_LINBE (0x1u << 25) /**< \brief (US_CSR) LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINISFE (0x1u << 26) /**< \brief (US_CSR) LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINIPE (0x1u << 27) /**< \brief (US_CSR) LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINCE (0x1u << 28) /**< \brief (US_CSR) LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSNRE (0x1u << 29) /**< \brief (US_CSR) LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINSTE (0x1u << 30) /**< \brief (US_CSR) LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LINHTE (0x1u << 31) /**< \brief (US_CSR) LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LSFE (0x1u << 6) /**< \brief (US_CSR) LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCRCE (0x1u << 7) /**< \brief (US_CSR) LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LTXD (0x1u << 24) /**< \brief (US_CSR) LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LCOL (0x1u << 25) /**< \brief (US_CSR) LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LFET (0x1u << 26) /**< \brief (US_CSR) LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LRXD (0x1u << 27) /**< \brief (US_CSR) LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) */ +#define US_CSR_LBLOVFE (0x1u << 28) /**< \brief (US_CSR) LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) */ +/* -------- US_RHR : (USART Offset: 0x0018) Receive Holding Register -------- */ +#define US_RHR_RXCHR_Pos 0 +#define US_RHR_RXCHR_Msk (0x1ffu << US_RHR_RXCHR_Pos) /**< \brief (US_RHR) Received Character */ +#define US_RHR_RXSYNH (0x1u << 15) /**< \brief (US_RHR) Received Sync */ +/* -------- US_THR : (USART Offset: 0x001C) Transmit Holding Register -------- */ +#define US_THR_TXCHR_Pos 0 +#define US_THR_TXCHR_Msk (0x1ffu << US_THR_TXCHR_Pos) /**< \brief (US_THR) Character to be Transmitted */ +#define US_THR_TXCHR(value) ((US_THR_TXCHR_Msk & ((value) << US_THR_TXCHR_Pos))) +#define US_THR_TXSYNH (0x1u << 15) /**< \brief (US_THR) Sync Field to be Transmitted */ +/* -------- US_BRGR : (USART Offset: 0x0020) Baud Rate Generator Register -------- */ +#define US_BRGR_CD_Pos 0 +#define US_BRGR_CD_Msk (0xffffu << US_BRGR_CD_Pos) /**< \brief (US_BRGR) Clock Divider */ +#define US_BRGR_CD(value) ((US_BRGR_CD_Msk & ((value) << US_BRGR_CD_Pos))) +#define US_BRGR_FP_Pos 16 +#define US_BRGR_FP_Msk (0x7u << US_BRGR_FP_Pos) /**< \brief (US_BRGR) Fractional Part */ +#define US_BRGR_FP(value) ((US_BRGR_FP_Msk & ((value) << US_BRGR_FP_Pos))) +/* -------- US_RTOR : (USART Offset: 0x0024) Receiver Time-out Register -------- */ +#define US_RTOR_TO_Pos 0 +#define US_RTOR_TO_Msk (0x1ffffu << US_RTOR_TO_Pos) /**< \brief (US_RTOR) Time-out Value */ +#define US_RTOR_TO(value) ((US_RTOR_TO_Msk & ((value) << US_RTOR_TO_Pos))) +/* -------- US_TTGR : (USART Offset: 0x0028) Transmitter Timeguard Register -------- */ +#define US_TTGR_TG_Pos 0 +#define US_TTGR_TG_Msk (0xffu << US_TTGR_TG_Pos) /**< \brief (US_TTGR) Timeguard Value */ +#define US_TTGR_TG(value) ((US_TTGR_TG_Msk & ((value) << US_TTGR_TG_Pos))) +#define US_TTGR_PCYCLE_Pos 0 +#define US_TTGR_PCYCLE_Msk (0xffffffu << US_TTGR_PCYCLE_Pos) /**< \brief (US_TTGR) LON PCYCLE Length */ +#define US_TTGR_PCYCLE(value) ((US_TTGR_PCYCLE_Msk & ((value) << US_TTGR_PCYCLE_Pos))) +/* -------- US_MAN : (USART Offset: 0x0050) Manchester Configuration Register -------- */ +#define US_MAN_TX_PL_Pos 0 +#define US_MAN_TX_PL_Msk (0xfu << US_MAN_TX_PL_Pos) /**< \brief (US_MAN) Transmitter Preamble Length */ +#define US_MAN_TX_PL(value) ((US_MAN_TX_PL_Msk & ((value) << US_MAN_TX_PL_Pos))) +#define US_MAN_TX_PP_Pos 8 +#define US_MAN_TX_PP_Msk (0x3u << US_MAN_TX_PP_Pos) /**< \brief (US_MAN) Transmitter Preamble Pattern */ +#define US_MAN_TX_PP(value) ((US_MAN_TX_PP_Msk & ((value) << US_MAN_TX_PP_Pos))) +#define US_MAN_TX_PP_ALL_ONE (0x0u << 8) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_TX_PP_ALL_ZERO (0x1u << 8) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_TX_PP_ZERO_ONE (0x2u << 8) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_TX_PP_ONE_ZERO (0x3u << 8) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_TX_MPOL (0x1u << 12) /**< \brief (US_MAN) Transmitter Manchester Polarity */ +#define US_MAN_RX_PL_Pos 16 +#define US_MAN_RX_PL_Msk (0xfu << US_MAN_RX_PL_Pos) /**< \brief (US_MAN) Receiver Preamble Length */ +#define US_MAN_RX_PL(value) ((US_MAN_RX_PL_Msk & ((value) << US_MAN_RX_PL_Pos))) +#define US_MAN_RX_PP_Pos 24 +#define US_MAN_RX_PP_Msk (0x3u << US_MAN_RX_PP_Pos) /**< \brief (US_MAN) Receiver Preamble Pattern detected */ +#define US_MAN_RX_PP(value) ((US_MAN_RX_PP_Msk & ((value) << US_MAN_RX_PP_Pos))) +#define US_MAN_RX_PP_ALL_ONE (0x0u << 24) /**< \brief (US_MAN) The preamble is composed of '1's */ +#define US_MAN_RX_PP_ALL_ZERO (0x1u << 24) /**< \brief (US_MAN) The preamble is composed of '0's */ +#define US_MAN_RX_PP_ZERO_ONE (0x2u << 24) /**< \brief (US_MAN) The preamble is composed of '01's */ +#define US_MAN_RX_PP_ONE_ZERO (0x3u << 24) /**< \brief (US_MAN) The preamble is composed of '10's */ +#define US_MAN_RX_MPOL (0x1u << 28) /**< \brief (US_MAN) Receiver Manchester Polarity */ +#define US_MAN_ONE (0x1u << 29) /**< \brief (US_MAN) Must Be Set to 1 */ +#define US_MAN_DRIFT (0x1u << 30) /**< \brief (US_MAN) Drift Compensation */ +#define US_MAN_RXIDLEV (0x1u << 31) /**< \brief (US_MAN) */ +/* -------- US_LINMR : (USART Offset: 0x0054) LIN Mode Register -------- */ +#define US_LINMR_NACT_Pos 0 +#define US_LINMR_NACT_Msk (0x3u << US_LINMR_NACT_Pos) /**< \brief (US_LINMR) LIN Node Action */ +#define US_LINMR_NACT(value) ((US_LINMR_NACT_Msk & ((value) << US_LINMR_NACT_Pos))) +#define US_LINMR_NACT_PUBLISH (0x0u << 0) /**< \brief (US_LINMR) The USART transmits the response. */ +#define US_LINMR_NACT_SUBSCRIBE (0x1u << 0) /**< \brief (US_LINMR) The USART receives the response. */ +#define US_LINMR_NACT_IGNORE (0x2u << 0) /**< \brief (US_LINMR) The USART does not transmit and does not receive the response. */ +#define US_LINMR_PARDIS (0x1u << 2) /**< \brief (US_LINMR) Parity Disable */ +#define US_LINMR_CHKDIS (0x1u << 3) /**< \brief (US_LINMR) Checksum Disable */ +#define US_LINMR_CHKTYP (0x1u << 4) /**< \brief (US_LINMR) Checksum Type */ +#define US_LINMR_DLM (0x1u << 5) /**< \brief (US_LINMR) Data Length Mode */ +#define US_LINMR_FSDIS (0x1u << 6) /**< \brief (US_LINMR) Frame Slot Mode Disable */ +#define US_LINMR_WKUPTYP (0x1u << 7) /**< \brief (US_LINMR) Wakeup Signal Type */ +#define US_LINMR_DLC_Pos 8 +#define US_LINMR_DLC_Msk (0xffu << US_LINMR_DLC_Pos) /**< \brief (US_LINMR) Data Length Control */ +#define US_LINMR_DLC(value) ((US_LINMR_DLC_Msk & ((value) << US_LINMR_DLC_Pos))) +#define US_LINMR_PDCM (0x1u << 16) /**< \brief (US_LINMR) DMAC Mode */ +#define US_LINMR_SYNCDIS (0x1u << 17) /**< \brief (US_LINMR) Synchronization Disable */ +/* -------- US_LINIR : (USART Offset: 0x0058) LIN Identifier Register -------- */ +#define US_LINIR_IDCHR_Pos 0 +#define US_LINIR_IDCHR_Msk (0xffu << US_LINIR_IDCHR_Pos) /**< \brief (US_LINIR) Identifier Character */ +#define US_LINIR_IDCHR(value) ((US_LINIR_IDCHR_Msk & ((value) << US_LINIR_IDCHR_Pos))) +/* -------- US_LINBRR : (USART Offset: 0x005C) LIN Baud Rate Register -------- */ +#define US_LINBRR_LINCD_Pos 0 +#define US_LINBRR_LINCD_Msk (0xffffu << US_LINBRR_LINCD_Pos) /**< \brief (US_LINBRR) Clock Divider after Synchronization */ +#define US_LINBRR_LINFP_Pos 16 +#define US_LINBRR_LINFP_Msk (0x7u << US_LINBRR_LINFP_Pos) /**< \brief (US_LINBRR) Fractional Part after Synchronization */ +/* -------- US_LONMR : (USART Offset: 0x0060) LON Mode Register -------- */ +#define US_LONMR_COMMT (0x1u << 0) /**< \brief (US_LONMR) LON comm_type Parameter Value */ +#define US_LONMR_COLDET (0x1u << 1) /**< \brief (US_LONMR) LON Collision Detection Feature */ +#define US_LONMR_TCOL (0x1u << 2) /**< \brief (US_LONMR) Terminate Frame upon Collision Notification */ +#define US_LONMR_CDTAIL (0x1u << 3) /**< \brief (US_LONMR) LON Collision Detection on Frame Tail */ +#define US_LONMR_DMAM (0x1u << 4) /**< \brief (US_LONMR) LON DMA Mode */ +#define US_LONMR_LCDS (0x1u << 5) /**< \brief (US_LONMR) LON Collision Detection Source */ +#define US_LONMR_EOFS_Pos 16 +#define US_LONMR_EOFS_Msk (0xffu << US_LONMR_EOFS_Pos) /**< \brief (US_LONMR) End of Frame Condition Size */ +#define US_LONMR_EOFS(value) ((US_LONMR_EOFS_Msk & ((value) << US_LONMR_EOFS_Pos))) +/* -------- US_LONPR : (USART Offset: 0x0064) LON Preamble Register -------- */ +#define US_LONPR_LONPL_Pos 0 +#define US_LONPR_LONPL_Msk (0x3fffu << US_LONPR_LONPL_Pos) /**< \brief (US_LONPR) LON Preamble Length */ +#define US_LONPR_LONPL(value) ((US_LONPR_LONPL_Msk & ((value) << US_LONPR_LONPL_Pos))) +/* -------- US_LONDL : (USART Offset: 0x0068) LON Data Length Register -------- */ +#define US_LONDL_LONDL_Pos 0 +#define US_LONDL_LONDL_Msk (0xffu << US_LONDL_LONDL_Pos) /**< \brief (US_LONDL) LON Data Length */ +#define US_LONDL_LONDL(value) ((US_LONDL_LONDL_Msk & ((value) << US_LONDL_LONDL_Pos))) +/* -------- US_LONL2HDR : (USART Offset: 0x006C) LON L2HDR Register -------- */ +#define US_LONL2HDR_BLI_Pos 0 +#define US_LONL2HDR_BLI_Msk (0x3fu << US_LONL2HDR_BLI_Pos) /**< \brief (US_LONL2HDR) LON Backlog Increment */ +#define US_LONL2HDR_BLI(value) ((US_LONL2HDR_BLI_Msk & ((value) << US_LONL2HDR_BLI_Pos))) +#define US_LONL2HDR_ALTP (0x1u << 6) /**< \brief (US_LONL2HDR) LON Alternate Path Bit */ +#define US_LONL2HDR_PB (0x1u << 7) /**< \brief (US_LONL2HDR) LON Priority Bit */ +/* -------- US_LONBL : (USART Offset: 0x0070) LON Backlog Register -------- */ +#define US_LONBL_LONBL_Pos 0 +#define US_LONBL_LONBL_Msk (0x3fu << US_LONBL_LONBL_Pos) /**< \brief (US_LONBL) LON Node Backlog Value */ +/* -------- US_LONB1TX : (USART Offset: 0x0074) LON Beta1 Tx Register -------- */ +#define US_LONB1TX_BETA1TX_Pos 0 +#define US_LONB1TX_BETA1TX_Msk (0xffffffu << US_LONB1TX_BETA1TX_Pos) /**< \brief (US_LONB1TX) LON Beta1 Length after Transmission */ +#define US_LONB1TX_BETA1TX(value) ((US_LONB1TX_BETA1TX_Msk & ((value) << US_LONB1TX_BETA1TX_Pos))) +/* -------- US_LONB1RX : (USART Offset: 0x0078) LON Beta1 Rx Register -------- */ +#define US_LONB1RX_BETA1RX_Pos 0 +#define US_LONB1RX_BETA1RX_Msk (0xffffffu << US_LONB1RX_BETA1RX_Pos) /**< \brief (US_LONB1RX) LON Beta1 Length after Reception */ +#define US_LONB1RX_BETA1RX(value) ((US_LONB1RX_BETA1RX_Msk & ((value) << US_LONB1RX_BETA1RX_Pos))) +/* -------- US_LONPRIO : (USART Offset: 0x007C) LON Priority Register -------- */ +#define US_LONPRIO_PSNB_Pos 0 +#define US_LONPRIO_PSNB_Msk (0x7fu << US_LONPRIO_PSNB_Pos) /**< \brief (US_LONPRIO) LON Priority Slot Number */ +#define US_LONPRIO_PSNB(value) ((US_LONPRIO_PSNB_Msk & ((value) << US_LONPRIO_PSNB_Pos))) +#define US_LONPRIO_NPS_Pos 8 +#define US_LONPRIO_NPS_Msk (0x7fu << US_LONPRIO_NPS_Pos) /**< \brief (US_LONPRIO) LON Node Priority Slot */ +#define US_LONPRIO_NPS(value) ((US_LONPRIO_NPS_Msk & ((value) << US_LONPRIO_NPS_Pos))) +/* -------- US_IDTTX : (USART Offset: 0x0080) LON IDT Tx Register -------- */ +#define US_IDTTX_IDTTX_Pos 0 +#define US_IDTTX_IDTTX_Msk (0xffffffu << US_IDTTX_IDTTX_Pos) /**< \brief (US_IDTTX) LON Indeterminate Time after Transmission (comm_type = 1 mode only) */ +#define US_IDTTX_IDTTX(value) ((US_IDTTX_IDTTX_Msk & ((value) << US_IDTTX_IDTTX_Pos))) +/* -------- US_IDTRX : (USART Offset: 0x0084) LON IDT Rx Register -------- */ +#define US_IDTRX_IDTRX_Pos 0 +#define US_IDTRX_IDTRX_Msk (0xffffffu << US_IDTRX_IDTRX_Pos) /**< \brief (US_IDTRX) LON Indeterminate Time after Reception (comm_type = 1 mode only) */ +#define US_IDTRX_IDTRX(value) ((US_IDTRX_IDTRX_Msk & ((value) << US_IDTRX_IDTRX_Pos))) +/* -------- US_ICDIFF : (USART Offset: 0x0088) IC DIFF Register -------- */ +#define US_ICDIFF_ICDIFF_Pos 0 +#define US_ICDIFF_ICDIFF_Msk (0xfu << US_ICDIFF_ICDIFF_Pos) /**< \brief (US_ICDIFF) IC Differentiator Number */ +#define US_ICDIFF_ICDIFF(value) ((US_ICDIFF_ICDIFF_Msk & ((value) << US_ICDIFF_ICDIFF_Pos))) +/* -------- US_WPMR : (USART Offset: 0x00E4) Write Protection Mode Register -------- */ +#define US_WPMR_WPEN (0x1u << 0) /**< \brief (US_WPMR) Write Protection Enable */ +#define US_WPMR_WPKEY_Pos 8 +#define US_WPMR_WPKEY_Msk (0xffffffu << US_WPMR_WPKEY_Pos) /**< \brief (US_WPMR) Write Protection Key */ +#define US_WPMR_WPKEY(value) ((US_WPMR_WPKEY_Msk & ((value) << US_WPMR_WPKEY_Pos))) +#define US_WPMR_WPKEY_PASSWD (0x555341u << 8) /**< \brief (US_WPMR) Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. */ +/* -------- US_WPSR : (USART Offset: 0x00E8) Write Protection Status Register -------- */ +#define US_WPSR_WPVS (0x1u << 0) /**< \brief (US_WPSR) Write Protection Violation Status */ +#define US_WPSR_WPVSRC_Pos 8 +#define US_WPSR_WPVSRC_Msk (0xffffu << US_WPSR_WPVSRC_Pos) /**< \brief (US_WPSR) Write Protection Violation Source */ + +/*@}*/ + + +#endif /* _SAMV71_USART_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_usbhs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_usbhs.h new file mode 100644 index 000000000..3a7505eda --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_usbhs.h @@ -0,0 +1,960 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USBHS_COMPONENT_ +#define _SAMV71_USBHS_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB High-Speed Interface */ +/* ============================================================================= */ +/** \addtogroup SAMV71_USBHS USB High-Speed Interface */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief UsbhsDevdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_DEVDMANXTDSC; /**< \brief (UsbhsDevdma Offset: 0x0) Device DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_DEVDMAADDRESS; /**< \brief (UsbhsDevdma Offset: 0x4) Device DMA Channel Address Register */ + __IO uint32_t USBHS_DEVDMACONTROL; /**< \brief (UsbhsDevdma Offset: 0x8) Device DMA Channel Control Register */ + __IO uint32_t USBHS_DEVDMASTATUS; /**< \brief (UsbhsDevdma Offset: 0xC) Device DMA Channel Status Register */ +} UsbhsDevdma; +/** \brief UsbhsHstdma hardware registers */ +typedef struct { + __IO uint32_t USBHS_HSTDMANXTDSC; /**< \brief (UsbhsHstdma Offset: 0x0) Host DMA Channel Next Descriptor Address Register */ + __IO uint32_t USBHS_HSTDMAADDRESS; /**< \brief (UsbhsHstdma Offset: 0x4) Host DMA Channel Address Register */ + __IO uint32_t USBHS_HSTDMACONTROL; /**< \brief (UsbhsHstdma Offset: 0x8) Host DMA Channel Control Register */ + __IO uint32_t USBHS_HSTDMASTATUS; /**< \brief (UsbhsHstdma Offset: 0xC) Host DMA Channel Status Register */ +} UsbhsHstdma; +/** \brief Usbhs hardware registers */ +#define USBHSDEVDMA_NUMBER 7 +#define USBHSHSTDMA_NUMBER 7 +typedef struct { + __IO uint32_t USBHS_DEVCTRL; /**< \brief (Usbhs Offset: 0x0000) Device General Control Register */ + __I uint32_t USBHS_DEVISR; /**< \brief (Usbhs Offset: 0x0004) Device Global Interrupt Status Register */ + __O uint32_t USBHS_DEVICR; /**< \brief (Usbhs Offset: 0x0008) Device Global Interrupt Clear Register */ + __O uint32_t USBHS_DEVIFR; /**< \brief (Usbhs Offset: 0x000C) Device Global Interrupt Set Register */ + __I uint32_t USBHS_DEVIMR; /**< \brief (Usbhs Offset: 0x0010) Device Global Interrupt Mask Register */ + __O uint32_t USBHS_DEVIDR; /**< \brief (Usbhs Offset: 0x0014) Device Global Interrupt Disable Register */ + __O uint32_t USBHS_DEVIER; /**< \brief (Usbhs Offset: 0x0018) Device Global Interrupt Enable Register */ + __IO uint32_t USBHS_DEVEPT; /**< \brief (Usbhs Offset: 0x001C) Device Endpoint Register */ + __I uint32_t USBHS_DEVFNUM; /**< \brief (Usbhs Offset: 0x0020) Device Frame Number Register */ + __I uint32_t Reserved1[55]; + __IO uint32_t USBHS_DEVEPTCFG[10]; /**< \brief (Usbhs Offset: 0x100) Device Endpoint Configuration Register (n = 0) */ + __I uint32_t Reserved2[2]; + __I uint32_t USBHS_DEVEPTISR[10]; /**< \brief (Usbhs Offset: 0x130) Device Endpoint Status Register (n = 0) */ + __I uint32_t Reserved3[2]; + __O uint32_t USBHS_DEVEPTICR[10]; /**< \brief (Usbhs Offset: 0x160) Device Endpoint Clear Register (n = 0) */ + __I uint32_t Reserved4[2]; + __O uint32_t USBHS_DEVEPTIFR[10]; /**< \brief (Usbhs Offset: 0x190) Device Endpoint Set Register (n = 0) */ + __I uint32_t Reserved5[2]; + __I uint32_t USBHS_DEVEPTIMR[10]; /**< \brief (Usbhs Offset: 0x1C0) Device Endpoint Mask Register (n = 0) */ + __I uint32_t Reserved6[2]; + __O uint32_t USBHS_DEVEPTIER[10]; /**< \brief (Usbhs Offset: 0x1F0) Device Endpoint Enable Register (n = 0) */ + __I uint32_t Reserved7[2]; + __O uint32_t USBHS_DEVEPTIDR[10]; /**< \brief (Usbhs Offset: 0x220) Device Endpoint Disable Register (n = 0) */ + __I uint32_t Reserved8[50]; + UsbhsDevdma USBHS_DEVDMA[USBHSDEVDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x310) n = 1 .. 7 */ + __I uint32_t Reserved9[32]; + __IO uint32_t USBHS_HSTCTRL; /**< \brief (Usbhs Offset: 0x0400) Host General Control Register */ + __I uint32_t USBHS_HSTISR; /**< \brief (Usbhs Offset: 0x0404) Host Global Interrupt Status Register */ + __O uint32_t USBHS_HSTICR; /**< \brief (Usbhs Offset: 0x0408) Host Global Interrupt Clear Register */ + __O uint32_t USBHS_HSTIFR; /**< \brief (Usbhs Offset: 0x040C) Host Global Interrupt Set Register */ + __I uint32_t USBHS_HSTIMR; /**< \brief (Usbhs Offset: 0x0410) Host Global Interrupt Mask Register */ + __O uint32_t USBHS_HSTIDR; /**< \brief (Usbhs Offset: 0x0414) Host Global Interrupt Disable Register */ + __O uint32_t USBHS_HSTIER; /**< \brief (Usbhs Offset: 0x0418) Host Global Interrupt Enable Register */ + __IO uint32_t USBHS_HSTPIP; /**< \brief (Usbhs Offset: 0x0041C) Host Pipe Register */ + __IO uint32_t USBHS_HSTFNUM; /**< \brief (Usbhs Offset: 0x0420) Host Frame Number Register */ + __IO uint32_t USBHS_HSTADDR1; /**< \brief (Usbhs Offset: 0x0424) Host Address 1 Register */ + __IO uint32_t USBHS_HSTADDR2; /**< \brief (Usbhs Offset: 0x0428) Host Address 2 Register */ + __IO uint32_t USBHS_HSTADDR3; /**< \brief (Usbhs Offset: 0x042C) Host Address 3 Register */ + __I uint32_t Reserved10[52]; + __IO uint32_t USBHS_HSTPIPCFG[10]; /**< \brief (Usbhs Offset: 0x500) Host Pipe Configuration Register (n = 0) */ + __I uint32_t Reserved11[2]; + __I uint32_t USBHS_HSTPIPISR[10]; /**< \brief (Usbhs Offset: 0x530) Host Pipe Status Register (n = 0) */ + __I uint32_t Reserved12[2]; + __O uint32_t USBHS_HSTPIPICR[10]; /**< \brief (Usbhs Offset: 0x560) Host Pipe Clear Register (n = 0) */ + __I uint32_t Reserved13[2]; + __O uint32_t USBHS_HSTPIPIFR[10]; /**< \brief (Usbhs Offset: 0x590) Host Pipe Set Register (n = 0) */ + __I uint32_t Reserved14[2]; + __I uint32_t USBHS_HSTPIPIMR[10]; /**< \brief (Usbhs Offset: 0x5C0) Host Pipe Mask Register (n = 0) */ + __I uint32_t Reserved15[2]; + __O uint32_t USBHS_HSTPIPIER[10]; /**< \brief (Usbhs Offset: 0x5F0) Host Pipe Enable Register (n = 0) */ + __I uint32_t Reserved16[2]; + __O uint32_t USBHS_HSTPIPIDR[10]; /**< \brief (Usbhs Offset: 0x620) Host Pipe Disable Register (n = 0) */ + __I uint32_t Reserved17[2]; + __IO uint32_t USBHS_HSTPIPINRQ[10]; /**< \brief (Usbhs Offset: 0x650) Host Pipe IN Request Register (n = 0) */ + __I uint32_t Reserved18[2]; + __IO uint32_t USBHS_HSTPIPERR[10]; /**< \brief (Usbhs Offset: 0x680) Host Pipe Error Register (n = 0) */ + __I uint32_t Reserved19[26]; + UsbhsHstdma USBHS_HSTDMA[USBHSHSTDMA_NUMBER]; /**< \brief (Usbhs Offset: 0x710) n = 1 .. 7 */ + __I uint32_t Reserved20[32]; + __IO uint32_t USBHS_CTRL; /**< \brief (Usbhs Offset: 0x0800) General Control Register */ + __I uint32_t USBHS_SR; /**< \brief (Usbhs Offset: 0x0804) General Status Register */ + __O uint32_t USBHS_SCR; /**< \brief (Usbhs Offset: 0x0808) General Status Clear Register */ + __O uint32_t USBHS_SFR; /**< \brief (Usbhs Offset: 0x080C) General Status Set Register */ + __IO uint32_t USBHS_TSTA1; /**< \brief (Usbhs Offset: 0x0810) General Test A1 Register */ + __IO uint32_t USBHS_TSTA2; /**< \brief (Usbhs Offset: 0x0814) General Test A2 Register */ + __I uint32_t USBHS_VERSION; /**< \brief (Usbhs Offset: 0x0818) General Version Register */ + __I uint32_t Reserved21[4]; + __I uint32_t USBHS_FSM; /**< \brief (Usbhs Offset: 0x082C) General Finite State Machine Register */ +} Usbhs; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- USBHS_DEVCTRL : (USBHS Offset: 0x0000) Device General Control Register -------- */ +#define USBHS_DEVCTRL_UADD_Pos 0 +#define USBHS_DEVCTRL_UADD_Msk (0x7fu << USBHS_DEVCTRL_UADD_Pos) /**< \brief (USBHS_DEVCTRL) USB Address */ +#define USBHS_DEVCTRL_UADD(value) ((USBHS_DEVCTRL_UADD_Msk & ((value) << USBHS_DEVCTRL_UADD_Pos))) +#define USBHS_DEVCTRL_ADDEN (0x1u << 7) /**< \brief (USBHS_DEVCTRL) Address Enable */ +#define USBHS_DEVCTRL_DETACH (0x1u << 8) /**< \brief (USBHS_DEVCTRL) Detach */ +#define USBHS_DEVCTRL_RMWKUP (0x1u << 9) /**< \brief (USBHS_DEVCTRL) Remote Wake-Up */ +#define USBHS_DEVCTRL_SPDCONF_Pos 10 +#define USBHS_DEVCTRL_SPDCONF_Msk (0x3u << USBHS_DEVCTRL_SPDCONF_Pos) /**< \brief (USBHS_DEVCTRL) Mode Configuration */ +#define USBHS_DEVCTRL_SPDCONF(value) ((USBHS_DEVCTRL_SPDCONF_Msk & ((value) << USBHS_DEVCTRL_SPDCONF_Pos))) +#define USBHS_DEVCTRL_SPDCONF_NORMAL (0x0u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. */ +#define USBHS_DEVCTRL_SPDCONF_LOW_POWER (0x1u << 10) /**< \brief (USBHS_DEVCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_DEVCTRL_SPDCONF_HIGH_SPEED (0x2u << 10) /**< \brief (USBHS_DEVCTRL) Forced high speed. */ +#define USBHS_DEVCTRL_SPDCONF_FORCED_FS (0x3u << 10) /**< \brief (USBHS_DEVCTRL) The peripheral remains in Full-speed mode whatever the host speed capability. */ +#define USBHS_DEVCTRL_LS (0x1u << 12) /**< \brief (USBHS_DEVCTRL) Low-Speed Mode Force */ +#define USBHS_DEVCTRL_TSTJ (0x1u << 13) /**< \brief (USBHS_DEVCTRL) Test mode J */ +#define USBHS_DEVCTRL_TSTK (0x1u << 14) /**< \brief (USBHS_DEVCTRL) Test mode K */ +#define USBHS_DEVCTRL_TSTPCKT (0x1u << 15) /**< \brief (USBHS_DEVCTRL) Test packet mode */ +#define USBHS_DEVCTRL_OPMODE2 (0x1u << 16) /**< \brief (USBHS_DEVCTRL) Specific Operational mode */ +/* -------- USBHS_DEVISR : (USBHS Offset: 0x0004) Device Global Interrupt Status Register -------- */ +#define USBHS_DEVISR_SUSP (0x1u << 0) /**< \brief (USBHS_DEVISR) Suspend Interrupt */ +#define USBHS_DEVISR_MSOF (0x1u << 1) /**< \brief (USBHS_DEVISR) Micro Start of Frame Interrupt */ +#define USBHS_DEVISR_SOF (0x1u << 2) /**< \brief (USBHS_DEVISR) Start of Frame Interrupt */ +#define USBHS_DEVISR_EORST (0x1u << 3) /**< \brief (USBHS_DEVISR) End of Reset Interrupt */ +#define USBHS_DEVISR_WAKEUP (0x1u << 4) /**< \brief (USBHS_DEVISR) Wake-Up Interrupt */ +#define USBHS_DEVISR_EORSM (0x1u << 5) /**< \brief (USBHS_DEVISR) End of Resume Interrupt */ +#define USBHS_DEVISR_UPRSM (0x1u << 6) /**< \brief (USBHS_DEVISR) Upstream Resume Interrupt */ +#define USBHS_DEVISR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVISR) Endpoint 0 Interrupt */ +#define USBHS_DEVISR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVISR) Endpoint 1 Interrupt */ +#define USBHS_DEVISR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVISR) Endpoint 2 Interrupt */ +#define USBHS_DEVISR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVISR) Endpoint 3 Interrupt */ +#define USBHS_DEVISR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVISR) Endpoint 4 Interrupt */ +#define USBHS_DEVISR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVISR) Endpoint 5 Interrupt */ +#define USBHS_DEVISR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVISR) Endpoint 6 Interrupt */ +#define USBHS_DEVISR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVISR) Endpoint 7 Interrupt */ +#define USBHS_DEVISR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVISR) Endpoint 8 Interrupt */ +#define USBHS_DEVISR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVISR) Endpoint 9 Interrupt */ +#define USBHS_DEVISR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVISR) Endpoint 10 Interrupt */ +#define USBHS_DEVISR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVISR) Endpoint 11 Interrupt */ +#define USBHS_DEVISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVISR) DMA Channel 1 Interrupt */ +#define USBHS_DEVISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVISR) DMA Channel 2 Interrupt */ +#define USBHS_DEVISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVISR) DMA Channel 3 Interrupt */ +#define USBHS_DEVISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVISR) DMA Channel 4 Interrupt */ +#define USBHS_DEVISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVISR) DMA Channel 5 Interrupt */ +#define USBHS_DEVISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVISR) DMA Channel 6 Interrupt */ +#define USBHS_DEVISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_DEVICR : (USBHS Offset: 0x0008) Device Global Interrupt Clear Register -------- */ +#define USBHS_DEVICR_SUSPC (0x1u << 0) /**< \brief (USBHS_DEVICR) Suspend Interrupt Clear */ +#define USBHS_DEVICR_MSOFC (0x1u << 1) /**< \brief (USBHS_DEVICR) Micro Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_SOFC (0x1u << 2) /**< \brief (USBHS_DEVICR) Start of Frame Interrupt Clear */ +#define USBHS_DEVICR_EORSTC (0x1u << 3) /**< \brief (USBHS_DEVICR) End of Reset Interrupt Clear */ +#define USBHS_DEVICR_WAKEUPC (0x1u << 4) /**< \brief (USBHS_DEVICR) Wake-Up Interrupt Clear */ +#define USBHS_DEVICR_EORSMC (0x1u << 5) /**< \brief (USBHS_DEVICR) End of Resume Interrupt Clear */ +#define USBHS_DEVICR_UPRSMC (0x1u << 6) /**< \brief (USBHS_DEVICR) Upstream Resume Interrupt Clear */ +/* -------- USBHS_DEVIFR : (USBHS Offset: 0x000C) Device Global Interrupt Set Register -------- */ +#define USBHS_DEVIFR_SUSPS (0x1u << 0) /**< \brief (USBHS_DEVIFR) Suspend Interrupt Set */ +#define USBHS_DEVIFR_MSOFS (0x1u << 1) /**< \brief (USBHS_DEVIFR) Micro Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_SOFS (0x1u << 2) /**< \brief (USBHS_DEVIFR) Start of Frame Interrupt Set */ +#define USBHS_DEVIFR_EORSTS (0x1u << 3) /**< \brief (USBHS_DEVIFR) End of Reset Interrupt Set */ +#define USBHS_DEVIFR_WAKEUPS (0x1u << 4) /**< \brief (USBHS_DEVIFR) Wake-Up Interrupt Set */ +#define USBHS_DEVIFR_EORSMS (0x1u << 5) /**< \brief (USBHS_DEVIFR) End of Resume Interrupt Set */ +#define USBHS_DEVIFR_UPRSMS (0x1u << 6) /**< \brief (USBHS_DEVIFR) Upstream Resume Interrupt Set */ +#define USBHS_DEVIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_DEVIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_DEVIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_DEVIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_DEVIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_DEVIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_DEVIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_DEVIMR : (USBHS Offset: 0x0010) Device Global Interrupt Mask Register -------- */ +#define USBHS_DEVIMR_SUSPE (0x1u << 0) /**< \brief (USBHS_DEVIMR) Suspend Interrupt Mask */ +#define USBHS_DEVIMR_MSOFE (0x1u << 1) /**< \brief (USBHS_DEVIMR) Micro Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_SOFE (0x1u << 2) /**< \brief (USBHS_DEVIMR) Start of Frame Interrupt Mask */ +#define USBHS_DEVIMR_EORSTE (0x1u << 3) /**< \brief (USBHS_DEVIMR) End of Reset Interrupt Mask */ +#define USBHS_DEVIMR_WAKEUPE (0x1u << 4) /**< \brief (USBHS_DEVIMR) Wake-Up Interrupt Mask */ +#define USBHS_DEVIMR_EORSME (0x1u << 5) /**< \brief (USBHS_DEVIMR) End of Resume Interrupt Mask */ +#define USBHS_DEVIMR_UPRSME (0x1u << 6) /**< \brief (USBHS_DEVIMR) Upstream Resume Interrupt Mask */ +#define USBHS_DEVIMR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIMR) Endpoint 0 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIMR) Endpoint 1 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIMR) Endpoint 2 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIMR) Endpoint 3 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIMR) Endpoint 4 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIMR) Endpoint 5 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIMR) Endpoint 6 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIMR) Endpoint 7 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIMR) Endpoint 8 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIMR) Endpoint 9 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIMR) Endpoint 10 Interrupt Mask */ +#define USBHS_DEVIMR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIMR) Endpoint 11 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIMR) DMA Channel 1 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIMR) DMA Channel 2 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIMR) DMA Channel 3 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIMR) DMA Channel 4 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIMR) DMA Channel 5 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIMR) DMA Channel 6 Interrupt Mask */ +#define USBHS_DEVIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIMR) DMA Channel 7 Interrupt Mask */ +/* -------- USBHS_DEVIDR : (USBHS Offset: 0x0014) Device Global Interrupt Disable Register -------- */ +#define USBHS_DEVIDR_SUSPEC (0x1u << 0) /**< \brief (USBHS_DEVIDR) Suspend Interrupt Disable */ +#define USBHS_DEVIDR_MSOFEC (0x1u << 1) /**< \brief (USBHS_DEVIDR) Micro Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_SOFEC (0x1u << 2) /**< \brief (USBHS_DEVIDR) Start of Frame Interrupt Disable */ +#define USBHS_DEVIDR_EORSTEC (0x1u << 3) /**< \brief (USBHS_DEVIDR) End of Reset Interrupt Disable */ +#define USBHS_DEVIDR_WAKEUPEC (0x1u << 4) /**< \brief (USBHS_DEVIDR) Wake-Up Interrupt Disable */ +#define USBHS_DEVIDR_EORSMEC (0x1u << 5) /**< \brief (USBHS_DEVIDR) End of Resume Interrupt Disable */ +#define USBHS_DEVIDR_UPRSMEC (0x1u << 6) /**< \brief (USBHS_DEVIDR) Upstream Resume Interrupt Disable */ +#define USBHS_DEVIDR_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIDR) Endpoint 0 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIDR) Endpoint 1 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIDR) Endpoint 2 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIDR) Endpoint 3 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIDR) Endpoint 4 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIDR) Endpoint 5 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIDR) Endpoint 6 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIDR) Endpoint 7 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIDR) Endpoint 8 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIDR) Endpoint 9 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIDR) Endpoint 10 Interrupt Disable */ +#define USBHS_DEVIDR_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIDR) Endpoint 11 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_DEVIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_DEVIER : (USBHS Offset: 0x0018) Device Global Interrupt Enable Register -------- */ +#define USBHS_DEVIER_SUSPES (0x1u << 0) /**< \brief (USBHS_DEVIER) Suspend Interrupt Enable */ +#define USBHS_DEVIER_MSOFES (0x1u << 1) /**< \brief (USBHS_DEVIER) Micro Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_SOFES (0x1u << 2) /**< \brief (USBHS_DEVIER) Start of Frame Interrupt Enable */ +#define USBHS_DEVIER_EORSTES (0x1u << 3) /**< \brief (USBHS_DEVIER) End of Reset Interrupt Enable */ +#define USBHS_DEVIER_WAKEUPES (0x1u << 4) /**< \brief (USBHS_DEVIER) Wake-Up Interrupt Enable */ +#define USBHS_DEVIER_EORSMES (0x1u << 5) /**< \brief (USBHS_DEVIER) End of Resume Interrupt Enable */ +#define USBHS_DEVIER_UPRSMES (0x1u << 6) /**< \brief (USBHS_DEVIER) Upstream Resume Interrupt Enable */ +#define USBHS_DEVIER_PEP_0 (0x1u << 12) /**< \brief (USBHS_DEVIER) Endpoint 0 Interrupt Enable */ +#define USBHS_DEVIER_PEP_1 (0x1u << 13) /**< \brief (USBHS_DEVIER) Endpoint 1 Interrupt Enable */ +#define USBHS_DEVIER_PEP_2 (0x1u << 14) /**< \brief (USBHS_DEVIER) Endpoint 2 Interrupt Enable */ +#define USBHS_DEVIER_PEP_3 (0x1u << 15) /**< \brief (USBHS_DEVIER) Endpoint 3 Interrupt Enable */ +#define USBHS_DEVIER_PEP_4 (0x1u << 16) /**< \brief (USBHS_DEVIER) Endpoint 4 Interrupt Enable */ +#define USBHS_DEVIER_PEP_5 (0x1u << 17) /**< \brief (USBHS_DEVIER) Endpoint 5 Interrupt Enable */ +#define USBHS_DEVIER_PEP_6 (0x1u << 18) /**< \brief (USBHS_DEVIER) Endpoint 6 Interrupt Enable */ +#define USBHS_DEVIER_PEP_7 (0x1u << 19) /**< \brief (USBHS_DEVIER) Endpoint 7 Interrupt Enable */ +#define USBHS_DEVIER_PEP_8 (0x1u << 20) /**< \brief (USBHS_DEVIER) Endpoint 8 Interrupt Enable */ +#define USBHS_DEVIER_PEP_9 (0x1u << 21) /**< \brief (USBHS_DEVIER) Endpoint 9 Interrupt Enable */ +#define USBHS_DEVIER_PEP_10 (0x1u << 22) /**< \brief (USBHS_DEVIER) Endpoint 10 Interrupt Enable */ +#define USBHS_DEVIER_PEP_11 (0x1u << 23) /**< \brief (USBHS_DEVIER) Endpoint 11 Interrupt Enable */ +#define USBHS_DEVIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_DEVIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_DEVIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_DEVIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_DEVIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_DEVIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_DEVIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_DEVIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_DEVIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_DEVIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_DEVIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_DEVIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_DEVIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_DEVIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_DEVEPT : (USBHS Offset: 0x001C) Device Endpoint Register -------- */ +#define USBHS_DEVEPT_EPEN0 (0x1u << 0) /**< \brief (USBHS_DEVEPT) Endpoint 0 Enable */ +#define USBHS_DEVEPT_EPEN1 (0x1u << 1) /**< \brief (USBHS_DEVEPT) Endpoint 1 Enable */ +#define USBHS_DEVEPT_EPEN2 (0x1u << 2) /**< \brief (USBHS_DEVEPT) Endpoint 2 Enable */ +#define USBHS_DEVEPT_EPEN3 (0x1u << 3) /**< \brief (USBHS_DEVEPT) Endpoint 3 Enable */ +#define USBHS_DEVEPT_EPEN4 (0x1u << 4) /**< \brief (USBHS_DEVEPT) Endpoint 4 Enable */ +#define USBHS_DEVEPT_EPEN5 (0x1u << 5) /**< \brief (USBHS_DEVEPT) Endpoint 5 Enable */ +#define USBHS_DEVEPT_EPEN6 (0x1u << 6) /**< \brief (USBHS_DEVEPT) Endpoint 6 Enable */ +#define USBHS_DEVEPT_EPEN7 (0x1u << 7) /**< \brief (USBHS_DEVEPT) Endpoint 7 Enable */ +#define USBHS_DEVEPT_EPEN8 (0x1u << 8) /**< \brief (USBHS_DEVEPT) Endpoint 8 Enable */ +#define USBHS_DEVEPT_EPRST0 (0x1u << 16) /**< \brief (USBHS_DEVEPT) Endpoint 0 Reset */ +#define USBHS_DEVEPT_EPRST1 (0x1u << 17) /**< \brief (USBHS_DEVEPT) Endpoint 1 Reset */ +#define USBHS_DEVEPT_EPRST2 (0x1u << 18) /**< \brief (USBHS_DEVEPT) Endpoint 2 Reset */ +#define USBHS_DEVEPT_EPRST3 (0x1u << 19) /**< \brief (USBHS_DEVEPT) Endpoint 3 Reset */ +#define USBHS_DEVEPT_EPRST4 (0x1u << 20) /**< \brief (USBHS_DEVEPT) Endpoint 4 Reset */ +#define USBHS_DEVEPT_EPRST5 (0x1u << 21) /**< \brief (USBHS_DEVEPT) Endpoint 5 Reset */ +#define USBHS_DEVEPT_EPRST6 (0x1u << 22) /**< \brief (USBHS_DEVEPT) Endpoint 6 Reset */ +#define USBHS_DEVEPT_EPRST7 (0x1u << 23) /**< \brief (USBHS_DEVEPT) Endpoint 7 Reset */ +#define USBHS_DEVEPT_EPRST8 (0x1u << 24) /**< \brief (USBHS_DEVEPT) Endpoint 8 Reset */ +/* -------- USBHS_DEVFNUM : (USBHS Offset: 0x0020) Device Frame Number Register -------- */ +#define USBHS_DEVFNUM_MFNUM_Pos 0 +#define USBHS_DEVFNUM_MFNUM_Msk (0x7u << USBHS_DEVFNUM_MFNUM_Pos) /**< \brief (USBHS_DEVFNUM) Micro Frame Number */ +#define USBHS_DEVFNUM_FNUM_Pos 3 +#define USBHS_DEVFNUM_FNUM_Msk (0x7ffu << USBHS_DEVFNUM_FNUM_Pos) /**< \brief (USBHS_DEVFNUM) Frame Number */ +#define USBHS_DEVFNUM_FNCERR (0x1u << 15) /**< \brief (USBHS_DEVFNUM) Frame Number CRC Error */ +/* -------- USBHS_DEVEPTCFG[10] : (USBHS Offset: 0x100) Device Endpoint Configuration Register (n = 0) -------- */ +#define USBHS_DEVEPTCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Memory Allocate */ +#define USBHS_DEVEPTCFG_EPBK_Pos 2 +#define USBHS_DEVEPTCFG_EPBK_Msk (0x3u << USBHS_DEVEPTCFG_EPBK_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Banks */ +#define USBHS_DEVEPTCFG_EPBK(value) ((USBHS_DEVEPTCFG_EPBK_Msk & ((value) << USBHS_DEVEPTCFG_EPBK_Pos))) +#define USBHS_DEVEPTCFG_EPBK_1_BANK (0x0u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Single-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_2_BANK (0x1u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Double-bank endpoint */ +#define USBHS_DEVEPTCFG_EPBK_3_BANK (0x2u << 2) /**< \brief (USBHS_DEVEPTCFG[10]) Triple-bank endpoint */ +#define USBHS_DEVEPTCFG_EPSIZE_Pos 4 +#define USBHS_DEVEPTCFG_EPSIZE_Msk (0x7u << USBHS_DEVEPTCFG_EPSIZE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Size */ +#define USBHS_DEVEPTCFG_EPSIZE(value) ((USBHS_DEVEPTCFG_EPSIZE_Msk & ((value) << USBHS_DEVEPTCFG_EPSIZE_Pos))) +#define USBHS_DEVEPTCFG_EPSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 8 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 16 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 32 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 64 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 128 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 256 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 512 bytes */ +#define USBHS_DEVEPTCFG_EPSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_DEVEPTCFG[10]) 1024 bytes */ +#define USBHS_DEVEPTCFG_EPDIR (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Direction */ +#define USBHS_DEVEPTCFG_EPDIR_OUT (0x0u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is OUT. */ +#define USBHS_DEVEPTCFG_EPDIR_IN (0x1u << 8) /**< \brief (USBHS_DEVEPTCFG[10]) The endpoint direction is IN (nor for control endpoints). */ +#define USBHS_DEVEPTCFG_AUTOSW (0x1u << 9) /**< \brief (USBHS_DEVEPTCFG[10]) Automatic Switch */ +#define USBHS_DEVEPTCFG_EPTYPE_Pos 11 +#define USBHS_DEVEPTCFG_EPTYPE_Msk (0x3u << USBHS_DEVEPTCFG_EPTYPE_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Endpoint Type */ +#define USBHS_DEVEPTCFG_EPTYPE(value) ((USBHS_DEVEPTCFG_EPTYPE_Msk & ((value) << USBHS_DEVEPTCFG_EPTYPE_Pos))) +#define USBHS_DEVEPTCFG_EPTYPE_CTRL (0x0u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Control */ +#define USBHS_DEVEPTCFG_EPTYPE_ISO (0x1u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Isochronous */ +#define USBHS_DEVEPTCFG_EPTYPE_BLK (0x2u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Bulk */ +#define USBHS_DEVEPTCFG_EPTYPE_INTRPT (0x3u << 11) /**< \brief (USBHS_DEVEPTCFG[10]) Interrupt */ +#define USBHS_DEVEPTCFG_NBTRANS_Pos 13 +#define USBHS_DEVEPTCFG_NBTRANS_Msk (0x3u << USBHS_DEVEPTCFG_NBTRANS_Pos) /**< \brief (USBHS_DEVEPTCFG[10]) Number of transactions per microframe for isochronous endpoint */ +#define USBHS_DEVEPTCFG_NBTRANS(value) ((USBHS_DEVEPTCFG_NBTRANS_Msk & ((value) << USBHS_DEVEPTCFG_NBTRANS_Pos))) +#define USBHS_DEVEPTCFG_NBTRANS_0_TRANS (0x0u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Reserved to endpoint that does not have the high-bandwidth isochronous capability. */ +#define USBHS_DEVEPTCFG_NBTRANS_1_TRANS (0x1u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Default value: one transaction per microframe. */ +#define USBHS_DEVEPTCFG_NBTRANS_2_TRANS (0x2u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Two transactions per microframe. This endpoint should be configured as double-bank. */ +#define USBHS_DEVEPTCFG_NBTRANS_3_TRANS (0x3u << 13) /**< \brief (USBHS_DEVEPTCFG[10]) Three transactions per microframe. This endpoint should be configured as triple-bank. */ +/* -------- USBHS_DEVEPTISR[10] : (USBHS Offset: 0x130) Device Endpoint Status Register (n = 0) -------- */ +#define USBHS_DEVEPTISR_TXINI (0x1u << 0) /**< \brief (USBHS_DEVEPTISR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTISR_RXOUTI (0x1u << 1) /**< \brief (USBHS_DEVEPTISR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTISR_RXSTPI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTISR_NAKOUTI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTISR_NAKINI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTISR_OVERFI (0x1u << 5) /**< \brief (USBHS_DEVEPTISR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTISR_STALLEDI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTISR_SHORTPACKET (0x1u << 7) /**< \brief (USBHS_DEVEPTISR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTISR_DTSEQ_Pos 8 +#define USBHS_DEVEPTISR_DTSEQ_Msk (0x3u << USBHS_DEVEPTISR_DTSEQ_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Data Toggle Sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data0 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Data1 toggle sequence */ +#define USBHS_DEVEPTISR_DTSEQ_DATA2 (0x2u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_DTSEQ_MDATA (0x3u << 8) /**< \brief (USBHS_DEVEPTISR[10]) Reserved for high-bandwidth isochronous endpoint */ +#define USBHS_DEVEPTISR_NBUSYBK_Pos 12 +#define USBHS_DEVEPTISR_NBUSYBK_Msk (0x3u << USBHS_DEVEPTISR_NBUSYBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Number of Busy Banks */ +#define USBHS_DEVEPTISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 0 busy bank (all banks free) */ +#define USBHS_DEVEPTISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 1 busy bank */ +#define USBHS_DEVEPTISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 2 busy banks */ +#define USBHS_DEVEPTISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_DEVEPTISR[10]) 3 busy banks */ +#define USBHS_DEVEPTISR_CURRBK_Pos 14 +#define USBHS_DEVEPTISR_CURRBK_Msk (0x3u << USBHS_DEVEPTISR_CURRBK_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Current Bank */ +#define USBHS_DEVEPTISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank0 */ +#define USBHS_DEVEPTISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank1 */ +#define USBHS_DEVEPTISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_DEVEPTISR[10]) Current bank is bank2 */ +#define USBHS_DEVEPTISR_RWALL (0x1u << 16) /**< \brief (USBHS_DEVEPTISR[10]) Read/Write Allowed */ +#define USBHS_DEVEPTISR_CTRLDIR (0x1u << 17) /**< \brief (USBHS_DEVEPTISR[10]) Control Direction */ +#define USBHS_DEVEPTISR_CFGOK (0x1u << 18) /**< \brief (USBHS_DEVEPTISR[10]) Configuration OK Status */ +#define USBHS_DEVEPTISR_BYCT_Pos 20 +#define USBHS_DEVEPTISR_BYCT_Msk (0x7ffu << USBHS_DEVEPTISR_BYCT_Pos) /**< \brief (USBHS_DEVEPTISR[10]) Byte Count */ +#define USBHS_DEVEPTISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_DEVEPTISR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTISR_HBISOINERRI (0x1u << 3) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt */ +#define USBHS_DEVEPTISR_HBISOFLUSHI (0x1u << 4) /**< \brief (USBHS_DEVEPTISR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_DEVEPTISR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTISR_ERRORTRANS (0x1u << 10) /**< \brief (USBHS_DEVEPTISR[10]) High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTICR[10] : (USBHS Offset: 0x160) Device Endpoint Clear Register (n = 0) -------- */ +#define USBHS_DEVEPTICR_TXINIC (0x1u << 0) /**< \brief (USBHS_DEVEPTICR[10]) Transmitted IN Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXOUTIC (0x1u << 1) /**< \brief (USBHS_DEVEPTICR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTICR_RXSTPIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKOUTIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTICR_NAKINIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_DEVEPTICR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTICR_STALLEDIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTICR_SHORTPACKETC (0x1u << 7) /**< \brief (USBHS_DEVEPTICR[10]) Short Packet Interrupt Clear */ +#define USBHS_DEVEPTICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_DEVEPTICR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOINERRIC (0x1u << 3) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Clear */ +#define USBHS_DEVEPTICR_HBISOFLUSHIC (0x1u << 4) /**< \brief (USBHS_DEVEPTICR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_DEVEPTICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_DEVEPTIFR[10] : (USBHS Offset: 0x190) Device Endpoint Set Register (n = 0) -------- */ +#define USBHS_DEVEPTIFR_TXINIS (0x1u << 0) /**< \brief (USBHS_DEVEPTIFR[10]) Transmitted IN Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXOUTIS (0x1u << 1) /**< \brief (USBHS_DEVEPTIFR[10]) Received OUT Data Interrupt Set */ +#define USBHS_DEVEPTIFR_RXSTPIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Received SETUP Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKOUTIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed OUT Interrupt Set */ +#define USBHS_DEVEPTIFR_NAKINIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) NAKed IN Interrupt Set */ +#define USBHS_DEVEPTIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_DEVEPTIFR[10]) Overflow Interrupt Set */ +#define USBHS_DEVEPTIFR_STALLEDIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) STALLed Interrupt Set */ +#define USBHS_DEVEPTIFR_SHORTPACKETS (0x1u << 7) /**< \brief (USBHS_DEVEPTIFR[10]) Short Packet Interrupt Set */ +#define USBHS_DEVEPTIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_DEVEPTIFR[10]) Number of Busy Banks Interrupt Set */ +#define USBHS_DEVEPTIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_DEVEPTIFR[10]) Underflow Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOINERRIS (0x1u << 3) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Underflow Error Interrupt Set */ +#define USBHS_DEVEPTIFR_HBISOFLUSHIS (0x1u << 4) /**< \brief (USBHS_DEVEPTIFR[10]) High Bandwidth Isochronous IN Flush Interrupt Set */ +#define USBHS_DEVEPTIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_DEVEPTIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_DEVEPTIMR[10] : (USBHS Offset: 0x1C0) Device Endpoint Mask Register (n = 0) -------- */ +#define USBHS_DEVEPTIMR_TXINE (0x1u << 0) /**< \brief (USBHS_DEVEPTIMR[10]) Transmitted IN Data Interrupt */ +#define USBHS_DEVEPTIMR_RXOUTE (0x1u << 1) /**< \brief (USBHS_DEVEPTIMR[10]) Received OUT Data Interrupt */ +#define USBHS_DEVEPTIMR_RXSTPE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Received SETUP Interrupt */ +#define USBHS_DEVEPTIMR_NAKOUTE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed OUT Interrupt */ +#define USBHS_DEVEPTIMR_NAKINE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) NAKed IN Interrupt */ +#define USBHS_DEVEPTIMR_OVERFE (0x1u << 5) /**< \brief (USBHS_DEVEPTIMR[10]) Overflow Interrupt */ +#define USBHS_DEVEPTIMR_STALLEDE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) STALLed Interrupt */ +#define USBHS_DEVEPTIMR_SHORTPACKETE (0x1u << 7) /**< \brief (USBHS_DEVEPTIMR[10]) Short Packet Interrupt */ +#define USBHS_DEVEPTIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_DEVEPTIMR[10]) Number of Busy Banks Interrupt */ +#define USBHS_DEVEPTIMR_KILLBK (0x1u << 13) /**< \brief (USBHS_DEVEPTIMR[10]) Kill IN Bank */ +#define USBHS_DEVEPTIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_DEVEPTIMR[10]) FIFO Control */ +#define USBHS_DEVEPTIMR_EPDISHDMA (0x1u << 16) /**< \brief (USBHS_DEVEPTIMR[10]) Endpoint Interrupts Disable HDMA Request */ +#define USBHS_DEVEPTIMR_NYETDIS (0x1u << 17) /**< \brief (USBHS_DEVEPTIMR[10]) NYET Token Disable */ +#define USBHS_DEVEPTIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_DEVEPTIMR[10]) Reset Data Toggle */ +#define USBHS_DEVEPTIMR_STALLRQ (0x1u << 19) /**< \brief (USBHS_DEVEPTIMR[10]) STALL Request */ +#define USBHS_DEVEPTIMR_UNDERFE (0x1u << 2) /**< \brief (USBHS_DEVEPTIMR[10]) Underflow Interrupt */ +#define USBHS_DEVEPTIMR_HBISOINERRE (0x1u << 3) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Error Interrupt */ +#define USBHS_DEVEPTIMR_HBISOFLUSHE (0x1u << 4) /**< \brief (USBHS_DEVEPTIMR[10]) High Bandwidth Isochronous IN Flush Interrupt */ +#define USBHS_DEVEPTIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_DEVEPTIMR[10]) CRC Error Interrupt */ +#define USBHS_DEVEPTIMR_MDATAE (0x1u << 8) /**< \brief (USBHS_DEVEPTIMR[10]) MData Interrupt */ +#define USBHS_DEVEPTIMR_DATAXE (0x1u << 9) /**< \brief (USBHS_DEVEPTIMR[10]) DataX Interrupt */ +#define USBHS_DEVEPTIMR_ERRORTRANSE (0x1u << 10) /**< \brief (USBHS_DEVEPTIMR[10]) Transaction Error Interrupt */ +/* -------- USBHS_DEVEPTIER[10] : (USBHS Offset: 0x1F0) Device Endpoint Enable Register (n = 0) -------- */ +#define USBHS_DEVEPTIER_TXINES (0x1u << 0) /**< \brief (USBHS_DEVEPTIER[10]) Transmitted IN Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXOUTES (0x1u << 1) /**< \brief (USBHS_DEVEPTIER[10]) Received OUT Data Interrupt Enable */ +#define USBHS_DEVEPTIER_RXSTPES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Received SETUP Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKOUTES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) NAKed OUT Interrupt Enable */ +#define USBHS_DEVEPTIER_NAKINES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) NAKed IN Interrupt Enable */ +#define USBHS_DEVEPTIER_OVERFES (0x1u << 5) /**< \brief (USBHS_DEVEPTIER[10]) Overflow Interrupt Enable */ +#define USBHS_DEVEPTIER_STALLEDES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) STALLed Interrupt Enable */ +#define USBHS_DEVEPTIER_SHORTPACKETES (0x1u << 7) /**< \brief (USBHS_DEVEPTIER[10]) Short Packet Interrupt Enable */ +#define USBHS_DEVEPTIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_DEVEPTIER[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_DEVEPTIER_KILLBKS (0x1u << 13) /**< \brief (USBHS_DEVEPTIER[10]) Kill IN Bank */ +#define USBHS_DEVEPTIER_FIFOCONS (0x1u << 14) /**< \brief (USBHS_DEVEPTIER[10]) FIFO Control */ +#define USBHS_DEVEPTIER_EPDISHDMAS (0x1u << 16) /**< \brief (USBHS_DEVEPTIER[10]) Endpoint Interrupts Disable HDMA Request Enable */ +#define USBHS_DEVEPTIER_NYETDISS (0x1u << 17) /**< \brief (USBHS_DEVEPTIER[10]) NYET Token Disable Enable */ +#define USBHS_DEVEPTIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_DEVEPTIER[10]) Reset Data Toggle Enable */ +#define USBHS_DEVEPTIER_STALLRQS (0x1u << 19) /**< \brief (USBHS_DEVEPTIER[10]) STALL Request Enable */ +#define USBHS_DEVEPTIER_UNDERFES (0x1u << 2) /**< \brief (USBHS_DEVEPTIER[10]) Underflow Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOINERRES (0x1u << 3) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Error Interrupt Enable */ +#define USBHS_DEVEPTIER_HBISOFLUSHES (0x1u << 4) /**< \brief (USBHS_DEVEPTIER[10]) High Bandwidth Isochronous IN Flush Interrupt Enable */ +#define USBHS_DEVEPTIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_DEVEPTIER[10]) CRC Error Interrupt Enable */ +#define USBHS_DEVEPTIER_MDATAES (0x1u << 8) /**< \brief (USBHS_DEVEPTIER[10]) MData Interrupt Enable */ +#define USBHS_DEVEPTIER_DATAXES (0x1u << 9) /**< \brief (USBHS_DEVEPTIER[10]) DataX Interrupt Enable */ +#define USBHS_DEVEPTIER_ERRORTRANSES (0x1u << 10) /**< \brief (USBHS_DEVEPTIER[10]) Transaction Error Interrupt Enable */ +/* -------- USBHS_DEVEPTIDR[10] : (USBHS Offset: 0x220) Device Endpoint Disable Register (n = 0) -------- */ +#define USBHS_DEVEPTIDR_TXINEC (0x1u << 0) /**< \brief (USBHS_DEVEPTIDR[10]) Transmitted IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXOUTEC (0x1u << 1) /**< \brief (USBHS_DEVEPTIDR[10]) Received OUT Data Interrupt Clear */ +#define USBHS_DEVEPTIDR_RXSTPEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Received SETUP Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKOUTEC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed OUT Interrupt Clear */ +#define USBHS_DEVEPTIDR_NAKINEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) NAKed IN Interrupt Clear */ +#define USBHS_DEVEPTIDR_OVERFEC (0x1u << 5) /**< \brief (USBHS_DEVEPTIDR[10]) Overflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_STALLEDEC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) STALLed Interrupt Clear */ +#define USBHS_DEVEPTIDR_SHORTPACKETEC (0x1u << 7) /**< \brief (USBHS_DEVEPTIDR[10]) Shortpacket Interrupt Clear */ +#define USBHS_DEVEPTIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_DEVEPTIDR[10]) Number of Busy Banks Interrupt Clear */ +#define USBHS_DEVEPTIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_DEVEPTIDR[10]) FIFO Control Clear */ +#define USBHS_DEVEPTIDR_EPDISHDMAC (0x1u << 16) /**< \brief (USBHS_DEVEPTIDR[10]) Endpoint Interrupts Disable HDMA Request Clear */ +#define USBHS_DEVEPTIDR_NYETDISC (0x1u << 17) /**< \brief (USBHS_DEVEPTIDR[10]) NYET Token Disable Clear */ +#define USBHS_DEVEPTIDR_STALLRQC (0x1u << 19) /**< \brief (USBHS_DEVEPTIDR[10]) STALL Request Clear */ +#define USBHS_DEVEPTIDR_UNDERFEC (0x1u << 2) /**< \brief (USBHS_DEVEPTIDR[10]) Underflow Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOINERREC (0x1u << 3) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_HBISOFLUSHEC (0x1u << 4) /**< \brief (USBHS_DEVEPTIDR[10]) High Bandwidth Isochronous IN Flush Interrupt Clear */ +#define USBHS_DEVEPTIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_DEVEPTIDR[10]) CRC Error Interrupt Clear */ +#define USBHS_DEVEPTIDR_MDATEC (0x1u << 8) /**< \brief (USBHS_DEVEPTIDR[10]) MData Interrupt Clear */ +#define USBHS_DEVEPTIDR_DATAXEC (0x1u << 9) /**< \brief (USBHS_DEVEPTIDR[10]) DataX Interrupt Clear */ +#define USBHS_DEVEPTIDR_ERRORTRANSEC (0x1u << 10) /**< \brief (USBHS_DEVEPTIDR[10]) Transaction Error Interrupt Clear */ +/* -------- USBHS_DEVDMANXTDSC : (USBHS Offset: N/A) Device DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_DEVDMANXTDSC) Next Descriptor Address */ +#define USBHS_DEVDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_DEVDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_DEVDMAADDRESS : (USBHS Offset: N/A) Device DMA Channel Address Register -------- */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_DEVDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_DEVDMAADDRESS) Buffer Address */ +#define USBHS_DEVDMAADDRESS_BUFF_ADD(value) ((USBHS_DEVDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_DEVDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_DEVDMACONTROL : (USBHS Offset: N/A) Device DMA Channel Control Register -------- */ +#define USBHS_DEVDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMACONTROL) Channel Enable Command */ +#define USBHS_DEVDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_DEVDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_DEVDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_DEVDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Enable Control */ +#define USBHS_DEVDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_DEVDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_DEVDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_DEVDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_DEVDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_DEVDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_DEVDMACONTROL) Burst Lock Enable */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_DEVDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_DEVDMACONTROL_BUFF_LENGTH(value) ((USBHS_DEVDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_DEVDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_DEVDMASTATUS : (USBHS Offset: N/A) Device DMA Channel Status Register -------- */ +#define USBHS_DEVDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_DEVDMASTATUS) Channel Enable Status */ +#define USBHS_DEVDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_DEVDMASTATUS) Channel Active Status */ +#define USBHS_DEVDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Transfer Status */ +#define USBHS_DEVDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_DEVDMASTATUS) End of Channel Buffer Status */ +#define USBHS_DEVDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_DEVDMASTATUS) Descriptor Loaded Status */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_DEVDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_DEVDMASTATUS) Buffer Byte Count */ +#define USBHS_DEVDMASTATUS_BUFF_COUNT(value) ((USBHS_DEVDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_DEVDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_HSTCTRL : (USBHS Offset: 0x0400) Host General Control Register -------- */ +#define USBHS_HSTCTRL_SOFE (0x1u << 8) /**< \brief (USBHS_HSTCTRL) Start of Frame Generation Enable */ +#define USBHS_HSTCTRL_RESET (0x1u << 9) /**< \brief (USBHS_HSTCTRL) Send USB Reset */ +#define USBHS_HSTCTRL_RESUME (0x1u << 10) /**< \brief (USBHS_HSTCTRL) Send USB Resume */ +#define USBHS_HSTCTRL_SPDCONF_Pos 12 +#define USBHS_HSTCTRL_SPDCONF_Msk (0x3u << USBHS_HSTCTRL_SPDCONF_Pos) /**< \brief (USBHS_HSTCTRL) Mode Configuration */ +#define USBHS_HSTCTRL_SPDCONF(value) ((USBHS_HSTCTRL_SPDCONF_Msk & ((value) << USBHS_HSTCTRL_SPDCONF_Pos))) +#define USBHS_HSTCTRL_SPDCONF_NORMAL (0x0u << 12) /**< \brief (USBHS_HSTCTRL) The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. */ +#define USBHS_HSTCTRL_SPDCONF_LOW_POWER (0x1u << 12) /**< \brief (USBHS_HSTCTRL) For a better consumption, if high speed is not needed. */ +#define USBHS_HSTCTRL_SPDCONF_HIGH_SPEED (0x2u << 12) /**< \brief (USBHS_HSTCTRL) Forced high speed. */ +#define USBHS_HSTCTRL_SPDCONF_FORCED_FS (0x3u << 12) /**< \brief (USBHS_HSTCTRL) The host remains in Full-speed mode whatever the peripheral speed capability. */ +/* -------- USBHS_HSTISR : (USBHS Offset: 0x0404) Host Global Interrupt Status Register -------- */ +#define USBHS_HSTISR_DCONNI (0x1u << 0) /**< \brief (USBHS_HSTISR) Device Connection Interrupt */ +#define USBHS_HSTISR_DDISCI (0x1u << 1) /**< \brief (USBHS_HSTISR) Device Disconnection Interrupt */ +#define USBHS_HSTISR_RSTI (0x1u << 2) /**< \brief (USBHS_HSTISR) USB Reset Sent Interrupt */ +#define USBHS_HSTISR_RSMEDI (0x1u << 3) /**< \brief (USBHS_HSTISR) Downstream Resume Sent Interrupt */ +#define USBHS_HSTISR_RXRSMI (0x1u << 4) /**< \brief (USBHS_HSTISR) Upstream Resume Received Interrupt */ +#define USBHS_HSTISR_HSOFI (0x1u << 5) /**< \brief (USBHS_HSTISR) Host Start of Frame Interrupt */ +#define USBHS_HSTISR_HWUPI (0x1u << 6) /**< \brief (USBHS_HSTISR) Host Wake-Up Interrupt */ +#define USBHS_HSTISR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTISR) Pipe 0 Interrupt */ +#define USBHS_HSTISR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTISR) Pipe 1 Interrupt */ +#define USBHS_HSTISR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTISR) Pipe 2 Interrupt */ +#define USBHS_HSTISR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTISR) Pipe 3 Interrupt */ +#define USBHS_HSTISR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTISR) Pipe 4 Interrupt */ +#define USBHS_HSTISR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTISR) Pipe 5 Interrupt */ +#define USBHS_HSTISR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTISR) Pipe 6 Interrupt */ +#define USBHS_HSTISR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTISR) Pipe 7 Interrupt */ +#define USBHS_HSTISR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTISR) Pipe 8 Interrupt */ +#define USBHS_HSTISR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTISR) Pipe 9 Interrupt */ +#define USBHS_HSTISR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTISR) Pipe 10 Interrupt */ +#define USBHS_HSTISR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTISR) Pipe 11 Interrupt */ +#define USBHS_HSTISR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTISR) DMA Channel 1 Interrupt */ +#define USBHS_HSTISR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTISR) DMA Channel 2 Interrupt */ +#define USBHS_HSTISR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTISR) DMA Channel 3 Interrupt */ +#define USBHS_HSTISR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTISR) DMA Channel 4 Interrupt */ +#define USBHS_HSTISR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTISR) DMA Channel 5 Interrupt */ +#define USBHS_HSTISR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTISR) DMA Channel 6 Interrupt */ +#define USBHS_HSTISR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTISR) DMA Channel 7 Interrupt */ +/* -------- USBHS_HSTICR : (USBHS Offset: 0x0408) Host Global Interrupt Clear Register -------- */ +#define USBHS_HSTICR_DCONNIC (0x1u << 0) /**< \brief (USBHS_HSTICR) Device Connection Interrupt Clear */ +#define USBHS_HSTICR_DDISCIC (0x1u << 1) /**< \brief (USBHS_HSTICR) Device Disconnection Interrupt Clear */ +#define USBHS_HSTICR_RSTIC (0x1u << 2) /**< \brief (USBHS_HSTICR) USB Reset Sent Interrupt Clear */ +#define USBHS_HSTICR_RSMEDIC (0x1u << 3) /**< \brief (USBHS_HSTICR) Downstream Resume Sent Interrupt Clear */ +#define USBHS_HSTICR_RXRSMIC (0x1u << 4) /**< \brief (USBHS_HSTICR) Upstream Resume Received Interrupt Clear */ +#define USBHS_HSTICR_HSOFIC (0x1u << 5) /**< \brief (USBHS_HSTICR) Host Start of Frame Interrupt Clear */ +#define USBHS_HSTICR_HWUPIC (0x1u << 6) /**< \brief (USBHS_HSTICR) Host Wake-Up Interrupt Clear */ +/* -------- USBHS_HSTIFR : (USBHS Offset: 0x040C) Host Global Interrupt Set Register -------- */ +#define USBHS_HSTIFR_DCONNIS (0x1u << 0) /**< \brief (USBHS_HSTIFR) Device Connection Interrupt Set */ +#define USBHS_HSTIFR_DDISCIS (0x1u << 1) /**< \brief (USBHS_HSTIFR) Device Disconnection Interrupt Set */ +#define USBHS_HSTIFR_RSTIS (0x1u << 2) /**< \brief (USBHS_HSTIFR) USB Reset Sent Interrupt Set */ +#define USBHS_HSTIFR_RSMEDIS (0x1u << 3) /**< \brief (USBHS_HSTIFR) Downstream Resume Sent Interrupt Set */ +#define USBHS_HSTIFR_RXRSMIS (0x1u << 4) /**< \brief (USBHS_HSTIFR) Upstream Resume Received Interrupt Set */ +#define USBHS_HSTIFR_HSOFIS (0x1u << 5) /**< \brief (USBHS_HSTIFR) Host Start of Frame Interrupt Set */ +#define USBHS_HSTIFR_HWUPIS (0x1u << 6) /**< \brief (USBHS_HSTIFR) Host Wake-Up Interrupt Set */ +#define USBHS_HSTIFR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIFR) DMA Channel 1 Interrupt Set */ +#define USBHS_HSTIFR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIFR) DMA Channel 2 Interrupt Set */ +#define USBHS_HSTIFR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIFR) DMA Channel 3 Interrupt Set */ +#define USBHS_HSTIFR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIFR) DMA Channel 4 Interrupt Set */ +#define USBHS_HSTIFR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIFR) DMA Channel 5 Interrupt Set */ +#define USBHS_HSTIFR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIFR) DMA Channel 6 Interrupt Set */ +#define USBHS_HSTIFR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIFR) DMA Channel 7 Interrupt Set */ +/* -------- USBHS_HSTIMR : (USBHS Offset: 0x0410) Host Global Interrupt Mask Register -------- */ +#define USBHS_HSTIMR_DCONNIE (0x1u << 0) /**< \brief (USBHS_HSTIMR) Device Connection Interrupt Enable */ +#define USBHS_HSTIMR_DDISCIE (0x1u << 1) /**< \brief (USBHS_HSTIMR) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIMR_RSTIE (0x1u << 2) /**< \brief (USBHS_HSTIMR) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIMR_RSMEDIE (0x1u << 3) /**< \brief (USBHS_HSTIMR) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIMR_RXRSMIE (0x1u << 4) /**< \brief (USBHS_HSTIMR) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIMR_HSOFIE (0x1u << 5) /**< \brief (USBHS_HSTIMR) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIMR_HWUPIE (0x1u << 6) /**< \brief (USBHS_HSTIMR) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIMR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIMR) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIMR) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIMR) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIMR) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIMR) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIMR) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIMR) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIMR) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIMR) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIMR) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIMR) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIMR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIMR) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIMR) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIMR) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIMR) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIMR) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIMR) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIMR) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIMR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIMR) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTIDR : (USBHS Offset: 0x0414) Host Global Interrupt Disable Register -------- */ +#define USBHS_HSTIDR_DCONNIEC (0x1u << 0) /**< \brief (USBHS_HSTIDR) Device Connection Interrupt Disable */ +#define USBHS_HSTIDR_DDISCIEC (0x1u << 1) /**< \brief (USBHS_HSTIDR) Device Disconnection Interrupt Disable */ +#define USBHS_HSTIDR_RSTIEC (0x1u << 2) /**< \brief (USBHS_HSTIDR) USB Reset Sent Interrupt Disable */ +#define USBHS_HSTIDR_RSMEDIEC (0x1u << 3) /**< \brief (USBHS_HSTIDR) Downstream Resume Sent Interrupt Disable */ +#define USBHS_HSTIDR_RXRSMIEC (0x1u << 4) /**< \brief (USBHS_HSTIDR) Upstream Resume Received Interrupt Disable */ +#define USBHS_HSTIDR_HSOFIEC (0x1u << 5) /**< \brief (USBHS_HSTIDR) Host Start of Frame Interrupt Disable */ +#define USBHS_HSTIDR_HWUPIEC (0x1u << 6) /**< \brief (USBHS_HSTIDR) Host Wake-Up Interrupt Disable */ +#define USBHS_HSTIDR_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIDR) Pipe 0 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIDR) Pipe 1 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIDR) Pipe 2 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIDR) Pipe 3 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIDR) Pipe 4 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIDR) Pipe 5 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIDR) Pipe 6 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIDR) Pipe 7 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIDR) Pipe 8 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIDR) Pipe 9 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIDR) Pipe 10 Interrupt Disable */ +#define USBHS_HSTIDR_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIDR) Pipe 11 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIDR) DMA Channel 1 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIDR) DMA Channel 2 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIDR) DMA Channel 3 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIDR) DMA Channel 4 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIDR) DMA Channel 5 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIDR) DMA Channel 6 Interrupt Disable */ +#define USBHS_HSTIDR_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIDR) DMA Channel 7 Interrupt Disable */ +/* -------- USBHS_HSTIER : (USBHS Offset: 0x0418) Host Global Interrupt Enable Register -------- */ +#define USBHS_HSTIER_DCONNIES (0x1u << 0) /**< \brief (USBHS_HSTIER) Device Connection Interrupt Enable */ +#define USBHS_HSTIER_DDISCIES (0x1u << 1) /**< \brief (USBHS_HSTIER) Device Disconnection Interrupt Enable */ +#define USBHS_HSTIER_RSTIES (0x1u << 2) /**< \brief (USBHS_HSTIER) USB Reset Sent Interrupt Enable */ +#define USBHS_HSTIER_RSMEDIES (0x1u << 3) /**< \brief (USBHS_HSTIER) Downstream Resume Sent Interrupt Enable */ +#define USBHS_HSTIER_RXRSMIES (0x1u << 4) /**< \brief (USBHS_HSTIER) Upstream Resume Received Interrupt Enable */ +#define USBHS_HSTIER_HSOFIES (0x1u << 5) /**< \brief (USBHS_HSTIER) Host Start of Frame Interrupt Enable */ +#define USBHS_HSTIER_HWUPIES (0x1u << 6) /**< \brief (USBHS_HSTIER) Host Wake-Up Interrupt Enable */ +#define USBHS_HSTIER_PEP_0 (0x1u << 8) /**< \brief (USBHS_HSTIER) Pipe 0 Interrupt Enable */ +#define USBHS_HSTIER_PEP_1 (0x1u << 9) /**< \brief (USBHS_HSTIER) Pipe 1 Interrupt Enable */ +#define USBHS_HSTIER_PEP_2 (0x1u << 10) /**< \brief (USBHS_HSTIER) Pipe 2 Interrupt Enable */ +#define USBHS_HSTIER_PEP_3 (0x1u << 11) /**< \brief (USBHS_HSTIER) Pipe 3 Interrupt Enable */ +#define USBHS_HSTIER_PEP_4 (0x1u << 12) /**< \brief (USBHS_HSTIER) Pipe 4 Interrupt Enable */ +#define USBHS_HSTIER_PEP_5 (0x1u << 13) /**< \brief (USBHS_HSTIER) Pipe 5 Interrupt Enable */ +#define USBHS_HSTIER_PEP_6 (0x1u << 14) /**< \brief (USBHS_HSTIER) Pipe 6 Interrupt Enable */ +#define USBHS_HSTIER_PEP_7 (0x1u << 15) /**< \brief (USBHS_HSTIER) Pipe 7 Interrupt Enable */ +#define USBHS_HSTIER_PEP_8 (0x1u << 16) /**< \brief (USBHS_HSTIER) Pipe 8 Interrupt Enable */ +#define USBHS_HSTIER_PEP_9 (0x1u << 17) /**< \brief (USBHS_HSTIER) Pipe 9 Interrupt Enable */ +#define USBHS_HSTIER_PEP_10 (0x1u << 18) /**< \brief (USBHS_HSTIER) Pipe 10 Interrupt Enable */ +#define USBHS_HSTIER_PEP_11 (0x1u << 19) /**< \brief (USBHS_HSTIER) Pipe 11 Interrupt Enable */ +#define USBHS_HSTIER_DMA_1 (0x1u << 25) /**< \brief (USBHS_HSTIER) DMA Channel 1 Interrupt Enable */ +#define USBHS_HSTIER_DMA_2 (0x1u << 26) /**< \brief (USBHS_HSTIER) DMA Channel 2 Interrupt Enable */ +#define USBHS_HSTIER_DMA_3 (0x1u << 27) /**< \brief (USBHS_HSTIER) DMA Channel 3 Interrupt Enable */ +#define USBHS_HSTIER_DMA_4 (0x1u << 28) /**< \brief (USBHS_HSTIER) DMA Channel 4 Interrupt Enable */ +#define USBHS_HSTIER_DMA_5 (0x1u << 29) /**< \brief (USBHS_HSTIER) DMA Channel 5 Interrupt Enable */ +#define USBHS_HSTIER_DMA_6 (0x1u << 30) /**< \brief (USBHS_HSTIER) DMA Channel 6 Interrupt Enable */ +#define USBHS_HSTIER_DMA_7 (0x1u << 31) /**< \brief (USBHS_HSTIER) DMA Channel 7 Interrupt Enable */ +/* -------- USBHS_HSTPIP : (USBHS Offset: 0x0041C) Host Pipe Register -------- */ +#define USBHS_HSTPIP_PEN0 (0x1u << 0) /**< \brief (USBHS_HSTPIP) Pipe 0 Enable */ +#define USBHS_HSTPIP_PEN1 (0x1u << 1) /**< \brief (USBHS_HSTPIP) Pipe 1 Enable */ +#define USBHS_HSTPIP_PEN2 (0x1u << 2) /**< \brief (USBHS_HSTPIP) Pipe 2 Enable */ +#define USBHS_HSTPIP_PEN3 (0x1u << 3) /**< \brief (USBHS_HSTPIP) Pipe 3 Enable */ +#define USBHS_HSTPIP_PEN4 (0x1u << 4) /**< \brief (USBHS_HSTPIP) Pipe 4 Enable */ +#define USBHS_HSTPIP_PEN5 (0x1u << 5) /**< \brief (USBHS_HSTPIP) Pipe 5 Enable */ +#define USBHS_HSTPIP_PEN6 (0x1u << 6) /**< \brief (USBHS_HSTPIP) Pipe 6 Enable */ +#define USBHS_HSTPIP_PEN7 (0x1u << 7) /**< \brief (USBHS_HSTPIP) Pipe 7 Enable */ +#define USBHS_HSTPIP_PEN8 (0x1u << 8) /**< \brief (USBHS_HSTPIP) Pipe 8 Enable */ +#define USBHS_HSTPIP_PRST0 (0x1u << 16) /**< \brief (USBHS_HSTPIP) Pipe 0 Reset */ +#define USBHS_HSTPIP_PRST1 (0x1u << 17) /**< \brief (USBHS_HSTPIP) Pipe 1 Reset */ +#define USBHS_HSTPIP_PRST2 (0x1u << 18) /**< \brief (USBHS_HSTPIP) Pipe 2 Reset */ +#define USBHS_HSTPIP_PRST3 (0x1u << 19) /**< \brief (USBHS_HSTPIP) Pipe 3 Reset */ +#define USBHS_HSTPIP_PRST4 (0x1u << 20) /**< \brief (USBHS_HSTPIP) Pipe 4 Reset */ +#define USBHS_HSTPIP_PRST5 (0x1u << 21) /**< \brief (USBHS_HSTPIP) Pipe 5 Reset */ +#define USBHS_HSTPIP_PRST6 (0x1u << 22) /**< \brief (USBHS_HSTPIP) Pipe 6 Reset */ +#define USBHS_HSTPIP_PRST7 (0x1u << 23) /**< \brief (USBHS_HSTPIP) Pipe 7 Reset */ +#define USBHS_HSTPIP_PRST8 (0x1u << 24) /**< \brief (USBHS_HSTPIP) Pipe 8 Reset */ +/* -------- USBHS_HSTFNUM : (USBHS Offset: 0x0420) Host Frame Number Register -------- */ +#define USBHS_HSTFNUM_MFNUM_Pos 0 +#define USBHS_HSTFNUM_MFNUM_Msk (0x7u << USBHS_HSTFNUM_MFNUM_Pos) /**< \brief (USBHS_HSTFNUM) Micro Frame Number */ +#define USBHS_HSTFNUM_MFNUM(value) ((USBHS_HSTFNUM_MFNUM_Msk & ((value) << USBHS_HSTFNUM_MFNUM_Pos))) +#define USBHS_HSTFNUM_FNUM_Pos 3 +#define USBHS_HSTFNUM_FNUM_Msk (0x7ffu << USBHS_HSTFNUM_FNUM_Pos) /**< \brief (USBHS_HSTFNUM) Frame Number */ +#define USBHS_HSTFNUM_FNUM(value) ((USBHS_HSTFNUM_FNUM_Msk & ((value) << USBHS_HSTFNUM_FNUM_Pos))) +#define USBHS_HSTFNUM_FLENHIGH_Pos 16 +#define USBHS_HSTFNUM_FLENHIGH_Msk (0xffu << USBHS_HSTFNUM_FLENHIGH_Pos) /**< \brief (USBHS_HSTFNUM) Frame Length */ +#define USBHS_HSTFNUM_FLENHIGH(value) ((USBHS_HSTFNUM_FLENHIGH_Msk & ((value) << USBHS_HSTFNUM_FLENHIGH_Pos))) +/* -------- USBHS_HSTADDR1 : (USBHS Offset: 0x0424) Host Address 1 Register -------- */ +#define USBHS_HSTADDR1_HSTADDRP0_Pos 0 +#define USBHS_HSTADDR1_HSTADDRP0_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP0_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP0(value) ((USBHS_HSTADDR1_HSTADDRP0_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP0_Pos))) +#define USBHS_HSTADDR1_HSTADDRP1_Pos 8 +#define USBHS_HSTADDR1_HSTADDRP1_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP1_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP1(value) ((USBHS_HSTADDR1_HSTADDRP1_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP1_Pos))) +#define USBHS_HSTADDR1_HSTADDRP2_Pos 16 +#define USBHS_HSTADDR1_HSTADDRP2_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP2_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP2(value) ((USBHS_HSTADDR1_HSTADDRP2_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP2_Pos))) +#define USBHS_HSTADDR1_HSTADDRP3_Pos 24 +#define USBHS_HSTADDR1_HSTADDRP3_Msk (0x7fu << USBHS_HSTADDR1_HSTADDRP3_Pos) /**< \brief (USBHS_HSTADDR1) USB Host Address */ +#define USBHS_HSTADDR1_HSTADDRP3(value) ((USBHS_HSTADDR1_HSTADDRP3_Msk & ((value) << USBHS_HSTADDR1_HSTADDRP3_Pos))) +/* -------- USBHS_HSTADDR2 : (USBHS Offset: 0x0428) Host Address 2 Register -------- */ +#define USBHS_HSTADDR2_HSTADDRP4_Pos 0 +#define USBHS_HSTADDR2_HSTADDRP4_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP4_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP4(value) ((USBHS_HSTADDR2_HSTADDRP4_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP4_Pos))) +#define USBHS_HSTADDR2_HSTADDRP5_Pos 8 +#define USBHS_HSTADDR2_HSTADDRP5_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP5_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP5(value) ((USBHS_HSTADDR2_HSTADDRP5_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP5_Pos))) +#define USBHS_HSTADDR2_HSTADDRP6_Pos 16 +#define USBHS_HSTADDR2_HSTADDRP6_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP6_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP6(value) ((USBHS_HSTADDR2_HSTADDRP6_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP6_Pos))) +#define USBHS_HSTADDR2_HSTADDRP7_Pos 24 +#define USBHS_HSTADDR2_HSTADDRP7_Msk (0x7fu << USBHS_HSTADDR2_HSTADDRP7_Pos) /**< \brief (USBHS_HSTADDR2) USB Host Address */ +#define USBHS_HSTADDR2_HSTADDRP7(value) ((USBHS_HSTADDR2_HSTADDRP7_Msk & ((value) << USBHS_HSTADDR2_HSTADDRP7_Pos))) +/* -------- USBHS_HSTADDR3 : (USBHS Offset: 0x042C) Host Address 3 Register -------- */ +#define USBHS_HSTADDR3_HSTADDRP8_Pos 0 +#define USBHS_HSTADDR3_HSTADDRP8_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP8_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP8(value) ((USBHS_HSTADDR3_HSTADDRP8_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP8_Pos))) +#define USBHS_HSTADDR3_HSTADDRP9_Pos 8 +#define USBHS_HSTADDR3_HSTADDRP9_Msk (0x7fu << USBHS_HSTADDR3_HSTADDRP9_Pos) /**< \brief (USBHS_HSTADDR3) USB Host Address */ +#define USBHS_HSTADDR3_HSTADDRP9(value) ((USBHS_HSTADDR3_HSTADDRP9_Msk & ((value) << USBHS_HSTADDR3_HSTADDRP9_Pos))) +/* -------- USBHS_HSTPIPCFG[10] : (USBHS Offset: 0x500) Host Pipe Configuration Register (n = 0) -------- */ +#define USBHS_HSTPIPCFG_ALLOC (0x1u << 1) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Memory Allocate */ +#define USBHS_HSTPIPCFG_PBK_Pos 2 +#define USBHS_HSTPIPCFG_PBK_Msk (0x3u << USBHS_HSTPIPCFG_PBK_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Banks */ +#define USBHS_HSTPIPCFG_PBK(value) ((USBHS_HSTPIPCFG_PBK_Msk & ((value) << USBHS_HSTPIPCFG_PBK_Pos))) +#define USBHS_HSTPIPCFG_PBK_1_BANK (0x0u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Single-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_2_BANK (0x1u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Double-bank pipe */ +#define USBHS_HSTPIPCFG_PBK_3_BANK (0x2u << 2) /**< \brief (USBHS_HSTPIPCFG[10]) Triple-bank pipe */ +#define USBHS_HSTPIPCFG_PSIZE_Pos 4 +#define USBHS_HSTPIPCFG_PSIZE_Msk (0x7u << USBHS_HSTPIPCFG_PSIZE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Size */ +#define USBHS_HSTPIPCFG_PSIZE(value) ((USBHS_HSTPIPCFG_PSIZE_Msk & ((value) << USBHS_HSTPIPCFG_PSIZE_Pos))) +#define USBHS_HSTPIPCFG_PSIZE_8_BYTE (0x0u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 8 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_16_BYTE (0x1u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 16 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_32_BYTE (0x2u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 32 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_64_BYTE (0x3u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 64 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_128_BYTE (0x4u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 128 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_256_BYTE (0x5u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 256 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_512_BYTE (0x6u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 512 bytes */ +#define USBHS_HSTPIPCFG_PSIZE_1024_BYTE (0x7u << 4) /**< \brief (USBHS_HSTPIPCFG[10]) 1024 bytes */ +#define USBHS_HSTPIPCFG_PTOKEN_Pos 8 +#define USBHS_HSTPIPCFG_PTOKEN_Msk (0x3u << USBHS_HSTPIPCFG_PTOKEN_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Token */ +#define USBHS_HSTPIPCFG_PTOKEN(value) ((USBHS_HSTPIPCFG_PTOKEN_Msk & ((value) << USBHS_HSTPIPCFG_PTOKEN_Pos))) +#define USBHS_HSTPIPCFG_PTOKEN_SETUP (0x0u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) SETUP */ +#define USBHS_HSTPIPCFG_PTOKEN_IN (0x1u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) IN */ +#define USBHS_HSTPIPCFG_PTOKEN_OUT (0x2u << 8) /**< \brief (USBHS_HSTPIPCFG[10]) OUT */ +#define USBHS_HSTPIPCFG_AUTOSW (0x1u << 10) /**< \brief (USBHS_HSTPIPCFG[10]) Automatic Switch */ +#define USBHS_HSTPIPCFG_PTYPE_Pos 12 +#define USBHS_HSTPIPCFG_PTYPE_Msk (0x3u << USBHS_HSTPIPCFG_PTYPE_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Type */ +#define USBHS_HSTPIPCFG_PTYPE(value) ((USBHS_HSTPIPCFG_PTYPE_Msk & ((value) << USBHS_HSTPIPCFG_PTYPE_Pos))) +#define USBHS_HSTPIPCFG_PTYPE_CTRL (0x0u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Control */ +#define USBHS_HSTPIPCFG_PTYPE_ISO (0x1u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Isochronous */ +#define USBHS_HSTPIPCFG_PTYPE_BLK (0x2u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Bulk */ +#define USBHS_HSTPIPCFG_PTYPE_INTRPT (0x3u << 12) /**< \brief (USBHS_HSTPIPCFG[10]) Interrupt */ +#define USBHS_HSTPIPCFG_PEPNUM_Pos 16 +#define USBHS_HSTPIPCFG_PEPNUM_Msk (0xfu << USBHS_HSTPIPCFG_PEPNUM_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Endpoint Number */ +#define USBHS_HSTPIPCFG_PEPNUM(value) ((USBHS_HSTPIPCFG_PEPNUM_Msk & ((value) << USBHS_HSTPIPCFG_PEPNUM_Pos))) +#define USBHS_HSTPIPCFG_INTFRQ_Pos 24 +#define USBHS_HSTPIPCFG_INTFRQ_Msk (0xffu << USBHS_HSTPIPCFG_INTFRQ_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Pipe Interrupt Request Frequency */ +#define USBHS_HSTPIPCFG_INTFRQ(value) ((USBHS_HSTPIPCFG_INTFRQ_Msk & ((value) << USBHS_HSTPIPCFG_INTFRQ_Pos))) +#define USBHS_HSTPIPCFG_PINGEN (0x1u << 20) /**< \brief (USBHS_HSTPIPCFG[10]) Ping Enable */ +#define USBHS_HSTPIPCFG_BINTERVAL_Pos 24 +#define USBHS_HSTPIPCFG_BINTERVAL_Msk (0xffu << USBHS_HSTPIPCFG_BINTERVAL_Pos) /**< \brief (USBHS_HSTPIPCFG[10]) Binterval Parameter for the Bulk-Out/Ping Transaction */ +#define USBHS_HSTPIPCFG_BINTERVAL(value) ((USBHS_HSTPIPCFG_BINTERVAL_Msk & ((value) << USBHS_HSTPIPCFG_BINTERVAL_Pos))) +/* -------- USBHS_HSTPIPISR[10] : (USBHS Offset: 0x530) Host Pipe Status Register (n = 0) -------- */ +#define USBHS_HSTPIPISR_RXINI (0x1u << 0) /**< \brief (USBHS_HSTPIPISR[10]) Received IN Data Interrupt */ +#define USBHS_HSTPIPISR_TXOUTI (0x1u << 1) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted OUT Data Interrupt */ +#define USBHS_HSTPIPISR_TXSTPI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Transmitted SETUP Interrupt */ +#define USBHS_HSTPIPISR_PERRI (0x1u << 3) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Error Interrupt */ +#define USBHS_HSTPIPISR_NAKEDI (0x1u << 4) /**< \brief (USBHS_HSTPIPISR[10]) NAKed Interrupt */ +#define USBHS_HSTPIPISR_OVERFI (0x1u << 5) /**< \brief (USBHS_HSTPIPISR[10]) Overflow Interrupt */ +#define USBHS_HSTPIPISR_RXSTALLDI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) Received STALLed Interrupt */ +#define USBHS_HSTPIPISR_SHORTPACKETI (0x1u << 7) /**< \brief (USBHS_HSTPIPISR[10]) Short Packet Interrupt */ +#define USBHS_HSTPIPISR_DTSEQ_Pos 8 +#define USBHS_HSTPIPISR_DTSEQ_Msk (0x3u << USBHS_HSTPIPISR_DTSEQ_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Data Toggle Sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA0 (0x0u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data0 toggle sequence */ +#define USBHS_HSTPIPISR_DTSEQ_DATA1 (0x1u << 8) /**< \brief (USBHS_HSTPIPISR[10]) Data1 toggle sequence */ +#define USBHS_HSTPIPISR_NBUSYBK_Pos 12 +#define USBHS_HSTPIPISR_NBUSYBK_Msk (0x3u << USBHS_HSTPIPISR_NBUSYBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Number of Busy Banks */ +#define USBHS_HSTPIPISR_NBUSYBK_0_BUSY (0x0u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 0 busy bank (all banks free) */ +#define USBHS_HSTPIPISR_NBUSYBK_1_BUSY (0x1u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 1 busy bank */ +#define USBHS_HSTPIPISR_NBUSYBK_2_BUSY (0x2u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 2 busy banks */ +#define USBHS_HSTPIPISR_NBUSYBK_3_BUSY (0x3u << 12) /**< \brief (USBHS_HSTPIPISR[10]) 3 busy banks */ +#define USBHS_HSTPIPISR_CURRBK_Pos 14 +#define USBHS_HSTPIPISR_CURRBK_Msk (0x3u << USBHS_HSTPIPISR_CURRBK_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Current Bank */ +#define USBHS_HSTPIPISR_CURRBK_BANK0 (0x0u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank0 */ +#define USBHS_HSTPIPISR_CURRBK_BANK1 (0x1u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank1 */ +#define USBHS_HSTPIPISR_CURRBK_BANK2 (0x2u << 14) /**< \brief (USBHS_HSTPIPISR[10]) Current bank is bank2 */ +#define USBHS_HSTPIPISR_RWALL (0x1u << 16) /**< \brief (USBHS_HSTPIPISR[10]) Read/Write Allowed */ +#define USBHS_HSTPIPISR_CFGOK (0x1u << 18) /**< \brief (USBHS_HSTPIPISR[10]) Configuration OK Status */ +#define USBHS_HSTPIPISR_PBYCT_Pos 20 +#define USBHS_HSTPIPISR_PBYCT_Msk (0x7ffu << USBHS_HSTPIPISR_PBYCT_Pos) /**< \brief (USBHS_HSTPIPISR[10]) Pipe Byte Count */ +#define USBHS_HSTPIPISR_UNDERFI (0x1u << 2) /**< \brief (USBHS_HSTPIPISR[10]) Underflow Interrupt */ +#define USBHS_HSTPIPISR_CRCERRI (0x1u << 6) /**< \brief (USBHS_HSTPIPISR[10]) CRC Error Interrupt */ +/* -------- USBHS_HSTPIPICR[10] : (USBHS Offset: 0x560) Host Pipe Clear Register (n = 0) -------- */ +#define USBHS_HSTPIPICR_RXINIC (0x1u << 0) /**< \brief (USBHS_HSTPIPICR[10]) Received IN Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXOUTIC (0x1u << 1) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted OUT Data Interrupt Clear */ +#define USBHS_HSTPIPICR_TXSTPIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Transmitted SETUP Interrupt Clear */ +#define USBHS_HSTPIPICR_NAKEDIC (0x1u << 4) /**< \brief (USBHS_HSTPIPICR[10]) NAKed Interrupt Clear */ +#define USBHS_HSTPIPICR_OVERFIC (0x1u << 5) /**< \brief (USBHS_HSTPIPICR[10]) Overflow Interrupt Clear */ +#define USBHS_HSTPIPICR_RXSTALLDIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) Received STALLed Interrupt Clear */ +#define USBHS_HSTPIPICR_SHORTPACKETIC (0x1u << 7) /**< \brief (USBHS_HSTPIPICR[10]) Short Packet Interrupt Clear */ +#define USBHS_HSTPIPICR_UNDERFIC (0x1u << 2) /**< \brief (USBHS_HSTPIPICR[10]) Underflow Interrupt Clear */ +#define USBHS_HSTPIPICR_CRCERRIC (0x1u << 6) /**< \brief (USBHS_HSTPIPICR[10]) CRC Error Interrupt Clear */ +/* -------- USBHS_HSTPIPIFR[10] : (USBHS Offset: 0x590) Host Pipe Set Register (n = 0) -------- */ +#define USBHS_HSTPIPIFR_RXINIS (0x1u << 0) /**< \brief (USBHS_HSTPIPIFR[10]) Received IN Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXOUTIS (0x1u << 1) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted OUT Data Interrupt Set */ +#define USBHS_HSTPIPIFR_TXSTPIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Transmitted SETUP Interrupt Set */ +#define USBHS_HSTPIPIFR_PERRIS (0x1u << 3) /**< \brief (USBHS_HSTPIPIFR[10]) Pipe Error Interrupt Set */ +#define USBHS_HSTPIPIFR_NAKEDIS (0x1u << 4) /**< \brief (USBHS_HSTPIPIFR[10]) NAKed Interrupt Set */ +#define USBHS_HSTPIPIFR_OVERFIS (0x1u << 5) /**< \brief (USBHS_HSTPIPIFR[10]) Overflow Interrupt Set */ +#define USBHS_HSTPIPIFR_RXSTALLDIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) Received STALLed Interrupt Set */ +#define USBHS_HSTPIPIFR_SHORTPACKETIS (0x1u << 7) /**< \brief (USBHS_HSTPIPIFR[10]) Short Packet Interrupt Set */ +#define USBHS_HSTPIPIFR_NBUSYBKS (0x1u << 12) /**< \brief (USBHS_HSTPIPIFR[10]) Number of Busy Banks Set */ +#define USBHS_HSTPIPIFR_UNDERFIS (0x1u << 2) /**< \brief (USBHS_HSTPIPIFR[10]) Underflow Interrupt Set */ +#define USBHS_HSTPIPIFR_CRCERRIS (0x1u << 6) /**< \brief (USBHS_HSTPIPIFR[10]) CRC Error Interrupt Set */ +/* -------- USBHS_HSTPIPIMR[10] : (USBHS Offset: 0x5C0) Host Pipe Mask Register (n = 0) -------- */ +#define USBHS_HSTPIPIMR_RXINE (0x1u << 0) /**< \brief (USBHS_HSTPIPIMR[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXOUTE (0x1u << 1) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIMR_TXSTPE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIMR_PERRE (0x1u << 3) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIMR_NAKEDE (0x1u << 4) /**< \brief (USBHS_HSTPIPIMR[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIMR_OVERFIE (0x1u << 5) /**< \brief (USBHS_HSTPIPIMR[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_RXSTALLDE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIMR_SHORTPACKETIE (0x1u << 7) /**< \brief (USBHS_HSTPIPIMR[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIMR_NBUSYBKE (0x1u << 12) /**< \brief (USBHS_HSTPIPIMR[10]) Number of Busy Banks Interrupt Enable */ +#define USBHS_HSTPIPIMR_FIFOCON (0x1u << 14) /**< \brief (USBHS_HSTPIPIMR[10]) FIFO Control */ +#define USBHS_HSTPIPIMR_PDISHDMA (0x1u << 16) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIMR_PFREEZE (0x1u << 17) /**< \brief (USBHS_HSTPIPIMR[10]) Pipe Freeze */ +#define USBHS_HSTPIPIMR_RSTDT (0x1u << 18) /**< \brief (USBHS_HSTPIPIMR[10]) Reset Data Toggle */ +#define USBHS_HSTPIPIMR_UNDERFIE (0x1u << 2) /**< \brief (USBHS_HSTPIPIMR[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIMR_CRCERRE (0x1u << 6) /**< \brief (USBHS_HSTPIPIMR[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIER[10] : (USBHS Offset: 0x5F0) Host Pipe Enable Register (n = 0) -------- */ +#define USBHS_HSTPIPIER_RXINES (0x1u << 0) /**< \brief (USBHS_HSTPIPIER[10]) Received IN Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXOUTES (0x1u << 1) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted OUT Data Interrupt Enable */ +#define USBHS_HSTPIPIER_TXSTPES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Transmitted SETUP Interrupt Enable */ +#define USBHS_HSTPIPIER_PERRES (0x1u << 3) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Error Interrupt Enable */ +#define USBHS_HSTPIPIER_NAKEDES (0x1u << 4) /**< \brief (USBHS_HSTPIPIER[10]) NAKed Interrupt Enable */ +#define USBHS_HSTPIPIER_OVERFIES (0x1u << 5) /**< \brief (USBHS_HSTPIPIER[10]) Overflow Interrupt Enable */ +#define USBHS_HSTPIPIER_RXSTALLDES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) Received STALLed Interrupt Enable */ +#define USBHS_HSTPIPIER_SHORTPACKETIES (0x1u << 7) /**< \brief (USBHS_HSTPIPIER[10]) Short Packet Interrupt Enable */ +#define USBHS_HSTPIPIER_NBUSYBKES (0x1u << 12) /**< \brief (USBHS_HSTPIPIER[10]) Number of Busy Banks Enable */ +#define USBHS_HSTPIPIER_PDISHDMAS (0x1u << 16) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Interrupts Disable HDMA Request Enable */ +#define USBHS_HSTPIPIER_PFREEZES (0x1u << 17) /**< \brief (USBHS_HSTPIPIER[10]) Pipe Freeze Enable */ +#define USBHS_HSTPIPIER_RSTDTS (0x1u << 18) /**< \brief (USBHS_HSTPIPIER[10]) Reset Data Toggle Enable */ +#define USBHS_HSTPIPIER_UNDERFIES (0x1u << 2) /**< \brief (USBHS_HSTPIPIER[10]) Underflow Interrupt Enable */ +#define USBHS_HSTPIPIER_CRCERRES (0x1u << 6) /**< \brief (USBHS_HSTPIPIER[10]) CRC Error Interrupt Enable */ +/* -------- USBHS_HSTPIPIDR[10] : (USBHS Offset: 0x620) Host Pipe Disable Register (n = 0) -------- */ +#define USBHS_HSTPIPIDR_RXINEC (0x1u << 0) /**< \brief (USBHS_HSTPIPIDR[10]) Received IN Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXOUTEC (0x1u << 1) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted OUT Data Interrupt Disable */ +#define USBHS_HSTPIPIDR_TXSTPEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Transmitted SETUP Interrupt Disable */ +#define USBHS_HSTPIPIDR_PERREC (0x1u << 3) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Error Interrupt Disable */ +#define USBHS_HSTPIPIDR_NAKEDEC (0x1u << 4) /**< \brief (USBHS_HSTPIPIDR[10]) NAKed Interrupt Disable */ +#define USBHS_HSTPIPIDR_OVERFIEC (0x1u << 5) /**< \brief (USBHS_HSTPIPIDR[10]) Overflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_RXSTALLDEC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) Received STALLed Interrupt Disable */ +#define USBHS_HSTPIPIDR_SHORTPACKETIEC (0x1u << 7) /**< \brief (USBHS_HSTPIPIDR[10]) Short Packet Interrupt Disable */ +#define USBHS_HSTPIPIDR_NBUSYBKEC (0x1u << 12) /**< \brief (USBHS_HSTPIPIDR[10]) Number of Busy Banks Disable */ +#define USBHS_HSTPIPIDR_FIFOCONC (0x1u << 14) /**< \brief (USBHS_HSTPIPIDR[10]) FIFO Control Disable */ +#define USBHS_HSTPIPIDR_PDISHDMAC (0x1u << 16) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Interrupts Disable HDMA Request Disable */ +#define USBHS_HSTPIPIDR_PFREEZEC (0x1u << 17) /**< \brief (USBHS_HSTPIPIDR[10]) Pipe Freeze Disable */ +#define USBHS_HSTPIPIDR_UNDERFIEC (0x1u << 2) /**< \brief (USBHS_HSTPIPIDR[10]) Underflow Interrupt Disable */ +#define USBHS_HSTPIPIDR_CRCERREC (0x1u << 6) /**< \brief (USBHS_HSTPIPIDR[10]) CRC Error Interrupt Disable */ +/* -------- USBHS_HSTPIPINRQ[10] : (USBHS Offset: 0x650) Host Pipe IN Request Register (n = 0) -------- */ +#define USBHS_HSTPIPINRQ_INRQ_Pos 0 +#define USBHS_HSTPIPINRQ_INRQ_Msk (0xffu << USBHS_HSTPIPINRQ_INRQ_Pos) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Number before Freeze */ +#define USBHS_HSTPIPINRQ_INRQ(value) ((USBHS_HSTPIPINRQ_INRQ_Msk & ((value) << USBHS_HSTPIPINRQ_INRQ_Pos))) +#define USBHS_HSTPIPINRQ_INMODE (0x1u << 8) /**< \brief (USBHS_HSTPIPINRQ[10]) IN Request Mode */ +/* -------- USBHS_HSTPIPERR[10] : (USBHS Offset: 0x680) Host Pipe Error Register (n = 0) -------- */ +#define USBHS_HSTPIPERR_DATATGL (0x1u << 0) /**< \brief (USBHS_HSTPIPERR[10]) Data Toggle Error */ +#define USBHS_HSTPIPERR_DATAPID (0x1u << 1) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_PID (0x1u << 2) /**< \brief (USBHS_HSTPIPERR[10]) Data PID Error */ +#define USBHS_HSTPIPERR_TIMEOUT (0x1u << 3) /**< \brief (USBHS_HSTPIPERR[10]) Time-Out Error */ +#define USBHS_HSTPIPERR_CRC16 (0x1u << 4) /**< \brief (USBHS_HSTPIPERR[10]) CRC16 Error */ +#define USBHS_HSTPIPERR_COUNTER_Pos 5 +#define USBHS_HSTPIPERR_COUNTER_Msk (0x3u << USBHS_HSTPIPERR_COUNTER_Pos) /**< \brief (USBHS_HSTPIPERR[10]) Error Counter */ +#define USBHS_HSTPIPERR_COUNTER(value) ((USBHS_HSTPIPERR_COUNTER_Msk & ((value) << USBHS_HSTPIPERR_COUNTER_Pos))) +/* -------- USBHS_HSTDMANXTDSC : (USBHS Offset: N/A) Host DMA Channel Next Descriptor Address Register -------- */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos 0 +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk (0xffffffffu << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos) /**< \brief (USBHS_HSTDMANXTDSC) Next Descriptor Address */ +#define USBHS_HSTDMANXTDSC_NXT_DSC_ADD(value) ((USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Msk & ((value) << USBHS_HSTDMANXTDSC_NXT_DSC_ADD_Pos))) +/* -------- USBHS_HSTDMAADDRESS : (USBHS Offset: N/A) Host DMA Channel Address Register -------- */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Pos 0 +#define USBHS_HSTDMAADDRESS_BUFF_ADD_Msk (0xffffffffu << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos) /**< \brief (USBHS_HSTDMAADDRESS) Buffer Address */ +#define USBHS_HSTDMAADDRESS_BUFF_ADD(value) ((USBHS_HSTDMAADDRESS_BUFF_ADD_Msk & ((value) << USBHS_HSTDMAADDRESS_BUFF_ADD_Pos))) +/* -------- USBHS_HSTDMACONTROL : (USBHS Offset: N/A) Host DMA Channel Control Register -------- */ +#define USBHS_HSTDMACONTROL_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMACONTROL) Channel Enable Command */ +#define USBHS_HSTDMACONTROL_LDNXT_DSC (0x1u << 1) /**< \brief (USBHS_HSTDMACONTROL) Load Next Channel Transfer Descriptor Enable Command */ +#define USBHS_HSTDMACONTROL_END_TR_EN (0x1u << 2) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Enable Control (OUT transfers only) */ +#define USBHS_HSTDMACONTROL_END_B_EN (0x1u << 3) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Enable Control */ +#define USBHS_HSTDMACONTROL_END_TR_IT (0x1u << 4) /**< \brief (USBHS_HSTDMACONTROL) End of Transfer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_END_BUFFIT (0x1u << 5) /**< \brief (USBHS_HSTDMACONTROL) End of Buffer Interrupt Enable */ +#define USBHS_HSTDMACONTROL_DESC_LD_IT (0x1u << 6) /**< \brief (USBHS_HSTDMACONTROL) Descriptor Loaded Interrupt Enable */ +#define USBHS_HSTDMACONTROL_BURST_LCK (0x1u << 7) /**< \brief (USBHS_HSTDMACONTROL) Burst Lock Enable */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos 16 +#define USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk (0xffffu << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos) /**< \brief (USBHS_HSTDMACONTROL) Buffer Byte Length (Write-only) */ +#define USBHS_HSTDMACONTROL_BUFF_LENGTH(value) ((USBHS_HSTDMACONTROL_BUFF_LENGTH_Msk & ((value) << USBHS_HSTDMACONTROL_BUFF_LENGTH_Pos))) +/* -------- USBHS_HSTDMASTATUS : (USBHS Offset: N/A) Host DMA Channel Status Register -------- */ +#define USBHS_HSTDMASTATUS_CHANN_ENB (0x1u << 0) /**< \brief (USBHS_HSTDMASTATUS) Channel Enable Status */ +#define USBHS_HSTDMASTATUS_CHANN_ACT (0x1u << 1) /**< \brief (USBHS_HSTDMASTATUS) Channel Active Status */ +#define USBHS_HSTDMASTATUS_END_TR_ST (0x1u << 4) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Transfer Status */ +#define USBHS_HSTDMASTATUS_END_BF_ST (0x1u << 5) /**< \brief (USBHS_HSTDMASTATUS) End of Channel Buffer Status */ +#define USBHS_HSTDMASTATUS_DESC_LDST (0x1u << 6) /**< \brief (USBHS_HSTDMASTATUS) Descriptor Loaded Status */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Pos 16 +#define USBHS_HSTDMASTATUS_BUFF_COUNT_Msk (0xffffu << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos) /**< \brief (USBHS_HSTDMASTATUS) Buffer Byte Count */ +#define USBHS_HSTDMASTATUS_BUFF_COUNT(value) ((USBHS_HSTDMASTATUS_BUFF_COUNT_Msk & ((value) << USBHS_HSTDMASTATUS_BUFF_COUNT_Pos))) +/* -------- USBHS_CTRL : (USBHS Offset: 0x0800) General Control Register -------- */ +#define USBHS_CTRL_RDERRE (0x1u << 4) /**< \brief (USBHS_CTRL) Remote Device Connection Error Interrupt Enable */ +#define USBHS_CTRL_FRZCLK (0x1u << 14) /**< \brief (USBHS_CTRL) Freeze USB Clock */ +#define USBHS_CTRL_USBE (0x1u << 15) /**< \brief (USBHS_CTRL) USBHS Enable */ +#define USBHS_CTRL_UIMOD (0x1u << 25) /**< \brief (USBHS_CTRL) USBHS Mode */ +#define USBHS_CTRL_UIMOD_HOST (0x0u << 25) /**< \brief (USBHS_CTRL) The module is in USB Host mode. */ +#define USBHS_CTRL_UIMOD_DEVICE (0x1u << 25) /**< \brief (USBHS_CTRL) The module is in USB Device mode. */ +/* -------- USBHS_SR : (USBHS Offset: 0x0804) General Status Register -------- */ +#define USBHS_SR_RDERRI (0x1u << 4) /**< \brief (USBHS_SR) Remote Device Connection Error Interrupt (Host mode only) */ +#define USBHS_SR_VBUSRQ (0x1u << 9) /**< \brief (USBHS_SR) VBus Request (Host mode only) */ +#define USBHS_SR_SPEED_Pos 12 +#define USBHS_SR_SPEED_Msk (0x3u << USBHS_SR_SPEED_Pos) /**< \brief (USBHS_SR) Speed Status (Device mode only) */ +#define USBHS_SR_SPEED_FULL_SPEED (0x0u << 12) /**< \brief (USBHS_SR) Full-Speed mode */ +#define USBHS_SR_SPEED_HIGH_SPEED (0x1u << 12) /**< \brief (USBHS_SR) High-Speed mode */ +#define USBHS_SR_SPEED_LOW_SPEED (0x2u << 12) /**< \brief (USBHS_SR) Low-Speed mode */ +#define USBHS_SR_CLKUSABLE (0x1u << 14) /**< \brief (USBHS_SR) UTMI Clock Usable */ +/* -------- USBHS_SCR : (USBHS Offset: 0x0808) General Status Clear Register -------- */ +#define USBHS_SCR_RDERRIC (0x1u << 4) /**< \brief (USBHS_SCR) Remote Device Connection Error Interrupt Clear */ +#define USBHS_SCR_VBUSRQC (0x1u << 9) /**< \brief (USBHS_SCR) VBus Request Clear */ +/* -------- USBHS_SFR : (USBHS Offset: 0x080C) General Status Set Register -------- */ +#define USBHS_SFR_RDERRIS (0x1u << 4) /**< \brief (USBHS_SFR) Remote Device Connection Error Interrupt Set */ +#define USBHS_SFR_VBUSRQS (0x1u << 9) /**< \brief (USBHS_SFR) VBus Request Set */ +/* -------- USBHS_TSTA1 : (USBHS Offset: 0x0810) General Test A1 Register -------- */ +#define USBHS_TSTA1_CounterA_Pos 0 +#define USBHS_TSTA1_CounterA_Msk (0x7fffu << USBHS_TSTA1_CounterA_Pos) /**< \brief (USBHS_TSTA1) Counter A */ +#define USBHS_TSTA1_CounterA(value) ((USBHS_TSTA1_CounterA_Msk & ((value) << USBHS_TSTA1_CounterA_Pos))) +#define USBHS_TSTA1_LoadCntA (0x1u << 15) /**< \brief (USBHS_TSTA1) Load CounterA */ +#define USBHS_TSTA1_CounterB_Pos 16 +#define USBHS_TSTA1_CounterB_Msk (0x3fu << USBHS_TSTA1_CounterB_Pos) /**< \brief (USBHS_TSTA1) Counter B */ +#define USBHS_TSTA1_CounterB(value) ((USBHS_TSTA1_CounterB_Msk & ((value) << USBHS_TSTA1_CounterB_Pos))) +#define USBHS_TSTA1_LoadCntB (0x1u << 23) /**< \brief (USBHS_TSTA1) Load CounterB */ +#define USBHS_TSTA1_SOFCntMa1_Pos 24 +#define USBHS_TSTA1_SOFCntMa1_Msk (0x7fu << USBHS_TSTA1_SOFCntMa1_Pos) /**< \brief (USBHS_TSTA1) SOF Counter Max */ +#define USBHS_TSTA1_SOFCntMa1(value) ((USBHS_TSTA1_SOFCntMa1_Msk & ((value) << USBHS_TSTA1_SOFCntMa1_Pos))) +#define USBHS_TSTA1_LoadSOFCnt (0x1u << 31) /**< \brief (USBHS_TSTA1) Load SOF Counter */ +/* -------- USBHS_TSTA2 : (USBHS Offset: 0x0814) General Test A2 Register -------- */ +#define USBHS_TSTA2_FullDetachEn (0x1u << 0) /**< \brief (USBHS_TSTA2) Full Detach Enable */ +#define USBHS_TSTA2_HSSerialMode (0x1u << 1) /**< \brief (USBHS_TSTA2) HS Serial Mode */ +#define USBHS_TSTA2_LoopBackMode (0x1u << 2) /**< \brief (USBHS_TSTA2) Loop-back Mode */ +#define USBHS_TSTA2_DisableGatedClock (0x1u << 3) /**< \brief (USBHS_TSTA2) Disable Gated Clock */ +#define USBHS_TSTA2_ForceSuspendMTo1 (0x1u << 4) /**< \brief (USBHS_TSTA2) Force SuspendM to 1 */ +#define USBHS_TSTA2_ByPassDpll (0x1u << 5) /**< \brief (USBHS_TSTA2) Bypass DPLL */ +#define USBHS_TSTA2_HostHSDisconnectDisable (0x1u << 6) /**< \brief (USBHS_TSTA2) Host HS Disconnect Disable */ +#define USBHS_TSTA2_ForceHSRst_50ms (0x1u << 7) /**< \brief (USBHS_TSTA2) Force HS Reset to 50 ms */ +#define USBHS_TSTA2_RemovePUWhenTX (0x1u << 9) /**< \brief (USBHS_TSTA2) Remove Pull-up When TX */ +/* -------- USBHS_VERSION : (USBHS Offset: 0x0818) General Version Register -------- */ +#define USBHS_VERSION_VERSION_Pos 0 +#define USBHS_VERSION_VERSION_Msk (0xfffu << USBHS_VERSION_VERSION_Pos) /**< \brief (USBHS_VERSION) Version Number */ +#define USBHS_VERSION_MFN_Pos 16 +#define USBHS_VERSION_MFN_Msk (0xfu << USBHS_VERSION_MFN_Pos) /**< \brief (USBHS_VERSION) Metal Fix Number */ +/* -------- USBHS_FSM : (USBHS Offset: 0x082C) General Finite State Machine Register -------- */ +#define USBHS_FSM_DRDSTATE_Pos 0 +#define USBHS_FSM_DRDSTATE_Msk (0xfu << USBHS_FSM_DRDSTATE_Pos) /**< \brief (USBHS_FSM) Dual Role Device State */ +#define USBHS_FSM_DRDSTATE_A_IDLESTATE (0x0u << 0) /**< \brief (USBHS_FSM) This is the start state for A-devices (when the ID pin is 0) */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VRISE (0x1u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to rise above the A-device VBus Valid threshold (4.4 V). */ +#define USBHS_FSM_DRDSTATE_A_WAIT_BCON (0x2u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the B-device to signal a connection. */ +#define USBHS_FSM_DRDSTATE_A_HOST (0x3u << 0) /**< \brief (USBHS_FSM) In this state, the A-device that operates in Host mode is operational. */ +#define USBHS_FSM_DRDSTATE_A_SUSPEND (0x4u << 0) /**< \brief (USBHS_FSM) The A-device operating as a host is in the Suspend mode. */ +#define USBHS_FSM_DRDSTATE_A_PERIPHERAL (0x5u << 0) /**< \brief (USBHS_FSM) The A-device operates as a peripheral. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_VFALL (0x6u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the voltage on VBus to drop below the A-device Session Valid threshold (1.4 V). */ +#define USBHS_FSM_DRDSTATE_A_VBUS_ERR (0x7u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for recovery of the over-current condition that caused it to enter this state. */ +#define USBHS_FSM_DRDSTATE_A_WAIT_DISCHARGE (0x8u << 0) /**< \brief (USBHS_FSM) In this state, the A-device waits for the data USB line to discharge (100 us). */ +#define USBHS_FSM_DRDSTATE_B_IDLE (0x9u << 0) /**< \brief (USBHS_FSM) This is the start state for B-device (when the ID pin is 1). */ +#define USBHS_FSM_DRDSTATE_B_PERIPHERAL (0xAu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the peripheral. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_BEGIN_HNP (0xBu << 0) /**< \brief (USBHS_FSM) In this state, the B-device is in Suspend mode and waits until 3 ms before initiating the HNP protocol if requested. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_DISCHARGE (0xCu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the data USB line to discharge (100 us)) before becoming Host. */ +#define USBHS_FSM_DRDSTATE_B_WAIT_ACON (0xDu << 0) /**< \brief (USBHS_FSM) In this state, the B-device waits for the A-device to signal a connect before becoming B-Host. */ +#define USBHS_FSM_DRDSTATE_B_HOST (0xEu << 0) /**< \brief (USBHS_FSM) In this state, the B-device acts as the Host. */ +#define USBHS_FSM_DRDSTATE_B_SRP_INIT (0xFu << 0) /**< \brief (USBHS_FSM) In this state, the B-device attempts to start a session using the SRP protocol. */ + +/*@}*/ + + +#endif /* _SAMV71_USBHS_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_utmi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_utmi.h new file mode 100644 index 000000000..639bd632e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_utmi.h @@ -0,0 +1,63 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UTMI_COMPONENT_ +#define _SAMV71_UTMI_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR USB Transmitter Interface Macrocell */ +/* ============================================================================= */ +/** \addtogroup SAMV71_UTMI USB Transmitter Interface Macrocell */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Utmi hardware registers */ +typedef struct { + __I uint32_t Reserved1[4]; + __IO uint32_t UTMI_OHCIICR; /**< \brief (Utmi Offset: 0x10) OHCI Interrupt Configuration Register */ + __I uint32_t Reserved2[7]; + __IO uint32_t UTMI_CKTRIM; /**< \brief (Utmi Offset: 0x30) UTMI Clock Trimming Register */ +} Utmi; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- UTMI_OHCIICR : (UTMI Offset: 0x10) OHCI Interrupt Configuration Register -------- */ +#define UTMI_OHCIICR_RES0 (0x1u << 0) /**< \brief (UTMI_OHCIICR) USB PORTx Reset */ +#define UTMI_OHCIICR_ARIE (0x1u << 4) /**< \brief (UTMI_OHCIICR) OHCI Asynchronous Resume Interrupt Enable */ +#define UTMI_OHCIICR_APPSTART (0x1u << 5) /**< \brief (UTMI_OHCIICR) Reserved */ +#define UTMI_OHCIICR_UDPPUDIS (0x1u << 23) /**< \brief (UTMI_OHCIICR) USB Device Pull-up Disable */ +/* -------- UTMI_CKTRIM : (UTMI Offset: 0x30) UTMI Clock Trimming Register -------- */ +#define UTMI_CKTRIM_FREQ_Pos 0 +#define UTMI_CKTRIM_FREQ_Msk (0x3u << UTMI_CKTRIM_FREQ_Pos) /**< \brief (UTMI_CKTRIM) UTMI Reference Clock Frequency */ +#define UTMI_CKTRIM_FREQ(value) ((UTMI_CKTRIM_FREQ_Msk & ((value) << UTMI_CKTRIM_FREQ_Pos))) +#define UTMI_CKTRIM_FREQ_XTAL12 (0x0u << 0) /**< \brief (UTMI_CKTRIM) 12 MHz reference clock */ +#define UTMI_CKTRIM_FREQ_XTAL16 (0x1u << 0) /**< \brief (UTMI_CKTRIM) 16 MHz reference clock */ + +/*@}*/ + + +#endif /* _SAMV71_UTMI_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_wdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_wdt.h new file mode 100644 index 000000000..8fe53440f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_wdt.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_WDT_COMPONENT_ +#define _SAMV71_WDT_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Watchdog Timer */ +/* ============================================================================= */ +/** \addtogroup SAMV71_WDT Watchdog Timer */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief Wdt hardware registers */ +typedef struct { + __O uint32_t WDT_CR; /**< \brief (Wdt Offset: 0x00) Control Register */ + __IO uint32_t WDT_MR; /**< \brief (Wdt Offset: 0x04) Mode Register */ + __I uint32_t WDT_SR; /**< \brief (Wdt Offset: 0x08) Status Register */ +} Wdt; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- WDT_CR : (WDT Offset: 0x00) Control Register -------- */ +#define WDT_CR_WDRSTT (0x1u << 0) /**< \brief (WDT_CR) Watchdog Restart */ +#define WDT_CR_KEY_Pos 24 +#define WDT_CR_KEY_Msk (0xffu << WDT_CR_KEY_Pos) /**< \brief (WDT_CR) Password */ +#define WDT_CR_KEY(value) ((WDT_CR_KEY_Msk & ((value) << WDT_CR_KEY_Pos))) +#define WDT_CR_KEY_PASSWD (0xA5u << 24) /**< \brief (WDT_CR) Writing any other value in this field aborts the write operation. */ +/* -------- WDT_MR : (WDT Offset: 0x04) Mode Register -------- */ +#define WDT_MR_WDV_Pos 0 +#define WDT_MR_WDV_Msk (0xfffu << WDT_MR_WDV_Pos) /**< \brief (WDT_MR) Watchdog Counter Value */ +#define WDT_MR_WDV(value) ((WDT_MR_WDV_Msk & ((value) << WDT_MR_WDV_Pos))) +#define WDT_MR_WDFIEN (0x1u << 12) /**< \brief (WDT_MR) Watchdog Fault Interrupt Enable */ +#define WDT_MR_WDRSTEN (0x1u << 13) /**< \brief (WDT_MR) Watchdog Reset Enable */ +#define WDT_MR_WDDIS (0x1u << 15) /**< \brief (WDT_MR) Watchdog Disable */ +#define WDT_MR_WDD_Pos 16 +#define WDT_MR_WDD_Msk (0xfffu << WDT_MR_WDD_Pos) /**< \brief (WDT_MR) Watchdog Delta Value */ +#define WDT_MR_WDD(value) ((WDT_MR_WDD_Msk & ((value) << WDT_MR_WDD_Pos))) +#define WDT_MR_WDDBGHLT (0x1u << 28) /**< \brief (WDT_MR) Watchdog Debug Halt */ +#define WDT_MR_WDIDLEHLT (0x1u << 29) /**< \brief (WDT_MR) Watchdog Idle Halt */ +/* -------- WDT_SR : (WDT Offset: 0x08) Status Register -------- */ +#define WDT_SR_WDUNF (0x1u << 0) /**< \brief (WDT_SR) Watchdog Underflow (cleared on read) */ +#define WDT_SR_WDERR (0x1u << 1) /**< \brief (WDT_SR) Watchdog Error (cleared on read) */ + +/*@}*/ + + +#endif /* _SAMV71_WDT_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_xdmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_xdmac.h new file mode 100644 index 000000000..af86f86a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/component/component_xdmac.h @@ -0,0 +1,619 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_XDMAC_COMPONENT_ +#define _SAMV71_XDMAC_COMPONENT_ + +/* ============================================================================= */ +/** SOFTWARE API DEFINITION FOR Extensible DMA Controller */ +/* ============================================================================= */ +/** \addtogroup SAMV71_XDMAC Extensible DMA Controller */ +/*@{*/ + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/** \brief XdmacChid hardware registers */ +typedef struct { + __O uint32_t XDMAC_CIE; /**< \brief (XdmacChid Offset: 0x0) Channel Interrupt Enable Register */ + __O uint32_t XDMAC_CID; /**< \brief (XdmacChid Offset: 0x4) Channel Interrupt Disable Register */ + __O uint32_t XDMAC_CIM; /**< \brief (XdmacChid Offset: 0x8) Channel Interrupt Mask Register */ + __I uint32_t XDMAC_CIS; /**< \brief (XdmacChid Offset: 0xC) Channel Interrupt Status Register */ + __IO uint32_t XDMAC_CSA; /**< \brief (XdmacChid Offset: 0x10) Channel Source Address Register */ + __IO uint32_t XDMAC_CDA; /**< \brief (XdmacChid Offset: 0x14) Channel Destination Address Register */ + __IO uint32_t XDMAC_CNDA; /**< \brief (XdmacChid Offset: 0x18) Channel Next Descriptor Address Register */ + __IO uint32_t XDMAC_CNDC; /**< \brief (XdmacChid Offset: 0x1C) Channel Next Descriptor Control Register */ + __IO uint32_t XDMAC_CUBC; /**< \brief (XdmacChid Offset: 0x20) Channel Microblock Control Register */ + __IO uint32_t XDMAC_CBC; /**< \brief (XdmacChid Offset: 0x24) Channel Block Control Register */ + __IO uint32_t XDMAC_CC; /**< \brief (XdmacChid Offset: 0x28) Channel Configuration Register */ + __IO uint32_t XDMAC_CDS_MSP; /**< \brief (XdmacChid Offset: 0x2C) Channel Data Stride Memory Set Pattern */ + __IO uint32_t XDMAC_CSUS; /**< \brief (XdmacChid Offset: 0x30) Channel Source Microblock Stride */ + __IO uint32_t XDMAC_CDUS; /**< \brief (XdmacChid Offset: 0x34) Channel Destination Microblock Stride */ + __I uint32_t Reserved1[2]; +} XdmacChid; +/** \brief Xdmac hardware registers */ +#define XDMACCHID_NUMBER 24 +typedef struct { + __IO uint32_t XDMAC_GTYPE; /**< \brief (Xdmac Offset: 0x00) Global Type Register */ + __I uint32_t XDMAC_GCFG; /**< \brief (Xdmac Offset: 0x04) Global Configuration Register */ + __IO uint32_t XDMAC_GWAC; /**< \brief (Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register */ + __O uint32_t XDMAC_GIE; /**< \brief (Xdmac Offset: 0x0C) Global Interrupt Enable Register */ + __O uint32_t XDMAC_GID; /**< \brief (Xdmac Offset: 0x10) Global Interrupt Disable Register */ + __I uint32_t XDMAC_GIM; /**< \brief (Xdmac Offset: 0x14) Global Interrupt Mask Register */ + __I uint32_t XDMAC_GIS; /**< \brief (Xdmac Offset: 0x18) Global Interrupt Status Register */ + __O uint32_t XDMAC_GE; /**< \brief (Xdmac Offset: 0x1C) Global Channel Enable Register */ + __O uint32_t XDMAC_GD; /**< \brief (Xdmac Offset: 0x20) Global Channel Disable Register */ + __I uint32_t XDMAC_GS; /**< \brief (Xdmac Offset: 0x24) Global Channel Status Register */ + __IO uint32_t XDMAC_GRS; /**< \brief (Xdmac Offset: 0x28) Global Channel Read Suspend Register */ + __IO uint32_t XDMAC_GWS; /**< \brief (Xdmac Offset: 0x2C) Global Channel Write Suspend Register */ + __O uint32_t XDMAC_GRWS; /**< \brief (Xdmac Offset: 0x30) Global Channel Read Write Suspend Register */ + __O uint32_t XDMAC_GRWR; /**< \brief (Xdmac Offset: 0x34) Global Channel Read Write Resume Register */ + __O uint32_t XDMAC_GSWR; /**< \brief (Xdmac Offset: 0x38) Global Channel Software Request Register */ + __I uint32_t XDMAC_GSWS; /**< \brief (Xdmac Offset: 0x3C) Global Channel Software Request Status Register */ + __O uint32_t XDMAC_GSWF; /**< \brief (Xdmac Offset: 0x40) Global Channel Software Flush Request Register */ + __I uint32_t Reserved1[3]; + XdmacChid XDMAC_CHID[XDMACCHID_NUMBER]; /**< \brief (Xdmac Offset: 0x50) chid = 0 .. 23 */ +} Xdmac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/* -------- XDMAC_GTYPE : (XDMAC Offset: 0x00) Global Type Register -------- */ +#define XDMAC_GTYPE_NB_CH_Pos 0 +#define XDMAC_GTYPE_NB_CH_Msk (0x1fu << XDMAC_GTYPE_NB_CH_Pos) /**< \brief (XDMAC_GTYPE) Number of Channels Minus One */ +#define XDMAC_GTYPE_NB_CH(value) ((XDMAC_GTYPE_NB_CH_Msk & ((value) << XDMAC_GTYPE_NB_CH_Pos))) +#define XDMAC_GTYPE_FIFO_SZ_Pos 5 +#define XDMAC_GTYPE_FIFO_SZ_Msk (0x7ffu << XDMAC_GTYPE_FIFO_SZ_Pos) /**< \brief (XDMAC_GTYPE) Number of Bytes */ +#define XDMAC_GTYPE_FIFO_SZ(value) ((XDMAC_GTYPE_FIFO_SZ_Msk & ((value) << XDMAC_GTYPE_FIFO_SZ_Pos))) +#define XDMAC_GTYPE_NB_REQ_Pos 16 +#define XDMAC_GTYPE_NB_REQ_Msk (0x7fu << XDMAC_GTYPE_NB_REQ_Pos) /**< \brief (XDMAC_GTYPE) Number of Peripheral Requests Minus One */ +#define XDMAC_GTYPE_NB_REQ(value) ((XDMAC_GTYPE_NB_REQ_Msk & ((value) << XDMAC_GTYPE_NB_REQ_Pos))) +/* -------- XDMAC_GCFG : (XDMAC Offset: 0x04) Global Configuration Register -------- */ +#define XDMAC_GCFG_CGDISREG (0x1u << 0) /**< \brief (XDMAC_GCFG) Configuration Registers Clock Gating Disable */ +#define XDMAC_GCFG_CGDISPIPE (0x1u << 1) /**< \brief (XDMAC_GCFG) Pipeline Clock Gating Disable */ +#define XDMAC_GCFG_CGDISFIFO (0x1u << 2) /**< \brief (XDMAC_GCFG) FIFO Clock Gating Disable */ +#define XDMAC_GCFG_CGDISIF (0x1u << 3) /**< \brief (XDMAC_GCFG) Bus Interface Clock Gating Disable */ +#define XDMAC_GCFG_BXKBEN (0x1u << 8) /**< \brief (XDMAC_GCFG) Boundary X Kilo byte Enable */ +/* -------- XDMAC_GWAC : (XDMAC Offset: 0x08) Global Weighted Arbiter Configuration Register -------- */ +#define XDMAC_GWAC_PW0_Pos 0 +#define XDMAC_GWAC_PW0_Msk (0xfu << XDMAC_GWAC_PW0_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 0 */ +#define XDMAC_GWAC_PW0(value) ((XDMAC_GWAC_PW0_Msk & ((value) << XDMAC_GWAC_PW0_Pos))) +#define XDMAC_GWAC_PW1_Pos 4 +#define XDMAC_GWAC_PW1_Msk (0xfu << XDMAC_GWAC_PW1_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 1 */ +#define XDMAC_GWAC_PW1(value) ((XDMAC_GWAC_PW1_Msk & ((value) << XDMAC_GWAC_PW1_Pos))) +#define XDMAC_GWAC_PW2_Pos 8 +#define XDMAC_GWAC_PW2_Msk (0xfu << XDMAC_GWAC_PW2_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 2 */ +#define XDMAC_GWAC_PW2(value) ((XDMAC_GWAC_PW2_Msk & ((value) << XDMAC_GWAC_PW2_Pos))) +#define XDMAC_GWAC_PW3_Pos 12 +#define XDMAC_GWAC_PW3_Msk (0xfu << XDMAC_GWAC_PW3_Pos) /**< \brief (XDMAC_GWAC) Pool Weight 3 */ +#define XDMAC_GWAC_PW3(value) ((XDMAC_GWAC_PW3_Msk & ((value) << XDMAC_GWAC_PW3_Pos))) +/* -------- XDMAC_GIE : (XDMAC Offset: 0x0C) Global Interrupt Enable Register -------- */ +#define XDMAC_GIE_IE0 (0x1u << 0) /**< \brief (XDMAC_GIE) XDMAC Channel 0 Interrupt Enable Bit */ +#define XDMAC_GIE_IE1 (0x1u << 1) /**< \brief (XDMAC_GIE) XDMAC Channel 1 Interrupt Enable Bit */ +#define XDMAC_GIE_IE2 (0x1u << 2) /**< \brief (XDMAC_GIE) XDMAC Channel 2 Interrupt Enable Bit */ +#define XDMAC_GIE_IE3 (0x1u << 3) /**< \brief (XDMAC_GIE) XDMAC Channel 3 Interrupt Enable Bit */ +#define XDMAC_GIE_IE4 (0x1u << 4) /**< \brief (XDMAC_GIE) XDMAC Channel 4 Interrupt Enable Bit */ +#define XDMAC_GIE_IE5 (0x1u << 5) /**< \brief (XDMAC_GIE) XDMAC Channel 5 Interrupt Enable Bit */ +#define XDMAC_GIE_IE6 (0x1u << 6) /**< \brief (XDMAC_GIE) XDMAC Channel 6 Interrupt Enable Bit */ +#define XDMAC_GIE_IE7 (0x1u << 7) /**< \brief (XDMAC_GIE) XDMAC Channel 7 Interrupt Enable Bit */ +#define XDMAC_GIE_IE8 (0x1u << 8) /**< \brief (XDMAC_GIE) XDMAC Channel 8 Interrupt Enable Bit */ +#define XDMAC_GIE_IE9 (0x1u << 9) /**< \brief (XDMAC_GIE) XDMAC Channel 9 Interrupt Enable Bit */ +#define XDMAC_GIE_IE10 (0x1u << 10) /**< \brief (XDMAC_GIE) XDMAC Channel 10 Interrupt Enable Bit */ +#define XDMAC_GIE_IE11 (0x1u << 11) /**< \brief (XDMAC_GIE) XDMAC Channel 11 Interrupt Enable Bit */ +#define XDMAC_GIE_IE12 (0x1u << 12) /**< \brief (XDMAC_GIE) XDMAC Channel 12 Interrupt Enable Bit */ +#define XDMAC_GIE_IE13 (0x1u << 13) /**< \brief (XDMAC_GIE) XDMAC Channel 13 Interrupt Enable Bit */ +#define XDMAC_GIE_IE14 (0x1u << 14) /**< \brief (XDMAC_GIE) XDMAC Channel 14 Interrupt Enable Bit */ +#define XDMAC_GIE_IE15 (0x1u << 15) /**< \brief (XDMAC_GIE) XDMAC Channel 15 Interrupt Enable Bit */ +#define XDMAC_GIE_IE16 (0x1u << 16) /**< \brief (XDMAC_GIE) XDMAC Channel 16 Interrupt Enable Bit */ +#define XDMAC_GIE_IE17 (0x1u << 17) /**< \brief (XDMAC_GIE) XDMAC Channel 17 Interrupt Enable Bit */ +#define XDMAC_GIE_IE18 (0x1u << 18) /**< \brief (XDMAC_GIE) XDMAC Channel 18 Interrupt Enable Bit */ +#define XDMAC_GIE_IE19 (0x1u << 19) /**< \brief (XDMAC_GIE) XDMAC Channel 19 Interrupt Enable Bit */ +#define XDMAC_GIE_IE20 (0x1u << 20) /**< \brief (XDMAC_GIE) XDMAC Channel 20 Interrupt Enable Bit */ +#define XDMAC_GIE_IE21 (0x1u << 21) /**< \brief (XDMAC_GIE) XDMAC Channel 21 Interrupt Enable Bit */ +#define XDMAC_GIE_IE22 (0x1u << 22) /**< \brief (XDMAC_GIE) XDMAC Channel 22 Interrupt Enable Bit */ +#define XDMAC_GIE_IE23 (0x1u << 23) /**< \brief (XDMAC_GIE) XDMAC Channel 23 Interrupt Enable Bit */ +/* -------- XDMAC_GID : (XDMAC Offset: 0x10) Global Interrupt Disable Register -------- */ +#define XDMAC_GID_ID0 (0x1u << 0) /**< \brief (XDMAC_GID) XDMAC Channel 0 Interrupt Disable Bit */ +#define XDMAC_GID_ID1 (0x1u << 1) /**< \brief (XDMAC_GID) XDMAC Channel 1 Interrupt Disable Bit */ +#define XDMAC_GID_ID2 (0x1u << 2) /**< \brief (XDMAC_GID) XDMAC Channel 2 Interrupt Disable Bit */ +#define XDMAC_GID_ID3 (0x1u << 3) /**< \brief (XDMAC_GID) XDMAC Channel 3 Interrupt Disable Bit */ +#define XDMAC_GID_ID4 (0x1u << 4) /**< \brief (XDMAC_GID) XDMAC Channel 4 Interrupt Disable Bit */ +#define XDMAC_GID_ID5 (0x1u << 5) /**< \brief (XDMAC_GID) XDMAC Channel 5 Interrupt Disable Bit */ +#define XDMAC_GID_ID6 (0x1u << 6) /**< \brief (XDMAC_GID) XDMAC Channel 6 Interrupt Disable Bit */ +#define XDMAC_GID_ID7 (0x1u << 7) /**< \brief (XDMAC_GID) XDMAC Channel 7 Interrupt Disable Bit */ +#define XDMAC_GID_ID8 (0x1u << 8) /**< \brief (XDMAC_GID) XDMAC Channel 8 Interrupt Disable Bit */ +#define XDMAC_GID_ID9 (0x1u << 9) /**< \brief (XDMAC_GID) XDMAC Channel 9 Interrupt Disable Bit */ +#define XDMAC_GID_ID10 (0x1u << 10) /**< \brief (XDMAC_GID) XDMAC Channel 10 Interrupt Disable Bit */ +#define XDMAC_GID_ID11 (0x1u << 11) /**< \brief (XDMAC_GID) XDMAC Channel 11 Interrupt Disable Bit */ +#define XDMAC_GID_ID12 (0x1u << 12) /**< \brief (XDMAC_GID) XDMAC Channel 12 Interrupt Disable Bit */ +#define XDMAC_GID_ID13 (0x1u << 13) /**< \brief (XDMAC_GID) XDMAC Channel 13 Interrupt Disable Bit */ +#define XDMAC_GID_ID14 (0x1u << 14) /**< \brief (XDMAC_GID) XDMAC Channel 14 Interrupt Disable Bit */ +#define XDMAC_GID_ID15 (0x1u << 15) /**< \brief (XDMAC_GID) XDMAC Channel 15 Interrupt Disable Bit */ +#define XDMAC_GID_ID16 (0x1u << 16) /**< \brief (XDMAC_GID) XDMAC Channel 16 Interrupt Disable Bit */ +#define XDMAC_GID_ID17 (0x1u << 17) /**< \brief (XDMAC_GID) XDMAC Channel 17 Interrupt Disable Bit */ +#define XDMAC_GID_ID18 (0x1u << 18) /**< \brief (XDMAC_GID) XDMAC Channel 18 Interrupt Disable Bit */ +#define XDMAC_GID_ID19 (0x1u << 19) /**< \brief (XDMAC_GID) XDMAC Channel 19 Interrupt Disable Bit */ +#define XDMAC_GID_ID20 (0x1u << 20) /**< \brief (XDMAC_GID) XDMAC Channel 20 Interrupt Disable Bit */ +#define XDMAC_GID_ID21 (0x1u << 21) /**< \brief (XDMAC_GID) XDMAC Channel 21 Interrupt Disable Bit */ +#define XDMAC_GID_ID22 (0x1u << 22) /**< \brief (XDMAC_GID) XDMAC Channel 22 Interrupt Disable Bit */ +#define XDMAC_GID_ID23 (0x1u << 23) /**< \brief (XDMAC_GID) XDMAC Channel 23 Interrupt Disable Bit */ +/* -------- XDMAC_GIM : (XDMAC Offset: 0x14) Global Interrupt Mask Register -------- */ +#define XDMAC_GIM_IM0 (0x1u << 0) /**< \brief (XDMAC_GIM) XDMAC Channel 0 Interrupt Mask Bit */ +#define XDMAC_GIM_IM1 (0x1u << 1) /**< \brief (XDMAC_GIM) XDMAC Channel 1 Interrupt Mask Bit */ +#define XDMAC_GIM_IM2 (0x1u << 2) /**< \brief (XDMAC_GIM) XDMAC Channel 2 Interrupt Mask Bit */ +#define XDMAC_GIM_IM3 (0x1u << 3) /**< \brief (XDMAC_GIM) XDMAC Channel 3 Interrupt Mask Bit */ +#define XDMAC_GIM_IM4 (0x1u << 4) /**< \brief (XDMAC_GIM) XDMAC Channel 4 Interrupt Mask Bit */ +#define XDMAC_GIM_IM5 (0x1u << 5) /**< \brief (XDMAC_GIM) XDMAC Channel 5 Interrupt Mask Bit */ +#define XDMAC_GIM_IM6 (0x1u << 6) /**< \brief (XDMAC_GIM) XDMAC Channel 6 Interrupt Mask Bit */ +#define XDMAC_GIM_IM7 (0x1u << 7) /**< \brief (XDMAC_GIM) XDMAC Channel 7 Interrupt Mask Bit */ +#define XDMAC_GIM_IM8 (0x1u << 8) /**< \brief (XDMAC_GIM) XDMAC Channel 8 Interrupt Mask Bit */ +#define XDMAC_GIM_IM9 (0x1u << 9) /**< \brief (XDMAC_GIM) XDMAC Channel 9 Interrupt Mask Bit */ +#define XDMAC_GIM_IM10 (0x1u << 10) /**< \brief (XDMAC_GIM) XDMAC Channel 10 Interrupt Mask Bit */ +#define XDMAC_GIM_IM11 (0x1u << 11) /**< \brief (XDMAC_GIM) XDMAC Channel 11 Interrupt Mask Bit */ +#define XDMAC_GIM_IM12 (0x1u << 12) /**< \brief (XDMAC_GIM) XDMAC Channel 12 Interrupt Mask Bit */ +#define XDMAC_GIM_IM13 (0x1u << 13) /**< \brief (XDMAC_GIM) XDMAC Channel 13 Interrupt Mask Bit */ +#define XDMAC_GIM_IM14 (0x1u << 14) /**< \brief (XDMAC_GIM) XDMAC Channel 14 Interrupt Mask Bit */ +#define XDMAC_GIM_IM15 (0x1u << 15) /**< \brief (XDMAC_GIM) XDMAC Channel 15 Interrupt Mask Bit */ +#define XDMAC_GIM_IM16 (0x1u << 16) /**< \brief (XDMAC_GIM) XDMAC Channel 16 Interrupt Mask Bit */ +#define XDMAC_GIM_IM17 (0x1u << 17) /**< \brief (XDMAC_GIM) XDMAC Channel 17 Interrupt Mask Bit */ +#define XDMAC_GIM_IM18 (0x1u << 18) /**< \brief (XDMAC_GIM) XDMAC Channel 18 Interrupt Mask Bit */ +#define XDMAC_GIM_IM19 (0x1u << 19) /**< \brief (XDMAC_GIM) XDMAC Channel 19 Interrupt Mask Bit */ +#define XDMAC_GIM_IM20 (0x1u << 20) /**< \brief (XDMAC_GIM) XDMAC Channel 20 Interrupt Mask Bit */ +#define XDMAC_GIM_IM21 (0x1u << 21) /**< \brief (XDMAC_GIM) XDMAC Channel 21 Interrupt Mask Bit */ +#define XDMAC_GIM_IM22 (0x1u << 22) /**< \brief (XDMAC_GIM) XDMAC Channel 22 Interrupt Mask Bit */ +#define XDMAC_GIM_IM23 (0x1u << 23) /**< \brief (XDMAC_GIM) XDMAC Channel 23 Interrupt Mask Bit */ +/* -------- XDMAC_GIS : (XDMAC Offset: 0x18) Global Interrupt Status Register -------- */ +#define XDMAC_GIS_IS0 (0x1u << 0) /**< \brief (XDMAC_GIS) XDMAC Channel 0 Interrupt Status Bit */ +#define XDMAC_GIS_IS1 (0x1u << 1) /**< \brief (XDMAC_GIS) XDMAC Channel 1 Interrupt Status Bit */ +#define XDMAC_GIS_IS2 (0x1u << 2) /**< \brief (XDMAC_GIS) XDMAC Channel 2 Interrupt Status Bit */ +#define XDMAC_GIS_IS3 (0x1u << 3) /**< \brief (XDMAC_GIS) XDMAC Channel 3 Interrupt Status Bit */ +#define XDMAC_GIS_IS4 (0x1u << 4) /**< \brief (XDMAC_GIS) XDMAC Channel 4 Interrupt Status Bit */ +#define XDMAC_GIS_IS5 (0x1u << 5) /**< \brief (XDMAC_GIS) XDMAC Channel 5 Interrupt Status Bit */ +#define XDMAC_GIS_IS6 (0x1u << 6) /**< \brief (XDMAC_GIS) XDMAC Channel 6 Interrupt Status Bit */ +#define XDMAC_GIS_IS7 (0x1u << 7) /**< \brief (XDMAC_GIS) XDMAC Channel 7 Interrupt Status Bit */ +#define XDMAC_GIS_IS8 (0x1u << 8) /**< \brief (XDMAC_GIS) XDMAC Channel 8 Interrupt Status Bit */ +#define XDMAC_GIS_IS9 (0x1u << 9) /**< \brief (XDMAC_GIS) XDMAC Channel 9 Interrupt Status Bit */ +#define XDMAC_GIS_IS10 (0x1u << 10) /**< \brief (XDMAC_GIS) XDMAC Channel 10 Interrupt Status Bit */ +#define XDMAC_GIS_IS11 (0x1u << 11) /**< \brief (XDMAC_GIS) XDMAC Channel 11 Interrupt Status Bit */ +#define XDMAC_GIS_IS12 (0x1u << 12) /**< \brief (XDMAC_GIS) XDMAC Channel 12 Interrupt Status Bit */ +#define XDMAC_GIS_IS13 (0x1u << 13) /**< \brief (XDMAC_GIS) XDMAC Channel 13 Interrupt Status Bit */ +#define XDMAC_GIS_IS14 (0x1u << 14) /**< \brief (XDMAC_GIS) XDMAC Channel 14 Interrupt Status Bit */ +#define XDMAC_GIS_IS15 (0x1u << 15) /**< \brief (XDMAC_GIS) XDMAC Channel 15 Interrupt Status Bit */ +#define XDMAC_GIS_IS16 (0x1u << 16) /**< \brief (XDMAC_GIS) XDMAC Channel 16 Interrupt Status Bit */ +#define XDMAC_GIS_IS17 (0x1u << 17) /**< \brief (XDMAC_GIS) XDMAC Channel 17 Interrupt Status Bit */ +#define XDMAC_GIS_IS18 (0x1u << 18) /**< \brief (XDMAC_GIS) XDMAC Channel 18 Interrupt Status Bit */ +#define XDMAC_GIS_IS19 (0x1u << 19) /**< \brief (XDMAC_GIS) XDMAC Channel 19 Interrupt Status Bit */ +#define XDMAC_GIS_IS20 (0x1u << 20) /**< \brief (XDMAC_GIS) XDMAC Channel 20 Interrupt Status Bit */ +#define XDMAC_GIS_IS21 (0x1u << 21) /**< \brief (XDMAC_GIS) XDMAC Channel 21 Interrupt Status Bit */ +#define XDMAC_GIS_IS22 (0x1u << 22) /**< \brief (XDMAC_GIS) XDMAC Channel 22 Interrupt Status Bit */ +#define XDMAC_GIS_IS23 (0x1u << 23) /**< \brief (XDMAC_GIS) XDMAC Channel 23 Interrupt Status Bit */ +/* -------- XDMAC_GE : (XDMAC Offset: 0x1C) Global Channel Enable Register -------- */ +#define XDMAC_GE_EN0 (0x1u << 0) /**< \brief (XDMAC_GE) XDMAC Channel 0 Enable Bit */ +#define XDMAC_GE_EN1 (0x1u << 1) /**< \brief (XDMAC_GE) XDMAC Channel 1 Enable Bit */ +#define XDMAC_GE_EN2 (0x1u << 2) /**< \brief (XDMAC_GE) XDMAC Channel 2 Enable Bit */ +#define XDMAC_GE_EN3 (0x1u << 3) /**< \brief (XDMAC_GE) XDMAC Channel 3 Enable Bit */ +#define XDMAC_GE_EN4 (0x1u << 4) /**< \brief (XDMAC_GE) XDMAC Channel 4 Enable Bit */ +#define XDMAC_GE_EN5 (0x1u << 5) /**< \brief (XDMAC_GE) XDMAC Channel 5 Enable Bit */ +#define XDMAC_GE_EN6 (0x1u << 6) /**< \brief (XDMAC_GE) XDMAC Channel 6 Enable Bit */ +#define XDMAC_GE_EN7 (0x1u << 7) /**< \brief (XDMAC_GE) XDMAC Channel 7 Enable Bit */ +#define XDMAC_GE_EN8 (0x1u << 8) /**< \brief (XDMAC_GE) XDMAC Channel 8 Enable Bit */ +#define XDMAC_GE_EN9 (0x1u << 9) /**< \brief (XDMAC_GE) XDMAC Channel 9 Enable Bit */ +#define XDMAC_GE_EN10 (0x1u << 10) /**< \brief (XDMAC_GE) XDMAC Channel 10 Enable Bit */ +#define XDMAC_GE_EN11 (0x1u << 11) /**< \brief (XDMAC_GE) XDMAC Channel 11 Enable Bit */ +#define XDMAC_GE_EN12 (0x1u << 12) /**< \brief (XDMAC_GE) XDMAC Channel 12 Enable Bit */ +#define XDMAC_GE_EN13 (0x1u << 13) /**< \brief (XDMAC_GE) XDMAC Channel 13 Enable Bit */ +#define XDMAC_GE_EN14 (0x1u << 14) /**< \brief (XDMAC_GE) XDMAC Channel 14 Enable Bit */ +#define XDMAC_GE_EN15 (0x1u << 15) /**< \brief (XDMAC_GE) XDMAC Channel 15 Enable Bit */ +#define XDMAC_GE_EN16 (0x1u << 16) /**< \brief (XDMAC_GE) XDMAC Channel 16 Enable Bit */ +#define XDMAC_GE_EN17 (0x1u << 17) /**< \brief (XDMAC_GE) XDMAC Channel 17 Enable Bit */ +#define XDMAC_GE_EN18 (0x1u << 18) /**< \brief (XDMAC_GE) XDMAC Channel 18 Enable Bit */ +#define XDMAC_GE_EN19 (0x1u << 19) /**< \brief (XDMAC_GE) XDMAC Channel 19 Enable Bit */ +#define XDMAC_GE_EN20 (0x1u << 20) /**< \brief (XDMAC_GE) XDMAC Channel 20 Enable Bit */ +#define XDMAC_GE_EN21 (0x1u << 21) /**< \brief (XDMAC_GE) XDMAC Channel 21 Enable Bit */ +#define XDMAC_GE_EN22 (0x1u << 22) /**< \brief (XDMAC_GE) XDMAC Channel 22 Enable Bit */ +#define XDMAC_GE_EN23 (0x1u << 23) /**< \brief (XDMAC_GE) XDMAC Channel 23 Enable Bit */ +/* -------- XDMAC_GD : (XDMAC Offset: 0x20) Global Channel Disable Register -------- */ +#define XDMAC_GD_DI0 (0x1u << 0) /**< \brief (XDMAC_GD) XDMAC Channel 0 Disable Bit */ +#define XDMAC_GD_DI1 (0x1u << 1) /**< \brief (XDMAC_GD) XDMAC Channel 1 Disable Bit */ +#define XDMAC_GD_DI2 (0x1u << 2) /**< \brief (XDMAC_GD) XDMAC Channel 2 Disable Bit */ +#define XDMAC_GD_DI3 (0x1u << 3) /**< \brief (XDMAC_GD) XDMAC Channel 3 Disable Bit */ +#define XDMAC_GD_DI4 (0x1u << 4) /**< \brief (XDMAC_GD) XDMAC Channel 4 Disable Bit */ +#define XDMAC_GD_DI5 (0x1u << 5) /**< \brief (XDMAC_GD) XDMAC Channel 5 Disable Bit */ +#define XDMAC_GD_DI6 (0x1u << 6) /**< \brief (XDMAC_GD) XDMAC Channel 6 Disable Bit */ +#define XDMAC_GD_DI7 (0x1u << 7) /**< \brief (XDMAC_GD) XDMAC Channel 7 Disable Bit */ +#define XDMAC_GD_DI8 (0x1u << 8) /**< \brief (XDMAC_GD) XDMAC Channel 8 Disable Bit */ +#define XDMAC_GD_DI9 (0x1u << 9) /**< \brief (XDMAC_GD) XDMAC Channel 9 Disable Bit */ +#define XDMAC_GD_DI10 (0x1u << 10) /**< \brief (XDMAC_GD) XDMAC Channel 10 Disable Bit */ +#define XDMAC_GD_DI11 (0x1u << 11) /**< \brief (XDMAC_GD) XDMAC Channel 11 Disable Bit */ +#define XDMAC_GD_DI12 (0x1u << 12) /**< \brief (XDMAC_GD) XDMAC Channel 12 Disable Bit */ +#define XDMAC_GD_DI13 (0x1u << 13) /**< \brief (XDMAC_GD) XDMAC Channel 13 Disable Bit */ +#define XDMAC_GD_DI14 (0x1u << 14) /**< \brief (XDMAC_GD) XDMAC Channel 14 Disable Bit */ +#define XDMAC_GD_DI15 (0x1u << 15) /**< \brief (XDMAC_GD) XDMAC Channel 15 Disable Bit */ +#define XDMAC_GD_DI16 (0x1u << 16) /**< \brief (XDMAC_GD) XDMAC Channel 16 Disable Bit */ +#define XDMAC_GD_DI17 (0x1u << 17) /**< \brief (XDMAC_GD) XDMAC Channel 17 Disable Bit */ +#define XDMAC_GD_DI18 (0x1u << 18) /**< \brief (XDMAC_GD) XDMAC Channel 18 Disable Bit */ +#define XDMAC_GD_DI19 (0x1u << 19) /**< \brief (XDMAC_GD) XDMAC Channel 19 Disable Bit */ +#define XDMAC_GD_DI20 (0x1u << 20) /**< \brief (XDMAC_GD) XDMAC Channel 20 Disable Bit */ +#define XDMAC_GD_DI21 (0x1u << 21) /**< \brief (XDMAC_GD) XDMAC Channel 21 Disable Bit */ +#define XDMAC_GD_DI22 (0x1u << 22) /**< \brief (XDMAC_GD) XDMAC Channel 22 Disable Bit */ +#define XDMAC_GD_DI23 (0x1u << 23) /**< \brief (XDMAC_GD) XDMAC Channel 23 Disable Bit */ +/* -------- XDMAC_GS : (XDMAC Offset: 0x24) Global Channel Status Register -------- */ +#define XDMAC_GS_ST0 (0x1u << 0) /**< \brief (XDMAC_GS) XDMAC Channel 0 Status Bit */ +#define XDMAC_GS_ST1 (0x1u << 1) /**< \brief (XDMAC_GS) XDMAC Channel 1 Status Bit */ +#define XDMAC_GS_ST2 (0x1u << 2) /**< \brief (XDMAC_GS) XDMAC Channel 2 Status Bit */ +#define XDMAC_GS_ST3 (0x1u << 3) /**< \brief (XDMAC_GS) XDMAC Channel 3 Status Bit */ +#define XDMAC_GS_ST4 (0x1u << 4) /**< \brief (XDMAC_GS) XDMAC Channel 4 Status Bit */ +#define XDMAC_GS_ST5 (0x1u << 5) /**< \brief (XDMAC_GS) XDMAC Channel 5 Status Bit */ +#define XDMAC_GS_ST6 (0x1u << 6) /**< \brief (XDMAC_GS) XDMAC Channel 6 Status Bit */ +#define XDMAC_GS_ST7 (0x1u << 7) /**< \brief (XDMAC_GS) XDMAC Channel 7 Status Bit */ +#define XDMAC_GS_ST8 (0x1u << 8) /**< \brief (XDMAC_GS) XDMAC Channel 8 Status Bit */ +#define XDMAC_GS_ST9 (0x1u << 9) /**< \brief (XDMAC_GS) XDMAC Channel 9 Status Bit */ +#define XDMAC_GS_ST10 (0x1u << 10) /**< \brief (XDMAC_GS) XDMAC Channel 10 Status Bit */ +#define XDMAC_GS_ST11 (0x1u << 11) /**< \brief (XDMAC_GS) XDMAC Channel 11 Status Bit */ +#define XDMAC_GS_ST12 (0x1u << 12) /**< \brief (XDMAC_GS) XDMAC Channel 12 Status Bit */ +#define XDMAC_GS_ST13 (0x1u << 13) /**< \brief (XDMAC_GS) XDMAC Channel 13 Status Bit */ +#define XDMAC_GS_ST14 (0x1u << 14) /**< \brief (XDMAC_GS) XDMAC Channel 14 Status Bit */ +#define XDMAC_GS_ST15 (0x1u << 15) /**< \brief (XDMAC_GS) XDMAC Channel 15 Status Bit */ +#define XDMAC_GS_ST16 (0x1u << 16) /**< \brief (XDMAC_GS) XDMAC Channel 16 Status Bit */ +#define XDMAC_GS_ST17 (0x1u << 17) /**< \brief (XDMAC_GS) XDMAC Channel 17 Status Bit */ +#define XDMAC_GS_ST18 (0x1u << 18) /**< \brief (XDMAC_GS) XDMAC Channel 18 Status Bit */ +#define XDMAC_GS_ST19 (0x1u << 19) /**< \brief (XDMAC_GS) XDMAC Channel 19 Status Bit */ +#define XDMAC_GS_ST20 (0x1u << 20) /**< \brief (XDMAC_GS) XDMAC Channel 20 Status Bit */ +#define XDMAC_GS_ST21 (0x1u << 21) /**< \brief (XDMAC_GS) XDMAC Channel 21 Status Bit */ +#define XDMAC_GS_ST22 (0x1u << 22) /**< \brief (XDMAC_GS) XDMAC Channel 22 Status Bit */ +#define XDMAC_GS_ST23 (0x1u << 23) /**< \brief (XDMAC_GS) XDMAC Channel 23 Status Bit */ +/* -------- XDMAC_GRS : (XDMAC Offset: 0x28) Global Channel Read Suspend Register -------- */ +#define XDMAC_GRS_RS0 (0x1u << 0) /**< \brief (XDMAC_GRS) XDMAC Channel 0 Read Suspend Bit */ +#define XDMAC_GRS_RS1 (0x1u << 1) /**< \brief (XDMAC_GRS) XDMAC Channel 1 Read Suspend Bit */ +#define XDMAC_GRS_RS2 (0x1u << 2) /**< \brief (XDMAC_GRS) XDMAC Channel 2 Read Suspend Bit */ +#define XDMAC_GRS_RS3 (0x1u << 3) /**< \brief (XDMAC_GRS) XDMAC Channel 3 Read Suspend Bit */ +#define XDMAC_GRS_RS4 (0x1u << 4) /**< \brief (XDMAC_GRS) XDMAC Channel 4 Read Suspend Bit */ +#define XDMAC_GRS_RS5 (0x1u << 5) /**< \brief (XDMAC_GRS) XDMAC Channel 5 Read Suspend Bit */ +#define XDMAC_GRS_RS6 (0x1u << 6) /**< \brief (XDMAC_GRS) XDMAC Channel 6 Read Suspend Bit */ +#define XDMAC_GRS_RS7 (0x1u << 7) /**< \brief (XDMAC_GRS) XDMAC Channel 7 Read Suspend Bit */ +#define XDMAC_GRS_RS8 (0x1u << 8) /**< \brief (XDMAC_GRS) XDMAC Channel 8 Read Suspend Bit */ +#define XDMAC_GRS_RS9 (0x1u << 9) /**< \brief (XDMAC_GRS) XDMAC Channel 9 Read Suspend Bit */ +#define XDMAC_GRS_RS10 (0x1u << 10) /**< \brief (XDMAC_GRS) XDMAC Channel 10 Read Suspend Bit */ +#define XDMAC_GRS_RS11 (0x1u << 11) /**< \brief (XDMAC_GRS) XDMAC Channel 11 Read Suspend Bit */ +#define XDMAC_GRS_RS12 (0x1u << 12) /**< \brief (XDMAC_GRS) XDMAC Channel 12 Read Suspend Bit */ +#define XDMAC_GRS_RS13 (0x1u << 13) /**< \brief (XDMAC_GRS) XDMAC Channel 13 Read Suspend Bit */ +#define XDMAC_GRS_RS14 (0x1u << 14) /**< \brief (XDMAC_GRS) XDMAC Channel 14 Read Suspend Bit */ +#define XDMAC_GRS_RS15 (0x1u << 15) /**< \brief (XDMAC_GRS) XDMAC Channel 15 Read Suspend Bit */ +#define XDMAC_GRS_RS16 (0x1u << 16) /**< \brief (XDMAC_GRS) XDMAC Channel 16 Read Suspend Bit */ +#define XDMAC_GRS_RS17 (0x1u << 17) /**< \brief (XDMAC_GRS) XDMAC Channel 17 Read Suspend Bit */ +#define XDMAC_GRS_RS18 (0x1u << 18) /**< \brief (XDMAC_GRS) XDMAC Channel 18 Read Suspend Bit */ +#define XDMAC_GRS_RS19 (0x1u << 19) /**< \brief (XDMAC_GRS) XDMAC Channel 19 Read Suspend Bit */ +#define XDMAC_GRS_RS20 (0x1u << 20) /**< \brief (XDMAC_GRS) XDMAC Channel 20 Read Suspend Bit */ +#define XDMAC_GRS_RS21 (0x1u << 21) /**< \brief (XDMAC_GRS) XDMAC Channel 21 Read Suspend Bit */ +#define XDMAC_GRS_RS22 (0x1u << 22) /**< \brief (XDMAC_GRS) XDMAC Channel 22 Read Suspend Bit */ +#define XDMAC_GRS_RS23 (0x1u << 23) /**< \brief (XDMAC_GRS) XDMAC Channel 23 Read Suspend Bit */ +/* -------- XDMAC_GWS : (XDMAC Offset: 0x2C) Global Channel Write Suspend Register -------- */ +#define XDMAC_GWS_WS0 (0x1u << 0) /**< \brief (XDMAC_GWS) XDMAC Channel 0 Write Suspend Bit */ +#define XDMAC_GWS_WS1 (0x1u << 1) /**< \brief (XDMAC_GWS) XDMAC Channel 1 Write Suspend Bit */ +#define XDMAC_GWS_WS2 (0x1u << 2) /**< \brief (XDMAC_GWS) XDMAC Channel 2 Write Suspend Bit */ +#define XDMAC_GWS_WS3 (0x1u << 3) /**< \brief (XDMAC_GWS) XDMAC Channel 3 Write Suspend Bit */ +#define XDMAC_GWS_WS4 (0x1u << 4) /**< \brief (XDMAC_GWS) XDMAC Channel 4 Write Suspend Bit */ +#define XDMAC_GWS_WS5 (0x1u << 5) /**< \brief (XDMAC_GWS) XDMAC Channel 5 Write Suspend Bit */ +#define XDMAC_GWS_WS6 (0x1u << 6) /**< \brief (XDMAC_GWS) XDMAC Channel 6 Write Suspend Bit */ +#define XDMAC_GWS_WS7 (0x1u << 7) /**< \brief (XDMAC_GWS) XDMAC Channel 7 Write Suspend Bit */ +#define XDMAC_GWS_WS8 (0x1u << 8) /**< \brief (XDMAC_GWS) XDMAC Channel 8 Write Suspend Bit */ +#define XDMAC_GWS_WS9 (0x1u << 9) /**< \brief (XDMAC_GWS) XDMAC Channel 9 Write Suspend Bit */ +#define XDMAC_GWS_WS10 (0x1u << 10) /**< \brief (XDMAC_GWS) XDMAC Channel 10 Write Suspend Bit */ +#define XDMAC_GWS_WS11 (0x1u << 11) /**< \brief (XDMAC_GWS) XDMAC Channel 11 Write Suspend Bit */ +#define XDMAC_GWS_WS12 (0x1u << 12) /**< \brief (XDMAC_GWS) XDMAC Channel 12 Write Suspend Bit */ +#define XDMAC_GWS_WS13 (0x1u << 13) /**< \brief (XDMAC_GWS) XDMAC Channel 13 Write Suspend Bit */ +#define XDMAC_GWS_WS14 (0x1u << 14) /**< \brief (XDMAC_GWS) XDMAC Channel 14 Write Suspend Bit */ +#define XDMAC_GWS_WS15 (0x1u << 15) /**< \brief (XDMAC_GWS) XDMAC Channel 15 Write Suspend Bit */ +#define XDMAC_GWS_WS16 (0x1u << 16) /**< \brief (XDMAC_GWS) XDMAC Channel 16 Write Suspend Bit */ +#define XDMAC_GWS_WS17 (0x1u << 17) /**< \brief (XDMAC_GWS) XDMAC Channel 17 Write Suspend Bit */ +#define XDMAC_GWS_WS18 (0x1u << 18) /**< \brief (XDMAC_GWS) XDMAC Channel 18 Write Suspend Bit */ +#define XDMAC_GWS_WS19 (0x1u << 19) /**< \brief (XDMAC_GWS) XDMAC Channel 19 Write Suspend Bit */ +#define XDMAC_GWS_WS20 (0x1u << 20) /**< \brief (XDMAC_GWS) XDMAC Channel 20 Write Suspend Bit */ +#define XDMAC_GWS_WS21 (0x1u << 21) /**< \brief (XDMAC_GWS) XDMAC Channel 21 Write Suspend Bit */ +#define XDMAC_GWS_WS22 (0x1u << 22) /**< \brief (XDMAC_GWS) XDMAC Channel 22 Write Suspend Bit */ +#define XDMAC_GWS_WS23 (0x1u << 23) /**< \brief (XDMAC_GWS) XDMAC Channel 23 Write Suspend Bit */ +/* -------- XDMAC_GRWS : (XDMAC Offset: 0x30) Global Channel Read Write Suspend Register -------- */ +#define XDMAC_GRWS_RWS0 (0x1u << 0) /**< \brief (XDMAC_GRWS) XDMAC Channel 0 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS1 (0x1u << 1) /**< \brief (XDMAC_GRWS) XDMAC Channel 1 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS2 (0x1u << 2) /**< \brief (XDMAC_GRWS) XDMAC Channel 2 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS3 (0x1u << 3) /**< \brief (XDMAC_GRWS) XDMAC Channel 3 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS4 (0x1u << 4) /**< \brief (XDMAC_GRWS) XDMAC Channel 4 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS5 (0x1u << 5) /**< \brief (XDMAC_GRWS) XDMAC Channel 5 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS6 (0x1u << 6) /**< \brief (XDMAC_GRWS) XDMAC Channel 6 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS7 (0x1u << 7) /**< \brief (XDMAC_GRWS) XDMAC Channel 7 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS8 (0x1u << 8) /**< \brief (XDMAC_GRWS) XDMAC Channel 8 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS9 (0x1u << 9) /**< \brief (XDMAC_GRWS) XDMAC Channel 9 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS10 (0x1u << 10) /**< \brief (XDMAC_GRWS) XDMAC Channel 10 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS11 (0x1u << 11) /**< \brief (XDMAC_GRWS) XDMAC Channel 11 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS12 (0x1u << 12) /**< \brief (XDMAC_GRWS) XDMAC Channel 12 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS13 (0x1u << 13) /**< \brief (XDMAC_GRWS) XDMAC Channel 13 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS14 (0x1u << 14) /**< \brief (XDMAC_GRWS) XDMAC Channel 14 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS15 (0x1u << 15) /**< \brief (XDMAC_GRWS) XDMAC Channel 15 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS16 (0x1u << 16) /**< \brief (XDMAC_GRWS) XDMAC Channel 16 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS17 (0x1u << 17) /**< \brief (XDMAC_GRWS) XDMAC Channel 17 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS18 (0x1u << 18) /**< \brief (XDMAC_GRWS) XDMAC Channel 18 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS19 (0x1u << 19) /**< \brief (XDMAC_GRWS) XDMAC Channel 19 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS20 (0x1u << 20) /**< \brief (XDMAC_GRWS) XDMAC Channel 20 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS21 (0x1u << 21) /**< \brief (XDMAC_GRWS) XDMAC Channel 21 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS22 (0x1u << 22) /**< \brief (XDMAC_GRWS) XDMAC Channel 22 Read Write Suspend Bit */ +#define XDMAC_GRWS_RWS23 (0x1u << 23) /**< \brief (XDMAC_GRWS) XDMAC Channel 23 Read Write Suspend Bit */ +/* -------- XDMAC_GRWR : (XDMAC Offset: 0x34) Global Channel Read Write Resume Register -------- */ +#define XDMAC_GRWR_RWR0 (0x1u << 0) /**< \brief (XDMAC_GRWR) XDMAC Channel 0 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR1 (0x1u << 1) /**< \brief (XDMAC_GRWR) XDMAC Channel 1 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR2 (0x1u << 2) /**< \brief (XDMAC_GRWR) XDMAC Channel 2 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR3 (0x1u << 3) /**< \brief (XDMAC_GRWR) XDMAC Channel 3 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR4 (0x1u << 4) /**< \brief (XDMAC_GRWR) XDMAC Channel 4 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR5 (0x1u << 5) /**< \brief (XDMAC_GRWR) XDMAC Channel 5 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR6 (0x1u << 6) /**< \brief (XDMAC_GRWR) XDMAC Channel 6 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR7 (0x1u << 7) /**< \brief (XDMAC_GRWR) XDMAC Channel 7 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR8 (0x1u << 8) /**< \brief (XDMAC_GRWR) XDMAC Channel 8 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR9 (0x1u << 9) /**< \brief (XDMAC_GRWR) XDMAC Channel 9 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR10 (0x1u << 10) /**< \brief (XDMAC_GRWR) XDMAC Channel 10 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR11 (0x1u << 11) /**< \brief (XDMAC_GRWR) XDMAC Channel 11 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR12 (0x1u << 12) /**< \brief (XDMAC_GRWR) XDMAC Channel 12 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR13 (0x1u << 13) /**< \brief (XDMAC_GRWR) XDMAC Channel 13 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR14 (0x1u << 14) /**< \brief (XDMAC_GRWR) XDMAC Channel 14 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR15 (0x1u << 15) /**< \brief (XDMAC_GRWR) XDMAC Channel 15 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR16 (0x1u << 16) /**< \brief (XDMAC_GRWR) XDMAC Channel 16 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR17 (0x1u << 17) /**< \brief (XDMAC_GRWR) XDMAC Channel 17 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR18 (0x1u << 18) /**< \brief (XDMAC_GRWR) XDMAC Channel 18 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR19 (0x1u << 19) /**< \brief (XDMAC_GRWR) XDMAC Channel 19 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR20 (0x1u << 20) /**< \brief (XDMAC_GRWR) XDMAC Channel 20 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR21 (0x1u << 21) /**< \brief (XDMAC_GRWR) XDMAC Channel 21 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR22 (0x1u << 22) /**< \brief (XDMAC_GRWR) XDMAC Channel 22 Read Write Resume Bit */ +#define XDMAC_GRWR_RWR23 (0x1u << 23) /**< \brief (XDMAC_GRWR) XDMAC Channel 23 Read Write Resume Bit */ +/* -------- XDMAC_GSWR : (XDMAC Offset: 0x38) Global Channel Software Request Register -------- */ +#define XDMAC_GSWR_SWREQ0 (0x1u << 0) /**< \brief (XDMAC_GSWR) XDMAC Channel 0 Software Request Bit */ +#define XDMAC_GSWR_SWREQ1 (0x1u << 1) /**< \brief (XDMAC_GSWR) XDMAC Channel 1 Software Request Bit */ +#define XDMAC_GSWR_SWREQ2 (0x1u << 2) /**< \brief (XDMAC_GSWR) XDMAC Channel 2 Software Request Bit */ +#define XDMAC_GSWR_SWREQ3 (0x1u << 3) /**< \brief (XDMAC_GSWR) XDMAC Channel 3 Software Request Bit */ +#define XDMAC_GSWR_SWREQ4 (0x1u << 4) /**< \brief (XDMAC_GSWR) XDMAC Channel 4 Software Request Bit */ +#define XDMAC_GSWR_SWREQ5 (0x1u << 5) /**< \brief (XDMAC_GSWR) XDMAC Channel 5 Software Request Bit */ +#define XDMAC_GSWR_SWREQ6 (0x1u << 6) /**< \brief (XDMAC_GSWR) XDMAC Channel 6 Software Request Bit */ +#define XDMAC_GSWR_SWREQ7 (0x1u << 7) /**< \brief (XDMAC_GSWR) XDMAC Channel 7 Software Request Bit */ +#define XDMAC_GSWR_SWREQ8 (0x1u << 8) /**< \brief (XDMAC_GSWR) XDMAC Channel 8 Software Request Bit */ +#define XDMAC_GSWR_SWREQ9 (0x1u << 9) /**< \brief (XDMAC_GSWR) XDMAC Channel 9 Software Request Bit */ +#define XDMAC_GSWR_SWREQ10 (0x1u << 10) /**< \brief (XDMAC_GSWR) XDMAC Channel 10 Software Request Bit */ +#define XDMAC_GSWR_SWREQ11 (0x1u << 11) /**< \brief (XDMAC_GSWR) XDMAC Channel 11 Software Request Bit */ +#define XDMAC_GSWR_SWREQ12 (0x1u << 12) /**< \brief (XDMAC_GSWR) XDMAC Channel 12 Software Request Bit */ +#define XDMAC_GSWR_SWREQ13 (0x1u << 13) /**< \brief (XDMAC_GSWR) XDMAC Channel 13 Software Request Bit */ +#define XDMAC_GSWR_SWREQ14 (0x1u << 14) /**< \brief (XDMAC_GSWR) XDMAC Channel 14 Software Request Bit */ +#define XDMAC_GSWR_SWREQ15 (0x1u << 15) /**< \brief (XDMAC_GSWR) XDMAC Channel 15 Software Request Bit */ +#define XDMAC_GSWR_SWREQ16 (0x1u << 16) /**< \brief (XDMAC_GSWR) XDMAC Channel 16 Software Request Bit */ +#define XDMAC_GSWR_SWREQ17 (0x1u << 17) /**< \brief (XDMAC_GSWR) XDMAC Channel 17 Software Request Bit */ +#define XDMAC_GSWR_SWREQ18 (0x1u << 18) /**< \brief (XDMAC_GSWR) XDMAC Channel 18 Software Request Bit */ +#define XDMAC_GSWR_SWREQ19 (0x1u << 19) /**< \brief (XDMAC_GSWR) XDMAC Channel 19 Software Request Bit */ +#define XDMAC_GSWR_SWREQ20 (0x1u << 20) /**< \brief (XDMAC_GSWR) XDMAC Channel 20 Software Request Bit */ +#define XDMAC_GSWR_SWREQ21 (0x1u << 21) /**< \brief (XDMAC_GSWR) XDMAC Channel 21 Software Request Bit */ +#define XDMAC_GSWR_SWREQ22 (0x1u << 22) /**< \brief (XDMAC_GSWR) XDMAC Channel 22 Software Request Bit */ +#define XDMAC_GSWR_SWREQ23 (0x1u << 23) /**< \brief (XDMAC_GSWR) XDMAC Channel 23 Software Request Bit */ +/* -------- XDMAC_GSWS : (XDMAC Offset: 0x3C) Global Channel Software Request Status Register -------- */ +#define XDMAC_GSWS_SWRS0 (0x1u << 0) /**< \brief (XDMAC_GSWS) XDMAC Channel 0 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS1 (0x1u << 1) /**< \brief (XDMAC_GSWS) XDMAC Channel 1 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS2 (0x1u << 2) /**< \brief (XDMAC_GSWS) XDMAC Channel 2 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS3 (0x1u << 3) /**< \brief (XDMAC_GSWS) XDMAC Channel 3 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS4 (0x1u << 4) /**< \brief (XDMAC_GSWS) XDMAC Channel 4 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS5 (0x1u << 5) /**< \brief (XDMAC_GSWS) XDMAC Channel 5 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS6 (0x1u << 6) /**< \brief (XDMAC_GSWS) XDMAC Channel 6 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS7 (0x1u << 7) /**< \brief (XDMAC_GSWS) XDMAC Channel 7 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS8 (0x1u << 8) /**< \brief (XDMAC_GSWS) XDMAC Channel 8 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS9 (0x1u << 9) /**< \brief (XDMAC_GSWS) XDMAC Channel 9 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS10 (0x1u << 10) /**< \brief (XDMAC_GSWS) XDMAC Channel 10 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS11 (0x1u << 11) /**< \brief (XDMAC_GSWS) XDMAC Channel 11 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS12 (0x1u << 12) /**< \brief (XDMAC_GSWS) XDMAC Channel 12 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS13 (0x1u << 13) /**< \brief (XDMAC_GSWS) XDMAC Channel 13 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS14 (0x1u << 14) /**< \brief (XDMAC_GSWS) XDMAC Channel 14 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS15 (0x1u << 15) /**< \brief (XDMAC_GSWS) XDMAC Channel 15 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS16 (0x1u << 16) /**< \brief (XDMAC_GSWS) XDMAC Channel 16 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS17 (0x1u << 17) /**< \brief (XDMAC_GSWS) XDMAC Channel 17 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS18 (0x1u << 18) /**< \brief (XDMAC_GSWS) XDMAC Channel 18 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS19 (0x1u << 19) /**< \brief (XDMAC_GSWS) XDMAC Channel 19 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS20 (0x1u << 20) /**< \brief (XDMAC_GSWS) XDMAC Channel 20 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS21 (0x1u << 21) /**< \brief (XDMAC_GSWS) XDMAC Channel 21 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS22 (0x1u << 22) /**< \brief (XDMAC_GSWS) XDMAC Channel 22 Software Request Status Bit */ +#define XDMAC_GSWS_SWRS23 (0x1u << 23) /**< \brief (XDMAC_GSWS) XDMAC Channel 23 Software Request Status Bit */ +/* -------- XDMAC_GSWF : (XDMAC Offset: 0x40) Global Channel Software Flush Request Register -------- */ +#define XDMAC_GSWF_SWF0 (0x1u << 0) /**< \brief (XDMAC_GSWF) XDMAC Channel 0 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF1 (0x1u << 1) /**< \brief (XDMAC_GSWF) XDMAC Channel 1 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF2 (0x1u << 2) /**< \brief (XDMAC_GSWF) XDMAC Channel 2 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF3 (0x1u << 3) /**< \brief (XDMAC_GSWF) XDMAC Channel 3 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF4 (0x1u << 4) /**< \brief (XDMAC_GSWF) XDMAC Channel 4 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF5 (0x1u << 5) /**< \brief (XDMAC_GSWF) XDMAC Channel 5 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF6 (0x1u << 6) /**< \brief (XDMAC_GSWF) XDMAC Channel 6 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF7 (0x1u << 7) /**< \brief (XDMAC_GSWF) XDMAC Channel 7 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF8 (0x1u << 8) /**< \brief (XDMAC_GSWF) XDMAC Channel 8 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF9 (0x1u << 9) /**< \brief (XDMAC_GSWF) XDMAC Channel 9 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF10 (0x1u << 10) /**< \brief (XDMAC_GSWF) XDMAC Channel 10 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF11 (0x1u << 11) /**< \brief (XDMAC_GSWF) XDMAC Channel 11 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF12 (0x1u << 12) /**< \brief (XDMAC_GSWF) XDMAC Channel 12 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF13 (0x1u << 13) /**< \brief (XDMAC_GSWF) XDMAC Channel 13 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF14 (0x1u << 14) /**< \brief (XDMAC_GSWF) XDMAC Channel 14 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF15 (0x1u << 15) /**< \brief (XDMAC_GSWF) XDMAC Channel 15 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF16 (0x1u << 16) /**< \brief (XDMAC_GSWF) XDMAC Channel 16 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF17 (0x1u << 17) /**< \brief (XDMAC_GSWF) XDMAC Channel 17 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF18 (0x1u << 18) /**< \brief (XDMAC_GSWF) XDMAC Channel 18 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF19 (0x1u << 19) /**< \brief (XDMAC_GSWF) XDMAC Channel 19 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF20 (0x1u << 20) /**< \brief (XDMAC_GSWF) XDMAC Channel 20 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF21 (0x1u << 21) /**< \brief (XDMAC_GSWF) XDMAC Channel 21 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF22 (0x1u << 22) /**< \brief (XDMAC_GSWF) XDMAC Channel 22 Software Flush Request Bit */ +#define XDMAC_GSWF_SWF23 (0x1u << 23) /**< \brief (XDMAC_GSWF) XDMAC Channel 23 Software Flush Request Bit */ +/* -------- XDMAC_CIE : (XDMAC Offset: N/A) Channel Interrupt Enable Register -------- */ +#define XDMAC_CIE_BIE (0x1u << 0) /**< \brief (XDMAC_CIE) End of Block Interrupt Enable Bit */ +#define XDMAC_CIE_LIE (0x1u << 1) /**< \brief (XDMAC_CIE) End of Linked List Interrupt Enable Bit */ +#define XDMAC_CIE_DIE (0x1u << 2) /**< \brief (XDMAC_CIE) End of Disable Interrupt Enable Bit */ +#define XDMAC_CIE_FIE (0x1u << 3) /**< \brief (XDMAC_CIE) End of Flush Interrupt Enable Bit */ +#define XDMAC_CIE_RBIE (0x1u << 4) /**< \brief (XDMAC_CIE) Read Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_WBIE (0x1u << 5) /**< \brief (XDMAC_CIE) Write Bus Error Interrupt Enable Bit */ +#define XDMAC_CIE_ROIE (0x1u << 6) /**< \brief (XDMAC_CIE) Request Overflow Error Interrupt Enable Bit */ +/* -------- XDMAC_CID : (XDMAC Offset: N/A) Channel Interrupt Disable Register -------- */ +#define XDMAC_CID_BID (0x1u << 0) /**< \brief (XDMAC_CID) End of Block Interrupt Disable Bit */ +#define XDMAC_CID_LID (0x1u << 1) /**< \brief (XDMAC_CID) End of Linked List Interrupt Disable Bit */ +#define XDMAC_CID_DID (0x1u << 2) /**< \brief (XDMAC_CID) End of Disable Interrupt Disable Bit */ +#define XDMAC_CID_FID (0x1u << 3) /**< \brief (XDMAC_CID) End of Flush Interrupt Disable Bit */ +#define XDMAC_CID_RBEID (0x1u << 4) /**< \brief (XDMAC_CID) Read Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_WBEID (0x1u << 5) /**< \brief (XDMAC_CID) Write Bus Error Interrupt Disable Bit */ +#define XDMAC_CID_ROID (0x1u << 6) /**< \brief (XDMAC_CID) Request Overflow Error Interrupt Disable Bit */ +/* -------- XDMAC_CIM : (XDMAC Offset: N/A) Channel Interrupt Mask Register -------- */ +#define XDMAC_CIM_BIM (0x1u << 0) /**< \brief (XDMAC_CIM) End of Block Interrupt Mask Bit */ +#define XDMAC_CIM_LIM (0x1u << 1) /**< \brief (XDMAC_CIM) End of Linked List Interrupt Mask Bit */ +#define XDMAC_CIM_DIM (0x1u << 2) /**< \brief (XDMAC_CIM) End of Disable Interrupt Mask Bit */ +#define XDMAC_CIM_FIM (0x1u << 3) /**< \brief (XDMAC_CIM) End of Flush Interrupt Mask Bit */ +#define XDMAC_CIM_RBEIM (0x1u << 4) /**< \brief (XDMAC_CIM) Read Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_WBEIM (0x1u << 5) /**< \brief (XDMAC_CIM) Write Bus Error Interrupt Mask Bit */ +#define XDMAC_CIM_ROIM (0x1u << 6) /**< \brief (XDMAC_CIM) Request Overflow Error Interrupt Mask Bit */ +/* -------- XDMAC_CIS : (XDMAC Offset: N/A) Channel Interrupt Status Register -------- */ +#define XDMAC_CIS_BIS (0x1u << 0) /**< \brief (XDMAC_CIS) End of Block Interrupt Status Bit */ +#define XDMAC_CIS_LIS (0x1u << 1) /**< \brief (XDMAC_CIS) End of Linked List Interrupt Status Bit */ +#define XDMAC_CIS_DIS (0x1u << 2) /**< \brief (XDMAC_CIS) End of Disable Interrupt Status Bit */ +#define XDMAC_CIS_FIS (0x1u << 3) /**< \brief (XDMAC_CIS) End of Flush Interrupt Status Bit */ +#define XDMAC_CIS_RBEIS (0x1u << 4) /**< \brief (XDMAC_CIS) Read Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_WBEIS (0x1u << 5) /**< \brief (XDMAC_CIS) Write Bus Error Interrupt Status Bit */ +#define XDMAC_CIS_ROIS (0x1u << 6) /**< \brief (XDMAC_CIS) Request Overflow Error Interrupt Status Bit */ +/* -------- XDMAC_CSA : (XDMAC Offset: N/A) Channel Source Address Register -------- */ +#define XDMAC_CSA_SA_Pos 0 +#define XDMAC_CSA_SA_Msk (0xffffffffu << XDMAC_CSA_SA_Pos) /**< \brief (XDMAC_CSA) Channel x Source Address */ +#define XDMAC_CSA_SA(value) ((XDMAC_CSA_SA_Msk & ((value) << XDMAC_CSA_SA_Pos))) +/* -------- XDMAC_CDA : (XDMAC Offset: N/A) Channel Destination Address Register -------- */ +#define XDMAC_CDA_DA_Pos 0 +#define XDMAC_CDA_DA_Msk (0xffffffffu << XDMAC_CDA_DA_Pos) /**< \brief (XDMAC_CDA) Channel x Destination Address */ +#define XDMAC_CDA_DA(value) ((XDMAC_CDA_DA_Msk & ((value) << XDMAC_CDA_DA_Pos))) +/* -------- XDMAC_CNDA : (XDMAC Offset: N/A) Channel Next Descriptor Address Register -------- */ +#define XDMAC_CNDA_NDAIF (0x1u << 0) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Interface */ +#define XDMAC_CNDA_NDA_Pos 2 +#define XDMAC_CNDA_NDA_Msk (0x3fffffffu << XDMAC_CNDA_NDA_Pos) /**< \brief (XDMAC_CNDA) Channel x Next Descriptor Address */ +#define XDMAC_CNDA_NDA(value) ((XDMAC_CNDA_NDA_Msk & ((value) << XDMAC_CNDA_NDA_Pos))) +/* -------- XDMAC_CNDC : (XDMAC Offset: N/A) Channel Next Descriptor Control Register -------- */ +#define XDMAC_CNDC_NDE (0x1u << 0) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Enable */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_DIS (0x0u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is disabled */ +#define XDMAC_CNDC_NDE_DSCR_FETCH_EN (0x1u << 0) /**< \brief (XDMAC_CNDC) Descriptor fetch is enabled */ +#define XDMAC_CNDC_NDSUP (0x1u << 1) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Source Update */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UNCHANGED (0x0u << 1) /**< \brief (XDMAC_CNDC) Source parameters remain unchanged. */ +#define XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED (0x1u << 1) /**< \brief (XDMAC_CNDC) Source parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDDUP (0x1u << 2) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor Destination Update */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UNCHANGED (0x0u << 2) /**< \brief (XDMAC_CNDC) Destination parameters remain unchanged. */ +#define XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED (0x1u << 2) /**< \brief (XDMAC_CNDC) Destination parameters are updated when the descriptor is retrieved. */ +#define XDMAC_CNDC_NDVIEW_Pos 3 +#define XDMAC_CNDC_NDVIEW_Msk (0x3u << XDMAC_CNDC_NDVIEW_Pos) /**< \brief (XDMAC_CNDC) Channel x Next Descriptor View */ +#define XDMAC_CNDC_NDVIEW(value) ((XDMAC_CNDC_NDVIEW_Msk & ((value) << XDMAC_CNDC_NDVIEW_Pos))) +#define XDMAC_CNDC_NDVIEW_NDV0 (0x0u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 0 */ +#define XDMAC_CNDC_NDVIEW_NDV1 (0x1u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 1 */ +#define XDMAC_CNDC_NDVIEW_NDV2 (0x2u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 2 */ +#define XDMAC_CNDC_NDVIEW_NDV3 (0x3u << 3) /**< \brief (XDMAC_CNDC) Next Descriptor View 3 */ +/* -------- XDMAC_CUBC : (XDMAC Offset: N/A) Channel Microblock Control Register -------- */ +#define XDMAC_CUBC_UBLEN_Pos 0 +#define XDMAC_CUBC_UBLEN_Msk (0xffffffu << XDMAC_CUBC_UBLEN_Pos) /**< \brief (XDMAC_CUBC) Channel x Microblock Length */ +#define XDMAC_CUBC_UBLEN(value) ((XDMAC_CUBC_UBLEN_Msk & ((value) << XDMAC_CUBC_UBLEN_Pos))) +/* -------- XDMAC_CBC : (XDMAC Offset: N/A) Channel Block Control Register -------- */ +#define XDMAC_CBC_BLEN_Pos 0 +#define XDMAC_CBC_BLEN_Msk (0xfffu << XDMAC_CBC_BLEN_Pos) /**< \brief (XDMAC_CBC) Channel x Block Length */ +#define XDMAC_CBC_BLEN(value) ((XDMAC_CBC_BLEN_Msk & ((value) << XDMAC_CBC_BLEN_Pos))) +/* -------- XDMAC_CC : (XDMAC Offset: N/A) Channel Configuration Register -------- */ +#define XDMAC_CC_TYPE (0x1u << 0) /**< \brief (XDMAC_CC) Channel x Transfer Type */ +#define XDMAC_CC_TYPE_MEM_TRAN (0x0u << 0) /**< \brief (XDMAC_CC) Self triggered mode (Memory to Memory Transfer). */ +#define XDMAC_CC_TYPE_PER_TRAN (0x1u << 0) /**< \brief (XDMAC_CC) Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). */ +#define XDMAC_CC_MBSIZE_Pos 1 +#define XDMAC_CC_MBSIZE_Msk (0x3u << XDMAC_CC_MBSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Memory Burst Size */ +#define XDMAC_CC_MBSIZE(value) ((XDMAC_CC_MBSIZE_Msk & ((value) << XDMAC_CC_MBSIZE_Pos))) +#define XDMAC_CC_MBSIZE_SINGLE (0x0u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to one. */ +#define XDMAC_CC_MBSIZE_FOUR (0x1u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to four. */ +#define XDMAC_CC_MBSIZE_EIGHT (0x2u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to eight. */ +#define XDMAC_CC_MBSIZE_SIXTEEN (0x3u << 1) /**< \brief (XDMAC_CC) The memory burst size is set to sixteen. */ +#define XDMAC_CC_DSYNC (0x1u << 4) /**< \brief (XDMAC_CC) Channel x Synchronization */ +#define XDMAC_CC_DSYNC_PER2MEM (0x0u << 4) /**< \brief (XDMAC_CC) Peripheral to Memory transfer */ +#define XDMAC_CC_DSYNC_MEM2PER (0x1u << 4) /**< \brief (XDMAC_CC) Memory to Peripheral transfer */ +#define XDMAC_CC_PROT (0x1u << 5) /**< \brief (XDMAC_CC) Channel x Protection */ +#define XDMAC_CC_PROT_SEC (0x0u << 5) /**< \brief (XDMAC_CC) Channel is secured */ +#define XDMAC_CC_PROT_UNSEC (0x1u << 5) /**< \brief (XDMAC_CC) Channel is unsecured */ +#define XDMAC_CC_SWREQ (0x1u << 6) /**< \brief (XDMAC_CC) Channel x Software Request Trigger */ +#define XDMAC_CC_SWREQ_HWR_CONNECTED (0x0u << 6) /**< \brief (XDMAC_CC) Hardware request line is connected to the peripheral request line. */ +#define XDMAC_CC_SWREQ_SWR_CONNECTED (0x1u << 6) /**< \brief (XDMAC_CC) Software request is connected to the peripheral request line. */ +#define XDMAC_CC_MEMSET (0x1u << 7) /**< \brief (XDMAC_CC) Channel x Fill Block of memory */ +#define XDMAC_CC_MEMSET_NORMAL_MODE (0x0u << 7) /**< \brief (XDMAC_CC) Memset is not activated */ +#define XDMAC_CC_MEMSET_HW_MODE (0x1u << 7) /**< \brief (XDMAC_CC) Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. */ +#define XDMAC_CC_CSIZE_Pos 8 +#define XDMAC_CC_CSIZE_Msk (0x7u << XDMAC_CC_CSIZE_Pos) /**< \brief (XDMAC_CC) Channel x Chunk Size */ +#define XDMAC_CC_CSIZE(value) ((XDMAC_CC_CSIZE_Msk & ((value) << XDMAC_CC_CSIZE_Pos))) +#define XDMAC_CC_CSIZE_CHK_1 (0x0u << 8) /**< \brief (XDMAC_CC) 1 data transferred */ +#define XDMAC_CC_CSIZE_CHK_2 (0x1u << 8) /**< \brief (XDMAC_CC) 2 data transferred */ +#define XDMAC_CC_CSIZE_CHK_4 (0x2u << 8) /**< \brief (XDMAC_CC) 4 data transferred */ +#define XDMAC_CC_CSIZE_CHK_8 (0x3u << 8) /**< \brief (XDMAC_CC) 8 data transferred */ +#define XDMAC_CC_CSIZE_CHK_16 (0x4u << 8) /**< \brief (XDMAC_CC) 16 data transferred */ +#define XDMAC_CC_DWIDTH_Pos 11 +#define XDMAC_CC_DWIDTH_Msk (0x3u << XDMAC_CC_DWIDTH_Pos) /**< \brief (XDMAC_CC) Channel x Data Width */ +#define XDMAC_CC_DWIDTH(value) ((XDMAC_CC_DWIDTH_Msk & ((value) << XDMAC_CC_DWIDTH_Pos))) +#define XDMAC_CC_DWIDTH_BYTE (0x0u << 11) /**< \brief (XDMAC_CC) The data size is set to 8 bits */ +#define XDMAC_CC_DWIDTH_HALFWORD (0x1u << 11) /**< \brief (XDMAC_CC) The data size is set to 16 bits */ +#define XDMAC_CC_DWIDTH_WORD (0x2u << 11) /**< \brief (XDMAC_CC) The data size is set to 32 bits */ +#define XDMAC_CC_SIF (0x1u << 13) /**< \brief (XDMAC_CC) Channel x Source Interface Identifier */ +#define XDMAC_CC_SIF_AHB_IF0 (0x0u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 0 */ +#define XDMAC_CC_SIF_AHB_IF1 (0x1u << 13) /**< \brief (XDMAC_CC) The data is read through the system bus interface 1 */ +#define XDMAC_CC_DIF (0x1u << 14) /**< \brief (XDMAC_CC) Channel x Destination Interface Identifier */ +#define XDMAC_CC_DIF_AHB_IF0 (0x0u << 14) /**< \brief (XDMAC_CC) The data is written through the system bus interface 0 */ +#define XDMAC_CC_DIF_AHB_IF1 (0x1u << 14) /**< \brief (XDMAC_CC) The data is written though the system bus interface 1 */ +#define XDMAC_CC_SAM_Pos 16 +#define XDMAC_CC_SAM_Msk (0x3u << XDMAC_CC_SAM_Pos) /**< \brief (XDMAC_CC) Channel x Source Addressing Mode */ +#define XDMAC_CC_SAM(value) ((XDMAC_CC_SAM_Msk & ((value) << XDMAC_CC_SAM_Pos))) +#define XDMAC_CC_SAM_FIXED_AM (0x0u << 16) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_SAM_INCREMENTED_AM (0x1u << 16) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_SAM_UBS_AM (0x2u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_SAM_UBS_DS_AM (0x3u << 16) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_DAM_Pos 18 +#define XDMAC_CC_DAM_Msk (0x3u << XDMAC_CC_DAM_Pos) /**< \brief (XDMAC_CC) Channel x Destination Addressing Mode */ +#define XDMAC_CC_DAM(value) ((XDMAC_CC_DAM_Msk & ((value) << XDMAC_CC_DAM_Pos))) +#define XDMAC_CC_DAM_FIXED_AM (0x0u << 18) /**< \brief (XDMAC_CC) The address remains unchanged. */ +#define XDMAC_CC_DAM_INCREMENTED_AM (0x1u << 18) /**< \brief (XDMAC_CC) The addressing mode is incremented (the increment size is set to the data size). */ +#define XDMAC_CC_DAM_UBS_AM (0x2u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary. */ +#define XDMAC_CC_DAM_UBS_DS_AM (0x3u << 18) /**< \brief (XDMAC_CC) The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. */ +#define XDMAC_CC_INITD (0x1u << 21) /**< \brief (XDMAC_CC) Channel Initialization Terminated (this bit is read-only) */ +#define XDMAC_CC_INITD_TERMINATED (0x0u << 21) /**< \brief (XDMAC_CC) Channel initialization is in progress. */ +#define XDMAC_CC_INITD_IN_PROGRESS (0x1u << 21) /**< \brief (XDMAC_CC) Channel initialization is completed. */ +#define XDMAC_CC_RDIP (0x1u << 22) /**< \brief (XDMAC_CC) Read in Progress (this bit is read-only) */ +#define XDMAC_CC_RDIP_DONE (0x0u << 22) /**< \brief (XDMAC_CC) No Active read transaction on the bus. */ +#define XDMAC_CC_RDIP_IN_PROGRESS (0x1u << 22) /**< \brief (XDMAC_CC) A read transaction is in progress. */ +#define XDMAC_CC_WRIP (0x1u << 23) /**< \brief (XDMAC_CC) Write in Progress (this bit is read-only) */ +#define XDMAC_CC_WRIP_DONE (0x0u << 23) /**< \brief (XDMAC_CC) No Active write transaction on the bus. */ +#define XDMAC_CC_WRIP_IN_PROGRESS (0x1u << 23) /**< \brief (XDMAC_CC) A Write transaction is in progress. */ +#define XDMAC_CC_PERID_Pos 24 +#define XDMAC_CC_PERID_Msk (0x7fu << XDMAC_CC_PERID_Pos) /**< \brief (XDMAC_CC) Channel x Peripheral Identifier */ +#define XDMAC_CC_PERID(value) ((XDMAC_CC_PERID_Msk & ((value) << XDMAC_CC_PERID_Pos))) +/* -------- XDMAC_CDS_MSP : (XDMAC Offset: N/A) Channel Data Stride Memory Set Pattern -------- */ +#define XDMAC_CDS_MSP_SDS_MSP_Pos 0 +#define XDMAC_CDS_MSP_SDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_SDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Source Data stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_SDS_MSP(value) ((XDMAC_CDS_MSP_SDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_SDS_MSP_Pos))) +#define XDMAC_CDS_MSP_DDS_MSP_Pos 16 +#define XDMAC_CDS_MSP_DDS_MSP_Msk (0xffffu << XDMAC_CDS_MSP_DDS_MSP_Pos) /**< \brief (XDMAC_CDS_MSP) Channel x Destination Data Stride or Memory Set Pattern */ +#define XDMAC_CDS_MSP_DDS_MSP(value) ((XDMAC_CDS_MSP_DDS_MSP_Msk & ((value) << XDMAC_CDS_MSP_DDS_MSP_Pos))) +/* -------- XDMAC_CSUS : (XDMAC Offset: N/A) Channel Source Microblock Stride -------- */ +#define XDMAC_CSUS_SUBS_Pos 0 +#define XDMAC_CSUS_SUBS_Msk (0xffffffu << XDMAC_CSUS_SUBS_Pos) /**< \brief (XDMAC_CSUS) Channel x Source Microblock Stride */ +#define XDMAC_CSUS_SUBS(value) ((XDMAC_CSUS_SUBS_Msk & ((value) << XDMAC_CSUS_SUBS_Pos))) +/* -------- XDMAC_CDUS : (XDMAC Offset: N/A) Channel Destination Microblock Stride -------- */ +#define XDMAC_CDUS_DUBS_Pos 0 +#define XDMAC_CDUS_DUBS_Msk (0xffffffu << XDMAC_CDUS_DUBS_Pos) /**< \brief (XDMAC_CDUS) Channel x Destination Microblock Stride */ +#define XDMAC_CDUS_DUBS(value) ((XDMAC_CDUS_DUBS_Msk & ((value) << XDMAC_CDUS_DUBS_Pos))) + +/*@}*/ + + +#endif /* _SAMV71_XDMAC_COMPONENT_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_acc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_acc.h new file mode 100644 index 000000000..5409699b5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_acc.h @@ -0,0 +1,56 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ACC_INSTANCE_ +#define _SAMV71_ACC_INSTANCE_ + +/* ========== Register definition for ACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ACC_CR (0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ +#else + #define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< \brief (ACC) Control Register */ + #define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< \brief (ACC) Mode Register */ + #define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< \brief (ACC) Interrupt Enable Register */ + #define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< \brief (ACC) Interrupt Disable Register */ + #define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< \brief (ACC) Interrupt Mask Register */ + #define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< \brief (ACC) Interrupt Status Register */ + #define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< \brief (ACC) Analog Control Register */ + #define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< \brief (ACC) Write Protection Mode Register */ + #define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< \brief (ACC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_ACC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_aes.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_aes.h new file mode 100644 index 000000000..b5f4c34fd --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_aes.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AES_INSTANCE_ +#define _SAMV71_AES_INSTANCE_ + +/* ========== Register definition for AES peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AES_CR (0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (0x4006C09CU) /**< \brief (AES) GCM H Word Register */ +#else + #define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< \brief (AES) Control Register */ + #define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< \brief (AES) Mode Register */ + #define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< \brief (AES) Interrupt Enable Register */ + #define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< \brief (AES) Interrupt Disable Register */ + #define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< \brief (AES) Interrupt Mask Register */ + #define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< \brief (AES) Interrupt Status Register */ + #define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< \brief (AES) Key Word Register */ + #define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< \brief (AES) Input Data Register */ + #define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< \brief (AES) Output Data Register */ + #define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< \brief (AES) Initialization Vector Register */ + #define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< \brief (AES) Additional Authenticated Data Length Register */ + #define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< \brief (AES) Plaintext/Ciphertext Length Register */ + #define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< \brief (AES) GCM Intermediate Hash Word Register */ + #define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< \brief (AES) GCM Authentication Tag Word Register */ + #define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< \brief (AES) GCM Encryption Counter Value Register */ + #define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< \brief (AES) GCM H Word Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_AES_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_afec0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_afec0.h new file mode 100644 index 000000000..92e06f8f3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_afec0.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC0_INSTANCE_ +#define _SAMV71_AFEC0_INSTANCE_ + +/* ========== Register definition for AFEC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC0_CR (0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ +#else + #define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< \brief (AFEC0) AFEC Control Register */ + #define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< \brief (AFEC0) AFEC Mode Register */ + #define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< \brief (AFEC0) AFEC Extended Mode Register */ + #define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< \brief (AFEC0) AFEC Channel Sequence 1 Register */ + #define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< \brief (AFEC0) AFEC Channel Sequence 2 Register */ + #define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< \brief (AFEC0) AFEC Channel Enable Register */ + #define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< \brief (AFEC0) AFEC Channel Disable Register */ + #define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< \brief (AFEC0) AFEC Channel Status Register */ + #define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< \brief (AFEC0) AFEC Last Converted Data Register */ + #define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< \brief (AFEC0) AFEC Interrupt Enable Register */ + #define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< \brief (AFEC0) AFEC Interrupt Disable Register */ + #define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< \brief (AFEC0) AFEC Interrupt Mask Register */ + #define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< \brief (AFEC0) AFEC Interrupt Status Register */ + #define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< \brief (AFEC0) AFEC Overrun Status Register */ + #define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< \brief (AFEC0) AFEC Compare Window Register */ + #define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< \brief (AFEC0) AFEC Channel Gain Register */ + #define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< \brief (AFEC0) AFEC Channel Differential Register */ + #define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< \brief (AFEC0) AFEC Channel Selection Register */ + #define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< \brief (AFEC0) AFEC Channel Data Register */ + #define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< \brief (AFEC0) AFEC Channel Offset Compensation Register */ + #define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< \brief (AFEC0) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< \brief (AFEC0) AFEC Temperature Compare Window Register */ + #define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< \brief (AFEC0) AFEC Analog Control Register */ + #define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< \brief (AFEC0) AFEC Sample & Hold Mode Register */ + #define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< \brief (AFEC0) AFEC Correction Select Register */ + #define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< \brief (AFEC0) AFEC Correction Values Register */ + #define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< \brief (AFEC0) AFEC Channel Error Correction Register */ + #define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< \brief (AFEC0) AFEC Write Protection Mode Register */ + #define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< \brief (AFEC0) AFEC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_AFEC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_afec1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_afec1.h new file mode 100644 index 000000000..fff54bc91 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_afec1.h @@ -0,0 +1,96 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_AFEC1_INSTANCE_ +#define _SAMV71_AFEC1_INSTANCE_ + +/* ========== Register definition for AFEC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_AFEC1_CR (0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ +#else + #define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< \brief (AFEC1) AFEC Control Register */ + #define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< \brief (AFEC1) AFEC Mode Register */ + #define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< \brief (AFEC1) AFEC Extended Mode Register */ + #define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< \brief (AFEC1) AFEC Channel Sequence 1 Register */ + #define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< \brief (AFEC1) AFEC Channel Sequence 2 Register */ + #define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< \brief (AFEC1) AFEC Channel Enable Register */ + #define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< \brief (AFEC1) AFEC Channel Disable Register */ + #define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< \brief (AFEC1) AFEC Channel Status Register */ + #define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< \brief (AFEC1) AFEC Last Converted Data Register */ + #define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< \brief (AFEC1) AFEC Interrupt Enable Register */ + #define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< \brief (AFEC1) AFEC Interrupt Disable Register */ + #define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< \brief (AFEC1) AFEC Interrupt Mask Register */ + #define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< \brief (AFEC1) AFEC Interrupt Status Register */ + #define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< \brief (AFEC1) AFEC Overrun Status Register */ + #define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< \brief (AFEC1) AFEC Compare Window Register */ + #define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< \brief (AFEC1) AFEC Channel Gain Register */ + #define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< \brief (AFEC1) AFEC Channel Differential Register */ + #define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< \brief (AFEC1) AFEC Channel Selection Register */ + #define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< \brief (AFEC1) AFEC Channel Data Register */ + #define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< \brief (AFEC1) AFEC Channel Offset Compensation Register */ + #define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< \brief (AFEC1) AFEC Temperature Sensor Mode Register */ + #define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< \brief (AFEC1) AFEC Temperature Compare Window Register */ + #define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< \brief (AFEC1) AFEC Analog Control Register */ + #define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< \brief (AFEC1) AFEC Sample & Hold Mode Register */ + #define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< \brief (AFEC1) AFEC Correction Select Register */ + #define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< \brief (AFEC1) AFEC Correction Values Register */ + #define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< \brief (AFEC1) AFEC Channel Error Correction Register */ + #define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< \brief (AFEC1) AFEC Write Protection Mode Register */ + #define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< \brief (AFEC1) AFEC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_AFEC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_chipid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_chipid.h new file mode 100644 index 000000000..ea356a9ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_chipid.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_CHIPID_INSTANCE_ +#define _SAMV71_CHIPID_INSTANCE_ + +/* ========== Register definition for CHIPID peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_CHIPID_CIDR (0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#else + #define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< \brief (CHIPID) Chip ID Register */ + #define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< \brief (CHIPID) Chip ID Extension Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_CHIPID_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_dacc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_dacc.h new file mode 100644 index 000000000..81afe995b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_dacc.h @@ -0,0 +1,66 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_DACC_INSTANCE_ +#define _SAMV71_DACC_INSTANCE_ + +/* ========== Register definition for DACC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_DACC_CR (0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (0x400400E4U) /**< \brief (DACC) Write Protection Mode register */ + #define REG_DACC_WPSR (0x400400E8U) /**< \brief (DACC) Write Protection Status register */ +#else + #define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< \brief (DACC) Control Register */ + #define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< \brief (DACC) Mode Register */ + #define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< \brief (DACC) Trigger Register */ + #define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< \brief (DACC) Channel Enable Register */ + #define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< \brief (DACC) Channel Disable Register */ + #define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< \brief (DACC) Channel Status Register */ + #define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< \brief (DACC) Conversion Data Register */ + #define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< \brief (DACC) Interrupt Enable Register */ + #define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< \brief (DACC) Interrupt Disable Register */ + #define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< \brief (DACC) Interrupt Mask Register */ + #define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< \brief (DACC) Interrupt Status Register */ + #define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< \brief (DACC) Analog Current Register */ + #define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< \brief (DACC) Write Protection Mode register */ + #define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< \brief (DACC) Write Protection Status register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_DACC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_efc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_efc.h new file mode 100644 index 000000000..d838eb703 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_efc.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_EFC_INSTANCE_ +#define _SAMV71_EFC_INSTANCE_ + +/* ========== Register definition for EFC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_EFC_FMR (0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#else + #define REG_EFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< \brief (EFC) EEFC Flash Mode Register */ + #define REG_EFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< \brief (EFC) EEFC Flash Command Register */ + #define REG_EFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< \brief (EFC) EEFC Flash Status Register */ + #define REG_EFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< \brief (EFC) EEFC Flash Result Register */ + #define REG_EFC_VERSION (*(__I uint32_t*)0x400E0C14U) /**< \brief (EFC) EEFC Version Register */ + #define REG_EFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< \brief (EFC) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_EFC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_gmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_gmac.h new file mode 100644 index 000000000..bfb146a0b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_gmac.h @@ -0,0 +1,370 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GMAC_INSTANCE_ +#define _SAMV71_GMAC_INSTANCE_ + +/* ========== Register definition for GMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GMAC_NCR (0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_OTLO (0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register Register */ + #define REG_GMAC_ORLO (0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_ISRPQ (0x40050400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */ + #define REG_GMAC_TBQBAPQ (0x40050440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (0x40050480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (0x400504A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (0x40050600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (0x40050620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (0x40050640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#else + #define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< \brief (GMAC) Network Control Register */ + #define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< \brief (GMAC) Network Configuration Register */ + #define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< \brief (GMAC) Network Status Register */ + #define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< \brief (GMAC) User Register */ + #define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< \brief (GMAC) DMA Configuration Register */ + #define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< \brief (GMAC) Transmit Status Register */ + #define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register */ + #define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register */ + #define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< \brief (GMAC) Receive Status Register */ + #define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< \brief (GMAC) Interrupt Status Register */ + #define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< \brief (GMAC) Interrupt Enable Register */ + #define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< \brief (GMAC) Interrupt Disable Register */ + #define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< \brief (GMAC) Interrupt Mask Register */ + #define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< \brief (GMAC) PHY Maintenance Register */ + #define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< \brief (GMAC) Received Pause Quantum Register */ + #define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< \brief (GMAC) Transmit Pause Quantum Register */ + #define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< \brief (GMAC) TX Partial Store and Forward Register */ + #define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< \brief (GMAC) RX Partial Store and Forward Register */ + #define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< \brief (GMAC) RX Jumbo Frame Max Length Register */ + #define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< \brief (GMAC) Hash Register Bottom */ + #define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< \brief (GMAC) Hash Register Top */ + #define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< \brief (GMAC) Specific Address 1 Bottom Register */ + #define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< \brief (GMAC) Specific Address 1 Top Register */ + #define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< \brief (GMAC) Specific Address 2 Bottom Register */ + #define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< \brief (GMAC) Specific Address 2 Top Register */ + #define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< \brief (GMAC) Specific Address 3 Bottom Register */ + #define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< \brief (GMAC) Specific Address 3 Top Register */ + #define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< \brief (GMAC) Specific Address 4 Bottom Register */ + #define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< \brief (GMAC) Specific Address 4 Top Register */ + #define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< \brief (GMAC) Type ID Match 1 Register */ + #define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< \brief (GMAC) Type ID Match 2 Register */ + #define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< \brief (GMAC) Type ID Match 3 Register */ + #define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< \brief (GMAC) Type ID Match 4 Register */ + #define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< \brief (GMAC) Wake on LAN Register */ + #define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< \brief (GMAC) IPG Stretch Register */ + #define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< \brief (GMAC) Stacked VLAN Register */ + #define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< \brief (GMAC) Transmit PFC Pause Register */ + #define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom Register */ + #define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< \brief (GMAC) Specific Address 1 Mask Top Register */ + #define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< \brief (GMAC) 1588 Timer Nanosecond Comparison Register */ + #define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< \brief (GMAC) 1588 Timer Second Comparison Low Register */ + #define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< \brief (GMAC) 1588 Timer Second Comparison High Register */ + #define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< \brief (GMAC) PTP Event Frame Received Seconds High Register */ + #define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */ + #define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds High Register */ + #define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< \brief (GMAC) Octets Transmitted Low Register */ + #define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< \brief (GMAC) Octets Transmitted High Register */ + #define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< \brief (GMAC) Frames Transmitted Register */ + #define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */ + #define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */ + #define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< \brief (GMAC) Pause Frames Transmitted Register */ + #define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */ + #define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */ + #define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< \brief (GMAC) Transmit Underruns Register */ + #define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< \brief (GMAC) Single Collision Frames Register */ + #define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< \brief (GMAC) Multiple Collision Frames Register */ + #define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< \brief (GMAC) Excessive Collisions Register */ + #define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< \brief (GMAC) Late Collisions Register */ + #define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< \brief (GMAC) Deferred Transmission Frames Register */ + #define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< \brief (GMAC) Carrier Sense Errors Register Register */ + #define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< \brief (GMAC) Octets Received Low Received Register */ + #define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< \brief (GMAC) Octets Received High Received Register */ + #define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< \brief (GMAC) Frames Received Register */ + #define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< \brief (GMAC) Broadcast Frames Received Register */ + #define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< \brief (GMAC) Multicast Frames Received Register */ + #define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< \brief (GMAC) Pause Frames Received Register */ + #define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< \brief (GMAC) 64 Byte Frames Received Register */ + #define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */ + #define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */ + #define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< \brief (GMAC) 256 to 511 Byte Frames Received Register */ + #define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */ + #define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */ + #define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */ + #define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< \brief (GMAC) Undersize Frames Received Register */ + #define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< \brief (GMAC) Oversize Frames Received Register */ + #define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< \brief (GMAC) Jabbers Received Register */ + #define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */ + #define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< \brief (GMAC) Length Field Frame Errors Register */ + #define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< \brief (GMAC) Receive Symbol Errors Register */ + #define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< \brief (GMAC) Alignment Errors Register */ + #define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< \brief (GMAC) Receive Resource Errors Register */ + #define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< \brief (GMAC) Receive Overrun Register */ + #define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */ + #define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< \brief (GMAC) TCP Checksum Errors Register */ + #define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< \brief (GMAC) UDP Checksum Errors Register */ + #define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< \brief (GMAC) 1588 Timer Increment Sub-nanoseconds Register */ + #define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< \brief (GMAC) 1588 Timer Seconds High Register */ + #define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< \brief (GMAC) 1588 Timer Seconds Low Register */ + #define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */ + #define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */ + #define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< \brief (GMAC) 1588 Timer Increment Register */ + #define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds Low Register */ + #define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds Register */ + #define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */ + #define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */ + #define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds Low Register */ + #define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds Register */ + #define REG_GMAC_ISRPQ (*(__I uint32_t*)0x40050400U) /**< \brief (GMAC) Interrupt Status Register Priority Queue (index = 1) */ + #define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x40050440U) /**< \brief (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x40050480U) /**< \brief (GMAC) Receive Buffer Queue Base Address Register Priority Queue (index = 1) */ + #define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x400504A0U) /**< \brief (GMAC) Receive Buffer Size Register Priority Queue (index = 1) */ + #define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< \brief (GMAC) Credit-Based Shaping Control Register */ + #define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */ + #define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< \brief (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */ + #define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< \brief (GMAC) Screening Type 1 Register Priority Queue (index = 0) */ + #define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< \brief (GMAC) Screening Type 2 Register Priority Queue (index = 0) */ + #define REG_GMAC_IERPQ (*(__O uint32_t*)0x40050600U) /**< \brief (GMAC) Interrupt Enable Register Priority Queue (index = 1) */ + #define REG_GMAC_IDRPQ (*(__O uint32_t*)0x40050620U) /**< \brief (GMAC) Interrupt Disable Register Priority Queue (index = 1) */ + #define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x40050640U) /**< \brief (GMAC) Interrupt Mask Register Priority Queue (index = 1) */ + #define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< \brief (GMAC) Screening Type 2 Ethertype Register (index = 0) */ + #define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 0) */ + #define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 0) */ + #define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 1) */ + #define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 1) */ + #define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 2) */ + #define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 2) */ + #define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 3) */ + #define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 3) */ + #define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 4) */ + #define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 4) */ + #define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 5) */ + #define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 5) */ + #define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 6) */ + #define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 6) */ + #define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 7) */ + #define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 7) */ + #define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 8) */ + #define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 8) */ + #define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 9) */ + #define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 9) */ + #define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 10) */ + #define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 10) */ + #define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 11) */ + #define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 11) */ + #define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 12) */ + #define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 12) */ + #define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 13) */ + #define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 13) */ + #define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 14) */ + #define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 14) */ + #define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 15) */ + #define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 15) */ + #define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 16) */ + #define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 16) */ + #define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 17) */ + #define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 17) */ + #define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 18) */ + #define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 18) */ + #define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 19) */ + #define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 19) */ + #define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 20) */ + #define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 20) */ + #define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 21) */ + #define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 21) */ + #define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 22) */ + #define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 22) */ + #define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< \brief (GMAC) Screening Type 2 Compare Word 0 Register (index = 23) */ + #define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< \brief (GMAC) Screening Type 2 Compare Word 1 Register (index = 23) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_GMAC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_gpbr.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_gpbr.h new file mode 100644 index 000000000..6b815ecd5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_gpbr.h @@ -0,0 +1,40 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_GPBR_INSTANCE_ +#define _SAMV71_GPBR_INSTANCE_ + +/* ========== Register definition for GPBR peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#else + #define REG_GPBR_GPBR (*(__IO uint32_t*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_GPBR_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_hsmci.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_hsmci.h new file mode 100644 index 000000000..091f8d90c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_hsmci.h @@ -0,0 +1,78 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_HSMCI_INSTANCE_ +#define _SAMV71_HSMCI_INSTANCE_ + +/* ========== Register definition for HSMCI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_HSMCI_CR (0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_FIFO (0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#else + #define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< \brief (HSMCI) Control Register */ + #define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< \brief (HSMCI) Mode Register */ + #define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< \brief (HSMCI) Data Timeout Register */ + #define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< \brief (HSMCI) SD/SDIO Card Register */ + #define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< \brief (HSMCI) Argument Register */ + #define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< \brief (HSMCI) Command Register */ + #define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< \brief (HSMCI) Block Register */ + #define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */ + #define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< \brief (HSMCI) Response Register */ + #define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< \brief (HSMCI) Receive Data Register */ + #define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< \brief (HSMCI) Transmit Data Register */ + #define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< \brief (HSMCI) Status Register */ + #define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< \brief (HSMCI) Interrupt Enable Register */ + #define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< \brief (HSMCI) Interrupt Disable Register */ + #define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< \brief (HSMCI) Interrupt Mask Register */ + #define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< \brief (HSMCI) DMA Configuration Register */ + #define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< \brief (HSMCI) Configuration Register */ + #define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< \brief (HSMCI) Write Protection Mode Register */ + #define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< \brief (HSMCI) Write Protection Status Register */ + #define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_HSMCI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_icm.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_icm.h new file mode 100644 index 000000000..4d1995070 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_icm.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ICM_INSTANCE_ +#define _SAMV71_ICM_INSTANCE_ + +/* ========== Register definition for ICM peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ICM_CFG (0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ +#else + #define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< \brief (ICM) Configuration Register */ + #define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< \brief (ICM) Control Register */ + #define REG_ICM_SR (*(__O uint32_t*)0x40048008U) /**< \brief (ICM) Status Register */ + #define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< \brief (ICM) Interrupt Enable Register */ + #define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< \brief (ICM) Interrupt Disable Register */ + #define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< \brief (ICM) Interrupt Mask Register */ + #define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< \brief (ICM) Interrupt Status Register */ + #define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< \brief (ICM) Undefined Access Status Register */ + #define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< \brief (ICM) Region Descriptor Area Start Address Register */ + #define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< \brief (ICM) Region Hash Area Start Address Register */ + #define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< \brief (ICM) User Initial Hash Value 0 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_ICM_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_isi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_isi.h new file mode 100644 index 000000000..d2d72cbb1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_isi.h @@ -0,0 +1,88 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ISI_INSTANCE_ +#define _SAMV71_ISI_INSTANCE_ + +/* ========== Register definition for ISI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_ISI_CFG1 (0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ +#else + #define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< \brief (ISI) ISI Configuration 1 Register */ + #define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< \brief (ISI) ISI Configuration 2 Register */ + #define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< \brief (ISI) ISI Preview Size Register */ + #define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< \brief (ISI) ISI Preview Decimation Factor Register */ + #define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */ + #define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< \brief (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */ + #define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */ + #define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */ + #define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< \brief (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */ + #define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< \brief (ISI) ISI Control Register */ + #define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< \brief (ISI) ISI Status Register */ + #define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< \brief (ISI) ISI Interrupt Enable Register */ + #define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< \brief (ISI) ISI Interrupt Disable Register */ + #define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< \brief (ISI) ISI Interrupt Mask Register */ + #define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< \brief (ISI) DMA Channel Enable Register */ + #define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< \brief (ISI) DMA Channel Disable Register */ + #define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< \brief (ISI) DMA Channel Status Register */ + #define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< \brief (ISI) DMA Preview Base Address Register */ + #define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< \brief (ISI) DMA Preview Control Register */ + #define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< \brief (ISI) DMA Preview Descriptor Address Register */ + #define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< \brief (ISI) DMA Codec Base Address Register */ + #define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< \brief (ISI) DMA Codec Control Register */ + #define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< \brief (ISI) DMA Codec Descriptor Address Register */ + #define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< \brief (ISI) Write Protection Mode Register */ + #define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< \brief (ISI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_ISI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_matrix.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_matrix.h new file mode 100644 index 000000000..91ce03ab8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_matrix.h @@ -0,0 +1,90 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MATRIX_INSTANCE_ +#define _SAMV71_MATRIX_INSTANCE_ + +/* ========== Register definition for MATRIX peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MATRIX_MCFG (0x40088000U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_SMCNFCS (0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ +#else + #define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< \brief (MATRIX) Master Configuration Register */ + #define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< \brief (MATRIX) Slave Configuration Register */ + #define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< \brief (MATRIX) Priority Register A for Slave 0 */ + #define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< \brief (MATRIX) Priority Register B for Slave 0 */ + #define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< \brief (MATRIX) Priority Register A for Slave 1 */ + #define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */ + #define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< \brief (MATRIX) Priority Register A for Slave 2 */ + #define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< \brief (MATRIX) Priority Register B for Slave 2 */ + #define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< \brief (MATRIX) Priority Register A for Slave 3 */ + #define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */ + #define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */ + #define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */ + #define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */ + #define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */ + #define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */ + #define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */ + #define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */ + #define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */ + #define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */ + #define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */ + #define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< \brief (MATRIX) Master Remap Control Register */ + #define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< \brief (MATRIX) CAN0 Configuration Register */ + #define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< \brief (MATRIX) System I/O and CAN1 Configuration Register */ + #define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< \brief (MATRIX) SMC NAND Flash Chip Select Configuration Register */ + #define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< \brief (MATRIX) Write Protection Mode Register */ + #define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< \brief (MATRIX) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MATRIX_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mcan0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mcan0.h new file mode 100644 index 000000000..a109f99c5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mcan0.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN0_INSTANCE_ +#define _SAMV71_MCAN0_INSTANCE_ + +/* ========== Register definition for MCAN0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN0_CUST (0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_IR (0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< \brief (MCAN0) Customer Register */ + #define REG_MCAN0_FBTP (*(__IO uint32_t*)0x4003000CU) /**< \brief (MCAN0) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< \brief (MCAN0) Test Register */ + #define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< \brief (MCAN0) RAM Watchdog Register */ + #define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< \brief (MCAN0) CC Control Register */ + #define REG_MCAN0_BTP (*(__IO uint32_t*)0x4003001CU) /**< \brief (MCAN0) Bit Timing and Prescaler Register */ + #define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< \brief (MCAN0) Timestamp Counter Configuration Register */ + #define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< \brief (MCAN0) Timestamp Counter Value Register */ + #define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< \brief (MCAN0) Timeout Counter Configuration Register */ + #define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< \brief (MCAN0) Timeout Counter Value Register */ + #define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< \brief (MCAN0) Error Counter Register */ + #define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< \brief (MCAN0) Protocol Status Register */ + #define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< \brief (MCAN0) Interrupt Register */ + #define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< \brief (MCAN0) Interrupt Enable Register */ + #define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< \brief (MCAN0) Interrupt Line Select Register */ + #define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< \brief (MCAN0) Interrupt Line Enable Register */ + #define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< \brief (MCAN0) Global Filter Configuration Register */ + #define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< \brief (MCAN0) Standard ID Filter Configuration Register */ + #define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< \brief (MCAN0) Extended ID Filter Configuration Register */ + #define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< \brief (MCAN0) Extended ID AND Mask Register */ + #define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< \brief (MCAN0) High Priority Message Status Register */ + #define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< \brief (MCAN0) New Data 1 Register */ + #define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< \brief (MCAN0) New Data 2 Register */ + #define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< \brief (MCAN0) Receive FIFO 0 Configuration Register */ + #define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< \brief (MCAN0) Receive FIFO 0 Status Register */ + #define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< \brief (MCAN0) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< \brief (MCAN0) Receive Rx Buffer Configuration Register */ + #define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< \brief (MCAN0) Receive FIFO 1 Configuration Register */ + #define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< \brief (MCAN0) Receive FIFO 1 Status Register */ + #define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< \brief (MCAN0) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< \brief (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< \brief (MCAN0) Transmit Buffer Configuration Register */ + #define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< \brief (MCAN0) Transmit FIFO/Queue Status Register */ + #define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< \brief (MCAN0) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< \brief (MCAN0) Transmit Buffer Request Pending Register */ + #define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< \brief (MCAN0) Transmit Buffer Add Request Register */ + #define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< \brief (MCAN0) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< \brief (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< \brief (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< \brief (MCAN0) Transmit Event FIFO Configuration Register */ + #define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< \brief (MCAN0) Transmit Event FIFO Status Register */ + #define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< \brief (MCAN0) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MCAN0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mcan1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mcan1.h new file mode 100644 index 000000000..c7c5b9910 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mcan1.h @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MCAN1_INSTANCE_ +#define _SAMV71_MCAN1_INSTANCE_ + +/* ========== Register definition for MCAN1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MCAN1_CUST (0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_IR (0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#else + #define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< \brief (MCAN1) Customer Register */ + #define REG_MCAN1_FBTP (*(__IO uint32_t*)0x4003400CU) /**< \brief (MCAN1) Fast Bit Timing and Prescaler Register */ + #define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< \brief (MCAN1) Test Register */ + #define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< \brief (MCAN1) RAM Watchdog Register */ + #define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< \brief (MCAN1) CC Control Register */ + #define REG_MCAN1_BTP (*(__IO uint32_t*)0x4003401CU) /**< \brief (MCAN1) Bit Timing and Prescaler Register */ + #define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< \brief (MCAN1) Timestamp Counter Configuration Register */ + #define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< \brief (MCAN1) Timestamp Counter Value Register */ + #define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< \brief (MCAN1) Timeout Counter Configuration Register */ + #define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< \brief (MCAN1) Timeout Counter Value Register */ + #define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< \brief (MCAN1) Error Counter Register */ + #define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< \brief (MCAN1) Protocol Status Register */ + #define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< \brief (MCAN1) Interrupt Register */ + #define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< \brief (MCAN1) Interrupt Enable Register */ + #define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< \brief (MCAN1) Interrupt Line Select Register */ + #define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< \brief (MCAN1) Interrupt Line Enable Register */ + #define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< \brief (MCAN1) Global Filter Configuration Register */ + #define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< \brief (MCAN1) Standard ID Filter Configuration Register */ + #define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< \brief (MCAN1) Extended ID Filter Configuration Register */ + #define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< \brief (MCAN1) Extended ID AND Mask Register */ + #define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< \brief (MCAN1) High Priority Message Status Register */ + #define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< \brief (MCAN1) New Data 1 Register */ + #define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< \brief (MCAN1) New Data 2 Register */ + #define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< \brief (MCAN1) Receive FIFO 0 Configuration Register */ + #define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< \brief (MCAN1) Receive FIFO 0 Status Register */ + #define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< \brief (MCAN1) Receive FIFO 0 Acknowledge Register */ + #define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< \brief (MCAN1) Receive Rx Buffer Configuration Register */ + #define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< \brief (MCAN1) Receive FIFO 1 Configuration Register */ + #define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< \brief (MCAN1) Receive FIFO 1 Status Register */ + #define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< \brief (MCAN1) Receive FIFO 1 Acknowledge Register */ + #define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< \brief (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */ + #define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< \brief (MCAN1) Transmit Buffer Configuration Register */ + #define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< \brief (MCAN1) Transmit FIFO/Queue Status Register */ + #define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< \brief (MCAN1) Transmit Buffer Element Size Configuration Register */ + #define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< \brief (MCAN1) Transmit Buffer Request Pending Register */ + #define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< \brief (MCAN1) Transmit Buffer Add Request Register */ + #define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Request Register */ + #define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< \brief (MCAN1) Transmit Buffer Transmission Occurred Register */ + #define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Register */ + #define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< \brief (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */ + #define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< \brief (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */ + #define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< \brief (MCAN1) Transmit Event FIFO Configuration Register */ + #define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< \brief (MCAN1) Transmit Event FIFO Status Register */ + #define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< \brief (MCAN1) Transmit Event FIFO Acknowledge Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MCAN1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mlb.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mlb.h new file mode 100644 index 000000000..1db417233 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_mlb.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_MLB_INSTANCE_ +#define _SAMV71_MLB_INSTANCE_ + +/* ========== Register definition for MLB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_MLB_MLBC0 (0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ + #define REG_MLB_MS0 (0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ + #define REG_MLB_MS1 (0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ + #define REG_MLB_MSS (0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ + #define REG_MLB_MSD (0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ + #define REG_MLB_MIEN (0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ + #define REG_MLB_MLBC1 (0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ + #define REG_MLB_HCTL (0x40068080U) /**< \brief (MLB) HBI Control Register */ + #define REG_MLB_HCMR (0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ + #define REG_MLB_HCER (0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ + #define REG_MLB_HCBR (0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ + #define REG_MLB_MDAT (0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ + #define REG_MLB_MDWE (0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ + #define REG_MLB_MCTL (0x400680E0U) /**< \brief (MLB) MIF Control Register */ + #define REG_MLB_MADR (0x400680E4U) /**< \brief (MLB) MIF Address Register */ + #define REG_MLB_ACTL (0x400683C0U) /**< \brief (MLB) AHB Control Register */ + #define REG_MLB_ACSR (0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ + #define REG_MLB_ACMR (0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ +#else + #define REG_MLB_MLBC0 (*(__IO uint32_t*)0x40068000U) /**< \brief (MLB) MediaLB Control 0 Register */ + #define REG_MLB_MS0 (*(__IO uint32_t*)0x4006800CU) /**< \brief (MLB) MediaLB Channel Status 0 Register */ + #define REG_MLB_MS1 (*(__IO uint32_t*)0x40068014U) /**< \brief (MLB) MediaLB Channel Status1 Register */ + #define REG_MLB_MSS (*(__IO uint32_t*)0x40068020U) /**< \brief (MLB) MediaLB System Status Register */ + #define REG_MLB_MSD (*(__I uint32_t*)0x40068024U) /**< \brief (MLB) MediaLB System Data Register */ + #define REG_MLB_MIEN (*(__IO uint32_t*)0x4006802CU) /**< \brief (MLB) MediaLB Interrupt Enable Register */ + #define REG_MLB_MLBC1 (*(__IO uint32_t*)0x4006803CU) /**< \brief (MLB) MediaLB Control 1 Register */ + #define REG_MLB_HCTL (*(__IO uint32_t*)0x40068080U) /**< \brief (MLB) HBI Control Register */ + #define REG_MLB_HCMR (*(__IO uint32_t*)0x40068088U) /**< \brief (MLB) HBI Channel Mask 0 Register */ + #define REG_MLB_HCER (*(__I uint32_t*)0x40068090U) /**< \brief (MLB) HBI Channel Error 0 Register */ + #define REG_MLB_HCBR (*(__I uint32_t*)0x40068098U) /**< \brief (MLB) HBI Channel Busy 0 Register */ + #define REG_MLB_MDAT (*(__IO uint32_t*)0x400680C0U) /**< \brief (MLB) MIF Data 0 Register */ + #define REG_MLB_MDWE (*(__IO uint32_t*)0x400680D0U) /**< \brief (MLB) MIF Data Write Enable 0 Register */ + #define REG_MLB_MCTL (*(__IO uint32_t*)0x400680E0U) /**< \brief (MLB) MIF Control Register */ + #define REG_MLB_MADR (*(__IO uint32_t*)0x400680E4U) /**< \brief (MLB) MIF Address Register */ + #define REG_MLB_ACTL (*(__IO uint32_t*)0x400683C0U) /**< \brief (MLB) AHB Control Register */ + #define REG_MLB_ACSR (*(__IO uint32_t*)0x400683D0U) /**< \brief (MLB) AHB Channel Status 0 Register */ + #define REG_MLB_ACMR (*(__IO uint32_t*)0x400683D8U) /**< \brief (MLB) AHB Channel Mask 0 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_MLB_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioa.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioa.h new file mode 100644 index 000000000..6f8b06571 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioa.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOA_INSTANCE_ +#define _SAMV71_PIOA_INSTANCE_ + +/* ========== Register definition for PIOA peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_KER (0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */ + #define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */ + #define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */ + #define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */ + #define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */ + #define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */ + #define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */ + #define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */ + #define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */ + #define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */ + #define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */ + #define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */ + #define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */ + #define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */ + #define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */ + #define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */ + #define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */ + #define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */ + #define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */ + #define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */ + #define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */ + #define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */ + #define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */ + #define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */ + #define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */ + #define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */ + #define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */ + #define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */ + #define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */ + #define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */ + #define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */ + #define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */ + #define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */ + #define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */ + #define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */ + #define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disable Register */ + #define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */ + #define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */ + #define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */ + #define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */ + #define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low-Level Select Register */ + #define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/High-Level Select Register */ + #define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */ + #define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */ + #define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< \brief (PIOA) Write Protection Mode Register */ + #define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< \brief (PIOA) Write Protection Status Register */ + #define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */ + #define REG_PIOA_KER (*(__IO uint32_t*)0x400E0F20U) /**< \brief (PIOA) Keypad Controller Enable Register */ + #define REG_PIOA_KRCR (*(__IO uint32_t*)0x400E0F24U) /**< \brief (PIOA) Keypad Controller Row Column Register */ + #define REG_PIOA_KDR (*(__IO uint32_t*)0x400E0F28U) /**< \brief (PIOA) Keypad Controller Debouncing Register */ + #define REG_PIOA_KIER (*(__O uint32_t*)0x400E0F30U) /**< \brief (PIOA) Keypad Controller Interrupt Enable Register */ + #define REG_PIOA_KIDR (*(__O uint32_t*)0x400E0F34U) /**< \brief (PIOA) Keypad Controller Interrupt Disable Register */ + #define REG_PIOA_KIMR (*(__I uint32_t*)0x400E0F38U) /**< \brief (PIOA) Keypad Controller Interrupt Mask Register */ + #define REG_PIOA_KSR (*(__I uint32_t*)0x400E0F3CU) /**< \brief (PIOA) Keypad Controller Status Register */ + #define REG_PIOA_KKPR (*(__I uint32_t*)0x400E0F40U) /**< \brief (PIOA) Keypad Controller Key Press Register */ + #define REG_PIOA_KKRR (*(__I uint32_t*)0x400E0F44U) /**< \brief (PIOA) Keypad Controller Key Release Register */ + #define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */ + #define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */ + #define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */ + #define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */ + #define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */ + #define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOA_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_piob.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_piob.h new file mode 100644 index 000000000..c6232ecdf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_piob.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOB_INSTANCE_ +#define _SAMV71_PIOB_INSTANCE_ + +/* ========== Register definition for PIOB peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_KER (0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */ + #define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */ + #define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */ + #define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */ + #define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */ + #define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< \brief (PIOB) Output Status Register */ + #define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */ + #define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */ + #define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */ + #define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */ + #define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */ + #define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */ + #define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */ + #define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */ + #define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */ + #define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */ + #define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */ + #define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */ + #define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */ + #define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */ + #define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */ + #define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */ + #define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */ + #define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */ + #define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */ + #define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */ + #define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */ + #define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */ + #define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */ + #define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */ + #define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */ + #define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */ + #define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */ + #define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */ + #define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */ + #define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disable Register */ + #define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */ + #define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */ + #define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */ + #define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */ + #define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low-Level Select Register */ + #define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/High-Level Select Register */ + #define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */ + #define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< \brief (PIOB) Lock Status */ + #define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< \brief (PIOB) Write Protection Mode Register */ + #define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< \brief (PIOB) Write Protection Status Register */ + #define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */ + #define REG_PIOB_KER (*(__IO uint32_t*)0x400E1120U) /**< \brief (PIOB) Keypad Controller Enable Register */ + #define REG_PIOB_KRCR (*(__IO uint32_t*)0x400E1124U) /**< \brief (PIOB) Keypad Controller Row Column Register */ + #define REG_PIOB_KDR (*(__IO uint32_t*)0x400E1128U) /**< \brief (PIOB) Keypad Controller Debouncing Register */ + #define REG_PIOB_KIER (*(__O uint32_t*)0x400E1130U) /**< \brief (PIOB) Keypad Controller Interrupt Enable Register */ + #define REG_PIOB_KIDR (*(__O uint32_t*)0x400E1134U) /**< \brief (PIOB) Keypad Controller Interrupt Disable Register */ + #define REG_PIOB_KIMR (*(__I uint32_t*)0x400E1138U) /**< \brief (PIOB) Keypad Controller Interrupt Mask Register */ + #define REG_PIOB_KSR (*(__I uint32_t*)0x400E113CU) /**< \brief (PIOB) Keypad Controller Status Register */ + #define REG_PIOB_KKPR (*(__I uint32_t*)0x400E1140U) /**< \brief (PIOB) Keypad Controller Key Press Register */ + #define REG_PIOB_KKRR (*(__I uint32_t*)0x400E1144U) /**< \brief (PIOB) Keypad Controller Key Release Register */ + #define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */ + #define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */ + #define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */ + #define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */ + #define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */ + #define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOB_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioc.h new file mode 100644 index 000000000..a15a33e6c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioc.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOC_INSTANCE_ +#define _SAMV71_PIOC_INSTANCE_ + +/* ========== Register definition for PIOC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_KER (0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */ + #define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */ + #define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */ + #define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */ + #define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */ + #define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< \brief (PIOC) Output Status Register */ + #define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */ + #define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */ + #define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */ + #define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */ + #define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */ + #define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */ + #define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */ + #define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */ + #define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */ + #define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */ + #define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */ + #define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */ + #define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */ + #define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */ + #define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */ + #define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */ + #define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */ + #define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */ + #define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */ + #define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */ + #define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */ + #define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */ + #define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */ + #define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */ + #define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */ + #define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */ + #define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */ + #define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */ + #define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */ + #define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disable Register */ + #define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */ + #define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */ + #define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */ + #define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */ + #define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low-Level Select Register */ + #define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/High-Level Select Register */ + #define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */ + #define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< \brief (PIOC) Lock Status */ + #define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< \brief (PIOC) Write Protection Mode Register */ + #define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< \brief (PIOC) Write Protection Status Register */ + #define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */ + #define REG_PIOC_KER (*(__IO uint32_t*)0x400E1320U) /**< \brief (PIOC) Keypad Controller Enable Register */ + #define REG_PIOC_KRCR (*(__IO uint32_t*)0x400E1324U) /**< \brief (PIOC) Keypad Controller Row Column Register */ + #define REG_PIOC_KDR (*(__IO uint32_t*)0x400E1328U) /**< \brief (PIOC) Keypad Controller Debouncing Register */ + #define REG_PIOC_KIER (*(__O uint32_t*)0x400E1330U) /**< \brief (PIOC) Keypad Controller Interrupt Enable Register */ + #define REG_PIOC_KIDR (*(__O uint32_t*)0x400E1334U) /**< \brief (PIOC) Keypad Controller Interrupt Disable Register */ + #define REG_PIOC_KIMR (*(__I uint32_t*)0x400E1338U) /**< \brief (PIOC) Keypad Controller Interrupt Mask Register */ + #define REG_PIOC_KSR (*(__I uint32_t*)0x400E133CU) /**< \brief (PIOC) Keypad Controller Status Register */ + #define REG_PIOC_KKPR (*(__I uint32_t*)0x400E1340U) /**< \brief (PIOC) Keypad Controller Key Press Register */ + #define REG_PIOC_KKRR (*(__I uint32_t*)0x400E1344U) /**< \brief (PIOC) Keypad Controller Key Release Register */ + #define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */ + #define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */ + #define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */ + #define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */ + #define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */ + #define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_piod.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_piod.h new file mode 100644 index 000000000..4fab74046 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_piod.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOD_INSTANCE_ +#define _SAMV71_PIOD_INSTANCE_ + +/* ========== Register definition for PIOD peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_KER (0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */ + #define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */ + #define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */ + #define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */ + #define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */ + #define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< \brief (PIOD) Output Status Register */ + #define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */ + #define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */ + #define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */ + #define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */ + #define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */ + #define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */ + #define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */ + #define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */ + #define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */ + #define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */ + #define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */ + #define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */ + #define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */ + #define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */ + #define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */ + #define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */ + #define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */ + #define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */ + #define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */ + #define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */ + #define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */ + #define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */ + #define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */ + #define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */ + #define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */ + #define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */ + #define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */ + #define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */ + #define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */ + #define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disable Register */ + #define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */ + #define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */ + #define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */ + #define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */ + #define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low-Level Select Register */ + #define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/High-Level Select Register */ + #define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */ + #define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< \brief (PIOD) Lock Status */ + #define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< \brief (PIOD) Write Protection Mode Register */ + #define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< \brief (PIOD) Write Protection Status Register */ + #define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */ + #define REG_PIOD_KER (*(__IO uint32_t*)0x400E1520U) /**< \brief (PIOD) Keypad Controller Enable Register */ + #define REG_PIOD_KRCR (*(__IO uint32_t*)0x400E1524U) /**< \brief (PIOD) Keypad Controller Row Column Register */ + #define REG_PIOD_KDR (*(__IO uint32_t*)0x400E1528U) /**< \brief (PIOD) Keypad Controller Debouncing Register */ + #define REG_PIOD_KIER (*(__O uint32_t*)0x400E1530U) /**< \brief (PIOD) Keypad Controller Interrupt Enable Register */ + #define REG_PIOD_KIDR (*(__O uint32_t*)0x400E1534U) /**< \brief (PIOD) Keypad Controller Interrupt Disable Register */ + #define REG_PIOD_KIMR (*(__I uint32_t*)0x400E1538U) /**< \brief (PIOD) Keypad Controller Interrupt Mask Register */ + #define REG_PIOD_KSR (*(__I uint32_t*)0x400E153CU) /**< \brief (PIOD) Keypad Controller Status Register */ + #define REG_PIOD_KKPR (*(__I uint32_t*)0x400E1540U) /**< \brief (PIOD) Keypad Controller Key Press Register */ + #define REG_PIOD_KKRR (*(__I uint32_t*)0x400E1544U) /**< \brief (PIOD) Keypad Controller Key Release Register */ + #define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */ + #define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */ + #define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */ + #define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */ + #define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */ + #define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOD_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioe.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioe.h new file mode 100644 index 000000000..63629dc57 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pioe.h @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PIOE_INSTANCE_ +#define _SAMV71_PIOE_INSTANCE_ + +/* ========== Register definition for PIOE peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_KER (0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#else + #define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */ + #define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */ + #define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */ + #define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */ + #define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */ + #define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< \brief (PIOE) Output Status Register */ + #define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */ + #define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */ + #define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */ + #define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */ + #define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */ + #define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */ + #define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */ + #define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */ + #define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */ + #define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */ + #define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */ + #define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */ + #define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */ + #define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */ + #define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */ + #define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */ + #define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */ + #define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */ + #define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */ + #define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */ + #define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */ + #define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */ + #define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */ + #define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */ + #define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */ + #define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */ + #define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */ + #define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */ + #define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */ + #define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disable Register */ + #define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */ + #define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */ + #define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */ + #define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */ + #define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low-Level Select Register */ + #define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/High-Level Select Register */ + #define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */ + #define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< \brief (PIOE) Lock Status */ + #define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< \brief (PIOE) Write Protection Mode Register */ + #define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< \brief (PIOE) Write Protection Status Register */ + #define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */ + #define REG_PIOE_KER (*(__IO uint32_t*)0x400E1720U) /**< \brief (PIOE) Keypad Controller Enable Register */ + #define REG_PIOE_KRCR (*(__IO uint32_t*)0x400E1724U) /**< \brief (PIOE) Keypad Controller Row Column Register */ + #define REG_PIOE_KDR (*(__IO uint32_t*)0x400E1728U) /**< \brief (PIOE) Keypad Controller Debouncing Register */ + #define REG_PIOE_KIER (*(__O uint32_t*)0x400E1730U) /**< \brief (PIOE) Keypad Controller Interrupt Enable Register */ + #define REG_PIOE_KIDR (*(__O uint32_t*)0x400E1734U) /**< \brief (PIOE) Keypad Controller Interrupt Disable Register */ + #define REG_PIOE_KIMR (*(__I uint32_t*)0x400E1738U) /**< \brief (PIOE) Keypad Controller Interrupt Mask Register */ + #define REG_PIOE_KSR (*(__I uint32_t*)0x400E173CU) /**< \brief (PIOE) Keypad Controller Status Register */ + #define REG_PIOE_KKPR (*(__I uint32_t*)0x400E1740U) /**< \brief (PIOE) Keypad Controller Key Press Register */ + #define REG_PIOE_KKRR (*(__I uint32_t*)0x400E1744U) /**< \brief (PIOE) Keypad Controller Key Release Register */ + #define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */ + #define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */ + #define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */ + #define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */ + #define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */ + #define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PIOE_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pmc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pmc.h new file mode 100644 index 000000000..369d31a26 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pmc.h @@ -0,0 +1,110 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PMC_INSTANCE_ +#define _SAMV71_PMC_INSTANCE_ + +/* ========== Register definition for PMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_SLPWK_ER1 (0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ +#else + #define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */ + #define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */ + #define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */ + #define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */ + #define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */ + #define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */ + #define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */ + #define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */ + #define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */ + #define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */ + #define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */ + #define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */ + #define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */ + #define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */ + #define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */ + #define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */ + #define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */ + #define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Startup Mode Register */ + #define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Startup Polarity Register */ + #define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */ + #define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protection Mode Register */ + #define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protection Status Register */ + #define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */ + #define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */ + #define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */ + #define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */ + #define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< \brief (PMC) Oscillator Calibration Register */ + #define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< \brief (PMC) SleepWalking Enable Register 0 */ + #define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< \brief (PMC) SleepWalking Disable Register 0 */ + #define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< \brief (PMC) SleepWalking Status Register 0 */ + #define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< \brief (PMC) SleepWalking Activity Status Register 0 */ + #define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< \brief (PMC) SleepWalking Enable Register 1 */ + #define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< \brief (PMC) SleepWalking Disable Register 1 */ + #define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< \brief (PMC) SleepWalking Status Register 1 */ + #define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< \brief (PMC) SleepWalking Activity Status Register 1 */ + #define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< \brief (PMC) SleepWalking Activity In Progress Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pwm0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pwm0.h new file mode 100644 index 000000000..fe993fb55 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pwm0.h @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM0_INSTANCE_ +#define _SAMV71_PWM0_INSTANCE_ + +/* ========== Register definition for PWM0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM0_CLK (0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_CMPV0 (0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM0_ETRG3 (0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM0_LEBR3 (0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM0_ETRG4 (0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM0_LEBR4 (0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#else + #define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< \brief (PWM0) PWM Clock Register */ + #define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< \brief (PWM0) PWM Enable Register */ + #define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< \brief (PWM0) PWM Disable Register */ + #define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< \brief (PWM0) PWM Status Register */ + #define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< \brief (PWM0) PWM Interrupt Enable Register 1 */ + #define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< \brief (PWM0) PWM Interrupt Disable Register 1 */ + #define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< \brief (PWM0) PWM Interrupt Mask Register 1 */ + #define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< \brief (PWM0) PWM Interrupt Status Register 1 */ + #define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< \brief (PWM0) PWM Sync Channels Mode Register */ + #define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< \brief (PWM0) PWM DMA Register */ + #define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< \brief (PWM0) PWM Sync Channels Update Control Register */ + #define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< \brief (PWM0) PWM Sync Channels Update Period Register */ + #define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< \brief (PWM0) PWM Sync Channels Update Period Update Register */ + #define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< \brief (PWM0) PWM Interrupt Enable Register 2 */ + #define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< \brief (PWM0) PWM Interrupt Disable Register 2 */ + #define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< \brief (PWM0) PWM Interrupt Mask Register 2 */ + #define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< \brief (PWM0) PWM Interrupt Status Register 2 */ + #define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< \brief (PWM0) PWM Output Override Value Register */ + #define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< \brief (PWM0) PWM Output Selection Register */ + #define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< \brief (PWM0) PWM Output Selection Set Register */ + #define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< \brief (PWM0) PWM Output Selection Clear Register */ + #define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< \brief (PWM0) PWM Output Selection Set Update Register */ + #define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< \brief (PWM0) PWM Output Selection Clear Update Register */ + #define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< \brief (PWM0) PWM Fault Mode Register */ + #define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< \brief (PWM0) PWM Fault Status Register */ + #define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< \brief (PWM0) PWM Fault Clear Register */ + #define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< \brief (PWM0) PWM Fault Protection Value Register 1 */ + #define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< \brief (PWM0) PWM Fault Protection Enable Register */ + #define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< \brief (PWM0) PWM Event Line 0 Mode Register */ + #define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< \brief (PWM0) PWM Spread Spectrum Register */ + #define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< \brief (PWM0) PWM Spread Spectrum Update Register */ + #define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< \brief (PWM0) PWM Stepper Motor Mode Register */ + #define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< \brief (PWM0) PWM Fault Protection Value 2 Register */ + #define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< \brief (PWM0) PWM Write Protection Control Register */ + #define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< \brief (PWM0) PWM Write Protection Status Register */ + #define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< \brief (PWM0) PWM Comparison 0 Value Register */ + #define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< \brief (PWM0) PWM Comparison 0 Value Update Register */ + #define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< \brief (PWM0) PWM Comparison 0 Mode Register */ + #define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< \brief (PWM0) PWM Comparison 0 Mode Update Register */ + #define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< \brief (PWM0) PWM Comparison 1 Value Register */ + #define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< \brief (PWM0) PWM Comparison 1 Value Update Register */ + #define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< \brief (PWM0) PWM Comparison 1 Mode Register */ + #define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< \brief (PWM0) PWM Comparison 1 Mode Update Register */ + #define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< \brief (PWM0) PWM Comparison 2 Value Register */ + #define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< \brief (PWM0) PWM Comparison 2 Value Update Register */ + #define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< \brief (PWM0) PWM Comparison 2 Mode Register */ + #define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< \brief (PWM0) PWM Comparison 2 Mode Update Register */ + #define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< \brief (PWM0) PWM Comparison 3 Value Register */ + #define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< \brief (PWM0) PWM Comparison 3 Value Update Register */ + #define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< \brief (PWM0) PWM Comparison 3 Mode Register */ + #define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< \brief (PWM0) PWM Comparison 3 Mode Update Register */ + #define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< \brief (PWM0) PWM Comparison 4 Value Register */ + #define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< \brief (PWM0) PWM Comparison 4 Value Update Register */ + #define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< \brief (PWM0) PWM Comparison 4 Mode Register */ + #define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< \brief (PWM0) PWM Comparison 4 Mode Update Register */ + #define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< \brief (PWM0) PWM Comparison 5 Value Register */ + #define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< \brief (PWM0) PWM Comparison 5 Value Update Register */ + #define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< \brief (PWM0) PWM Comparison 5 Mode Register */ + #define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< \brief (PWM0) PWM Comparison 5 Mode Update Register */ + #define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< \brief (PWM0) PWM Comparison 6 Value Register */ + #define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< \brief (PWM0) PWM Comparison 6 Value Update Register */ + #define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< \brief (PWM0) PWM Comparison 6 Mode Register */ + #define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< \brief (PWM0) PWM Comparison 6 Mode Update Register */ + #define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< \brief (PWM0) PWM Comparison 7 Value Register */ + #define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< \brief (PWM0) PWM Comparison 7 Value Update Register */ + #define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< \brief (PWM0) PWM Comparison 7 Mode Register */ + #define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< \brief (PWM0) PWM Comparison 7 Mode Update Register */ + #define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< \brief (PWM0) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< \brief (PWM0) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< \brief (PWM0) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< \brief (PWM0) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< \brief (PWM0) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< \brief (PWM0) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< \brief (PWM0) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< \brief (PWM0) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< \brief (PWM0) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM0_ETRG3 (*(__IO uint32_t*)0x4002046CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM0_LEBR3 (*(__IO uint32_t*)0x40020470U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM0_ETRG4 (*(__IO uint32_t*)0x4002048CU) /**< \brief (PWM0) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM0_LEBR4 (*(__IO uint32_t*)0x40020490U) /**< \brief (PWM0) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PWM0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pwm1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pwm1.h new file mode 100644 index 000000000..0f4eb11d5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_pwm1.h @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_PWM1_INSTANCE_ +#define _SAMV71_PWM1_INSTANCE_ + +/* ========== Register definition for PWM1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_PWM1_CLK (0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_CMPV0 (0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM1_ETRG3 (0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM1_LEBR3 (0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM1_ETRG4 (0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM1_LEBR4 (0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#else + #define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< \brief (PWM1) PWM Clock Register */ + #define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< \brief (PWM1) PWM Enable Register */ + #define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< \brief (PWM1) PWM Disable Register */ + #define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< \brief (PWM1) PWM Status Register */ + #define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< \brief (PWM1) PWM Interrupt Enable Register 1 */ + #define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< \brief (PWM1) PWM Interrupt Disable Register 1 */ + #define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< \brief (PWM1) PWM Interrupt Mask Register 1 */ + #define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< \brief (PWM1) PWM Interrupt Status Register 1 */ + #define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< \brief (PWM1) PWM Sync Channels Mode Register */ + #define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< \brief (PWM1) PWM DMA Register */ + #define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< \brief (PWM1) PWM Sync Channels Update Control Register */ + #define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< \brief (PWM1) PWM Sync Channels Update Period Register */ + #define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< \brief (PWM1) PWM Sync Channels Update Period Update Register */ + #define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< \brief (PWM1) PWM Interrupt Enable Register 2 */ + #define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< \brief (PWM1) PWM Interrupt Disable Register 2 */ + #define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< \brief (PWM1) PWM Interrupt Mask Register 2 */ + #define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< \brief (PWM1) PWM Interrupt Status Register 2 */ + #define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< \brief (PWM1) PWM Output Override Value Register */ + #define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< \brief (PWM1) PWM Output Selection Register */ + #define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< \brief (PWM1) PWM Output Selection Set Register */ + #define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< \brief (PWM1) PWM Output Selection Clear Register */ + #define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< \brief (PWM1) PWM Output Selection Set Update Register */ + #define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< \brief (PWM1) PWM Output Selection Clear Update Register */ + #define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< \brief (PWM1) PWM Fault Mode Register */ + #define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< \brief (PWM1) PWM Fault Status Register */ + #define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< \brief (PWM1) PWM Fault Clear Register */ + #define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< \brief (PWM1) PWM Fault Protection Value Register 1 */ + #define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< \brief (PWM1) PWM Fault Protection Enable Register */ + #define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< \brief (PWM1) PWM Event Line 0 Mode Register */ + #define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< \brief (PWM1) PWM Spread Spectrum Register */ + #define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< \brief (PWM1) PWM Spread Spectrum Update Register */ + #define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< \brief (PWM1) PWM Stepper Motor Mode Register */ + #define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< \brief (PWM1) PWM Fault Protection Value 2 Register */ + #define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< \brief (PWM1) PWM Write Protection Control Register */ + #define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< \brief (PWM1) PWM Write Protection Status Register */ + #define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< \brief (PWM1) PWM Comparison 0 Value Register */ + #define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< \brief (PWM1) PWM Comparison 0 Value Update Register */ + #define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< \brief (PWM1) PWM Comparison 0 Mode Register */ + #define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< \brief (PWM1) PWM Comparison 0 Mode Update Register */ + #define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< \brief (PWM1) PWM Comparison 1 Value Register */ + #define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< \brief (PWM1) PWM Comparison 1 Value Update Register */ + #define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< \brief (PWM1) PWM Comparison 1 Mode Register */ + #define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< \brief (PWM1) PWM Comparison 1 Mode Update Register */ + #define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< \brief (PWM1) PWM Comparison 2 Value Register */ + #define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< \brief (PWM1) PWM Comparison 2 Value Update Register */ + #define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< \brief (PWM1) PWM Comparison 2 Mode Register */ + #define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< \brief (PWM1) PWM Comparison 2 Mode Update Register */ + #define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< \brief (PWM1) PWM Comparison 3 Value Register */ + #define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< \brief (PWM1) PWM Comparison 3 Value Update Register */ + #define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< \brief (PWM1) PWM Comparison 3 Mode Register */ + #define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< \brief (PWM1) PWM Comparison 3 Mode Update Register */ + #define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< \brief (PWM1) PWM Comparison 4 Value Register */ + #define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< \brief (PWM1) PWM Comparison 4 Value Update Register */ + #define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< \brief (PWM1) PWM Comparison 4 Mode Register */ + #define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< \brief (PWM1) PWM Comparison 4 Mode Update Register */ + #define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< \brief (PWM1) PWM Comparison 5 Value Register */ + #define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< \brief (PWM1) PWM Comparison 5 Value Update Register */ + #define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< \brief (PWM1) PWM Comparison 5 Mode Register */ + #define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< \brief (PWM1) PWM Comparison 5 Mode Update Register */ + #define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< \brief (PWM1) PWM Comparison 6 Value Register */ + #define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< \brief (PWM1) PWM Comparison 6 Value Update Register */ + #define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< \brief (PWM1) PWM Comparison 6 Mode Register */ + #define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< \brief (PWM1) PWM Comparison 6 Mode Update Register */ + #define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< \brief (PWM1) PWM Comparison 7 Value Register */ + #define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< \brief (PWM1) PWM Comparison 7 Value Update Register */ + #define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< \brief (PWM1) PWM Comparison 7 Mode Register */ + #define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< \brief (PWM1) PWM Comparison 7 Mode Update Register */ + #define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 0) */ + #define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 0) */ + #define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 0) */ + #define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 0) */ + #define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 0) */ + #define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 0) */ + #define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 0) */ + #define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 0) */ + #define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 1) */ + #define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 1) */ + #define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 1) */ + #define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 1) */ + #define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 1) */ + #define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 1) */ + #define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 1) */ + #define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 1) */ + #define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 2) */ + #define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 2) */ + #define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 2) */ + #define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 2) */ + #define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 2) */ + #define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 2) */ + #define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 2) */ + #define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 2) */ + #define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< \brief (PWM1) PWM Channel Mode Register (ch_num = 3) */ + #define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< \brief (PWM1) PWM Channel Duty Cycle Register (ch_num = 3) */ + #define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< \brief (PWM1) PWM Channel Duty Cycle Update Register (ch_num = 3) */ + #define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< \brief (PWM1) PWM Channel Period Register (ch_num = 3) */ + #define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< \brief (PWM1) PWM Channel Period Update Register (ch_num = 3) */ + #define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< \brief (PWM1) PWM Channel Counter Register (ch_num = 3) */ + #define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< \brief (PWM1) PWM Channel Dead Time Register (ch_num = 3) */ + #define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< \brief (PWM1) PWM Channel Dead Time Update Register (ch_num = 3) */ + #define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 0) */ + #define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 1) */ + #define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 1) */ + #define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */ + #define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 2) */ + #define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 2) */ + #define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */ + #define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< \brief (PWM1) PWM Channel Mode Update Register (ch_num = 3) */ + #define REG_PWM1_ETRG3 (*(__IO uint32_t*)0x4005C46CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 3) */ + #define REG_PWM1_LEBR3 (*(__IO uint32_t*)0x4005C470U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 3) */ + #define REG_PWM1_ETRG4 (*(__IO uint32_t*)0x4005C48CU) /**< \brief (PWM1) PWM External Trigger Register (trg_num = 4) */ + #define REG_PWM1_LEBR4 (*(__IO uint32_t*)0x4005C490U) /**< \brief (PWM1) PWM Leading-Edge Blanking Register (trg_num = 4) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_PWM1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_qspi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_qspi.h new file mode 100644 index 000000000..a2bc751c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_qspi.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_QSPI_INSTANCE_ +#define _SAMV71_QSPI_INSTANCE_ + +/* ========== Register definition for QSPI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_QSPI_CR (0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ +#else + #define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< \brief (QSPI) Control Register */ + #define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< \brief (QSPI) Mode Register */ + #define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< \brief (QSPI) Receive Data Register */ + #define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< \brief (QSPI) Transmit Data Register */ + #define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< \brief (QSPI) Status Register */ + #define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< \brief (QSPI) Interrupt Enable Register */ + #define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< \brief (QSPI) Interrupt Disable Register */ + #define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< \brief (QSPI) Interrupt Mask Register */ + #define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< \brief (QSPI) Serial Clock Register */ + #define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< \brief (QSPI) Instruction Address Register */ + #define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< \brief (QSPI) Instruction Code Register */ + #define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< \brief (QSPI) Instruction Frame Register */ + #define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< \brief (QSPI) Scrambling Mode Register */ + #define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< \brief (QSPI) Scrambling Key Register */ + #define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< \brief (QSPI) Write Protection Mode Register */ + #define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< \brief (QSPI) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_QSPI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rstc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rstc.h new file mode 100644 index 000000000..fb07bd139 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rstc.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSTC_INSTANCE_ +#define _SAMV71_RSTC_INSTANCE_ + +/* ========== Register definition for RSTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */ +#else + #define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< \brief (RSTC) Control Register */ + #define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< \brief (RSTC) Status Register */ + #define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< \brief (RSTC) Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RSTC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rswdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rswdt.h new file mode 100644 index 000000000..a754c0837 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rswdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RSWDT_INSTANCE_ +#define _SAMV71_RSWDT_INSTANCE_ + +/* ========== Register definition for RSWDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RSWDT_CR (0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (0x400E1908U) /**< \brief (RSWDT) Status Register */ +#else + #define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< \brief (RSWDT) Control Register */ + #define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< \brief (RSWDT) Mode Register */ + #define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< \brief (RSWDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RSWDT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rtc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rtc.h new file mode 100644 index 000000000..7dbe3774f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rtc.h @@ -0,0 +1,62 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTC_INSTANCE_ +#define _SAMV71_RTC_INSTANCE_ + +/* ========== Register definition for RTC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */ +#else + #define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< \brief (RTC) Control Register */ + #define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< \brief (RTC) Mode Register */ + #define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< \brief (RTC) Time Register */ + #define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< \brief (RTC) Calendar Register */ + #define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */ + #define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */ + #define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< \brief (RTC) Status Register */ + #define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */ + #define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */ + #define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */ + #define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */ + #define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RTC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rtt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rtt.h new file mode 100644 index 000000000..7d9657bff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_rtt.h @@ -0,0 +1,46 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_RTT_INSTANCE_ +#define _SAMV71_RTT_INSTANCE_ + +/* ========== Register definition for RTT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */ +#else + #define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< \brief (RTT) Mode Register */ + #define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< \brief (RTT) Alarm Register */ + #define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< \brief (RTT) Value Register */ + #define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< \brief (RTT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_RTT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_sdramc.h new file mode 100644 index 000000000..91b689bf7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_sdramc.h @@ -0,0 +1,64 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SDRAMC_INSTANCE_ +#define _SAMV71_SDRAMC_INSTANCE_ + +/* ========== Register definition for SDRAMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SDRAMC_MR (0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ +#else + #define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< \brief (SDRAMC) SDRAMC Mode Register */ + #define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */ + #define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< \brief (SDRAMC) SDRAMC Configuration Register */ + #define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< \brief (SDRAMC) SDRAMC Low Power Register */ + #define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */ + #define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */ + #define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */ + #define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */ + #define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */ + #define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */ + #define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< \brief (SDRAMC) SDRAMC OCMS Register */ + #define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< \brief (SDRAMC) SDRAMC OCMS KEY1 Register */ + #define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< \brief (SDRAMC) SDRAMC OCMS KEY2 Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SDRAMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_smc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_smc.h new file mode 100644 index 000000000..4e5bd62fc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_smc.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SMC_INSTANCE_ +#define _SAMV71_SMC_INSTANCE_ + +/* ========== Register definition for SMC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SMC_SETUP0 (0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */ + #define REG_SMC_OCMS (0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#else + #define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */ + #define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */ + #define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */ + #define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< \brief (SMC) SMC MODE Register (CS_number = 0) */ + #define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */ + #define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */ + #define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */ + #define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< \brief (SMC) SMC MODE Register (CS_number = 1) */ + #define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */ + #define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */ + #define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */ + #define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< \brief (SMC) SMC MODE Register (CS_number = 2) */ + #define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */ + #define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */ + #define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */ + #define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< \brief (SMC) SMC MODE Register (CS_number = 3) */ + #define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< \brief (SMC) SMC OCMS MODE Register */ + #define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< \brief (SMC) SMC OCMS KEY1 Register */ + #define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< \brief (SMC) SMC OCMS KEY2 Register */ + #define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< \brief (SMC) SMC Write Protection Mode Register */ + #define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< \brief (SMC) SMC Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SMC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_spi0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_spi0.h new file mode 100644 index 000000000..76b0ca7c6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_spi0.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI0_INSTANCE_ +#define _SAMV71_SPI0_INSTANCE_ + +/* ========== Register definition for SPI0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI0_CR (0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (0x40008030U) /**< \brief (SPI0) Chip Select Register */ + #define REG_SPI0_WPMR (0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#else + #define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< \brief (SPI0) Control Register */ + #define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< \brief (SPI0) Mode Register */ + #define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< \brief (SPI0) Receive Data Register */ + #define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< \brief (SPI0) Transmit Data Register */ + #define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< \brief (SPI0) Status Register */ + #define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< \brief (SPI0) Interrupt Enable Register */ + #define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< \brief (SPI0) Interrupt Disable Register */ + #define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< \brief (SPI0) Interrupt Mask Register */ + #define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< \brief (SPI0) Chip Select Register */ + #define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< \brief (SPI0) Write Protection Mode Register */ + #define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< \brief (SPI0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SPI0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_spi1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_spi1.h new file mode 100644 index 000000000..4efcbb714 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_spi1.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SPI1_INSTANCE_ +#define _SAMV71_SPI1_INSTANCE_ + +/* ========== Register definition for SPI1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SPI1_CR (0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (0x40058030U) /**< \brief (SPI1) Chip Select Register */ + #define REG_SPI1_WPMR (0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ +#else + #define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< \brief (SPI1) Control Register */ + #define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< \brief (SPI1) Mode Register */ + #define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< \brief (SPI1) Receive Data Register */ + #define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< \brief (SPI1) Transmit Data Register */ + #define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< \brief (SPI1) Status Register */ + #define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< \brief (SPI1) Interrupt Enable Register */ + #define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< \brief (SPI1) Interrupt Disable Register */ + #define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< \brief (SPI1) Interrupt Mask Register */ + #define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< \brief (SPI1) Chip Select Register */ + #define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< \brief (SPI1) Write Protection Mode Register */ + #define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< \brief (SPI1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SPI1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_ssc.h new file mode 100644 index 000000000..eb17eed35 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_ssc.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SSC_INSTANCE_ +#define _SAMV71_SSC_INSTANCE_ + +/* ========== Register definition for SSC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SSC_CR (0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ +#else + #define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< \brief (SSC) Control Register */ + #define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< \brief (SSC) Clock Mode Register */ + #define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< \brief (SSC) Receive Clock Mode Register */ + #define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< \brief (SSC) Receive Frame Mode Register */ + #define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< \brief (SSC) Transmit Clock Mode Register */ + #define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< \brief (SSC) Transmit Frame Mode Register */ + #define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< \brief (SSC) Receive Holding Register */ + #define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< \brief (SSC) Transmit Holding Register */ + #define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< \brief (SSC) Receive Sync. Holding Register */ + #define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< \brief (SSC) Transmit Sync. Holding Register */ + #define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< \brief (SSC) Receive Compare 0 Register */ + #define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< \brief (SSC) Receive Compare 1 Register */ + #define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< \brief (SSC) Status Register */ + #define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< \brief (SSC) Interrupt Enable Register */ + #define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< \brief (SSC) Interrupt Disable Register */ + #define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< \brief (SSC) Interrupt Mask Register */ + #define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< \brief (SSC) Write Protection Mode Register */ + #define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< \brief (SSC) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SSC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_supc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_supc.h new file mode 100644 index 000000000..66591cb7a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_supc.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_SUPC_INSTANCE_ +#define _SAMV71_SUPC_INSTANCE_ + +/* ========== Register definition for SUPC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ +#else + #define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */ + #define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */ + #define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */ + #define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake-up Mode Register */ + #define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake-up Inputs Register */ + #define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_SUPC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc0.h new file mode 100644 index 000000000..db1c3eae8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc0.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC0_INSTANCE_ +#define _SAMV71_TC0_INSTANCE_ + +/* ========== Register definition for TC0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC0_CCR0 (0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ +#else + #define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< \brief (TC0) Channel Control Register (channel = 0) */ + #define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */ + #define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< \brief (TC0) Register AB (channel = 0) */ + #define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< \brief (TC0) Counter Value (channel = 0) */ + #define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< \brief (TC0) Register A (channel = 0) */ + #define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< \brief (TC0) Register B (channel = 0) */ + #define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< \brief (TC0) Register C (channel = 0) */ + #define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< \brief (TC0) Status Register (channel = 0) */ + #define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */ + #define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */ + #define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */ + #define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */ + #define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< \brief (TC0) Channel Control Register (channel = 1) */ + #define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */ + #define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< \brief (TC0) Register AB (channel = 1) */ + #define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< \brief (TC0) Counter Value (channel = 1) */ + #define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< \brief (TC0) Register A (channel = 1) */ + #define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< \brief (TC0) Register B (channel = 1) */ + #define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< \brief (TC0) Register C (channel = 1) */ + #define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< \brief (TC0) Status Register (channel = 1) */ + #define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */ + #define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */ + #define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */ + #define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */ + #define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< \brief (TC0) Channel Control Register (channel = 2) */ + #define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */ + #define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< \brief (TC0) Register AB (channel = 2) */ + #define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< \brief (TC0) Counter Value (channel = 2) */ + #define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< \brief (TC0) Register A (channel = 2) */ + #define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< \brief (TC0) Register B (channel = 2) */ + #define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< \brief (TC0) Register C (channel = 2) */ + #define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< \brief (TC0) Status Register (channel = 2) */ + #define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */ + #define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */ + #define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */ + #define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */ + #define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< \brief (TC0) Block Control Register */ + #define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< \brief (TC0) Block Mode Register */ + #define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */ + #define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */ + #define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */ + #define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< \brief (TC0) QDEC Interrupt Status Register */ + #define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< \brief (TC0) Fault Mode Register */ + #define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< \brief (TC0) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc1.h new file mode 100644 index 000000000..e09fa011e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc1.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC1_INSTANCE_ +#define _SAMV71_TC1_INSTANCE_ + +/* ========== Register definition for TC1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC1_CCR0 (0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ +#else + #define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< \brief (TC1) Channel Control Register (channel = 0) */ + #define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */ + #define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< \brief (TC1) Register AB (channel = 0) */ + #define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< \brief (TC1) Counter Value (channel = 0) */ + #define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< \brief (TC1) Register A (channel = 0) */ + #define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< \brief (TC1) Register B (channel = 0) */ + #define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< \brief (TC1) Register C (channel = 0) */ + #define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< \brief (TC1) Status Register (channel = 0) */ + #define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */ + #define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */ + #define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */ + #define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */ + #define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< \brief (TC1) Channel Control Register (channel = 1) */ + #define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */ + #define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< \brief (TC1) Register AB (channel = 1) */ + #define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< \brief (TC1) Counter Value (channel = 1) */ + #define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< \brief (TC1) Register A (channel = 1) */ + #define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< \brief (TC1) Register B (channel = 1) */ + #define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< \brief (TC1) Register C (channel = 1) */ + #define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< \brief (TC1) Status Register (channel = 1) */ + #define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */ + #define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */ + #define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */ + #define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */ + #define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< \brief (TC1) Channel Control Register (channel = 2) */ + #define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */ + #define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< \brief (TC1) Register AB (channel = 2) */ + #define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< \brief (TC1) Counter Value (channel = 2) */ + #define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< \brief (TC1) Register A (channel = 2) */ + #define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< \brief (TC1) Register B (channel = 2) */ + #define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< \brief (TC1) Register C (channel = 2) */ + #define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< \brief (TC1) Status Register (channel = 2) */ + #define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */ + #define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */ + #define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */ + #define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */ + #define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< \brief (TC1) Block Control Register */ + #define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< \brief (TC1) Block Mode Register */ + #define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */ + #define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */ + #define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */ + #define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< \brief (TC1) QDEC Interrupt Status Register */ + #define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< \brief (TC1) Fault Mode Register */ + #define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< \brief (TC1) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc2.h new file mode 100644 index 000000000..093af7766 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc2.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC2_INSTANCE_ +#define _SAMV71_TC2_INSTANCE_ + +/* ========== Register definition for TC2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC2_CCR0 (0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ +#else + #define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< \brief (TC2) Channel Control Register (channel = 0) */ + #define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */ + #define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< \brief (TC2) Register AB (channel = 0) */ + #define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< \brief (TC2) Counter Value (channel = 0) */ + #define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< \brief (TC2) Register A (channel = 0) */ + #define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< \brief (TC2) Register B (channel = 0) */ + #define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< \brief (TC2) Register C (channel = 0) */ + #define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< \brief (TC2) Status Register (channel = 0) */ + #define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */ + #define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */ + #define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */ + #define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */ + #define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< \brief (TC2) Channel Control Register (channel = 1) */ + #define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */ + #define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< \brief (TC2) Register AB (channel = 1) */ + #define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< \brief (TC2) Counter Value (channel = 1) */ + #define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< \brief (TC2) Register A (channel = 1) */ + #define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< \brief (TC2) Register B (channel = 1) */ + #define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< \brief (TC2) Register C (channel = 1) */ + #define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< \brief (TC2) Status Register (channel = 1) */ + #define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */ + #define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */ + #define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */ + #define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */ + #define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< \brief (TC2) Channel Control Register (channel = 2) */ + #define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */ + #define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< \brief (TC2) Register AB (channel = 2) */ + #define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< \brief (TC2) Counter Value (channel = 2) */ + #define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< \brief (TC2) Register A (channel = 2) */ + #define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< \brief (TC2) Register B (channel = 2) */ + #define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< \brief (TC2) Register C (channel = 2) */ + #define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< \brief (TC2) Status Register (channel = 2) */ + #define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */ + #define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */ + #define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */ + #define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */ + #define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< \brief (TC2) Block Control Register */ + #define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< \brief (TC2) Block Mode Register */ + #define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */ + #define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */ + #define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */ + #define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< \brief (TC2) QDEC Interrupt Status Register */ + #define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< \brief (TC2) Fault Mode Register */ + #define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< \brief (TC2) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc3.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc3.h new file mode 100644 index 000000000..57888b2ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_tc3.h @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TC3_INSTANCE_ +#define _SAMV71_TC3_INSTANCE_ + +/* ========== Register definition for TC3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TC3_CCR0 (0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ +#else + #define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< \brief (TC3) Channel Control Register (channel = 0) */ + #define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< \brief (TC3) Channel Mode Register (channel = 0) */ + #define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 0) */ + #define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< \brief (TC3) Register AB (channel = 0) */ + #define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< \brief (TC3) Counter Value (channel = 0) */ + #define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< \brief (TC3) Register A (channel = 0) */ + #define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< \brief (TC3) Register B (channel = 0) */ + #define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< \brief (TC3) Register C (channel = 0) */ + #define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< \brief (TC3) Status Register (channel = 0) */ + #define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< \brief (TC3) Interrupt Enable Register (channel = 0) */ + #define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< \brief (TC3) Interrupt Disable Register (channel = 0) */ + #define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< \brief (TC3) Interrupt Mask Register (channel = 0) */ + #define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< \brief (TC3) Extended Mode Register (channel = 0) */ + #define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< \brief (TC3) Channel Control Register (channel = 1) */ + #define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< \brief (TC3) Channel Mode Register (channel = 1) */ + #define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 1) */ + #define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< \brief (TC3) Register AB (channel = 1) */ + #define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< \brief (TC3) Counter Value (channel = 1) */ + #define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< \brief (TC3) Register A (channel = 1) */ + #define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< \brief (TC3) Register B (channel = 1) */ + #define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< \brief (TC3) Register C (channel = 1) */ + #define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< \brief (TC3) Status Register (channel = 1) */ + #define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< \brief (TC3) Interrupt Enable Register (channel = 1) */ + #define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< \brief (TC3) Interrupt Disable Register (channel = 1) */ + #define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< \brief (TC3) Interrupt Mask Register (channel = 1) */ + #define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< \brief (TC3) Extended Mode Register (channel = 1) */ + #define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< \brief (TC3) Channel Control Register (channel = 2) */ + #define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< \brief (TC3) Channel Mode Register (channel = 2) */ + #define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< \brief (TC3) Stepper Motor Mode Register (channel = 2) */ + #define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< \brief (TC3) Register AB (channel = 2) */ + #define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< \brief (TC3) Counter Value (channel = 2) */ + #define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< \brief (TC3) Register A (channel = 2) */ + #define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< \brief (TC3) Register B (channel = 2) */ + #define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< \brief (TC3) Register C (channel = 2) */ + #define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< \brief (TC3) Status Register (channel = 2) */ + #define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< \brief (TC3) Interrupt Enable Register (channel = 2) */ + #define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< \brief (TC3) Interrupt Disable Register (channel = 2) */ + #define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< \brief (TC3) Interrupt Mask Register (channel = 2) */ + #define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< \brief (TC3) Extended Mode Register (channel = 2) */ + #define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< \brief (TC3) Block Control Register */ + #define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< \brief (TC3) Block Mode Register */ + #define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< \brief (TC3) QDEC Interrupt Enable Register */ + #define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< \brief (TC3) QDEC Interrupt Disable Register */ + #define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< \brief (TC3) QDEC Interrupt Mask Register */ + #define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< \brief (TC3) QDEC Interrupt Status Register */ + #define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< \brief (TC3) Fault Mode Register */ + #define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< \brief (TC3) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TC3_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_trng.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_trng.h new file mode 100644 index 000000000..0b9fad8bb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TRNG_INSTANCE_ +#define _SAMV71_TRNG_INSTANCE_ + +/* ========== Register definition for TRNG peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TRNG_CR (0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (0x40070050U) /**< \brief (TRNG) Output Data Register */ +#else + #define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< \brief (TRNG) Control Register */ + #define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< \brief (TRNG) Interrupt Enable Register */ + #define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< \brief (TRNG) Interrupt Disable Register */ + #define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< \brief (TRNG) Interrupt Mask Register */ + #define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< \brief (TRNG) Interrupt Status Register */ + #define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< \brief (TRNG) Output Data Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TRNG_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs0.h new file mode 100644 index 000000000..6d4a44b16 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs0.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS0_INSTANCE_ +#define _SAMV71_TWIHS0_INSTANCE_ + +/* ========== Register definition for TWIHS0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS0_CR (0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_WPMR (0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ +#else + #define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< \brief (TWIHS0) Control Register */ + #define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< \brief (TWIHS0) Master Mode Register */ + #define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< \brief (TWIHS0) Slave Mode Register */ + #define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< \brief (TWIHS0) Internal Address Register */ + #define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< \brief (TWIHS0) Clock Waveform Generator Register */ + #define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< \brief (TWIHS0) Status Register */ + #define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< \brief (TWIHS0) Interrupt Enable Register */ + #define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< \brief (TWIHS0) Interrupt Disable Register */ + #define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< \brief (TWIHS0) Interrupt Mask Register */ + #define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< \brief (TWIHS0) Receive Holding Register */ + #define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< \brief (TWIHS0) Transmit Holding Register */ + #define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< \brief (TWIHS0) SMBus Timing Register */ + #define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< \brief (TWIHS0) Filter Register */ + #define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< \brief (TWIHS0) SleepWalking Matching Register */ + #define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< \brief (TWIHS0) Write Protection Mode Register */ + #define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< \brief (TWIHS0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TWIHS0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs1.h new file mode 100644 index 000000000..9909b79c0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs1.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS1_INSTANCE_ +#define _SAMV71_TWIHS1_INSTANCE_ + +/* ========== Register definition for TWIHS1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS1_CR (0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_WPMR (0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ +#else + #define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< \brief (TWIHS1) Control Register */ + #define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< \brief (TWIHS1) Master Mode Register */ + #define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< \brief (TWIHS1) Slave Mode Register */ + #define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< \brief (TWIHS1) Internal Address Register */ + #define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< \brief (TWIHS1) Clock Waveform Generator Register */ + #define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< \brief (TWIHS1) Status Register */ + #define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< \brief (TWIHS1) Interrupt Enable Register */ + #define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< \brief (TWIHS1) Interrupt Disable Register */ + #define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< \brief (TWIHS1) Interrupt Mask Register */ + #define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< \brief (TWIHS1) Receive Holding Register */ + #define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< \brief (TWIHS1) Transmit Holding Register */ + #define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< \brief (TWIHS1) SMBus Timing Register */ + #define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< \brief (TWIHS1) Filter Register */ + #define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< \brief (TWIHS1) SleepWalking Matching Register */ + #define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< \brief (TWIHS1) Write Protection Mode Register */ + #define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< \brief (TWIHS1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TWIHS1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs2.h new file mode 100644 index 000000000..9ca673768 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_twihs2.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_TWIHS2_INSTANCE_ +#define _SAMV71_TWIHS2_INSTANCE_ + +/* ========== Register definition for TWIHS2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_TWIHS2_CR (0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_WPMR (0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ +#else + #define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< \brief (TWIHS2) Control Register */ + #define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< \brief (TWIHS2) Master Mode Register */ + #define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< \brief (TWIHS2) Slave Mode Register */ + #define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< \brief (TWIHS2) Internal Address Register */ + #define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< \brief (TWIHS2) Clock Waveform Generator Register */ + #define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< \brief (TWIHS2) Status Register */ + #define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< \brief (TWIHS2) Interrupt Enable Register */ + #define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< \brief (TWIHS2) Interrupt Disable Register */ + #define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< \brief (TWIHS2) Interrupt Mask Register */ + #define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< \brief (TWIHS2) Receive Holding Register */ + #define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< \brief (TWIHS2) Transmit Holding Register */ + #define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< \brief (TWIHS2) SMBus Timing Register */ + #define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< \brief (TWIHS2) Filter Register */ + #define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< \brief (TWIHS2) SleepWalking Matching Register */ + #define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< \brief (TWIHS2) Write Protection Mode Register */ + #define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< \brief (TWIHS2) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_TWIHS2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart0.h new file mode 100644 index 000000000..f9db636eb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart0.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART0_INSTANCE_ +#define _SAMV71_UART0_INSTANCE_ + +/* ========== Register definition for UART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART0_CR (0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ +#else + #define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< \brief (UART0) Control Register */ + #define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< \brief (UART0) Mode Register */ + #define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< \brief (UART0) Interrupt Enable Register */ + #define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< \brief (UART0) Interrupt Disable Register */ + #define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< \brief (UART0) Interrupt Mask Register */ + #define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< \brief (UART0) Status Register */ + #define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< \brief (UART0) Receive Holding Register */ + #define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< \brief (UART0) Transmit Holding Register */ + #define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< \brief (UART0) Baud Rate Generator Register */ + #define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< \brief (UART0) Comparison Register */ + #define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< \brief (UART0) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart1.h new file mode 100644 index 000000000..f23717124 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart1.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART1_INSTANCE_ +#define _SAMV71_UART1_INSTANCE_ + +/* ========== Register definition for UART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART1_CR (0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ +#else + #define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< \brief (UART1) Control Register */ + #define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< \brief (UART1) Mode Register */ + #define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< \brief (UART1) Interrupt Enable Register */ + #define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< \brief (UART1) Interrupt Disable Register */ + #define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< \brief (UART1) Interrupt Mask Register */ + #define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< \brief (UART1) Status Register */ + #define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< \brief (UART1) Receive Holding Register */ + #define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< \brief (UART1) Transmit Holding Register */ + #define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< \brief (UART1) Baud Rate Generator Register */ + #define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< \brief (UART1) Comparison Register */ + #define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< \brief (UART1) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart2.h new file mode 100644 index 000000000..b2e04a5ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart2.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART2_INSTANCE_ +#define _SAMV71_UART2_INSTANCE_ + +/* ========== Register definition for UART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART2_CR (0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ +#else + #define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< \brief (UART2) Control Register */ + #define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< \brief (UART2) Mode Register */ + #define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< \brief (UART2) Interrupt Enable Register */ + #define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< \brief (UART2) Interrupt Disable Register */ + #define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< \brief (UART2) Interrupt Mask Register */ + #define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< \brief (UART2) Status Register */ + #define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< \brief (UART2) Receive Holding Register */ + #define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< \brief (UART2) Transmit Holding Register */ + #define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< \brief (UART2) Baud Rate Generator Register */ + #define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< \brief (UART2) Comparison Register */ + #define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< \brief (UART2) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart3.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart3.h new file mode 100644 index 000000000..65468521c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart3.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART3_INSTANCE_ +#define _SAMV71_UART3_INSTANCE_ + +/* ========== Register definition for UART3 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART3_CR (0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ +#else + #define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< \brief (UART3) Control Register */ + #define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< \brief (UART3) Mode Register */ + #define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< \brief (UART3) Interrupt Enable Register */ + #define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< \brief (UART3) Interrupt Disable Register */ + #define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< \brief (UART3) Interrupt Mask Register */ + #define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< \brief (UART3) Status Register */ + #define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< \brief (UART3) Receive Holding Register */ + #define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< \brief (UART3) Transmit Holding Register */ + #define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< \brief (UART3) Baud Rate Generator Register */ + #define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< \brief (UART3) Comparison Register */ + #define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< \brief (UART3) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART3_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart4.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart4.h new file mode 100644 index 000000000..8e9d3447f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_uart4.h @@ -0,0 +1,60 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UART4_INSTANCE_ +#define _SAMV71_UART4_INSTANCE_ + +/* ========== Register definition for UART4 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UART4_CR (0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ +#else + #define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< \brief (UART4) Control Register */ + #define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< \brief (UART4) Mode Register */ + #define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< \brief (UART4) Interrupt Enable Register */ + #define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< \brief (UART4) Interrupt Disable Register */ + #define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< \brief (UART4) Interrupt Mask Register */ + #define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< \brief (UART4) Status Register */ + #define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< \brief (UART4) Receive Holding Register */ + #define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< \brief (UART4) Transmit Holding Register */ + #define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< \brief (UART4) Baud Rate Generator Register */ + #define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< \brief (UART4) Comparison Register */ + #define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< \brief (UART4) Write Protection Mode Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UART4_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart0.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart0.h new file mode 100644 index 000000000..4114f457e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart0.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART0_INSTANCE_ +#define _SAMV71_USART0_INSTANCE_ + +/* ========== Register definition for USART0 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART0_CR (0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_MAN (0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ +#else + #define REG_USART0_CR (*(__O uint32_t*)0x40024000U) /**< \brief (USART0) Control Register */ + #define REG_USART0_MR (*(__IO uint32_t*)0x40024004U) /**< \brief (USART0) Mode Register */ + #define REG_USART0_IER (*(__O uint32_t*)0x40024008U) /**< \brief (USART0) Interrupt Enable Register */ + #define REG_USART0_IDR (*(__O uint32_t*)0x4002400CU) /**< \brief (USART0) Interrupt Disable Register */ + #define REG_USART0_IMR (*(__I uint32_t*)0x40024010U) /**< \brief (USART0) Interrupt Mask Register */ + #define REG_USART0_CSR (*(__I uint32_t*)0x40024014U) /**< \brief (USART0) Channel Status Register */ + #define REG_USART0_RHR (*(__I uint32_t*)0x40024018U) /**< \brief (USART0) Receive Holding Register */ + #define REG_USART0_THR (*(__O uint32_t*)0x4002401CU) /**< \brief (USART0) Transmit Holding Register */ + #define REG_USART0_BRGR (*(__IO uint32_t*)0x40024020U) /**< \brief (USART0) Baud Rate Generator Register */ + #define REG_USART0_RTOR (*(__IO uint32_t*)0x40024024U) /**< \brief (USART0) Receiver Time-out Register */ + #define REG_USART0_TTGR (*(__IO uint32_t*)0x40024028U) /**< \brief (USART0) Transmitter Timeguard Register */ + #define REG_USART0_MAN (*(__IO uint32_t*)0x40024050U) /**< \brief (USART0) Manchester Configuration Register */ + #define REG_USART0_LINMR (*(__IO uint32_t*)0x40024054U) /**< \brief (USART0) LIN Mode Register */ + #define REG_USART0_LINIR (*(__IO uint32_t*)0x40024058U) /**< \brief (USART0) LIN Identifier Register */ + #define REG_USART0_LINBRR (*(__I uint32_t*)0x4002405CU) /**< \brief (USART0) LIN Baud Rate Register */ + #define REG_USART0_LONMR (*(__IO uint32_t*)0x40024060U) /**< \brief (USART0) LON Mode Register */ + #define REG_USART0_LONPR (*(__IO uint32_t*)0x40024064U) /**< \brief (USART0) LON Preamble Register */ + #define REG_USART0_LONDL (*(__IO uint32_t*)0x40024068U) /**< \brief (USART0) LON Data Length Register */ + #define REG_USART0_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< \brief (USART0) LON L2HDR Register */ + #define REG_USART0_LONBL (*(__I uint32_t*)0x40024070U) /**< \brief (USART0) LON Backlog Register */ + #define REG_USART0_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< \brief (USART0) LON Beta1 Tx Register */ + #define REG_USART0_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< \brief (USART0) LON Beta1 Rx Register */ + #define REG_USART0_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< \brief (USART0) LON Priority Register */ + #define REG_USART0_IDTTX (*(__IO uint32_t*)0x40024080U) /**< \brief (USART0) LON IDT Tx Register */ + #define REG_USART0_IDTRX (*(__IO uint32_t*)0x40024084U) /**< \brief (USART0) LON IDT Rx Register */ + #define REG_USART0_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< \brief (USART0) IC DIFF Register */ + #define REG_USART0_WPMR (*(__IO uint32_t*)0x400240E4U) /**< \brief (USART0) Write Protection Mode Register */ + #define REG_USART0_WPSR (*(__I uint32_t*)0x400240E8U) /**< \brief (USART0) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USART0_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart1.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart1.h new file mode 100644 index 000000000..b34876104 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart1.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART1_INSTANCE_ +#define _SAMV71_USART1_INSTANCE_ + +/* ========== Register definition for USART1 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART1_CR (0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_MAN (0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ +#else + #define REG_USART1_CR (*(__O uint32_t*)0x40028000U) /**< \brief (USART1) Control Register */ + #define REG_USART1_MR (*(__IO uint32_t*)0x40028004U) /**< \brief (USART1) Mode Register */ + #define REG_USART1_IER (*(__O uint32_t*)0x40028008U) /**< \brief (USART1) Interrupt Enable Register */ + #define REG_USART1_IDR (*(__O uint32_t*)0x4002800CU) /**< \brief (USART1) Interrupt Disable Register */ + #define REG_USART1_IMR (*(__I uint32_t*)0x40028010U) /**< \brief (USART1) Interrupt Mask Register */ + #define REG_USART1_CSR (*(__I uint32_t*)0x40028014U) /**< \brief (USART1) Channel Status Register */ + #define REG_USART1_RHR (*(__I uint32_t*)0x40028018U) /**< \brief (USART1) Receive Holding Register */ + #define REG_USART1_THR (*(__O uint32_t*)0x4002801CU) /**< \brief (USART1) Transmit Holding Register */ + #define REG_USART1_BRGR (*(__IO uint32_t*)0x40028020U) /**< \brief (USART1) Baud Rate Generator Register */ + #define REG_USART1_RTOR (*(__IO uint32_t*)0x40028024U) /**< \brief (USART1) Receiver Time-out Register */ + #define REG_USART1_TTGR (*(__IO uint32_t*)0x40028028U) /**< \brief (USART1) Transmitter Timeguard Register */ + #define REG_USART1_MAN (*(__IO uint32_t*)0x40028050U) /**< \brief (USART1) Manchester Configuration Register */ + #define REG_USART1_LINMR (*(__IO uint32_t*)0x40028054U) /**< \brief (USART1) LIN Mode Register */ + #define REG_USART1_LINIR (*(__IO uint32_t*)0x40028058U) /**< \brief (USART1) LIN Identifier Register */ + #define REG_USART1_LINBRR (*(__I uint32_t*)0x4002805CU) /**< \brief (USART1) LIN Baud Rate Register */ + #define REG_USART1_LONMR (*(__IO uint32_t*)0x40028060U) /**< \brief (USART1) LON Mode Register */ + #define REG_USART1_LONPR (*(__IO uint32_t*)0x40028064U) /**< \brief (USART1) LON Preamble Register */ + #define REG_USART1_LONDL (*(__IO uint32_t*)0x40028068U) /**< \brief (USART1) LON Data Length Register */ + #define REG_USART1_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< \brief (USART1) LON L2HDR Register */ + #define REG_USART1_LONBL (*(__I uint32_t*)0x40028070U) /**< \brief (USART1) LON Backlog Register */ + #define REG_USART1_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< \brief (USART1) LON Beta1 Tx Register */ + #define REG_USART1_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< \brief (USART1) LON Beta1 Rx Register */ + #define REG_USART1_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< \brief (USART1) LON Priority Register */ + #define REG_USART1_IDTTX (*(__IO uint32_t*)0x40028080U) /**< \brief (USART1) LON IDT Tx Register */ + #define REG_USART1_IDTRX (*(__IO uint32_t*)0x40028084U) /**< \brief (USART1) LON IDT Rx Register */ + #define REG_USART1_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< \brief (USART1) IC DIFF Register */ + #define REG_USART1_WPMR (*(__IO uint32_t*)0x400280E4U) /**< \brief (USART1) Write Protection Mode Register */ + #define REG_USART1_WPSR (*(__I uint32_t*)0x400280E8U) /**< \brief (USART1) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USART1_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart2.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart2.h new file mode 100644 index 000000000..de26cafd3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usart2.h @@ -0,0 +1,94 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USART2_INSTANCE_ +#define _SAMV71_USART2_INSTANCE_ + +/* ========== Register definition for USART2 peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USART2_CR (0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_MAN (0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ +#else + #define REG_USART2_CR (*(__O uint32_t*)0x4002C000U) /**< \brief (USART2) Control Register */ + #define REG_USART2_MR (*(__IO uint32_t*)0x4002C004U) /**< \brief (USART2) Mode Register */ + #define REG_USART2_IER (*(__O uint32_t*)0x4002C008U) /**< \brief (USART2) Interrupt Enable Register */ + #define REG_USART2_IDR (*(__O uint32_t*)0x4002C00CU) /**< \brief (USART2) Interrupt Disable Register */ + #define REG_USART2_IMR (*(__I uint32_t*)0x4002C010U) /**< \brief (USART2) Interrupt Mask Register */ + #define REG_USART2_CSR (*(__I uint32_t*)0x4002C014U) /**< \brief (USART2) Channel Status Register */ + #define REG_USART2_RHR (*(__I uint32_t*)0x4002C018U) /**< \brief (USART2) Receive Holding Register */ + #define REG_USART2_THR (*(__O uint32_t*)0x4002C01CU) /**< \brief (USART2) Transmit Holding Register */ + #define REG_USART2_BRGR (*(__IO uint32_t*)0x4002C020U) /**< \brief (USART2) Baud Rate Generator Register */ + #define REG_USART2_RTOR (*(__IO uint32_t*)0x4002C024U) /**< \brief (USART2) Receiver Time-out Register */ + #define REG_USART2_TTGR (*(__IO uint32_t*)0x4002C028U) /**< \brief (USART2) Transmitter Timeguard Register */ + #define REG_USART2_MAN (*(__IO uint32_t*)0x4002C050U) /**< \brief (USART2) Manchester Configuration Register */ + #define REG_USART2_LINMR (*(__IO uint32_t*)0x4002C054U) /**< \brief (USART2) LIN Mode Register */ + #define REG_USART2_LINIR (*(__IO uint32_t*)0x4002C058U) /**< \brief (USART2) LIN Identifier Register */ + #define REG_USART2_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< \brief (USART2) LIN Baud Rate Register */ + #define REG_USART2_LONMR (*(__IO uint32_t*)0x4002C060U) /**< \brief (USART2) LON Mode Register */ + #define REG_USART2_LONPR (*(__IO uint32_t*)0x4002C064U) /**< \brief (USART2) LON Preamble Register */ + #define REG_USART2_LONDL (*(__IO uint32_t*)0x4002C068U) /**< \brief (USART2) LON Data Length Register */ + #define REG_USART2_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< \brief (USART2) LON L2HDR Register */ + #define REG_USART2_LONBL (*(__I uint32_t*)0x4002C070U) /**< \brief (USART2) LON Backlog Register */ + #define REG_USART2_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< \brief (USART2) LON Beta1 Tx Register */ + #define REG_USART2_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< \brief (USART2) LON Beta1 Rx Register */ + #define REG_USART2_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< \brief (USART2) LON Priority Register */ + #define REG_USART2_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< \brief (USART2) LON IDT Tx Register */ + #define REG_USART2_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< \brief (USART2) LON IDT Rx Register */ + #define REG_USART2_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< \brief (USART2) IC DIFF Register */ + #define REG_USART2_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< \brief (USART2) Write Protection Mode Register */ + #define REG_USART2_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< \brief (USART2) Write Protection Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USART2_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usbhs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usbhs.h new file mode 100644 index 000000000..1224c69e7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_usbhs.h @@ -0,0 +1,240 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_USBHS_INSTANCE_ +#define _SAMV71_USBHS_INSTANCE_ + +/* ========== Register definition for USBHS peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_USBHS_DEVCTRL (0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#else + #define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< \brief (USBHS) Device General Control Register */ + #define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< \brief (USBHS) Device Global Interrupt Status Register */ + #define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< \brief (USBHS) Device Global Interrupt Clear Register */ + #define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< \brief (USBHS) Device Global Interrupt Set Register */ + #define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< \brief (USBHS) Device Global Interrupt Mask Register */ + #define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< \brief (USBHS) Device Global Interrupt Disable Register */ + #define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< \brief (USBHS) Device Global Interrupt Enable Register */ + #define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< \brief (USBHS) Device Endpoint Register */ + #define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< \brief (USBHS) Device Frame Number Register */ + #define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< \brief (USBHS) Device Endpoint Configuration Register (n = 0) */ + #define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< \brief (USBHS) Device Endpoint Status Register (n = 0) */ + #define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< \brief (USBHS) Device Endpoint Clear Register (n = 0) */ + #define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< \brief (USBHS) Device Endpoint Set Register (n = 0) */ + #define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< \brief (USBHS) Device Endpoint Mask Register (n = 0) */ + #define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< \brief (USBHS) Device Endpoint Enable Register (n = 0) */ + #define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< \brief (USBHS) Device Endpoint Disable Register (n = 0) */ + #define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038310U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038314U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 1) */ + #define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038318U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 1) */ + #define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003831CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 1) */ + #define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038320U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038324U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 2) */ + #define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038328U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 2) */ + #define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003832CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 2) */ + #define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038330U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038334U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 3) */ + #define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038338U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 3) */ + #define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003833CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 3) */ + #define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038340U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038344U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 4) */ + #define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038348U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 4) */ + #define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003834CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 4) */ + #define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038350U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038354U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 5) */ + #define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038358U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 5) */ + #define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003835CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 5) */ + #define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038360U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038364U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 6) */ + #define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038368U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 6) */ + #define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003836CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 6) */ + #define REG_USBHS_DEVDMANXTDSC7 (*(__IO uint32_t*)0x40038370U) /**< \brief (USBHS) Device DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_DEVDMAADDRESS7 (*(__IO uint32_t*)0x40038374U) /**< \brief (USBHS) Device DMA Channel Address Register (n = 7) */ + #define REG_USBHS_DEVDMACONTROL7 (*(__IO uint32_t*)0x40038378U) /**< \brief (USBHS) Device DMA Channel Control Register (n = 7) */ + #define REG_USBHS_DEVDMASTATUS7 (*(__IO uint32_t*)0x4003837CU) /**< \brief (USBHS) Device DMA Channel Status Register (n = 7) */ + #define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< \brief (USBHS) Host General Control Register */ + #define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< \brief (USBHS) Host Global Interrupt Status Register */ + #define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< \brief (USBHS) Host Global Interrupt Clear Register */ + #define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< \brief (USBHS) Host Global Interrupt Set Register */ + #define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< \brief (USBHS) Host Global Interrupt Mask Register */ + #define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< \brief (USBHS) Host Global Interrupt Disable Register */ + #define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< \brief (USBHS) Host Global Interrupt Enable Register */ + #define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< \brief (USBHS) Host Pipe Register */ + #define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< \brief (USBHS) Host Frame Number Register */ + #define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< \brief (USBHS) Host Address 1 Register */ + #define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< \brief (USBHS) Host Address 2 Register */ + #define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< \brief (USBHS) Host Address 3 Register */ + #define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< \brief (USBHS) Host Pipe Configuration Register (n = 0) */ + #define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< \brief (USBHS) Host Pipe Status Register (n = 0) */ + #define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< \brief (USBHS) Host Pipe Clear Register (n = 0) */ + #define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< \brief (USBHS) Host Pipe Set Register (n = 0) */ + #define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< \brief (USBHS) Host Pipe Mask Register (n = 0) */ + #define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< \brief (USBHS) Host Pipe Enable Register (n = 0) */ + #define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< \brief (USBHS) Host Pipe Disable Register (n = 0) */ + #define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< \brief (USBHS) Host Pipe IN Request Register (n = 0) */ + #define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< \brief (USBHS) Host Pipe Error Register (n = 0) */ + #define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038710U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 1) */ + #define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038714U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 1) */ + #define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038718U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 1) */ + #define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003871CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 1) */ + #define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038720U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 2) */ + #define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038724U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 2) */ + #define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038728U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 2) */ + #define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003872CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 2) */ + #define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038730U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 3) */ + #define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038734U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 3) */ + #define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038738U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 3) */ + #define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003873CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 3) */ + #define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038740U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 4) */ + #define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038744U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 4) */ + #define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038748U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 4) */ + #define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003874CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 4) */ + #define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038750U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 5) */ + #define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038754U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 5) */ + #define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038758U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 5) */ + #define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003875CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 5) */ + #define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038760U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 6) */ + #define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038764U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 6) */ + #define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038768U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 6) */ + #define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003876CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 6) */ + #define REG_USBHS_HSTDMANXTDSC7 (*(__IO uint32_t*)0x40038770U) /**< \brief (USBHS) Host DMA Channel Next Descriptor Address Register (n = 7) */ + #define REG_USBHS_HSTDMAADDRESS7 (*(__IO uint32_t*)0x40038774U) /**< \brief (USBHS) Host DMA Channel Address Register (n = 7) */ + #define REG_USBHS_HSTDMACONTROL7 (*(__IO uint32_t*)0x40038778U) /**< \brief (USBHS) Host DMA Channel Control Register (n = 7) */ + #define REG_USBHS_HSTDMASTATUS7 (*(__IO uint32_t*)0x4003877CU) /**< \brief (USBHS) Host DMA Channel Status Register (n = 7) */ + #define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< \brief (USBHS) General Control Register */ + #define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< \brief (USBHS) General Status Register */ + #define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< \brief (USBHS) General Status Clear Register */ + #define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< \brief (USBHS) General Status Set Register */ + #define REG_USBHS_TSTA1 (*(__IO uint32_t*)0x40038810U) /**< \brief (USBHS) General Test A1 Register */ + #define REG_USBHS_TSTA2 (*(__IO uint32_t*)0x40038814U) /**< \brief (USBHS) General Test A2 Register */ + #define REG_USBHS_VERSION (*(__I uint32_t*)0x40038818U) /**< \brief (USBHS) General Version Register */ + #define REG_USBHS_FSM (*(__I uint32_t*)0x4003882CU) /**< \brief (USBHS) General Finite State Machine Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_USBHS_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_utmi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_utmi.h new file mode 100644 index 000000000..9393eb389 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_utmi.h @@ -0,0 +1,42 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_UTMI_INSTANCE_ +#define _SAMV71_UTMI_INSTANCE_ + +/* ========== Register definition for UTMI peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_UTMI_OHCIICR (0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#else + #define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< \brief (UTMI) OHCI Interrupt Configuration Register */ + #define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< \brief (UTMI) UTMI Clock Trimming Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_UTMI_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_wdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_wdt.h new file mode 100644 index 000000000..dbff034ed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_wdt.h @@ -0,0 +1,44 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_WDT_INSTANCE_ +#define _SAMV71_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */ +#else + #define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< \brief (WDT) Control Register */ + #define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< \brief (WDT) Mode Register */ + #define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< \brief (WDT) Status Register */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_WDT_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_xdmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_xdmac.h new file mode 100644 index 000000000..8c94039ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/instance/instance_xdmac.h @@ -0,0 +1,744 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_XDMAC_INSTANCE_ +#define _SAMV71_XDMAC_INSTANCE_ + +/* ========== Register definition for XDMAC peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + #define REG_XDMAC_GTYPE (0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ +#else + #define REG_XDMAC_GTYPE (*(__IO uint32_t*)0x40078000U) /**< \brief (XDMAC) Global Type Register */ + #define REG_XDMAC_GCFG (*(__I uint32_t*)0x40078004U) /**< \brief (XDMAC) Global Configuration Register */ + #define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< \brief (XDMAC) Global Weighted Arbiter Configuration Register */ + #define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< \brief (XDMAC) Global Interrupt Enable Register */ + #define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< \brief (XDMAC) Global Interrupt Disable Register */ + #define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< \brief (XDMAC) Global Interrupt Mask Register */ + #define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< \brief (XDMAC) Global Interrupt Status Register */ + #define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< \brief (XDMAC) Global Channel Enable Register */ + #define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< \brief (XDMAC) Global Channel Disable Register */ + #define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< \brief (XDMAC) Global Channel Status Register */ + #define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< \brief (XDMAC) Global Channel Read Suspend Register */ + #define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< \brief (XDMAC) Global Channel Write Suspend Register */ + #define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< \brief (XDMAC) Global Channel Read Write Suspend Register */ + #define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< \brief (XDMAC) Global Channel Read Write Resume Register */ + #define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< \brief (XDMAC) Global Channel Software Request Register */ + #define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< \brief (XDMAC) Global Channel Software Request Status Register */ + #define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< \brief (XDMAC) Global Channel Software Flush Request Register */ + #define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 0) */ + #define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 0) */ + #define REG_XDMAC_CIM0 (*(__O uint32_t*)0x40078058U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 0) */ + #define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 0) */ + #define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< \brief (XDMAC) Channel Source Address Register (chid = 0) */ + #define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 0) */ + #define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 0) */ + #define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 0) */ + #define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 0) */ + #define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< \brief (XDMAC) Channel Block Control Register (chid = 0) */ + #define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< \brief (XDMAC) Channel Configuration Register (chid = 0) */ + #define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 0) */ + #define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 0) */ + #define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 0) */ + #define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 1) */ + #define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 1) */ + #define REG_XDMAC_CIM1 (*(__O uint32_t*)0x40078098U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 1) */ + #define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 1) */ + #define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 1) */ + #define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 1) */ + #define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 1) */ + #define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 1) */ + #define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 1) */ + #define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 1) */ + #define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 1) */ + #define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 1) */ + #define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 1) */ + #define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 1) */ + #define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 2) */ + #define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 2) */ + #define REG_XDMAC_CIM2 (*(__O uint32_t*)0x400780D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 2) */ + #define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 2) */ + #define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 2) */ + #define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 2) */ + #define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 2) */ + #define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 2) */ + #define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 2) */ + #define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 2) */ + #define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 2) */ + #define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 2) */ + #define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 2) */ + #define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 2) */ + #define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 3) */ + #define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 3) */ + #define REG_XDMAC_CIM3 (*(__O uint32_t*)0x40078118U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 3) */ + #define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 3) */ + #define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< \brief (XDMAC) Channel Source Address Register (chid = 3) */ + #define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 3) */ + #define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 3) */ + #define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 3) */ + #define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 3) */ + #define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< \brief (XDMAC) Channel Block Control Register (chid = 3) */ + #define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< \brief (XDMAC) Channel Configuration Register (chid = 3) */ + #define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 3) */ + #define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 3) */ + #define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 3) */ + #define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 4) */ + #define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 4) */ + #define REG_XDMAC_CIM4 (*(__O uint32_t*)0x40078158U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 4) */ + #define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 4) */ + #define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< \brief (XDMAC) Channel Source Address Register (chid = 4) */ + #define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 4) */ + #define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 4) */ + #define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 4) */ + #define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 4) */ + #define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< \brief (XDMAC) Channel Block Control Register (chid = 4) */ + #define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< \brief (XDMAC) Channel Configuration Register (chid = 4) */ + #define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 4) */ + #define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 4) */ + #define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 4) */ + #define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 5) */ + #define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 5) */ + #define REG_XDMAC_CIM5 (*(__O uint32_t*)0x40078198U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 5) */ + #define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 5) */ + #define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 5) */ + #define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 5) */ + #define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 5) */ + #define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 5) */ + #define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 5) */ + #define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 5) */ + #define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 5) */ + #define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 5) */ + #define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 5) */ + #define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 5) */ + #define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 6) */ + #define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 6) */ + #define REG_XDMAC_CIM6 (*(__O uint32_t*)0x400781D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 6) */ + #define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 6) */ + #define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 6) */ + #define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 6) */ + #define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 6) */ + #define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 6) */ + #define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 6) */ + #define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 6) */ + #define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 6) */ + #define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 6) */ + #define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 6) */ + #define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 6) */ + #define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 7) */ + #define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 7) */ + #define REG_XDMAC_CIM7 (*(__O uint32_t*)0x40078218U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 7) */ + #define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 7) */ + #define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< \brief (XDMAC) Channel Source Address Register (chid = 7) */ + #define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 7) */ + #define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 7) */ + #define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 7) */ + #define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 7) */ + #define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< \brief (XDMAC) Channel Block Control Register (chid = 7) */ + #define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< \brief (XDMAC) Channel Configuration Register (chid = 7) */ + #define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 7) */ + #define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 7) */ + #define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 7) */ + #define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 8) */ + #define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 8) */ + #define REG_XDMAC_CIM8 (*(__O uint32_t*)0x40078258U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 8) */ + #define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 8) */ + #define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< \brief (XDMAC) Channel Source Address Register (chid = 8) */ + #define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 8) */ + #define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 8) */ + #define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 8) */ + #define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 8) */ + #define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< \brief (XDMAC) Channel Block Control Register (chid = 8) */ + #define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< \brief (XDMAC) Channel Configuration Register (chid = 8) */ + #define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 8) */ + #define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 8) */ + #define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 8) */ + #define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 9) */ + #define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 9) */ + #define REG_XDMAC_CIM9 (*(__O uint32_t*)0x40078298U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 9) */ + #define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 9) */ + #define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 9) */ + #define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 9) */ + #define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 9) */ + #define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 9) */ + #define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 9) */ + #define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 9) */ + #define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 9) */ + #define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 9) */ + #define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 9) */ + #define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 9) */ + #define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 10) */ + #define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 10) */ + #define REG_XDMAC_CIM10 (*(__O uint32_t*)0x400782D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 10) */ + #define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 10) */ + #define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 10) */ + #define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 10) */ + #define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 10) */ + #define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 10) */ + #define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 10) */ + #define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 10) */ + #define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 10) */ + #define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 10) */ + #define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 10) */ + #define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 10) */ + #define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 11) */ + #define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 11) */ + #define REG_XDMAC_CIM11 (*(__O uint32_t*)0x40078318U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 11) */ + #define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 11) */ + #define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< \brief (XDMAC) Channel Source Address Register (chid = 11) */ + #define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 11) */ + #define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 11) */ + #define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 11) */ + #define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 11) */ + #define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< \brief (XDMAC) Channel Block Control Register (chid = 11) */ + #define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< \brief (XDMAC) Channel Configuration Register (chid = 11) */ + #define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 11) */ + #define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 11) */ + #define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 11) */ + #define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 12) */ + #define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 12) */ + #define REG_XDMAC_CIM12 (*(__O uint32_t*)0x40078358U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 12) */ + #define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 12) */ + #define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< \brief (XDMAC) Channel Source Address Register (chid = 12) */ + #define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 12) */ + #define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 12) */ + #define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 12) */ + #define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 12) */ + #define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< \brief (XDMAC) Channel Block Control Register (chid = 12) */ + #define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< \brief (XDMAC) Channel Configuration Register (chid = 12) */ + #define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 12) */ + #define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 12) */ + #define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 12) */ + #define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 13) */ + #define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 13) */ + #define REG_XDMAC_CIM13 (*(__O uint32_t*)0x40078398U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 13) */ + #define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 13) */ + #define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 13) */ + #define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 13) */ + #define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 13) */ + #define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 13) */ + #define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 13) */ + #define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 13) */ + #define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 13) */ + #define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 13) */ + #define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 13) */ + #define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 13) */ + #define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 14) */ + #define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 14) */ + #define REG_XDMAC_CIM14 (*(__O uint32_t*)0x400783D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 14) */ + #define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 14) */ + #define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 14) */ + #define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 14) */ + #define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 14) */ + #define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 14) */ + #define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 14) */ + #define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 14) */ + #define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 14) */ + #define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 14) */ + #define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 14) */ + #define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 14) */ + #define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 15) */ + #define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 15) */ + #define REG_XDMAC_CIM15 (*(__O uint32_t*)0x40078418U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 15) */ + #define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 15) */ + #define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< \brief (XDMAC) Channel Source Address Register (chid = 15) */ + #define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 15) */ + #define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 15) */ + #define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 15) */ + #define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 15) */ + #define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< \brief (XDMAC) Channel Block Control Register (chid = 15) */ + #define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< \brief (XDMAC) Channel Configuration Register (chid = 15) */ + #define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 15) */ + #define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 15) */ + #define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 15) */ + #define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 16) */ + #define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 16) */ + #define REG_XDMAC_CIM16 (*(__O uint32_t*)0x40078458U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 16) */ + #define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 16) */ + #define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< \brief (XDMAC) Channel Source Address Register (chid = 16) */ + #define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 16) */ + #define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 16) */ + #define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 16) */ + #define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 16) */ + #define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< \brief (XDMAC) Channel Block Control Register (chid = 16) */ + #define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< \brief (XDMAC) Channel Configuration Register (chid = 16) */ + #define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 16) */ + #define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 16) */ + #define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 16) */ + #define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 17) */ + #define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 17) */ + #define REG_XDMAC_CIM17 (*(__O uint32_t*)0x40078498U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 17) */ + #define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 17) */ + #define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 17) */ + #define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 17) */ + #define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 17) */ + #define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 17) */ + #define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 17) */ + #define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 17) */ + #define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 17) */ + #define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 17) */ + #define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 17) */ + #define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 17) */ + #define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 18) */ + #define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 18) */ + #define REG_XDMAC_CIM18 (*(__O uint32_t*)0x400784D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 18) */ + #define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 18) */ + #define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 18) */ + #define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 18) */ + #define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 18) */ + #define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 18) */ + #define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 18) */ + #define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 18) */ + #define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 18) */ + #define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 18) */ + #define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 18) */ + #define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 18) */ + #define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 19) */ + #define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 19) */ + #define REG_XDMAC_CIM19 (*(__O uint32_t*)0x40078518U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 19) */ + #define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 19) */ + #define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< \brief (XDMAC) Channel Source Address Register (chid = 19) */ + #define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 19) */ + #define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 19) */ + #define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 19) */ + #define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 19) */ + #define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< \brief (XDMAC) Channel Block Control Register (chid = 19) */ + #define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< \brief (XDMAC) Channel Configuration Register (chid = 19) */ + #define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 19) */ + #define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 19) */ + #define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 19) */ + #define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 20) */ + #define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 20) */ + #define REG_XDMAC_CIM20 (*(__O uint32_t*)0x40078558U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 20) */ + #define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 20) */ + #define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< \brief (XDMAC) Channel Source Address Register (chid = 20) */ + #define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 20) */ + #define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 20) */ + #define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 20) */ + #define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 20) */ + #define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< \brief (XDMAC) Channel Block Control Register (chid = 20) */ + #define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< \brief (XDMAC) Channel Configuration Register (chid = 20) */ + #define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 20) */ + #define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 20) */ + #define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 20) */ + #define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 21) */ + #define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 21) */ + #define REG_XDMAC_CIM21 (*(__O uint32_t*)0x40078598U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 21) */ + #define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 21) */ + #define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 21) */ + #define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 21) */ + #define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 21) */ + #define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 21) */ + #define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 21) */ + #define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 21) */ + #define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 21) */ + #define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 21) */ + #define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 21) */ + #define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 21) */ + #define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 22) */ + #define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 22) */ + #define REG_XDMAC_CIM22 (*(__O uint32_t*)0x400785D8U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 22) */ + #define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 22) */ + #define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< \brief (XDMAC) Channel Source Address Register (chid = 22) */ + #define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 22) */ + #define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 22) */ + #define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 22) */ + #define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 22) */ + #define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< \brief (XDMAC) Channel Block Control Register (chid = 22) */ + #define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< \brief (XDMAC) Channel Configuration Register (chid = 22) */ + #define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 22) */ + #define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 22) */ + #define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 22) */ + #define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< \brief (XDMAC) Channel Interrupt Enable Register (chid = 23) */ + #define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< \brief (XDMAC) Channel Interrupt Disable Register (chid = 23) */ + #define REG_XDMAC_CIM23 (*(__O uint32_t*)0x40078618U) /**< \brief (XDMAC) Channel Interrupt Mask Register (chid = 23) */ + #define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< \brief (XDMAC) Channel Interrupt Status Register (chid = 23) */ + #define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< \brief (XDMAC) Channel Source Address Register (chid = 23) */ + #define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< \brief (XDMAC) Channel Destination Address Register (chid = 23) */ + #define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< \brief (XDMAC) Channel Next Descriptor Address Register (chid = 23) */ + #define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< \brief (XDMAC) Channel Next Descriptor Control Register (chid = 23) */ + #define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< \brief (XDMAC) Channel Microblock Control Register (chid = 23) */ + #define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< \brief (XDMAC) Channel Block Control Register (chid = 23) */ + #define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< \brief (XDMAC) Channel Configuration Register (chid = 23) */ + #define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< \brief (XDMAC) Channel Data Stride Memory Set Pattern (chid = 23) */ + #define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< \brief (XDMAC) Channel Source Microblock Stride (chid = 23) */ + #define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< \brief (XDMAC) Channel Destination Microblock Stride (chid = 23) */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _SAMV71_XDMAC_INSTANCE_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j19.h new file mode 100644 index 000000000..618875508 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j19.h @@ -0,0 +1,438 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_PIO_ +#define _SAMV71J19_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J19_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j20.h new file mode 100644 index 000000000..85a0f5701 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j20.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_PIO_ +#define _SAMV71J20_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J20_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j21.h new file mode 100644 index 000000000..29d857f9a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71j21.h @@ -0,0 +1,442 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_PIO_ +#define _SAMV71J21_PIO_ + +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA24_IDX 24 +#define PIO_PA27_IDX 27 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71J21_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n19.h new file mode 100644 index 000000000..1be3ae3ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n19.h @@ -0,0 +1,499 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_PIO_ +#define _SAMV71N19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N19_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n20.h new file mode 100644 index 000000000..cbb174ba2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n20.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_PIO_ +#define _SAMV71N20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N20_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n21.h new file mode 100644 index 000000000..db03f1b07 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71n21.h @@ -0,0 +1,495 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_PIO_ +#define _SAMV71N21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 + +#endif /* _SAMV71N21_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q19.h new file mode 100644 index 000000000..dd66d451e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q19.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_PIO_ +#define _SAMV71Q19_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== PIO definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== PIO definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== PIO definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== PIO definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== PIO definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== PIO definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== PIO definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== PIO definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== PIO definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== PIO definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== PIO definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== PIO definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== PIO definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== PIO definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== PIO definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== PIO definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== PIO definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== PIO definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== PIO definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== PIO definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== PIO definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== PIO definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== PIO definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== PIO definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== PIO definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== PIO definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== PIO definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== PIO definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== PIO definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== PIO definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== PIO definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== PIO definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== PIO definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== PIO definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== PIO indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q19_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q20.h new file mode 100644 index 000000000..4d6b340f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q20.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_PIO_ +#define _SAMV71Q20_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q20_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q21.h new file mode 100644 index 000000000..da4e46d32 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/pio/pio_samv71q21.h @@ -0,0 +1,672 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_PIO_ +#define _SAMV71Q21_PIO_ + +#define PIO_PA0 (1u << 0) /**< \brief Pin Controlled by PA0 */ +#define PIO_PA1 (1u << 1) /**< \brief Pin Controlled by PA1 */ +#define PIO_PA2 (1u << 2) /**< \brief Pin Controlled by PA2 */ +#define PIO_PA3 (1u << 3) /**< \brief Pin Controlled by PA3 */ +#define PIO_PA4 (1u << 4) /**< \brief Pin Controlled by PA4 */ +#define PIO_PA5 (1u << 5) /**< \brief Pin Controlled by PA5 */ +#define PIO_PA6 (1u << 6) /**< \brief Pin Controlled by PA6 */ +#define PIO_PA7 (1u << 7) /**< \brief Pin Controlled by PA7 */ +#define PIO_PA8 (1u << 8) /**< \brief Pin Controlled by PA8 */ +#define PIO_PA9 (1u << 9) /**< \brief Pin Controlled by PA9 */ +#define PIO_PA10 (1u << 10) /**< \brief Pin Controlled by PA10 */ +#define PIO_PA11 (1u << 11) /**< \brief Pin Controlled by PA11 */ +#define PIO_PA12 (1u << 12) /**< \brief Pin Controlled by PA12 */ +#define PIO_PA13 (1u << 13) /**< \brief Pin Controlled by PA13 */ +#define PIO_PA14 (1u << 14) /**< \brief Pin Controlled by PA14 */ +#define PIO_PA15 (1u << 15) /**< \brief Pin Controlled by PA15 */ +#define PIO_PA16 (1u << 16) /**< \brief Pin Controlled by PA16 */ +#define PIO_PA17 (1u << 17) /**< \brief Pin Controlled by PA17 */ +#define PIO_PA18 (1u << 18) /**< \brief Pin Controlled by PA18 */ +#define PIO_PA19 (1u << 19) /**< \brief Pin Controlled by PA19 */ +#define PIO_PA20 (1u << 20) /**< \brief Pin Controlled by PA20 */ +#define PIO_PA21 (1u << 21) /**< \brief Pin Controlled by PA21 */ +#define PIO_PA22 (1u << 22) /**< \brief Pin Controlled by PA22 */ +#define PIO_PA23 (1u << 23) /**< \brief Pin Controlled by PA23 */ +#define PIO_PA24 (1u << 24) /**< \brief Pin Controlled by PA24 */ +#define PIO_PA25 (1u << 25) /**< \brief Pin Controlled by PA25 */ +#define PIO_PA26 (1u << 26) /**< \brief Pin Controlled by PA26 */ +#define PIO_PA27 (1u << 27) /**< \brief Pin Controlled by PA27 */ +#define PIO_PA28 (1u << 28) /**< \brief Pin Controlled by PA28 */ +#define PIO_PA29 (1u << 29) /**< \brief Pin Controlled by PA29 */ +#define PIO_PA30 (1u << 30) /**< \brief Pin Controlled by PA30 */ +#define PIO_PA31 (1u << 31) /**< \brief Pin Controlled by PA31 */ +#define PIO_PB0 (1u << 0) /**< \brief Pin Controlled by PB0 */ +#define PIO_PB1 (1u << 1) /**< \brief Pin Controlled by PB1 */ +#define PIO_PB2 (1u << 2) /**< \brief Pin Controlled by PB2 */ +#define PIO_PB3 (1u << 3) /**< \brief Pin Controlled by PB3 */ +#define PIO_PB4 (1u << 4) /**< \brief Pin Controlled by PB4 */ +#define PIO_PB5 (1u << 5) /**< \brief Pin Controlled by PB5 */ +#define PIO_PB6 (1u << 6) /**< \brief Pin Controlled by PB6 */ +#define PIO_PB7 (1u << 7) /**< \brief Pin Controlled by PB7 */ +#define PIO_PB8 (1u << 8) /**< \brief Pin Controlled by PB8 */ +#define PIO_PB9 (1u << 9) /**< \brief Pin Controlled by PB9 */ +#define PIO_PB12 (1u << 12) /**< \brief Pin Controlled by PB12 */ +#define PIO_PB13 (1u << 13) /**< \brief Pin Controlled by PB13 */ +#define PIO_PC0 (1u << 0) /**< \brief Pin Controlled by PC0 */ +#define PIO_PC1 (1u << 1) /**< \brief Pin Controlled by PC1 */ +#define PIO_PC2 (1u << 2) /**< \brief Pin Controlled by PC2 */ +#define PIO_PC3 (1u << 3) /**< \brief Pin Controlled by PC3 */ +#define PIO_PC4 (1u << 4) /**< \brief Pin Controlled by PC4 */ +#define PIO_PC5 (1u << 5) /**< \brief Pin Controlled by PC5 */ +#define PIO_PC6 (1u << 6) /**< \brief Pin Controlled by PC6 */ +#define PIO_PC7 (1u << 7) /**< \brief Pin Controlled by PC7 */ +#define PIO_PC8 (1u << 8) /**< \brief Pin Controlled by PC8 */ +#define PIO_PC9 (1u << 9) /**< \brief Pin Controlled by PC9 */ +#define PIO_PC10 (1u << 10) /**< \brief Pin Controlled by PC10 */ +#define PIO_PC11 (1u << 11) /**< \brief Pin Controlled by PC11 */ +#define PIO_PC12 (1u << 12) /**< \brief Pin Controlled by PC12 */ +#define PIO_PC13 (1u << 13) /**< \brief Pin Controlled by PC13 */ +#define PIO_PC14 (1u << 14) /**< \brief Pin Controlled by PC14 */ +#define PIO_PC15 (1u << 15) /**< \brief Pin Controlled by PC15 */ +#define PIO_PC16 (1u << 16) /**< \brief Pin Controlled by PC16 */ +#define PIO_PC17 (1u << 17) /**< \brief Pin Controlled by PC17 */ +#define PIO_PC18 (1u << 18) /**< \brief Pin Controlled by PC18 */ +#define PIO_PC19 (1u << 19) /**< \brief Pin Controlled by PC19 */ +#define PIO_PC20 (1u << 20) /**< \brief Pin Controlled by PC20 */ +#define PIO_PC21 (1u << 21) /**< \brief Pin Controlled by PC21 */ +#define PIO_PC22 (1u << 22) /**< \brief Pin Controlled by PC22 */ +#define PIO_PC23 (1u << 23) /**< \brief Pin Controlled by PC23 */ +#define PIO_PC24 (1u << 24) /**< \brief Pin Controlled by PC24 */ +#define PIO_PC25 (1u << 25) /**< \brief Pin Controlled by PC25 */ +#define PIO_PC26 (1u << 26) /**< \brief Pin Controlled by PC26 */ +#define PIO_PC27 (1u << 27) /**< \brief Pin Controlled by PC27 */ +#define PIO_PC28 (1u << 28) /**< \brief Pin Controlled by PC28 */ +#define PIO_PC29 (1u << 29) /**< \brief Pin Controlled by PC29 */ +#define PIO_PC30 (1u << 30) /**< \brief Pin Controlled by PC30 */ +#define PIO_PC31 (1u << 31) /**< \brief Pin Controlled by PC31 */ +#define PIO_PD0 (1u << 0) /**< \brief Pin Controlled by PD0 */ +#define PIO_PD1 (1u << 1) /**< \brief Pin Controlled by PD1 */ +#define PIO_PD2 (1u << 2) /**< \brief Pin Controlled by PD2 */ +#define PIO_PD3 (1u << 3) /**< \brief Pin Controlled by PD3 */ +#define PIO_PD4 (1u << 4) /**< \brief Pin Controlled by PD4 */ +#define PIO_PD5 (1u << 5) /**< \brief Pin Controlled by PD5 */ +#define PIO_PD6 (1u << 6) /**< \brief Pin Controlled by PD6 */ +#define PIO_PD7 (1u << 7) /**< \brief Pin Controlled by PD7 */ +#define PIO_PD8 (1u << 8) /**< \brief Pin Controlled by PD8 */ +#define PIO_PD9 (1u << 9) /**< \brief Pin Controlled by PD9 */ +#define PIO_PD10 (1u << 10) /**< \brief Pin Controlled by PD10 */ +#define PIO_PD11 (1u << 11) /**< \brief Pin Controlled by PD11 */ +#define PIO_PD12 (1u << 12) /**< \brief Pin Controlled by PD12 */ +#define PIO_PD13 (1u << 13) /**< \brief Pin Controlled by PD13 */ +#define PIO_PD14 (1u << 14) /**< \brief Pin Controlled by PD14 */ +#define PIO_PD15 (1u << 15) /**< \brief Pin Controlled by PD15 */ +#define PIO_PD16 (1u << 16) /**< \brief Pin Controlled by PD16 */ +#define PIO_PD17 (1u << 17) /**< \brief Pin Controlled by PD17 */ +#define PIO_PD18 (1u << 18) /**< \brief Pin Controlled by PD18 */ +#define PIO_PD19 (1u << 19) /**< \brief Pin Controlled by PD19 */ +#define PIO_PD20 (1u << 20) /**< \brief Pin Controlled by PD20 */ +#define PIO_PD21 (1u << 21) /**< \brief Pin Controlled by PD21 */ +#define PIO_PD22 (1u << 22) /**< \brief Pin Controlled by PD22 */ +#define PIO_PD23 (1u << 23) /**< \brief Pin Controlled by PD23 */ +#define PIO_PD24 (1u << 24) /**< \brief Pin Controlled by PD24 */ +#define PIO_PD25 (1u << 25) /**< \brief Pin Controlled by PD25 */ +#define PIO_PD26 (1u << 26) /**< \brief Pin Controlled by PD26 */ +#define PIO_PD27 (1u << 27) /**< \brief Pin Controlled by PD27 */ +#define PIO_PD28 (1u << 28) /**< \brief Pin Controlled by PD28 */ +#define PIO_PD29 (1u << 29) /**< \brief Pin Controlled by PD29 */ +#define PIO_PD30 (1u << 30) /**< \brief Pin Controlled by PD30 */ +#define PIO_PD31 (1u << 31) /**< \brief Pin Controlled by PD31 */ +#define PIO_PE0 (1u << 0) /**< \brief Pin Controlled by PE0 */ +#define PIO_PE1 (1u << 1) /**< \brief Pin Controlled by PE1 */ +#define PIO_PE2 (1u << 2) /**< \brief Pin Controlled by PE2 */ +#define PIO_PE3 (1u << 3) /**< \brief Pin Controlled by PE3 */ +#define PIO_PE4 (1u << 4) /**< \brief Pin Controlled by PE4 */ +#define PIO_PE5 (1u << 5) /**< \brief Pin Controlled by PE5 */ +/* ========== Pio definition for AFEC0 peripheral ========== */ +#define PIO_PD30X1_AFE0_AD0 (1u << 30) /**< \brief Afec0 signal: AFE0_AD0 */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Afec0 signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PB0X1_AFE0_AD10 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB0X1_RTCOUT0 (1u << 0) /**< \brief Afec0 signal: AFE0_AD10/RTCOUT0 */ +#define PIO_PB3X1_AFE0_AD2 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PB3X1_WKUP12 (1u << 3) /**< \brief Afec0 signal: AFE0_AD2/WKUP12 */ +#define PIO_PE5X1_AFE0_AD3 (1u << 5) /**< \brief Afec0 signal: AFE0_AD3 */ +#define PIO_PE4X1_AFE0_AD4 (1u << 4) /**< \brief Afec0 signal: AFE0_AD4 */ +#define PIO_PB2X1_AFE0_AD5 (1u << 2) /**< \brief Afec0 signal: AFE0_AD5 */ +#define PIO_PA17X1_AFE0_AD6 (1u << 17) /**< \brief Afec0 signal: AFE0_AD6 */ +#define PIO_PA18X1_AFE0_AD7 (1u << 18) /**< \brief Afec0 signal: AFE0_AD7 */ +#define PIO_PA19X1_AFE0_AD8 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA19X1_WKUP9 (1u << 19) /**< \brief Afec0 signal: AFE0_AD8/WKUP9 */ +#define PIO_PA20X1_AFE0_AD9 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA20X1_WKUP10 (1u << 20) /**< \brief Afec0 signal: AFE0_AD9/WKUP10 */ +#define PIO_PA8B_AFE0_ADTRG (1u << 8) /**< \brief Afec0 signal: AFE0_ADTRG */ +/* ========== Pio definition for AFEC1 peripheral ========== */ +#define PIO_PB1X1_AFE1_AD0 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PB1X1_RTCOUT1 (1u << 1) /**< \brief Afec1 signal: AFE1_AD0/RTCOUT1 */ +#define PIO_PC13X1_AFE1_AD1 (1u << 13) /**< \brief Afec1 signal: AFE1_AD1 */ +#define PIO_PE3X1_AFE1_AD10 (1u << 3) /**< \brief Afec1 signal: AFE1_AD10 */ +#define PIO_PE0X1_AFE1_AD11 (1u << 0) /**< \brief Afec1 signal: AFE1_AD11 */ +#define PIO_PC15X1_AFE1_AD2 (1u << 15) /**< \brief Afec1 signal: AFE1_AD2 */ +#define PIO_PC12X1_AFE1_AD3 (1u << 12) /**< \brief Afec1 signal: AFE1_AD3 */ +#define PIO_PC29X1_AFE1_AD4 (1u << 29) /**< \brief Afec1 signal: AFE1_AD4 */ +#define PIO_PC30X1_AFE1_AD5 (1u << 30) /**< \brief Afec1 signal: AFE1_AD5 */ +#define PIO_PC31X1_AFE1_AD6 (1u << 31) /**< \brief Afec1 signal: AFE1_AD6 */ +#define PIO_PC26X1_AFE1_AD7 (1u << 26) /**< \brief Afec1 signal: AFE1_AD7 */ +#define PIO_PC27X1_AFE1_AD8 (1u << 27) /**< \brief Afec1 signal: AFE1_AD8 */ +#define PIO_PC0X1_AFE1_AD9 (1u << 0) /**< \brief Afec1 signal: AFE1_AD9 */ +#define PIO_PD9C_AFE1_ADTRG (1u << 9) /**< \brief Afec1 signal: AFE1_ADTRG */ +/* ========== Pio definition for ARM peripheral ========== */ +#define PIO_PB7X1_SWCLK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB7X1_TCK (1u << 7) /**< \brief Arm signal: SWCLK/TCK */ +#define PIO_PB6X1_SWDIO (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB6X1_TMS (1u << 6) /**< \brief Arm signal: SWDIO/TMS */ +#define PIO_PB4X1_TDI (1u << 4) /**< \brief Arm signal: TDI */ +#define PIO_PB5X1_TDO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_TRACESWO (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +#define PIO_PB5X1_WKUP13 (1u << 5) /**< \brief Arm signal: TDO/TRACESWO/WKUP13 */ +/* ========== Pio definition for DACC peripheral ========== */ +#define PIO_PB13X1_DAC0 (1u << 13) /**< \brief Dacc signal: DAC0 */ +#define PIO_PD0X1_DAC1 (1u << 0) /**< \brief Dacc signal: DAC1 */ +#define PIO_PA2C_DATRG (1u << 2) /**< \brief Dacc signal: DATRG */ +/* ========== Pio definition for EBI peripheral ========== */ +#define PIO_PC18A_A0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC18A_NBS0 (1u << 18) /**< \brief Ebi signal: A0/NBS0 */ +#define PIO_PC19A_A1 (1u << 19) /**< \brief Ebi signal: A1 */ +#define PIO_PC28A_A10 (1u << 28) /**< \brief Ebi signal: A10 */ +#define PIO_PC29A_A11 (1u << 29) /**< \brief Ebi signal: A11 */ +#define PIO_PC30A_A12 (1u << 30) /**< \brief Ebi signal: A12 */ +#define PIO_PC31A_A13 (1u << 31) /**< \brief Ebi signal: A13 */ +#define PIO_PA18C_A14 (1u << 18) /**< \brief Ebi signal: A14 */ +#define PIO_PA19C_A15 (1u << 19) /**< \brief Ebi signal: A15 */ +#define PIO_PA20C_A16 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA20C_BA0 (1u << 20) /**< \brief Ebi signal: A16/BA0 */ +#define PIO_PA0C_A17 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA0C_BA1 (1u << 0) /**< \brief Ebi signal: A17/BA1 */ +#define PIO_PA1C_A18 (1u << 1) /**< \brief Ebi signal: A18 */ +#define PIO_PA23C_A19 (1u << 23) /**< \brief Ebi signal: A19 */ +#define PIO_PC20A_A2 (1u << 20) /**< \brief Ebi signal: A2 */ +#define PIO_PA24C_A20 (1u << 24) /**< \brief Ebi signal: A20 */ +#define PIO_PC16A_A21 (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC16A_NANDALE (1u << 16) /**< \brief Ebi signal: A21/NANDALE */ +#define PIO_PC17A_A22 (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PC17A_NANDCLE (1u << 17) /**< \brief Ebi signal: A22/NANDCLE */ +#define PIO_PA25C_A23 (1u << 25) /**< \brief Ebi signal: A23 */ +#define PIO_PC21A_A3 (1u << 21) /**< \brief Ebi signal: A3 */ +#define PIO_PC22A_A4 (1u << 22) /**< \brief Ebi signal: A4 */ +#define PIO_PC23A_A5 (1u << 23) /**< \brief Ebi signal: A5 */ +#define PIO_PC24A_A6 (1u << 24) /**< \brief Ebi signal: A6 */ +#define PIO_PC25A_A7 (1u << 25) /**< \brief Ebi signal: A7 */ +#define PIO_PC26A_A8 (1u << 26) /**< \brief Ebi signal: A8 */ +#define PIO_PC27A_A9 (1u << 27) /**< \brief Ebi signal: A9 */ +#define PIO_PD17C_CAS (1u << 17) /**< \brief Ebi signal: CAS */ +#define PIO_PC0A_D0 (1u << 0) /**< \brief Ebi signal: D0 */ +#define PIO_PC1A_D1 (1u << 1) /**< \brief Ebi signal: D1 */ +#define PIO_PE2A_D10 (1u << 2) /**< \brief Ebi signal: D10 */ +#define PIO_PE3A_D11 (1u << 3) /**< \brief Ebi signal: D11 */ +#define PIO_PE4A_D12 (1u << 4) /**< \brief Ebi signal: D12 */ +#define PIO_PE5A_D13 (1u << 5) /**< \brief Ebi signal: D13 */ +#define PIO_PA15A_D14 (1u << 15) /**< \brief Ebi signal: D14 */ +#define PIO_PA16A_D15 (1u << 16) /**< \brief Ebi signal: D15 */ +#define PIO_PC2A_D2 (1u << 2) /**< \brief Ebi signal: D2 */ +#define PIO_PC3A_D3 (1u << 3) /**< \brief Ebi signal: D3 */ +#define PIO_PC4A_D4 (1u << 4) /**< \brief Ebi signal: D4 */ +#define PIO_PC5A_D5 (1u << 5) /**< \brief Ebi signal: D5 */ +#define PIO_PC6A_D6 (1u << 6) /**< \brief Ebi signal: D6 */ +#define PIO_PC7A_D7 (1u << 7) /**< \brief Ebi signal: D7 */ +#define PIO_PE0A_D8 (1u << 0) /**< \brief Ebi signal: D8 */ +#define PIO_PE1A_D9 (1u << 1) /**< \brief Ebi signal: D9 */ +#define PIO_PC9A_NANDOE (1u << 9) /**< \brief Ebi signal: NANDOE */ +#define PIO_PC10A_NANDWE (1u << 10) /**< \brief Ebi signal: NANDWE */ +#define PIO_PC14A_NCS0 (1u << 14) /**< \brief Ebi signal: NCS0 */ +#define PIO_PC15A_NCS1 (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PC15A_SDCS (1u << 15) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_NCS1 (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PD18A_SDCS (1u << 18) /**< \brief Ebi signal: NCS1/SDCS */ +#define PIO_PA22C_NCS2 (1u << 22) /**< \brief Ebi signal: NCS2 */ +#define PIO_PC12A_NCS3 (1u << 12) /**< \brief Ebi signal: NCS3 */ +#define PIO_PD19A_NCS3 (1u << 19) /**< \brief Ebi signal: NCS3 */ +#define PIO_PC11A_NRD (1u << 11) /**< \brief Ebi signal: NRD */ +#define PIO_PC13A_NWAIT (1u << 13) /**< \brief Ebi signal: NWAIT */ +#define PIO_PC8A_NWR0 (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PC8A_NWE (1u << 8) /**< \brief Ebi signal: NWR0/NWE */ +#define PIO_PD15C_NWR1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD15C_NBS1 (1u << 15) /**< \brief Ebi signal: NWR1/NBS1 */ +#define PIO_PD16C_RAS (1u << 16) /**< \brief Ebi signal: RAS */ +#define PIO_PC13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD13C_SDA10 (1u << 13) /**< \brief Ebi signal: SDA10 */ +#define PIO_PD23C_SDCK (1u << 23) /**< \brief Ebi signal: SDCK */ +#define PIO_PD14C_SDCKE (1u << 14) /**< \brief Ebi signal: SDCKE */ +#define PIO_PD29C_SDWE (1u << 29) /**< \brief Ebi signal: SDWE */ +/* ========== Pio definition for GMAC peripheral ========== */ +#define PIO_PD13A_GCOL (1u << 13) /**< \brief Gmac signal: GCOL */ +#define PIO_PD10A_GCRS (1u << 10) /**< \brief Gmac signal: GCRS */ +#define PIO_PD8A_GMDC (1u << 8) /**< \brief Gmac signal: GMDC */ +#define PIO_PD9A_GMDIO (1u << 9) /**< \brief Gmac signal: GMDIO */ +#define PIO_PD5A_GRX0 (1u << 5) /**< \brief Gmac signal: GRX0 */ +#define PIO_PD6A_GRX1 (1u << 6) /**< \brief Gmac signal: GRX1 */ +#define PIO_PD11A_GRX2 (1u << 11) /**< \brief Gmac signal: GRX2 */ +#define PIO_PD12A_GRX3 (1u << 12) /**< \brief Gmac signal: GRX3 */ +#define PIO_PD14A_GRXCK (1u << 14) /**< \brief Gmac signal: GRXCK */ +#define PIO_PD4A_GRXDV (1u << 4) /**< \brief Gmac signal: GRXDV */ +#define PIO_PD7A_GRXER (1u << 7) /**< \brief Gmac signal: GRXER */ +#define PIO_PB1B_GTSUCOMP (1u << 1) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PB12B_GTSUCOMP (1u << 12) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD11C_GTSUCOMP (1u << 11) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD20C_GTSUCOMP (1u << 20) /**< \brief Gmac signal: GTSUCOMP */ +#define PIO_PD2A_GTX0 (1u << 2) /**< \brief Gmac signal: GTX0 */ +#define PIO_PD3A_GTX1 (1u << 3) /**< \brief Gmac signal: GTX1 */ +#define PIO_PD15A_GTX2 (1u << 15) /**< \brief Gmac signal: GTX2 */ +#define PIO_PD16A_GTX3 (1u << 16) /**< \brief Gmac signal: GTX3 */ +#define PIO_PD0A_GTXCK (1u << 0) /**< \brief Gmac signal: GTXCK */ +#define PIO_PD1A_GTXEN (1u << 1) /**< \brief Gmac signal: GTXEN */ +#define PIO_PD17A_GTXER (1u << 17) /**< \brief Gmac signal: GTXER */ +/* ========== Pio definition for HSMCI peripheral ========== */ +#define PIO_PA28C_MCCDA (1u << 28) /**< \brief Hsmci signal: MCCDA */ +#define PIO_PA25D_MCCK (1u << 25) /**< \brief Hsmci signal: MCCK */ +#define PIO_PA30C_MCDA0 (1u << 30) /**< \brief Hsmci signal: MCDA0 */ +#define PIO_PA31C_MCDA1 (1u << 31) /**< \brief Hsmci signal: MCDA1 */ +#define PIO_PA26C_MCDA2 (1u << 26) /**< \brief Hsmci signal: MCDA2 */ +#define PIO_PA27C_MCDA3 (1u << 27) /**< \brief Hsmci signal: MCDA3 */ +/* ========== Pio definition for ISI peripheral ========== */ +#define PIO_PD22D_ISI_D0 (1u << 22) /**< \brief Isi signal: ISI_D0 */ +#define PIO_PD21D_ISI_D1 (1u << 21) /**< \brief Isi signal: ISI_D1 */ +#define PIO_PD30D_ISI_D10 (1u << 30) /**< \brief Isi signal: ISI_D10 */ +#define PIO_PD31D_ISI_D11 (1u << 31) /**< \brief Isi signal: ISI_D11 */ +#define PIO_PB3D_ISI_D2 (1u << 3) /**< \brief Isi signal: ISI_D2 */ +#define PIO_PA9B_ISI_D3 (1u << 9) /**< \brief Isi signal: ISI_D3 */ +#define PIO_PA5B_ISI_D4 (1u << 5) /**< \brief Isi signal: ISI_D4 */ +#define PIO_PD11D_ISI_D5 (1u << 11) /**< \brief Isi signal: ISI_D5 */ +#define PIO_PD12D_ISI_D6 (1u << 12) /**< \brief Isi signal: ISI_D6 */ +#define PIO_PA27D_ISI_D7 (1u << 27) /**< \brief Isi signal: ISI_D7 */ +#define PIO_PD27D_ISI_D8 (1u << 27) /**< \brief Isi signal: ISI_D8 */ +#define PIO_PD28D_ISI_D9 (1u << 28) /**< \brief Isi signal: ISI_D9 */ +#define PIO_PD24D_ISI_HSYNC (1u << 24) /**< \brief Isi signal: ISI_HSYNC */ +#define PIO_PA24D_ISI_PCK (1u << 24) /**< \brief Isi signal: ISI_PCK */ +#define PIO_PD25D_ISI_VSYNC (1u << 25) /**< \brief Isi signal: ISI_VSYNC */ +/* ========== Pio definition for MCAN0 peripheral ========== */ +#define PIO_PB3A_CANRX0 (1u << 3) /**< \brief Mcan0 signal: CANRX0 */ +#define PIO_PB2A_CANTX0 (1u << 2) /**< \brief Mcan0 signal: CANTX0 */ +/* ========== Pio definition for MCAN1 peripheral ========== */ +#define PIO_PC12C_CANRX1 (1u << 12) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PD28B_CANRX1 (1u << 28) /**< \brief Mcan1 signal: CANRX1 */ +#define PIO_PC14C_CANTX1 (1u << 14) /**< \brief Mcan1 signal: CANTX1 */ +#define PIO_PD12B_CANTX1 (1u << 12) /**< \brief Mcan1 signal: CANTX1 */ +/* ========== Pio definition for MLB peripheral ========== */ +#define PIO_PB4C_MLBCLK (1u << 4) /**< \brief Mlb signal: MLBCLK */ +#define PIO_PB5C_MLBDAT (1u << 5) /**< \brief Mlb signal: MLBDAT */ +#define PIO_PD10D_MLBSIG (1u << 10) /**< \brief Mlb signal: MLBSIG */ +/* ========== Pio definition for PIOA peripheral ========== */ +#define PIO_PA21X1_AFE0_AD1 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA21X1_PIODCEN2 (1u << 21) /**< \brief Pioa signal: AFE0_AD1/PIODCEN2 */ +#define PIO_PA3X1_PIODC0 (1u << 3) /**< \brief Pioa signal: PIODC0 */ +#define PIO_PA10X1_PIODC4 (1u << 10) /**< \brief Pioa signal: PIODC4 */ +#define PIO_PA12X1_PIODC6 (1u << 12) /**< \brief Pioa signal: PIODC6 */ +#define PIO_PA13X1_PIODC7 (1u << 13) /**< \brief Pioa signal: PIODC7 */ +#define PIO_PA22X1_PIODCCLK (1u << 22) /**< \brief Pioa signal: PIODCCLK */ +#define PIO_PA4X1_WKUP3 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA4X1_PIODC1 (1u << 4) /**< \brief Pioa signal: WKUP3/PIODC1 */ +#define PIO_PA5X1_WKUP4 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA5X1_PIODC2 (1u << 5) /**< \brief Pioa signal: WKUP4/PIODC2 */ +#define PIO_PA9X1_WKUP6 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA9X1_PIODC3 (1u << 9) /**< \brief Pioa signal: WKUP6/PIODC3 */ +#define PIO_PA11X1_WKUP7 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA11X1_PIODC5 (1u << 11) /**< \brief Pioa signal: WKUP7/PIODC5 */ +#define PIO_PA14X1_WKUP8 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +#define PIO_PA14X1_PIODCEN1 (1u << 14) /**< \brief Pioa signal: WKUP8/PIODCEN1 */ +/* ========== Pio definition for PMC peripheral ========== */ +#define PIO_PA6B_PCK0 (1u << 6) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB12D_PCK0 (1u << 12) /**< \brief Pmc signal: PCK0 */ +#define PIO_PB13B_PCK0 (1u << 13) /**< \brief Pmc signal: PCK0 */ +#define PIO_PA17B_PCK1 (1u << 17) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA21B_PCK1 (1u << 21) /**< \brief Pmc signal: PCK1 */ +#define PIO_PA3C_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA18B_PCK2 (1u << 18) /**< \brief Pmc signal: PCK2 */ +#define PIO_PA31B_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +#define PIO_PB3B_PCK2 (1u << 3) /**< \brief Pmc signal: PCK2 */ +#define PIO_PD31C_PCK2 (1u << 31) /**< \brief Pmc signal: PCK2 */ +/* ========== Pio definition for PWM0 peripheral ========== */ +#define PIO_PA10B_PWMC0_PWMEXTRG0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG0 */ +#define PIO_PA22B_PWMC0_PWMEXTRG1 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMEXTRG1 */ +#define PIO_PA9C_PWMC0_PWMFI0 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI0 */ +#define PIO_PD8B_PWMC0_PWMFI1 (1u << 8) /**< \brief Pwm0 signal: PWMC0_PWMFI1 */ +#define PIO_PD9B_PWMC0_PWMFI2 (1u << 9) /**< \brief Pwm0 signal: PWMC0_PWMFI2 */ +#define PIO_PA0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA23B_PWMC0_PWMH0 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PB0A_PWMC0_PWMH0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD11B_PWMC0_PWMH0 (1u << 11) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PD20A_PWMC0_PWMH0 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWMH0 */ +#define PIO_PA2A_PWMC0_PWMH1 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA12B_PWMC0_PWMH1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA24B_PWMC0_PWMH1 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PB1A_PWMC0_PWMH1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PD21A_PWMC0_PWMH1 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH1 */ +#define PIO_PA13B_PWMC0_PWMH2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA25B_PWMC0_PWMH2 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PB4B_PWMC0_PWMH2 (1u << 4) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PC19B_PWMC0_PWMH2 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PD22A_PWMC0_PWMH2 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWMH2 */ +#define PIO_PA7B_PWMC0_PWMH3 (1u << 7) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA14B_PWMC0_PWMH3 (1u << 14) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA17C_PWMC0_PWMH3 (1u << 17) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC13B_PWMC0_PWMH3 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PC21B_PWMC0_PWMH3 (1u << 21) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PD23A_PWMC0_PWMH3 (1u << 23) /**< \brief Pwm0 signal: PWMC0_PWMH3 */ +#define PIO_PA1A_PWMC0_PWML0 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA19B_PWMC0_PWML0 (1u << 19) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PB5B_PWMC0_PWML0 (1u << 5) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PC0B_PWMC0_PWML0 (1u << 0) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD10B_PWMC0_PWML0 (1u << 10) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PD24A_PWMC0_PWML0 (1u << 24) /**< \brief Pwm0 signal: PWMC0_PWML0 */ +#define PIO_PA20B_PWMC0_PWML1 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PB12A_PWMC0_PWML1 (1u << 12) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC1B_PWMC0_PWML1 (1u << 1) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PC18B_PWMC0_PWML1 (1u << 18) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PD25A_PWMC0_PWML1 (1u << 25) /**< \brief Pwm0 signal: PWMC0_PWML1 */ +#define PIO_PA16C_PWMC0_PWML2 (1u << 16) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA30A_PWMC0_PWML2 (1u << 30) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PB13A_PWMC0_PWML2 (1u << 13) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC2B_PWMC0_PWML2 (1u << 2) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PC20B_PWMC0_PWML2 (1u << 20) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PD26A_PWMC0_PWML2 (1u << 26) /**< \brief Pwm0 signal: PWMC0_PWML2 */ +#define PIO_PA15C_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC3B_PWMC0_PWML3 (1u << 3) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC15B_PWMC0_PWML3 (1u << 15) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PC22B_PWMC0_PWML3 (1u << 22) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +#define PIO_PD27A_PWMC0_PWML3 (1u << 27) /**< \brief Pwm0 signal: PWMC0_PWML3 */ +/* ========== Pio definition for PWM1 peripheral ========== */ +#define PIO_PA30B_PWMC1_PWMEXTRG0 (1u << 30) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG0 */ +#define PIO_PA18A_PWMC1_PWMEXTRG1 (1u << 18) /**< \brief Pwm1 signal: PWMC1_PWMEXTRG1 */ +#define PIO_PA21C_PWMC1_PWMFI0 (1u << 21) /**< \brief Pwm1 signal: PWMC1_PWMFI0 */ +#define PIO_PA26D_PWMC1_PWMFI1 (1u << 26) /**< \brief Pwm1 signal: PWMC1_PWMFI1 */ +#define PIO_PA28D_PWMC1_PWMFI2 (1u << 28) /**< \brief Pwm1 signal: PWMC1_PWMFI2 */ +#define PIO_PA12C_PWMC1_PWMH0 (1u << 12) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PD1B_PWMC1_PWMH0 (1u << 1) /**< \brief Pwm1 signal: PWMC1_PWMH0 */ +#define PIO_PA14C_PWMC1_PWMH1 (1u << 14) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PD3B_PWMC1_PWMH1 (1u << 3) /**< \brief Pwm1 signal: PWMC1_PWMH1 */ +#define PIO_PA31D_PWMC1_PWMH2 (1u << 31) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PD5B_PWMC1_PWMH2 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWMH2 */ +#define PIO_PA8A_PWMC1_PWMH3 (1u << 8) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PD7B_PWMC1_PWMH3 (1u << 7) /**< \brief Pwm1 signal: PWMC1_PWMH3 */ +#define PIO_PA11C_PWMC1_PWML0 (1u << 11) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PD0B_PWMC1_PWML0 (1u << 0) /**< \brief Pwm1 signal: PWMC1_PWML0 */ +#define PIO_PA13C_PWMC1_PWML1 (1u << 13) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PD2B_PWMC1_PWML1 (1u << 2) /**< \brief Pwm1 signal: PWMC1_PWML1 */ +#define PIO_PA23D_PWMC1_PWML2 (1u << 23) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PD4B_PWMC1_PWML2 (1u << 4) /**< \brief Pwm1 signal: PWMC1_PWML2 */ +#define PIO_PA5A_PWMC1_PWML3 (1u << 5) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +#define PIO_PD6B_PWMC1_PWML3 (1u << 6) /**< \brief Pwm1 signal: PWMC1_PWML3 */ +/* ========== Pio definition for QSPI peripheral ========== */ +#define PIO_PA11A_QCS (1u << 11) /**< \brief Qspi signal: QCS */ +#define PIO_PA13A_QIO0 (1u << 13) /**< \brief Qspi signal: QIO0 */ +#define PIO_PA12A_QIO1 (1u << 12) /**< \brief Qspi signal: QIO1 */ +#define PIO_PA17A_QIO2 (1u << 17) /**< \brief Qspi signal: QIO2 */ +#define PIO_PD31A_QIO3 (1u << 31) /**< \brief Qspi signal: QIO3 */ +#define PIO_PA14A_QSCK (1u << 14) /**< \brief Qspi signal: QSCK */ +/* ========== Pio definition for SPI0 peripheral ========== */ +#define PIO_PD20B_SPI0_MISO (1u << 20) /**< \brief Spi0 signal: SPI0_MISO */ +#define PIO_PD21B_SPI0_MOSI (1u << 21) /**< \brief Spi0 signal: SPI0_MOSI */ +#define PIO_PB2D_SPI0_NPCS0 (1u << 2) /**< \brief Spi0 signal: SPI0_NPCS0 */ +#define PIO_PA31A_SPI0_NPCS1 (1u << 31) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD25B_SPI0_NPCS1 (1u << 25) /**< \brief Spi0 signal: SPI0_NPCS1 */ +#define PIO_PD12C_SPI0_NPCS2 (1u << 12) /**< \brief Spi0 signal: SPI0_NPCS2 */ +#define PIO_PD27B_SPI0_NPCS3 (1u << 27) /**< \brief Spi0 signal: SPI0_NPCS3 */ +#define PIO_PD22B_SPI0_SPCK (1u << 22) /**< \brief Spi0 signal: SPI0_SPCK */ +/* ========== Pio definition for SPI1 peripheral ========== */ +#define PIO_PC26C_SPI1_MISO (1u << 26) /**< \brief Spi1 signal: SPI1_MISO */ +#define PIO_PC27C_SPI1_MOSI (1u << 27) /**< \brief Spi1 signal: SPI1_MOSI */ +#define PIO_PC25C_SPI1_NPCS0 (1u << 25) /**< \brief Spi1 signal: SPI1_NPCS0 */ +#define PIO_PC28C_SPI1_NPCS1 (1u << 28) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PD0C_SPI1_NPCS1 (1u << 0) /**< \brief Spi1 signal: SPI1_NPCS1 */ +#define PIO_PC29C_SPI1_NPCS2 (1u << 29) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PD1C_SPI1_NPCS2 (1u << 1) /**< \brief Spi1 signal: SPI1_NPCS2 */ +#define PIO_PC30C_SPI1_NPCS3 (1u << 30) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PD2C_SPI1_NPCS3 (1u << 2) /**< \brief Spi1 signal: SPI1_NPCS3 */ +#define PIO_PC24C_SPI1_SPCK (1u << 24) /**< \brief Spi1 signal: SPI1_SPCK */ +/* ========== Pio definition for SSC peripheral ========== */ +#define PIO_PA10C_RD (1u << 10) /**< \brief Ssc signal: RD */ +#define PIO_PD24B_RF (1u << 24) /**< \brief Ssc signal: RF */ +#define PIO_PA22A_RK (1u << 22) /**< \brief Ssc signal: RK */ +#define PIO_PB5D_TD (1u << 5) /**< \brief Ssc signal: TD */ +#define PIO_PD10C_TD (1u << 10) /**< \brief Ssc signal: TD */ +#define PIO_PD26B_TD (1u << 26) /**< \brief Ssc signal: TD */ +#define PIO_PB0D_TF (1u << 0) /**< \brief Ssc signal: TF */ +#define PIO_PB1D_TK (1u << 1) /**< \brief Ssc signal: TK */ +/* ========== Pio definition for TC0 peripheral ========== */ +#define PIO_PA4B_TCLK0 (1u << 4) /**< \brief Tc0 signal: TCLK0 */ +#define PIO_PA28B_TCLK1 (1u << 28) /**< \brief Tc0 signal: TCLK1 */ +#define PIO_PA29B_TCLK2 (1u << 29) /**< \brief Tc0 signal: TCLK2 */ +#define PIO_PA0B_TIOA0 (1u << 0) /**< \brief Tc0 signal: TIOA0 */ +#define PIO_PA15B_TIOA1 (1u << 15) /**< \brief Tc0 signal: TIOA1 */ +#define PIO_PA26B_TIOA2 (1u << 26) /**< \brief Tc0 signal: TIOA2 */ +#define PIO_PA1B_TIOB0 (1u << 1) /**< \brief Tc0 signal: TIOB0 */ +#define PIO_PA16B_TIOB1 (1u << 16) /**< \brief Tc0 signal: TIOB1 */ +#define PIO_PA27B_TIOB2 (1u << 27) /**< \brief Tc0 signal: TIOB2 */ +/* ========== Pio definition for TC1 peripheral ========== */ +#define PIO_PC25B_TCLK3 (1u << 25) /**< \brief Tc1 signal: TCLK3 */ +#define PIO_PC28B_TCLK4 (1u << 28) /**< \brief Tc1 signal: TCLK4 */ +#define PIO_PC31B_TCLK5 (1u << 31) /**< \brief Tc1 signal: TCLK5 */ +#define PIO_PC23B_TIOA3 (1u << 23) /**< \brief Tc1 signal: TIOA3 */ +#define PIO_PC26B_TIOA4 (1u << 26) /**< \brief Tc1 signal: TIOA4 */ +#define PIO_PC29B_TIOA5 (1u << 29) /**< \brief Tc1 signal: TIOA5 */ +#define PIO_PC24B_TIOB3 (1u << 24) /**< \brief Tc1 signal: TIOB3 */ +#define PIO_PC27B_TIOB4 (1u << 27) /**< \brief Tc1 signal: TIOB4 */ +#define PIO_PC30B_TIOB5 (1u << 30) /**< \brief Tc1 signal: TIOB5 */ +/* ========== Pio definition for TC2 peripheral ========== */ +#define PIO_PC7B_TCLK6 (1u << 7) /**< \brief Tc2 signal: TCLK6 */ +#define PIO_PC10B_TCLK7 (1u << 10) /**< \brief Tc2 signal: TCLK7 */ +#define PIO_PC14B_TCLK8 (1u << 14) /**< \brief Tc2 signal: TCLK8 */ +#define PIO_PC5B_TIOA6 (1u << 5) /**< \brief Tc2 signal: TIOA6 */ +#define PIO_PC8B_TIOA7 (1u << 8) /**< \brief Tc2 signal: TIOA7 */ +#define PIO_PC11B_TIOA8 (1u << 11) /**< \brief Tc2 signal: TIOA8 */ +#define PIO_PC6B_TIOB6 (1u << 6) /**< \brief Tc2 signal: TIOB6 */ +#define PIO_PC9B_TIOB7 (1u << 9) /**< \brief Tc2 signal: TIOB7 */ +#define PIO_PC12B_TIOB8 (1u << 12) /**< \brief Tc2 signal: TIOB8 */ +/* ========== Pio definition for TC3 peripheral ========== */ +#define PIO_PE5B_TCLK10 (1u << 5) /**< \brief Tc3 signal: TCLK10 */ +#define PIO_PD24C_TCLK11 (1u << 24) /**< \brief Tc3 signal: TCLK11 */ +#define PIO_PE2B_TCLK9 (1u << 2) /**< \brief Tc3 signal: TCLK9 */ +#define PIO_PE3B_TIOA10 (1u << 3) /**< \brief Tc3 signal: TIOA10 */ +#define PIO_PD21C_TIOA11 (1u << 21) /**< \brief Tc3 signal: TIOA11 */ +#define PIO_PE0B_TIOA9 (1u << 0) /**< \brief Tc3 signal: TIOA9 */ +#define PIO_PE4B_TIOB10 (1u << 4) /**< \brief Tc3 signal: TIOB10 */ +#define PIO_PD22C_TIOB11 (1u << 22) /**< \brief Tc3 signal: TIOB11 */ +#define PIO_PE1B_TIOB9 (1u << 1) /**< \brief Tc3 signal: TIOB9 */ +/* ========== Pio definition for TWIHS0 peripheral ========== */ +#define PIO_PA4A_TWCK0 (1u << 4) /**< \brief Twihs0 signal: TWCK0 */ +#define PIO_PA3A_TWD0 (1u << 3) /**< \brief Twihs0 signal: TWD0 */ +/* ========== Pio definition for TWIHS1 peripheral ========== */ +#define PIO_PB5A_TWCK1 (1u << 5) /**< \brief Twihs1 signal: TWCK1 */ +#define PIO_PB4A_TWD1 (1u << 4) /**< \brief Twihs1 signal: TWD1 */ +/* ========== Pio definition for TWIHS2 peripheral ========== */ +#define PIO_PD28C_TWCK2 (1u << 28) /**< \brief Twihs2 signal: TWCK2 */ +#define PIO_PD27C_TWD2 (1u << 27) /**< \brief Twihs2 signal: TWD2 */ +/* ========== Pio definition for UART0 peripheral ========== */ +#define PIO_PA9A_URXD0 (1u << 9) /**< \brief Uart0 signal: URXD0 */ +#define PIO_PA10A_UTXD0 (1u << 10) /**< \brief Uart0 signal: UTXD0 */ +/* ========== Pio definition for UART1 peripheral ========== */ +#define PIO_PA5C_URXD1 (1u << 5) /**< \brief Uart1 signal: URXD1 */ +#define PIO_PA4C_UTXD1 (1u << 4) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PA6C_UTXD1 (1u << 6) /**< \brief Uart1 signal: UTXD1 */ +#define PIO_PD26D_UTXD1 (1u << 26) /**< \brief Uart1 signal: UTXD1 */ +/* ========== Pio definition for UART2 peripheral ========== */ +#define PIO_PD25C_URXD2 (1u << 25) /**< \brief Uart2 signal: URXD2 */ +#define PIO_PD26C_UTXD2 (1u << 26) /**< \brief Uart2 signal: UTXD2 */ +/* ========== Pio definition for UART3 peripheral ========== */ +#define PIO_PD28A_URXD3 (1u << 28) /**< \brief Uart3 signal: URXD3 */ +#define PIO_PD30A_UTXD3 (1u << 30) /**< \brief Uart3 signal: UTXD3 */ +#define PIO_PD31B_UTXD3 (1u << 31) /**< \brief Uart3 signal: UTXD3 */ +/* ========== Pio definition for UART4 peripheral ========== */ +#define PIO_PD18C_URXD4 (1u << 18) /**< \brief Uart4 signal: URXD4 */ +#define PIO_PD3C_UTXD4 (1u << 3) /**< \brief Uart4 signal: UTXD4 */ +#define PIO_PD19C_UTXD4 (1u << 19) /**< \brief Uart4 signal: UTXD4 */ +/* ========== Pio definition for USART0 peripheral ========== */ +#define PIO_PB2C_CTS0 (1u << 2) /**< \brief Usart0 signal: CTS0 */ +#define PIO_PD0D_DCD0 (1u << 0) /**< \brief Usart0 signal: DCD0 */ +#define PIO_PD2D_DSR0 (1u << 2) /**< \brief Usart0 signal: DSR0 */ +#define PIO_PD1D_DTR0 (1u << 1) /**< \brief Usart0 signal: DTR0 */ +#define PIO_PD3D_RI0 (1u << 3) /**< \brief Usart0 signal: RI0 */ +#define PIO_PB3C_RTS0 (1u << 3) /**< \brief Usart0 signal: RTS0 */ +#define PIO_PB0C_RXD0 (1u << 0) /**< \brief Usart0 signal: RXD0 */ +#define PIO_PB13C_SCK0 (1u << 13) /**< \brief Usart0 signal: SCK0 */ +#define PIO_PB1C_TXD0 (1u << 1) /**< \brief Usart0 signal: TXD0 */ +/* ========== Pio definition for USART1 peripheral ========== */ +#define PIO_PA25A_CTS1 (1u << 25) /**< \brief Usart1 signal: CTS1 */ +#define PIO_PA26A_DCD1 (1u << 26) /**< \brief Usart1 signal: DCD1 */ +#define PIO_PA28A_DSR1 (1u << 28) /**< \brief Usart1 signal: DSR1 */ +#define PIO_PA27A_DTR1 (1u << 27) /**< \brief Usart1 signal: DTR1 */ +#define PIO_PA3B_LONCOL1 (1u << 3) /**< \brief Usart1 signal: LONCOL1 */ +#define PIO_PA29A_RI1 (1u << 29) /**< \brief Usart1 signal: RI1 */ +#define PIO_PA24A_RTS1 (1u << 24) /**< \brief Usart1 signal: RTS1 */ +#define PIO_PA21A_RXD1 (1u << 21) /**< \brief Usart1 signal: RXD1 */ +#define PIO_PA23A_SCK1 (1u << 23) /**< \brief Usart1 signal: SCK1 */ +#define PIO_PB4D_TXD1 (1u << 4) /**< \brief Usart1 signal: TXD1 */ +/* ========== Pio definition for USART2 peripheral ========== */ +#define PIO_PD19B_CTS2 (1u << 19) /**< \brief Usart2 signal: CTS2 */ +#define PIO_PD4D_DCD2 (1u << 4) /**< \brief Usart2 signal: DCD2 */ +#define PIO_PD6D_DSR2 (1u << 6) /**< \brief Usart2 signal: DSR2 */ +#define PIO_PD5D_DTR2 (1u << 5) /**< \brief Usart2 signal: DTR2 */ +#define PIO_PD7D_RI2 (1u << 7) /**< \brief Usart2 signal: RI2 */ +#define PIO_PD18B_RTS2 (1u << 18) /**< \brief Usart2 signal: RTS2 */ +#define PIO_PD15B_RXD2 (1u << 15) /**< \brief Usart2 signal: RXD2 */ +#define PIO_PD17B_SCK2 (1u << 17) /**< \brief Usart2 signal: SCK2 */ +#define PIO_PD16B_TXD2 (1u << 16) /**< \brief Usart2 signal: TXD2 */ +/* ========== Pio indexes ========== */ +#define PIO_PA0_IDX 0 +#define PIO_PA1_IDX 1 +#define PIO_PA2_IDX 2 +#define PIO_PA3_IDX 3 +#define PIO_PA4_IDX 4 +#define PIO_PA5_IDX 5 +#define PIO_PA6_IDX 6 +#define PIO_PA7_IDX 7 +#define PIO_PA8_IDX 8 +#define PIO_PA9_IDX 9 +#define PIO_PA10_IDX 10 +#define PIO_PA11_IDX 11 +#define PIO_PA12_IDX 12 +#define PIO_PA13_IDX 13 +#define PIO_PA14_IDX 14 +#define PIO_PA15_IDX 15 +#define PIO_PA16_IDX 16 +#define PIO_PA17_IDX 17 +#define PIO_PA18_IDX 18 +#define PIO_PA19_IDX 19 +#define PIO_PA20_IDX 20 +#define PIO_PA21_IDX 21 +#define PIO_PA22_IDX 22 +#define PIO_PA23_IDX 23 +#define PIO_PA24_IDX 24 +#define PIO_PA25_IDX 25 +#define PIO_PA26_IDX 26 +#define PIO_PA27_IDX 27 +#define PIO_PA28_IDX 28 +#define PIO_PA29_IDX 29 +#define PIO_PA30_IDX 30 +#define PIO_PA31_IDX 31 +#define PIO_PB0_IDX 32 +#define PIO_PB1_IDX 33 +#define PIO_PB2_IDX 34 +#define PIO_PB3_IDX 35 +#define PIO_PB4_IDX 36 +#define PIO_PB5_IDX 37 +#define PIO_PB6_IDX 38 +#define PIO_PB7_IDX 39 +#define PIO_PB8_IDX 40 +#define PIO_PB9_IDX 41 +#define PIO_PB12_IDX 44 +#define PIO_PB13_IDX 45 +#define PIO_PC0_IDX 64 +#define PIO_PC1_IDX 65 +#define PIO_PC2_IDX 66 +#define PIO_PC3_IDX 67 +#define PIO_PC4_IDX 68 +#define PIO_PC5_IDX 69 +#define PIO_PC6_IDX 70 +#define PIO_PC7_IDX 71 +#define PIO_PC8_IDX 72 +#define PIO_PC9_IDX 73 +#define PIO_PC10_IDX 74 +#define PIO_PC11_IDX 75 +#define PIO_PC12_IDX 76 +#define PIO_PC13_IDX 77 +#define PIO_PC14_IDX 78 +#define PIO_PC15_IDX 79 +#define PIO_PC16_IDX 80 +#define PIO_PC17_IDX 81 +#define PIO_PC18_IDX 82 +#define PIO_PC19_IDX 83 +#define PIO_PC20_IDX 84 +#define PIO_PC21_IDX 85 +#define PIO_PC22_IDX 86 +#define PIO_PC23_IDX 87 +#define PIO_PC24_IDX 88 +#define PIO_PC25_IDX 89 +#define PIO_PC26_IDX 90 +#define PIO_PC27_IDX 91 +#define PIO_PC28_IDX 92 +#define PIO_PC29_IDX 93 +#define PIO_PC30_IDX 94 +#define PIO_PC31_IDX 95 +#define PIO_PD0_IDX 96 +#define PIO_PD1_IDX 97 +#define PIO_PD2_IDX 98 +#define PIO_PD3_IDX 99 +#define PIO_PD4_IDX 100 +#define PIO_PD5_IDX 101 +#define PIO_PD6_IDX 102 +#define PIO_PD7_IDX 103 +#define PIO_PD8_IDX 104 +#define PIO_PD9_IDX 105 +#define PIO_PD10_IDX 106 +#define PIO_PD11_IDX 107 +#define PIO_PD12_IDX 108 +#define PIO_PD13_IDX 109 +#define PIO_PD14_IDX 110 +#define PIO_PD15_IDX 111 +#define PIO_PD16_IDX 112 +#define PIO_PD17_IDX 113 +#define PIO_PD18_IDX 114 +#define PIO_PD19_IDX 115 +#define PIO_PD20_IDX 116 +#define PIO_PD21_IDX 117 +#define PIO_PD22_IDX 118 +#define PIO_PD23_IDX 119 +#define PIO_PD24_IDX 120 +#define PIO_PD25_IDX 121 +#define PIO_PD26_IDX 122 +#define PIO_PD27_IDX 123 +#define PIO_PD28_IDX 124 +#define PIO_PD29_IDX 125 +#define PIO_PD30_IDX 126 +#define PIO_PD31_IDX 127 +#define PIO_PE0_IDX 128 +#define PIO_PE1_IDX 129 +#define PIO_PE2_IDX 130 +#define PIO_PE3_IDX 131 +#define PIO_PE4_IDX 132 +#define PIO_PE5_IDX 133 + +#endif /* _SAMV71Q21_PIO_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71.h new file mode 100644 index 000000000..8daa59672 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71.h @@ -0,0 +1,55 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71_ +#define _SAMV71_ + +#if defined __SAMV71J19__ + #include "samv71j19.h" +#elif defined __SAMV71J20__ + #include "samv71j20.h" +#elif defined __SAMV71J21__ + #include "samv71j21.h" +#elif defined __SAMV71N19__ + #include "samv71n19.h" +#elif defined __SAMV71N20__ + #include "samv71n20.h" +#elif defined __SAMV71N21__ + #include "samv71n21.h" +#elif defined __SAMV71Q19__ + #include "samv71q19.h" +#elif defined __SAMV71Q20__ + #include "samv71q20.h" +#elif defined __SAMV71Q21__ + #include "samv71q21.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAMV71_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j19.h new file mode 100644 index 000000000..182838c72 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j19.h @@ -0,0 +1,633 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J19_ +#define _SAMV71J19_ + +/** \addtogroup SAMV71J19_definitions SAMV71J19 definitions + This file defines all structures and symbols for SAMV71J19: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J19 Analog Front End 0 (AFEC0) */ + PWM0_IRQn = 31, /**< 31 SAMV71J19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J19 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J19 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J19 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pvReserved30; + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J19_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j20.h new file mode 100644 index 000000000..194b3eff4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j20.h @@ -0,0 +1,640 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J20_ +#define _SAMV71J20_ + +/** \addtogroup SAMV71J20_definitions SAMV71J20 definitions + This file defines all structures and symbols for SAMV71J20: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J20 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J20 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J20 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J20_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j21.h new file mode 100644 index 000000000..f8ccf9518 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71j21.h @@ -0,0 +1,639 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71J21_ +#define _SAMV71J21_ + +/** \addtogroup SAMV71J21_definitions SAMV71J21 definitions + This file defines all structures and symbols for SAMV71J21: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71J21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71J21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71J21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71J21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71J21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71J21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71J21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71J21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71J21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71J21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71J21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71J21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71J21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71J21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71J21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71J21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71J21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71J21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71J21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71J21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71J21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71J21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71J21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71J21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71J21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71J21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71J21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71J21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71J21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71J21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71J21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71J21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71J21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71J21 Analog Front End 1 (AFEC1) */ + SPI1_IRQn = 42, /**< 42 SAMV71J21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71J21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71J21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71J21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71J21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71J21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71J21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71J21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71J21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71J21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71J21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71J21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71J21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71J21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71J21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pvReserved41; + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71J21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71J21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71J21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71J21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71J21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71J21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71J21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71J21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71J21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71J21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71j21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000000UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71J21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71J21_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n19.h new file mode 100644 index 000000000..6a1b27894 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n19.h @@ -0,0 +1,646 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N19_ +#define _SAMV71N19_ + +/** \addtogroup SAMV71N19_definitions SAMV71N19 definitions + This file defines all structures and symbols for SAMV71N19: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N19 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N19 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N19 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71N19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71N19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N19 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N19 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N19 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N19 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N19_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n20.h new file mode 100644 index 000000000..129230fa0 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n20.h @@ -0,0 +1,639 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N20_ +#define _SAMV71N20_ + +/** \addtogroup SAMV71N20_definitions SAMV71N20 definitions + This file defines all structures and symbols for SAMV71N20: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N20 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N20 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N20 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N20 Analog Front End 0 (AFEC0) */ + PWM0_IRQn = 31, /**< 31 SAMV71N20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N20 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N20 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N20 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N20 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pvReserved30; + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N20_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n21.h new file mode 100644 index 000000000..122dc7acf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71n21.h @@ -0,0 +1,639 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71N21_ +#define _SAMV71N21_ + +/** \addtogroup SAMV71N21_definitions SAMV71N21 definitions + This file defines all structures and symbols for SAMV71N21: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71N21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71N21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71N21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71N21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71N21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71N21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71N21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71N21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71N21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71N21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71N21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71N21 Parallel I/O Controller B (PIOB) */ + USART0_IRQn = 13, /**< 13 SAMV71N21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71N21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71N21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71N21 Parallel I/O Controller D (PIOD) */ + HSMCI_IRQn = 18, /**< 18 SAMV71N21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71N21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71N21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71N21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71N21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71N21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71N21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71N21 Timer/Counter 2 (TC2) */ + AFEC0_IRQn = 29, /**< 29 SAMV71N21 Analog Front End 0 (AFEC0) */ + PWM0_IRQn = 31, /**< 31 SAMV71N21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71N21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71N21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71N21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71N21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71N21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71N21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71N21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71N21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71N21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71N21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71N21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71N21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71N21 UART 4 (UART4) */ + TC9_IRQn = 50, /**< 50 SAMV71N21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71N21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71N21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71N21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71N21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71N21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71N21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71N21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71N21 Pulse Width Modulation 1 (PWM1) */ + RSWDT_IRQn = 63, /**< 63 SAMV71N21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pvReserved12; + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pvReserved17; + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pvReserved26; + void* pvReserved27; + void* pvReserved28; + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pvReserved30; + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pvReserved47; + void* pvReserved48; + void* pvReserved49; + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pvReserved62; + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOD_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71N21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71N21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71N21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71N21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71N21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71N21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71N21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71N21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71N21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_piod.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71N21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71n21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000001UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71N21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71N21_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q19.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q19.h new file mode 100644 index 000000000..49321e170 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q19.h @@ -0,0 +1,694 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q19_ +#define _SAMV71Q19_ + +/** \addtogroup SAMV71Q19_definitions SAMV71Q19 definitions + This file defines all structures and symbols for SAMV71Q19: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q19 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q19 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q19 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q19 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q19 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q19 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q19 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q19 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q19 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q19 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q19 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q19 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q19 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q19 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q19 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q19 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q19 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q19 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q19 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q19 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q19 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q19 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q19 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q19 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q19 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q19 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q19 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q19 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q19 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q19 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q19 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q19 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q19 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q19 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q19 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q19 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q19 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q19 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q19 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q19 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q19 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q19 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q19 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q19 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q19 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q19 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q19 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q19 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q19 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q19 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q19 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q19 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q19 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q19 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q19 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q19 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q19 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q19 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q19 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q19 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q19 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q19 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q19 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q19 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q19 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q19 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q19 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q19 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q19_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q19.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x80000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (1024u) +#define IFLASH_NB_OF_LOCK_BITS (32u) +#define IRAM_SIZE (0x40000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA12D0A00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q19 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q19_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q20.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q20.h new file mode 100644 index 000000000..661e7b118 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q20.h @@ -0,0 +1,693 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q20_ +#define _SAMV71Q20_ + +/** \addtogroup SAMV71Q20_definitions SAMV71Q20 definitions + This file defines all structures and symbols for SAMV71Q20: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q20 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q20 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q20 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q20 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q20 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q20 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q20 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q20 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q20 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q20 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q20 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q20 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q20 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q20 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q20 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q20 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q20 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q20 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q20 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q20 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q20 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q20 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q20 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q20 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q20 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q20 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q20 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q20 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q20 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q20 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q20 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q20 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q20 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q20 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q20 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q20 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q20 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q20 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q20 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q20 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q20 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q20 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q20 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q20 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q20 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q20 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q20 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q20 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q20 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q20 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q20 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q20 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q20 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q20 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q20 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q20 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q20 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q20 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q20 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q20 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q20 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q20 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q20 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q20 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q20 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q20 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q20 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q20 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q20_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q20.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x100000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (2048u) +#define IFLASH_NB_OF_LOCK_BITS (64u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220C00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q20 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q20_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q21.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q21.h new file mode 100644 index 000000000..ba63bb575 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/samv71q21.h @@ -0,0 +1,694 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef _SAMV71Q21_ +#define _SAMV71Q21_ + +/** \addtogroup SAMV71Q21_definitions SAMV71Q21 definitions + This file defines all structures and symbols for SAMV71Q21: + - registers and bit-fields + - peripheral base address + - peripheral ID + - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#endif + +/* ************************************************************************** */ +/* CMSIS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_cmsis CMSIS Definitions */ +/*@{*/ + +/**< Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M7 Processor Exceptions Numbers ******************************/ + NonMaskableInt_IRQn = -14, /**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< 3 HardFault Interrupt */ + MemoryManagement_IRQn = -12, /**< 4 Cortex-M7 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< 5 Cortex-M7 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< 6 Cortex-M7 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 Cortex-M7 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Cortex-M7 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Cortex-M7 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 Cortex-M7 System Tick Interrupt */ +/****** SAMV71Q21 specific Interrupt Numbers *********************************/ + + SUPC_IRQn = 0, /**< 0 SAMV71Q21 Supply Controller (SUPC) */ + RSTC_IRQn = 1, /**< 1 SAMV71Q21 Reset Controller (RSTC) */ + RTC_IRQn = 2, /**< 2 SAMV71Q21 Real Time Clock (RTC) */ + RTT_IRQn = 3, /**< 3 SAMV71Q21 Real Time Timer (RTT) */ + WDT_IRQn = 4, /**< 4 SAMV71Q21 Watchdog Timer (WDT) */ + PMC_IRQn = 5, /**< 5 SAMV71Q21 Power Management Controller (PMC) */ + EFC_IRQn = 6, /**< 6 SAMV71Q21 Enhanced Embedded Flash Controller (EFC) */ + UART0_IRQn = 7, /**< 7 SAMV71Q21 UART 0 (UART0) */ + UART1_IRQn = 8, /**< 8 SAMV71Q21 UART 1 (UART1) */ + PIOA_IRQn = 10, /**< 10 SAMV71Q21 Parallel I/O Controller A (PIOA) */ + PIOB_IRQn = 11, /**< 11 SAMV71Q21 Parallel I/O Controller B (PIOB) */ + PIOC_IRQn = 12, /**< 12 SAMV71Q21 Parallel I/O Controller C (PIOC) */ + USART0_IRQn = 13, /**< 13 SAMV71Q21 USART 0 (USART0) */ + USART1_IRQn = 14, /**< 14 SAMV71Q21 USART 1 (USART1) */ + USART2_IRQn = 15, /**< 15 SAMV71Q21 USART 2 (USART2) */ + PIOD_IRQn = 16, /**< 16 SAMV71Q21 Parallel I/O Controller D (PIOD) */ + PIOE_IRQn = 17, /**< 17 SAMV71Q21 Parallel I/O Controller E (PIOE) */ + HSMCI_IRQn = 18, /**< 18 SAMV71Q21 Multimedia Card Interface (HSMCI) */ + TWIHS0_IRQn = 19, /**< 19 SAMV71Q21 Two Wire Interface 0 HS (TWIHS0) */ + TWIHS1_IRQn = 20, /**< 20 SAMV71Q21 Two Wire Interface 1 HS (TWIHS1) */ + SPI0_IRQn = 21, /**< 21 SAMV71Q21 Serial Peripheral Interface 0 (SPI0) */ + SSC_IRQn = 22, /**< 22 SAMV71Q21 Synchronous Serial Controller (SSC) */ + TC0_IRQn = 23, /**< 23 SAMV71Q21 Timer/Counter 0 (TC0) */ + TC1_IRQn = 24, /**< 24 SAMV71Q21 Timer/Counter 1 (TC1) */ + TC2_IRQn = 25, /**< 25 SAMV71Q21 Timer/Counter 2 (TC2) */ + TC3_IRQn = 26, /**< 26 SAMV71Q21 Timer/Counter 3 (TC3) */ + TC4_IRQn = 27, /**< 27 SAMV71Q21 Timer/Counter 4 (TC4) */ + TC5_IRQn = 28, /**< 28 SAMV71Q21 Timer/Counter 5 (TC5) */ + AFEC0_IRQn = 29, /**< 29 SAMV71Q21 Analog Front End 0 (AFEC0) */ + DACC_IRQn = 30, /**< 30 SAMV71Q21 Digital To Analog Converter (DACC) */ + PWM0_IRQn = 31, /**< 31 SAMV71Q21 Pulse Width Modulation 0 (PWM0) */ + ICM_IRQn = 32, /**< 32 SAMV71Q21 Integrity Check Monitor (ICM) */ + ACC_IRQn = 33, /**< 33 SAMV71Q21 Analog Comparator (ACC) */ + USBHS_IRQn = 34, /**< 34 SAMV71Q21 USB Host / Device Controller (USBHS) */ + MCAN0_IRQn = 35, /**< 35 SAMV71Q21 MCAN Controller 0 (MCAN0) */ + MCAN0_LINE1_IRQn = 36, /**< 36 SAMV71Q21 MCAN Controller 0 LINE1 (MCAN0) */ + MCAN1_IRQn = 37, /**< 37 SAMV71Q21 MCAN Controller 1 (MCAN1) */ + MCAN1_LINE1_IRQn = 38, /**< 38 SAMV71Q21 MCAN Controller 1 LINE1 (MCAN1) */ + GMAC_IRQn = 39, /**< 39 SAMV71Q21 Ethernet MAC (GMAC) */ + AFEC1_IRQn = 40, /**< 40 SAMV71Q21 Analog Front End 1 (AFEC1) */ + TWIHS2_IRQn = 41, /**< 41 SAMV71Q21 Two Wire Interface 2 HS (TWIHS2) */ + SPI1_IRQn = 42, /**< 42 SAMV71Q21 Serial Peripheral Interface 1 (SPI1) */ + QSPI_IRQn = 43, /**< 43 SAMV71Q21 Quad I/O Serial Peripheral Interface (QSPI) */ + UART2_IRQn = 44, /**< 44 SAMV71Q21 UART 2 (UART2) */ + UART3_IRQn = 45, /**< 45 SAMV71Q21 UART 3 (UART3) */ + UART4_IRQn = 46, /**< 46 SAMV71Q21 UART 4 (UART4) */ + TC6_IRQn = 47, /**< 47 SAMV71Q21 Timer/Counter 6 (TC6) */ + TC7_IRQn = 48, /**< 48 SAMV71Q21 Timer/Counter 7 (TC7) */ + TC8_IRQn = 49, /**< 49 SAMV71Q21 Timer/Counter 8 (TC8) */ + TC9_IRQn = 50, /**< 50 SAMV71Q21 Timer/Counter 9 (TC9) */ + TC10_IRQn = 51, /**< 51 SAMV71Q21 Timer/Counter 10 (TC10) */ + TC11_IRQn = 52, /**< 52 SAMV71Q21 Timer/Counter 11 (TC11) */ + MLB_IRQn = 53, /**< 53 SAMV71Q21 MediaLB (MLB) */ + AES_IRQn = 56, /**< 56 SAMV71Q21 AES (AES) */ + TRNG_IRQn = 57, /**< 57 SAMV71Q21 True Random Generator (TRNG) */ + XDMAC_IRQn = 58, /**< 58 SAMV71Q21 DMA (XDMAC) */ + ISI_IRQn = 59, /**< 59 SAMV71Q21 Camera Interface (ISI) */ + PWM1_IRQn = 60, /**< 60 SAMV71Q21 Pulse Width Modulation 1 (PWM1) */ + SDRAMC_IRQn = 62, /**< 62 SAMV71Q21 SDRAM Controller (SDRAMC) */ + RSWDT_IRQn = 63, /**< 63 SAMV71Q21 Reinforced Secure Watchdog Timer (RSWDT) */ + + PERIPH_COUNT_IRQn = 64 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNMI_Handler; + void* pfnHardFault_Handler; + void* pfnMemManage_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pfnReserved1_Handler; + void* pfnReserved2_Handler; + void* pfnReserved3_Handler; + void* pfnReserved4_Handler; + void* pfnSVC_Handler; + void* pfnDebugMon_Handler; + void* pfnReserved5_Handler; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnSUPC_Handler; /* 0 Supply Controller */ + void* pfnRSTC_Handler; /* 1 Reset Controller */ + void* pfnRTC_Handler; /* 2 Real Time Clock */ + void* pfnRTT_Handler; /* 3 Real Time Timer */ + void* pfnWDT_Handler; /* 4 Watchdog Timer */ + void* pfnPMC_Handler; /* 5 Power Management Controller */ + void* pfnEFC_Handler; /* 6 Enhanced Embedded Flash Controller */ + void* pfnUART0_Handler; /* 7 UART 0 */ + void* pfnUART1_Handler; /* 8 UART 1 */ + void* pvReserved9; + void* pfnPIOA_Handler; /* 10 Parallel I/O Controller A */ + void* pfnPIOB_Handler; /* 11 Parallel I/O Controller B */ + void* pfnPIOC_Handler; /* 12 Parallel I/O Controller C */ + void* pfnUSART0_Handler; /* 13 USART 0 */ + void* pfnUSART1_Handler; /* 14 USART 1 */ + void* pfnUSART2_Handler; /* 15 USART 2 */ + void* pfnPIOD_Handler; /* 16 Parallel I/O Controller D */ + void* pfnPIOE_Handler; /* 17 Parallel I/O Controller E */ + void* pfnHSMCI_Handler; /* 18 Multimedia Card Interface */ + void* pfnTWIHS0_Handler; /* 19 Two Wire Interface 0 HS */ + void* pfnTWIHS1_Handler; /* 20 Two Wire Interface 1 HS */ + void* pfnSPI0_Handler; /* 21 Serial Peripheral Interface 0 */ + void* pfnSSC_Handler; /* 22 Synchronous Serial Controller */ + void* pfnTC0_Handler; /* 23 Timer/Counter 0 */ + void* pfnTC1_Handler; /* 24 Timer/Counter 1 */ + void* pfnTC2_Handler; /* 25 Timer/Counter 2 */ + void* pfnTC3_Handler; /* 26 Timer/Counter 3 */ + void* pfnTC4_Handler; /* 27 Timer/Counter 4 */ + void* pfnTC5_Handler; /* 28 Timer/Counter 5 */ + void* pfnAFEC0_Handler; /* 29 Analog Front End 0 */ + void* pfnDACC_Handler; /* 30 Digital To Analog Converter */ + void* pfnPWM0_Handler; /* 31 Pulse Width Modulation 0 */ + void* pfnICM_Handler; /* 32 Integrity Check Monitor */ + void* pfnACC_Handler; /* 33 Analog Comparator */ + void* pfnUSBHS_Handler; /* 34 USB Host / Device Controller */ + void* pfnMCAN0_Handler; /* 35 MCAN Controller 0 */ + void* pfnMCAN0_Line1_Handler; /* 36 MCAN Controller 0 */ + void* pfnMCAN1_Handler; /* 37 MCAN Controller 1 */ + void* pfnMCAN1_Line1_Handler; /* 38 MCAN Controller 1 */ + void* pfnGMAC_Handler; /* 39 Ethernet MAC */ + void* pfnAFEC1_Handler; /* 40 Analog Front End 1 */ + void* pfnTWIHS2_Handler; /* 41 Two Wire Interface 2 HS */ + void* pfnSPI1_Handler; /* 42 Serial Peripheral Interface 1 */ + void* pfnQSPI_Handler; /* 43 Quad I/O Serial Peripheral Interface */ + void* pfnUART2_Handler; /* 44 UART 2 */ + void* pfnUART3_Handler; /* 45 UART 3 */ + void* pfnUART4_Handler; /* 46 UART 4 */ + void* pfnTC6_Handler; /* 47 Timer/Counter 6 */ + void* pfnTC7_Handler; /* 48 Timer/Counter 7 */ + void* pfnTC8_Handler; /* 49 Timer/Counter 8 */ + void* pfnTC9_Handler; /* 50 Timer/Counter 9 */ + void* pfnTC10_Handler; /* 51 Timer/Counter 10 */ + void* pfnTC11_Handler; /* 52 Timer/Counter 11 */ + void* pfnMLB_Handler; /* 53 MediaLB */ + void* pvReserved54; + void* pvReserved55; + void* pfnAES_Handler; /* 56 AES */ + void* pfnTRNG_Handler; /* 57 True Random Generator */ + void* pfnXDMAC_Handler; /* 58 DMA */ + void* pfnISI_Handler; /* 59 Camera Interface */ + void* pfnPWM1_Handler; /* 60 Pulse Width Modulation 1 */ + void* pvReserved61; + void* pfnSDRAMC_Handler; /* 62 SDRAM Controller */ + void* pfnRSWDT_Handler; /* 63 Reinforced Secure Watchdog Timer */ +} DeviceVectors; + +/* Cortex-M7 core handlers */ +void Reset_Handler ( void ); +void NMI_Handler ( void ); +void HardFault_Handler ( void ); +void MemManage_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVC_Handler ( void ); +void DebugMon_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void ACC_Handler ( void ); +void AES_Handler ( void ); +void AFEC0_Handler ( void ); +void AFEC1_Handler ( void ); +void DACC_Handler ( void ); +void EFC_Handler ( void ); +void GMAC_Handler ( void ); +void HSMCI_Handler ( void ); +void ICM_Handler ( void ); +void ISI_Handler ( void ); +void MCAN0_Handler ( void ); +void MCAN0_Line1_Handler ( void ); +void MCAN1_Handler ( void ); +void MCAN1_Line1_Handler ( void ); +void MLB_Handler ( void ); +void PIOA_Handler ( void ); +void PIOB_Handler ( void ); +void PIOC_Handler ( void ); +void PIOD_Handler ( void ); +void PIOE_Handler ( void ); +void PMC_Handler ( void ); +void PWM0_Handler ( void ); +void PWM1_Handler ( void ); +void QSPI_Handler ( void ); +void RSTC_Handler ( void ); +void RSWDT_Handler ( void ); +void RTC_Handler ( void ); +void RTT_Handler ( void ); +void SDRAMC_Handler ( void ); +void SPI0_Handler ( void ); +void SPI1_Handler ( void ); +void SSC_Handler ( void ); +void SUPC_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void TC8_Handler ( void ); +void TC9_Handler ( void ); +void TC10_Handler ( void ); +void TC11_Handler ( void ); +void TRNG_Handler ( void ); +void TWIHS0_Handler ( void ); +void TWIHS1_Handler ( void ); +void TWIHS2_Handler ( void ); +void UART0_Handler ( void ); +void UART1_Handler ( void ); +void UART2_Handler ( void ); +void UART3_Handler ( void ); +void UART4_Handler ( void ); +void USART0_Handler ( void ); +void USART1_Handler ( void ); +void USART2_Handler ( void ); +void USBHS_Handler ( void ); +void WDT_Handler ( void ); +void XDMAC_Handler ( void ); + +/** + * \brief Configuration of the Cortex-M7 Processor and Core Peripherals + */ + +#define __CM7_REV 0x0000 /**< SAMV71Q21 core revision number ([15:8] revision number, [7:0] patch number) */ +#define __MPU_PRESENT 1 /**< SAMV71Q21 does provide a MPU */ +#define __NVIC_PRIO_BITS 3 /**< SAMV71Q21 uses 3 Bits for the Priority Levels */ +#define __FPU_PRESENT 1 /**< SAMV71Q21 does provide a FPU */ +#define __FPU_DP 1 /**< SAMV71Q21 Double precision FPU */ +#define __ICACHE_PRESENT 1 /**< SAMV71Q21 does provide an Instruction Cache */ +#define __DCACHE_PRESENT 1 /**< SAMV71Q21 does provide a Data Cache */ +#define __DTCM_PRESENT 1 /**< SAMV71Q21 does provide a Data TCM */ +#define __ITCM_PRESENT 1 /**< SAMV71Q21 does provide an Instruction TCM */ +#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */ + +/* + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_samv71.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_api Peripheral Software API */ +/*@{*/ + +#include "component/component_acc.h" +#include "component/component_aes.h" +#include "component/component_afec.h" +#include "component/component_chipid.h" +#include "component/component_dacc.h" +#include "component/component_efc.h" +#include "component/component_gmac.h" +#include "component/component_gpbr.h" +#include "component/component_hsmci.h" +#include "component/component_icm.h" +#include "component/component_isi.h" +#include "component/component_matrix.h" +#include "component/component_mcan.h" +#include "component/component_mlb.h" +#include "component/component_pio.h" +#include "component/component_pmc.h" +#include "component/component_pwm.h" +#include "component/component_qspi.h" +#include "component/component_rstc.h" +#include "component/component_rswdt.h" +#include "component/component_rtc.h" +#include "component/component_rtt.h" +#include "component/component_sdramc.h" +#include "component/component_smc.h" +#include "component/component_spi.h" +#include "component/component_ssc.h" +#include "component/component_supc.h" +#include "component/component_tc.h" +#include "component/component_trng.h" +#include "component/component_twihs.h" +#include "component/component_uart.h" +#include "component/component_usart.h" +#include "component/component_usbhs.h" +#include "component/component_utmi.h" +#include "component/component_wdt.h" +#include "component/component_xdmac.h" +/*@}*/ + +/* ************************************************************************** */ +/* REGISTER ACCESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/instance_hsmci.h" +#include "instance/instance_ssc.h" +#include "instance/instance_spi0.h" +#include "instance/instance_tc0.h" +#include "instance/instance_tc1.h" +#include "instance/instance_tc2.h" +#include "instance/instance_twihs0.h" +#include "instance/instance_twihs1.h" +#include "instance/instance_pwm0.h" +#include "instance/instance_usart0.h" +#include "instance/instance_usart1.h" +#include "instance/instance_usart2.h" +#include "instance/instance_mcan0.h" +#include "instance/instance_mcan1.h" +#include "instance/instance_usbhs.h" +#include "instance/instance_afec0.h" +#include "instance/instance_dacc.h" +#include "instance/instance_acc.h" +#include "instance/instance_icm.h" +#include "instance/instance_isi.h" +#include "instance/instance_gmac.h" +#include "instance/instance_tc3.h" +#include "instance/instance_spi1.h" +#include "instance/instance_pwm1.h" +#include "instance/instance_twihs2.h" +#include "instance/instance_afec1.h" +#include "instance/instance_mlb.h" +#include "instance/instance_aes.h" +#include "instance/instance_trng.h" +#include "instance/instance_xdmac.h" +#include "instance/instance_qspi.h" +#include "instance/instance_smc.h" +#include "instance/instance_sdramc.h" +#include "instance/instance_matrix.h" +#include "instance/instance_utmi.h" +#include "instance/instance_pmc.h" +#include "instance/instance_uart0.h" +#include "instance/instance_chipid.h" +#include "instance/instance_uart1.h" +#include "instance/instance_efc.h" +#include "instance/instance_pioa.h" +#include "instance/instance_piob.h" +#include "instance/instance_pioc.h" +#include "instance/instance_piod.h" +#include "instance/instance_pioe.h" +#include "instance/instance_rstc.h" +#include "instance/instance_supc.h" +#include "instance/instance_rtt.h" +#include "instance/instance_wdt.h" +#include "instance/instance_rtc.h" +#include "instance/instance_gpbr.h" +#include "instance/instance_rswdt.h" +#include "instance/instance_uart2.h" +#include "instance/instance_uart3.h" +#include "instance/instance_uart4.h" +/*@}*/ + +/* ************************************************************************** */ +/* PERIPHERAL ID DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_id Peripheral Ids Definitions */ +/*@{*/ + +#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */ +#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */ +#define ID_RTC ( 2) /**< \brief Real Time Clock (RTC) */ +#define ID_RTT ( 3) /**< \brief Real Time Timer (RTT) */ +#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */ +#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */ +#define ID_EFC ( 6) /**< \brief Enhanced Embedded Flash Controller (EFC) */ +#define ID_UART0 ( 7) /**< \brief UART 0 (UART0) */ +#define ID_UART1 ( 8) /**< \brief UART 1 (UART1) */ +#define ID_SMC ( 9) /**< \brief Static Memory Controller (SMC) */ +#define ID_PIOA (10) /**< \brief Parallel I/O Controller A (PIOA) */ +#define ID_PIOB (11) /**< \brief Parallel I/O Controller B (PIOB) */ +#define ID_PIOC (12) /**< \brief Parallel I/O Controller C (PIOC) */ +#define ID_USART0 (13) /**< \brief USART 0 (USART0) */ +#define ID_USART1 (14) /**< \brief USART 1 (USART1) */ +#define ID_USART2 (15) /**< \brief USART 2 (USART2) */ +#define ID_PIOD (16) /**< \brief Parallel I/O Controller D (PIOD) */ +#define ID_PIOE (17) /**< \brief Parallel I/O Controller E (PIOE) */ +#define ID_HSMCI (18) /**< \brief Multimedia Card Interface (HSMCI) */ +#define ID_TWIHS0 (19) /**< \brief Two Wire Interface 0 HS (TWIHS0) */ +#define ID_TWIHS1 (20) /**< \brief Two Wire Interface 1 HS (TWIHS1) */ +#define ID_SPI0 (21) /**< \brief Serial Peripheral Interface 0 (SPI0) */ +#define ID_SSC (22) /**< \brief Synchronous Serial Controller (SSC) */ +#define ID_TC0 (23) /**< \brief Timer/Counter 0 (TC0) */ +#define ID_TC1 (24) /**< \brief Timer/Counter 1 (TC1) */ +#define ID_TC2 (25) /**< \brief Timer/Counter 2 (TC2) */ +#define ID_TC3 (26) /**< \brief Timer/Counter 3 (TC3) */ +#define ID_TC4 (27) /**< \brief Timer/Counter 4 (TC4) */ +#define ID_TC5 (28) /**< \brief Timer/Counter 5 (TC5) */ +#define ID_AFEC0 (29) /**< \brief Analog Front End 0 (AFEC0) */ +#define ID_DACC (30) /**< \brief Digital To Analog Converter (DACC) */ +#define ID_PWM0 (31) /**< \brief Pulse Width Modulation 0 (PWM0) */ +#define ID_ICM (32) /**< \brief Integrity Check Monitor (ICM) */ +#define ID_ACC (33) /**< \brief Analog Comparator (ACC) */ +#define ID_USBHS (34) /**< \brief USB Host / Device Controller (USBHS) */ +#define ID_MCAN0 (35) /**< \brief MCAN Controller 0 (MCAN0) */ +#define ID_MCAN1 (37) /**< \brief MCAN Controller 1 (MCAN1) */ +#define ID_GMAC (39) /**< \brief Ethernet MAC (GMAC) */ +#define ID_AFEC1 (40) /**< \brief Analog Front End 1 (AFEC1) */ +#define ID_TWIHS2 (41) /**< \brief Two Wire Interface 2 HS (TWIHS2) */ +#define ID_SPI1 (42) /**< \brief Serial Peripheral Interface 1 (SPI1) */ +#define ID_QSPI (43) /**< \brief Quad I/O Serial Peripheral Interface (QSPI) */ +#define ID_UART2 (44) /**< \brief UART 2 (UART2) */ +#define ID_UART3 (45) /**< \brief UART 3 (UART3) */ +#define ID_UART4 (46) /**< \brief UART 4 (UART4) */ +#define ID_TC6 (47) /**< \brief Timer/Counter 6 (TC6) */ +#define ID_TC7 (48) /**< \brief Timer/Counter 7 (TC7) */ +#define ID_TC8 (49) /**< \brief Timer/Counter 8 (TC8) */ +#define ID_TC9 (50) /**< \brief Timer/Counter 9 (TC9) */ +#define ID_TC10 (51) /**< \brief Timer/Counter 10 (TC10) */ +#define ID_TC11 (52) /**< \brief Timer/Counter 11 (TC11) */ +#define ID_MLB (53) /**< \brief MediaLB (MLB) */ +#define ID_AES (56) /**< \brief AES (AES) */ +#define ID_TRNG (57) /**< \brief True Random Generator (TRNG) */ +#define ID_XDMAC (58) /**< \brief DMA (XDMAC) */ +#define ID_ISI (59) /**< \brief Camera Interface (ISI) */ +#define ID_PWM1 (60) /**< \brief Pulse Width Modulation 1 (PWM1) */ +#define ID_SDRAMC (62) /**< \brief SDRAM Controller (SDRAMC) */ +#define ID_RSWDT (63) /**< \brief Reinforced Secure Watchdog Timer (RSWDT) */ + +#define ID_PERIPH_COUNT (64) /**< \brief Number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/* BASE ADDRESS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_base Peripheral Base Address Definitions */ +/*@{*/ + +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define HSMCI (0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC (0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 (0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 (0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 (0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 (0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 (0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 (0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 (0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 (0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 (0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 (0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 (0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 (0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS (0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 (0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC (0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC (0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM (0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI (0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC (0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 (0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 (0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 (0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 (0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 (0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB (0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES (0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG (0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC (0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI (0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC (0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC (0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX (0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI (0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC (0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 (0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID (0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 (0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC (0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA (0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB (0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC (0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD (0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE (0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC (0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC (0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT (0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT (0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC (0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR (0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT (0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 (0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 (0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 (0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#else +#define HSMCI ((Hsmci *)0x40000000U) /**< \brief (HSMCI ) Base Address */ +#define SSC ((Ssc *)0x40004000U) /**< \brief (SSC ) Base Address */ +#define SPI0 ((Spi *)0x40008000U) /**< \brief (SPI0 ) Base Address */ +#define TC0 ((Tc *)0x4000C000U) /**< \brief (TC0 ) Base Address */ +#define TC1 ((Tc *)0x40010000U) /**< \brief (TC1 ) Base Address */ +#define TC2 ((Tc *)0x40014000U) /**< \brief (TC2 ) Base Address */ +#define TWIHS0 ((Twihs *)0x40018000U) /**< \brief (TWIHS0) Base Address */ +#define TWIHS1 ((Twihs *)0x4001C000U) /**< \brief (TWIHS1) Base Address */ +#define PWM0 ((Pwm *)0x40020000U) /**< \brief (PWM0 ) Base Address */ +#define USART0 ((Usart *)0x40024000U) /**< \brief (USART0) Base Address */ +#define USART1 ((Usart *)0x40028000U) /**< \brief (USART1) Base Address */ +#define USART2 ((Usart *)0x4002C000U) /**< \brief (USART2) Base Address */ +#define MCAN0 ((Mcan *)0x40030000U) /**< \brief (MCAN0 ) Base Address */ +#define MCAN1 ((Mcan *)0x40034000U) /**< \brief (MCAN1 ) Base Address */ +#define USBHS ((Usbhs *)0x40038000U) /**< \brief (USBHS ) Base Address */ +#define AFEC0 ((Afec *)0x4003C000U) /**< \brief (AFEC0 ) Base Address */ +#define DACC ((Dacc *)0x40040000U) /**< \brief (DACC ) Base Address */ +#define ACC ((Acc *)0x40044000U) /**< \brief (ACC ) Base Address */ +#define ICM ((Icm *)0x40048000U) /**< \brief (ICM ) Base Address */ +#define ISI ((Isi *)0x4004C000U) /**< \brief (ISI ) Base Address */ +#define GMAC ((Gmac *)0x40050000U) /**< \brief (GMAC ) Base Address */ +#define TC3 ((Tc *)0x40054000U) /**< \brief (TC3 ) Base Address */ +#define SPI1 ((Spi *)0x40058000U) /**< \brief (SPI1 ) Base Address */ +#define PWM1 ((Pwm *)0x4005C000U) /**< \brief (PWM1 ) Base Address */ +#define TWIHS2 ((Twihs *)0x40060000U) /**< \brief (TWIHS2) Base Address */ +#define AFEC1 ((Afec *)0x40064000U) /**< \brief (AFEC1 ) Base Address */ +#define MLB ((Mlb *)0x40068000U) /**< \brief (MLB ) Base Address */ +#define AES ((Aes *)0x4006C000U) /**< \brief (AES ) Base Address */ +#define TRNG ((Trng *)0x40070000U) /**< \brief (TRNG ) Base Address */ +#define XDMAC ((Xdmac *)0x40078000U) /**< \brief (XDMAC ) Base Address */ +#define QSPI ((Qspi *)0x4007C000U) /**< \brief (QSPI ) Base Address */ +#define SMC ((Smc *)0x40080000U) /**< \brief (SMC ) Base Address */ +#define SDRAMC ((Sdramc *)0x40084000U) /**< \brief (SDRAMC) Base Address */ +#define MATRIX ((Matrix *)0x40088000U) /**< \brief (MATRIX) Base Address */ +#define UTMI ((Utmi *)0x400E0400U) /**< \brief (UTMI ) Base Address */ +#define PMC ((Pmc *)0x400E0600U) /**< \brief (PMC ) Base Address */ +#define UART0 ((Uart *)0x400E0800U) /**< \brief (UART0 ) Base Address */ +#define CHIPID ((Chipid *)0x400E0940U) /**< \brief (CHIPID) Base Address */ +#define UART1 ((Uart *)0x400E0A00U) /**< \brief (UART1 ) Base Address */ +#define EFC ((Efc *)0x400E0C00U) /**< \brief (EFC ) Base Address */ +#define PIOA ((Pio *)0x400E0E00U) /**< \brief (PIOA ) Base Address */ +#define PIOB ((Pio *)0x400E1000U) /**< \brief (PIOB ) Base Address */ +#define PIOC ((Pio *)0x400E1200U) /**< \brief (PIOC ) Base Address */ +#define PIOD ((Pio *)0x400E1400U) /**< \brief (PIOD ) Base Address */ +#define PIOE ((Pio *)0x400E1600U) /**< \brief (PIOE ) Base Address */ +#define RSTC ((Rstc *)0x400E1800U) /**< \brief (RSTC ) Base Address */ +#define SUPC ((Supc *)0x400E1810U) /**< \brief (SUPC ) Base Address */ +#define RTT ((Rtt *)0x400E1830U) /**< \brief (RTT ) Base Address */ +#define WDT ((Wdt *)0x400E1850U) /**< \brief (WDT ) Base Address */ +#define RTC ((Rtc *)0x400E1860U) /**< \brief (RTC ) Base Address */ +#define GPBR ((Gpbr *)0x400E1890U) /**< \brief (GPBR ) Base Address */ +#define RSWDT ((Rswdt *)0x400E1900U) /**< \brief (RSWDT ) Base Address */ +#define UART2 ((Uart *)0x400E1A00U) /**< \brief (UART2 ) Base Address */ +#define UART3 ((Uart *)0x400E1C00U) /**< \brief (UART3 ) Base Address */ +#define UART4 ((Uart *)0x400E1E00U) /**< \brief (UART4 ) Base Address */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/* PIO DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ +/** \addtogroup SAMV71Q21_pio Peripheral Pio Definitions */ +/*@{*/ + +#include "pio/pio_samv71q21.h" +/*@}*/ + +/* ************************************************************************** */ +/* MEMORY MAPPING DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define IFLASH_SIZE (0x200000u) +#define IFLASH_PAGE_SIZE (512u) +#define IFLASH_LOCK_REGION_SIZE (16384u) +#define IFLASH_NB_OF_PAGES (4096u) +#define IFLASH_NB_OF_LOCK_BITS (128u) +#define IRAM_SIZE (0x60000u) + +#define QSPIMEM_ADDR (0x80000000u) /**< QSPI Memory base address */ +#define AXIMX_ADDR (0xA0000000u) /**< AXI Bus Matrix base address */ +#define ITCM_ADDR (0x00000000u) /**< Instruction Tightly Coupled Memory base address */ +#define IFLASH_ADDR (0x00400000u) /**< Internal Flash base address */ +#define IROM_ADDR (0x00800000u) /**< Internal ROM base address */ +#define DTCM_ADDR (0x20000000u) /**< Data Tightly Coupled Memory base address */ +#define IRAM_ADDR (0x20400000u) /**< Internal RAM base address */ +#define EBI_CS0_ADDR (0x60000000u) /**< EBI Chip Select 0 base address */ +#define EBI_CS1_ADDR (0x61000000u) /**< EBI Chip Select 1 base address */ +#define EBI_CS2_ADDR (0x62000000u) /**< EBI Chip Select 2 base address */ +#define EBI_CS3_ADDR (0x63000000u) /**< EBI Chip Select 3 base address */ +#define SDRAM_CS_ADDR (0x70000000u) /**< SDRAM Chip Select base address */ +#define USBHS_RAM_ADDR (0xA0100000u)/**< USB RAM base address */ + +/* ************************************************************************** */ +/* MISCELLANEOUS DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +#define CHIP_JTAGID (0x05B3D03FUL) +#define CHIP_CIDR (0xA1220E00UL) +#define CHIP_EXID (0x00000002UL) + +/* ************************************************************************** */ +/* ELECTRICAL DEFINITIONS FOR SAMV71Q21 */ +/* ************************************************************************** */ + +/* %ATMEL_ELECTRICAL% */ + +/* Device characteristics */ +#define CHIP_FREQ_SLCK_RC_MIN (20000UL) +#define CHIP_FREQ_SLCK_RC (32000UL) +#define CHIP_FREQ_SLCK_RC_MAX (44000UL) +#define CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) +#define CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) +#define CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) +#define CHIP_FREQ_CPU_MAX (300000000UL) +#define CHIP_FREQ_XTAL_32K (32768UL) +#define CHIP_FREQ_XTAL_12M (12000000UL) + +/* Embedded Flash Read Wait State (VDDCORE set at 1.20V) */ +#define CHIP_FREQ_FWS_0 (26000000UL) /**< \brief Maximum operating frequency when FWS is 0 */ +#define CHIP_FREQ_FWS_1 (52000000UL) /**< \brief Maximum operating frequency when FWS is 1 */ +#define CHIP_FREQ_FWS_2 (78000000UL) /**< \brief Maximum operating frequency when FWS is 2 */ +#define CHIP_FREQ_FWS_3 (104000000UL) /**< \brief Maximum operating frequency when FWS is 3 */ +#define CHIP_FREQ_FWS_4 (131000000UL) /**< \brief Maximum operating frequency when FWS is 4 */ +#define CHIP_FREQ_FWS_5 (150000000UL) /**< \brief Maximum operating frequency when FWS is 5 */ + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* _SAMV71Q21_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/system_samv71.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/system_samv71.h new file mode 100644 index 000000000..ed4fa0163 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/samv7/system_samv71.h @@ -0,0 +1,73 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +#ifndef SYSTEM_SAMV71_H_INCLUDED +#define SYSTEM_SAMV71_H_INCLUDED + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +extern "C" { +#endif +/**INDENT-ON**/ +/* @endcond */ + +#include + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/** + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/** + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +/** + * Initialize flash. + */ +void system_init_flash(uint32_t dw_clk); + +void sysclk_enable_usb(void); +void sysclk_disable_usb(void); + +/* @cond 0 */ +/**INDENT-OFF**/ +#ifdef __cplusplus +} +#endif +/**INDENT-ON**/ +/* @endcond */ + +#endif /* SYSTEM_SAMV71_H_INCLUDED */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/sdramc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/sdramc.h new file mode 100644 index 000000000..2d25daf01 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/sdramc.h @@ -0,0 +1,70 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Definitions and function prototype for SDRAMC. + */ + +// --------------------------------------------------------------------------- +// SDRAM +// --------------------------------------------------------------------------- +/** SDRAMC Configuration */ +#define EBI_SDRAMC_ADDR (0x70000000u) + +/** SDRAM bus width */ +#define BOARD_SDRAM_BUSWIDTH 16 + + +typedef struct _SSdramc_config +{ + uint32_t dwColumnBits ; // Number of Column Bits + uint32_t dwRowBits ; // Number of Row Bits + uint32_t dwBanks ; // Number of Banks + uint32_t dwCAS ; // CAS Latency + uint32_t dwDataBusWidth ; // Data Bus Width + uint32_t dwWriteRecoveryDelay ; // Write Recovery Delay + uint32_t dwRowCycleDelay_RowRefreshCycle ; // Row Cycle Delay and Row Refresh Cycle + uint32_t dwRowPrechargeDelay ; // Row Precharge Delay + uint32_t dwRowColumnDelay ; // Row to Column Delay + uint32_t dwActivePrechargeDelay ; // Active to Precharge Delay + uint32_t dwExitSelfRefreshActiveDelay ; // Exit Self Refresh to Active Delay + uint32_t dwBK1 ; // bk1 addr + +} SSdramc_config ; + +typedef struct _SSdramc_Memory +{ + SSdramc_config cfg ; + +} SSdramc_Memory ; + +extern void SDRAMC_Configure( SSdramc_Memory* pMemory, + uint32_t dwClockFrequency ) ; diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/smc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/smc.h new file mode 100644 index 000000000..ca7e53abe --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/smc.h @@ -0,0 +1,174 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** +* \file +* +* Definitions and function prototype for SMC module +*/ + +#ifndef _SMC_ +#define _SMC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +typedef union _SmcStatus { + uint8_t BStatus; + struct _SmcStatusBits { + uint8_t smcSts:1, /**< NAND Flash Controller Status */ + xfrDone:1, /**< NFC Data Transfer Terminated */ + cmdDone:1, /**< Command Done */ + rbEdge: 1, /**< Ready/Busy Line 3 Edge Detected*/ + hammingReady:1; /**< Hamming ecc ready */ + } bStatus; +} SmcStatus; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/* + * NFC definitions + */ + +/** Base address of NFC SRAM */ +#define NFC_SRAM_BASE_ADDRESS 0x200000 +/** Base address for NFC Address Command */ +#define NFC_CMD_BASE_ADDR 0x70000000 + + +/* -------- NFCADDR_CMD : NFC Address Command -------- */ +#define NFCADDR_CMD_CMD1 (0xFFu << 2) +/* Command Register Value for Cycle 1 */ +#define NFCADDR_CMD_CMD2 (0xFFu << 10) +/* Command Register Value for Cycle 2 */ +#define NFCADDR_CMD_VCMD2 (0x1u << 18) +/* Valid Cycle 2 Command */ +#define NFCADDR_CMD_ACYCLE (0x7u << 19) +/* Number of Address required for the current command */ +#define NFCADDR_CMD_ACYCLE_NONE (0x0u << 19) +/* No address cycle */ +#define NFCADDR_CMD_ACYCLE_ONE (0x1u << 19) +/* One address cycle */ +#define NFCADDR_CMD_ACYCLE_TWO (0x2u << 19) +/* Two address cycles */ +#define NFCADDR_CMD_ACYCLE_THREE (0x3u << 19) +/* Three address cycles */ +#define NFCADDR_CMD_ACYCLE_FOUR (0x4u << 19) +/* Four address cycles */ +#define NFCADDR_CMD_ACYCLE_FIVE (0x5u << 19) +/* Five address cycles */ +#define NFCADDR_CMD_CSID (0x7u << 22) +/* Chip Select Identifier */ +#define NFCADDR_CMD_CSID_0 (0x0u << 22) +/* CS0 */ +#define NFCADDR_CMD_CSID_1 (0x1u << 22) +/* CS1 */ +#define NFCADDR_CMD_CSID_2 (0x2u << 22) +/* CS2 */ +#define NFCADDR_CMD_CSID_3 (0x3u << 22) +/* CS3 */ +#define NFCADDR_CMD_CSID_4 (0x4u << 22) +/* CS4 */ +#define NFCADDR_CMD_CSID_5 (0x5u << 22) +/* CS5 */ +#define NFCADDR_CMD_CSID_6 (0x6u << 22) +/* CS6 */ +#define NFCADDR_CMD_CSID_7 (0x7u << 22) +/* CS7 */ +#define NFCADDR_CMD_DATAEN (0x1u << 25) +/* NFC Data Enable */ +#define NFCADDR_CMD_DATADIS (0x0u << 25) +/* NFC Data disable */ +#define NFCADDR_CMD_NFCRD (0x0u << 26) +/* NFC Read Enable */ +#define NFCADDR_CMD_NFCWR (0x1u << 26) +/* NFC Write Enable */ +#define NFCADDR_CMD_NFCCMD (0x1u << 27) +/* NFC Command Enable */ + +/* + * ECC definitions (Hsiao Code Errors) + */ + +/** A single bit was incorrect but has been recovered. */ +#define Hsiao_ERROR_SINGLEBIT 1 + +/** The original code has been corrupted. */ +#define Hsiao_ERROR_ECC 2 + +/** Multiple bits are incorrect in the data and they cannot be corrected. */ +#define Hsiao_ERROR_MULTIPLEBITS 3 + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/* + * NFC functions + */ + +extern void SMC_NFC_Configure(uint32_t mode); +extern void SMC_NFC_Reset(void); +extern void SMC_NFC_EnableNfc(void); +extern void SMC_NFC_EnableSpareRead(void); +extern void SMC_NFC_DisableSpareRead(void); +extern void SMC_NFC_EnableSpareWrite(void); +extern void SMC_NFC_DisableSpareWrite(void); +extern uint8_t SMC_NFC_isSpareRead(void); +extern uint8_t SMC_NFC_isSpareWrite(void); +extern uint8_t SMC_NFC_isTransferComplete(void); +extern uint8_t SMC_NFC_isReadyBusy(void); +extern uint8_t SMC_NFC_isNfcBusy(void); +extern uint32_t SMC_NFC_GetStatus(void); + +extern void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, + uint32_t cycle0); +extern void SMC_NFC_Wait_CommandDone(void); +extern void SMC_NFC_Wait_XfrDone(void); +extern void SMC_NFC_Wait_RBbusy(void); +extern void SMC_NFC_Wait_HammingReady(void); + +extern void SMC_ECC_Configure(uint32_t type, uint32_t pageSize); +extern uint32_t SMC_ECC_GetCorrectoinType(void); +extern uint8_t SMC_ECC_GetStatus(uint8_t eccNumber); + +extern void SMC_ECC_GetValue(uint32_t *ecc); +extern void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, + uint8_t busWidth); +extern uint8_t SMC_ECC_VerifyHsiao(uint8_t *data, uint32_t size, + const uint8_t *originalCode, const uint8_t *verifyCode, uint8_t busWidth); + +#endif /* #ifndef _SMC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/spi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/spi.h new file mode 100644 index 000000000..30a9b9ea3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/spi.h @@ -0,0 +1,114 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Serial Peripheral Interface (SPI) controller. + * + */ + +#ifndef _SPI_ +#define _SPI_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** + * + * Here are several macros which should be used when configuring a SPI + * peripheral. + * + * \section spi_configuration_macros SPI Configuration Macros + * - \ref SPI_PCS + * - \ref SPI_SCBR + * - \ref SPI_DLYBS + * - \ref SPI_DLYBCT + */ + +/** Calculate the PCS field value given the chip select NPCS value */ +#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF)) + +/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */ +#define SPI_SCBR(baudrate, masterClock) \ + SPI_CSR_SCBR((uint32_t)(masterClock / baudrate)) + +/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */ +#define SPI_DLYBS(delay, masterClock) \ + SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1) + +/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */ +#define SPI_DLYBCT(delay, masterClock) \ + SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1) + +/*------------------------------------------------------------------------------ */ + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void SPI_Enable( Spi* spi ) ; +extern void SPI_Disable( Spi* spi ) ; + +extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) ; +extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) ; + +extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) ; +extern void SPI_SetMode( Spi* spi, uint32_t dwConfiguration ); + +extern void SPI_ChipSelect( Spi* spi, uint8_t cS); +extern void SPI_ReleaseCS( Spi* spi ); + +extern void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) ; +extern void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast ); + +extern uint32_t SPI_Read( Spi* spi ) ; +extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) ; +extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData ); + +extern uint32_t SPI_GetStatus( Spi* spi ) ; +extern uint32_t SPI_IsFinished( Spi* pSpi ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/spi_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/spi_dma.h new file mode 100644 index 000000000..2f30b9d81 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/spi_dma.h @@ -0,0 +1,148 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of SPI driver, transfer data through DMA. + * + */ + +#ifndef _SPI_DMA_ +#define _SPI_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define SPID_ERROR 1 + +/** SPI driver is currently in use.*/ +#define SPID_ERROR_LOCK 2 + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/** Calculates the value of the SCBR field of the Chip Select Register + given MCK and SPCK.*/ +#define SPID_CSR_SCBR(mck, spck) SPI_CSR_SCBR((mck) / (spck)) + +/** Calculates the value of the DLYBS field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBS(mck, delay) SPI_CSR_DLYBS((((delay) * \ + ((mck) / 1000000)) / 1000) + 1) + +/** Calculates the value of the DLYBCT field of the Chip Select Register + given delay in ns and MCK.*/ +#define SPID_CSR_DLYBCT(mck, delay) SPI_CSR_DLYBCT((((delay) / 32 * \ + ((mck) / 1000000)) / 1000) + 1) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** SPI transfer complete callback. */ +typedef void (*SpidCallback)( uint8_t, void* ) ; + +/** \brief Spi Transfer Request prepared by the application upper layer. + * + * This structure is sent to the SPI_SendCommand function to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct _SpidCmd +{ + /** Pointer to the Tx data. */ + uint8_t *pTxBuff; + /** Tx size in bytes. */ + uint8_t TxSize; + /** Pointer to the Rx data. */ + uint8_t *pRxBuff; + /** Rx size in bytes. */ + uint16_t RxSize; + /** SPI chip select. */ + uint8_t spiCs; + /** Callback function invoked at the end of transfer. */ + SpidCallback callback; + /** Callback arguments. */ + void *pArgument; +} SpidCmd ; + +/** Constant structure associated with SPI port. This structure prevents + client applications to have access in the same time. */ +typedef struct _Spid +{ + /** Pointer to SPI Hardware registers */ + Spi* pSpiHw ; + /** Current SpiCommand being processed */ + SpidCmd *pCurrentCommand ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** SPI Id as defined in the product datasheet */ + uint8_t spiId ; + /** Mutual exclusion semaphore. */ + volatile int8_t semaphore ; +} Spid ; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint32_t SPID_Configure( Spid* pSpid, + Spi* pSpiHw, + uint8_t spiId, + uint32_t SpiMode, + sXdmad* pXdmad ) ; + +extern void SPID_ConfigureCS( Spid* pSpid, uint32_t dwCS, uint32_t dwCsr ) ; + +extern uint32_t SPID_SendCommand( Spid* pSpid, SpidCmd* pCommand ) ; + +extern void SPID_Handler( Spid* pSpid ) ; + +extern void SPID_DmaHandler( Spid *pSpid ); + +extern uint32_t SPID_IsBusy( const Spid* pSpid ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SPI_DMA_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/ssc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/ssc.h new file mode 100644 index 000000000..fb66189c8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/ssc.h @@ -0,0 +1,72 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for Synchronous Serial (SSC) controller. + * + */ + +#ifndef _SSC_ +#define _SSC_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock); +extern void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr); +extern void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr); +extern void SSC_EnableTransmitter(Ssc *ssc); +extern void SSC_DisableTransmitter(Ssc *ssc); +extern void SSC_EnableReceiver(Ssc *ssc); +extern void SSC_DisableReceiver(Ssc *ssc ); +extern void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources); +extern void SSC_Write(Ssc *ssc, uint32_t frame); +extern uint32_t SSC_Read(Ssc *ssc ); +extern uint8_t SSC_IsRxReady(Ssc *ssc); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _SSC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/supc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/supc.h new file mode 100644 index 000000000..0430ffc8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/supc.h @@ -0,0 +1,75 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _SUPC_H_ +#define _SUPC_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include + + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + + + +void SUPC_SelectExtCrystal32K(void); +uint8_t SUPC_IsSlowClkExtCrystal32K(void); +uint8_t SUPC_Read_Status(uint32_t status); +void SUPC_DisableSupplyMonitor(void); +void SUPC_DisableVoltageReg(void); +void SUPC_ConfigSupplyMonitor(uint32_t Config); +void SUPC_BrownoutDetectEnable(uint8_t enable); +void SUPC_BrownoutResetEnable(void); +void SUPC_SramBackupMode(uint8_t enable); +void SUPC_BypassXtal32KOsc(void); +void SUPC_EnablesWakeupInput(uint32_t Input, uint8_t enable); +void SUPC_SetLowPowerDebounce(uint8_t period); +void SUPC_SetWakeupDebounce(uint8_t period); +void SUPC_EnablesWakeupMode(uint32_t Regs, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _PMC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/tc.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/tc.h new file mode 100644 index 000000000..7b874756b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/tc.h @@ -0,0 +1,77 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +#ifndef _TC_ +#define _TC_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + extern "C" { +#endif + +extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) ; + +extern void TC_Start( Tc *pTc, uint32_t dwChannel ) ; + +extern void TC_Stop( Tc *pTc, uint32_t dwChannel ) ; + +extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, + uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TC_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/timetick.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/timetick.h new file mode 100644 index 000000000..87f3674ad --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/timetick.h @@ -0,0 +1,103 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Methods and definitions for Global time tick and wait functions. + * + * Defines a common and simplest use of Time Tick, to increase tickCount + * every 1ms, the application can get this value through GetTickCount(). + * + * \par Usage + * + * -# Configure the System Tick with TimeTick_Configure() when MCK changed + * \note + * Must be done before any invoke of GetTickCount(), Wait() or Sleep(). + * -# Uses GetTickCount to get current tick value. + * -# Uses Wait to wait several ms. + * -# Uses Sleep to enter wait for interrupt mode to wait several ms. + * + */ + +#ifndef _TIMETICK_ +#define _TIMETICK_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +typedef struct +{ + volatile uint32_t *pTimer1; + volatile uint32_t *pTimer2; + volatile uint32_t *pTimer3; + volatile uint32_t *pTimer4; +}SyTickDelayCounter_t; + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +typedef struct _TimeEvent +{ + uint32_t event; + uint32_t time_tick; + uint32_t time_start; + uint32_t occur; + struct _TimeEvent *pPreEvent; + struct _TimeEvent *pNextEvent; +}TimeEvent; + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +uint32_t TimeTick_Configure( void ) ; + +void TimeTick_Increment( uint32_t dwInc ) ; + +uint32_t GetDelayInTicks(uint32_t startTick,uint32_t endTick); + +uint32_t GetTicks(void); + +void Wait( volatile uint32_t dwMs ) ; + +void Sleep( volatile uint32_t dwMs ) ; + +extern void SetTimeEvent(TimeEvent* pEvent); + +#endif /* _TIMETICK_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/trace.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/trace.h new file mode 100644 index 000000000..3d387fb57 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/trace.h @@ -0,0 +1,230 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * Standard output methods for reporting debug information, warnings and + * errors, which can be easily be turned on/off. + * + * \par Usage + * -# Initialize the DBGU using TRACE_CONFIGURE() if you intend to eventually + * disable ALL traces; otherwise use DBGU_Configure(). + * -# Uses the TRACE_DEBUG(), TRACE_INFO(), TRACE_WARNING(), TRACE_ERROR() + * TRACE_FATAL() macros to output traces throughout the program. + * -# Each type of trace has a level : Debug 5, Info 4, Warning 3, Error 2 + * and Fatal 1. Disable a group of traces by changing the value of + * TRACE_LEVEL during compilation; traces with a level bigger than TRACE_LEVEL + * are not generated. To generate no trace, use the reserved value 0. + * -# Trace disabling can be static or dynamic. If dynamic disabling is selected + * the trace level can be modified in runtime. If static disabling is selected + * the disabled traces are not compiled. + * + * \par traceLevels Trace level description + * -# TRACE_DEBUG (5): Traces whose only purpose is for debugging the program, + * and which do not produce meaningful information otherwise. + * -# TRACE_INFO (4): Informational trace about the program execution. Should + * enable the user to see the execution flow. + * -# TRACE_WARNING (3): Indicates that a minor error has happened. In most case + * it can be discarded safely; it may even be expected. + * -# TRACE_ERROR (2): Indicates an error which may not stop the program execution, + * but which indicates there is a problem with the code. + * -# TRACE_FATAL (1): Indicates a major error which prevents the program from going + * any further. + */ + +#ifndef _TRACE_ +#define _TRACE_ + +/* + * Headers + */ + +#include "pio.h" + +#include + +/* + * Global Definitions + */ + +/** Softpack Version */ +#define SOFTPACK_VERSION "1.2" + +#define TRACE_LEVEL_DEBUG 5 +#define TRACE_LEVEL_INFO 4 +#define TRACE_LEVEL_WARNING 3 +#define TRACE_LEVEL_ERROR 2 +#define TRACE_LEVEL_FATAL 1 +#define TRACE_LEVEL_NO_TRACE 0 + +/* By default, all traces are output except the debug one. */ +#if !defined(TRACE_LEVEL) +#define TRACE_LEVEL TRACE_LEVEL_INFO +#endif + +/* By default, trace level is static (not dynamic) */ +#if !defined(DYN_TRACES) +#define DYN_TRACES 0 +#endif + +#if defined(NOTRACE) +#error "Error: NOTRACE has to be not defined !" +#endif + +#undef NOTRACE +#if (DYN_TRACES==0) + #if (TRACE_LEVEL == TRACE_LEVEL_NO_TRACE) + #define NOTRACE + #endif +#endif + + + +/* ------------------------------------------------------------------------------ + * Global Macros + * ------------------------------------------------------------------------------ + */ + +extern void TRACE_CONFIGURE( uint32_t dwBaudRate, uint32_t dwMCk ) ; + +/** + * Initializes the DBGU for ISP project + * + * \param mode DBGU mode. + * \param baudrate DBGU baudrate. + * \param mck Master clock frequency. + */ +#ifndef DYNTRACE +#define DYNTRACE 0 +#endif + +#if (TRACE_LEVEL==0) && (DYNTRACE==0) +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) {} +#else +#define TRACE_CONFIGURE_ISP(mode, baudrate, mck) { \ + const Pin pinsUART0[] = {PINS_UART}; \ + PIO_Configure(pinsUART0, PIO_LISTSIZE(pinsUART0)); \ + UART_Configure( baudrate, mck ) ; \ + } +#endif + +/** + * Outputs a formatted string using 'printf' if the log level is high + * enough. Can be disabled by defining TRACE_LEVEL=0 during compilation. + * \param ... Additional parameters depending on formatted string. + */ +#if defined(NOTRACE) + +/* Empty macro */ +#define TRACE_DEBUG(...) { } +#define TRACE_INFO(...) { } +#define TRACE_WARNING(...) { } +#define TRACE_ERROR(...) { } +#define TRACE_FATAL(...) { while(1); } + +#define TRACE_DEBUG_WP(...) { } +#define TRACE_INFO_WP(...) { } +#define TRACE_WARNING_WP(...) { } +#define TRACE_ERROR_WP(...) { } +#define TRACE_FATAL_WP(...) { while(1); } + +#elif (DYN_TRACES == 1) + +/* Trace output depends on dwTraceLevel value */ +#define TRACE_DEBUG(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf("-D- " __VA_ARGS__); } } +#define TRACE_INFO(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf("-I- " __VA_ARGS__); } } +#define TRACE_WARNING(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf("-W- " __VA_ARGS__); } } +#define TRACE_ERROR(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf("-E- " __VA_ARGS__); } } +#define TRACE_FATAL(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf("-F- " __VA_ARGS__); while(1); } } + +#define TRACE_DEBUG_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_DEBUG) { printf(__VA_ARGS__); } } +#define TRACE_INFO_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_INFO) { printf(__VA_ARGS__); } } +#define TRACE_WARNING_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_WARNING) { printf(__VA_ARGS__); } } +#define TRACE_ERROR_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_ERROR) { printf(__VA_ARGS__); } } +#define TRACE_FATAL_WP(...) { if (dwTraceLevel >= TRACE_LEVEL_FATAL) { printf(__VA_ARGS__); while(1); } } + +#else + +/* Trace compilation depends on TRACE_LEVEL value */ +#if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) +#define TRACE_DEBUG(...) { printf("-D- " __VA_ARGS__); } +#define TRACE_DEBUG_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_DEBUG(...) { } +#define TRACE_DEBUG_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_INFO) +#define TRACE_INFO(...) { printf("-I- " __VA_ARGS__); } +#define TRACE_INFO_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_INFO(...) { } +#define TRACE_INFO_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_WARNING) +#define TRACE_WARNING(...) { printf("-W- " __VA_ARGS__); } +#define TRACE_WARNING_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_WARNING(...) { } +#define TRACE_WARNING_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_ERROR) +#define TRACE_ERROR(...) { printf("-E- " __VA_ARGS__); } +#define TRACE_ERROR_WP(...) { printf(__VA_ARGS__); } +#else +#define TRACE_ERROR(...) { } +#define TRACE_ERROR_WP(...) { } +#endif + +#if (TRACE_LEVEL >= TRACE_LEVEL_FATAL) +#define TRACE_FATAL(...) { printf("-F- " __VA_ARGS__); while(1); } +#define TRACE_FATAL_WP(...) { printf(__VA_ARGS__); while(1); } +#else +#define TRACE_FATAL(...) { while(1); } +#define TRACE_FATAL_WP(...) { while(1); } +#endif + +#endif + + +/** + * Exported variables + */ +/** Depending on DYN_TRACES, dwTraceLevel is a modifiable runtime variable or a define */ +#if !defined(NOTRACE) && (DYN_TRACES == 1) + extern uint32_t dwTraceLevel ; +#endif + +#endif //#ifndef TRACE_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/trng.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/trng.h new file mode 100644 index 000000000..7e87637e8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/trng.h @@ -0,0 +1,50 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TRNG_ +#define _TRNG_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + +void TRNG_Enable(void); +void TRNG_Disable(void); +void TRNG_EnableIt(void); +void TRNG_DisableIt(void); +uint32_t TRNG_GetStatus(void); +uint32_t TRNG_GetRandData(void); + +#endif /* #ifndef _TRNG_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/twi.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/twi.h new file mode 100644 index 000000000..9e3835543 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/twi.h @@ -0,0 +1,111 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Interface for configuration the Two Wire Interface (TWI) peripheral. + * + */ + +#ifndef _TWI_ +#define _TWI_ + +/*------------------------------------------------------------------------------ + * Headers + *------------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ +/* Returns 1 if the TXRDY bit (ready to transmit data) is set in the given status register value.*/ +#define TWI_STATUS_TXRDY(status) ((status & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY) + +/* Returns 1 if the RXRDY bit (ready to receive data) is set in the given status register value.*/ +#define TWI_STATUS_RXRDY(status) ((status & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY) + +/* Returns 1 if the TXCOMP bit (transfer complete) is set in the given status register value.*/ +#define TWI_STATUS_TXCOMP(status) ((status & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP) + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * External function + *----------------------------------------------------------------------------*/ + +extern void TWI_ConfigureMaster(Twihs *pTwi, uint32_t twck, uint32_t mck); + +extern void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress); + +extern void TWI_Stop(Twihs *pTwi); + +extern void TWI_StartRead( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize); + +extern uint8_t TWI_ReadByte(Twihs *pTwi); + +extern void TWI_WriteByte(Twihs *pTwi, uint8_t byte); + +extern void TWI_StartWrite( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte); + +extern uint8_t TWI_ByteReceived(Twihs *pTwi); + +extern uint8_t TWI_ByteSent(Twihs *pTwi); + +extern uint8_t TWI_TransferComplete(Twihs *pTwi); + +extern void TWI_EnableIt(Twihs *pTwi, uint32_t sources); + +extern void TWI_DisableIt(Twihs *pTwi, uint32_t sources); + +extern uint32_t TWI_GetStatus(Twihs *pTwi); + +extern uint32_t TWI_GetMaskedStatus(Twihs *pTwi); + +extern void TWI_SendSTOPCondition(Twihs *pTwi); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _TWI_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/twid.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/twid.h new file mode 100644 index 000000000..dd68ccfeb --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/twid.h @@ -0,0 +1,142 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _TWID_ +#define _TWID_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ + +/** TWI driver is currently busy. */ +#define TWID_ERROR_BUSY 1 + + /** Transfer is still pending.*/ +#define ASYNC_STATUS_PENDING 0xFF +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + + /*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +/** \brief Asynchronous transfer descriptor. */ +typedef struct _Async +{ + /** Asynchronous transfer status.*/ + volatile uint32_t status ; + /** Callback function to invoke when transfer completes or fails.*/ + void *callback ; + /** Driver storage area; do not use.*/ + uint8_t pStorage[9] ; +} Async ; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct _Twid +{ + /** Pointer to the underlying TWI peripheral.*/ + Twihs *pTwi ; + /** Current asynchronous transfer being processed.*/ + Async *pTransfer ; +} Twid; + +/** \brief TWI driver structure. Holds the internal state of the driver.*/ +typedef struct +{ + uint8_t Twi_id; + /** Pointer to the underlying TWI driver.*/ + Twid *pTwid ; + /** Pointer to the underlying DMA driver for TWI.*/ + sXdmad *pTwiDma; +} TwihsDma; + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ +extern void TWID_Initialize( Twid *pTwid, Twihs *pTwi ) ; +extern void TWID_DmaInitialize(TwihsDma *pTwidma, Twihs *pTwi, uint8_t bPolling); + +extern void TWID_Handler( Twid *pTwid ) ; + +extern uint32_t ASYNC_IsFinished( Async* pAsync ) ; + +extern uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_Write( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaRead( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +extern uint8_t TWID_DmaWrite( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync); + +#ifdef __cplusplus +} +#endif + +#endif //#ifndef TWID_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/uart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/uart.h new file mode 100644 index 000000000..e631dc9cc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/uart.h @@ -0,0 +1,69 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +#ifndef UART_H +#define UART_H + + +//------------------------------------------------------------------------------ +// Global functions +//------------------------------------------------------------------------------ + +void UART_Configure(Uart *uart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock); + +void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled); + +void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled); + +void UART_PutChar( Uart *uart, uint8_t c); + +uint32_t UART_IsRxReady(Uart *uart); + +uint8_t UART_GetChar(Uart *uart); + +uint32_t UART_GetStatus(Uart *uart); + +void UART_EnableIt(Uart *uart,uint32_t mode); + +void UART_DisableIt(Uart *uart,uint32_t mode); + +uint32_t UART_GetItMask(Uart *uart); + +void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_ReceiveBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen); + +void UART_CompareConfig(Uart *uart, uint8_t Val1, uint8_t Val2); + +uint32_t UART_IsTxReady(Uart *uart); + +#endif //#ifndef UART_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/uart_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/uart_dma.h new file mode 100644 index 000000000..6dbc00a60 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/uart_dma.h @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of UART driver, transfer data through DMA. + * + */ + +#ifndef _UART_DMA_ +#define _UART_DMA_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define UARTD_ERROR 1 + +/** UART driver is currently in use.*/ +#define UARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** UART transfer complete callback. */ +typedef void (*UartdCallback)( uint8_t, void* ) ; + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the UART_Send or UART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint32_t ChNum; + /** Callback function invoked at the end of transfer. */ + UartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer. */ + volatile uint8_t sempaphore; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size */ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UartChannel ; + +/** Constant structure associated with UART port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** USART Id as defined in the product datasheet */ + uint8_t uartId ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; + /** Pointer to UART Hardware registers */ + Uart* pUartHw ; + /** Current Uart Rx channel */ + UartChannel *pRxChannel ; + /** Current Uart Tx channel */ + UartChannel *pTxChannel ; +} UartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t UARTD_Configure( UartDma *pUartd , + uint8_t uartId, + uint32_t uartMode, + uint32_t baud, + uint32_t clk ); + +uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_EnableRxChannels( UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_DisableTxChannels( UartDma *pUartd, UartChannel *pTxCh); + +uint32_t UARTD_DisableRxChannels( UartDma *pUartd, UartChannel *pRxCh); + +uint32_t UARTD_SendData( UartDma* pUartd ) ; + +uint32_t UARTD_RcvData( UartDma *pUartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _UART_DMA_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usart.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usart.h new file mode 100644 index 000000000..0be16f7e3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usart.h @@ -0,0 +1,164 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \par Purpose + * + * This module provides several definitions and methods for using an USART + * peripheral. + * + * \par Usage + * + * -# Enable the USART peripheral clock in the PMC. + * -# Enable the required USART PIOs (see pio.h). + * -# Configure the UART by calling USART_Configure. + * -# Enable the transmitter and/or the receiver of the USART using + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + * -# Send data through the USART using the USART_Write methods. + * -# Receive data from the USART using the USART_Read functions; the + * availability of data can be polled + * with USART_IsDataAvailable. + * -# Disable the transmitter and/or the receiver of the USART with + * USART_SetTransmitterEnabled and USART_SetReceiverEnabled. + */ + +#ifndef _USART_ +#define _USART_ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \section USART_mode USART modes + * This section lists several common operating modes for an USART peripheral. + * + * \b Modes + * - USART_MODE_ASYNCHRONOUS + * - USART_MODE_IRDA + */ + +/** Basic asynchronous mode, i.e. 8 bits no parity.*/ +#define USART_MODE_ASYNCHRONOUS (US_MR_CHRL_8_BIT | US_MR_PAR_NO) + +#define MAX_RX_TIMEOUT 131071 + +/** IRDA mode*/ +#define USART_MODE_IRDA \ + (US_MR_USART_MODE_IRDA | US_MR_CHRL_8_BIT | US_MR_PAR_NO | US_MR_FILTER) + +/** SPI mode*/ +#define AT91C_US_USMODE_SPIM 0xE +#define US_SPI_CPOL_0 (0x0<<16) +#define US_SPI_CPHA_0 (0x0<<8) +#define US_SPI_CPOL_1 (0x1<<16) +#define US_SPI_CPHA_1 (0x1<<8) +#define US_SPI_BPMODE_0 (US_SPI_CPOL_0|US_SPI_CPHA_1) +#define US_SPI_BPMODE_1 (US_SPI_CPOL_0|US_SPI_CPHA_0) +#define US_SPI_BPMODE_2 (US_SPI_CPOL_1|US_SPI_CPHA_1) +#define US_SPI_BPMODE_3 (US_SPI_CPOL_1|US_SPI_CPHA_0) + +#ifdef __cplusplus + extern "C" { +#endif + +/*------------------------------------------------------------------------------*/ +/* Exported functions */ +/*------------------------------------------------------------------------------*/ + + +void USART_Configure( Usart *pUsart, uint32_t mode, uint32_t baudrate, + uint32_t masterClock ) ; + +void USART_SetBaudrate(Usart *pUsart, uint8_t OverSamp, uint32_t baudrate, + uint32_t masterClock); + +uint32_t USART_GetStatus( Usart *usart ) ; + + +void USART_ResetRx(Usart *pUsart); + +void USART_ResetTx(Usart *pUsart); + +void USART_EnableTx(Usart *pUsart); + +void USART_EnableRx(Usart *pUsart); + +void USART_DisableRx(Usart *pUsart); + +void USART_DisableTx(Usart *pUsart); + +void USART_EnableIt( Usart *usart,uint32_t mode ) ; + +void USART_DisableIt( Usart *usart,uint32_t mode ) ; + +uint32_t USART_GetItMask( Usart * usart ) ; + +void USART_SetTransmitterEnabled( Usart *usart, uint8_t enabled ) ; + +void USART_SetReceiverEnabled( Usart *usart, uint8_t enabled ) ; + +void USART_SetRTSEnabled(Usart *usart, uint8_t enabled); + +void USART_Write( Usart *usart, uint16_t data, volatile uint32_t timeOut ) ; + +uint16_t USART_Read( Usart *usart, volatile uint32_t timeOut ) ; + +uint8_t USART_IsDataAvailable( Usart *usart ) ; + +void USART_SetIrdaFilter(Usart *pUsart, uint8_t filter); + +void USART_PutChar( Usart *usart, uint8_t c ) ; + +uint32_t USART_IsRxReady( Usart *usart ) ; + +uint8_t USART_GetChar( Usart *usart ) ; + +void USART_EnableRecvTimeOut(Usart *usart, uint32_t timeout); + +void USART_EnableTxTimeGaurd(Usart *pUsart, uint32_t TimeGaurd); + +void USART_AcknowledgeRxTimeOut(Usart *usart, uint8_t Periodic); + + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usart_dma.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usart_dma.h new file mode 100644 index 000000000..499380d8d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usart_dma.h @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2009, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of USART driver, transfer data through DMA. + * + */ + +#ifndef _USART_DMA_H_ +#define _USART_DMA_H_ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** An unspecified error has occurred.*/ +#define USARTD_ERROR 1 + +/** USART driver is currently in use.*/ +#define USARTD_ERROR_LOCK 2 + + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** USART transfer complete callback. */ +typedef void (*UsartdCallback)( uint8_t, void* ) ; + +/** \brief usart Transfer Request prepared by the application upper layer. + * + * This structure is sent to the USART_Send or USART_Rcv to start the transfer. + * At the end of the transfer, the callback is invoked by the interrupt handler. + */ +typedef struct +{ + /** Pointer to the Buffer. */ + uint8_t *pBuff; + /** Buff size in bytes. */ + uint32_t BuffSize; + /** Dma channel num. */ + uint8_t ChNum; + /** Callback function invoked at the end of transfer. */ + UsartdCallback callback; + /** Callback arguments. */ + void *pArgument; + /** flag to indicate the current transfer progress */ + volatile uint8_t dmaProgress; + /* DMA LLI structure */ + LinkedListDescriporView1 *pLLIview; + /* DMA transfer type */ + eXdmadProgState dmaProgrammingMode; + /* DMA LLI size or num of micro block*/ + uint16_t dmaBlockSize; + /* Flag using ring buffer or FiFo*/ + uint8_t dmaRingBuffer; +} UsartChannel ; + +/** Constant structure associated with USART port. This structure prevents + client applications to have access in the same time. */ +typedef struct +{ + /** USART Id as defined in the product datasheet */ + uint8_t usartId ; + /** Pointer to USART Hardware registers */ + Usart* pUsartHw ; + /** Current Usart Rx channel */ + UsartChannel *pRxChannel ; + /** Current Usart Tx channel */ + UsartChannel *pTxChannel ; + /** Pointer to DMA driver */ + sXdmad* pXdmad; +} UsartDma; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +uint32_t USARTD_Configure( UsartDma *pUsartd , + uint8_t USARTId, + uint32_t UsartMode, + uint32_t BaudRate, + uint32_t UsartClk); + +uint32_t USARTD_EnableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_EnableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh); + +uint32_t USARTD_DisableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_DisableRxChannels( UsartDma *pUsartd, UsartChannel *pTxCh); + +uint32_t USARTD_SendData( UsartDma* pUsartd ) ; + +uint32_t USARTD_RcvData( UsartDma *pUsartd); + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _USART_DMA_ */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usbhs.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usbhs.h new file mode 100644 index 000000000..d5a4b9bee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/usbhs.h @@ -0,0 +1,1674 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +#ifndef USBHS_H +#define USBHS_H +/** addtogroup usbd_hal + *@{ + */ + +#define USB_DEVICE_HS_SUPPORT + +//! Control endpoint size +#define USB_DEVICE_EP_CTRL_SIZE 64 + +/** Indicates chip has an UDP High Speed. */ +#define CHIP_USB_UDP + +/** Indicates chip has an internal pull-up. */ +#define CHIP_USB_PULLUP_INTERNAL + +/** Number of USB endpoints */ +#define CHIP_USB_NUMENDPOINTS 10 + +/** Endpoints max packet size */ +#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_ENDPOINTS_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_ENDPOINTS_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_ENDPOINTS_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + +/** Max size of the FMA FIFO */ +#define DMA_MAX_FIFO_SIZE (65536/1) +/** fifo space size in DW */ +#define EPT_VIRTUAL_SIZE 16384 + + + //! @name USBHS Host IP properties +//! +//! @{ +//! Get maximal number of endpoints +#define uhd_get_pipe_max_nbr() (9) +#define USBHS_EPT_NUM (uhd_get_pipe_max_nbr()+1) + //! Get maximal number of banks of endpoints +#define uhd_get_pipe_bank_max_nbr(ep) ((ep == 0) ? 1 : (( ep <= 2) ? 3 : 2)) + //! Get maximal size of endpoint (3X, 1024/64) +#define uhd_get_pipe_size_max(ep) (((ep) == 0) ? 64 : 1024) + //! Get DMA support of endpoints +#define Is_uhd_pipe_dma_supported(ep) ((((ep) >= 1) && ((ep) <= 6)) ? true : false) + //! Get High Band Width support of endpoints +#define Is_uhd_pipe_high_bw_supported(ep) (((ep) >= 2) ? true : false) +//! @} + +typedef enum +{ + HOST_MODE= 0, + DEVICE_MODE=1 +}USB_Mode_t; + +//! Maximum transfer size on USB DMA +#define UHD_PIPE_MAX_TRANS 0x8000 + +/** +================================= + USBHS_CTRL +================================= +**/ + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_FreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL |= USBHS_CTRL_FRZCLK; +} + +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_UnFreezeClock(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_FRZCLK); +} +/** + * \brief Freeze or unfreeze USB clock + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ +__STATIC_INLINE void USBHS_VBusHWC(Usbhs *pUsbhs, uint8_t Enable) +{ + + if(!Enable) { + pUsbhs->USBHS_CTRL |= (1<<8); + } else { + pUsbhs->USBHS_CTRL &= ~((uint32_t)(1<<8)); + } +} + +/** + * \brief Enables or disables USB + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable or disable + */ + +__STATIC_INLINE void USBHS_UsbEnable(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_CTRL |= USBHS_CTRL_USBE; + } else { + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_USBE); + } +} + + +/** + * \brief Device or Host Mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Mode Device or Host Mode + */ + +__STATIC_INLINE void USBHS_UsbMode(Usbhs *pUsbhs, USB_Mode_t Mode) +{ + if(Mode) { + pUsbhs->USBHS_CTRL |= USBHS_CTRL_UIMOD_DEVICE; + } else { + pUsbhs->USBHS_CTRL &= ~((uint32_t)USBHS_CTRL_UIMOD_DEVICE); + } +} + +/********************* USBHS_SR *****************/ + +/** + * \brief Check if clock is usable or not + * \param pUsbhs Pointer to an USBHS instance. + * \return 1 if USB clock is usable + */ + +__STATIC_INLINE uint8_t USBHS_ISUsableClock(Usbhs *pUsbhs) +{ + return (( pUsbhs->USBHS_SR & USBHS_SR_CLKUSABLE) >> 14); +} + + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \return USB status + */ + +__STATIC_INLINE uint32_t USBHS_ReadStatus(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_SR); +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE uint32_t USBHS_GetUsbSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) ); +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbFullSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_FULL_SPEED) ? true:false; +} + + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbHighSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_HIGH_SPEED) ? true:false; +} + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \return USB speed status + */ + +__STATIC_INLINE bool USBHS_IsUsbLowSpeed(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_SR & USBHS_SR_SPEED_Msk) == USBHS_SR_SPEED_LOW_SPEED) ? true:false; +} +/********************* USBHS_SCR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param AckType Interrupt Acknowledge type + */ + +__STATIC_INLINE void USBHS_Ack(Usbhs *pUsbhs, uint32_t AckType) +{ + pUsbhs->USBHS_SCR |= AckType; +} + +/********************* USBHS_SFR *****************/ + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_Set(Usbhs *pUsbhs, uint32_t SetStatus) +{ + pUsbhs->USBHS_SFR |= SetStatus; +} + + + /*-------------------------------------------------------- + * =========== USB Device functions ====================== + *---------------------------------------------------------*/ + +/** + * \brief Enable or disable USB address + * \param pUsbhs Pointer to an USBHS instance. + * \param SetStatus Set USB status + */ + +__STATIC_INLINE void USBHS_EnableAddress(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; + } else { + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_ADDEN); + } +} + +/** + * \brief Configure USB address and enable or disable it + * \param pUsbhs Pointer to an USBHS instance. + * \param Addr USB device status + */ + +__STATIC_INLINE void USBHS_SetAddress(Usbhs *pUsbhs, uint8_t Addr) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_UADD(Addr); + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_ADDEN; +} + +/** + * \brief Get USB address + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE uint8_t USBHS_GetAddress(Usbhs *pUsbhs) +{ + return ( pUsbhs->USBHS_DEVCTRL & USBHS_DEVCTRL_UADD_Msk); +} + +/** + * \brief Attach or detach USB. + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Attachs or detach USB device + */ + +__STATIC_INLINE void USBHS_DetachUsb(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_DETACH; + } else { + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_DETACH); + } + +} + +/** + * \brief Force Low Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables the Full speed + */ + +__STATIC_INLINE void USBHS_ForceLowSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_LS; + } else { + pUsbhs->USBHS_DEVCTRL &= ~((uint32_t)USBHS_DEVCTRL_LS); + } +} + +/** + * \brief Disable/Enables High Speed mode + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableHighSpeed(Usbhs *pUsbhs, uint8_t Enable) +{ + uint32_t cfg = pUsbhs->USBHS_DEVCTRL; + cfg &= ~((uint32_t)USBHS_DEVCTRL_SPDCONF_Msk); + if(Enable) { + pUsbhs->USBHS_DEVCTRL |= cfg; + } else { + pUsbhs->USBHS_DEVCTRL |= (cfg | USBHS_DEVCTRL_SPDCONF_FORCED_FS); + } + +} + +/** + * \brief Set Remote WakeUp mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_SetRemoteWakeUp(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_RMWKUP; +} + +/** + * \brief Disable/Enables Test mode + * \param pUsbhs Pointer to an USBHS instance. + * \param mode Enables/disable option + */ + +__STATIC_INLINE void USBHS_EnableTestMode(Usbhs *pUsbhs, uint32_t mode) +{ + pUsbhs->USBHS_DEVCTRL |= mode; +} + + +/** + * \brief Disable/Enables HS Test mode + * \param pUsbhs Pointer to an USBHS instance. + */ + +__STATIC_INLINE void USBHS_EnableHSTestMode(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED; +} + +/** + * \brief Read status for an interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt type + */ + +__STATIC_INLINE uint32_t USBHS_ReadIntStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVISR & IntType); +} + +/** + * \brief Read status for an Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint + */ + +__STATIC_INLINE uint32_t USBHS_ReadEpIntStatus(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_PEP_0 << EpNum) ); +} + +/** + * \brief Read status for a DMA Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum DMA Endpoint + */ +__STATIC_INLINE uint32_t USBHS_ReadDmaIntStatus(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVISR & ( USBHS_DEVISR_DMA_1 << DmaNum) ); +} + +/** + * \brief Acknowledge interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE void USBHS_AckInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVICR |= IntType; +} + +/** + * \brief Raise interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + + +__STATIC_INLINE void USBHS_RaiseInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIFR |= IntType; +} + +/** + * \brief Raise DMA interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_RaiseDmaInt(Usbhs *pUsbhs, uint8_t Dma) +{ + assert(Dma< USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIFR |= ( USBHS_DEVIFR_DMA_1 << Dma ); +} + +/** + * \brief check for interrupt of endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnable(Usbhs *pUsbhs, uint32_t IntType) +{ + return (pUsbhs->USBHS_DEVIMR & IntType); +} + +/** + * \brief Check if endpoint's interrupt is enabled for a given endpoint number + * \param pUsbhs Pointer to an USBHS instance. + * \param EpNum Endpoint number + */ + +__STATIC_INLINE uint32_t USBHS_IsIntEnableEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_PEP_0 << EpNum )); +} + + +/** + * \brief Check if endpoint's DMA interrupt is enabled for a given endpoint + * DMA number + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ + +__STATIC_INLINE uint32_t USBHS_IsDmaIntEnable(Usbhs *pUsbhs, uint8_t DmaNum) +{ + return (pUsbhs->USBHS_DEVIMR & (USBHS_DEVIMR_DMA_1 << DmaNum)); +} + + +/** + * \brief Enables Interrupt + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Interrupt Type + */ +__STATIC_INLINE void USBHS_EnableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIER |= IntType; +} + +/** + * \brief Enables interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaNum Endpoint's DMA number + */ +__STATIC_INLINE void USBHS_EnableIntEP(Usbhs *pUsbhs, uint8_t EpNum) +{ + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_PEP_0 << EpNum); +} + +/** + * \brief Enables DMA interrupt for a given endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaEp Endpoint's DMA interrupt number + */ + +__STATIC_INLINE void USBHS_EnableDMAIntEP(Usbhs *pUsbhs, uint32_t DmaEp) +{ + assert(DmaEp< USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIER |= (USBHS_DEVIER_DMA_1 << DmaEp); +} + + /** + * \brief Disables interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param IntType Int type + */ + +__STATIC_INLINE void USBHS_DisableInt(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_DEVIDR |= IntType; +} + + /** + * \brief Disables interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param Ep Endpoint number + */ + +__STATIC_INLINE void USBHS_DisableIntEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_PEP_0 << Ep); +} + + /** + * \brief Disables DMA interrupt for endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param DmaEp Endpoint's DMA number + */ +__STATIC_INLINE void USBHS_DisableDMAIntEP(Usbhs *pUsbhs, uint8_t DmaEp) +{ + assert(DmaEp< USBHSDEVDMA_NUMBER); + pUsbhs->USBHS_DEVIDR |= (USBHS_DEVIDR_DMA_1 << DmaEp); +} + + + /** + * \brief Enables or disables endpoint. + * \param pUsbhs Pointer to an USBHS instance. + * \param Enable Enable/disable endpoint + */ + +__STATIC_INLINE void USBHS_EnableEP(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPEN0 << Ep); + } else { + pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPEN0 << Ep); + } + +} + + + /** + * \brief Rests Endpoint + * \param pUsbhs Pointer to an USBHS instance. + * \param Ep Endpoint Number + */ + +__STATIC_INLINE void USBHS_ResetEP(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPT |= (USBHS_DEVEPT_EPRST0 << Ep); + //pUsbhs->USBHS_DEVEPT &= ~(uint32_t)(USBHS_DEVEPT_EPRST0 << Ep); +} + + /** + * \brief Checks if Endpoint is enable + * \param pUsbhs Pointer to an USBHS instance. + * \param Ep Endpoint Number + */ + +__STATIC_INLINE uint32_t USBHS_IsEPEnabled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPT & (USBHS_DEVEPT_EPEN0 << Ep) ); +} + + /** + * \brief Get MicrFrame number + * \param pUsbhs Pointer to an USBHS instance. + * \retruns Micro frame number + */ +__STATIC_INLINE uint8_t USBHS_GetMicroFrameNum(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_MFNUM_Msk); +} + + + /** + * \brief Get Frame number + * \param pUsbhs Pointer to an USBHS instance. + * \retruns frame number + */ +__STATIC_INLINE uint8_t USBHS_GetFrameNum(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNUM_Msk) + >> USBHS_DEVFNUM_FNUM_Pos); +} + + /** + * \brief Get Frame number CRC error + * \param pUsbhs Pointer to an USBHS instance. + * \retruns Frame number error status + */ +__STATIC_INLINE uint8_t USBHS_GetFrameNumCrcErr(Usbhs *pUsbhs) +{ + return ( (pUsbhs->USBHS_DEVFNUM & USBHS_DEVFNUM_FNCERR) >> 15); +} + + /*----------------------------------------- + * =========== USB Device's Endpoint functions ======== + *------------------------------------------*/ + +/** + * Set Endpoints configuration + * Bank size, type and direction + */ +__STATIC_INLINE void USBHS_ConfigureEPs(Usbhs *pUsbhs, const uint8_t Ep, + const uint8_t Type, const uint8_t Dir, + const uint8_t Size, const uint8_t Bank) +{ + + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Size << USBHS_DEVEPTCFG_EPSIZE_Pos) & USBHS_DEVEPTCFG_EPSIZE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + ((Dir << 8 ) & USBHS_DEVEPTCFG_EPDIR); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (( (Type) << USBHS_DEVEPTCFG_EPTYPE_Pos) & USBHS_DEVEPTCFG_EPTYPE_Msk); + pUsbhs->USBHS_DEVEPTCFG[Ep] |= + (( (Bank) << USBHS_DEVEPTCFG_EPBK_Pos) & USBHS_DEVEPTCFG_EPBK_Msk); +} + + +/** + * Enable or disable Auto switch of banks + */ +__STATIC_INLINE void USBHS_AutoSwitchBankEnable(Usbhs *pUsbhs, uint8_t Ep, uint8_t Enable) +{ + if(Enable) { + pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_AUTOSW; + } else { + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_AUTOSW); + } +} + + +/** + * Allocate Endpoint memory + */ +__STATIC_INLINE void USBHS_AllocateMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |=USBHS_DEVEPTCFG_ALLOC; +} + + +/** + * Free allocated Endpoint memory + */ +__STATIC_INLINE void USBHS_FreeMemory(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] &= ~((uint32_t)USBHS_DEVEPTCFG_ALLOC); +} + + +/** + * Get Endpoint configuration + */ +__STATIC_INLINE uint32_t USBHS_GetConfigureEPs(Usbhs *pUsbhs, uint8_t Ep, + uint32_t IntType) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep] ) & IntType); +} + +/** + * Get Endpoint Type + */ +__STATIC_INLINE uint8_t USBHS_GetEpType(Usbhs *pUsbhs, uint8_t Ep) +{ + return ((pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPTYPE_Msk) + >> USBHS_DEVEPTCFG_EPTYPE_Pos); +} + +/** + * Get Endpoint Size + */ +__STATIC_INLINE uint32_t USBHS_GetEpSize(Usbhs *pUsbhs, uint8_t Ep) +{ + return ( 8 << ( (pUsbhs->USBHS_DEVEPTCFG[Ep] & USBHS_DEVEPTCFG_EPSIZE_Msk) + >> USBHS_DEVEPTCFG_EPSIZE_Pos) ); +} + + +/** + * Sets ISO endpoint's Number of Transfer for High Speed + */ +__STATIC_INLINE void USBHS_SetIsoTrans(Usbhs *pUsbhs, uint8_t Ep, + uint8_t nbTrans) +{ + pUsbhs->USBHS_DEVEPTCFG[Ep] |= USBHS_DEVEPTCFG_NBTRANS(nbTrans) ; +} + +/** + * Check for interrupt types enabled for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsEpIntEnable(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpIntType) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & EpIntType); +} + + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_EnableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] |= EpInt; +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE uint32_t USBHS_IsBankKilled(Usbhs *pUsbhs, uint8_t Ep) +{ + return (pUsbhs->USBHS_DEVEPTIMR[Ep] & USBHS_DEVEPTIMR_KILLBK); +} + +/** + * Enables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_KillBank(Usbhs *pUsbhs, uint8_t Ep) +{ + pUsbhs->USBHS_DEVEPTIER[Ep] = USBHS_DEVEPTIER_KILLBKS; +} +/** + * Disables an interrupt type for a given endpoint + */ +__STATIC_INLINE void USBHS_DisableEPIntType(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIDR[Ep] |= EpInt; +} + +/** + * Clears register/acknowledge for a given endpoint + */ +__STATIC_INLINE void USBHS_AckEpInterrupt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTICR[Ep] |= EpInt; +} + +/** + * Sets/Raise register for a given endpoint + */ +__STATIC_INLINE void USBHS_RaiseEPInt(Usbhs *pUsbhs, uint8_t Ep, uint32_t EpInt) +{ + pUsbhs->USBHS_DEVEPTIFR[Ep] |= EpInt; +} + +/** + * Gets interrupt status for a given EP + */ +__STATIC_INLINE uint32_t USBHS_ReadEPStatus(Usbhs *pUsbhs, uint8_t Ep, + uint32_t EpInt) +{ + return (pUsbhs->USBHS_DEVEPTISR[Ep] & EpInt); +} + +/** + * Check if given endpoint's bank is free + */ +__STATIC_INLINE uint8_t USBHS_IsBankFree(Usbhs *pUsbhs, uint8_t Ep) +{ + if( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk)) { + return false; + } else { + return true; + } +} + +/** + * Read endpoint's bank number in use + */ +__STATIC_INLINE uint8_t USBHS_NumOfBanksInUse(Usbhs *pUsbhs, uint8_t Ep) +{ + return ( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_NBUSYBK_Msk) + >> USBHS_DEVEPTISR_NBUSYBK_Pos); +} + + +/** + * Read endpoint's bank number in use + */ +__STATIC_INLINE uint16_t USBHS_ByteCount(Usbhs *pUsbhs, uint8_t Ep) +{ + return (uint16_t)( (pUsbhs->USBHS_DEVEPTISR[Ep] & USBHS_DEVEPTISR_BYCT_Msk) + >> USBHS_DEVEPTISR_BYCT_Pos); +} + + /*-------------------------------------------------------- + * =========== USB Device's Ep's DMA functions ========= + *---------------------------------------------------------*/ + + /** + * \brief Sets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \param Desc NDA address + */ +__STATIC_INLINE void USBHS_SetDmaNDA(UsbhsDevdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_DEVDMANXTDSC = Desc; +} + + /** + * \brief Gets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \return Next DMA descriptor + */ +__STATIC_INLINE uint32_t USBHS_GetDmaNDA(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMANXTDSC); +} + + /** + * \brief Sets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \param Addr DMA's buffer Addrs + */ +__STATIC_INLINE void USBHS_SetDmaBuffAdd(UsbhsDevdma *pUsbDma, uint32_t Addr) +{ + pUsbDma->USBHS_DEVDMAADDRESS = Addr; +} + + + /** + * \brief Gets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \return DMA addrs + */ +__STATIC_INLINE uint32_t USBHS_GetDmaBuffAdd(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMAADDRESS); +} + + /** + * \brief Setup the USBHS DMA + * \param pUsbDma USBHS device DMA instance + * \param Cfg DMA's configuration + */ +__STATIC_INLINE void USBHS_ConfigureDma(UsbhsDevdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_DEVDMACONTROL |= Cfg; +} + + /** + * \brief Get DMA configuration + * \param pUsbDma USBHS device DMA instance + * \return DMA control setup + */ +__STATIC_INLINE uint32_t USBHS_GetDmaConfiguration(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMACONTROL); +} + + + /** + * \brief Set DMA status + * \param pUsbDma USBHS device DMA instance + * \Status Set DMA status + */ +__STATIC_INLINE void USBHS_SetDmaStatus(UsbhsDevdma *pUsbDma, uint32_t Status) +{ + pUsbDma->USBHS_DEVDMASTATUS = Status; +} + + + /** + * \brief Get Dma Status + * \param pUsbDma USBHS device DMA instance + * \return Dma status + */ +__STATIC_INLINE uint32_t USBHS_GetDmaStatus(UsbhsDevdma *pUsbDma) +{ + return (pUsbDma->USBHS_DEVDMASTATUS); +} + + + /** + * \brief Get DMA buffer's count + * \param pUsbDma USBHS device DMA instance + * \return Buffer count + */ +__STATIC_INLINE uint16_t USBHS_GetDmaBuffCount(UsbhsDevdma *pUsbDma) +{ + return ( (pUsbDma->USBHS_DEVDMASTATUS & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos); +} + + + /*-------------------------------------------------------- + * =========== USB Host Functions ======================== + *---------------------------------------------------------*/ + +/** Number of USB endpoints */ +#define CHIP_USB_NUMPIPE 10 +/** Number of USB endpoints */ +#define CHIP_USB_DMA_NUMPIPE 7 + +/** Endpoints max paxcket size */ +#define CHIP_USB_PIPE_MAXPACKETSIZE(ep) \ + ((ep == 0) ? 64 : 1024) + +/** Endpoints Number of Bank */ +#define CHIP_USB_PIPE_BANKS(ep) ((ep==0)?1:((ep<=2)?3:2)) + + +#define CHIP_USB_PIPE_HBW(ep) ((((ep)>=1) &&((ep)<=2))?true:false) + +/** Endpoints DMA support */ +#define CHIP_USB_PIPE_DMA(ep) ((((ep)>=1)&&((ep)<=7))?true:false) + + /** + * \brief Sets USB host's speed to Normal , it sets to HS from FS + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostHighSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_NORMAL; +} + + /** + * \brief Sets USB host's speed to Low speed + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostLowSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_LOW_POWER; +} + + /** + * \brief Sets USB host's speed to forced Full speed + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostForcedFullSpeed(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SPDCONF_FORCED_FS; +} + + /** + * \brief Sets USB host sends reste signal on USB Bus + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_Reset(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESET; +} + + /** + * \brief Sets USB host sends reste signal on USB Bus + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_StopReset(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_RESET; +} + + /** + * \brief Sets USB host send Resume on USB bus + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_Resume(void) +{ + USBHS->USBHS_HSTCTRL |= USBHS_HSTCTRL_RESUME; +} + + /** + * \brief Sets USB host Enable the Generation of Start of Frame + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_EnableSOF(Usbhs *pUsbhs) +{ + pUsbhs->USBHS_HSTCTRL |= USBHS_HSTCTRL_SOFE; +} + + /** + * \brief Sets USB host Enable the Generation of Start of Frame + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsEnableSOF(Usbhs *pUsbhs) +{ + return (pUsbhs->USBHS_HSTCTRL & USBHS_HSTCTRL_SOFE) >> 8; +} + /** + * \brief Sets USB host disable the Generation of Start of Frame + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_DisableSOF(void) +{ + USBHS->USBHS_HSTCTRL &= ~USBHS_HSTCTRL_SOFE; +} + + /** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostStatus(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTISR & IntType); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_PEP_0 << PipeInt) ); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaPipeStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + return (pUsbhs->USBHS_HSTISR & ( USBHS_HSTISR_DMA_1 << PipeInt) ); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_ClearHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTICR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostStatus(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIFR = IntType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_SetHostDmaStatus(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIFR = (USBHS_HSTIFR_DMA_1 << PipeInt) ; +} + +/*** Interrupt Mask ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostIntEnable(Usbhs *pUsbhs, uint8_t IntType) +{ + return (pUsbhs->USBHS_HSTIMR & IntType) ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_PEP_0 << PipeInt) ); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + return ( pUsbhs->USBHS_HSTIMR & (USBHS_HSTIMR_DMA_1 << PipeInt) ); +} + +/*** Interrupt Disable ****/ +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntDisable(Usbhs *pUsbhs, uint32_t IntType) +{ + pUsbhs->USBHS_HSTIDR = IntType ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_PEP_0 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntDisable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt); + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIDR = (USBHS_HSTIDR_DMA_1 << PipeInt) ; +} + +/*** Interrupt Enable ****/ + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostIntEnable(Usbhs *pUsbhs, uint8_t IntType) +{ + pUsbhs->USBHS_HSTIER = IntType ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTIER =(USBHS_HSTIER_PEP_0 << PipeInt) ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDmaIntEnable(Usbhs *pUsbhs, uint8_t PipeInt) +{ + assert( PipeInt < CHIP_USB_DMA_NUMPIPE); + pUsbhs->USBHS_HSTIER |= (USBHS_HSTIER_DMA_1 << PipeInt); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSOF(void) +{ + return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_FNUM_Msk) >> USBHS_HSTFNUM_FNUM_Pos); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetMSOF(void) +{ + return ( (USBHS->USBHS_HSTFNUM & USBHS_HSTFNUM_MFNUM_Msk) >> USBHS_HSTFNUM_MFNUM_Pos); +} + +__STATIC_INLINE void USBHS_HostSetAddr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Addr) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + if (Pipe <4) + { + pUsbhs->USBHS_HSTADDR1 |= (Addr << (8*Pipe)); + } + else if( (Pipe <8) && (Pipe >=4)) + { + pUsbhs->USBHS_HSTADDR2 |= (Addr << (8* (Pipe -4))); + } + else + { + pUsbhs->USBHS_HSTADDR3 |= (Addr << (8*(Pipe -8))); + } + +} + +__STATIC_INLINE uint8_t USBHS_HostGetAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + if (Pipe <4) + { + return ( pUsbhs->USBHS_HSTADDR1 >> (8*Pipe)) ; + } + else if( (Pipe <8) && (Pipe >=4)) + { + return (pUsbhs->USBHS_HSTADDR2 >> (8*(Pipe -4))); + } + else + { + return (pUsbhs->USBHS_HSTADDR3 >> (8*(Pipe -8))); + } + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeDisable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PEN0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + return (pUsbhs->USBHS_HSTPIP &(USBHS_HSTPIP_PEN0 << Pipe)); +} +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostPipeReset(Usbhs *pUsbhs, uint8_t Pipe) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIP |= (USBHS_HSTPIP_PRST0 << Pipe); + pUsbhs->USBHS_HSTPIP &= ~(USBHS_HSTPIP_PRST0 << Pipe); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostConfigure(Usbhs *pUsbhs, uint8_t Pipe, uint32_t pipeBank, uint8_t pipeSize, uint32_t pipeType, uint32_t pipeToken, uint8_t pipeEpNum, uint8_t PipeIntFreq) +{ + assert( Pipe < CHIP_USB_NUMPIPE); + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= ( pipeBank | pipeToken | USBHS_HSTPIPCFG_PSIZE(pipeSize) | pipeType | USBHS_HSTPIPCFG_PEPNUM(pipeEpNum) | USBHS_HSTPIPCFG_INTFRQ(PipeIntFreq)); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAllocMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_ALLOC; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostFreeMem(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_ALLOC; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint16_t USBHS_HostGetSize(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (8 << ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PSIZE_Msk) >> USBHS_HSTPIPCFG_PSIZE_Pos)) ; + +} + + /** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetToken(Usbhs *pUsbhs, uint8_t Pipe, uint32_t Token) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTOKEN_Msk; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= Token; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetToken(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTOKEN_Msk) ; + +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeType(Usbhs *pUsbhs, uint8_t Pipe, uint8_t PipeType) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_PTYPE_Msk ; + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= PipeType ; + +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetPipeType(Usbhs *pUsbhs, uint8_t Pipe ) +{ + return (pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PTYPE_Msk) ; + +} + +__STATIC_INLINE uint8_t USBHS_GetPipeEpAddr(Usbhs *pUsbhs, uint8_t Pipe) +{ + + if( USBHS_HostGetToken(USBHS, Pipe) == USBHS_HSTPIPCFG_PTOKEN_IN) + { + return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x80); + } + else + { + return ( ((pUsbhs->USBHS_HSTPIPCFG[Pipe] & USBHS_HSTPIPCFG_PEPNUM_Msk) >> USBHS_HSTPIPCFG_PEPNUM_Pos) | 0x00) ; + } +} + + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableAutoSw(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] &= ~USBHS_HSTPIPCFG_AUTOSW; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetIntFreq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Freq) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_BINTERVAL(Freq); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePing(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPCFG[Pipe] |= USBHS_HSTPIPCFG_PINGEN; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetDataTogSeq(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_DTSEQ_Msk) >> USBHS_HSTPIPISR_DTSEQ_Pos ) ; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetNumOfBusyBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_NBUSYBK_Msk) >> USBHS_HSTPIPISR_NBUSYBK_Pos ) ; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetCurrentBank(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_CURRBK_Msk) >> USBHS_HSTPIPISR_CURRBK_Pos ) ; +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetPipeByteCount(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ( (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_HSTPIPISR_PBYCT_Msk) >> USBHS_HSTPIPISR_PBYCT_Pos ) ; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostConfigOk(Usbhs *pUsbhs, uint8_t Pipe) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & USBHS_DEVEPTISR_CFGOK); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_HostGetIntTypeStatus(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + return (pUsbhs->USBHS_HSTPIPISR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostAckPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPICR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetPipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIFR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint32_t USBHS_IsHostPipeIntTypeEnable(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + return ( pUsbhs->USBHS_HSTPIPIMR[Pipe] & intType); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIDR[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnablePipeIntType(Usbhs *pUsbhs, uint8_t Pipe, uint32_t intType) +{ + pUsbhs->USBHS_HSTPIPIER[Pipe] = intType; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostEnableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] |= USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostDisableInReq(Usbhs *pUsbhs, uint8_t Pipe) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] &= ~USBHS_HSTPIPINRQ_INMODE; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_IsHostInReqEnable(Usbhs *pUsbhs, uint8_t Pipe) +{ + return ((pUsbhs->USBHS_HSTPIPINRQ[Pipe] & USBHS_HSTPIPINRQ_INMODE) >> 8); +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostInReq(Usbhs *pUsbhs, uint8_t Pipe, uint8_t InReq) +{ + pUsbhs->USBHS_HSTPIPINRQ[Pipe] = USBHS_HSTPIPINRQ_INRQ(InReq-1); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostSetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] |= Err; +} + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE uint8_t USBHS_HostGetErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + return (pUsbhs->USBHS_HSTPIPERR[Pipe] & Err); +} + + +/** + * \brief Gets USB host interrupt status + * \param pUsbhs USBHS host instance + */ +__STATIC_INLINE void USBHS_HostClearErr(Usbhs *pUsbhs, uint8_t Pipe, uint8_t Err) +{ + pUsbhs->USBHS_HSTPIPERR[Pipe] = Err; +} + + +__STATIC_INLINE uint8_t USBHS_GetInterruptPipeNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return ctz(((status & mask) >> 8) | (1 << USBHS_EPT_NUM)); +} + +static inline uint8_t USBHS_GetInterruptPipeDmaNum(void) +{ + uint32_t status = USBHS->USBHS_HSTISR; + uint32_t mask = USBHS->USBHS_HSTIMR; + return (ctz(((status & mask) >> 25) | (1 << (USBHS_EPT_NUM-1))) + 1); +} + /*-------------------------------------------------------- + * =========== USB Host's pipe DMA functions ========= + *---------------------------------------------------------*/ + + /** + * \brief Sets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \param Desc NDA addrs + */ +__STATIC_INLINE void USBHS_SetHostDmaNDA(UsbhsHstdma *pUsbDma, uint32_t Desc) +{ + pUsbDma->USBHS_HSTDMANXTDSC = Desc; +} + + /** + * \brief Gets DMA next descriptor address + * \param pUsbDma USBHS device DMA instance + * \return Next DMA descriptor + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaNDA(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMANXTDSC); +} + + /** + * \brief Sets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \param Addr DMA's buffer Addrs + */ +__STATIC_INLINE void USBHS_SetHostDmaBuffAdd(UsbhsHstdma *pUsbDma, uint32_t Addr) +{ + pUsbDma->USBHS_HSTDMAADDRESS = Addr; +} + + + /** + * \brief Gets USBHS's DMA Buffer addresse + * \param pUsbDma USBHS device DMA instance + * \return DMA addrs + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaBuffAdd(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMAADDRESS); +} + + /** + * \brief Setup the USBHS DMA + * \param pUsbDma USBHS device DMA instance + * \param Cfg DMA's configuration + */ +__STATIC_INLINE void USBHS_HostConfigureDma(UsbhsHstdma *pUsbDma, uint32_t Cfg) +{ + pUsbDma->USBHS_HSTDMACONTROL |= Cfg; +} + + /** + * \brief Get DMA configuration + * \param pUsbDma USBHS device DMA instance + * \return DMA control setup + */ +__STATIC_INLINE uint32_t USBHS_GetHostDmaConfiguration(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMACONTROL); +} + + + /** + * \brief Set DMA status + * \param pUsbDma USBHS device DMA instance + * \Status Set DMA status + */ +__STATIC_INLINE void USBHS_SetHostPipeDmaStatus(UsbhsHstdma *pUsbDma, uint32_t Status) +{ + pUsbDma->USBHS_HSTDMASTATUS = Status; +} + + + /** + * \brief Get Dma Status + * \param pUsbDma USBHS device DMA instance + * \return Dma status + */ +__STATIC_INLINE uint32_t USBHS_GetHostPipeDmaStatus(UsbhsHstdma *pUsbDma) +{ + return (pUsbDma->USBHS_HSTDMASTATUS); +} + +/**@}*/ +#endif /* #ifndef USBHS_H */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/video.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/video.h new file mode 100644 index 000000000..f0bb6f9ff --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/video.h @@ -0,0 +1,80 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _VIDEO_H +#define _VIDEO_H + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ +/** Type of video is YUV */ +#define YUV 0 +/** Type of video is RGB */ +#define RGB 1 + +/*---------------------------------------------------------------------------- + * Type + *----------------------------------------------------------------------------*/ +typedef struct _isi_Video +{ + /** LCD Vertical Size */ + uint32_t lcd_vsize; + /** LCD Horizontal Size*/ + uint32_t lcd_hsize; + /** LCD Number of Bit Per Pixel*/ + uint32_t lcd_nbpp; + /** LCD Frame Buffer Address*/ + uint32_t lcd_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t Isi_fbd_base; + /** Start of Line Delay*/ + uint32_t Hblank; + /** Start of frame Delay */ + uint32_t Vblank; + /** Vertical size of the Image sensor [0..2047]*/ + uint32_t codec_vsize; + /** Horizontal size of the Image sensor [0..2047]*/ + uint32_t codec_hsize; + /** Base address for codec DMA*/ + uint32_t codec_fb_addr; + /** Base address for the frame buffer descriptors list*/ + uint32_t codec_fbd_base; + /** Buffer index */ + uint32_t IsiPrevBuffIndex; + /** Type of video */ + uint8_t rgb_or_yuv; +}isi_Video, *pIsi_Video; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +extern void VIDEO_Ycc2Rgb(uint8_t *ycc, uint16_t *rgb, uint32_t len); + +#endif + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/wdt.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/wdt.h new file mode 100644 index 000000000..baafd7281 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/wdt.h @@ -0,0 +1,74 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * Interface for Watchdog Timer (WDT) controller. + * + * \section Usage + * -# Enable watchdog with given mode using \ref WDT_Enable(). + * -# Disable watchdog using \ref WDT_Disable() + * -# Restart the watchdog using \ref WDT_Restart(). + * -# Get watchdog status using \ref WDT_GetStatus(). + * -# Calculate watchdog period value using \ref WDT_GetPeriod(). + */ + +#ifndef _WDT_ +#define _WDT_ + +#include "chip.h" + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) ; + +extern void WDT_Disable( Wdt* pWDT ) ; + +extern void WDT_Restart( Wdt* pWDT ) ; + +extern uint32_t WDT_GetStatus( Wdt* pWDT ) ; + +extern uint32_t WDT_GetPeriod( uint32_t dwMs ) ; + +#ifdef __cplusplus +} +#endif + +#endif /* #ifndef _WDT_ */ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdma_hardware_interface.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdma_hardware_interface.h new file mode 100644 index 000000000..efbea7d80 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdma_hardware_interface.h @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _XDMAD_IF_H +#define _XDMAD_IF_H + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** DMA hardware interface */ +typedef struct _XdmaHardwareInterface { + uint8_t bXdmac; /**< DMA Controller number */ + uint32_t bPeriphID; /**< Peripheral ID */ + uint8_t bTransfer; /**< Transfer type 0: Tx, 1 :Rx*/ + uint8_t bIfID; /**< DMA Interface ID */ +} XdmaHardwareInterface; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bPeriphID); +extern uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID, uint8_t bTransfer); + +#endif //#ifndef _XDMAD_IF_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdmac.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdmac.h new file mode 100644 index 000000000..48dff188b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdmac.h @@ -0,0 +1,177 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** \addtogroup dmac_module Working with DMAC + * + * \section Usage + *
    + *
  • Enable or disable the a DMAC controller with DMAC_Enable() and or + * DMAC_Disable().
    • + *
  • Enable or disable %Dma interrupt using DMAC_EnableIt()or + * DMAC_DisableIt().
    • + *
  • Get %Dma interrupt status by DMAC_GetStatus() and + * DMAC_GetInterruptMask().
    • + *
  • Enable or disable specified %Dma channel with DMAC_EnableChannel() or + * DMAC_DisableChannel().
    • + *
  • Get %Dma channel status by DMAC_GetChannelStatus().
    • + *
  • ControlA and ControlB register is set by DMAC_SetControlA() and + * DMAC_SetControlB().
    • + *
  • Configure source and/or destination start address with + * DMAC_SetSourceAddr() and/or DMAC_SetDestinationAddr().
    • + *
  • Set %Dma descriptor address using DMAC_SetDescriptorAddr().
    • + *
  • Set source transfer buffer size with DMAC_SetBufferSize().
    • + *
  • Configure source and/or destination Picture-In-Picuture mode with + * DMAC_SetSourcePip() and/or DMAC_SetDestPip().
    • + *
+ * + * For more accurate information, please look at the DMAC section of the + * Datasheet. + * + * \sa \ref dmad_module + * + * Related files :\n + * \ref dmac.c\n + * \ref dmac.h.\n + * + */ + +#ifndef DMAC_H +#define DMAC_H +/**@{*/ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +//_RB_ #include <../../../../utils/utility.h> +#include + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ + +/** \addtogroup dmac_defines DMAC Definitions + * @{ + */ +/** Number of DMA channels */ +#define XDMAC_CONTROLLER_NUM 1 +/** Number of DMA channels */ +#define XDMAC_CHANNEL_NUM 24 +/** Max DMA single transfer size */ +#define XDMAC_MAX_BT_SIZE 0xFFFF +/** @}*/ + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +#define XDMA_GET_DATASIZE(size) ((size==0)? XDMAC_CC_DWIDTH_BYTE : \ + ((size==1)? XDMAC_CC_DWIDTH_HALFWORD : \ + (XDMAC_CC_DWIDTH_WORD ))) +#define XDMA_GET_CC_SAM(s) ((s==0)? XDMAC_CC_SAM_FIXED_AM : \ + ((s==1)? XDMAC_CC_SAM_INCREMENTED_AM : \ + ((s==2)? XDMAC_CC_SAM_UBS_AM : \ + XDMAC_CC_SAM_UBS_DS_AM ))) +#define XDMA_GET_CC_DAM(d) ((d==0)? XDMAC_CC_DAM_FIXED_AM : \ + ((d==1)? XDMAC_CC_DAM_INCREMENTED_AM : \ + ((d==2)? XDMAC_CC_DAM_UBS_AM : \ + XDMAC_CC_DAM_UBS_DS_AM ))) +#define XDMA_GET_CC_MEMSET(m) ((m==0)? XDMAC_CC_MEMSET_NORMAL_MODE : \ + XDMAC_CC_MEMSET_HW_MODE) + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmac_functions + * @{ + */ + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t XDMAC_GetType( Xdmac *pXdmac); +extern uint32_t XDMAC_GetConfig( Xdmac *pXdmac); +extern uint32_t XDMAC_GetArbiter( Xdmac *pXdmac); +extern void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask ); +extern void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask ); +extern uint32_t XDMAC_GetGItMask( Xdmac *pXdmac ); +extern uint32_t XDMAC_GetGIsr( Xdmac *pXdmac ); +extern uint32_t XDMAC_GetMaskedGIsr( Xdmac *pXdmac ); +extern void XDMAC_EnableChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_EnableChannels( Xdmac *pXdmac, uint32_t bmChannels ); +extern void XDMAC_DisableChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_DisableChannels( Xdmac *pXdmac, uint32_t bmChannels ); +extern uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac); +extern void XDMAC_SuspendReadChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_SuspendWriteChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_SuspendReadWriteChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_ResumeReadWriteChannel( Xdmac *pXdmac, uint8_t channel ); +extern void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel); +extern uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac); +extern void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel); +extern void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask ); +extern void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, + uint8_t dwInteruptMask ); +extern uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel); +extern uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel); +extern uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel); +extern void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr); +extern void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr); +extern void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr, uint8_t ndaif); +extern void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, + uint8_t config); +extern void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, + uint32_t ublen); +extern void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, + uint16_t blen); +extern void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, + uint32_t config); +extern uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel); +extern void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, + uint32_t dds_msp); +extern void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t subs); +extern void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, + uint32_t dubs); +extern uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel); +#ifdef __cplusplus +} +#endif + +/** @}*/ +/**@}*/ +#endif //#ifndef DMAC_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdmad.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdmad.h new file mode 100644 index 000000000..abb70c0ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/include/xdmad.h @@ -0,0 +1,260 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +#ifndef _XDMAD_H +#define _XDMAD_H + + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include + + +/** \addtogroup dmad_defines DMA Driver Defines + @{*/ +/*---------------------------------------------------------------------------- + * Consts + *----------------------------------------------------------------------------*/ +#define XDMAD_TRANSFER_MEMORY 0xFF /**< DMA transfer from or to memory */ +#define XDMAD_ALLOC_FAILED 0xFFFF /**< Channel allocate failed */ + +#define XDMAD_TRANSFER_TX 0 +#define XDMAD_TRANSFER_RX 1 + +/* XDMA_MBR_UBC */ +#define XDMA_UBC_NDE (0x1u << 24) +#define XDMA_UBC_NDE_FETCH_DIS (0x0u << 24) +#define XDMA_UBC_NDE_FETCH_EN (0x1u << 24) +#define XDMA_UBC_NSEN (0x1u << 25) +#define XDMA_UBC_NSEN_UNCHANGED (0x0u << 25) +#define XDMA_UBC_NSEN_UPDATED (0x1u << 25) +#define XDMA_UBC_NDEN (0x1u << 26) +#define XDMA_UBC_NDEN_UNCHANGED (0x0u << 26) +#define XDMA_UBC_NDEN_UPDATED (0x1u << 26) +#define XDMA_UBC_NVIEW_Pos 27 +#define XDMA_UBC_NVIEW_Msk (0x3u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV0 (0x0u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV1 (0x1u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV2 (0x2u << XDMA_UBC_NVIEW_Pos) +#define XDMA_UBC_NVIEW_NDV3 (0x3u << XDMA_UBC_NVIEW_Pos) + +/*---------------------------------------------------------------------------- + * MACRO + *----------------------------------------------------------------------------*/ + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_structs DMA Driver Structs + @{*/ + +/** DMA status or return code */ +typedef enum _XdmadStatus { + XDMAD_OK = 0, /**< Operation is successful */ + XDMAD_PARTIAL_DONE, + XDMAD_DONE, + XDMAD_BUSY, /**< Channel occupied or transfer not finished */ + XDMAD_ERROR, /**< Operation failed */ + XDMAD_CANCELED /**< Operation cancelled */ +} eXdmadStatus, eXdmadRC; + +/** DMA state for channel */ +typedef enum _XdmadState { + XDMAD_STATE_FREE = 0, /**< Free channel */ + XDMAD_STATE_ALLOCATED, /**< Allocated to some peripheral */ + XDMAD_STATE_START, /**< DMA started */ + XDMAD_STATE_IN_XFR, /**< DMA in transferring */ + XDMAD_STATE_DONE, /**< DMA transfer done */ + XDMAD_STATE_HALTED, /**< DMA transfer stopped */ +} eXdmadState; + +/** DMA Programming state for channel */ +typedef enum _XdmadProgState { + XDMAD_SINGLE= 0, + XDMAD_MULTI, + XDMAD_LLI, +} eXdmadProgState; + +/** DMA transfer callback */ +typedef void (*XdmadTransferCallback)(uint32_t status, void* pArg); + +/** DMA driver channel */ +typedef struct _XdmadChannel { + XdmadTransferCallback fCallback; /**< Callback */ + void* pArg; /**< Callback argument */ + uint8_t bIrqOwner; /**< Uses DMA handler or external one */ + uint8_t bSrcPeriphID; /**< HW ID for source */ + uint8_t bDstPeriphID; /**< HW ID for destination */ + uint8_t bSrcTxIfID; /**< DMA Tx Interface ID for source */ + uint8_t bSrcRxIfID; /**< DMA Rx Interface ID for source */ + uint8_t bDstTxIfID; /**< DMA Tx Interface ID for destination */ + uint8_t bDstRxIfID; /**< DMA Rx Interface ID for destination */ + volatile uint8_t state; /**< DMA channel state */ +} sXdmadChannel; + +/** DMA driver instance */ +typedef struct _Xdmad { + Xdmac *pXdmacs; + sXdmadChannel XdmaChannels[XDMACCHID_NUMBER]; + uint8_t numControllers; + uint8_t numChannels; + uint8_t pollingMode; + uint8_t pollingTimeout; + uint8_t xdmaMutex; +} sXdmad; + +typedef struct _XdmadCfg { + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +} sXdmadCfg; + +/** \brief Structure for storing parameters for DMA view0 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView0 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Transfer Address Member. */ + uint32_t mbr_ta; +}LinkedListDescriporView0; + +/** \brief Structure for storing parameters for DMA view1 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView1 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; +}LinkedListDescriporView1; + +/** \brief Structure for storing parameters for DMA view2 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView2 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; +}LinkedListDescriporView2; + +/** \brief Structure for storing parameters for DMA view3 that can be + * performed by the DMA Master transfer.*/ +typedef struct _LinkedListDescriporView3 +{ + /** Next Descriptor Address number. */ + uint32_t mbr_nda; + /** Microblock Control Member. */ + uint32_t mbr_ubc; + /** Source Address Member. */ + uint32_t mbr_sa; + /** Destination Address Member. */ + uint32_t mbr_da; + /** Configuration Register. */ + uint32_t mbr_cfg; + /** Block Control Member. */ + uint32_t mbr_bc; + /** Data Stride Member. */ + uint32_t mbr_ds; + /** Source Microblock Stride Member. */ + uint32_t mbr_sus; + /** Destination Microblock Stride Member. */ + uint32_t mbr_dus; +}LinkedListDescriporView3; + +/** @}*/ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** \addtogroup dmad_functions DMA Driver Functions + @{*/ +extern void XDMAD_Initialize( sXdmad *pXdmad, + uint8_t bPollingMode ); + +extern void XDMAD_Handler( sXdmad *pDmad); + +extern uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad, + uint8_t bSrcID, uint8_t bDstID); +extern eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, uint32_t dwChannel ); + +extern eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad, + uint32_t dwChannel, + sXdmadCfg *pXdmaParam, + uint32_t dwXdmaDescCfg, + uint32_t dwXdmaDescAddr, + uint32_t dwXdmaIntEn); + +extern eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel); + +extern eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel ); + +extern eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel ); + +extern eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad, + uint32_t dwChannel, + XdmadTransferCallback fCallback, + void* pArg ); + +extern eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel ); +/** @}*/ +/**@}*/ +#endif //#ifndef _XDMAD_H + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Initialized.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Initialized.c new file mode 100644 index 000000000..ba0d9914e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Initialized.c @@ -0,0 +1,51 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported function + *----------------------------------------------------------------------------*/ + +/** + * Invoked after the USB driver has been initialized. By default, configures + * the UDP/UDPHS interrupt. + */ +void USBDCallbacks_Initialized(void) +{ +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Resumed.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Resumed.c new file mode 100644 index 000000000..68cc8fda1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Resumed.c @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "USBD_LEDs.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Invoked when the USB device leaves the Suspended state. By default, + * configures the LEDs. + */ +void USBDCallbacks_Resumed(void) +{ +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Suspended.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Suspended.c new file mode 100644 index 000000000..018b9d18e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBDCallbacks_Suspended.c @@ -0,0 +1,49 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "USBD_LEDs.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Invoked when the USB device gets suspended. By default, turns off all LEDs. + */ +void USBDCallbacks_Suspended(void) +{ + +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBD_HAL.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBD_HAL.c new file mode 100644 index 000000000..b40f768ed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/USBD_HAL.c @@ -0,0 +1,2144 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + + \file + + Implementation of USB device functions on a UDP controller. + + See \ref usbd_api_method USBD API Methods. +*/ + +/** \addtogroup usbd_hal + *@{*/ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" +#include "USBD_HAL.h" + +#include +#include +#include +#include + +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ + +#define DMA + +/** Maximum number of endpoints interrupts. */ +#define NUM_IT_MAX 11 +/** Maximum number of endpoint DMA interrupts */ +#define NUM_IT_MAX_DMA \ + ((USBHS->UDPHS_IPFEATURES \ + & UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Msk) \ + >>UDPHS_IPFEATURES_DMA_CHANNEL_NBR_Pos) + +/** Bits that should be shifted to access interrupt bits. */ +#define SHIFT_INTERUPT 12 + +/** Max size of the FMA FIFO */ +#define DMA_MAX_FIFO_SIZE (65536/1) +/** fifo space size in DW */ +#define EPT_VIRTUAL_SIZE 16384 + +/** + * \section endpoint_states_sec "UDP Endpoint states" + * + * This page lists the endpoint states. + * + * \subsection States + * - UDPHS_ENDPOINT_DISABLED + * - UDPHS_ENDPOINT_HALTED + * - UDPHS_ENDPOINT_IDLE + * - UDPHS_ENDPOINT_SENDING + * - UDPHS_ENDPOINT_RECEIVING + * - UDPHS_ENDPOINT_SENDINGM + * - UDPHS_ENDPOINT_RECEIVINGM + */ + +/** Endpoint states: Endpoint is disabled */ +#define UDPHS_ENDPOINT_DISABLED 0 +/** Endpoint states: Endpoint is halted (i.e. STALLs every request) */ +#define UDPHS_ENDPOINT_HALTED 1 +/** Endpoint states: Endpoint is idle (i.e. ready for transmission) */ +#define UDPHS_ENDPOINT_IDLE 2 +/** Endpoint states: Endpoint is sending data */ +#define UDPHS_ENDPOINT_SENDING 3 +/** Endpoint states: Endpoint is receiving data */ +#define UDPHS_ENDPOINT_RECEIVING 4 +/** Endpoint states: Endpoint is sending MBL */ +#define UDPHS_ENDPOINT_SENDINGM 5 +/** Endpoint states: Endpoint is receiving MBL */ +#define UDPHS_ENDPOINT_RECEIVINGM 6 + + +/** Get Number of buffer in Multi-Buffer-List + * \param i input index + * \param o output index + * \param size list size + */ +#define MBL_NbBuffer(i, o, size) (((i)>(o))?((i)-(o)):((i)+(size)-(o))) + +/** Buffer list is full */ +#define MBL_FULL 1 +/** Buffer list is null */ +#define MBL_NULL 2 + +/*--------------------------------------------------------------------------- + * Types + *---------------------------------------------------------------------------*/ + +/** Describes header for UDP endpoint transfer. */ +typedef struct { + /** Optional callback to invoke when the transfer completes. */ + void* fCallback; + /** Optional argument to the callback function. */ + void* pArgument; + /** Transfer type */ + uint8_t transType; + /* Reserved to 32-b aligned */ + uint8_t reserved[3]; +} TransferHeader; + +/** Describes a transfer on a UDP endpoint. */ +typedef struct { + + /** Optional callback to invoke when the transfer completes. */ + TransferCallback fCallback; + /** Optional argument to the callback function. */ + void *pArgument; + /** Transfer type */ + uint8_t transType; + uint8_t reserved[3]; + /** Number of bytes which have been written into the UDP internal FIFO + * buffers. */ + int32_t buffered; + /** Pointer to a data buffer used for emission/reception. */ + uint8_t *pData; + /** Number of bytes which have been sent/received. */ + int32_t transferred; + /** Number of bytes which have not been buffered/transferred yet. */ + int32_t remaining; +} Transfer; + +/** Describes Multi Buffer List transfer on a UDP endpoint. */ +typedef struct { + /** Optional callback to invoke when the transfer completes. */ + MblTransferCallback fCallback; + /** Optional argument to the callback function. */ + void *pArgument; + /** Transfer type */ + uint8_t transType; + /** List state (OK, FULL, NULL) (run time) */ + uint8_t listState; + /** Multi-Buffer List size */ + uint16_t listSize; + /** Pointer to multi-buffer list */ + USBDTransferBuffer *pMbl; + /** Offset number of buffers to start transfer */ + uint16_t offsetSize; + /** Current processing buffer index (run time) */ + uint16_t outCurr; + /** Loaded buffer index (run time) */ + uint16_t outLast; + /** Current buffer for input (run time) */ + uint16_t inCurr; +} MblTransfer; + +/** + * Describes the state of an endpoint of the UDP controller. + */ +typedef struct { + + /* CSR */ + /** Current endpoint state. */ + volatile uint8_t state; + /** Current reception bank (0 or 1). */ + volatile uint8_t bank; + /** Maximum packet size for the endpoint. */ + volatile uint16_t size; + /** Describes an ongoing transfer (if current state is either + * UDPHS_ENDPOINT_SENDING or UDPHS_ENDPOINT_RECEIVING) */ + union { + TransferHeader transHdr; + Transfer singleTransfer; + MblTransfer mblTransfer; + } transfer; + /** Special case for send a ZLP */ + uint32_t sendZLP; +} Endpoint; + +/** + * DMA Descriptor. + */ +typedef struct { + void *pNxtDesc; + void *pAddr; + uint32_t dwCtrl; + uint32_t dw; +} UdphsDmaDescriptor; + +/*--------------------------------------------------------------------------- + * Internal variables + *---------------------------------------------------------------------------*/ + +/** Holds the internal state for each endpoint of the UDP. */ +static Endpoint endpoints[CHIP_USB_NUMENDPOINTS]; + +/** 7.1.20 Test Mode Support + * Test codes for the USB HS test mode. */ +static const char test_packet_buffer[] = { + 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, // JKJKJKJK * 9 + 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, // JJKKJJKK * 8 + 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, // JJJJKKKK * 8 + 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8 + 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, // JJJJJJJK * 8 + 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E // {JKKKKKKK * 10}, JK +}; + + + +/** DMA link list */ +COMPILER_ALIGNED(16) static UdphsDmaDescriptor dmaLL[5]; +COMPILER_ALIGNED(16) static UdphsDmaDescriptor *pDmaLL; + +/*--------------------------------------------------------------------------- + * Internal Functions + *---------------------------------------------------------------------------*/ + +/** + * Handles a completed transfer on the given endpoint, invoking the + * configured callback if any. + * \param bEndpoint Number of the endpoint for which the transfer has completed. + * \param bStatus Status code returned by the transfer operation + */ +static void UDPHS_EndOfTransfer(uint8_t bEndpoint, uint8_t bStatus) +{ + Endpoint *pEp = &(endpoints[bEndpoint]); + + /* Check that endpoint was sending or receiving data */ + if ( (pEp->state == UDPHS_ENDPOINT_RECEIVING) + || (pEp->state == UDPHS_ENDPOINT_SENDING) ) + { + Transfer *pXfr = (Transfer*)&(pEp->transfer); + uint32_t transferred = pXfr->transferred; + uint32_t remaining = pXfr->remaining + pXfr->buffered; + + TRACE_DEBUG_WP("EoT "); + if (pEp->state == UDPHS_ENDPOINT_SENDING) + pEp->sendZLP = 0; + pEp->state = UDPHS_ENDPOINT_IDLE; + pXfr->pData = 0; + pXfr->transferred = -1; + pXfr->buffered = -1; + pXfr->remaining = -1; + + /* Invoke callback */ + if (pXfr->fCallback) + { + pXfr->fCallback(pXfr->pArgument, bStatus, transferred, remaining); + } + else + { + TRACE_DEBUG_WP("NoCB "); + } + } + else if ( (pEp->state == UDPHS_ENDPOINT_RECEIVINGM) + || (pEp->state == UDPHS_ENDPOINT_SENDINGM) ) + { + MblTransfer *pXfr = (MblTransfer*)&(pEp->transfer); + TRACE_DEBUG_WP("EoMT "); + + pEp->state = UDPHS_ENDPOINT_IDLE; + pXfr->listState = 0; + pXfr->outCurr = pXfr->inCurr = pXfr->outLast = 0; + /* Invoke callback */ + if (pXfr->fCallback) + { + pXfr->fCallback(pXfr->pArgument, bStatus); + } + else + { + TRACE_DEBUG_WP("NoCB "); + } + } +} + +/** + * Update multi-buffer-transfer descriptors. + * \param pTransfer Pointer to instance MblTransfer. + * \param size Size of bytes that processed. + * \param forceEnd Force the buffer END. + * \return 1 if current buffer ended. + */ +static uint8_t UDPHS_MblUpdate(MblTransfer *pTransfer, + USBDTransferBuffer * pBi, + uint16_t size, + uint8_t forceEnd) +{ + /* Update transfer descriptor */ + pBi->remaining -= size; + /* Check if list NULL */ + if (pTransfer->listState == MBL_NULL) { + return 1; + } + /* Check if current buffer ended */ + if (pBi->remaining == 0 || forceEnd || size == 0) { + + /* Process to next buffer */ + if ((++ pTransfer->outCurr) == pTransfer->listSize) + pTransfer->outCurr = 0; + /* Check buffer NULL case */ + if (pTransfer->outCurr == pTransfer->inCurr) + pTransfer->listState = MBL_NULL; + else { + pTransfer->listState = 0; + /* Continue transfer, prepare for next operation */ + pBi = &pTransfer->pMbl[pTransfer->outCurr]; + pBi->buffered = 0; + pBi->transferred = 0; + pBi->remaining = pBi->size; + } + return 1; + } + return 0; +} + +/** + * Transfers a data payload from the current transfer buffer to the endpoint + * FIFO + * \param bEndpoint Number of the endpoint which is sending data. + */ +static uint8_t UDPHS_MblWriteFifo(uint8_t bEndpoint) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pTransfer = (MblTransfer*)&(pEndpoint->transfer); + USBDTransferBuffer *pBi = &(pTransfer->pMbl[pTransfer->outCurr]); + uint8_t *pFifo; + int32_t size; + + volatile uint8_t * pBytes; + volatile uint8_t bufferEnd = 1; + + /* Get the number of bytes to send */ + size = pEndpoint->size; + if (size > pBi->remaining) size = pBi->remaining; + + TRACE_DEBUG_WP("w%d.%d ", pTransfer->outCurr, size); + + /* Record last accessed buffer */ + pTransfer->outLast = pTransfer->outCurr; + + pBytes = &(pBi->pBuffer[pBi->transferred + pBi->buffered]); + pBi->buffered += size; + bufferEnd = UDPHS_MblUpdate(pTransfer, pBi, size, 0); + + /* Write packet in the FIFO buffer */ + pFifo = (uint8_t*)((uint32_t*)USBHS_RAM_ADDR + + (EPT_VIRTUAL_SIZE * bEndpoint)); + memory_sync(); + if (size) { + int32_t c8 = size >> 3; + int32_t c1 = size & 0x7; + for (; c8; c8 --) { + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + *(pFifo++) = *(pBytes ++); + } + for (; c1; c1 --) { + *(pFifo++) = *(pBytes ++); + } + } + return bufferEnd; +} + +#if 0 +/** + * Transfers a data payload from an endpoint FIFO to the current transfer + * buffer, if NULL packet received, the current buffer is ENDed. + * \param bEndpoint Endpoint number. + * \param wPacketSize Size of received data packet */ + * \return 1 if the buffer ENDed. */ + */ +static uint8_t UDPHS_MblReadFifo(uint8_t bEndpoint, uint16_t wPacketSize) +{ + + return 0; +} +*/ +#endif +/** + * Transfers a data payload from the current transfer buffer to the endpoint + * FIFO + * \param bEndpoint Number of the endpoint which is sending data. + */ +static void UDPHS_WritePayload(uint8_t bEndpoint, int32_t size) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + uint8_t *pFifo; + + /* Get the number of bytes to send */ + if (size > pTransfer->remaining) + { + size = pTransfer->remaining; + } + + /* Update transfer descriptor information */ + pTransfer->buffered += size; + pTransfer->remaining -= size; + + /* Write packet in the FIFO buffer */ + pFifo = (uint8_t*)((uint32_t*)USBHS_RAM_ADDR + + (EPT_VIRTUAL_SIZE * bEndpoint)); + memory_sync(); + for (; size; size --) + { + *(pFifo ++) = *(pTransfer->pData ++); + } + memory_sync(); + +} + +/** + * Transfers a data payload from an endpoint FIFO to the current transfer buffer + * \param bEndpoint Endpoint number. + * \param wPacketSize Size of received data packet + */ +static void UDPHS_ReadPayload(uint8_t bEndpoint, int32_t wPacketSize) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + Transfer *pTransfer = (Transfer*)&(pEndpoint->transfer); + uint8_t *pFifo; + /* Check that the requested size is not bigger than the remaining transfer */ + if (wPacketSize > pTransfer->remaining) { + + pTransfer->buffered += wPacketSize - pTransfer->remaining; + wPacketSize = pTransfer->remaining; + } + + /* Update transfer descriptor information */ + pTransfer->remaining -= wPacketSize; + pTransfer->transferred += wPacketSize; + + /* Retrieve packet */ + pFifo = (uint8_t*)((uint32_t*)USBHS_RAM_ADDR + + (EPT_VIRTUAL_SIZE * bEndpoint)); + while (wPacketSize > 0) + { + *(pTransfer->pData ++) = *(pFifo ++); + memory_sync(); + wPacketSize--; + } + +} + +/** + * Received SETUP packet from endpoint 0 FIFO + * \param pRequest Generic USB SETUP request sent over Control endpoints + */ +static void UDPHS_ReadRequest(USBGenericRequest *pRequest) +{ + uint32_t *pData = (uint32_t *)(void*)pRequest; + volatile uint32_t *pFifo; + pFifo = (volatile uint32_t*)USBHS_RAM_ADDR; + *pData ++ = *pFifo; + memory_sync(); + pFifo = (volatile uint32_t*)USBHS_RAM_ADDR; + *pData = *pFifo; + memory_sync(); +} + + +/** + * Endpoint interrupt handler. + * Handle IN/OUT transfers, received SETUP packets and STALLing + * \param bEndpoint Index of endpoint + */ +static void UDPHS_EndpointHandler(uint8_t bEndpoint) +{ + Usbhs *pUdp = USBHS; + + //UdphsDma *pDma = &pUdp->USBHS_DEVDMA[bEndpoint]; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + //MblTransfer *pMblt = (MblTransfer*)&(pEp->transfer); + uint32_t status = USBHS_ReadEPStatus(pUdp, bEndpoint, 0xFFFFFFFF); + uint32_t type = USBHS_GetEpType(pUdp, bEndpoint); + uint32_t reqBuf[2]; + USBGenericRequest *pReq = (USBGenericRequest *)reqBuf; + uint16_t wPktSize; + + + TRACE_DEBUG_WP("Ep%d ", bEndpoint); + /* IN packet sent */ + if ( ( status & USBHS_DEVEPTISR_TXINI) && USBHS_IsEpIntEnable(pUdp, bEndpoint, USBHS_DEVEPTIMR_TXINE)) + { + TRACE_DEBUG_WP("Wr "); + + /* Multi-buffer-list transfer state */ + if ( pEp->state == UDPHS_ENDPOINT_SENDINGM ) + { + } + /* Sending state */ + else if ( pEp->state == UDPHS_ENDPOINT_SENDING ) + { + if (pXfr->buffered) + { + pXfr->transferred += pXfr->buffered; + pXfr->buffered = 0; + } + if((pXfr->transferred % pEp->size == 0) && ( pXfr->remaining == 0) && ( pXfr->transferred > 0)&&(pEp->sendZLP == 0)) + { + pEp->sendZLP = 1; // Force ZLP transmission in total length is a multiple of endpoint size + } + if ( pXfr->buffered == 0 + && pXfr->transferred == 0 + && pXfr->remaining == 0 + && pEp->sendZLP == 0 ) + { + pEp->sendZLP = 1; + } + + /* End of Xfr ? */ + if ( pXfr->remaining || pEp->sendZLP == 1) + { + if(pEp->sendZLP == 1) + { + // A null packet will be send, keep trace of it : Change this value only if ZLP will be send!!! + pEp->sendZLP = 2; + } + + /* Transfer remaining */ + TRACE_DEBUG_WP("%d ", pEp->size); + /* Send next packet */ + UDPHS_WritePayload(bEndpoint, pEp->size); + USBHS_AckEpInterrupt(USBHS, 0, USBHS_DEVEPTICR_TXINIC); + + } + else + { + TRACE_DEBUG_WP("l%d ", pXfr->transferred); + /* Disable interrupt on non-control EP */ + if (type != USBHS_DEVEPTCFG_EPTYPE_CTRL) + { + USBHS_DisableIntEP(pUdp, bEndpoint); + } + + USBHS_DisableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIDR_TXINEC); + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + + pEp->sendZLP = 0; + } + } + else + { + TRACE_DEBUG("Err Wr %d\n\r", pEp->sendZLP); + } + } + /* OUT packet received */ + if ( USBHS_DEVEPTISR_RXOUTI & status ) + { + TRACE_DEBUG_WP("Rd "); + + /* NOT in receiving state */ + if (pEp->state != UDPHS_ENDPOINT_RECEIVING) + { + /* Check if ACK received on a Control EP */ + if ( (USBHS_DEVEPTCFG_EPTYPE_CTRL == type) + && (0 == (status & USBHS_DEVEPTISR_BYCT_Msk)) ) + { + TRACE_INFO_WP("Ack "); + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_RXOUTIC); + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + + } + /* data has been STALLed */ + else if (USBHS_DEVEPTISR_STALLEDI & status) + { + TRACE_INFO_WP("Discard "); + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_RXOUTIC); + } + /* NAK the data */ + else + { + TRACE_INFO_WP("Nak "); + USBHS_DisableIntEP(pUdp, bEndpoint); + } + } + /* In read state */ + else + { + wPktSize = USBHS_ByteCount(pUdp, bEndpoint); + + TRACE_DEBUG_WP("%d ", wPktSize); + UDPHS_ReadPayload(bEndpoint, wPktSize); + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_RXOUTIC); + + /* Check if transfer is finished */ + if (pXfr->remaining == 0 || wPktSize < pEp->size) + { + USBHS_DisableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIDR_RXOUTEC); + + /* Disable interrupt if not control EP */ + if (USBHS_DEVEPTCFG_EPTYPE_CTRL != type) + { + USBHS_DisableIntEP(pUdp, bEndpoint); + } + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_NAKINIC); + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_TXINIC); + } + } + } + /* STALL sent */ + if ( USBHS_DEVEPTISR_STALLEDI & status ) + { + /* Acknowledge */ + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_STALLEDIC); + + /* ISO error */ + if (type == USBHS_DEVEPTCFG_EPTYPE_ISO) + { + TRACE_WARNING("IsoE[%d]\n\r", bEndpoint); + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + } + /* If EP is not halted, clear STALL */ + else + { + TRACE_WARNING("Stall[%d]\n\r", bEndpoint); + + if (pEp->state != UDPHS_ENDPOINT_HALTED) + { + USBHS_DisableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIDR_STALLRQC); + } + } + } + /* SETUP packet received */ + if ( USBHS_DEVEPTISR_RXSTPI & status ) + { + /* If a transfer was pending, complete it + Handles the case where during the status phase of a control write + transfer, the host receives the device ZLP and ack it, but the ack + is not received by the device */ + if (pEp->state == UDPHS_ENDPOINT_RECEIVING + || pEp->state == UDPHS_ENDPOINT_RECEIVINGM + || pEp->state == UDPHS_ENDPOINT_SENDING + || pEp->state == UDPHS_ENDPOINT_SENDINGM) + { + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_SUCCESS); + } + + /* ISO Err Flow */ + if (type == USBHS_DEVEPTCFG_EPTYPE_ISO) + { + TRACE_WARNING("IsoFE[%d]\n\r", bEndpoint); + /* Acknowledge setup packet */ + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_RXSTPIC); + } + else + { + TRACE_DEBUG_WP("Stup "); + /* Copy setup */ + UDPHS_ReadRequest(pReq); + /* Acknowledge setup packet */ + USBHS_AckEpInterrupt(pUdp, bEndpoint, USBHS_DEVEPTICR_RXSTPIC); + + /* Handler */ + USBD_RequestHandler(bEndpoint, pReq); + + } + } +} +#ifdef DMA +/** + * DMA Single transfer + * \param bEndpoint EP number. + * \pXfr Pointer to transfer instance. + * \dwCfg DMA Control configuration (excluding length). + */ +static inline void UDPHS_DmaSingle(uint8_t bEndpoint, Transfer *pXfr, uint32_t dwCfg) +{ + Usbhs *pUdp = USBHS; + UsbhsDevdma *pUsbDma = &pUdp->USBHS_DEVDMA[bEndpoint]; + + /* Single transfer */ + SCB_CleanInvalidateDCache(); + + USBHS_SetDmaBuffAdd(pUsbDma, (uint32_t)&pXfr->pData[pXfr->transferred]); + USBHS_GetDmaStatus(pUsbDma); + + + TRACE_DEBUG_WP("Dma[B%d:T%d] ", pXfr->buffered, pXfr->transferred); + /* DMA Configure */ + USBHS_ConfigureDma(pUsbDma, 0); + USBHS_ConfigureDma(pUsbDma, (USBHS_DEVDMACONTROL_BUFF_LENGTH(pXfr->buffered) | dwCfg) ); + + /* Interrupt enable */ + USBHS_EnableDMAIntEP(pUdp, bEndpoint); +} +/** + * Endpoint DMA interrupt handler. + * This function handles DMA interrupts. + * \param bEndpoint Index of endpoint + */ +static void UDPHS_DmaHandler(uint8_t bEndpoint) +{ + Usbhs *pUdp = USBHS; + uint8_t bDmaEndpoint = bEndpoint -1; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + + uint32_t dwDmaSr; + int32_t iRemain, iXfred; + uint8_t bRc = USBD_STATUS_SUCCESS; + UsbhsDevdma *pUsbDma = &pUdp->USBHS_DEVDMA[bDmaEndpoint]; + + dwDmaSr = USBHS_GetDmaStatus(pUsbDma); + TRACE_DEBUG_WP("iDma%d,%x ", bDmaEndpoint, dwDmaSr); + /* Mbl transfer */ + if (pEp->state == UDPHS_ENDPOINT_SENDINGM) + { + /* Not implemented */ + return; + } + else if (pEp->state == UDPHS_ENDPOINT_RECEIVINGM) + { + /* Not implemented */ + return; + } + + /* Disable DMA interrupt to avoid receiving 2 (B_EN and TR_EN) */ + pUdp->USBHS_DEVDMA[bDmaEndpoint].USBHS_DEVDMACONTROL &= ~(USBHS_DEVDMACONTROL_END_TR_EN + |USBHS_DEVDMACONTROL_END_B_EN); + SCB_CleanInvalidateDCache(); + if (USBHS_DEVDMASTATUS_END_BF_ST & dwDmaSr) + { + TRACE_DEBUG_WP("EoDmaB "); + /* BUFF_COUNT holds the number of untransmitted bytes. + BUFF_COUNT is equal to zero in case of good transfer */ + iRemain = (dwDmaSr & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos; + TRACE_DEBUG_WP("C%d ", iRemain); + iXfred = pXfr->buffered - iRemain; + + pXfr->transferred += iXfred; + pXfr->buffered = iRemain; + pXfr->remaining -= iXfred; + TRACE_DEBUG_WP("[B%d:T%d:R%d] ", pXfr->buffered, pXfr->transferred, pXfr->remaining); + /* There is still data */ + if (pXfr->remaining + pXfr->buffered > 0) + { + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + { + pXfr->buffered = DMA_MAX_FIFO_SIZE; + } + else + { + pXfr->buffered = pXfr->remaining; + } + /* Single transfer again */ + UDPHS_DmaSingle(bDmaEndpoint, pXfr, USBHS_DEVDMACONTROL_END_TR_EN + | USBHS_DEVDMACONTROL_END_TR_IT + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT + | USBHS_DEVDMACONTROL_CHANN_ENB); + } + } + else if (USBHS_DEVDMASTATUS_END_TR_ST & dwDmaSr) + { + TRACE_DEBUG_WP("EoDmaT "); + pXfr->transferred = pXfr->buffered - + ((dwDmaSr & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) + >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos); + pXfr->remaining = 0; + + TRACE_DEBUG_WP("[B%d:T%d] ", pXfr->buffered, pXfr->transferred); + } + else + { + TRACE_ERROR("UDPHS_DmaHandler: ST 0x%X\n\r", (unsigned int)dwDmaSr); + bRc = USBD_STATUS_ABORTED; + } + /* Callback */ + if (pXfr->remaining == 0) + { + UDPHS_EndOfTransfer(bEndpoint, bRc); + + } + +} +#endif +/** + * Sends data through a USB endpoint. Sets up the transfer descriptor, + * writes one or two data payloads (depending on the number of FIFO bank + * for the endpoint) and then starts the actual transfer. The operation is + * complete when all the data has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param pEndpoint Pointer to Endpoint struct. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +static inline uint8_t UDPHS_Write(uint8_t bEndpoint, + const void *pData, + uint32_t dLength) +{ + Usbhs *pUdp = USBHS; + uint8_t bDmaEndpoint = bEndpoint -1; + + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + /* Return if busy */ + if (pEp->state != UDPHS_ENDPOINT_IDLE) + { + return USBD_STATUS_LOCKED; + } + /* Sending state */ + pEp->state = UDPHS_ENDPOINT_SENDING; + TRACE_DEBUG_WP("Wr%d(%d) ", bEndpoint, dLength); + pEp->sendZLP = 0; + /* Setup transfer descriptor */ + pXfr->pData = (void*) pData; + pXfr->remaining = dLength; + pXfr->buffered = 0; + pXfr->transferred = 0; + + #ifdef DMA + SCB_CleanInvalidateDCache(); + /* 1. DMA supported, 2. Not ZLP */ + if (CHIP_USB_ENDPOINTS_DMA(bEndpoint) + && pXfr->remaining > 0) + { + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + { + /* Transfer the max */ + pXfr->buffered = DMA_MAX_FIFO_SIZE; + } + else + { + /* Good size */ + pXfr->buffered = pXfr->remaining; + } + /* Single transfer */ + UDPHS_DmaSingle(bDmaEndpoint, pXfr, USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT + | USBHS_DEVDMACONTROL_CHANN_ENB); + return USBD_STATUS_SUCCESS; + } + #endif + + /* Enable IT */ + USBHS_EnableIntEP(pUdp, bEndpoint ); + USBHS_EnableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIER_TXINES); + return USBD_STATUS_SUCCESS; +} + +/** + * Sends data through a USB endpoint. Sets up the transfer descriptor list, + * writes one or two data payloads (depending on the number of FIFO bank + * for the endpoint) and then starts the actual transfer. The operation is + * complete when all the transfer buffer in the list has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param pEndpoint Pointer to Endpoint struct. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +static inline uint8_t UDPHS_AddWr(uint8_t bEndpoint, + const void *pData, + uint32_t dLength) +{ + Usbhs *pUdp = USBHS; + + Endpoint *pEp = &(endpoints[bEndpoint]); + MblTransfer *pMbl = (MblTransfer*)&(pEp->transfer); + USBDTransferBuffer *pTx; + /* Check parameter */ + if (dLength >= 0x10000) + { + return USBD_STATUS_INVALID_PARAMETER; + } + /* Data in process */ + if (pEp->state > UDPHS_ENDPOINT_IDLE) + { /* MBL transfer */ + if (pMbl->transType) + { + if (pMbl->listState == MBL_FULL) + { + return USBD_STATUS_LOCKED; + } + } + else + { + return USBD_STATUS_LOCKED; + } + } + + TRACE_DEBUG_WP("AddW%d(%d) ", bEndpoint, dLength); + /* Add buffer to buffer list and update index */ + pTx = &(pMbl->pMbl[pMbl->inCurr]); + pTx->pBuffer = (uint8_t*)pData; + pTx->size = pTx->remaining = dLength; + pTx->transferred = pTx->buffered = 0; + /* Update input index */ + if (pMbl->inCurr >= (pMbl->listSize-1)) pMbl->inCurr = 0; + else pMbl->inCurr ++; + if (pMbl->inCurr == pMbl->outCurr) pMbl->listState = MBL_FULL; + else pMbl->listState = 0; + /* Start sending when offset achieved */ + if (MBL_NbBuffer(pMbl->inCurr, pMbl->outCurr, pMbl->listSize) + >= pMbl->offsetSize + && pEp->state == UDPHS_ENDPOINT_IDLE) + { + uint8_t nbBanks = CHIP_USB_ENDPOINTS_BANKS(bEndpoint); + + /* Change state */ + pEp->state = UDPHS_ENDPOINT_SENDINGM; + + TRACE_DEBUG_WP("StartM "); + + /* Fill data into FIFO */ + for (; + nbBanks && pMbl->pMbl[pMbl->inCurr].remaining; + nbBanks --) + { + UDPHS_MblWriteFifo(bEndpoint); + USBHS_RaiseEPInt(pUdp, bEndpoint, USBHS_DEVEPTIFR_TXINIS); + } + + /* Enable interrupt */ + USBHS_EnableIntEP(pUdp, bEndpoint); + USBHS_EnableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIER_TXINES); + + } + + return USBD_STATUS_SUCCESS; +} + +/** + * Reads incoming data on an USB endpoint This methods sets the transfer + * descriptor and activate the endpoint interrupt. The actual transfer is + * then carried out by the endpoint interrupt handler. The Read operation + * finishes either when the buffer is full, or a short packet (inferior to + * endpoint maximum size) is received. + * + * *The buffer must be kept allocated until the transfer is finished*. + * \param bEndpoint Endpoint number. + * \param pData Pointer to a data buffer. + * \param dLength Size of the data buffer in bytes. + * \return USBD_STATUS_SUCCESS if the read operation has been started; + * otherwise, the corresponding error code. + */ +static inline uint8_t UDPHS_Read(uint8_t bEndpoint, + void *pData, + uint32_t dLength) +{ + Usbhs *pUdp = USBHS; + uint8_t bDmaEndpoint = (bEndpoint-1); + Endpoint *pEp = &(endpoints[bEndpoint]); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + /* Return if busy */ + if (pEp->state != UDPHS_ENDPOINT_IDLE) + { + return USBD_STATUS_LOCKED; + } + /* Receiving state */ + pEp->state = UDPHS_ENDPOINT_RECEIVING; + + TRACE_DEBUG_WP("Rd%d(%d) ", bEndpoint, dLength); + /* Setup transfer descriptor */ + pXfr->pData = (void*) pData; + pXfr->remaining = dLength; + pXfr->buffered = 0; + pXfr->transferred = 0; + + #ifdef DMA + SCB_CleanInvalidateDCache(); + /* If: 1. DMA supported, 2. Has data */ + if (CHIP_USB_ENDPOINTS_DMA(bEndpoint) + && pXfr->remaining > 0) + { + /* DMA XFR size adjust */ + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + pXfr->buffered = DMA_MAX_FIFO_SIZE; + else + pXfr->buffered = pXfr->remaining; + /* Single transfer */ + UDPHS_DmaSingle(bDmaEndpoint, pXfr, USBHS_DEVDMACONTROL_END_TR_EN + | USBHS_DEVDMACONTROL_END_TR_IT + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT + | USBHS_DEVDMACONTROL_CHANN_ENB); + return USBD_STATUS_SUCCESS; + } + #endif + + /* Enable IT */ + USBHS_EnableIntEP(pUdp, bEndpoint); + USBHS_EnableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIER_RXOUTES); + + return USBD_STATUS_SUCCESS; +} +#if 0 +/** + * Reads incoming data on an USB endpoint This methods sets the transfer + * descriptor and activate the endpoint interrupt. The actual transfer is + * then carried out by the endpoint interrupt handler. The Read operation + * finishes either when the buffer is full, or a short packet (inferior to + * endpoint maximum size) is received. + * + * *The buffer must be kept allocated until the transfer is finished*. + * \param bEndpoint Endpoint number. + * \param pData Pointer to a data buffer. + * \param dLength Size of the data buffer in bytes. + * \return USBD_STATUS_SUCCESS if the read operation has been started; + * otherwise, the corresponding error code. + */ +static inline uint8_t UDPHS_AddRd(uint8_t bEndpoint, + void *pData, + uint32_t dLength) +{ + return USBD_STATUS_SW_NOT_SUPPORTED; +} +#endif +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ +/** + * USBD (UDP) interrupt handler + * Manages device resume, suspend, end of bus reset. + * Forwards endpoint events to the appropriate handler. + */ +void USBHS_Handler(void) +{ + Usbhs *pUdp = USBHS; + + uint32_t status, IntStatus; + uint8_t numIt; + + status = USBHS_ReadIntStatus(pUdp, 0xFFFFFFFF); + IntStatus = status & USBHS_IsIntEnable(pUdp, 0xFFFFFFFF); + + + /* Handle all USBHS interrupts */ + TRACE_DEBUG_WP("\n\r%c ", USBD_HAL_IsHighSpeed() ? 'H' : 'F'); + //while( status ) + { + /* SOF */ + if (IntStatus & USBHS_DEVISR_SOF) + { + TRACE_DEBUG_WP("SOF "); + /* SOF handler */ + + /* Acknowledge interrupt */ + USBHS_AckInt(pUdp, USBHS_DEVICR_SOFC); + status &= ~(uint32_t)USBHS_DEVISR_SOF; + } + /* MSOF*/ + else if (IntStatus & USBHS_DEVISR_MSOF) + { + TRACE_DEBUG_WP("Mosf "); + + /* Acknowledge interrupt */ + USBHS_AckInt(pUdp, USBHS_DEVICR_MSOFC); + + } + /* Suspend, treated last */ + else if (IntStatus & USBHS_DEVISR_SUSP) + { + TRACE_WARNING_WP("Susp "); + USBHS_FreezeClock(pUdp, false); + USBHS_DisableInt(pUdp, USBHS_DEVIDR_SUSPEC); + + /* Enable wakeup */ + USBHS_EnableInt(pUdp, USBHS_DEVIER_WAKEUPES ); + + USBHS_FreezeClock(pUdp, true); // Mandatory to exit of sleep mode after a wakeup event + /* Acknowledge interrupt */ + //USBHS_AckInt(pUdp, (USBHS_DEVICR_SUSPC | USBHS_DEVICR_WAKEUPC) ); + + USBD_SuspendHandler(); + } + /* Wake up */ + else if (IntStatus & USBHS_DEVISR_WAKEUP) + { + + TRACE_INFO_WP("Rsm "); + USBHS_FreezeClock(pUdp, false); + + while( !USBHS_ISUsableClock(pUdp) ) + { + if(status & USBHS_DEVISR_SUSP) + { + break; // In case of USB state change in HS + } + } + + /* Acknowledge interrupt */ + /*USBHS_AckInt(pUdp, (USBHS_DEVICR_SUSPC | + USBHS_DEVICR_WAKEUPC | + USBHS_DEVICR_EORSMC) );*/ + + USBHS_DisableInt(pUdp, USBHS_DEVIDR_WAKEUPEC); + USBHS_EnableInt(pUdp, USBHS_DEVIER_SUSPES ); + //USBHS_AckInt(pUdp, (USBHS_DEVIER_EORSMES | USBHS_DEVICR_WAKEUPC) ); + + + } + /* Bus reset */ + else if (IntStatus & USBHS_DEVISR_EORST) + { + TRACE_DEBUG_WP("EoB "); + + /* Acknowledge interrupt */ + USBHS_AckInt(pUdp, USBHS_DEVICR_EORSTC); + /* Flush and enable the suspend interrupt */ + USBHS_AckInt(pUdp, (USBHS_DEVICR_SUSPC | USBHS_DEVICR_WAKEUPC) ); + USBHS_EnableInt(pUdp, USBHS_DEVIER_SUSPES ); + + /* Reset handler */ + USBD_ResetHandler(); + + + } + /* Upstream resume */ + else if (IntStatus & USBHS_DEVISR_UPRSM) + { + TRACE_DEBUG_WP("ExtRes "); + /* Acknowledge interrupt */ + USBHS_AckInt(pUdp, USBHS_DEVICR_UPRSMC); + } + + /* Endpoints */ + else + { + #ifdef DMA + for (numIt = 0; numIt < NUM_IT_MAX; numIt ++) + { + if (CHIP_USB_ENDPOINTS_DMA(numIt)) + { + if (IntStatus & (USBHS_DEVIMR_DMA_1 << (numIt - 1) )) + { + UDPHS_DmaHandler(numIt); + } + } + else if (IntStatus & (USBHS_DEVISR_PEP_0 << numIt)) + { + UDPHS_EndpointHandler(numIt); + } + memory_sync(); + } + + #else + for (numIt = 0; numIt < NUM_IT_MAX; numIt ++) + { + if (IntStatus & (USBHS_DEVISR_PEP_0 << numIt)) + { + UDPHS_EndpointHandler(numIt); + } + memory_sync(); + } + #endif + } + + /* Update interrupt status */ + //status = USBHS_ReadIntStatus(pUdp, 0xFFFFFFFF); + //status &= USBHS_IsIntEnable(pUdp, 0xFFFFFFFF); + + TRACE_DEBUG_WP("\n\r"); + if (status) + { + TRACE_DEBUG_WP(" - "); + } + } + //NVIC_ClearPendingIRQ(USBHS_IRQn); // clear l'IRQ + memory_sync(); + +} + +/** + * \brief Reset endpoints and disable them. + * -# Terminate transfer if there is any, with given status; + * -# Reset the endpoint & disable it. + * \param bmEPs Bitmap for endpoints to reset. + * \param bStatus Status passed to terminate transfer on endpoint. + * \param bKeepCfg 1 to keep old endpoint configuration. + * \note Use USBD_HAL_ConfigureEP() to configure and enable endpoint + if not keeping old configuration. + * \sa USBD_HAL_ConfigureEP(). + */ +void USBD_HAL_ResetEPs(uint32_t bmEPs, uint8_t bStatus, uint8_t bKeepCfg) +{ + Usbhs *pUdp = USBHS; + + Endpoint *pEndpoint; + uint32_t tmp = bmEPs & ((1<USBHS_DEVIDR |= (epBit << SHIFT_INTERUPT); + /* Kill pending Banks ?? */ + #if 0 + while(USBHS_IsBankFree(pUdp, ep) > 0) + { + USBHS_KillBank(pUdp, ep); + while(USBHS_IsBankKilled(pUdp, ep)); + } + #endif + + /* Reset transfer information */ + pEndpoint = &(endpoints[ep]); + /* Reset endpoint state */ + pEndpoint->bank = 0; + /* Endpoint configure */ + epCfg = pUdp->USBHS_DEVEPTCFG[ep]; + /* Reset endpoint */ +// USBHS_ResetEP(pUdp, epBit); + /* Restore configure */ + if (bKeepCfg) + { + pUdp->USBHS_DEVEPTCFG[ep] = epCfg; + } + else + { + pEndpoint->state = UDPHS_ENDPOINT_DISABLED; + } + + /* Terminate transfer on this EP */ + UDPHS_EndOfTransfer(ep, bStatus); + } + epBit <<= 1; + } +} + +/** + * Cancel pending READ/WRITE + * \param bmEPs Bitmap for endpoints to reset. + * \note EP callback is invoked with USBD_STATUS_CANCELED. + */ +void USBD_HAL_CancelIo(uint32_t bmEPs) +{ + Usbhs *pUdp = USBHS; + //UdphsEpt *pHwEp = NULL; + + uint32_t tmp = bmEPs & ((1<UDPHS_EPT[ep]; + + /* Disable ISR */ + pUdp->USBHS_DEVIDR |= (epBit << SHIFT_INTERUPT); + /* Kill pending Banks ?? */ + #if 0 + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + pHwEp->UDPHS_EPTSETSTA = UDPHS_EPTSETSTA_KILL_BANK; + #endif + + /* Terminate transfer on this EP */ + UDPHS_EndOfTransfer(ep, USBD_STATUS_CANCELED); + } + epBit <<= 1; + } +} + +/** + * Configures an endpoint according to its endpoint Descriptor. + * \param pDescriptor Pointer to an endpoint descriptor. + * \return The endpoint address. + */ +uint8_t USBD_HAL_ConfigureEP(const USBEndpointDescriptor *pDescriptor) +{ + Usbhs *pUdp = USBHS; + + Endpoint *pEndpoint; + uint8_t bEndpoint; + uint8_t bType; + uint8_t bEndpointDir; + uint8_t bNbTrans = 1; + uint8_t bSizeEpt = 0; + uint8_t bHs = ((USBHS_GetUsbSpeed(pUdp) == USBHS_SR_SPEED_HIGH_SPEED)? true: false ); + + /* NULL descriptor -> Control endpoint 0 */ + if (pDescriptor == 0) + { + + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + bType = USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size = CHIP_USB_ENDPOINTS_MAXPACKETSIZE(0); + pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(0); + } + /* Device descriptor -> Control endpoint 0 */ + else if (pDescriptor->bDescriptorType == USBGenericDescriptor_DEVICE) + { + USBDeviceDescriptor *pDevDesc = (USBDeviceDescriptor*)pDescriptor; + bEndpoint = 0; + pEndpoint = &(endpoints[bEndpoint]); + bType = USBEndpointDescriptor_CONTROL; + bEndpointDir = 0; + pEndpoint->size =pDevDesc->bMaxPacketSize0; + pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(0); + } + /* Endpoint descriptor */ + else + { + /* The endpoint number */ + bEndpoint = USBEndpointDescriptor_GetNumber(pDescriptor); + pEndpoint = &(endpoints[bEndpoint]); + /* Transfer type: Control, Isochronous, Bulk, Interrupt */ + bType = USBEndpointDescriptor_GetType(pDescriptor); + /* Direction, ignored for control endpoints */ + bEndpointDir = USBEndpointDescriptor_GetDirection(pDescriptor); + pEndpoint->size = USBEndpointDescriptor_GetMaxPacketSize(pDescriptor); + pEndpoint->bank = CHIP_USB_ENDPOINTS_BANKS(bEndpoint); + + /* Convert descriptor value to EP configuration */ + if (bHs) { /* HS Interval, *125us */ + + /* MPS: Bit12,11 specify NB_TRANS, as USB 2.0 Spec. */ + bNbTrans = ((pEndpoint->size >> 11) & 0x3); + if(CHIP_USB_ENDPOINTS_HBW(bEndpoint)) + { + if (bNbTrans == 3) + bNbTrans = 1; + else + bNbTrans ++; + } + else + { + bNbTrans = 0; + } + + + /* Mask, bit 10..0 is the size */ + pEndpoint->size &= 0x7FF; + } + } + + TRACE_DEBUG_WP("CfgE%d ", bEndpoint); + + /* Abort the current transfer is the endpoint was configured and in + Write or Read state */ + if( (pEndpoint->state == UDPHS_ENDPOINT_RECEIVING) + || (pEndpoint->state == UDPHS_ENDPOINT_SENDING) + || (pEndpoint->state == UDPHS_ENDPOINT_RECEIVINGM) + || (pEndpoint->state == UDPHS_ENDPOINT_SENDINGM) ) { + + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_RESET); + } + pEndpoint->state = UDPHS_ENDPOINT_IDLE; + + + /* Configure endpoint size */ + if( pEndpoint->size <= 8 ) + bSizeEpt = 0; + else if ( pEndpoint->size <= 16 ) + bSizeEpt = 1; + else if ( pEndpoint->size <= 32 ) + bSizeEpt = 2; + else if ( pEndpoint->size <= 64 ) + bSizeEpt = 3; + else if ( pEndpoint->size <= 128 ) + bSizeEpt = 4; + else if ( pEndpoint->size <= 256 ) + bSizeEpt = 5; + else if ( pEndpoint->size <= 512 ) + bSizeEpt = 6; + else if ( pEndpoint->size <= 1024 ) + bSizeEpt = 7; + + /* Configure endpoint */ + if (bType == USBEndpointDescriptor_CONTROL) + { + USBHS_EnableIntEP(pUdp, bEndpoint); + } + + USBHS_ConfigureEPs(pUdp, bEndpoint, bType, bEndpointDir, bSizeEpt, ((pEndpoint->bank) - 1)); + + USBHS_AllocateMemory(pUdp, bEndpoint); + while( (USBHS_DEVEPTISR_CFGOK & pUdp->USBHS_DEVEPTISR[bEndpoint]) == 0 ) { + + /* resolved by clearing the reset IT in good place */ + TRACE_ERROR("PB bEndpoint: 0x%X\n\r", bEndpoint); + TRACE_ERROR("PB bSizeEpt: 0x%X\n\r", bSizeEpt); + TRACE_ERROR("PB bEndpointDir: 0x%X\n\r", bEndpointDir); + TRACE_ERROR("PB bType: 0x%X\n\r", bType); + TRACE_ERROR("PB pEndpoint->bank: 0x%X\n\r", pEndpoint->bank); + TRACE_ERROR("PB UDPHS_EPTCFG: 0x%X\n\r", (unsigned int)pUdp->USBHS_DEVEPTCFG[bEndpoint]); + for(;;); + } + + if (bType == USBEndpointDescriptor_CONTROL) + { + // enable Endpoint + USBHS_EnableEP(pUdp, bEndpoint, true); + // Enable Ep interrupt type + USBHS_EnableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIER_RXOUTES | USBHS_DEVEPTIER_RXSTPES ); + // enable endpoint interrupt + USBHS_EnableIntEP(pUdp, bEndpoint); + } + else + { +#ifndef DMA + USBHS_EnableEP(pUdp, bEndpoint, true); +#else + USBHS_EnableEP(pUdp, bEndpoint, true); + if (bType == USBEndpointDescriptor_ISOCHRONOUS) + { + USBHS_SetIsoTrans(pUdp, bEndpoint, bNbTrans); + } + USBHS_AutoSwitchBankEnable(pUdp, bEndpoint, true); +#endif + } + + //TRACE_DEBUG_WP("<%x,%x,%x> ", pEpt->UDPHS_EPTCFG, pEpt->UDPHS_EPTCTL, pEpt->UDPHS_EPTSTA); + return bEndpoint; +} + +/** + * Set callback for a USB endpoint for transfer (read/write). + * + * \param bEP Endpoint number. + * \param fCallback Optional callback function to invoke when the transfer is + * complete. + * \param pCbData Optional pointer to data to the callback function. + * \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED if endpoint is busy. + */ +uint8_t USBD_HAL_SetTransferCallback(uint8_t bEP, + TransferCallback fCallback, + void *pCbData) +{ + Endpoint *pEndpoint = &(endpoints[bEP]); + TransferHeader *pTransfer = (TransferHeader*)&(pEndpoint->transfer); + /* Check that the endpoint is not transferring */ + if (pEndpoint->state > UDPHS_ENDPOINT_IDLE) { + return USBD_STATUS_LOCKED; + } + TRACE_DEBUG_WP("sXfrCb "); + /* Setup the transfer callback and extension data */ + pTransfer->fCallback = (void*)fCallback; + pTransfer->pArgument = pCbData; + return USBD_STATUS_SUCCESS; +} + +/** + * Configure an endpoint to use multi-buffer-list transfer mode. + * The buffers can be added by _Read/_Write function. + * \param pMbList Pointer to a multi-buffer list used, NULL to disable MBL. + * \param mblSize Multi-buffer list size (number of buffers can be queued) + * \param startOffset When number of buffer achieve this offset transfer start + */ +uint8_t USBD_HAL_SetupMblTransfer( uint8_t bEndpoint, + USBDTransferBuffer* pMbList, + uint16_t mblSize, + uint16_t startOffset) +{ + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + MblTransfer *pXfr = (MblTransfer*)&(pEndpoint->transfer); + uint16_t i; + /* Check that the endpoint is not transferring */ + if (pEndpoint->state > UDPHS_ENDPOINT_IDLE) { + return USBD_STATUS_LOCKED; + } + TRACE_DEBUG_WP("sMblXfr "); + /* Enable Multi-Buffer Transfer List */ + if (pMbList) { + /* Reset list items */ + for (i = 0; i < mblSize; i --) { + pMbList[i].pBuffer = NULL; + pMbList[i].size = 0; + pMbList[i].transferred = 0; + pMbList[i].buffered = 0; + pMbList[i].remaining = 0; + } + /* Setup transfer */ + pXfr->transType = 1; + pXfr->listState = 0; /* OK */ + pXfr->listSize = mblSize; + pXfr->pMbl = pMbList; + pXfr->outCurr = pXfr->outLast = 0; + pXfr->inCurr = 0; + pXfr->offsetSize = startOffset; + } + /* Disable Multi-Buffer Transfer */ + else { + pXfr->transType = 0; + pXfr->pMbl = NULL; + pXfr->listSize = 0; + pXfr->offsetSize = 1; + } + return USBD_STATUS_SUCCESS; +} + +/** + * Sends data through a USB endpoint. Sets up the transfer descriptor, + * writes one or two data payloads (depending on the number of FIFO bank + * for the endpoint) and then starts the actual transfer. The operation is + * complete when all the data has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param bEndpoint Endpoint number. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +uint8_t USBD_HAL_Write( uint8_t bEndpoint, + const void *pData, + uint32_t dLength) +{ + if (endpoints[bEndpoint].transfer.transHdr.transType) + return UDPHS_AddWr(bEndpoint, pData, dLength); + else + return UDPHS_Write(bEndpoint, pData, dLength); +} + +/** + * Special write function. + * Sends data through a USB endpoint. Sets up the transfer descriptor, + * writes header and one or two data payloads (depending on the number of + * FIFO bank for the endpoint) and then starts the actual transfer. The + * operation is complete when all the data has been sent. + * + * *If the size of the buffer is greater than the size of the endpoint + * (or twice the size if the endpoint has two FIFO banks), then the buffer + * must be kept allocated until the transfer is finished*. This means that + * it is not possible to declare it on the stack (i.e. as a local variable + * of a function which returns after starting a transfer). + * + * \param bEndpoint Endpoint number. + * \param pData Pointer to a buffer with the data to send. + * \param dLength Size of the data buffer. + * \return USBD_STATUS_SUCCESS if the transfer has been started; + * otherwise, the corresponding error status code. + */ +uint8_t USBD_HAL_WrWithHdr(uint8_t bEndpoint, + const void * pHdr, uint8_t bHdrLen, + const void * pData,uint32_t dLength) +{ + Usbhs *pUdp = USBHS; + + Endpoint *pEp = &(endpoints[bEndpoint]); + uint8_t bDmaEndpoint = (bEndpoint-1); + Transfer *pXfr = (Transfer*)&(pEp->transfer); + /* Return if DMA is not supported */ + if (!CHIP_USB_ENDPOINTS_DMA(bEndpoint)) + { + return USBD_STATUS_HW_NOT_SUPPORTED; + } + +#ifdef DMA + /* Return if busy */ + if (pEp->state != UDPHS_ENDPOINT_IDLE) + { + return USBD_STATUS_LOCKED; + } + /* Sending state */ + pEp->state = UDPHS_ENDPOINT_SENDING; + TRACE_DEBUG_WP("Wr%d(%d+%d) ", bEndpoint, bHdrLen, dLength); + + pEp->sendZLP = 0; + + /* Setup transfer descriptor */ + pXfr->pData = (void*) pData; + pXfr->remaining = bHdrLen + dLength; + pXfr->buffered = 0; + pXfr->transferred = 0; + + SCB_CleanInvalidateDCache(); + /* 1. DMA supported always, 2. Not ZLP */ + if (bHdrLen + dLength > 0) + { + uint8_t bNbTrans = (USBHS_GetConfigureEPs(pUdp, bEndpoint, USBHS_DEVEPTCFG_NBTRANS_Msk) + >> USBHS_DEVEPTCFG_NBTRANS_Pos); + if (pXfr->remaining > DMA_MAX_FIFO_SIZE) + { + /* Transfer the max */ + pXfr->buffered = DMA_MAX_FIFO_SIZE; + } + else + { + /* Good size, total size */ + pXfr->buffered = pXfr->remaining; + } + + /* LD1: header - load to fifo without interrupt */ + /* Header discarded if exceed the DMA FIFO length */ + //if (bHdrLen > DMA_MAX_FIFO_SIZE) bHdrLen = DMA_MAX_FIFO_SIZE; + pDmaLL[0].pNxtDesc = (void*)&pDmaLL[1]; + pDmaLL[0].pAddr = (void*)pHdr; + pDmaLL[0].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(bHdrLen) + | USBHS_DEVDMACONTROL_LDNXT_DSC; + /* High bandwidth ISO EP, max size n*ep_size */ + if (bNbTrans > 1) { + uint8_t* pU8 = (uint8_t*)pData; + uint32_t maxSize = bNbTrans * pEp->size; + dLength = pXfr->buffered - bHdrLen; + if (dLength > maxSize) dLength = maxSize; + #if 0 /* Prepare banks by 1 DMA descriptor -- NK if not standard EP size, works! */ + /* LD2: data - load to fifo with interrupt */ + pDmaLL[1].pNxtDesc = (void*)NULL; + pDmaLL[1].pAddr = (void*)pU8; + pDmaLL[1].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(dLength) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT; + #else + uint32_t pktLen, ndxData = 0; + /* LD2: data - bank 0 */ + pktLen = pEp->size - bHdrLen; + if (pktLen >= dLength) { /* It's the last DMA LLI */ + pDmaLL[1].pNxtDesc = (void*)NULL; + pDmaLL[1].pAddr = (void*)pU8; + pDmaLL[1].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(dLength) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT; + } + else { + pDmaLL[1].pNxtDesc = (void*)&pDmaLL[2]; + pDmaLL[1].pAddr = (void*)pU8; + pDmaLL[1].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(pktLen) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_LDNXT_DSC; + + dLength -= pktLen; ndxData += pktLen; + /* LD3: data - bank 1 */ + pktLen = pEp->size; + if (pktLen >= dLength) { /* It's the last */ + pDmaLL[1].pNxtDesc = (void*) NULL; + pDmaLL[1].pAddr = (void*)&pU8[ndxData]; + pDmaLL[1].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(dLength) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT; + } + else { + pDmaLL[2].pNxtDesc = (void*)&pDmaLL[3]; + pDmaLL[2].pAddr = (void*)&pU8[ndxData]; + pDmaLL[2].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(pktLen) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_LDNXT_DSC; + dLength -= pktLen; ndxData += pktLen; + /* LD4: data - bank 2 */ + pDmaLL[3].pNxtDesc = (void*) NULL; + pDmaLL[3].pAddr = (void*)&pU8[ndxData]; + pDmaLL[3].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(dLength) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT; + } + } + #endif + } + else { /* Normal, fill all data */ + /* LD2: data - load to fifo with interrupt */ + dLength = pXfr->buffered - bHdrLen; + pDmaLL[1].pNxtDesc = (void*)NULL; + pDmaLL[1].pAddr = (void*)pData; + pDmaLL[1].dwCtrl = USBHS_DEVDMACONTROL_CHANN_ENB + | USBHS_DEVDMACONTROL_BUFF_LENGTH(dLength) + | USBHS_DEVDMACONTROL_END_B_EN + | USBHS_DEVDMACONTROL_END_BUFFIT; + } + /* Interrupt enable */ + pUdp->USBHS_DEVIER |= (USBHS_DEVIMR_DMA_1 << bDmaEndpoint); + /* Start transfer with LLI */ + pUdp->USBHS_DEVDMA[bDmaEndpoint].USBHS_DEVDMANXTDSC = (uint32_t)pDmaLL; + pUdp->USBHS_DEVDMA[bDmaEndpoint].USBHS_DEVDMACONTROL = 0; + pUdp->USBHS_DEVDMA[bDmaEndpoint].USBHS_DEVDMACONTROL = USBHS_DEVDMACONTROL_LDNXT_DSC; + return USBD_STATUS_SUCCESS; + } +#endif + + /* Enable IT */ + USBHS_EnableIntEP( pUdp, bEndpoint ); + USBHS_EnableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIER_TXINES); + return USBD_STATUS_SUCCESS; +} + +/** + * Reads incoming data on an USB endpoint This methods sets the transfer + * descriptor and activate the endpoint interrupt. The actual transfer is + * then carried out by the endpoint interrupt handler. The Read operation + * finishes either when the buffer is full, or a short packet (inferior to + * endpoint maximum size) is received. + * + * *The buffer must be kept allocated until the transfer is finished*. + * \param bEndpoint Endpoint number. + * \param pData Pointer to a data buffer. + * \param dLength Size of the data buffer in bytes. + * \return USBD_STATUS_SUCCESS if the read operation has been started; + * otherwise, the corresponding error code. + */ +uint8_t USBD_HAL_Read(uint8_t bEndpoint, + void *pData, + uint32_t dLength) +{ + if (endpoints[bEndpoint].transfer.transHdr.transType) + return USBD_STATUS_SW_NOT_SUPPORTED; + else + return UDPHS_Read(bEndpoint, pData, dLength); +} + +/** + * \brief Enable Pull-up, connect. + * + * -# Enable HW access if needed + * -# Enable Pull-Up + * -# Disable HW access if needed + */ +void USBD_HAL_Connect(void) +{ + + // At startup the USB bus state is unknown, + // therefore the state is considered IDLE to not miss any USB event + + USBHS_FreezeClock(USBHS, false); + + // Authorize attach + USBHS_DetachUsb(USBHS, false); + + // (RESET_AND_WAKEUP) + // After the attach and the first USB suspend, the following USB Reset time can be inferior to CPU restart clock time. + // Thus, the USB Reset state is not detected and endpoint control is not allocated + // In this case, a Reset is do automatically after attach. + USBD_HAL_ConfigureEP(0); + + // Enable USB line events + USBHS_EnableInt(USBHS, (USBHS_DEVIER_EORSTES | USBHS_DEVIER_WAKEUPES | USBHS_DEVIER_SUSPES | USBHS_DEVIER_SOFES) ); + +#ifdef USB_DEVICE_HS_SUPPORT + USBHS_EnableInt(USBHS, USBHS_DEVIER_MSOFES); +#endif + + // Reset following interrupts flag + USBHS_AckInt(USBHS, ( USBHS_DEVICR_EORSTC | USBHS_DEVICR_SOFC | USBHS_DEVICR_MSOFC ) ); + + + // The first suspend interrupt is not detected else raise it + USBHS_RaiseInt(USBHS, USBHS_DEVIFR_SUSPS); + + USBHS_AckInt(USBHS, USBHS_DEVICR_WAKEUPC); + + USBHS_FreezeClock(USBHS, true); +} + +/** + * \brief Disable Pull-up, disconnect. + * + * -# Enable HW access if needed + * -# Disable PULL-Up + * -# Disable HW access if needed + */ +void USBD_HAL_Disconnect(void) +{ + USBHS_FreezeClock(USBHS, ENABLE); + // Detach device from the bus + USBHS_DetachUsb(USBHS, true); +} + +/** + * Starts a remote wake-up procedure. + */ +void USBD_HAL_RemoteWakeUp(void) +{ + Usbhs *pUdp = USBHS; + + TRACE_INFO_WP("RWUp "); + + /* Activates a remote wakeup (edge on ESR), then clear ESR */ + USBHS_SetRemoteWakeUp(pUdp); + while(pUdp->USBHS_DEVCTRL & USBHS_DEVCTRL_RMWKUP); + { + TRACE_DEBUG_WP("w"); + } +} + +/** + * Sets the device address to the given value. + * \param address New device address. + */ +void USBD_HAL_SetAddress(uint8_t address) +{ + Usbhs *pUdp = USBHS; + + if (address) + { + USBHS_SetAddress(pUdp, address); + } + else + { + USBHS_EnableAddress(pUdp, false); + } +} + +/** + * Sets the current device configuration. + * \param cfgnum - Configuration number to set. + */ +void USBD_HAL_SetConfiguration(uint8_t cfgnum) +{ + /* Nothing to do now */ + cfgnum = cfgnum; +} + +/** + * Initializes the USB HW Access driver. + */ +void USBD_HAL_Init(void) +{ + +#ifdef DMA + /* DMA Link list should be 16-bytes aligned */ + if ((uint32_t)dmaLL & 0xFFFFFFF0) + pDmaLL = (UdphsDmaDescriptor*)((uint32_t)&dmaLL[1] & 0xFFFFFFF0); + else + pDmaLL = (UdphsDmaDescriptor*)((uint32_t)&dmaLL[0]); +#endif +/** Disable USB hardware */ + USBHS_UsbEnable(USBHS, false); + + USBHS_UsbMode(USBHS, DEVICE_MODE); + + /** Enable USB hardware*/ + USBHS_UsbEnable(USBHS, true); + + USBHS_FreezeClock(USBHS, false); + + if(ForceFS) + { + USBHS_EnableHighSpeed(USBHS, false); + } + else + { + USBHS_EnableHighSpeed(USBHS, true); + } + /* Check USB clock */ + while( !USBHS_ISUsableClock(USBHS) ); + + USBHS_FreezeClock(USBHS, true); + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(USBHS_IRQn); + /* IRQ */ + NVIC_EnableIRQ(USBHS_IRQn) ; + +} + +/** + * Causes the given endpoint to acknowledge the next packet it receives + * with a STALL handshake except setup request. + * \param bEP Endpoint number. + * \return USBD_STATUS_SUCCESS or USBD_STATUS_LOCKED. + */ +uint8_t USBD_HAL_Stall(uint8_t bEP) +{ + Usbhs *pUdp = USBHS; + + Endpoint *pEndpoint = &(endpoints[bEP]); + + /* Check that endpoint is in Idle state */ + if (pEndpoint->state != UDPHS_ENDPOINT_IDLE) + { + TRACE_WARNING("UDP_Stall: EP%d locked\n\r", bEP); + return USBD_STATUS_LOCKED; + } + /* STALL endpoint */ + USBHS_EnableEPIntType(pUdp, bEP, USBHS_DEVEPTIER_STALLRQS); + + TRACE_INFO_WP("Stall%d ", bEP); + return USBD_STATUS_SUCCESS; +} + +/** + * Sets/Clear/Get the HALT state on the endpoint. + * In HALT state, the endpoint should keep stalling any packet. + * \param bEndpoint Endpoint number. + * \param ctl Control code CLR/HALT/READ. + * 0: Clear HALT state; + * 1: Set HALT state; + * .: Return HALT status. + * \return USBD_STATUS_INVALID_PARAMETER if endpoint not exist, + * otherwise endpoint halt status. + */ +uint8_t USBD_HAL_Halt(uint8_t bEndpoint, uint8_t ctl) +{ + Usbhs *pUdp = USBHS; + + Endpoint *pEndpoint = &(endpoints[bEndpoint]); + uint8_t bDmaEndpoint = (bEndpoint-1); + uint8_t status = 0; + /* SET Halt */ + if (ctl == 1) + { + /* Check that endpoint is enabled and not already in Halt state */ + if ((pEndpoint->state != UDPHS_ENDPOINT_DISABLED) + && (pEndpoint->state != UDPHS_ENDPOINT_HALTED)) + { + + TRACE_INFO_WP("Halt%d ", bEndpoint); + + /* Abort the current transfer if necessary */ + UDPHS_EndOfTransfer(bEndpoint, USBD_STATUS_ABORTED); + + /* Put endpoint into Halt state */ + pEndpoint->state = UDPHS_ENDPOINT_HALTED; + memory_sync(); + //SCB_CleanInvalidateDCache(); + + while(!USBHS_IsBankFree(pUdp, bEndpoint)) + { + USBHS_KillBank(pUdp, bEndpoint); + while(USBHS_IsBankKilled(pUdp, bEndpoint)); + } + + if(USBHS_IsBankFree(pUdp, bEndpoint)) + { + USBHS_AutoSwitchBankEnable(pUdp, bEndpoint, false); + USBHS_EnableEPIntType(pUdp, bEndpoint, (USBHS_DEVEPTIER_STALLRQS | USBHS_DEVEPTIER_RSTDTS) ); + } + else + { + USBHS_EnableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIER_NBUSYBKES ); +#ifdef DMA + if (CHIP_USB_ENDPOINTS_DMA(bDmaEndpoint)) + { + /* Enable the endpoint DMA interrupt */ + USBHS_EnableDMAIntEP(pUdp, bDmaEndpoint); + } + else + { + /* Enable the endpoint interrupt */ + USBHS_EnableIntEP( pUdp, bEndpoint ); + } +#else + /* Enable the endpoint interrupt */ + USBHS_EnableIntEP( pUdp, bEndpoint ); +#endif + } + } + + } + /* CLEAR Halt */ + else if (ctl == 0) + { + /* Check if the endpoint is halted */ + if ((pEndpoint->state == UDPHS_ENDPOINT_HALTED) || (USBHS_IsEpIntEnable(pUdp, bEndpoint, USBHS_DEVEPTIMR_STALLRQ)) ) + { + + TRACE_INFO_WP("Unhalt%d ", bEndpoint); + /* Return endpoint to Idle state */ + pEndpoint->state = UDPHS_ENDPOINT_IDLE; + + /* Clear FORCESTALL flag */ + USBHS_DisableEPIntType(pUdp, bEndpoint, USBHS_DEVEPTIDR_STALLRQC); + USBHS_AutoSwitchBankEnable(pUdp, bEndpoint, true); + } + } + + /* Return Halt status */ + if (pEndpoint->state == UDPHS_ENDPOINT_HALTED) + { + status = 1; + } + return( status ); +} + +/** + * Indicates if the device is running in high or full-speed. Always returns 0 + * since UDP does not support high-speed mode. + */ +uint8_t USBD_HAL_IsHighSpeed(void) +{ + Usbhs *pUdp = USBHS; + uint32_t tmp = USBHS_GetUsbSpeed(pUdp); + return ((tmp & USBHS_SR_SPEED_HIGH_SPEED) >> USBHS_SR_SPEED_Pos) ; +} + +/** + * Suspend USB Device HW Interface + * + * -# Disable transceiver + * -# Disable USB Clock + * -# Disable USB Peripheral + */ +void USBD_HAL_Suspend(void) +{ + /* The device enters the Suspended state */ + USBHS_FreezeClock(USBHS, ENABLE); +} + +/** + * Activate USB Device HW Interface + * -# Enable USB Peripheral + * -# Enable USB Clock + * -# Enable transceiver + */ +void USBD_HAL_Activate(void) +{ + USBHS_FreezeClock(USBHS, DISABLE); +} + +void USBD_HAL_Disable(void) +{ + //** Disable USB hardware + USBHS_UsbEnable(USBHS, false); + + /* Clear IRQ */ + NVIC_ClearPendingIRQ(USBHS_IRQn); + /* IRQ */ + NVIC_DisableIRQ(USBHS_IRQn) ; +} + + +/** + * Certification test for High Speed device. + * \param bIndex Test to be done + */ +void USBD_HAL_Test( uint8_t bIndex ) +{ + Usbhs *pUdp = USBHS; + uint8_t *pFifo; + uint32_t i; + + /* remove suspend for TEST */ + USBHS_DisableInt(pUdp, USBHS_DEVIDR_SUSPEC); + /* force High Speed (remove suspend) */ + pUdp->USBHS_DEVCTRL |= USBHS_DEVCTRL_SPDCONF_HIGH_SPEED; + + USBHS_EnableTestMode(pUdp, USBHS_DEVCTRL_OPMODE2); + + switch( bIndex ) { + + case USBFeatureRequest_TESTPACKET: + TRACE_DEBUG_WP("TEST_PACKET "); + + pUdp->USBHS_DEVDMA[1].USBHS_DEVDMACONTROL = 0; + pUdp->USBHS_DEVDMA[2].USBHS_DEVDMACONTROL = 0; + + /* Configure endpoint 2, 64 bytes, direction IN, type BULK, 1 bank */ + pUdp->USBHS_DEVEPTCFG[2]= USBHS_DEVEPTCFG_EPSIZE_64_BYTE + | USBHS_DEVEPTCFG_EPDIR + | USBHS_DEVEPTCFG_EPTYPE_BLK + | USBHS_DEVEPTCFG_EPBK_1_BANK; + USBHS_AllocateMemory(pUdp, 2); + while( (USBHS_DEVEPTISR_CFGOK & pUdp->USBHS_DEVEPTISR[2]) != USBHS_DEVEPTISR_CFGOK); + USBHS_EnableEP(pUdp, 2, true); + + /* Write FIFO */ + pFifo = (uint8_t*)((uint32_t *)(USBHS_RAM_ADDR) + (EPT_VIRTUAL_SIZE * 2)); + for( i=0; i + *
  • Enable ACC peripheral clock by setting the corresponding bit in + * PMC_PCER1 (PMC Peripheral Clock Enable Register 1) + *
    • + *
  • Reset the controller by asserting ACC_CR_SWRST in ACC_CR(ACC Control + * Register)
    • + *
  • Configure the mode as following steps:
    • + * -# Select inputs for SELMINUS and SELPLUS in ACC_MR (ACC Mode Register). + * -# Enable Analog Comparator by setting ACEN in ACC_MR. + * -# Configure Edge Type to detect different compare output. + * + *
  • Wait until the automatic mask period expires by polling MASK bit in + * ACC_ISR. + * + * + * For more accurate information, please look at the ACC section of the + * Datasheet. + * + * Related files :\n + * \ref acc.c\n + * \ref acc.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * Implementation of Analog Comparator Controller (ACC). + * + */ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Initialize the ACC controller + * + * \param pAcc Pointer to an Acc instance. + * \param idAcc ACC identifier + * \param ucSelplus input connected to inp, 0~7 + * \param ucSelminus input connected to inm,0~7 + * \param wAc_en Analog comparator enabled/disabled + * \param wEdge CF flag triggering mode + * \param wInvert INVert comparator output,use pattern defined in the device + * header file + */ +extern void ACC_Configure( Acc *pAcc, uint8_t idAcc, uint8_t ucSelplus, + uint8_t ucSelminus, uint16_t wAc_en, uint16_t wEdge, uint16_t wInvert ) +{ + /* Enable peripheral clock*/ + PMC->PMC_PCER1 = 1 << (idAcc - 32) ; + + /* Reset the controller */ + pAcc->ACC_CR |= ACC_CR_SWRST ; + + /* Write to the MR register */ + ACC_CfgModeReg( pAcc, + ( (ucSelplus<ACC_ACR = (ACC_ACR_ISEL_HISP + | ((0x01 << ACC_ACR_HYST_Pos) & ACC_ACR_HYST_Msk)); + + /* Automatic Output Masking Period*/ + while ( pAcc->ACC_ISR & (uint32_t)ACC_ISR_MASK ) ; +} + +/** + * Return the Channel Converted Data + * \param pAcc Pointer to an Acc instance. + * \param ucSelplus input applied on ACC SELPLUS + * \param ucSelminus input applied on ACC SELMINUS + */ +extern void ACC_SetComparisonPair( Acc *pAcc, uint8_t ucSelplus, uint8_t ucSelminus ) +{ + uint32_t dwTemp ; + + assert( ucSelplus < 8 && ucSelminus < 8 ) ; + + dwTemp = pAcc->ACC_MR ; + pAcc->ACC_MR = + dwTemp & (uint32_t) ((~ACC_MR_SELMINUS_Msk) & (~ACC_MR_SELPLUS_Msk)); + + pAcc->ACC_MR |= ( ((ucSelplus << ACC_MR_SELPLUS_Pos) & ACC_MR_SELPLUS_Msk) | + ((ucSelminus << ACC_MR_SELMINUS_Pos) & ACC_MR_SELMINUS_Msk) ) ; +} + +/** + * Return Comparison Result + * \param pAcc Pointer to an Acc instance. + * \param dwStatus value of ACC_ISR + */ +extern uint32_t ACC_GetComparisonResult( Acc *pAcc, uint32_t dwStatus ) +{ + uint32_t dwTemp = pAcc->ACC_MR ; + + if ( (dwTemp & ACC_MR_INV) == ACC_MR_INV ) { + if ( dwStatus & ACC_ISR_SCO ) { + return 0 ; /* inn>inp*/ + } else { + return 1 ;/* inp>inn*/ + } + } else { + if ( dwStatus & ACC_ISR_SCO ) { + return 1 ; /* inp>inn*/ + } else { + return 0 ;/* inn>inp*/ + } + } +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/aes.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/aes.c new file mode 100644 index 000000000..fba934de8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/aes.c @@ -0,0 +1,267 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup aes_module Working with AES + * \ingroup peripherals_module + * The AES driver provides the interface to configure and use the AES peripheral. + * \n + * + * The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm + * that can be used to protect electronic data. The AES algorithm is a symmetric block + * cipher that can encrypt (encipher) and decrypt (decipher) information. + * Encryption converts data to an unintelligible form called ciphertext. + * Decrypting the ciphertext converts the data back into its original form, + * called plaintext. The CIPHER bit in the AES Mode Register (AES_MR) allows selection + * between the encryption and the decryption processes. The AES is capable of using cryptographic + * keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. + * This 128-bit/192-bit/256-bit key is defined in the Key Registers (AES_KEYWRx) and set by + * AES_WriteKey(). The input to the encryption processes of the CBC, CFB, and OFB modes includes, + * in addition to the plaintext, a 128-bit data block called the initialization vector (IV), + * which must be set with AES_SetVector(). + * The initialization vector is used in an initial step in the encryption of a message and + * in the corresponding decryption of the message. The Initialization Vector Registers are + * also used by the CTR mode to set the counter value. + * + * To Enable a AES encryption and decryption,the user has to follow these few steps: + *
      + *
    • A software triggered hardware reset of the AES interface is performed by AES_SoftReset().
      • + *
    • Configure AES algorithm mode, key mode, start mode and operation mode by AES_Configure().
      • + *
    • Input AES data for encryption and decryption with function AES_SetInput()
      • + *
    • Set AES key with function AES_WriteKey().
      • + *
    • To start the encryption or the decryption process with AES_Start()
      • + *
    • To get the encryption or decryption result by AES_GetOutput()
      • + *
    + * + * + * For more accurate information, please look at the AES section of the + * Datasheet. + * + * Related files :\n + * \ref aes.c\n + * \ref aes.h\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Advanced Encryption Standard (AES) + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Starts Manual encryption/decryption process. + */ +void AES_Start(void) +{ + AES->AES_CR = AES_CR_START; +} + +/** + * \brief Resets the AES. A software triggered hardware reset of the AES interface is performed. + */ +void AES_SoftReset(void) +{ + AES->AES_CR = AES_CR_SWRST; +} + + +/** + * \brief Configures an AES peripheral with the specified parameters. + * \param mode Desired value for the AES mode register (see the datasheet). + */ +void AES_Configure(uint32_t mode) +{ + AES->AES_MR = mode; +} + +/** + * \brief Enables the selected interrupts sources on a AES peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void AES_EnableIt(uint32_t sources) +{ + AES->AES_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a AES peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void AES_DisableIt(uint32_t sources) +{ + AES->AES_IDR = sources; +} + +/** + * \brief Get the current status register of the given AES peripheral. + * \return AES status register. + */ +uint32_t AES_GetStatus(void) +{ + return AES->AES_ISR; +} + +/** + * \brief Set the 128-bit/192-bit/256-bit cryptographic key used for encryption/decryption. + * \param pKey Pointer to a 16/24/32 bytes cipher key. + * \param keyLength length of key + */ +void AES_WriteKey(const uint32_t *pKey, uint32_t keyLength) +{ + AES->AES_KEYWR[0] = pKey[0]; + AES->AES_KEYWR[1] = pKey[1]; + AES->AES_KEYWR[2] = pKey[2]; + AES->AES_KEYWR[3] = pKey[3]; + + if( keyLength >= 24 ) { + AES->AES_KEYWR[4] = pKey[4]; + AES->AES_KEYWR[5] = pKey[5]; + } + if( keyLength == 32 ) { + AES->AES_KEYWR[6] = pKey[6]; + AES->AES_KEYWR[7] = pKey[7]; + } +} + +/** + * \brief Set the for 32-bit input Data allow to set the 128-bit data block used for encryption/decryption. + * \param data Pointer to the 16-bytes data to cipher/decipher. + */ +void AES_SetInput(uint32_t *data) +{ + uint8_t i; + for (i = 0; i< 4; i++) + AES->AES_IDATAR[i] = data[i]; +} + +/** + * \brief Get the four 32-bit data contain the 128-bit data block which has been encrypted/decrypted. + * \param data pointer to the word that has been encrypted/decrypted.. + */ +void AES_GetOutput(uint32_t *data) +{ + uint8_t i; + for (i = 0; i< 4; i++) + data[i] = AES->AES_ODATAR[i]; +} + +/** + * \brief Set four 64-bit initialization vector data block, which is used by some + * modes of operation as an additional initial input. + * \param pVector point to the word of the initialization vector. + */ +void AES_SetVector(const uint32_t *pVector) +{ + AES->AES_IVR[0] = pVector[0]; + AES->AES_IVR[1] = pVector[1]; + AES->AES_IVR[2] = pVector[2]; + AES->AES_IVR[3] = pVector[3]; +} + + +/** + * \brief Set Length in bytes of the AAD data that is to be processed. + * \param len Length. + */ +void AES_SetAadLen(uint32_t len) +{ + AES->AES_AADLENR = len; +} + +/** + * \brief Set Length in bytes of the Length in bytes of the + * plaintext/ciphertext (C) data that is to be processed.. + * \param len Length. + */ +void AES_SetDataLen(uint32_t len) +{ + AES->AES_CLENR = len; +} + +/** + * \brief Set The four 32-bit Hash Word registers expose the intermediate GHASH value. + * May be read to save the current GHASH value so processing can later be resumed, + * presumably on a later message fragment. modes of operation as an additional initial input. + * \param hash point to the word of the hash. + */ +void AES_SetGcmHash(uint32_t * hash) +{ + uint8_t i; + for (i = 0; i< 4; i++) + AES->AES_GHASHR[i] = hash[i]; +} + + +/** + * \brief Get The four 32-bit Tag which contain the final 128-bit GCM Authentication tag + * ¡°T¡± when GCM processing is complete. + * \param tag point to the word of the tag. + */ +void AES_GetGcmTag(uint32_t * tag) +{ + uint8_t i; + for (i = 0; i< 4; i++) + tag[i] = AES->AES_TAGR[i] ; +} + +/** + * \brief Reports the current value of the 32-bit GCM counter + * \param counter Point to value of GCM counter. + */ +void AES_GetGcmCounter(uint32_t * counter) +{ + *counter = AES->AES_CTRR; +} + + +/** + * \brief Get the four 32-bit data contain the 128-bit H value computed from the KEYW value + * \param data point to the word that has been encrypted/decrypted.. + */ +void AES_GetGcmH(uint32_t *h) +{ + uint8_t i; + for (i = 0; i< 4; i++) + h[i] = AES->AES_GCMHR[i]; +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afe_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afe_dma.c new file mode 100644 index 000000000..09dda6419 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afe_dma.c @@ -0,0 +1,248 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup afe_dma_module Working with AFE (DMA support) + * \ingroup peripherals_module + * The afec driver provides the interface to configure and use the afecC + * peripheral with DMA support.\n + * + * For more accurate information, please look at the AFEC section of the + * Datasheet. + * + * Related files :\n + * \ref afe_dma.c\n + * \ref afe_dma.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * + */ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/* DMA driver instance */ +static uint32_t afeDmaRxChannel; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief AFE xDMA Rx callback + * Invoked on AFE DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to AfeDma instance. + */ +static void Afe_Rx_Cb(uint32_t channel, AfeDma* pArg) +{ + AfeCmd *pAfedCmd = pArg->pCurrentCommand; + if (channel != afeDmaRxChannel) + return; + + /* Configure and enable interrupt on RC compare */ + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_DisableIRQ(XDMAC_IRQn); + + /* Release the DMA channels */ + XDMAD_FreeChannel(pArg->pXdmad, afeDmaRxChannel); + SCB_CleanInvalidateDCache(); + /* Release the dataflash semaphore */ + pArg->semaphore++; + + /* Invoke the callback associated with the current command */ + if (pAfedCmd && pAfedCmd->callback) { + pAfedCmd->callback(0, pAfedCmd->pArgument); + } +} + +/** + * \brief Configure the DMA Channels: 0 RX. + * Channels are disabled after configure. + * \param pXdmad Pointer to a AfeDma instance + * \returns 0 if the dma channel configuration successfully; otherwise returns + * AFE_ERROR_XXX. + */ +static uint8_t _AfeConfigureDmaChannels( AfeDma* pAfed ) +{ + + /* Driver initialize */ + XDMAD_Initialize( pAfed->pXdmad, 0 ); + + XDMAD_FreeChannel( pAfed->pXdmad, afeDmaRxChannel); + + /* Allocate a DMA channel for AFE0/1 RX. */ + afeDmaRxChannel = + XDMAD_AllocateChannel( pAfed->pXdmad, pAfed->afeId, XDMAD_TRANSFER_MEMORY); + if ( afeDmaRxChannel == XDMAD_ALLOC_FAILED ) { + return AFE_ERROR; + } + + /* Setup callbacks for AFE0/1 RX */ + XDMAD_SetCallback(pAfed->pXdmad, afeDmaRxChannel, + (XdmadTransferCallback)Afe_Rx_Cb, pAfed); + if (XDMAD_PrepareChannel( pAfed->pXdmad, afeDmaRxChannel )) + return AFE_ERROR; + return AFE_OK; +} + +/** + * \brief Configure the DMA source and destination with Linker List mode. + * \param pXdmad Pointer to a AfeDma instance + * \param pCommand Pointer to AfeCmd instance + * \param AfeCmd Pointer to command + */ + +static uint8_t _Afe_configureLinkList(Afec *pAfeHw, void *pXdmad, AfeCmd *pCommand) +{ + uint32_t xdmaCndc, xdmaInt; + sXdmadCfg xdmadRxCfg; + uint32_t afeId; + if ((unsigned int)pAfeHw == (unsigned int)AFEC0 ) afeId = ID_AFEC0; + if ((unsigned int)pAfeHw == (unsigned int)AFEC1 ) afeId = ID_AFEC1; + /* Setup RX Link List */ + xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | + XDMA_UBC_NDE_FETCH_DIS| + XDMA_UBC_NDEN_UPDATED | + pCommand->RxSize; + + xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff; + xdmadRxCfg.mbr_sa = (uint32_t)&(pAfeHw->AFEC_LCDR); + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_WORD| + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID( + XDMAIF_Get_ChannelNumber( afeId, XDMAD_TRANSFER_RX )); + + xdmadRxCfg.mbr_bc = 0; + xdmadRxCfg.mbr_sus = 0; + xdmadRxCfg.mbr_dus =0; + + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + xdmaCndc = 0; + if (XDMAD_ConfigureTransfer( pXdmad, afeDmaRxChannel, + &xdmadRxCfg, xdmaCndc, 0, xdmaInt)) + return AFE_ERROR; + SCB_CleanInvalidateDCache(); + return AFE_OK; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + +/** + * \brief Initializes the AfeDma structure and the corresponding AFE & DMA . + * hardware select value. + * The driver will uses DMA channel 0 for RX . + * The DMA channels are freed automatically when no DMA command processing. + * + * \param pAfed Pointer to a AfeDma instance. + * \param pAfeHw Associated Afe peripheral. + * \param AfeId Afe peripheral identifier. + * \param pDmad Pointer to a Dmad instance. + */ +uint32_t Afe_ConfigureDma( AfeDma *pAfed , + Afec *pAfeHw , + uint8_t AfeId, + sXdmad *pXdmad ) +{ + /* Initialize the Afe structure */ + pAfed->pAfeHw = pAfeHw; + pAfed->afeId = AfeId; + pAfed->semaphore = 1; + pAfed->pCurrentCommand = 0; + pAfed->pXdmad = pXdmad; + return 0; +} + +/** + * \brief Starts a AFE transfer. This is a non blocking function. It will + * return as soon as the transfer is started. + * + * \param pAfed Pointer to a AfeDma instance. + * \param pCommand Pointer to the Afe command to execute. + * \returns 0 if the transfer has been started successfully; otherwise returns + * AFE_ERROR_LOCK is the driver is in use, or AFE_ERROR if the command is not + * valid. + */ +uint32_t Afe_SendData( AfeDma *pAfed, AfeCmd *pCommand) +{ + Afec *pAfeHw = pAfed->pAfeHw; + + /* Try to get the dataflash semaphore */ + if (pAfed->semaphore == 0) { + + return AFE_ERROR_LOCK; + } + pAfed->semaphore--; + + // Initialize the callback + pAfed->pCurrentCommand = pCommand; + + /* Initialize DMA controller using channel 0 for RX. */ + if (_AfeConfigureDmaChannels(pAfed) ) + return AFE_ERROR_LOCK; + + /* Configure and enable interrupt on RC compare */ + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority( XDMAC_IRQn ,1); + NVIC_EnableIRQ(XDMAC_IRQn); + + if (_Afe_configureLinkList(pAfeHw, pAfed->pXdmad, pCommand)) + return AFE_ERROR_LOCK; + + AFEC_StartConversion(pAfeHw); + /* Start DMA 0(RX) */ + SCB_CleanInvalidateDCache(); + if (XDMAD_StartTransfer( pAfed->pXdmad, afeDmaRxChannel )) + return AFE_ERROR_LOCK; + + return AFE_OK;; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afec.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afec.c new file mode 100644 index 000000000..476793b31 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/afec.c @@ -0,0 +1,449 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup AFEC_module Working with AFE + * \ingroup peripherals_module + * The AFE driver provides the interface to configure and use the AFE peripheral. + * \n + * + * It converts the analog input to digital format. The converted result could be + * 12bit or 10bit. The AFE supports up to 16 analog lines. + * + * To Enable a AFE conversion,the user has to follow these few steps: + *
      + *
    • Select an appropriate reference voltage on ADVREF
      • + *
    • Configure the AFE according to its requirements and special needs,which + * could be broken down into several parts: + * -# Select the resolution by setting or clearing AFEC_MR_LOWRES bit in + * AFEC_MR (Mode Register) + * -# Set AFE clock by setting AFEC_MR_PRESCAL bits in AFEC_MR, the clock is + * calculated with AFEClock = MCK / ( (PRESCAL+1) * 2 ) + * -# Set Startup Time,Tracking Clock cycles and Transfer Clock respectively + * in AFEC_MR. +
      • + *
    • Start conversion by setting AFEC_CR_START in AFEC_CR.
      • + *
    + * + * For more accurate information, please look at the AFE section of the + * Datasheet. + * + * Related files :\n + * \ref afec.c\n + * \ref afec.h\n + * \ref afe_dma.c\n + * \ref afe_dma.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * Implementation of Analog-to-Digital Converter (AFE). + * + */ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/** Current working clock */ +static uint32_t dwAFEClock = 0; + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Initialize the AFE controller + * + * \param pAFE Pointer to an AFE instance. + * \param dwID AFE Index + */ +extern void AFEC_Initialize( Afec* pAFE, uint32_t dwID ) +{ + /* Enable peripheral clock*/ + PMC_EnablePeripheral(dwID); + + /* Reset the controller */ + pAFE->AFEC_CR = AFEC_CR_SWRST; + + /* Reset Mode Register */ + pAFE->AFEC_MR = 0; +} + +/** + * \brief Set AFE clock. + * + * \param pAFE Pointer to an AFE instance. + * \param dwPres prescale value + * \param dwMck Board MCK (Hz) + * + * \return AFE clock + */ + +extern uint32_t AFEC_SetClock( Afec* pAFE, uint32_t dwClk, uint32_t dwMck ) +{ + uint32_t dwPres, dwMr; + /* Formula for PRESCAL is: + PRESCAL = peripheral clock/ fAFE Clock - 1 */ + + dwPres = (dwMck) / (dwClk ) - 1; + dwMr = AFEC_MR_PRESCAL(dwPres); + if (dwMr == 0) return 0; + + dwMr |= (pAFE->AFEC_MR & ~AFEC_MR_PRESCAL_Msk); + pAFE->AFEC_MR = dwMr; + dwAFEClock = dwMck / (dwPres + 1); + return dwAFEClock; +} + +/** + * \brief Set AFE timing. + * + * \param pAFE Pointer to an AFE instance. + * \param dwStartup startup value + * \param dwTracking tracking value + * \param dwSettling settling value + */ +extern void AFEC_SetTiming( Afec* pAFE, uint32_t dwStartup, uint32_t dwTracking, + uint32_t dwSettling ) +{ + uint32_t dwMr; + + dwMr = pAFE->AFEC_MR; + dwMr &= (~AFEC_MR_STARTUP_Msk) & (~AFEC_MR_TRACKTIM_Msk) & (~AFEC_MR_SETTLING_Msk); + + /* Formula: + * Startup Time = startup value / AFEClock + * Transfer Time = (TRANSFER * 2 + 3) / AFEClock + * Tracking Time = (TRACKTIM + 1) / AFEClock + * Settling Time = settling value / AFEClock + */ + dwMr |= dwStartup | dwTracking | dwSettling; + pAFE->AFEC_MR |= dwMr; +} + +/** + * \brief Set AFE trigger. + * + * \param pAFE Pointer to an AFE instance. + * \param dwTrgSel Trigger selection + */ +extern void AFEC_SetTrigger( Afec* pAFE, uint32_t dwTrgSel ) +{ + uint32_t dwMr; + + dwMr = pAFE->AFEC_MR; + dwMr &= ~AFEC_MR_TRGSEL_Msk; + dwMr |= dwTrgSel; + pAFE->AFEC_MR |= dwMr; +} + + +/** + * \brief Enable/Disable sleep mode. + * + * \param pAFE Pointer to an AFE instance. + * \param bEnDis Enable/Disable sleep mode. + */ +extern void AFEC_SetSleepMode( Afec *pAFE, uint8_t bEnDis ) +{ + if ( bEnDis ) { + pAFE->AFEC_MR |= AFEC_MR_SLEEP; + } else { + pAFE->AFEC_MR &= ~AFEC_MR_SLEEP; + } +} + +/** + * \brief Enable/Disable fast wake up. + * + * \param pAFE Pointer to an AFE instance. + * \param bEnDis Enable/Disable fast wake up in sleep mode. + */ +extern void AFEC_SetFastWakeup( Afec *pAFE, uint8_t bEnDis ) +{ + if ( bEnDis ) { + pAFE->AFEC_MR |= AFEC_MR_FWUP; + } else { + pAFE->AFEC_MR &= ~AFEC_MR_FWUP; + } +} + +/** + * \brief Enable/Disable sequence mode. + * + * \param pAFE Pointer to an AFE instance. + * \param bEnDis Enable/Disable sequence mode. + */ +extern void AFEC_SetSequenceMode( Afec *pAFE, uint8_t bEnDis ) +{ + if ( bEnDis ) { + /* User Sequence Mode: The sequence respects what is defined in + AFEC_SEQR1 and AFEC_SEQR2 */ + pAFE->AFEC_MR |= AFEC_MR_USEQ; + } else { + /* Normal Mode: The controller converts channels in a simple + numeric order. */ + pAFE->AFEC_MR &= ~AFEC_MR_USEQ; + } +} + +/** + * \brief Set channel sequence. + * + * \param pAFE Pointer to an AFE instance. + * \param dwSEQ1 Sequence 1 ~ 8 channel number. + * \param dwSEQ2 Sequence 9 ~ 16 channel number. + */ +extern void AFEC_SetSequence( Afec *pAFE, uint32_t dwSEQ1, uint32_t dwSEQ2 ) +{ + pAFE->AFEC_SEQ1R = dwSEQ1; + pAFE->AFEC_SEQ2R = dwSEQ2; +} + +/** + * \brief Set channel sequence by given channel list. + * + * \param pAFE Pointer to an AFE instance. + * \param ucChList Channel list. + * \param ucNumCh Number of channels in list. + */ +extern void AFEC_SetSequenceByList( Afec *pAFE, uint8_t ucChList[], uint8_t ucNumCh ) +{ + uint8_t i; + uint8_t ucShift; + + pAFE->AFEC_SEQ1R = 0; + for (i = 0, ucShift = 0; i < 8; i ++, ucShift += 4) { + if (i >= ucNumCh) return; + pAFE->AFEC_SEQ1R |= ucChList[i] << ucShift; + + } + pAFE->AFEC_SEQ2R = 0; + for (ucShift = 0; i < 16; i ++, ucShift += 4) { + if (i >= ucNumCh) return; + pAFE->AFEC_SEQ2R |= ucChList[i] << ucShift; + } +} + +/** + * \brief Set analog change. + * IF enabled, it allows different analog settings for each channel, + * otherwise, DIFF0, GAIN0 and OFF0 are used for all channels. + * + * \param pAFE Pointer to an AFE instance. + * \param bEnDis Enable/Disable. + */ +extern void AFEC_SetAnalogChange( Afec* pAFE, uint8_t bEnDis ) +{ + if ( bEnDis ) { + pAFE->AFEC_MR |= AFEC_MR_ONE; + } else { + pAFE->AFEC_MR &= ~AFEC_MR_ONE; + } +} + +/** + * \brief Set "TAG" mode, show channel number in last data or not. + * + * \param pAFE Pointer to an AFE instance. + * \param bEnDis Enable/Disable TAG value. + */ +extern void AFEC_SetTagEnable( Afec *pAFE, uint8_t bEnDis ) +{ + if ( bEnDis ) { + pAFE->AFEC_EMR |= AFEC_EMR_TAG; + } else { + pAFE->AFEC_EMR &= ~AFEC_EMR_TAG; + } +} + +/** + * \brief Set compare channel. + * + * \param pAFE Pointer to an AFE instance. + * \param dwChannel channel number to be set,16 for all channels + */ +extern void AFEC_SetCompareChannel( Afec* pAFE, uint32_t dwChannel ) +{ + assert( dwChannel <= 16 ) ; + + if ( dwChannel < 16 ) { + pAFE->AFEC_EMR &= ~(AFEC_EMR_CMPALL); + pAFE->AFEC_EMR &= ~(AFEC_EMR_CMPSEL_Msk); + pAFE->AFEC_EMR |= (dwChannel << AFEC_EMR_CMPSEL_Pos); + } else { + pAFE->AFEC_EMR |= AFEC_EMR_CMPALL; + } +} + +/** + * \brief Set compare mode. + * + * \param pAFE Pointer to an AFE instance. + * \param dwMode compare mode + */ +extern void AFEC_SetCompareMode( Afec* pAFE, uint32_t dwMode ) +{ + pAFE->AFEC_EMR &= ~(AFEC_EMR_CMPMODE_Msk); + pAFE->AFEC_EMR |= (dwMode & AFEC_EMR_CMPMODE_Msk); +} + +/** + * \brief Set comparison window. + * + * \param pAFE Pointer to an AFE instance. + * \param dwHi_Lo Comparison Window + */ +extern void AFEC_SetComparisonWindow( Afec* pAFE, uint32_t dwHi_Lo ) +{ + pAFE->AFEC_CWR = dwHi_Lo ; +} + +/** + * \brief Return the Channel Converted Data + * + * \param pAFE Pointer to an AFE instance. + * \param dwChannel channel to get converted value + */ +extern uint32_t AFEC_GetConvertedData( Afec* pAFE, uint32_t dwChannel ) +{ + uint32_t dwData = 0; + assert( dwChannel < 12 ) ; + pAFE->AFEC_CSELR = dwChannel; + dwData = pAFE->AFEC_CDR; + + return dwData ; +} + + +/** + * Sets the AFE startup time. + * \param pAFE Pointer to an AFE instance. + * \param dwUs Startup time in uS. + */ +void AFEC_SetStartupTime( Afec *pAFE, uint32_t dwUs ) +{ + uint32_t dwStart; + uint32_t dwMr; + + if (dwAFEClock == 0) return; + /* Formula for STARTUP is: + STARTUP = (time x AFECLK) / (1000000) - 1 + Division multiplied by 10 for higher precision */ + + dwStart = (dwUs * dwAFEClock) / (100000); + if (dwStart % 10) dwStart /= 10; + else + { + dwStart /= 10; + if (dwStart) dwStart --; + } + if (dwStart > 896) dwMr = AFEC_MR_STARTUP_SUT960; + else if (dwStart > 832) dwMr = AFEC_MR_STARTUP_SUT896; + else if (dwStart > 768) dwMr = AFEC_MR_STARTUP_SUT832; + else if (dwStart > 704) dwMr = AFEC_MR_STARTUP_SUT768; + else if (dwStart > 640) dwMr = AFEC_MR_STARTUP_SUT704; + else if (dwStart > 576) dwMr = AFEC_MR_STARTUP_SUT640; + else if (dwStart > 512) dwMr = AFEC_MR_STARTUP_SUT576; + else if (dwStart > 112) dwMr = AFEC_MR_STARTUP_SUT512; + else if (dwStart > 96) dwMr = AFEC_MR_STARTUP_SUT112; + else if (dwStart > 80) dwMr = AFEC_MR_STARTUP_SUT96; + else if (dwStart > 64) dwMr = AFEC_MR_STARTUP_SUT80; + else if (dwStart > 24) dwMr = AFEC_MR_STARTUP_SUT64; + else if (dwStart > 16) dwMr = AFEC_MR_STARTUP_SUT24; + else if (dwStart > 8) dwMr = AFEC_MR_STARTUP_SUT16; + else if (dwStart > 0) dwMr = AFEC_MR_STARTUP_SUT8; + else dwMr = AFEC_MR_STARTUP_SUT0; + + dwMr |= pAFE->AFEC_MR & ~AFEC_MR_STARTUP_Msk; + pAFE->AFEC_MR = dwMr; +} + + +/** + * Set AFE tracking time + * \param pAFE Pointer to an AFE instance. + * \param dwNs Tracking time in nS. + */ +void AFEC_SetTrackingTime( Afec *pAFE, uint32_t dwNs ) +{ + uint32_t dwShtim; + uint32_t dwMr; + + if (dwAFEClock == 0) return; + /* Formula for SHTIM is: + SHTIM = (time x AFECLK) / (1000000000) - 1 + Since 1 billion is close to the maximum value for an integer, we first + divide AFECLK by 1000 to avoid an overflow */ + dwShtim = (dwNs * (dwAFEClock / 1000)) / 100000; + if (dwShtim % 10) dwShtim /= 10; + else + { + dwShtim /= 10; + if (dwShtim) dwShtim --; + } + dwMr = AFEC_MR_TRACKTIM(dwShtim); + dwMr |= pAFE->AFEC_MR & ~AFEC_MR_TRACKTIM_Msk; + pAFE->AFEC_MR = dwMr; +} + +/** + * \brief Set analog offset to be used for channel CSEL. + * + * \param afec Base address of the AFEC. + * \param dwChannel AFEC channel number. + * \param aoffset Analog offset value. + */ +void AFEC_SetAnalogOffset( Afec *pAFE, uint32_t dwChannel,uint32_t aoffset ) +{ + assert( dwChannel < 12 ) ; + pAFE->AFEC_CSELR = dwChannel; + pAFE->AFEC_COCR = (aoffset & AFEC_COCR_AOFF_Msk);; +} + +/** + * \brief Set analog offset to be used for channel CSEL. + * + * \param afec Base address of the AFEC. + * \param control Analog control value. + */ +void AFEC_SetAnalogControl( Afec *pAFE, uint32_t control) +{ + pAFE->AFEC_ACR = control; +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/dac_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/dac_dma.c new file mode 100644 index 000000000..c664f7746 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/dac_dma.c @@ -0,0 +1,234 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup dacc_module Working with DACC + * \ingroup peripherals_module + * The DACC driver provides the interface to configure and use the DACC + * peripheral.\n + * + * The DACC(Digital-to-Analog Converter Controller) converts digital code to + * analog output. + * The data to be converted are sent in a common register for all channels. + * It offers up to 2 analog outputs.The output voltage ranges from (1/6)ADVREF + * to (5/6)ADVREF. + * + * To Enable a DACC conversion,the user has to follow these few steps: + *
      + *
    • Select an appropriate reference voltage on ADVREF
      • + *
    • Configure the DACC according to its requirements and special needs, + * which could be broken down into several parts: + * -# Enable DACC in free running mode by clearing TRGEN in DACC_MR; + * -# Configure Refresh Period through setting REFRESH fields + * in DACC_MR; The refresh mechanism is used to protect the output analog + * value from + * decreasing. + * -# Enable channels and write digital code to DACC_CDR,in free running mode, + * the conversion is started right after at least one channel is enabled and + * data is written . +
      • + *
    + * + * For more accurate information, please look at the DACC section of the + * Datasheet. + * + * Related files :\n + * \ref dac_dma.c\n + * \ref dac_dma.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * Implementation of Digital-to-Analog Converter Controller (DACC). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/* DMA driver instance */ +static uint32_t dacDmaTxChannel; +static LinkedListDescriporView1 dmaWriteLinkList[256]; +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configure the DMA Channels: 0 RX. + * Channels are disabled after configure. + * \returns 0 if the dma channel configuration successfully; otherwise returns + * DAC_ERROR_XXX. + */ +static uint8_t _DacConfigureDmaChannels( DacDma* pDacd ) +{ + + /* Driver initialize */ + XDMAD_Initialize( pDacd->pXdmad, 0 ); + + XDMAD_FreeChannel( pDacd->pXdmad, dacDmaTxChannel); + + /* Allocate a DMA channel for DAC0/1 TX. */ + dacDmaTxChannel = + XDMAD_AllocateChannel( pDacd->pXdmad, XDMAD_TRANSFER_MEMORY, ID_DACC); + if ( dacDmaTxChannel == XDMAD_ALLOC_FAILED ) { + return DAC_ERROR; + } + + if ( XDMAD_PrepareChannel( pDacd->pXdmad, dacDmaTxChannel )) + return DAC_ERROR; + return DAC_OK; +} + + +/** + * \brief Configure the DMA source and destination with Linker List mode. + * + * \param pBuffer Pointer to dac buffer + * \param size length of buffer + */ + +static uint8_t _Dac_configureLinkList(Dacc *pDacHw, void *pXdmad, DacCmd *pCommand) +{ + uint32_t xdmaCndc; + sXdmadCfg xdmadCfg; + uint32_t * pBuffer; + /* Setup TX Link List */ + uint8_t i; + pBuffer = (uint32_t *)pCommand->pTxBuff; + for(i = 0; i < pCommand->TxSize; i++){ + dmaWriteLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 + | XDMA_UBC_NDE_FETCH_EN + | XDMA_UBC_NSEN_UPDATED + | XDMAC_CUBC_UBLEN(4); + dmaWriteLinkList[i].mbr_sa = (uint32_t)pBuffer; + dmaWriteLinkList[i].mbr_da = + (uint32_t)&(pDacHw->DACC_CDR[pCommand->dacChannel]); + if ( i == (pCommand->TxSize - 1 )) { + if (pCommand->loopback) { + dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[0]; + } else { + dmaWriteLinkList[i].mbr_nda = 0; + } + } else { + dmaWriteLinkList[i].mbr_nda = (uint32_t)&dmaWriteLinkList[i+1]; + } + pBuffer++; + } + xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_MEM2PER + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_WORD + | XDMAC_CC_SIF_AHB_IF0 + | XDMAC_CC_DIF_AHB_IF1 + | XDMAC_CC_SAM_INCREMENTED_AM + | XDMAC_CC_DAM_FIXED_AM + | XDMAC_CC_PERID( + XDMAIF_Get_ChannelNumber(ID_DACC, XDMAD_TRANSFER_TX )); + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 + | XDMAC_CNDC_NDE_DSCR_FETCH_EN + | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED + | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + XDMAD_ConfigureTransfer( pXdmad, dacDmaTxChannel, &xdmadCfg, xdmaCndc, + (uint32_t)&dmaWriteLinkList[0], XDMAC_CIE_LIE); + return DAC_OK; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes the DacDma structure and the corresponding DAC & DMA . + * hardware select value. + * The driver will uses DMA channel 0 for RX . + * The DMA channels are freed automatically when no DMA command processing. + * + * \param pDacd Pointer to a DacDma instance. + * \param pDacHw Associated Dac peripheral. + * \param DacId Dac peripheral identifier. + * \param pDmad Pointer to a Dmad instance. + */ +uint32_t Dac_ConfigureDma( DacDma *pDacd , + Dacc *pDacHw , + uint8_t DacId, + sXdmad *pXdmad ) +{ + /* Initialize the Dac structure */ + pDacd->pDacHw = pDacHw; + pDacd->dacId = DacId; + pDacd->semaphore = 1; + pDacd->pCurrentCommand = 0; + pDacd->pXdmad = pXdmad; + return 0; +} + +/** + * \brief Starts a DAC transfer. This is a non blocking function. It will + * return as soon as the transfer is started. + * + * \param pDacd Pointer to a DacDma instance. + * \param pCommand Pointer to the Dac command to execute. + * \returns 0 if the transfer has been started successfully; otherwise returns + * DAC_ERROR_LOCK is the driver is in use, or DAC_ERROR if the command is not + * valid. + */ +uint32_t Dac_SendData( DacDma *pDacd, DacCmd *pCommand) +{ + Dacc *pDacHw = pDacd->pDacHw; + + /* Try to get the dataflash semaphore */ + if (pDacd->semaphore == 0) { + return DAC_ERROR_LOCK; + } + pDacd->semaphore--; + + // Initialize the callback + pDacd->pCurrentCommand = pCommand; + + /* Initialize DMA controller using channel 0 for RX. */ + if (_DacConfigureDmaChannels(pDacd) ) + return DAC_ERROR_LOCK; + + if (_Dac_configureLinkList(pDacHw, pDacd->pXdmad, pCommand)) + return DAC_ERROR_LOCK; + + SCB_CleanDCache(); + + /* Start DMA TX */ + if (XDMAD_StartTransfer( pDacd->pXdmad, dacDmaTxChannel )) + return DAC_ERROR_LOCK; + return DAC_OK;; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/efc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/efc.c new file mode 100644 index 000000000..8fc5263b6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/efc.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup efc_module Working with EEFC + * + * The EEFC driver provides the interface to configure and use the EEFC + * peripheral. + * + * The user needs to set the number of wait states depending on the frequency + * used.\n + * Configure number of cycles for flash read/write operations in the FWS field + * of EEFC_FMR. + * + * It offers a function to send flash command to EEFC and waits for the + * flash to be ready. + * + * To send flash command, the user could do in either of following way: + *
      + *
    • Write a correct key, command and argument in EEFC_FCR.
      • + *
    • Or, Use IAP (In Application Programming) function which is executed from + * ROM directly, this allows flash programming to be done by code running in + * flash.
      • + *
    • Once the command is achieved, it can be detected even by polling + * EEFC_FSR or interrupt. + *
    + * + * The command argument could be a page number,GPNVM number or nothing, it + * depends on the command itself. Some useful functions in this driver could + * help user translate physical flash address into a page number and vice verse. + * + * For more accurate information, please look at the EEFC section of the + * Datasheet. + * + * Related files :\n + * \ref efc.c\n + * \ref efc.h.\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Enhanced Embedded Flash Controller (EEFC). + * + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +#define EEFC_FCR_FCMD(value) ((EEFC_FCR_FCMD_Msk & ((value) << EEFC_FCR_FCMD_Pos))) + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +extern void EFC_WriteFMR( Efc* efc, uint32_t dwFmr ); + +#ifdef __ICCARM__ +extern __ramfunc void EFC_WriteFMR( Efc* efc, uint32_t dwFmr ) +#else + __attribute__ ((section (".ramfunc"))) +extern void EFC_WriteFMR( Efc* efc, uint32_t dwFmr ) +#endif +{ + efc->EEFC_FMR = dwFmr; +} + +/** + * \brief Enables the flash ready interrupt source on the EEFC peripheral. + * + * \param efc Pointer to a Efc instance + */ +extern void EFC_EnableFrdyIt( Efc* efc ) +{ + uint32_t dwFmr; + + dwFmr = efc->EEFC_FMR |= EEFC_FMR_FRDY; + EFC_WriteFMR(efc, dwFmr); +} + +/** + * \brief Disables the flash ready interrupt source on the EEFC peripheral. + * + * \param efc Pointer to a Efc instance + */ +extern void EFC_DisableFrdyIt( Efc* efc ) +{ + uint32_t dwFmr; + + dwFmr = efc->EEFC_FMR & (~EEFC_FMR_FRDY); + EFC_WriteFMR(efc, dwFmr); +} + + +/** + * \brief Set read/write wait state on the EEFC peripheral. + * + * \param efc Pointer to a Efc instance + * \param cycles the number of wait states in cycle. + */ +extern void EFC_SetWaitState( Efc* efc, uint8_t ucCycles ) +{ + uint32_t dwFmr ; + + dwFmr = efc->EEFC_FMR ; + dwFmr &= ~((uint32_t)EEFC_FMR_FWS_Msk) ; + dwFmr |= EEFC_FMR_FWS(ucCycles); + EFC_WriteFMR(efc, dwFmr); +} + +/** + * \brief Returns the current status of the EEFC. + * + * \note Keep in mind that this function clears the value of some status bits + * (LOCKE, PROGE). + * + * \param efc Pointer to a Efc instance + */ +extern uint32_t EFC_GetStatus( Efc* efc ) +{ + return efc->EEFC_FSR ; +} + +/** + * \brief Returns the result of the last executed command. + * + * \param efc Pointer to a Efc instance + */ +extern uint32_t EFC_GetResult( Efc* efc ) +{ + return efc->EEFC_FRR ; +} + +/** + * \brief Translates the given address page and offset values. + * \note The resulting values are stored in the provided variables if they are + * not null. + * + * \param efc Pointer to a Efc instance + * \param address Address to translate. + * \param pPage First page accessed. + * \param pOffset Byte offset in first page. + */ +extern void EFC_TranslateAddress( Efc** ppEfc, uint32_t dwAddress, uint16_t* pwPage, + uint16_t* pwOffset ) +{ + assert( dwAddress >= IFLASH_ADDR ) ; + assert( dwAddress <= (IFLASH_ADDR + IFLASH_SIZE) ) ; + + /* Store values */ + if ( ppEfc ) { + *ppEfc = EFC ; + } + + if ( pwPage ) { + *pwPage = (dwAddress - IFLASH_ADDR) / IFLASH_PAGE_SIZE ; + } + + if ( pwOffset ) { + *pwOffset = (dwAddress - IFLASH_ADDR) % IFLASH_PAGE_SIZE; ; + } +} + + +/** + * \brief Computes the address of a flash access given the page and offset. + * + * \param efc Pointer to a Efc instance + * \param page Page number. + * \param offset Byte offset inside page. + * \param pAddress Computed address (optional). + */ +extern void EFC_ComputeAddress( Efc *efc, uint16_t wPage, uint16_t wOffset, + uint32_t *pdwAddress ) +{ + uint32_t dwAddress ; + + /* Stop warning */ + efc = efc; + + assert( efc ) ; + assert( wPage <= IFLASH_NB_OF_PAGES ) ; + assert( wOffset < IFLASH_PAGE_SIZE ) ; + dwAddress = IFLASH_ADDR + wPage * IFLASH_PAGE_SIZE + wOffset ; + + /* Store result */ + if ( pdwAddress != NULL ) { + *pdwAddress = dwAddress ; + } +} + +/** + * \brief Performs the given command and wait until its completion (or an error). + * + * \param efc Pointer to a Efc instance + * \param command Command to perform. + * \param argument Optional command argument. + * + * \return 0 if successful, otherwise returns an error code. + */ + +extern uint32_t EFC_PerformCommand( Efc* efc, uint32_t dwCommand, + uint32_t dwArgument, uint32_t dwUseIAP ) +{ + if ( dwUseIAP != 0 ) { + /* Pointer on IAP function in ROM */ + static uint32_t (*IAP_PerformCommand)( uint32_t, uint32_t ) ; + + IAP_PerformCommand = (uint32_t (*)( uint32_t, uint32_t )) + *((uint32_t*)CHIP_FLASH_IAP_ADDRESS ) ; + if (efc == EFC) { + IAP_PerformCommand( 0, EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(dwArgument) + | EEFC_FCR_FCMD(dwCommand) ) ; + } + return (efc->EEFC_FSR & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR)) ; + } else { + uint32_t dwStatus ; + + efc->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EEFC_FCR_FARG(dwArgument) + | EEFC_FCR_FCMD(dwCommand) ; + do { + dwStatus = efc->EEFC_FSR ; + } + while ( (dwStatus & EEFC_FSR_FRDY) != EEFC_FSR_FRDY ) ; + + return ( dwStatus & (EEFC_FSR_FLOCKE | EEFC_FSR_FCMDE | EEFC_FSR_FLERR) ) ; + } +} + +/** + * \brief Set flash access mode. + * + * \param dwMode - 0:128-bit, (1<<24):64-bit + */ +extern void EFC_SetFlashAccessMode(Efc* efc, uint32_t dwMode) +{ + uint32_t dwFmr; + + dwFmr = dwMode; + EFC_WriteFMR(efc, dwFmr); +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/exceptions.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/exceptions.c new file mode 100644 index 000000000..066bee15c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/exceptions.c @@ -0,0 +1,210 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * This file contains the default exception handlers. + * + * \note + * The exception handler has weak aliases. + * As they are weak aliases, any function with the same name will override + * this definition. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Default NMI interrupt handler. + */ +void NMI_Handler( void ) +{ + while ( 1 ) ; +} + +/** + * \brief This function back trace the stack to give exact address where fault + happened +**/ +#if (TRACE_LEVEL > 4) +__STATIC_INLINE uint32_t StackUnwind(void) +{ + uint32_t Fault_Add; + +#if defined (__CC_ARM) + uint32_t temp; + __ASM("mrs temp, msp "); + __ASM{ ldr Fault_Add, [temp,#28]} +#else + __ASM("mrs r0, msp "); + __ASM("ldr %0, [r0,#28]" : "=r" (Fault_Add)); +#endif + return Fault_Add; +} +#endif + +/** + * \brief If Other Faults are enabled then HardFault error will look for those + * errors to give more detail about fault +**/ +static void HardFault_reason(void) +{ + uint32_t CFSRValue; + TRACE_DEBUG("In Hard Fault Handler\n\r"); + TRACE_DEBUG("SCB->HFSR = 0x%08x\n\r", SCB->HFSR); + + if ((SCB->HFSR & SCB_HFSR_DEBUGEVT_Msk)) { + TRACE_DEBUG("Debug Event Hard Fault\n\r"); + TRACE_DEBUG("SCB->DFSR = 0x%08x\n", SCB->DFSR ); + } + + if ((SCB->HFSR & SCB_HFSR_VECTTBL_Msk)) { + TRACE_DEBUG("Fault was due to vector table read on \ + exception processing\n\r"); + } + // Forced HardFault + if ((SCB->HFSR & SCB_HFSR_FORCED_Msk)) { + TRACE_DEBUG("Forced Hard Fault\n\r"); + TRACE_DEBUG("SCB->CFSR = 0x%08x\n\r", SCB->CFSR ); + // Usage Fault + if((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk)) + { + CFSRValue = SCB->CFSR; + TRACE_DEBUG("Usage fault: "); + CFSRValue >>= SCB_CFSR_USGFAULTSR_Pos; + if((CFSRValue & (1 << 9))) { + TRACE_DEBUG("Divide by zero\n\r"); + } + if((CFSRValue & (1 << 8))) { + TRACE_DEBUG("Unaligned access error\n\r"); + } + if((CFSRValue & (1 << 3))) { + TRACE_DEBUG("Coprocessor access error\n\r"); + } + if((CFSRValue & (1 << 2))) { + TRACE_DEBUG("Integrity check error on EXC_RETURN\n\r"); + } + } + // Bus Fault + if((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk)) { + CFSRValue = SCB->CFSR; + TRACE_DEBUG("Bus fault: "); + CFSRValue >>= SCB_CFSR_BUSFAULTSR_Pos; + + if((CFSRValue & (1 << 7)) && (CFSRValue & (1 << 1))) { + TRACE_DEBUG("Precise data access error. Bus Fault Address \ + Register is: %x \n\r", SCB->BFAR ); + } + if((CFSRValue & (1 << 4))) { + TRACE_DEBUG("Bus fault has occurred on exception entry\n\r"); + } + if((CFSRValue & (1 << 3))) { + TRACE_DEBUG("bus fault has occurred on exception return\n\r"); + } + if((CFSRValue & (1 << 2))) { + TRACE_DEBUG("Imprecise data access error\n\r"); + } + + if((CFSRValue & (1 << 0))) { + TRACE_DEBUG("This bit indicates a bus fault on an instruction \ + pre-fetch. \n\r"); + } + } + } + // MemoryFault + if((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk)) { + CFSRValue = SCB->CFSR; + TRACE_DEBUG("Memory fault: "); + CFSRValue >>= SCB_CFSR_MEMFAULTSR_Pos; + if((CFSRValue & (1 << 9)) != 0) { + TRACE_DEBUG("Divide by zero\n\r"); + } + } + __ISB(); + __DMB(); + __ASM volatile("BKPT #01"); +} +/** + * \brief Default HardFault interrupt handler. + */ + +void HardFault_Handler( void ) +{ + TRACE_DEBUG("\n\rHardFault at address 0X%x\n\r", StackUnwind()); + __ISB(); + __DMB(); + HardFault_reason(); +} + +#ifndef MPU_EXAMPLE_FEATURE +/** + * \brief Default MemManage interrupt handler. + */ +void MemManage_Handler( void ) +{ + TRACE_DEBUG("\n\rMemoryMemFault (MPU fault) at address 0X%x\n\r", + StackUnwind()); + __ISB(); + __DMB(); + __ASM volatile("BKPT #01"); +} +#endif + +/** + * \brief Default BusFault interrupt handler. + */ +void BusFault_Handler( void ) +{ + __ASM("nop"); + __ASM("nop"); + TRACE_DEBUG("\n\rBus Fault at address 0X%x\n\r", StackUnwind()); + + __ISB(); + __DMB(); + __ASM volatile("BKPT #01"); +} + +/** + * \brief Default UsageFault interrupt handler. + */ +void UsageFault_Handler( void ) +{ + TRACE_DEBUG("\r\nUsage fault at address 0X%x", StackUnwind()); + + __ISB(); + __DMB(); + __ASM volatile("BKPT #01"); +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/flashd.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/flashd.c new file mode 100644 index 000000000..b6b5b66ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/flashd.c @@ -0,0 +1,585 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup flashd_module Flash Memory Interface + * The flash driver manages the programming, erasing, locking and unlocking + * sequences with dedicated commands. + * + * To implement flash programming operation, the user has to follow these few + * steps : + *
      + *
    • Configure flash wait states to initializes the flash.
      • + *
    • Checks whether a region to be programmed is locked.
      • + *
    • Unlocks the user region to be programmed if the region have locked + * before.
      • + *
    • Erases the user page before program (optional).
      • + *
    • Writes the user page from the page buffer.
      • + *
    • Locks the region of programmed area if any.
      • + *
    + * + * Writing 8-bit and 16-bit data is not allowed and may lead to unpredictable + * data corruption. + * A check of this validity and padding for 32-bit alignment should be done in + * write algorithm. + * Lock/unlock range associated with the user address range is automatically + * translated. + * + * This security bit can be enabled through the command "Set General Purpose + * NVM Bit 0". + * + * A 128-bit factory programmed unique ID could be read to serve several + * purposes. + * + * The driver accesses the flash memory by calling the lowlevel module provided + * in \ref efc_module. + * For more accurate information, please look at the EEFC section of the + * Datasheet. + * + * Related files :\n + * \ref flashd.c\n + * \ref flashd.h.\n + * \ref efc.c\n + * \ref efc.h.\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * The flash driver provides the unified interface for flash program operations. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +#define GPNVM_NUM_MAX 9 + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +static uint32_t _pdwPageBuffer[IFLASH_PAGE_SIZE/sizeof(uint32_t)] ; +static uint32_t _dwUseIAP = 1; /* Use IAP interface by default. */ + + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + + +/** + * \brief Computes the lock range associated with the given address range. + * + * \param dwStart Start address of lock range. + * \param dwEnd End address of lock range. + * \param pdwActualStart Actual start address of lock range. + * \param pdwActualEnd Actual end address of lock range. + */ +static void ComputeLockRange( uint32_t dwStart, uint32_t dwEnd, + uint32_t *pdwActualStart, uint32_t *pdwActualEnd ) +{ + Efc* pStartEfc ; + Efc* pEndEfc ; + uint16_t wStartPage ; + uint16_t wEndPage ; + uint16_t wNumPagesInRegion ; + uint16_t wActualStartPage ; + uint16_t wActualEndPage ; + + /* Convert start and end address in page numbers */ + EFC_TranslateAddress( &pStartEfc, dwStart, &wStartPage, 0 ) ; + EFC_TranslateAddress( &pEndEfc, dwEnd, &wEndPage, 0 ) ; + + /* Find out the first page of the first region to lock */ + wNumPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ; + wActualStartPage = wStartPage - (wStartPage % wNumPagesInRegion) ; + wActualEndPage = wEndPage ; + + if ( (wEndPage % wNumPagesInRegion) != 0 ) { + wActualEndPage += wNumPagesInRegion - (wEndPage % wNumPagesInRegion) ; + } + /* Store actual page numbers */ + EFC_ComputeAddress( pStartEfc, wActualStartPage, 0, pdwActualStart ) ; + EFC_ComputeAddress( pEndEfc, wActualEndPage, 0, pdwActualEnd ) ; + TRACE_DEBUG( "Actual lock range is 0x%06X - 0x%06X\n\r", + (unsigned int)*pdwActualStart, (unsigned int)*pdwActualEnd ) ; +} + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Initializes the flash driver. + * + * \param dwMCk Master clock frequency in Hz. + * \param dwUseIAP 0: use EEFC controller interface, 1: use IAP interface. + * dwUseIAP should be set to 1 when running out of flash. + */ + +extern void FLASHD_Initialize( uint32_t dwMCk, uint32_t dwUseIAP ) +{ + dwMCk = dwMCk; /* avoid warnings */ + + EFC_DisableFrdyIt( EFC ) ; + _dwUseIAP = dwUseIAP ; +} + +/** + * \brief Erases the entire flash. + * + * \param dwAddress Flash start address. + * \return 0 if successful; otherwise returns an error code. + */ +extern uint32_t FLASHD_Erase( uint32_t dwAddress ) +{ + Efc* pEfc ; + uint16_t wPage ; + uint16_t wOffset ; + uint32_t dwError ; + + assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ; + + /* Translate write address */ + EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ; + dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EA, 0, _dwUseIAP ) ; + + return dwError ; +} + +/** + * \brief Erases flash by sector. + * + * \param dwAddress Start address of be erased sector. + * + * \return 0 if successful; otherwise returns an error code. + */ +extern uint32_t FLASHD_EraseSector( uint32_t dwAddress ) +{ + Efc* pEfc ; + uint16_t wPage ; + uint16_t wOffset ; + uint32_t dwError ; + + assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ; + + /* Translate write address */ + EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ; + dwError = EFC_PerformCommand( pEfc, EFC_FCMD_ES, wPage, _dwUseIAP ) ; + + return dwError ; +} + +/** + * \brief Erases flash by pages. + * + * \param dwAddress Start address of be erased pages. + * \param dwPageNum Number of pages to be erased with EPA command (4, 8, 16, 32) + * + * \return 0 if successful; otherwise returns an error code. + */ +extern uint32_t FLASHD_ErasePages( uint32_t dwAddress, uint32_t dwPageNum ) +{ + Efc* pEfc ; + uint16_t wPage ; + uint16_t wOffset ; + uint32_t dwError ; + static uint32_t dwFarg ; + + assert( (dwAddress >=IFLASH_ADDR) || (dwAddress <= (IFLASH_ADDR + IFLASH_SIZE)) ) ; + + /* Translate write address */ + EFC_TranslateAddress( &pEfc, dwAddress, &wPage, &wOffset ) ; + + /* Get FARG field for EPA command: + * The first page to be erased is specified in the FARG[15:2] field of + * the MC_FCR register. The first page number must be modulo 4, 8,16 or 32 + * according to the number of pages to erase at the same time. + * + * The 2 lowest bits of the FARG field define the number of pages to + * be erased (FARG[1:0]). + */ + if (dwPageNum == 32) { + wPage &= ~(32u - 1u); + dwFarg = (wPage << 2) | 3; /* 32 pages */ + } else if (dwPageNum == 16) { + wPage &= ~(16u - 1u); + dwFarg = (wPage << 2) | 2; /* 16 pages */ + } else if (dwPageNum == 8) { + wPage &= ~(8u - 1u); + dwFarg = (wPage << 2) | 1; /* 8 pages */ + } else { + wPage &= ~(4u - 1u); + dwFarg = (wPage << 2) | 0; /* 4 pages */ + } + dwError = EFC_PerformCommand( pEfc, EFC_FCMD_EPA, dwFarg, _dwUseIAP ) ; + + return dwError ; +} + + +/** + * \brief Writes a data buffer in the internal flash + * + * \note This function works in polling mode, and thus only returns when the + * data has been effectively written. + * \param address Write address. + * \param pBuffer Data buffer. + * \param size Size of data buffer in bytes. + * \return 0 if successful, otherwise returns an error code. + */ +extern uint32_t FLASHD_Write( uint32_t dwAddress, + const void *pvBuffer, uint32_t dwSize ) +{ + Efc* pEfc ; + uint16_t page ; + uint16_t offset ; + uint32_t writeSize ; + uint32_t pageAddress ; + uint16_t padding ; + uint32_t dwError ; + uint32_t dwIdx ; + uint32_t *pAlignedDestination ; + uint8_t *pucPageBuffer = (uint8_t *)_pdwPageBuffer; + + assert( pvBuffer ) ; + assert( dwAddress >=IFLASH_ADDR ) ; + assert( (dwAddress + dwSize) <= (IFLASH_ADDR + IFLASH_SIZE) ) ; + + /* Translate write address */ + EFC_TranslateAddress( &pEfc, dwAddress, &page, &offset ) ; + + /* Write all pages */ + while ( dwSize > 0 ) { + /* Copy data in temporary buffer to avoid alignment problems */ + writeSize = min((uint32_t)IFLASH_PAGE_SIZE - offset, dwSize ) ; + EFC_ComputeAddress(pEfc, page, 0, &pageAddress ) ; + padding = IFLASH_PAGE_SIZE - offset - writeSize ; + + /* Pre-buffer data */ + memcpy( pucPageBuffer, (void *) pageAddress, offset); + + /* Buffer data */ + memcpy( pucPageBuffer + offset, pvBuffer, writeSize); + + /* Post-buffer data */ + memcpy( pucPageBuffer + offset + writeSize, + (void *) (pageAddress + offset + writeSize), padding); + + /* Write page + * Writing 8-bit and 16-bit data is not allowed and may + lead to unpredictable data corruption + */ + pAlignedDestination = (uint32_t*)pageAddress ; + for (dwIdx = 0; dwIdx < (IFLASH_PAGE_SIZE / sizeof(uint32_t)); ++ dwIdx) { + *pAlignedDestination++ = _pdwPageBuffer[dwIdx]; + memory_barrier() + } + + /* Note: It is not possible to use Erase and write Command (EWP) on all Flash + (this command is available on the First 2 Small Sector, 16K Bytes). + For the next block, Erase them first then use Write page command. */ + + /* Send writing command */ + dwError = EFC_PerformCommand( pEfc, EFC_FCMD_WP, page, _dwUseIAP ) ; + if ( dwError ) { + return dwError ; + } + + /* Progression */ + pvBuffer = (void *)((uint32_t) pvBuffer + writeSize) ; + dwSize -= writeSize ; + page++; + offset = 0; + } + + return 0 ; +} + +/** + * \brief Locks all the regions in the given address range. The actual lock + * range is reported through two output parameters. + * + * \param start Start address of lock range. + * \param end End address of lock range. + * \param pActualStart Start address of the actual lock range (optional). + * \param pActualEnd End address of the actual lock range (optional). + * \return 0 if successful, otherwise returns an error code. + */ +extern uint32_t FLASHD_Lock( uint32_t start, uint32_t end, + uint32_t *pActualStart, uint32_t *pActualEnd ) +{ + Efc *pEfc ; + uint32_t actualStart, actualEnd ; + uint16_t startPage, endPage ; + uint32_t dwError ; + uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE; + + /* Compute actual lock range and store it */ + ComputeLockRange( start, end, &actualStart, &actualEnd ) ; + if ( pActualStart != NULL ) { + *pActualStart = actualStart ; + } + if ( pActualEnd != NULL ) { + *pActualEnd = actualEnd; + } + + /* Compute page numbers */ + EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ; + EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ; + + /* Lock all pages */ + while ( startPage < endPage ) { + dwError = EFC_PerformCommand( pEfc, EFC_FCMD_SLB, startPage, _dwUseIAP ) ; + if ( dwError ) { + return dwError ; + } + startPage += numPagesInRegion; + } + + return 0 ; +} + +/** + * \brief Unlocks all the regions in the given address range. The actual unlock + * range is reported through two output parameters. + * \param start Start address of unlock range. + * \param end End address of unlock range. + * \param pActualStart Start address of the actual unlock range (optional). + * \param pActualEnd End address of the actual unlock range (optional). + * \return 0 if successful, otherwise returns an error code. + */ +extern uint32_t FLASHD_Unlock( uint32_t start, uint32_t end, + uint32_t *pActualStart, uint32_t *pActualEnd ) +{ + Efc* pEfc ; + uint32_t actualStart, actualEnd ; + uint16_t startPage, endPage ; + uint32_t dwError ; + uint16_t numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE; + + /* Compute actual unlock range and store it */ + ComputeLockRange(start, end, &actualStart, &actualEnd); + if ( pActualStart != NULL ) { + *pActualStart = actualStart ; + } + if ( pActualEnd != NULL ) { + *pActualEnd = actualEnd ; + } + + /* Compute page numbers */ + EFC_TranslateAddress( &pEfc, actualStart, &startPage, 0 ) ; + EFC_TranslateAddress( 0, actualEnd, &endPage, 0 ) ; + + /* Unlock all pages */ + while ( startPage < endPage ) { + dwError = EFC_PerformCommand( pEfc, EFC_FCMD_CLB, startPage, _dwUseIAP ) ; + if ( dwError ) { + return dwError ; + } + startPage += numPagesInRegion ; + } + return 0 ; +} + +/** + * \brief Returns the number of locked regions inside the given address range. + * + * \param start Start address of range + * \param end End address of range. + */ +extern uint32_t FLASHD_IsLocked( uint32_t start, uint32_t end ) +{ + uint32_t i, j; + Efc *pEfc ; + uint16_t startPage, endPage ; + uint8_t startRegion, endRegion ; + uint32_t numPagesInRegion ; + uint32_t status[IFLASH_NB_OF_LOCK_BITS / 32u] ; + uint32_t numLockedRegions = 0 ; + + assert( end >= start ) ; + assert( (start >=IFLASH_ADDR) && (end <= IFLASH_ADDR + IFLASH_SIZE) ) ; + + /* Compute page numbers */ + EFC_TranslateAddress( &pEfc, start, &startPage, 0 ) ; + EFC_TranslateAddress( 0, end, &endPage, 0 ) ; + + /* Compute region numbers */ + numPagesInRegion = IFLASH_LOCK_REGION_SIZE / IFLASH_PAGE_SIZE ; + startRegion = startPage / numPagesInRegion ; + endRegion = endPage / numPagesInRegion ; + if ((endPage % numPagesInRegion) != 0) { + endRegion++ ; + } + + /* Retrieve lock status */ + EFC_PerformCommand( pEfc, EFC_FCMD_GLB, 0, _dwUseIAP ) ; + for (i = 0; i < (IFLASH_NB_OF_LOCK_BITS / 32u); i++) { + status[i] = EFC_GetResult( pEfc ) ; + } + + /* Check status of each involved region */ + while ( startRegion < endRegion ) { + i = startRegion / 32u; + j = startRegion % 32u; + if ( (status[i] & (1 << j)) != 0 ) { + numLockedRegions++ ; + } + startRegion++ ; + } + return numLockedRegions ; +} + +/** + * \brief Check if the given GPNVM bit is set or not. + * + * \param gpnvm GPNVM bit index. + * \returns 1 if the given GPNVM bit is currently set; otherwise returns 0. + */ +extern uint32_t FLASHD_IsGPNVMSet( uint8_t ucGPNVM ) +{ + uint32_t dwStatus ; + + assert( ucGPNVM < GPNVM_NUM_MAX ) ; + + /* Get GPNVMs status */ + EFC_PerformCommand( EFC, EFC_FCMD_GFB, 0, _dwUseIAP ) ; + dwStatus = EFC_GetResult( EFC ) ; + + /* Check if GPNVM is set */ + if ( (dwStatus & (1 << ucGPNVM)) != 0 ) { + return 1 ; + } else { + return 0 ; + } +} + +/** + * \brief Sets the selected GPNVM bit. + * + * \param gpnvm GPNVM bit index. + * \returns 0 if successful; otherwise returns an error code. + */ +extern uint32_t FLASHD_SetGPNVM( uint8_t ucGPNVM ) +{ + assert( ucGPNVM < GPNVM_NUM_MAX ) ; + + if ( !FLASHD_IsGPNVMSet( ucGPNVM ) ) { + return EFC_PerformCommand( EFC, EFC_FCMD_SFB, ucGPNVM, _dwUseIAP ) ; + } else { + return 0 ; + } +} + +/** + * \brief Clears the selected GPNVM bit. + * + * \param gpnvm GPNVM bit index. + * \returns 0 if successful; otherwise returns an error code. + */ +extern uint32_t FLASHD_ClearGPNVM( uint8_t ucGPNVM ) +{ + assert( ucGPNVM < GPNVM_NUM_MAX ) ; + + if ( FLASHD_IsGPNVMSet( ucGPNVM ) ) { + return EFC_PerformCommand( EFC, EFC_FCMD_CFB, ucGPNVM, _dwUseIAP ) ; + } else { + return 0 ; + } +} + +/** + * \brief Read the unique ID. + * + * \param pdwUniqueID pointer on a 4bytes char containing the unique ID value. + * \returns 0 if successful; otherwise returns an error code. + */ +#ifdef __ICCARM__ +extern __ramfunc uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) +#else + __attribute__ ((section (".ramfunc"))) +uint32_t FLASHD_ReadUniqueID( uint32_t* pdwUniqueID ) +#endif +{ + uint32_t status ; + if (pdwUniqueID == NULL) { + return 1; + } + + pdwUniqueID[0] = 0 ; + pdwUniqueID[1] = 0 ; + pdwUniqueID[2] = 0 ; + pdwUniqueID[3] = 0 ; + + /* Send the Start Read unique Identifier command (STUI) by writing the Flash + Command Register with the STUI command.*/ + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EFC_FCMD_STUI; + + /* When the Unique Identifier is ready to be read, the FRDY bit in the Flash + Programming Status Register (EEFC_FSR) falls. */ + do { + status = EFC->EEFC_FSR ; + } while ( (status & EEFC_FSR_FRDY) == EEFC_FSR_FRDY ) ; + + /* The Unique Identifier is located in the first 128 bits of the Flash + memory mapping. So, at the address 0x400000-0x40000F. */ + pdwUniqueID[0] = *(uint32_t *)IFLASH_ADDR; + pdwUniqueID[1] = *(uint32_t *)(IFLASH_ADDR + 4); + pdwUniqueID[2] = *(uint32_t *)(IFLASH_ADDR + 8); + pdwUniqueID[3] = *(uint32_t *)(IFLASH_ADDR + 12); + + /* To stop the Unique Identifier mode, the user needs to send the Stop Read + unique Identifier command (SPUI) by writing the Flash Command Register + with the SPUI command. */ + EFC->EEFC_FCR = EEFC_FCR_FKEY_PASSWD | EFC_FCMD_SPUI ; + + /* When the Stop read Unique Unique Identifier command (SPUI) has been + performed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) + rises. */ + do { + status = EFC->EEFC_FSR ; + } while ( (status & EEFC_FSR_FRDY) != EEFC_FSR_FRDY ) ; + + return 0; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/gmac.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/gmac.c new file mode 100644 index 000000000..c1927254a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/gmac.c @@ -0,0 +1,687 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include +#include +#include + + + +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Return 1 if PHY is idle + */ +uint8_t GMAC_IsIdle(Gmac *pGmac) +{ + return ((pGmac->GMAC_NSR & GMAC_NSR_IDLE) > 0); +} + + +/** + * Execute PHY maintenance command + */ +void GMAC_PHYMaintain(Gmac *pGmac, + uint8_t bPhyAddr, + uint8_t bRegAddr, + uint8_t bRW, + uint16_t wData) +{ + /* Wait until bus idle */ + while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Write maintain register */ + pGmac->GMAC_MAN = (~GMAC_MAN_WZO & GMAC_MAN_CLTTO) + | (GMAC_MAN_OP(bRW ? 0x2 : 0x1)) + | GMAC_MAN_WTN(0x02) + | GMAC_MAN_PHYA(bPhyAddr) + | GMAC_MAN_REGA(bRegAddr) + | GMAC_MAN_DATA(wData) ; +} + +/** + * Return PHY maintenance data returned + */ +uint16_t GMAC_PHYData(Gmac *pGmac) +{ + /* Wait until bus idle */ + while((pGmac->GMAC_NSR & GMAC_NSR_IDLE) == 0); + /* Return data */ + return (uint16_t)(pGmac->GMAC_MAN & GMAC_MAN_DATA_Msk); +} + +/** + * \brief Set MDC clock according to current board clock. Per 802.3, MDC should + * be less then 2.5MHz. + * \param pGmac Pointer to an Gmac instance. + * \param mck Mdc clock + * \return 1 if successfully, 0 if MDC clock not found. + */ +uint8_t GMAC_SetMdcClock( Gmac *pGmac, uint32_t mck ) +{ + uint32_t clock_dividor; + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + if (mck <= 20000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_8; // MDC clock = MCK/8 + } else if (mck <= 40000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_16; // MDC clock = MCK/16 + } else if (mck <= 80000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_32; // MDC clock = MCK/32 + } else if (mck <= 160000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_64; // MDC clock = MCK/64 + } else if (mck <= 240000000) { + clock_dividor = GMAC_NCFGR_CLK_MCK_96; // MDC clock = MCK/96 + } else { + TRACE_ERROR("E: No valid MDC clock.\n\r"); + return 0; + } + pGmac->GMAC_NCFGR = (pGmac->GMAC_NCFGR & (~GMAC_NCFGR_CLK_Msk)) | clock_dividor; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); + return 1; +} + +/** + * \brief Enable MDI with PHY + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_EnableMdio( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_NCR |= GMAC_NCR_MPE; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief Enable MDI with PHY + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_DisableMdio( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_NCR &= ~GMAC_NCR_MPE; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief Enable MII mode for GMAC, called once after auto negotiate + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_EnableMII( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + pGmac->GMAC_UR &= ~GMAC_UR_RMII; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief Enable GMII mode for GMAC, called once after auto negotiate + * \param pGmac Pointer to an Gmac instance. + */ +void GMAC_EnableGMII( Gmac *pGmac ) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + /* RGMII disable */ + pGmac->GMAC_UR &= ~GMAC_UR_RMII; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +#define GMAC_NCFGR_GBE (0x1u << 10) +/** + * \brief Enable RGMII mode for GMAC, called once after auto negotiate + * \param pGmac Pointer to an Gmac instance. + * \param duplex: 1 full duplex 0 half duplex + * \param speed: 0 10M 1 100M + */ +void GMAC_EnableRGMII(Gmac *pGmac, uint32_t duplex, uint32_t speed) +{ + pGmac->GMAC_NCR &= ~(GMAC_NCR_RXEN | GMAC_NCR_TXEN); + if (duplex == GMAC_DUPLEX_HALF) { + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_FD; + } else { + pGmac->GMAC_NCFGR |= GMAC_NCFGR_FD; + } + + + if (speed == GMAC_SPEED_10M) { + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_SPD; + } else if(speed == GMAC_SPEED_100M) { + pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; + } else { + pGmac->GMAC_NCFGR |= GMAC_NCFGR_SPD; + } + + /* RGMII enable */ + pGmac->GMAC_UR = 0; + pGmac->GMAC_NCFGR &= ~GMAC_NCFGR_GBE; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); + return; +} + +/** + * \brief Setup the GMAC for the link : speed 100M/10M and Full/Half duplex + * \param pGmac Pointer to an Gmac instance. + * \param speed Link speed, 0 for 10M, 1 for 100M + * \param fullduplex 1 for Full Duplex mode + */ +void GMAC_SetLinkSpeed(Gmac *pGmac, uint8_t speed, uint8_t fullduplex) +{ + uint32_t ncfgr; + ncfgr = pGmac->GMAC_NCFGR; + ncfgr &= ~(GMAC_NCFGR_SPD | GMAC_NCFGR_FD); + if (speed) { + ncfgr |= GMAC_NCFGR_SPD; + } + if (fullduplex) { + ncfgr |= GMAC_NCFGR_FD; + } + pGmac->GMAC_NCFGR = ncfgr; + pGmac->GMAC_NCR |= (GMAC_NCR_RXEN | GMAC_NCR_TXEN); +} + +/** + * \brief set local loop back + * \param pGmac Pointer to an Gmac instance. + */ +uint32_t GMAC_SetLocalLoopBack(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_LBL; + return 0; +} + +/** + * Return interrupt mask. + */ +uint32_t GMAC_GetItMask(Gmac *pGmac, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + return pGmac->GMAC_IMR; + } else { + return pGmac->GMAC_IMRPQ[queueIdx -1]; + } +} + + +/** + * Return transmit status + */ +uint32_t GMAC_GetTxStatus(Gmac *pGmac) +{ + return pGmac->GMAC_TSR; +} + +/** + * Clear transmit status + */ +void GMAC_ClearTxStatus(Gmac *pGmac, uint32_t dwStatus) +{ + pGmac->GMAC_TSR = dwStatus; +} + +/** + * Return receive status + */ +uint32_t GMAC_GetRxStatus(Gmac *pGmac) +{ + return pGmac->GMAC_RSR; +} + +/** + * Clear receive status + */ +void GMAC_ClearRxStatus(Gmac *pGmac, uint32_t dwStatus) +{ + pGmac->GMAC_RSR = dwStatus; +} + + +/** + * Enable/Disable GMAC receive. + */ +void GMAC_ReceiveEnable(Gmac* pGmac, uint8_t bEnaDis) +{ + if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_RXEN; + else pGmac->GMAC_NCR &= ~GMAC_NCR_RXEN; +} + +/** + * Enable/Disable GMAC transmit. + */ +void GMAC_TransmitEnable(Gmac *pGmac, uint8_t bEnaDis) +{ + if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_TXEN; + else pGmac->GMAC_NCR &= ~GMAC_NCR_TXEN; +} + + +/** + * Set Rx Queue + */ +void GMAC_SetRxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + pGmac->GMAC_RBQB = GMAC_RBQB_ADDR_Msk & dwAddr; + } else { + pGmac->GMAC_RBQBAPQ[queueIdx - 1] = GMAC_RBQB_ADDR_Msk & dwAddr; + } +} + +/** + * Get Rx Queue Address + */ +uint32_t GMAC_GetRxQueue(Gmac *pGmac, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + return pGmac->GMAC_RBQB; + } else { + return pGmac->GMAC_RBQBAPQ[queueIdx - 1]; + } +} + +/** + * Set Tx Queue + */ +void GMAC_SetTxQueue(Gmac *pGmac, uint32_t dwAddr, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + pGmac->GMAC_TBQB = GMAC_TBQB_ADDR_Msk & dwAddr; + } else { + pGmac->GMAC_TBQBAPQ[queueIdx - 1] = GMAC_TBQB_ADDR_Msk & dwAddr; + } +} + +/** + * Get Tx Queue + */ +uint32_t GMAC_GetTxQueue(Gmac *pGmac, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + return pGmac->GMAC_TBQB; + } else { + return pGmac->GMAC_TBQBAPQ[queueIdx - 1]; + } +} + + +/** + * Write control value + */ +void GMAC_NetworkControl(Gmac *pGmac, uint32_t bmNCR) +{ + pGmac->GMAC_NCR = bmNCR; +} + + +/** + * Get control value + */ +uint32_t GMAC_GetNetworkControl(Gmac *pGmac) +{ + return pGmac->GMAC_NCR; +} + +/** + * Enable interrupt(s). + */ +void GMAC_EnableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + pGmac->GMAC_IER = dwSources; + } else { + pGmac->GMAC_IERPQ[queueIdx-1] = dwSources; + } +} + +/** + * Disable interrupt(s). + */ +void GMAC_DisableAllQueueIt(Gmac *pGmac, uint32_t dwSources) +{ + pGmac->GMAC_IDR = dwSources; + pGmac->GMAC_IDRPQ[0] = dwSources; + pGmac->GMAC_IDRPQ[1] = dwSources; +} + +/** + * Disable interrupt(s). + */ +void GMAC_EnableAllQueueIt(Gmac *pGmac, uint32_t dwSources) +{ + pGmac->GMAC_IER = dwSources; + pGmac->GMAC_IERPQ[0] = dwSources; + pGmac->GMAC_IERPQ[1] = dwSources; +} + +/** + * Disable interrupt(s). + */ +void GMAC_DisableIt(Gmac *pGmac, uint32_t dwSources, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + pGmac->GMAC_IDR = dwSources; + } else { + pGmac->GMAC_IDRPQ[queueIdx-1] = dwSources; + } +} + +/** + * Return interrupt status. + */ +uint32_t GMAC_GetItStatus(Gmac *pGmac, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + return pGmac->GMAC_ISR; + } else { + return pGmac->GMAC_ISRPQ[queueIdx-1]; + } +} + + +/** + * Set MAC Address + */ +void GMAC_SetAddress(Gmac *pGmac, uint8_t bIndex, uint8_t *pMacAddr) +{ + pGmac->GMAC_SA[bIndex].GMAC_SAB = (pMacAddr[3] << 24) + | (pMacAddr[2] << 16) + | (pMacAddr[1] << 8) + | (pMacAddr[0] ) + ; + pGmac->GMAC_SA[bIndex].GMAC_SAT = (pMacAddr[5] << 8) + | (pMacAddr[4] ) + ; +} + +/** + * Set MAC Address via 2 DW + */ +void GMAC_SetAddress32(Gmac *pGmac, uint8_t bIndex, uint32_t dwMacT, uint32_t dwMacB) +{ + pGmac->GMAC_SA[bIndex].GMAC_SAB = dwMacB; + pGmac->GMAC_SA[bIndex].GMAC_SAT = dwMacT; +} + +/** + * Set MAC Address via int64 + */ +void GMAC_SetAddress64(Gmac *pGmac, uint8_t bIndex, uint64_t ddwMac) +{ + pGmac->GMAC_SA[bIndex].GMAC_SAB = (uint32_t)ddwMac; + pGmac->GMAC_SA[bIndex].GMAC_SAT = (uint32_t)(ddwMac >32); +} + + +/** + * Clear all statistics registers + */ +void GMAC_ClearStatistics(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_CLRSTAT; +} + +/** + * Increase all statistics registers + */ +void GMAC_IncreaseStatistics(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_INCSTAT; +} + +/** + * Enable/Disable statistics registers writing. + */ +void GMAC_StatisticsWriteEnable(Gmac *pGmac, uint8_t bEnaDis) +{ + if (bEnaDis) pGmac->GMAC_NCR |= GMAC_NCR_WESTAT; + else pGmac->GMAC_NCR &= ~GMAC_NCR_WESTAT; +} + + +/** + * Setup network configuration register + */ +void GMAC_Configure(Gmac *pGmac, uint32_t dwCfg) +{ + pGmac->GMAC_NCFGR = dwCfg; +} + + +/** + * Setup DMA configuration register + */ +void GMAC_SetDMAConfig(Gmac *pGmac, uint32_t dwDmaCfg, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + pGmac->GMAC_DCFGR = dwDmaCfg; + } else { + pGmac->GMAC_RBSRPQ[queueIdx-1] = dwDmaCfg; + } +} + +/** + * Return DMA configuration register + */ +uint32_t GMAC_GetDMAConfig(Gmac *pGmac, gmacQueList_t queueIdx) +{ + if(!queueIdx) { + return pGmac->GMAC_DCFGR; + } else { + return pGmac->GMAC_RBSRPQ[queueIdx-1]; + }; +} + +/** + * Return network configuration. + */ +uint32_t GMAC_GetConfigure(Gmac *pGmac) +{ + return pGmac->GMAC_NCFGR; +} + + +/** + * Start transmission + */ +void GMAC_TransmissionStart(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_TSTART; +} + +/** + * Halt transmission + */ +void GMAC_TransmissionHalt(Gmac *pGmac) +{ + pGmac->GMAC_NCR |= GMAC_NCR_THALT; +} + + +/* Screener Register configurations */ +void GMAC_ClearScreener1Reg (Gmac *pGmac, gmacQueList_t queueIdx) +{ + pGmac->GMAC_ST1RPQ[queueIdx] = 0u; +} + +void GMAC_WriteScreener1Reg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t regVal) +{ + pGmac->GMAC_ST1RPQ[queueIdx] = regVal; +} + +void GMAC_ClearScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx) +{ + pGmac->GMAC_ST2RPQ[queueIdx] = 0u; +} + +void GMAC_WriteScreener2Reg (Gmac *pGmac, gmacQueList_t queueIdx, uint32_t regVal) +{ + pGmac->GMAC_ST2RPQ[queueIdx] = regVal; +} + +void GMAC_WriteEthTypeReg (Gmac *pGmac, gmacQueList_t queueIdx, uint16_t etherType) +{ + pGmac->GMAC_ST2ER[queueIdx] = (uint32_t)etherType; +} + +void GMAC_WriteCompareReg(Gmac *pGmac, gmacQueList_t queueIdx, uint32_t c0Reg, + uint16_t c1Reg) +{ + pGmac->GMAC_ST2COMP[queueIdx].GMAC_ST2COM0 = c0Reg; + pGmac->GMAC_ST2COMP[queueIdx].GMAC_ST2COM1 = (uint32_t)c1Reg; + memory_barrier(); +} + +/* CBS queue control APIs */ +void GMAC_EnableCbsQueA(Gmac *pGmac) +{ + pGmac->GMAC_CBSCR |= GMAC_CBSCR_QAE; +} + +void GMAC_DisableCbsQueA(Gmac *pGmac) +{ + pGmac->GMAC_CBSCR &= ~GMAC_CBSCR_QAE; +} + +void GMAC_EnableCbsQueB(Gmac *pGmac) +{ + pGmac->GMAC_CBSCR |= GMAC_CBSCR_QBE; +} + +void GMAC_DisableCbsQueB(Gmac *pGmac) +{ + pGmac->GMAC_CBSCR &= ~GMAC_CBSCR_QBE; +} + + +void GMAC_ConfigIdleSlopeA(Gmac *pGmac, uint32_t idleSlopeA) +{ + /* 10/100 speeds use a 4-bit interface */ + pGmac->GMAC_CBSISQA = idleSlopeA >2u; +} + +void GMAC_ConfigIdleSlopeB(Gmac *pGmac, uint32_t idleSlopeB) +{ + /* 10/100 speeds use a 4-bit interface */ + pGmac->GMAC_CBSISQB = idleSlopeB >2u; +} + +void GMAC_SetTsuTmrIncReg( Gmac *pGmac, uint32_t nanoSec) +{ + pGmac->GMAC_TI = nanoSec; +} + +uint16_t GMAC_GetPtpEvtMsgRxdMsbSec( Gmac *pGmac ) +{ + return (uint16_t)(pGmac->GMAC_EFRSH & GMAC_EFRSH_RUD_Msk); +} + +uint32_t GMAC_GetPtpEvtMsgRxdLsbSec( Gmac *pGmac ) +{ + return (pGmac->GMAC_EFRSL & GMAC_EFRSL_RUD_Msk); +} + +uint32_t GMAC_GetPtpEvtMsgRxdNanoSec( Gmac *pGmac ) +{ + return (pGmac->GMAC_EFRN & GMAC_EFRN_RUD_Msk); +} + +void GMAC_SetTsuCompare(Gmac *pGmac, uint32_t seconds47, uint32_t seconds31, + uint32_t nanosec ) +{ + pGmac->GMAC_SCH = seconds47; + pGmac->GMAC_SCL = seconds31; + pGmac->GMAC_NSC = nanosec; + memory_barrier(); +} + + +void GMAC_SetTsuCompareNanoSec(Gmac *pGmac, uint32_t nanosec) +{ + pGmac->GMAC_NSC = nanosec; +} + +void GMAC_SetTsuCompareSec31(Gmac *pGmac, uint32_t seconds31) +{ + pGmac->GMAC_SCL = seconds31; +} + +void GMAC_SetTsuCompareSec47(Gmac *pGmac, uint16_t seconds47) +{ + pGmac->GMAC_SCH = seconds47; +} + + +uint32_t GMAC_GetRxEvtFrameSec(Gmac *pGmac) +{ + return pGmac->GMAC_EFRSL; +} + +uint32_t GMAC_GetRxEvtFrameNsec(Gmac *pGmac) +{ + return pGmac->GMAC_EFRN; +} + +uint32_t GMAC_GetRxPeerEvtFrameSec(Gmac *pGmac) +{ + return pGmac->GMAC_PEFRSL; +} + +uint32_t GMAC_GetRxPeerEvtFrameNsec(Gmac *pGmac) +{ + return pGmac->GMAC_PEFRN; +} + +uint32_t GMAC_GetTxEvtFrameSec(Gmac *pGmac) +{ + return pGmac->GMAC_EFTSL; +} + +uint32_t GMAC_GetTxEvtFrameNsec(Gmac *pGmac) +{ + return pGmac->GMAC_EFTN; +} + +uint32_t GMAC_GetTxPeerEvtFrameSec(Gmac *pGmac) +{ + return pGmac->GMAC_PEFTSL; +} + +uint32_t GMAC_GetTxPeerEvtFrameNsec(Gmac *pGmac) +{ + return pGmac->GMAC_PEFTN; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/gmacd.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/gmacd.c new file mode 100644 index 000000000..01745c1ca --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/gmacd.c @@ -0,0 +1,1022 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + /** \file */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" +#include + +/** \addtogroup gmacd_defines + @{*/ + +/*---------------------------------------------------------------------------- + * Macro + *----------------------------------------------------------------------------*/ +#define GMAC_CACHE +#if defined GMAC_CACHE + #define GMAC_CACHE_COHERENCE {SCB_CleanInvalidateDCache();} +#else + #define GMAC_CACHE_COHERENCE {} +#endif + +/** ISO/IEC 14882:2003(E) - 5.6 Multiplicative operators: + * The binary / operator yields the quotient, and the binary % operator yields + * the remainder from the division of the first expression by the second. + * If the second operand of / or % is zero the behaviour is undefined; otherwise + * (a/b)*b + a%b is equal to a. + * If both operands are non-negative then the remainder is non-negative; + * if not, the sign of the remainder is implementation-defined 74). + */ +__STATIC_INLINE int fixed_mod(int a, int b) +{ + int rem = a % b; + while (rem < 0) + rem += b; + + return rem; +} + +/** Return count in buffer */ +#define GCIRC_CNT(head,tail,size) fixed_mod((head) - (tail), (size)) + +/** Return space available, 0..size-1. always leave one free char as a + completely full buffer has head == tail, which is the same as empty */ +#define GCIRC_SPACE(head,tail,size) GCIRC_CNT((tail),((head)+1),(size)) + +/** Return count up to the end of the buffer. Carefully avoid accessing head + and tail more than once, so they can change underneath us without returning + inconsistent results */ +#define GCIRC_CNT_TO_END(head,tail,size) \ + ({int end = (size) - (tail); \ + int n = fixed_mod((head) + end, (size)); \ + n < end ? n : end;}) + +/** Return space available up to the end of the buffer */ +#define GCIRC_SPACE_TO_END(head,tail,size) \ + ({int end = (size) - 1 - (head); \ + int n = fixed_mod(end + (tail), (size)); \ + n <= end ? n : end+1;}) + +/** Increment head or tail */ +#define GCIRC_INC(headortail,size) \ + headortail++; \ + if(headortail >= size) { \ + headortail = 0; \ + } + +/** Circular buffer is empty ? */ +#define GCIRC_EMPTY(head, tail) (head == tail) + +/** Clear circular buffer */ +#define GCIRC_CLEAR(head, tail) (head = tail = 0) + +/* This variable holds the write index into gPtpMsgTxQue */ +uint8_t ptpTxQueWriteIdx = 0u; +uint8_t ptpTxQueReadIdx = 0u; + +/* This queue holds the transmit event messages */ +ptpMsgType gPtpMsgTxQue[EFRS_BUFFER_LEN]; +uint16_t gPtpMsgTxSeqId[EFRS_BUFFER_LEN]; + + + +const uint32_t isrMasks[] = { GMAC_IMR_SFT, GMAC_IMR_DRQFT, + GMAC_IMR_PDRQFT , GMAC_IMR_PDRSFT }; + +/*--------------------------------------------------------------------------- + * Local functions + *---------------------------------------------------------------------------*/ + +/** + * \brief Disable TX & reset registers and descriptor list + * \param pDrv Pointer to GMAC Driver instance. + */ +static void GMACD_ResetTx(sGmacd *pDrv, gmacQueList_t queIdx) +{ + Gmac *pHw = pDrv->pHw; + uint8_t *pTxBuffer = pDrv->queueList[queIdx].pTxBuffer; + sGmacTxDescriptor *pTd = pDrv->queueList[queIdx].pTxD; + uint32_t Index; + uint32_t Address; + + /* Disable TX */ + GMAC_TransmitEnable(pHw, 0); + + /* Setup the TX descriptors. */ + GCIRC_CLEAR(pDrv->queueList[queIdx].wTxHead, pDrv->queueList[queIdx].wTxTail); + for(Index = 0; Index < pDrv->queueList[queIdx].wTxListSize; Index++) { + Address = (uint32_t)(&(pTxBuffer[Index * + pDrv->queueList[queIdx].wTxBufferSize])); + pTd[Index].addr = Address; + pTd[Index].status.val = (uint32_t)GMAC_TX_USED_BIT; + } + + pTd[pDrv->queueList[queIdx].wTxListSize - 1].status.val = + GMAC_TX_USED_BIT | GMAC_TX_WRAP_BIT; + + /* Transmit Buffer Queue Pointer Register */ + + GMAC_SetTxQueue(pHw, (uint32_t)pTd, queIdx); +} + +/** + * \brief Disable RX & reset registers and descriptor list + * \param pDrv Pointer to GMAC Driver instance. + */ +static void GMACD_ResetRx(sGmacd *pDrv, gmacQueList_t queIdx ) +{ + Gmac *pHw = pDrv->pHw; + uint8_t *pRxBuffer = pDrv->queueList[queIdx].pRxBuffer; + sGmacRxDescriptor *pRd = pDrv->queueList[queIdx].pRxD; + + uint32_t Index; + uint32_t Address; + + /* Disable RX */ + GMAC_ReceiveEnable(pHw, 0); + + /* Setup the RX descriptors. */ + pDrv->queueList[queIdx].wRxI = 0; + for(Index = 0; Index < pDrv->queueList[queIdx].wRxListSize; Index++) { + Address = (uint32_t)(&(pRxBuffer[Index * + pDrv->queueList[queIdx].wRxBufferSize])); + /* Remove GMAC_RXD_bmOWNERSHIP and GMAC_RXD_bmWRAP */ + pRd[Index].addr.val = Address & GMAC_ADDRESS_MASK; + pRd[Index].status.val = 0; + } + + pRd[pDrv->queueList[queIdx].wRxListSize - 1].addr.val |= GMAC_RX_WRAP_BIT; + + /* Receive Buffer Queue Pointer Register */ + GMAC_SetRxQueue(pHw, (uint32_t)pRd, queIdx); +} + + +/** + * \brief Process successfully sent packets + * \param pGmacd Pointer to GMAC Driver instance. + */ +static void GMACD_TxCompleteHandler(sGmacd *pGmacd, gmacQueList_t qId) +{ + Gmac *pHw = pGmacd->pHw; + sGmacTxDescriptor *pTxTd; + fGmacdTransferCallback fTxCb; + uint32_t tsr; + + /* Clear status */ + tsr = GMAC_GetTxStatus(pHw); + GMAC_ClearTxStatus(pHw, tsr); + + while (!GCIRC_EMPTY( + pGmacd->queueList[qId].wTxHead, pGmacd->queueList[qId].wTxTail)) { + pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail]; + + /* Make hw descriptor updates visible to CPU */ + GMAC_CACHE_COHERENCE + + /* Exit if frame has not been sent yet: + * On TX completion, the GMAC set the USED bit only into the + * very first buffer descriptor of the sent frame. + * Otherwise it updates this descriptor with status error bits. + * This is the descriptor write back. + */ + if ((pTxTd->status.val & GMAC_TX_USED_BIT) == 0) + break; + + /* Process all buffers of the current transmitted frame */ + while ((pTxTd->status.val & GMAC_TX_LAST_BUFFER_BIT) == 0) { + GCIRC_INC(pGmacd->queueList[qId].wTxTail, + pGmacd->queueList[qId].wTxListSize); + pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail]; + memory_sync(); + } + + /* Notify upper layer that a frame has been sent */ + fTxCb = pGmacd->queueList[qId].fTxCbList[pGmacd->queueList[qId].wTxTail]; + if (fTxCb) + fTxCb(tsr); + + /* Go to next frame */ + GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize); + } + + /* If a wakeup has been scheduled, notify upper layer that it can + send other packets, send will be successful. */ + if (pGmacd->queueList[qId].fWakupCb && + GCIRC_SPACE(pGmacd->queueList[qId].wTxHead, + pGmacd->queueList[qId].wTxTail, + pGmacd->queueList[qId].wTxListSize) >= + pGmacd->queueList[qId].bWakeupThreshold) + pGmacd->queueList[qId].fWakupCb(); +} + + +/** + * \brief Reset TX queue when errors are detected + * \param pGmacd Pointer to GMAC Driver instance. + */ +static void GMACD_TxErrorHandler(sGmacd *pGmacd, gmacQueList_t qId) +{ + Gmac *pHw = pGmacd->pHw; + sGmacTxDescriptor *pTxTd; + fGmacdTransferCallback fTxCb; + uint32_t tsr; + + /* Clear TXEN bit into the Network Configuration Register: + * this is a workaround to recover from TX lockups that + * occur on sama5d3 gmac (r1p24f2) when using scatter-gather. + * This issue has never been seen on sama5d4 gmac (r1p31). + */ + GMAC_TransmitEnable(pHw, 0); + + /* The following step should be optional since this function is called + * directly by the IRQ handler. Indeed, according to Cadence + * documentation, the transmission is halted on errors such as + * too many retries or transmit under run. + * However it would become mandatory if the call of this function + * were scheduled as a task by the IRQ handler (this is how Linux + * driver works). Then this function might compete with GMACD_Send(). + * + * Setting bit 10, tx_halt, of the Network Control Register is not enough: + * We should wait for bit 3, tx_go, of the Transmit Status Register to + * be cleared at transmit completion if a frame is being transmitted. + */ + GMAC_TransmissionHalt(pHw); + while (GMAC_GetTxStatus(pHw) & GMAC_TSR_TXGO); + + /* Treat frames in TX queue including the ones that caused the error. */ + while (!GCIRC_EMPTY(pGmacd->queueList[qId].wTxHead, + pGmacd->queueList[qId].wTxTail)) { + int tx_completed = 0; + pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail]; + + /* Make hw descriptor updates visible to CPU */ + GMAC_CACHE_COHERENCE + /* Check USED bit on the very first buffer descriptor to validate + * TX completion. + */ + if (pTxTd->status.val & GMAC_TX_USED_BIT) + tx_completed = 1; + + /* Go to the last buffer descriptor of the frame */ + while ((pTxTd->status.val & GMAC_TX_LAST_BUFFER_BIT) == 0) { + GCIRC_INC(pGmacd->queueList[qId].wTxTail, + pGmacd->queueList[qId].wTxListSize); + pTxTd = &pGmacd->queueList[qId].pTxD[pGmacd->queueList[qId].wTxTail]; + GMAC_CACHE_COHERENCE + } + + /* Notify upper layer that a frame status */ + fTxCb = pGmacd->queueList[qId].fTxCbList[pGmacd->queueList[qId].wTxTail]; + if (fTxCb) + fTxCb(tx_completed ? GMAC_TSR_TXCOMP : 0); + // TODO: which error to notify? + + /* Go to next frame */ + GCIRC_INC(pGmacd->queueList[qId].wTxTail, pGmacd->queueList[qId].wTxListSize); + } + + /* Reset TX queue */ + GMACD_ResetTx(pGmacd, qId); + + /* Clear status */ + tsr = GMAC_GetTxStatus(pHw); + GMAC_ClearTxStatus(pHw, tsr); + + /* Now we are ready to start transmission again */ + GMAC_TransmitEnable(pHw, 1); + if (pGmacd->queueList[qId].fWakupCb) + pGmacd->queueList[qId].fWakupCb(); +} + + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + + +#ifndef PTP_1588_TX_DISABLE + +void GMACD_TxPtpEvtMsgCBRegister (sGmacd * pGmacd, + fGmacdTxPtpEvtCallBack pTxPtpEvtCb, gmacQueList_t queIdx) +{ + pGmacd->queueList[queIdx].fTxPtpEvtCb = pTxPtpEvtCb; +} + +#endif /* #ifdef PTP_1588_TX_DISABLE */ + +/** + * \brief GMAC Interrupt handler + * \param pGmacd Pointer to GMAC Driver instance. + */ +void GMACD_Handler(sGmacd *pGmacd, gmacQueList_t queIdx) +{ + Gmac *pHw = pGmacd->pHw; + uint32_t isr; + uint32_t rsr; + + /* Interrupt Status Register is cleared on read */ + while ( (isr = GMAC_GetItStatus(pHw, queIdx)) !=0) { + /* Sync Frame Received - PTP */ + if(0u != (isr & GMAC_ISR_SFR)) { + rsr = GMAC_ISR_SFR; + memory_barrier(); + /* Invoke callbacks */ + if (pGmacd->queueList[queIdx].fRxCb) { + pGmacd->queueList[queIdx].fRxCb(rsr); + } else { + } + } else { + } + + /* Peer Delay Request Frame Received - PTP */ + if (0u != (isr & GMAC_ISR_PDRQFR) ) { + rsr = GMAC_ISR_PDRQFR; + memory_barrier(); + + /* Invoke callbacks */ + if (pGmacd->queueList[queIdx].fRxCb) { + pGmacd->queueList[queIdx].fRxCb(rsr); + } else { + } + } else { + } + + /* Peer Delay Response Frame Received - PTP */ + if (0u != (isr & GMAC_ISR_PDRSFR) ) { + + rsr = GMAC_ISR_PDRSFR; + memory_barrier(); + + /* Invoke callbacks */ + if (pGmacd->queueList[queIdx].fRxCb) { + pGmacd->queueList[queIdx].fRxCb(rsr); + } else { + } + } else { + } + + if( 0u != (isr & GMAC_ISR_TSU)) { + /* Invoke call back with flag set to TSU comparison interrupt */ + rsr = GMAC_ISR_TSU; + memory_barrier(); + + /* Invoke callbacks */ + if (pGmacd->queueList[queIdx].fRxCb) { + pGmacd->queueList[queIdx].fRxCb(rsr); + } else { + } + } else { + } + + /* RX packet */ + if (isr & GMAC_INT_RX_BITS) { + /* Clear status */ + rsr = GMAC_GetRxStatus(pHw); + GMAC_ClearRxStatus(pHw, rsr); + + /* Invoke callback */ + if (pGmacd->queueList[queIdx].fRxCb) + pGmacd->queueList[queIdx].fRxCb(rsr); + } + + /* TX error */ + if (isr & GMAC_INT_TX_ERR_BITS) { + GMACD_TxErrorHandler(pGmacd, queIdx); + break; + } + +#ifndef PTP_1588_TX_DISABLE + /* Transmit of SYNC / PDELAY_REQ / PDELAY_RSP */ + if(0u != (isr & isrMasks[gPtpMsgTxQue[ptpTxQueReadIdx]])) { + /* Invoke callback */ + /* Check if it is possible for multiple messages to be triggered + within a single isr. If so, a loop may be needed to validate the top + of the queue with the actual interrupt that has been triggered */ +/* while(0u != (isr & (GMAC_IMR_SFT | GMAC_IMR_PDRQFT | GMAC_IMR_PDRSFT))) { */ + if (pGmacd->queueList[queIdx].fTxPtpEvtCb) { + switch (gPtpMsgTxQue[ptpTxQueReadIdx]) { + case SYNC_MSG_TYPE: + pGmacd->queueList[queIdx].fTxPtpEvtCb + (gPtpMsgTxQue[ptpTxQueReadIdx], + GMAC_GetTxEvtFrameSec(pHw), + GMAC_GetTxEvtFrameNsec(pHw), + gPtpMsgTxSeqId[ptpTxQueReadIdx]); + isr &= GMAC_IMR_SFT; + break; + case PDELAY_REQ_TYPE: + pGmacd->queueList[queIdx].fTxPtpEvtCb + (gPtpMsgTxQue[ptpTxQueReadIdx], + GMAC_GetTxPeerEvtFrameSec(pHw), + GMAC_GetTxPeerEvtFrameNsec(pHw), + gPtpMsgTxSeqId[ptpTxQueReadIdx]); + isr &= GMAC_IMR_PDRQFT; + break; + case PDELAY_RESP_TYPE: + pGmacd->queueList[queIdx].fTxPtpEvtCb + (gPtpMsgTxQue[ptpTxQueReadIdx], + GMAC_GetTxPeerEvtFrameSec(pHw), + GMAC_GetTxPeerEvtFrameNsec(pHw), + gPtpMsgTxSeqId[ptpTxQueReadIdx]); + isr &= GMAC_IMR_PDRSFT; + break; + default: + /* Only for Peer messages & sync messages */ + break; + }; + } else { + } + + ptpTxQueReadIdx++; + ptpTxQueReadIdx &= (EFRS_BUFFER_LEN-1); + + } else { + /* if(0u != (isr & isrMasks[gPtpMsgTxQue[ptpTxQueReadIdx]])) */ + } +#endif /* #ifndef PTP_1588_TX_DISABLE */ + /* TX packet */ + if (isr & GMAC_IER_TCOMP) + GMACD_TxCompleteHandler(pGmacd, queIdx); + if (isr & GMAC_IER_HRESP) { + TRACE_ERROR("HRESP\n\r"); + } + } +} + + +/** + * \brief Initialize the GMAC with the Gmac controller address + * \param pGmacd Pointer to GMAC Driver instance. + * \param pHw Pointer to HW address for registers. + * \param bID HW ID for power management + * \param enableCAF Enable/Disable CopyAllFrame. + * \param enableNBC Enable/Disable NoBroadCast. + */ + void GMACD_Init(sGmacd *pGmacd, + Gmac *pHw, + uint8_t bID, + uint8_t enableCAF, + uint8_t enableNBC ) +{ + uint32_t dwNcfgr; + + /* Check parameters */ +// assert(GRX_BUFFERS * GMAC_RX_UNITSIZE > GMAC_FRAME_LENTGH_MAX); + + TRACE_DEBUG("GMAC_Init\n\r"); + + /* Initialize struct */ + pGmacd->pHw = pHw; + pGmacd->bId = bID; + + /* Power ON */ + PMC_EnablePeripheral(bID); + + /* Disable TX & RX and more */ + GMAC_NetworkControl(pHw, 0); + GMAC_DisableAllQueueIt(pHw, ~0u); + + GMAC_ClearStatistics(pHw); + /* Clear all status bits in the receive status register. */ + GMAC_ClearRxStatus(pHw, GMAC_RSR_RXOVR | GMAC_RSR_REC + | GMAC_RSR_BNA |GMAC_RSR_HNO); + + /* Clear all status bits in the transmit status register */ + GMAC_ClearTxStatus(pHw, GMAC_TSR_UBR | GMAC_TSR_COL | GMAC_TSR_RLE + | GMAC_TSR_TXGO | GMAC_TSR_TFC | GMAC_TSR_TXCOMP + | GMAC_TSR_HRESP ); + + /* Clear All interrupts */ + GMAC_GetItStatus(pHw, GMAC_QUE_0); + GMAC_GetItStatus(pHw, GMAC_QUE_1); + GMAC_GetItStatus(pHw, GMAC_QUE_2); + + /* Enable the copy of data into the buffers + ignore broadcasts, and don't copy FCS. */ + dwNcfgr = GMAC_NCFGR_FD | GMAC_NCFGR_DBW(0) | GMAC_NCFGR_CLK_MCK_64 | + GMAC_NCFGR_MAXFS | GMAC_NCFGR_PEN | GMAC_NCFGR_RFCS; + if( enableCAF ) { + dwNcfgr |= GMAC_NCFGR_CAF; + } + if( enableNBC ) { + dwNcfgr |= GMAC_NCFGR_NBC; + } + + GMAC_Configure(pHw, dwNcfgr); +} + + +/** + * Initialize necessary allocated buffer lists for GMAC Driver to transfer data. + * Must be invoked after GMACD_Init() but before RX/TX start. + * Replace the deprecated GMACD_InitTransfer(). + * \param pGmacd Pointer to GMAC Driver instance. + * \param pInit Pointer to sGmacInit. + * \param pInit Pointer to gmacQueList_t for different queue. + * \return GMACD_OK or GMACD_PARAM. + * \note If input address is not 8-byte aligned the address is automatically + * adjusted and the list size is reduced by one. + */ +uint8_t GMACD_InitTransfer(sGmacd *pGmacd, const sGmacInit *pInit, + gmacQueList_t queIdx) +{ + Gmac *pHw = pGmacd->pHw; + uint8_t *pRxBuffer = pInit->pRxBuffer; + sGmacRxDescriptor *pRxD = pInit->pRxD; + uint16_t wRxBufferSize = pInit->wRxBufferSize; + uint16_t wRxSize = pInit->wRxSize; + uint8_t *pTxBuffer = pInit->pTxBuffer; + sGmacTxDescriptor *pTxD = pInit->pTxD; + uint16_t wTxBufferSize = pInit->wTxBufferSize; + uint16_t wTxSize = pInit->wTxSize; + fGmacdTransferCallback *pTxCb = pInit->pTxCb; + uint32_t dwDmaCfg; + if (wRxSize <= 1 || wTxSize <= 1 || pTxCb == NULL) return GMACD_PARAM; + + if (!wRxBufferSize || wRxBufferSize > 16*1024 || wRxBufferSize & 0x3f) + return GMACD_PARAM; + + if (!wTxBufferSize) + return GMACD_PARAM; + + if (pInit->bIsGem) { + if(!queIdx) { + dwDmaCfg = (GMAC_DCFGR_DRBS(wRxBufferSize >> 6) ) + | GMAC_DCFGR_RXBMS(3) | GMAC_DCFGR_TXPBMS; + switch (pInit->bDmaBurstLength) { + case 16: + dwDmaCfg |= GMAC_DCFGR_FBLDO_INCR16; + break; + case 8: + dwDmaCfg |= GMAC_DCFGR_FBLDO_INCR8; + break; + case 4: + dwDmaCfg |= GMAC_DCFGR_FBLDO_INCR4; + break; + case 1: + dwDmaCfg |= GMAC_DCFGR_FBLDO_SINGLE; + break; + default: + return GMACD_PARAM; + break; + } + } else { + dwDmaCfg = (GMAC_RBSRPQ_RBS(wRxBufferSize >> 6) ); + } + GMAC_SetDMAConfig(pHw, dwDmaCfg, queIdx); + } + + pGmacd->queueList[queIdx].wRxBufferSize = wRxBufferSize; + pGmacd->queueList[queIdx].wTxBufferSize = wTxBufferSize; + /* Assign RX buffers */ + if (((uint32_t)pRxBuffer & 0x7) + || ((uint32_t)pRxD & 0x7) ) { + wRxSize --; + TRACE_DEBUG("RX list address adjusted\n\r"); + } + pGmacd->queueList[queIdx].pRxBuffer = (uint8_t*)((uint32_t)pRxBuffer & 0xFFFFFFF8); + pGmacd->queueList[queIdx].pRxD = (sGmacRxDescriptor*)((uint32_t)pRxD & 0xFFFFFFF8); + pGmacd->queueList[queIdx].wRxListSize = wRxSize; + + /* Assign TX buffers */ + if ( ((uint32_t)pTxBuffer & 0x7) + || ((uint32_t)pTxD & 0x7) ) { + wTxSize --; + TRACE_DEBUG("TX list address adjusted\n\r"); + } + pGmacd->queueList[queIdx].pTxBuffer = (uint8_t*)((uint32_t)pTxBuffer & 0xFFFFFFF8); + pGmacd->queueList[queIdx].pTxD = (sGmacTxDescriptor*)((uint32_t)pTxD & 0xFFFFFFF8); + pGmacd->queueList[queIdx].wTxListSize = wTxSize; + pGmacd->queueList[queIdx].fTxCbList = pTxCb; + + /* Reset TX & RX */ + GMACD_ResetRx(pGmacd, queIdx); + GMACD_ResetTx(pGmacd, queIdx); + + /* Setup the interrupts for RX/TX completion (and errors) */ + switch(queIdx) { + case GMAC_QUE_0: + /* YBP: Que 0 should be configured last so as to enable transmit and + Receive in the NCR register */ + + /* Enable Rx and Tx, plus the status register. */ + GMAC_TransmitEnable(pHw, 1); + GMAC_ReceiveEnable(pHw, 1); + GMAC_StatisticsWriteEnable(pHw, 1); + + GMAC_EnableIt(pHw, + GMAC_INT_RX_BITS | + GMAC_INT_TX_BITS | + GMAC_INT_TX_ERR_BITS, GMAC_QUE_0); + break; + + case GMAC_QUE_1: + GMAC_EnableIt(pHw, + GMAC_INT_RX_BITS | + GMAC_INT_TX_BITS | + GMAC_INT_TX_ERR_BITS, GMAC_QUE_1); + break; + case GMAC_QUE_2: + GMAC_EnableIt(pHw, + GMAC_INT_RX_BITS | + GMAC_INT_TX_BITS | + GMAC_INT_TX_ERR_BITS, GMAC_QUE_2); + break; + }; + return GMACD_OK; +} + + +/** + * Reset TX & RX queue & statistics + * \param pGmacd Pointer to GMAC Driver instance. + */ +void GMACD_Reset(sGmacd *pGmacd) +{ + Gmac *pHw = pGmacd->pHw; + + GMACD_ResetRx(pGmacd, GMAC_QUE_0); + GMACD_ResetRx(pGmacd, GMAC_QUE_1); + GMACD_ResetRx(pGmacd, GMAC_QUE_2); + + GMACD_ResetTx(pGmacd, GMAC_QUE_0); + GMACD_ResetTx(pGmacd, GMAC_QUE_1); + GMACD_ResetTx(pGmacd, GMAC_QUE_2); + + //memset((void*)&GmacStatistics, 0x00, sizeof(GmacStats)); + GMAC_NetworkControl(pHw, GMAC_NCR_TXEN | GMAC_NCR_RXEN + | GMAC_NCR_WESTAT | GMAC_NCR_CLRSTAT); +} + +/** + * \brief Send a frame split into buffers. If the frame size is larger than + * transfer buffer size error returned. If frame transfer status is monitored, + * specify callback for each frame. + * \param pGmacd Pointer to GMAC Driver instance. + * \param sgl Pointer to a scatter-gather list describing the buffers of the + * ethernet frame. + * \param fTxCb Pointer to callback function. + */ +uint8_t GMACD_SendSG(sGmacd *pGmacd, + const sGmacSGList *sgl, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx) +{ + Gmac *pHw = pGmacd->pHw; + sGmacTxDescriptor *pTd = pGmacd->queueList[queIdx].pTxD; + sGmacTxDescriptor *pTxTd; + uint16_t wTxPos, wTxHead; + int i; + + TRACE_DEBUG("%s\n\r", __FUNCTION__); + + /* Check parameter */ + if (!sgl->len) { + TRACE_ERROR("%s:: ethernet frame is empty.\r\n", __FUNCTION__); + return GMACD_PARAM; + } + if (sgl->len >= pGmacd->queueList[queIdx].wTxListSize) { + TRACE_ERROR("%s: ethernet frame has too many buffers.\r\n", __FUNCTION__); + return GMACD_PARAM; + } + /* Check available space */ + if (GCIRC_SPACE(pGmacd->queueList[queIdx].wTxHead, + pGmacd->queueList[queIdx].wTxTail, + pGmacd->queueList[queIdx].wTxListSize) < (int)sgl->len) + return GMACD_TX_BUSY; + + /* Tag end of TX queue */ + wTxHead = fixed_mod(pGmacd->queueList[queIdx].wTxHead + sgl->len, + pGmacd->queueList[queIdx].wTxListSize); + wTxPos = wTxHead; + pGmacd->queueList[queIdx].fTxCbList[wTxPos] = NULL; + pTxTd = &pTd[wTxPos]; + pTxTd->status.val = GMAC_TX_USED_BIT; + /* Update buffer descriptors in reverse order to avoid a race + * condition with hardware. + */ + for (i = (int)(sgl->len-1); i >= 0; --i) { + const sGmacSG *sg = &sgl->sg[i]; + uint32_t status; + + if (sg->size > pGmacd->queueList[queIdx].wTxBufferSize) { + TRACE_ERROR("%s: buffer size is too big.\r\n", __FUNCTION__); + return GMACD_PARAM; + } + + if (wTxPos == 0) + wTxPos = pGmacd->queueList[queIdx].wTxListSize-1; + else + wTxPos--; + + /* Reset TX callback */ + pGmacd->queueList[queIdx].fTxCbList[wTxPos] = NULL; + + pTxTd = &pTd[wTxPos]; +#ifdef GMAC_ZERO_COPY + /** Update buffer descriptor address word: + * MUST be done before status word to avoid a race condition. + */ + pTxTd->addr = (uint32_t)sg->pBuffer; + +#else + /* Copy data into transmission buffer */ + if (sg->pBuffer && sg->size){ + memcpy((void *)pTxTd->addr, sg->pBuffer, sg->size); + } +#endif + GMAC_CACHE_COHERENCE + + /* Compute buffer descriptor status word */ + status = sg->size & GMAC_LENGTH_FRAME; + if (i == (int)(sgl->len-1)) { + status |= GMAC_TX_LAST_BUFFER_BIT; + pGmacd->queueList[queIdx].fTxCbList[wTxPos] = fTxCb; + } + if (wTxPos == pGmacd->queueList[queIdx].wTxListSize-1) + status |= GMAC_TX_WRAP_BIT; + + /* Update buffer descriptor status word: clear USED bit */ + pTxTd->status.val = status; + + /* Make newly initialized descriptor visible to hardware */ + GMAC_CACHE_COHERENCE + } + + /* Update TX ring buffer pointers */ + pGmacd->queueList[queIdx].wTxHead = wTxHead; + /* Now start to transmit if it is not already done */ + + GMAC_TransmissionStart(pHw); + return GMACD_OK; +} + +/** + * \brief Send a packet with GMAC. If the packet size is larger than transfer + * buffer size error returned. If packet transfer status is monitored, specify + * callback for each packet. + * \param pGmacd Pointer to GMAC Driver instance. + * \param pBuffer The buffer to be send + * \param size The size of buffer to be send + * \param fTxCb Threshold Wakeup callback + * \return OK, Busy or invalid packet + */ +uint8_t GMACD_Send(sGmacd *pGmacd, + void *pBuffer, + uint32_t size, + fGmacdTransferCallback fTxCb, + gmacQueList_t queIdx) +{ + sGmacSGList sgl; + sGmacSG sg; + + uint8_t *msgPtr; + ptpMsgType ptpMsg; + /* Init single entry scatter-gather list */ + sg.size = size; + sg.pBuffer = pBuffer; + sgl.len = 1; + sgl.sg = &sg; + + + +#ifndef PTP_1588_TX_DISABLE + + msgPtr = (uint8_t *)pBuffer; + if(0x88u == msgPtr[12] && 0xf7u == msgPtr[13]) { + /* Extract Tx PTP message type */ + ptpMsg = (ptpMsgType)(msgPtr[14] & 0x0F); + if (ptpMsg == SYNC_MSG_TYPE || ptpMsg == PDELAY_REQ_TYPE + || ptpMsg == PDELAY_RESP_TYPE) { + /* Only add message to Tx queue of msg types that have + tx event ISRs enabled. */ + gPtpMsgTxQue[ptpTxQueWriteIdx] = ptpMsg; + + /* Copy the Sequence Id */ + gPtpMsgTxSeqId[ptpTxQueWriteIdx] = + (uint16_t)(((uint16_t)msgPtr[44] << 8) | msgPtr[45]); + ptpTxQueWriteIdx++; + ptpTxQueWriteIdx &= (EFRS_BUFFER_LEN-1u); + } else { + /* if (ptpMsg == SYNC_MSG_TYPE || ptpMsg == PDELAY_REQ_TYPE\ + || ptpMsg == PDELAY_RESP_TYPE) { */ + } + } else { /* if(0x88 == msgPtr[12] && 0xf7 == msgPtr[13]) { */ + } +#endif /* #ifndef PTP_1588_TX_DISABLE */ + return GMACD_SendSG(pGmacd, &sgl, fTxCb, queIdx); +} + +/** + * Return current load of TX. + * \param pGmacd Pointer to GMAC Driver instance. + */ +uint32_t GMACD_TxLoad(sGmacd *pGmacd, gmacQueList_t queIdx) +{ + uint16_t head = pGmacd->queueList[queIdx].wTxHead; + uint16_t tail = pGmacd->queueList[queIdx].wTxTail; + return GCIRC_CNT(head, tail, pGmacd->queueList[queIdx].wTxListSize); +} + +/** + * \brief Receive a packet with GMAC. + * If not enough buffer for the packet, the remaining data is lost but right + * frame length is returned. + * \param pGmacd Pointer to GMAC Driver instance. + * \param pFrame Buffer to store the frame + * \param frameSize Size of the frame + * \param pRcvSize Received size + * \return OK, no data, or frame too small + */ +uint8_t GMACD_Poll(sGmacd * pGmacd, + uint8_t *pFrame, + uint32_t frameSize, + uint32_t *pRcvSize, + gmacQueList_t queIdx) +{ + + uint16_t bufferLength; + uint32_t tmpFrameSize = 0; + uint8_t *pTmpFrame = 0; + uint32_t tmpIdx = pGmacd->queueList[queIdx].wRxI; + volatile sGmacRxDescriptor *pRxTd = + &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; + + uint8_t isFrame = 0; + + if (pFrame == NULL) return GMACD_PARAM; + + /* Set the default return value */ + *pRcvSize = 0; + + /* Process received RxTd */ + while ((pRxTd->addr.val & GMAC_RX_OWNERSHIP_BIT) == GMAC_RX_OWNERSHIP_BIT) { + /* A start of frame has been received, discard previous fragments */ + if ((pRxTd->status.val & GMAC_RX_SOF_BIT) == GMAC_RX_SOF_BIT) { + /* Skip previous fragment */ + while (tmpIdx != pGmacd->queueList[queIdx].wRxI) { + pRxTd = + &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + GCIRC_INC(pGmacd->queueList[queIdx].wRxI, + pGmacd->queueList[queIdx].wRxListSize); + } + pTmpFrame = pFrame; + tmpFrameSize = 0; + /* Start to gather buffers in a frame */ + isFrame = 1; + } + /* Increment the pointer */ + GCIRC_INC(tmpIdx, pGmacd->queueList[queIdx].wRxListSize); + + /* Copy data in the frame buffer */ + if (isFrame) { + if (tmpIdx == pGmacd->queueList[queIdx].wRxI) { + TRACE_INFO("no EOF (Invalid of buffers too small)\n\r"); + do { + pRxTd = + &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + GCIRC_INC(pGmacd->queueList[queIdx].wRxI, + pGmacd->queueList[queIdx].wRxListSize); + } while(tmpIdx != pGmacd->queueList[queIdx].wRxI); + return GMACD_RX_NULL; + } + + /* Copy the buffer into the application frame */ + bufferLength = pGmacd->queueList[queIdx].wRxBufferSize; + if ((tmpFrameSize + bufferLength) > frameSize) { + bufferLength = frameSize - tmpFrameSize; + } + memcpy(pTmpFrame, (void*)(pRxTd->addr.val & GMAC_ADDRESS_MASK), + bufferLength); + pTmpFrame += bufferLength; + tmpFrameSize += bufferLength; + + /* An end of frame has been received, return the data */ + if ((pRxTd->status.val & GMAC_RX_EOF_BIT) == GMAC_RX_EOF_BIT) + { + /* Frame size from the GMAC */ + *pRcvSize = (pRxTd->status.val & GMAC_LENGTH_FRAME); + + /* Application frame buffer is too small all data have not been + copied */ + if (tmpFrameSize < *pRcvSize) { + return GMACD_SIZE_TOO_SMALL; + } + TRACE_DEBUG("packet %d-%d (%d)\n\r", + pGmacd->queueList[queIdx].wRxI, tmpIdx, *pRcvSize); + /* All data have been copied in the application frame buffer + => release TD */ + while (pGmacd->queueList[queIdx].wRxI != tmpIdx) { + pRxTd = + &pGmacd->queueList[queIdx].pRxD[pGmacd->queueList[queIdx].wRxI]; + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + GCIRC_INC(pGmacd->queueList[queIdx].wRxI, + pGmacd->queueList[queIdx].wRxListSize); + } + + GMAC_CACHE_COHERENCE + return GMACD_OK; + } + } else { + /* SOF has not been detected, skip the fragment */ + pRxTd->addr.val &= ~(GMAC_RX_OWNERSHIP_BIT); + pGmacd->queueList[queIdx].wRxI = tmpIdx; + GMAC_CACHE_COHERENCE + } + /* Process the next buffer */ + pRxTd = &pGmacd->queueList[queIdx].pRxD[tmpIdx]; + GMAC_CACHE_COHERENCE + } + return GMACD_RX_NULL; +} + +/** + * \brief Registers pRxCb callback. Callback will be invoked after the next + * received frame. When GMAC_Poll() returns GMAC_RX_NO_DATA the application task + * call GMAC_Set_RxCb() to register pRxCb() callback and enters suspend state. + * The callback is in charge to resume the task once a new frame has been + * received. The next time GMAC_Poll() is called, it will be successful. + * \param pGmacd Pointer to GMAC Driver instance. + * \param fRxCb Pointer to callback function + * \return OK, no data, or frame too small + */ + +void GMACD_SetRxCallback(sGmacd * pGmacd, fGmacdTransferCallback fRxCb, + gmacQueList_t queIdx) +{ + Gmac *pHw = pGmacd->pHw; + if (fRxCb == NULL) { + GMAC_DisableIt(pHw, GMAC_IDR_RCOMP, queIdx); + pGmacd->queueList[queIdx].fRxCb = NULL; + } else { + pGmacd->queueList[queIdx].fRxCb = fRxCb; + GMAC_EnableIt(pHw, GMAC_IER_RCOMP, queIdx); + } +} + +/** + * Register/Clear TX wakeup callback. + * + * When GMACD_Send() returns GMACD_TX_BUSY (all TD busy) the application + * task calls GMACD_SetTxWakeupCallback() to register fWakeup() callback and + * enters suspend state. The callback is in charge to resume the task once + * several TD have been released. The next time GMACD_Send() will be called, + * it shall be successful. + * + * This function is usually invoked with NULL callback from the TX wakeup + * callback itself, to unregister. Once the callback has resumed the + * application task, there is no need to invoke the callback again. + * + * \param pGmacd Pointer to GMAC Driver instance. + * \param fWakeup Wakeup callback. + * \param bThreshold Number of free TD before wakeup callback invoked. + * \return GMACD_OK, GMACD_PARAM on parameter error. + */ +uint8_t GMACD_SetTxWakeupCallback(sGmacd * pGmacd, + fGmacdWakeupCallback fWakeup, + uint8_t bThreshold, + gmacQueList_t queIdx) +{ + if (fWakeup == NULL) { + pGmacd->queueList[queIdx].fWakupCb = NULL; + } else { + if (bThreshold <= pGmacd->queueList[queIdx].wTxListSize) { + pGmacd->queueList[queIdx].fWakupCb = fWakeup; + pGmacd->queueList[queIdx].bWakeupThreshold = bThreshold; + } else { + return GMACD_PARAM; + } + } + return GMACD_OK; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/hsmci.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/hsmci.c new file mode 100644 index 000000000..8360bf633 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/hsmci.c @@ -0,0 +1,565 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * + * Implementation of High Speed MultiMedia Card Interface (HSMCI) controller. + */ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" +#include + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** \addtogroup hsmci_functions + *@{ + */ + +/** + * \brief Enable Multi-Media Interface + * + * \param pRMci Pointer to a Hsmci instance + */ +extern void HSMCI_Enable(Hsmci* pRMci) +{ + pRMci->HSMCI_CR = HSMCI_CR_MCIEN; +} + +/** + * \brief Disable Multi-Media Interface + * + * \param pRMci Pointer to a Hsmci instance + */ +extern void HSMCI_Disable(Hsmci* pRMci) +{ + pRMci->HSMCI_CR = HSMCI_CR_MCIDIS; + +} + +/** + * \brief Reset (& Disable) Multi-Media Interface + * + * \param mci Pointer to a Hsmci instance + * \param bBackup Backup registers values to keep previous settings, including + * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. + */ +extern void HSMCI_Reset(Hsmci* pRMci, uint8_t bBackup) +{ + if (bBackup) { + uint32_t mr = pRMci->HSMCI_MR; + uint32_t dtor = pRMci->HSMCI_DTOR; + uint32_t sdcr = pRMci->HSMCI_SDCR; + uint32_t cstor = pRMci->HSMCI_CSTOR; + uint32_t dma = pRMci->HSMCI_DMA; + uint32_t cfg = pRMci->HSMCI_CFG; + + pRMci->HSMCI_CR = HSMCI_CR_SWRST; + + pRMci->HSMCI_MR = mr; + pRMci->HSMCI_DTOR = dtor; + pRMci->HSMCI_SDCR = sdcr; + pRMci->HSMCI_CSTOR = cstor; + pRMci->HSMCI_DMA = dma; + pRMci->HSMCI_CFG = cfg; + } else { + pRMci->HSMCI_CR = HSMCI_CR_SWRST; + } +} + +/** + * \brief Select slot + * \param pRMci Pointer to a Hsmci instance + * \param bSlot Slot ID (0~3 for A~D). + */ +extern void HSMCI_Select(Hsmci *pRMci, uint8_t bSlot, uint8_t bBusWidth) +{ + uint32_t dwSdcr; + dwSdcr = (HSMCI_SDCR_SDCSEL_Msk & bSlot); + switch(bBusWidth) { + case 1: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1; + break; + case 4: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4; + break; + case 8: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8; + break; + } +} + +/** + * \brief Set slot + * \param pRMci Pointer to a Hsmci instance + * \param bSlot Slot ID (0~3 for A~D). + */ +extern void HSMCI_SetSlot(Hsmci *pRMci, uint8_t bSlot) +{ + uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCSEL_Msk; + pRMci->HSMCI_SDCR = dwSdcr | (HSMCI_SDCR_SDCSEL_Msk & bSlot); +} + +/** + * \brief Set bus width of MCI + * \param pRMci Pointer to a Hsmci instance + * \param bBusWidth 1,4 or 8 (bits). + */ +extern void HSMCI_SetBusWidth(Hsmci * pRMci,uint8_t bBusWidth) +{ + uint32_t dwSdcr = pRMci->HSMCI_SDCR & ~HSMCI_SDCR_SDCBUS_Msk; + switch(bBusWidth) { + case 1: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_1; + break; + case 4: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_4; + break; + case 8: + pRMci->HSMCI_SDCR = dwSdcr | HSMCI_SDCR_SDCBUS_8; + break; + } +} + +/** + * \brief Return bus width setting. + * + * \param pRMci Pointer to an MCI instance. + * \return 1, 4 or 8. + */ +extern uint8_t HSMCI_GetBusWidth(Hsmci * pRMci) +{ + switch(pRMci->HSMCI_SDCR & HSMCI_SDCR_SDCBUS_Msk) { + case HSMCI_SDCR_SDCBUS_1: return 1; + case HSMCI_SDCR_SDCBUS_4: return 4; + case HSMCI_SDCR_SDCBUS_8: return 8; + } + return 0; +} + +/** + * \brief Configures a MCI peripheral as specified. + * + * \param pRMci Pointer to an MCI instance. + * \param dwMode Value of the MCI Mode register. + */ +extern void HSMCI_ConfigureMode(Hsmci *pRMci, uint32_t dwMode) +{ + pRMci->HSMCI_MR = dwMode; + +} + +/** + * \brief Return mode register + * \param pRMci Pointer to an MCI instance. + */ +extern uint32_t HSMCI_GetMode(Hsmci * pRMci) +{ + return pRMci->HSMCI_MR; +} + +/** + * \brief Enable/Disable R/W proof + * + * \param pRMci Pointer to an MCI instance. + * \param bRdProof Read proof enable/disable. + * \param bWrProof Write proof enable/disable. + */ +extern void HSMCI_ProofEnable(Hsmci *pRMci, uint8_t bRdProof, uint8_t bWrProof) +{ + uint32_t mr = pRMci->HSMCI_MR; + pRMci->HSMCI_MR = (mr & (~(HSMCI_MR_WRPROOF | HSMCI_MR_RDPROOF))) + | (bRdProof ? HSMCI_MR_RDPROOF : 0) + | (bWrProof ? HSMCI_MR_WRPROOF : 0) + ; +} + +/** + * \brief Padding value setting. + * + * \param pRMci Pointer to an MCI instance. + * \param bPadvEn Padding value 0xFF/0x00. + */ +extern void HSMCI_PadvCtl(Hsmci *pRMci, uint8_t bPadv) +{ + if (bPadv) { + pRMci->HSMCI_MR |= HSMCI_MR_PADV; + } else { + pRMci->HSMCI_MR &= ~HSMCI_MR_PADV; + } +} + +/** + * \brief Force byte transfer enable/disable. + * + * \param pRMci Pointer to an MCI instance. + * \param bFByteEn FBYTE enable/disable. + */ +extern void HSMCI_FByteEnable(Hsmci *pRMci, uint8_t bFByteEn) +{ + if (bFByteEn) { + pRMci->HSMCI_MR |= HSMCI_MR_FBYTE; + } else { + pRMci->HSMCI_MR &= ~HSMCI_MR_FBYTE; + } +} + +/** + * \brief Check if Force Byte mode enabled. + * + * \param pRMci Pointer to an MCI instance. + * \return 1 if _FBYTE is enabled. + */ +extern uint8_t HSMCI_IsFByteEnabled(Hsmci *pRMci) +{ + return ((pRMci->HSMCI_MR & HSMCI_MR_FBYTE) > 0); +} + +/** + * \brief Set Clock Divider & Power save divider for MCI. + * + * \param pRMci Pointer to an MCI instance. + * \param bClkDiv Clock Divider value (0 ~ 255). + * \param bPwsDiv Power Saving Divider (1 ~ 7). + */ +extern void HSMCI_DivCtrl(Hsmci *pRMci, uint32_t bClkDiv, uint8_t bPwsDiv) +{ + uint32_t mr = pRMci->HSMCI_MR; + uint32_t clkdiv ,clkodd; + clkdiv = bClkDiv - 2 ; + clkodd = (bClkDiv & 1)? HSMCI_MR_CLKODD: 0; + clkdiv = clkdiv >> 1; + + pRMci->HSMCI_MR = (mr & ~(HSMCI_MR_CLKDIV_Msk | HSMCI_MR_PWSDIV_Msk)) + | HSMCI_MR_CLKDIV(clkdiv) + | HSMCI_MR_PWSDIV(bPwsDiv) + | clkodd + ; +} + +/** + * \brief Enables one or more interrupt sources of MCI peripheral. + * + * \param pRMci Pointer to an Hsmci instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void HSMCI_EnableIt(Hsmci *pRMci, uint32_t dwSources) +{ + pRMci->HSMCI_IER = dwSources; +} + +/** + * \brief Disable one or more interrupt sources of MCI peripheral. + * + * \param pRMci Pointer to an Hsmci instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void HSMCI_DisableIt(Hsmci *pRMci, uint32_t dwSources) +{ + pRMci->HSMCI_IDR = dwSources; +} + +/** + * \brief Return the interrupt mask register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI interrupt mask register. + */ +extern uint32_t HSMCI_GetItMask(Hsmci *pRMci) +{ + return (pRMci->HSMCI_IMR) ; +} + +/** + * \brief Set block len & count for transfer + * + * \param pRMci Pointer to an Hsmci instance. + * \param wBlkLen Block size. + * \param wCnt Block(byte) count. + */ +extern void HSMCI_ConfigureTransfer(Hsmci *pRMci, + uint16_t wBlkLen, + uint16_t wCnt) +{ + pRMci->HSMCI_BLKR = (wBlkLen << 16) | wCnt; +} + +/** + * \brief Set block length + * + * Count is reset to 0. + * + * \param pRMci Pointer to an Hsmci instance. + * \param wBlkSize Block size. + */ +extern void HSMCI_SetBlockLen(Hsmci *pRMci, uint16_t wBlkSize) +{ + pRMci->HSMCI_BLKR = wBlkSize << 16; +} + +/** + * \brief Set block (byte) count + * + * \param pRMci Pointer to an Hsmci instance. + * \param wBlkCnt Block(byte) count. + */ +extern void HSMCI_SetBlockCount(Hsmci *pRMci, uint16_t wBlkCnt) +{ + pRMci->HSMCI_BLKR |= wBlkCnt; +} + +/** + * \brief Configure the Completion Signal Timeout + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Completion Signal Timeout configure. + */ +extern void HSMCI_ConfigureCompletionTO(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_CSTOR = dwConfigure; +} + +/** + * \brief Configure the Data Timeout + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Data Timeout configure. + */ +extern void HSMCI_ConfigureDataTO(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_DTOR = dwConfigure; +} + +/** + * \brief Send command + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwCmd Command register value. + * \param dwArg Argument register value. + */ +extern void HSMCI_SendCmd(Hsmci *pRMci, uint32_t dwCmd, uint32_t dwArg) +{ + pRMci->HSMCI_ARGR = dwArg; + pRMci->HSMCI_CMDR = dwCmd; +} + + +/** + * \brief Return the response register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI response register. + */ +extern uint32_t HSMCI_GetResponse(Hsmci *pRMci) +{ + return pRMci->HSMCI_RSPR[0]; +} + +/** + * \brief Return the receive data register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI receive data register. + */ +extern uint32_t HSMCI_Read(Hsmci *pRMci) +{ + return pRMci->HSMCI_RDR; +} + +/** + * \brief Read from FIFO + * + * \param pRMci Pointer to an Hsmci instance. + * \param pdwData Pointer to data buffer. + * \param dwSize Size of data buffer (in DWord). + */ +extern void HSMCI_ReadFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize) +{ + volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO); + register uint32_t c4, c1; + + if (dwSize == 0) + return; + + c4 = dwSize >> 2; + c1 = dwSize & 0x3; + + for(;c4;c4 --) { + *pdwData ++ = *pFIFO ++; + *pdwData ++ = *pFIFO ++; + *pdwData ++ = *pFIFO ++; + *pdwData ++ = *pFIFO ++; + } + for(;c1;c1 --) { + *pdwData ++ = *pFIFO ++; + } +} + +/** + * \brief Sends data through MCI peripheral. + * + * \param pRMci Pointer to an Hsmci instance. + * \param + */ +extern void HSMCI_Write(Hsmci *pRMci, uint32_t dwData) +{ + pRMci->HSMCI_TDR = dwData; +} + +/** + * \brief Write to FIFO + * + * \param pRMci Pointer to an Hsmci instance. + * \param pdwData Pointer to data buffer. + * \param dwSize Size of data buffer (In DWord). + */ +extern void HSMCI_WriteFifo(Hsmci *pRMci, uint8_t *pdwData, uint32_t dwSize) +{ + volatile uint32_t *pFIFO = (volatile uint32_t*)(pRMci->HSMCI_FIFO); + register uint32_t c4, c1; + + if (dwSize == 0) + return; + + c4 = dwSize >> 2; + c1 = dwSize & 0x3; + + for(;c4;c4 --) { + *pFIFO ++ = *pdwData ++; + *pFIFO ++ = *pdwData ++; + *pFIFO ++ = *pdwData ++; + *pFIFO ++ = *pdwData ++; + } + for(;c1;c1 --) { + *pFIFO ++ = *pdwData ++; + } +} + +/** + * \brief Return the status register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI status register. + */ +extern uint32_t HSMCI_GetStatus(Hsmci *pRMci) +{ + return pRMci->HSMCI_SR; +} + +/** + * \brief Configure the HSMCI DMA + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Configure value. + */ +extern void HSMCI_ConfigureDma(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_DMA = dwConfigure; +} + +/** + * \brief Enable the HSMCI DMA + * + * \param pRMci Pointer to an Hsmci instance. + * \param bEnable 1 to enable, 0 to disable. + */ +extern void HSMCI_EnableDma(Hsmci *pRMci, uint8_t bEnable) +{ + if (bEnable) { + pRMci->HSMCI_DMA |= HSMCI_DMA_DMAEN ;//| HSMCI_DMA_CHKSIZE_32; + } else { + pRMci->HSMCI_DMA &= ~HSMCI_DMA_DMAEN; + } +} + +/** + * \brief Configure the HSMCI + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure Configure value. + */ +extern void HSMCI_Configure(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_CFG = dwConfigure; +} + +/** + * \brief Enable/Disable High-Speed mode for MCI + * + * \param pRMci Pointer to an Hsmci instance. + * \param bHsEnable Enable/Disable high-speed. + */ +extern void HSMCI_HsEnable(Hsmci *pRMci, uint8_t bHsEnable) +{ + if (bHsEnable) { + pRMci->HSMCI_CFG |= HSMCI_CFG_HSMODE; + } else { + pRMci->HSMCI_CFG &= ~HSMCI_CFG_HSMODE; + } +} + +/** + * \brief Check if High-speed mode is enabled on MCI + * \param pRMci Pointer to an Hsmci instance. + * \return 1 + */ +extern uint8_t HSMCI_IsHsEnabled(Hsmci * pRMci) +{ + return ((pRMci->HSMCI_CFG & HSMCI_CFG_HSMODE) > 0); +} + +/** + * \brief Configure the Write Protection Mode + * + * \param pRMci Pointer to an Hsmci instance. + * \param dwConfigure WP mode configure value. + */ +extern void HSMCI_ConfigureWP(Hsmci *pRMci, uint32_t dwConfigure) +{ + pRMci->HSMCI_WPMR = dwConfigure; +} + +/** + * \brief Return the write protect status register. + * + * \param pRMci Pointer to an Hsmci instance. + * \return MCI write protect status register. + */ +extern uint32_t HSMCI_GetWPStatus(Hsmci *pRMci) +{ + return pRMci->HSMCI_WPSR; +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/icm.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/icm.c new file mode 100644 index 000000000..370f2d424 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/icm.c @@ -0,0 +1,225 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT ICMLL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup icm_module Working with ICM + * The TWI driver provides the interface to True Random Number Generator (ICM) passes the American NIST Special Publication 800-22 and Diehard + Random Tests Suites. + The ICM may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by + FIPS PUB 140-2 and 140-3. use the TWI + * peripheral. + * + * \section Usage + *
      + *
    • Configures a TWI peripheral to operate in master mode, at the given + * frequency (in Hz) using TWI_Configure().
      • + *
    • Sends a STOP condition on the TWI using TWI_Stop().
      • + *
    • Starts a read operation on the TWI bus with the specified slave using + * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever + * a byte is available (poll using TWI_ByteReceived()).
      • + *
    • Starts a write operation on the TWI to access the selected slave using + * TWI_StartWrite(). A byte of data must be provided to start the write; + * other bytes are written next.
      • + *
    • Sends a byte of data to one of the TWI slaves on the bus using TWI_WriteByte(). + * This function must be called once before TWI_StartWrite() with the first byte of data + * to send, then it ICMll be called repeatedly after that to send the remaining bytes.
      • + *
    • Check if a byte has been received and can be read on the given TWI + * peripheral using TWI_ByteReceived().< + * Check if a byte has been sent using TWI_ByteSent().
      • + *
    • Check if the current transmission is complete (the STOP has been sent) + * using TWI_TransferComplete().
      • + *
    • Enables & disable the selected interrupts sources on a TWI peripheral + * using TWI_EnableIt() and TWI_DisableIt().
      • + *
    • Get current status register of the given TWI peripheral using + * TWI_GetStatus(). Get current status register of the given TWI peripheral, but + * masking interrupt sources which are not currently enabled using + * TWI_GetMaskedStatus().
      • + *
    + * For more accurate information, please look at the TWI section of the + * Datasheet. + * + * Related files :\n + * \ref twi.c\n + * \ref twi.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of True Random Number Generator (ICM) + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enable ICM, the ICM controller is activated + */ +void ICM_Enable(void) +{ + ICM->ICM_CTRL = ICM_CTRL_ENABLE; +} + +/** + * \brief Disable ICM, if a region is active, this region is terminated + */ +void ICM_Disable(void) +{ + ICM->ICM_CTRL = ICM_CTRL_DISABLE; +} + +/** + * \brief Resets the ICM controller. + */ +void ICM_SoftReset(void) +{ + ICM->ICM_CTRL = ICM_CTRL_SWRST; +} + +/** + * \brief Recompute Internal hash. + * \param region, When REHASH[region] is set to one, the region digest is re-computed. + * \note This bit is only available when Region monitoring is disabled. + */ +void ICM_ReComputeHash(uint8_t region) +{ + ICM->ICM_CTRL = ICM_CTRL_REHASH(region); +} + +/** + * \brief Enable region monitoring for given region + * \param region, When bit RMEN[region] is set to one, the monitoring of Region is activated. + */ +void ICM_EnableMonitor(uint8_t region) +{ + ICM->ICM_CTRL = ICM_CTRL_RMEN(region); +} + +/** + * \brief Disable region monitoring for given region + * \param region, When bit RMDIS[region] is set to one, the monitoring of Region is disabled. + */ +void ICM_DisableMonitor(uint8_t region) +{ + ICM->ICM_CTRL = ICM_CTRL_RMDIS(region); +} + +/** + * \brief Configures an ICM peripheral with the specified parameters. + * \param mode Desired value for the ICM mode register (see the datasheet). + */ +void ICM_Configure(uint32_t mode) +{ + ICM->ICM_CFG = mode; +} + +/** + * \brief Enables the selected interrupts sources on a ICM peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void ICM_EnableIt(uint32_t sources) +{ + ICM->ICM_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a ICM peripheral. + * \param sources Bitwise OR of selected interrupt sources. + */ +void ICM_DisableIt(uint32_t sources) +{ + ICM->ICM_IDR = sources; +} + +/** + * \brief Get the current interrupt status register of the given ICM peripheral. + * \return ICM status register. + */ +uint32_t ICM_GetIntStatus(void) +{ + return ICM->ICM_ISR; +} + +/** + * \brief Get the current status register of the given ICM peripheral. + * \return ICM status register. + */ +uint32_t ICM_GetStatus(void) +{ + return ICM->ICM_SR; +} + + +/** + * \brief Get the undefined access status register of the given ICM peripheral. + * \return ICM status register. + */ +uint32_t ICM_GetUStatus(void) +{ + return ICM->ICM_UASR; +} + +/** + * \brief Set descriptor area start address register. + * \param addr start address + * \note The start address is a multiple of the total size of the data structure (64 bytes). + */ +void ICM_SetDescStartAddress(uint32_t addr) +{ + ICM->ICM_DSCR = addr; +} + +/** + * \brief Set hash area start address register. + * \param addr start address + * \note This field points at the Hash memory location. The address must be a multiple of 128 bytes. + */ +void ICM_SetHashStartAddress(uint32_t addr) +{ + ICM->ICM_HASH = addr; +} + +/** + * \brief Set ICM user initial Hash value register. + * \param val Initial Hash Value + */ +void ICM_SetInitHashValue(uint32_t val) +{ + ICM->ICM_UIHVAL[0] = ICM_UIHVAL_VAL(val); +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/isi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/isi.c new file mode 100644 index 000000000..67d307011 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/isi.c @@ -0,0 +1,368 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Workaround for ISI CFG2 register read. + * \note The ISI_CFG2[31:27] can be written correctly, because the input writing + * data are assigned directly to the internal control bits as specified, + * the mismatch only happens in reading operation. + * [31:28] are shift right 1 bit, so [31:27] can be read from [30:27]. + */ +__STATIC_INLINE uint32_t _ISI_GetCFG2_Workaround(void) +{ + uint32_t wrongfield; + wrongfield = ISI->ISI_CFG2 >> (ISI_CFG2_YCC_SWAP_Pos - 1); + return (ISI->ISI_CFG2 & 0x07FFFFFF) | (wrongfield << ISI_CFG2_YCC_SWAP_Pos); +} + +/*---------------------------------------------------------------------------- + * Export functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enable ISI + */ +void ISI_Enable(void) +{ + ISI->ISI_CR |= ISI_CR_ISI_EN; + while( (ISI->ISI_SR & ISI_CR_ISI_EN)!=ISI_CR_ISI_EN); +} + +/** + * \brief Enable ISI Dma channel + * \param channel to be enabled + */ +void ISI_DmaChannelEnable(uint32_t channel) +{ + ISI->ISI_DMA_CHER |= channel; +} + +/** + * \brief Disable ISI Dma channel + * \param channel to be disabled + */ +void ISI_DmaChannelDisable(uint32_t channel) +{ + ISI->ISI_DMA_CHDR |=channel; +} + +/** + * \brief Disable ISI + */ +void ISI_Disable(void) +{ + /* Write one to this field to disable the module */ + ISI->ISI_CR |= ISI_CR_ISI_DIS; + /* Software must poll DIS_DONE field in the ISI_STATUS register to verify that the command + has successfully completed.*/ + while( (ISI->ISI_SR & ISI_SR_DIS_DONE) != ISI_SR_DIS_DONE); +} + + +/** + * \brief Enable ISI interrupt + * \param flag of interrupt to enable + */ +void ISI_EnableInterrupt(uint32_t flag) +{ + ISI->ISI_IER = flag; +} + +/** + * \brief Disable ISI interrupt + * \param flag of interrupt to disable + */ +void ISI_DisableInterrupt(uint32_t flag) +{ + ISI->ISI_IDR = flag; +} + +/** + * \brief Return ISI status register + * \return Status of ISI register + */ +uint32_t ISI_StatusRegister(void) +{ + return(ISI->ISI_SR); +} + +/** + * \brief Enable Codec path for capture next frame + */ +void ISI_CodecPathFull(void) +{ + // The codec path is enabled and the next frame is captured. + // Both codec and preview data-paths are working simultaneously + ISI->ISI_CR |= ISI_CR_ISI_CDC; + ISI->ISI_CFG1 |= ISI_CFG1_FULL; +} + +/** + * \brief Set frame rate + * \param frame frame rate capture + */ +void ISI_SetFrameRate(uint32_t frame) +{ + if( frame > 7 ) { + TRACE_ERROR("rate too big\n\r"); + frame = 7; + } + ISI->ISI_CFG1 |= ISI_CFG1_FRATE(frame); +} + +/** + * \brief Get the number of byte per pixels + * \param bmpRgb BMP type can be YUV or RGB + */ +uint8_t ISI_BytesForOnePixel(uint8_t bmpRgb) +{ + uint8_t nbByte_Pixel; + + if (bmpRgb == RGB) { + if ((_ISI_GetCFG2_Workaround() & ISI_CFG2_RGB_MODE) == ISI_CFG2_RGB_MODE){ + // RGB: 5:6:5 16bits/pixels + nbByte_Pixel = 2; + } else { + // RGB: 8:8:8 24bits/pixels + nbByte_Pixel = 3; + } + } else { + // YUV: 2 pixels for 4 bytes + nbByte_Pixel = 2; + } + return nbByte_Pixel; +} + +/** + * \brief Reset ISI + */ +void ISI_Reset(void) +{ + uint32_t timeout=0; + + // Resets the image sensor interface. + // Finish capturing the current frame and then shut down the module. + ISI->ISI_CR = ISI_CR_ISI_SRST | ISI_CR_ISI_DIS; + // wait Software reset has completed successfully. + while( (!(ISI->ISI_SR & ISI_SR_SRST)) + && (timeout < 0x5000) ) { + timeout++; + } + if( timeout == 0x5000 ) { + TRACE_ERROR("ISI-Reset timeout\n\r"); + } +} + + +/** + * \brief Set the windows blank + * \param hBlank pixel clock periods to wait before the beginning of a line. + * \param vBlank lines are skipped at the beginning of the frame. + */ +void ISI_SetBlank(uint8_t hBlank, uint8_t vBlank) +{ + ISI->ISI_CFG1 |= ISI_CFG1_SLD(hBlank) + ISI_CFG1_SFD(vBlank); +} + + +/** + * \brief Set vertical and horizontal Size of the Image Sensor + * \param hSize Horizontal size of the Image sensor [0..2047]. + * \param vSize Vertical size of the Image sensor [0..2047]. + */ +void ISI_SetSensorSize(uint32_t hSize, uint32_t vSize) +{ + // IM_VSIZE: Vertical size of the Image sensor [0..2047] + // Vertical size = IM_VSIZE + 1 + // IM_HSIZE: Horizontal size of the Image sensor [0..2047] + // Horizontal size = IM_HSIZE + 1 + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | ISI_CFG2_IM_VSIZE(vSize - 1) + | ISI_CFG2_IM_HSIZE(hSize - 1); +} + +/** + * \brief Defines RGB pattern when RGB_MODE is set to 1. + * \param wRgbPixelMapping RGB pattern + */ +void ISI_RgbPixelMapping(uint32_t wRgbPixelMapping) +{ + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() & (~ISI_CFG2_RGB_CFG_Msk); + if (wRgbPixelMapping != ISI_CFG2_RGB_CFG_DEFAULT) + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | wRgbPixelMapping + | ISI_CFG2_RGB_MODE; + else + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround(); +} + +/** + * \brief Enables RGB swap + * \param swapMode 0: D7-R7, 1: D0-R7 + */ +void ISI_RgbSwapMode(uint32_t swapMode) +{ + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() & (~ISI_CFG2_RGB_SWAP); + if(swapMode) ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | ISI_CFG2_RGB_SWAP; +} + +/** + * \brief Defines YCrCb swap format. + * \param wYuvSwapMode YUV Swap format + */ +void ISI_YCrCbFormat(uint32_t wYuvSwapMode) +{ + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() & (~ISI_CFG2_YCC_SWAP_Msk); + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | wYuvSwapMode; +} + +/** + * \brief Input image is assumed to be grayscale-coded. + * \param wPixelFormat 0: 2 pixels per word, 1:1 pixel per word. + */ +void ISI_setGrayScaleMode(uint32_t wPixelFormat) +{ + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | ISI_CFG2_GRAYSCALE ; + if(wPixelFormat) ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | ISI_CFG2_GS_MODE; + +} + +/** + * \brief Set data stream format. + * \param wStreamMode 0: YUV input, 1: RGB 8:8:8/5:6:5 input + */ +void ISI_setInputStream(uint32_t wStreamMode) +{ + ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() & (~ISI_CFG2_COL_SPACE); + if(wStreamMode) ISI->ISI_CFG2 = _ISI_GetCFG2_Workaround() | ISI_CFG2_COL_SPACE; +} + +/** + * \brief Set preview size. + * \param hSize Horizontal Preview size (640 max only in RGB mode). + * \param vSize Vertical Preview size (480 max only in RGB mode). + */ +void ISI_setPreviewSize(uint32_t hSize, uint32_t vSize) +{ + if (hSize > 640) hSize = 640; + if (vSize > 480) vSize = 480; + ISI->ISI_PSIZE = ISI_PSIZE_PREV_VSIZE(vSize - 1) | ISI_PSIZE_PREV_HSIZE(hSize - 1); +} + +/** + * \brief calculate scaler factor automatically. + * \note The sensor size and preview size for LCD was configured before this setting. + */ +void ISI_calcScalerFactor(void) +{ + uint32_t hLcdSize, hSensorSize; + uint32_t hRatio; + hLcdSize = ((ISI->ISI_PSIZE & ISI_PSIZE_PREV_HSIZE_Msk) >> ISI_PSIZE_PREV_HSIZE_Pos) +1 ; + hSensorSize = ((_ISI_GetCFG2_Workaround() & ISI_CFG2_IM_HSIZE_Msk ) + >> ISI_CFG2_IM_HSIZE_Pos) + 1; + hRatio = 1600 * hSensorSize / hLcdSize; + ISI->ISI_PDECF = (hRatio/100); +} + +/** + * \brief Configure DMA for preview path. + * \param baseFrameBufDesc Preview Descriptor Address. + * \param dmaCtrl DMA Preview Control. + * \param frameBufferStartAddr DMA Preview Base Address. + */ +void ISI_setDmaInPreviewPath(uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, uint32_t frameBufferStartAddr) +{ + ISI->ISI_DMA_P_DSCR = baseFrameBufDesc; + ISI->ISI_DMA_P_CTRL = dmaCtrl; + ISI->ISI_DMA_P_ADDR = frameBufferStartAddr; +} + +/** + * \brief Configure DMA for Codec path. + * \param baseFrameBufDesc Preview Descriptor Address. + * \param dmaCtrl DMA Preview Control. + * \param frameBufferStartAddr DMA Preview Base Address. + */ +void ISI_setDmaInCodecPath(uint32_t baseFrameBufDesc, + uint32_t dmaCtrl, uint32_t frameBufferStartAddr) +{ + ISI->ISI_DMA_C_DSCR = baseFrameBufDesc; + ISI->ISI_DMA_C_CTRL = dmaCtrl; + ISI->ISI_DMA_C_ADDR = frameBufferStartAddr; +} + +/** + * \brief ISI set matrix for YUV to RGB color space for preview path. + * \param yuv2rgb structure of YUV to RBG parameters. + */ +void ISI_SetMatrix4Yuv2Rgb (ISI_Y2R* yuv2rgb) +{ + ISI->ISI_Y2R_SET0 = ISI_Y2R_SET0_C0(yuv2rgb->C0) + | ISI_Y2R_SET0_C1(yuv2rgb->C1) + | ISI_Y2R_SET0_C2(yuv2rgb->C2) + | ISI_Y2R_SET0_C3(yuv2rgb->C3); + + ISI->ISI_Y2R_SET1 = ISI_Y2R_SET1_C4(yuv2rgb->C4) + | ((yuv2rgb->Yoff == 1)? ISI_Y2R_SET1_Yoff: 0) + | ((yuv2rgb->Croff == 1)? ISI_Y2R_SET1_Croff: 0) + | ((yuv2rgb->Cboff == 1)? ISI_Y2R_SET1_Cboff: 0); +} + +/** + * \brief ISI set matrix for RGB to YUV color space for codec path. + * \param rgb2yuv structure of RGB to YUV parameters. + */ +void ISI_SetMatrix4Rgb2Yuv (ISI_R2Y* rgb2yuv) +{ + ISI->ISI_R2Y_SET0 = ISI_R2Y_SET0_C0(rgb2yuv->C0) + | ISI_R2Y_SET0_C1(rgb2yuv->C1) + | ISI_R2Y_SET0_C2(rgb2yuv->C2) + | ((rgb2yuv->Roff == 1)? ISI_R2Y_SET0_Roff: 0); + + ISI->ISI_R2Y_SET1 = ISI_R2Y_SET1_C3(rgb2yuv->C3) + | ISI_R2Y_SET1_C4(rgb2yuv->C4) + | ISI_R2Y_SET1_C5(rgb2yuv->C5) + | ((rgb2yuv->Goff == 1)? ISI_R2Y_SET1_Goff: 0); + + ISI->ISI_R2Y_SET2 = ISI_R2Y_SET2_C6(rgb2yuv->C6) + | ISI_R2Y_SET2_C7(rgb2yuv->C7) + | ISI_R2Y_SET2_C8(rgb2yuv->C8) + | ((rgb2yuv->Boff == 1)? ISI_R2Y_SET2_Boff: 0); +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/iso7816_4.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/iso7816_4.c new file mode 100644 index 000000000..e2c981db2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/iso7816_4.c @@ -0,0 +1,587 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * \section Purpose + * + * ISO 7816 driver + * + * \section Usage + * + * Explanation on the usage of the code made available through the header file. + */ + +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" + +/*------------------------------------------------------------------------------ + * Definitions + *----------------------------------------------------------------------------*/ +/** Case for APDU commands*/ +#define CASE1 1 +#define CASE2 2 +#define CASE3 3 + +/** Flip flop for send and receive char */ +#define USART_SEND 0 +#define USART_RECEIVE 1 + +#define USART7816BAUDRATE 9600 +/*----------------------------------------------------------------------------- + * Internal variables + *---------------------------------------------------------------------------*/ +/** Variable for state of send and receive from USART */ +static uint8_t StateUsartGlobal = USART_RECEIVE; +/** Pin reset master card */ +static Pin st_pinIso7816RstMC; +static Usart *UsartIso; +static uint32_t UsartIsoId; + +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ + +/** + * Get a character from ISO7816 + * \param pCharToReceive Pointer for store the received char + * \return 0: if timeout else status of US_CSR + */ +static uint32_t ISO7816_GetChar( uint8_t *pCharToReceive ) +{ + uint32_t status; + uint32_t timeout=0; + + if( StateUsartGlobal == USART_SEND ) { + while((UsartIso->US_CSR & US_CSR_TXEMPTY) == 0) {} + UsartIso->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + StateUsartGlobal = USART_RECEIVE; + } + + /* Wait USART ready for reception */ + while( ((UsartIso->US_CSR & US_CSR_RXRDY) == 0) ) { + if(timeout++ > 12000 * (BOARD_MCK/1000000)) { + TRACE_DEBUG("TimeOut\n\r"); + return( 0 ); + } + } + + TRACE_DEBUG("T: %u\n\r", timeout); + + + /* At least one complete character has been received and US_RHR has not + yet been read. */ + + /* Get a char */ + *pCharToReceive = ((UsartIso->US_RHR) & 0xFF); + + status = (UsartIso->US_CSR&(US_CSR_OVRE | US_CSR_FRAME | + US_CSR_PARE | US_CSR_TIMEOUT | US_CSR_NACK | + (1<<10))); + + if (status != 0 ) { + /* TRACE_DEBUG("R:0x%X\n\r", status); */ + TRACE_DEBUG("R:0x%X\n\r", UsartIso->US_CSR); + TRACE_DEBUG("Nb:0x%X\n\r", UsartIso->US_NER ); + UsartIso->US_CR = US_CR_RSTSTA; + } + + /* Return status */ + return( status ); +} + +/** + * Send a char to ISO7816 + * \param CharToSend char to be send + * \return status of US_CSR + */ +static uint32_t ISO7816_SendChar( uint8_t CharToSend ) +{ + uint32_t status; + + if( StateUsartGlobal == USART_RECEIVE ) { + UsartIso->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + StateUsartGlobal = USART_SEND; + } + + /* Wait USART ready for transmit */ + while((UsartIso->US_CSR & US_CSR_TXRDY) == 0) {} + /* There is no character in the US_THR */ + + /* Transmit a char */ + UsartIso->US_THR = CharToSend; + + status = (UsartIso->US_CSR & (US_CSR_OVRE | US_CSR_FRAME | + US_CSR_PARE | US_CSR_TIMEOUT | US_CSR_NACK | + (1<<10))); + + if (status != 0 ) { + TRACE_DEBUG("E:0x%X\n\r", UsartIso->US_CSR); + TRACE_DEBUG("Nb:0x%X\n\r", UsartIso->US_NER ); + UsartIso->US_CR = US_CR_RSTSTA; + } + + /* Return status */ + return( status ); +} + + +/** + * Iso 7816 ICC power on + */ +static void ISO7816_IccPowerOn( void ) +{ + /* Set RESET Master Card */ + PIO_Set(&st_pinIso7816RstMC); +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * Iso 7816 ICC power off + */ +void ISO7816_IccPowerOff( void ) +{ + /* Clear RESET Master Card */ + PIO_Clear(&st_pinIso7816RstMC); +} + +/** + * Transfer Block TPDU T=0 + * \param pAPDU APDU buffer + * \param pMessage Message buffer + * \param wLength Block length + * \return Message index + */ +uint16_t ISO7816_XfrBlockTPDU_T0(const uint8_t *pAPDU, + uint8_t *pMessage, + uint16_t wLength ) +{ + uint16_t NeNc; + uint16_t indexApdu = 4; + uint16_t indexMessage = 0; + uint8_t SW1 = 0; + uint8_t procByte = 0; + uint8_t cmdCase; + uint8_t ins; + + TRACE_DEBUG("pAPDU[0]=0x%X\n\r",pAPDU[0]); + TRACE_DEBUG("pAPDU[1]=0x%X\n\r",pAPDU[1]); + TRACE_DEBUG("pAPDU[2]=0x%X\n\r",pAPDU[2]); + TRACE_DEBUG("pAPDU[3]=0x%X\n\r",pAPDU[3]); + TRACE_DEBUG("pAPDU[4]=0x%X\n\r",pAPDU[4]); + TRACE_DEBUG("wlength=%d\n\r",wLength); + + ISO7816_SendChar( pAPDU[0] ); /* CLA */ + ISO7816_SendChar( pAPDU[1] ); /* INS */ + ISO7816_SendChar( pAPDU[2] ); /* P1 */ + ISO7816_SendChar( pAPDU[3] ); /* P2 */ + ISO7816_SendChar( pAPDU[4] ); /* P3 */ + + /* Handle the four structures of command APDU */ + indexApdu = 4; + + if( wLength == 4 ) { + cmdCase = CASE1; + NeNc = 0; + } else if( wLength == 5) { + cmdCase = CASE2; + NeNc = pAPDU[4]; /* C5 */ + if (NeNc == 0) { + NeNc = 256; + } + } else if( wLength == 6) { + NeNc = pAPDU[4]; /* C5 */ + cmdCase = CASE3; + } else if( wLength == 7) { + NeNc = pAPDU[4]; /* C5 */ + if( NeNc == 0 ) { + cmdCase = CASE2; + NeNc = (pAPDU[5]<<8)+pAPDU[6]; + } else { + cmdCase = CASE3; + } + } else { + NeNc = pAPDU[4]; /* C5 */ + if( NeNc == 0 ) { + cmdCase = CASE3; + NeNc = (pAPDU[5]<<8)+pAPDU[6]; + } else { + cmdCase = CASE3; + } + } + + TRACE_DEBUG("CASE=0x%X NeNc=0x%X\n\r", cmdCase, NeNc); + + /* Handle Procedure Bytes */ + do { + ISO7816_GetChar(&procByte); + ins = procByte ^ 0xff; + /* Handle NULL */ + if ( procByte == ISO_NULL_VAL ) { + TRACE_DEBUG("INS\n\r"); + continue; + } + /* Handle SW1 */ + else if ( ((procByte & 0xF0) ==0x60) || ((procByte & 0xF0) ==0x90) ) { + TRACE_DEBUG("SW1\n\r"); + SW1 = 1; + } + /* Handle INS */ + else if ( pAPDU[1] == procByte) { + TRACE_DEBUG("HdlINS\n\r"); + if (cmdCase == CASE2) { + /* receive data from card */ + do { + ISO7816_GetChar(&pMessage[indexMessage++]); + } while( 0 != --NeNc ); + } else { + /* Send data */ + do { + ISO7816_SendChar(pAPDU[indexApdu++]); + } while( 0 != --NeNc ); + } + } + /* Handle INS ^ 0xff */ + else if ( pAPDU[1] == ins) { + TRACE_DEBUG("HdlINS+\n\r"); + if (cmdCase == CASE2) { + /* receive data from card */ + ISO7816_GetChar(&pMessage[indexMessage++]); + } else { + ISO7816_SendChar(pAPDU[indexApdu++]); + } + NeNc--; + } else { + /* ?? */ + TRACE_DEBUG("procByte=0x%X\n\r", procByte); + break; + } + } while (NeNc != 0); + + /* Status Bytes */ + if (SW1 == 0) { + ISO7816_GetChar(&pMessage[indexMessage++]); /* SW1 */ + } else { + pMessage[indexMessage++] = procByte; + } + ISO7816_GetChar(&pMessage[indexMessage++]); /* SW2 */ + + return( indexMessage ); + +} + +/** + * Escape ISO7816 + */ +void ISO7816_Escape( void ) +{ + TRACE_DEBUG("For user, if needed\n\r"); +} + +/** + * Restart clock ISO7816 + */ +void ISO7816_RestartClock( void ) +{ + TRACE_DEBUG("ISO7816_RestartClock\n\r"); + UsartIso->US_BRGR = 13; +} + +/** + * Stop clock ISO7816 + */ +void ISO7816_StopClock( void ) +{ + TRACE_DEBUG("ISO7816_StopClock\n\r"); + UsartIso->US_BRGR = 0; +} + +/** + * T0 APDU + */ +void ISO7816_toAPDU( void ) +{ + TRACE_DEBUG("ISO7816_toAPDU\n\r"); + TRACE_DEBUG("Not supported at this time\n\r"); +} + +/** + * Answer To Reset (ATR) + * \param pAtr ATR buffer + * \param pLength Pointer for store the ATR length + */ +void ISO7816_Datablock_ATR( uint8_t* pAtr, uint8_t* pLength ) +{ + uint32_t i; + uint32_t j; + uint32_t y; + + *pLength = 0; + + /* Read ATR TS */ + ISO7816_GetChar(&pAtr[0]); + /* Read ATR T0 */ + ISO7816_GetChar(&pAtr[1]); + y = pAtr[1] & 0xF0; + i = 2; + + /* Read ATR Ti */ + while (y) { + if (y & 0x10) { /* TA[i] */ + ISO7816_GetChar(&pAtr[i++]); + } + if (y & 0x20) { /* TB[i] */ + ISO7816_GetChar(&pAtr[i++]); + } + if (y & 0x40) { /* TC[i] */ + ISO7816_GetChar(&pAtr[i++]); + } + if (y & 0x80) { /* TD[i] */ + ISO7816_GetChar(&pAtr[i]); + y = pAtr[i++] & 0xF0; + } else { + y = 0; + } + } + + /* Historical Bytes */ + y = pAtr[1] & 0x0F; + for( j=0; j < y; j++ ) { + ISO7816_GetChar(&pAtr[i++]); + } + + *pLength = i; + +} + +/** + * Set data rate and clock frequency + * \param dwClockFrequency ICC clock frequency in KHz. + * \param dwDataRate ICC data rate in bpd + */ +void ISO7816_SetDataRateandClockFrequency( uint32_t dwClockFrequency, + uint32_t dwDataRate ) +{ + uint8_t ClockFrequency; + + /* Define the baud rate divisor register */ + /* CD = MCK / SCK */ + /* SCK = FIDI x BAUD = 372 x 9600 */ + /* BOARD_MCK */ + /* CD = MCK/(FIDI x BAUD) = 48000000 / (372x9600) = 13 */ + UsartIso->US_BRGR = BOARD_MCK / (dwClockFrequency*1000); + + ClockFrequency = BOARD_MCK / UsartIso->US_BRGR; + + UsartIso->US_FIDI = (ClockFrequency)/dwDataRate; + +} + +/** + * Pin status for ISO7816 RESET + * \return 1 if the Pin RstMC is high; otherwise 0. + */ +uint8_t ISO7816_StatusReset( void ) +{ + return PIO_Get(&st_pinIso7816RstMC); +} + +/** + * cold reset + */ +void ISO7816_cold_reset( void ) +{ + volatile uint32_t i; + + /* tb: wait 400 cycles*/ + for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) { + } + + UsartIso->US_RHR; + UsartIso->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + + ISO7816_IccPowerOn(); +} + +/** + * Warm reset + */ +void ISO7816_warm_reset( void ) +{ + volatile uint32_t i; + + ISO7816_IccPowerOff(); + + /* tb: wait 400 cycles */ + for( i=0; i<(120*(BOARD_MCK/1000000)); i++ ) { + } + + UsartIso->US_RHR; + UsartIso->US_CR = US_CR_RSTSTA | US_CR_RSTIT | US_CR_RSTNACK; + + ISO7816_IccPowerOn(); +} + +/** + * Decode ATR trace + * \param pAtr pointer on ATR buffer + */ +void ISO7816_Decode_ATR( uint8_t* pAtr ) +{ + uint32_t i; + uint32_t j; + uint32_t y; + uint8_t offset; + + printf("\n\r"); + printf("ATR: Answer To Reset:\n\r"); + printf("TS = 0x%X Initial character ",pAtr[0]); + if( pAtr[0] == 0x3B ) { + + printf("Direct Convention\n\r"); + } else { + if( pAtr[0] == 0x3F ) { + printf("Inverse Convention\n\r"); + } else { + printf("BAD Convention\n\r"); + } + } + + printf("T0 = 0x%X Format character\n\r",pAtr[1]); + printf(" Number of historical bytes: K = %d\n\r", pAtr[1]&0x0F); + printf(" Presence further interface byte:\n\r"); + if( pAtr[1]&0x10 ) { + printf("TA "); + } + if( pAtr[1]&0x20 ) { + printf("TB "); + } + if( pAtr[1]&0x40 ) { + printf("TC "); + } + if( pAtr[1]&0x80 ) { + printf("TD "); + } + if( pAtr[1] != 0 ) { + printf(" present\n\r"); + } + + i = 2; + y = pAtr[1] & 0xF0; + + /* Read ATR Ti */ + offset = 1; + while (y) { + + if (y & 0x10) { /* TA[i] */ + printf("TA[%d] = 0x%X ", offset, pAtr[i]); + if( offset == 1 ) { + printf("FI = %d ", (pAtr[i]>>4)); + printf("DI = %d", (pAtr[i]&0x0F)); + } + printf("\n\r"); + i++; + } + if (y & 0x20) { /* TB[i] */ + printf("TB[%d] = 0x%X\n\r", offset, pAtr[i]); + i++; + } + if (y & 0x40) { /* TC[i] */ + printf("TC[%d] = 0x%X ", offset, pAtr[i]); + if( offset == 1 ) { + printf("Extra Guard Time: N = %d", pAtr[i]); + } + printf("\n\r"); + i++; + } + if (y & 0x80) { /* TD[i] */ + printf("TD[%d] = 0x%X\n\r", offset, pAtr[i]); + y = pAtr[i++] & 0xF0; + } else { + y = 0; + } + offset++; + } + + /* Historical Bytes */ + printf("Historical bytes:\n\r"); + y = pAtr[1] & 0x0F; + for( j=0; j < y; j++ ) { + printf(" 0x%X", pAtr[i]); + if( (pAtr[i] > 0x21) && (pAtr[i] < 0x7D) ) { /* ASCII */ + printf("(%c) ", pAtr[i]); + } + i++; + } + printf("\n\r\n\r"); + +} + +/** Initializes a ISO driver + * \param pUsart Pointer to the USART peripheral to configure. + * \param usartId USART ID for iso7816 + * \param pPinIso7816RstMC Pin ISO 7816 Rst MC + */ +void ISO7816_Init( Usart *pUsart, uint32_t usartId , const Pin pPinIso7816RstMC ) +{ + TRACE_DEBUG("ISO_Init\n\r"); + UsartIso = pUsart; + UsartIsoId = usartId; + uint32_t baudrate = USART7816BAUDRATE; + + /* Pin ISO7816 initialize */ + st_pinIso7816RstMC = pPinIso7816RstMC; + + PMC_EnablePeripheral(UsartIsoId); + + UsartIso->US_FIDI = 372; /* by default */ + + /* Configure USART */ + USART_Configure( UsartIso, + US_MR_USART_MODE_IS07816_T_0 + | US_MR_USCLKS_MCK + | US_MR_NBSTOP_1_BIT + | US_MR_PAR_EVEN + | US_MR_CHRL_8_BIT + | US_MR_CLKO + | (3<<24), /* MAX_ITERATION */ + baudrate, + BOARD_MCK); + + /* Write the Time-guard Register */ + UsartIso->US_TTGR = 5; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mcan.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mcan.c new file mode 100644 index 000000000..baed8627d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mcan.c @@ -0,0 +1,1140 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * Implements functions for Controller Area Network (CAN) + * peripheral operations. + */ +/** \addtogroup can_module + *@{*/ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "board.h" +#include "chip.h" +#include "mcan_config.h" +#include +/*--------------------------------------------------------------------------- + * Definitions + *---------------------------------------------------------------------------*/ +#define MAILBOX_ADDRESS(address) ( 0xFFFC & (address) ) + +#define CAN_CLK_FREQ_HZ MCAN_PROG_CLK_FREQ_HZ + +#define MCAN0_TSEG1 ( MCAN0_PROP_SEG + MCAN0_PHASE_SEG1 ) +#define MCAN0_TSEG2 ( MCAN0_PHASE_SEG2 ) +#define MCAN0_BRP ((uint32_t) (( (float) CAN_CLK_FREQ_HZ / \ + ((float)( MCAN0_TSEG1 + MCAN0_TSEG2 + 3 ) *\ + (float) MCAN0_BIT_RATE_BPS )) - 1 )) +#define MCAN0_SJW ( MCAN0_SYNC_JUMP - 1 ) +#define MCAN0_FTSEG1 ( MCAN0_FAST_PROP_SEG + MCAN0_FAST_PHASE_SEG1 ) +#define MCAN0_FTSEG2 ( MCAN0_FAST_PHASE_SEG2 ) +#define MCAN0_FBRP ((uint32_t) (( (float) CAN_CLK_FREQ_HZ / \ + ((float)( MCAN0_FTSEG1 + MCAN0_FTSEG2 + 3 ) * \ + (float) MCAN0_FAST_BIT_RATE_BPS )) - 1 )) +#define MCAN0_FSJW ( MCAN0_FAST_SYNC_JUMP - 1 ) + +#define MCAN0_STD_FLTS_WRDS (MCAN0_NMBR_STD_FLTS) + /* 128 max filters */ +#define MCAN0_EXT_FLTS_WRDS (MCAN0_NMBR_EXT_FLTS * 2) + /* 64 max filters */ +#define MCAN0_RX_FIFO0_WRDS (MCAN0_NMBR_RX_FIFO0_ELMTS * \ + ((MCAN0_RX_FIFO0_ELMT_SZ/4) + 2)) + /* 64 elements max */ +#define MCAN0_RX_FIFO1_WRDS (MCAN0_NMBR_RX_FIFO1_ELMTS *\ + ((MCAN0_RX_FIFO1_ELMT_SZ/4) + 2)) + /* 64 elements max */ +#define MCAN0_RX_DED_BUFS_WRDS (MCAN0_NMBR_RX_DED_BUF_ELMTS * \ + ((MCAN0_RX_BUF_ELMT_SZ/4) + 2)) + /* 64 elements max */ +#define MCAN0_TX_EVT_FIFO_WRDS (MCAN0_NMBR_TX_EVT_FIFO_ELMTS * 2) + /* 32 elements max */ +#define MCAN0_TX_DED_BUF_WRDS (MCAN0_NMBR_TX_DED_BUF_ELMTS * \ + ((MCAN0_TX_BUF_ELMT_SZ/4) + 2)) + /* 32 elements max */ +#define MCAN0_TX_FIFO_Q_WRDS (MCAN0_NMBR_TX_FIFO_Q_ELMTS *\ + ((MCAN0_TX_BUF_ELMT_SZ/4) + 2)) + /* 32 elements max */ + +#define MCAN1_TSEG1 ( MCAN1_PROP_SEG + MCAN1_PHASE_SEG1 ) +#define MCAN1_TSEG2 ( MCAN1_PHASE_SEG2 ) +#define MCAN1_BRP ((uint32_t) (( (float) CAN_CLK_FREQ_HZ / \ + ((float)( MCAN1_TSEG1 + MCAN1_TSEG2 + 3 ) *\ + (float) MCAN1_BIT_RATE_BPS )) - 1 )) +#define MCAN1_SJW ( MCAN1_SYNC_JUMP - 1 ) +#define MCAN1_FTSEG1 ( MCAN1_FAST_PROP_SEG + MCAN1_FAST_PHASE_SEG1 ) +#define MCAN1_FTSEG2 ( MCAN1_FAST_PHASE_SEG2 ) +#define MCAN1_FBRP ((uint32_t) (( (float) CAN_CLK_FREQ_HZ /\ + ((float)( MCAN1_FTSEG1 + MCAN1_FTSEG2 + 3 ) *\ + (float) MCAN1_FAST_BIT_RATE_BPS )) - 1 )) +#define MCAN1_FSJW ( MCAN1_FAST_SYNC_JUMP - 1 ) + +#define MCAN1_STD_FLTS_WRDS (MCAN1_NMBR_STD_FLTS) + /* 128 max filters */ +#define MCAN1_EXT_FLTS_WRDS (MCAN1_NMBR_EXT_FLTS * 2) + /* 64 max filters */ +#define MCAN1_RX_FIFO0_WRDS (MCAN1_NMBR_RX_FIFO0_ELMTS * \ + ((MCAN1_RX_FIFO0_ELMT_SZ/4) + 2)) + /* 64 elements max */ +#define MCAN1_RX_FIFO1_WRDS (MCAN1_NMBR_RX_FIFO1_ELMTS *\ + ((MCAN1_RX_FIFO1_ELMT_SZ/4) + 2)) + /* 64 elements max */ +#define MCAN1_RX_DED_BUFS_WRDS (MCAN1_NMBR_RX_DED_BUF_ELMTS * \ + ((MCAN1_RX_BUF_ELMT_SZ/4) + 2)) + /* 64 elements max */ +#define MCAN1_TX_EVT_FIFO_WRDS (MCAN1_NMBR_TX_EVT_FIFO_ELMTS * 2) +/* 32 elements max */ +#define MCAN1_TX_DED_BUF_WRDS (MCAN1_NMBR_TX_DED_BUF_ELMTS * \ + ((MCAN1_TX_BUF_ELMT_SZ/4) + 2)) + /* 32 elements max */ +#define MCAN1_TX_FIFO_Q_WRDS (MCAN1_NMBR_TX_FIFO_Q_ELMTS * \ + ((MCAN1_TX_BUF_ELMT_SZ/4) + 2)) + /* 32 elements max */ + +/* validate CAN0 entries */ +#if ( MCAN0_TSEG1 > 63 ) +#error "Invalid CAN0 TSEG1" +#endif +#if ( MCAN0_TSEG2 > 15 ) +#error "Invalid CAN0 TSEG2" +#endif +#if ( MCAN0_SJW > 15 ) +#error "Invalid CAN0 SJW" +#endif +#if ( MCAN0_FTSEG1 > 15 ) +#error "Invalid CAN0 FTSEG1" +#endif +#if ( MCAN0_FTSEG2 > 7 ) +#error "Invalid CAN0 FTSEG2" +#endif +#if ( MCAN0_FSJW > 3 ) +#error "Invalid CAN0 FSJW" +#endif + +#if ( MCAN0_NMBR_STD_FLTS > 128 ) +#error "Invalid CAN0 # of Standard Filters" +#endif +#if ( MCAN0_NMBR_EXT_FLTS > 64 ) +#error "Invalid CAN0 # of Extended Filters" +#endif +#if ( MCAN0_NMBR_RX_FIFO0_ELMTS > 64 ) +#error "Invalid CAN0 # RX FIFO 0 ELEMENTS" +#endif +#if ( MCAN0_NMBR_RX_FIFO1_ELMTS > 64 ) +#error "Invalid CAN0 # RX FIFO 0 ELEMENTS" +#endif +#if ( MCAN0_NMBR_RX_DED_BUF_ELMTS > 64 ) +#error "Invalid CAN0 # RX BUFFER ELEMENTS" +#endif +#if ( MCAN0_NMBR_TX_EVT_FIFO_ELMTS > 32 ) +#error "Invalid CAN0 # TX EVENT FIFO ELEMENTS" +#endif +#if ( (MCAN0_NMBR_TX_DED_BUF_ELMTS + MCAN0_NMBR_TX_FIFO_Q_ELMTS) > 32 ) +#error "Invalid CAN0 # TX BUFFER ELEMENTS" +#endif + +#if ( 8 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (0u) +#elif ( 12 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (1u) +#elif ( 16 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (2u) +#elif ( 20 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (3u) +#elif ( 24 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (4u) +#elif ( 32 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (5u) +#elif ( 48 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (6u) +#elif ( 64 == MCAN0_RX_FIFO0_ELMT_SZ ) +#define MCAN0_RX_FIFO0_DATA_SIZE (7u) +#else +#error "Invalid CAN0 RX FIFO0 ELEMENT SIZE" +#endif + +#if ( 8 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (0u) +#elif ( 12 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (1u) +#elif ( 16 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (2u) +#elif ( 20 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (3u) +#elif ( 24 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (4u) +#elif ( 32 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (5u) +#elif ( 48 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (6u) +#elif ( 64 == MCAN0_RX_FIFO1_ELMT_SZ ) +#define MCAN0_RX_FIFO1_DATA_SIZE (7u) +#else +#error "Invalid CAN0 RX FIFO1 ELEMENT SIZE" +#endif + +#if ( 8 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (0u) +#elif ( 12 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (1u) +#elif ( 16 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (2u) +#elif ( 20 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (3u) +#elif ( 24 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (4u) +#elif ( 32 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (5u) +#elif ( 48 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (6u) +#elif ( 64 == MCAN0_RX_BUF_ELMT_SZ ) +#define MCAN0_RX_BUF_DATA_SIZE (7u) +#else +#error "Invalid CAN0 RX BUFFER ELEMENT SIZE" +#endif + +#if ( 8 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (0u) +#elif ( 12 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (1u) +#elif ( 16 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (2u) +#elif ( 20 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (3u) +#elif ( 24 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (4u) +#elif ( 32 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (5u) +#elif ( 48 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (6u) +#elif ( 64 == MCAN0_TX_BUF_ELMT_SZ ) +#define MCAN0_TX_BUF_DATA_SIZE (7u) +#else +#error "Invalid CAN0 TX BUFFER ELEMENT SIZE" +#endif + +/* validate CAN1 entries */ +#if ( MCAN1_TSEG1 > 63 ) +#error "Invalid CAN1 TSEG1" +#endif +#if ( MCAN1_TSEG2 > 15 ) +#error "Invalid CAN1 TSEG2" +#endif +#if ( MCAN1_SJW > 15 ) +#error "Invalid CAN1 SJW" +#endif +#if ( MCAN1_FTSEG1 > 15 ) +#error "Invalid CAN1 FTSEG1" +#endif +#if ( MCAN1_FTSEG2 > 7 ) +#error "Invalid CAN1 FTSEG2" +#endif +#if ( MCAN1_FSJW > 3 ) +#error "Invalid CAN1 FSJW" +#endif + +#if ( MCAN1_NMBR_STD_FLTS > 128 ) +#error "Invalid CAN1 # of Standard Filters" +#endif +#if ( MCAN1_NMBR_EXT_FLTS > 64 ) +#error "Invalid CAN1 # of Extended Filters" +#endif +#if ( MCAN1_NMBR_RX_FIFO0_ELMTS > 64 ) +#error "Invalid CAN1 # RX FIFO 0 ELEMENTS" +#endif +#if ( MCAN1_NMBR_RX_FIFO1_ELMTS > 64 ) +#error "Invalid CAN1 # RX FIFO 0 ELEMENTS" +#endif +#if ( MCAN1_NMBR_RX_DED_BUF_ELMTS > 64 ) +#error "Invalid CAN1 # RX BUFFER ELEMENTS" +#endif +#if ( MCAN1_NMBR_TX_EVT_FIFO_ELMTS > 32 ) +#error "Invalid CAN1 # TX EVENT FIFO ELEMENTS" +#endif +#if ( (MCAN1_NMBR_TX_DED_BUF_ELMTS + MCAN1_NMBR_TX_FIFO_Q_ELMTS) > 32 ) +#error "Invalid CAN1 # TX BUFFER ELEMENTS" +#endif + +#if ( 8 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (0u) +#elif ( 12 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (1u) +#elif ( 16 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (2u) +#elif ( 20 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (3u) +#elif ( 24 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (4u) +#elif ( 32 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (5u) +#elif ( 48 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (6u) +#elif ( 64 == MCAN1_RX_FIFO0_ELMT_SZ ) +#define MCAN1_RX_FIFO0_DATA_SIZE (7u) +#else +#error "Invalid CAN1 RX FIFO0 ELEMENT SIZE" +#endif + +#if ( 8 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (0u) +#elif ( 12 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (1u) +#elif ( 16 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (2u) +#elif ( 20 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (3u) +#elif ( 24 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (4u) +#elif ( 32 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (5u) +#elif ( 48 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (6u) +#elif ( 64 == MCAN1_RX_FIFO1_ELMT_SZ ) +#define MCAN1_RX_FIFO1_DATA_SIZE (7u) +#else +#error "Invalid CAN1 RX FIFO1 ELEMENT SIZE" +#endif + +#if ( 8 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (0u) +#elif ( 12 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (1u) +#elif ( 16 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (2u) +#elif ( 20 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (3u) +#elif ( 24 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (4u) +#elif ( 32 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (5u) +#elif ( 48 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (6u) +#elif ( 64 == MCAN1_RX_BUF_ELMT_SZ ) +#define MCAN1_RX_BUF_DATA_SIZE (7u) +#else +#error "Invalid CAN1 RX BUFFER ELEMENT SIZE" +#endif + +#if ( 8 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (0u) +#elif ( 12 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (1u) +#elif ( 16 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (2u) +#elif ( 20 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (3u) +#elif ( 24 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (4u) +#elif ( 32 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (5u) +#elif ( 48 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (6u) +#elif ( 64 == MCAN1_TX_BUF_ELMT_SZ ) +#define MCAN1_TX_BUF_DATA_SIZE (7u) +#else +#error "Invalid CAN1 TX BUFFER ELEMENT SIZE" +#endif + +#define CAN_11_BIT_ID_MASK (0x7FF) +#define CAN_29_BIT_ID_MASK (0x1FFFFFFF) +#define ELMT_SIZE_MASK (0x1F) +/* max element size is 18 words, fits in 5 bits */ + +#define BUFFER_XTD_MASK (0x40000000) +#define BUFFER_EXT_ID_MASK (0x1FFFFFFF) +#define BUFFER_STD_ID_MASK (0x1FFC0000) +#define BUFFER_DLC_MASK (0x000F0000) +#define BUFFER_RXTS_MASK (0x0000FFFF) + +#define STD_FILT_SFT_MASK (3 << 30) +#define STD_FILT_SFT_RANGE (0 << 30) +#define STD_FILT_SFT_DUAL (1 << 30) +#define STD_FILT_SFT_CLASSIC (2 << 30) +#define STD_FILT_SFEC_MASK (7 << 27) +#define STD_FILT_SFEC_DISABLE (0 << 27) +#define STD_FILT_SFEC_FIFO0 (1 << 27) +#define STD_FILT_SFEC_FIFO1 (2 << 27) +#define STD_FILT_SFEC_REJECT (3 << 27) +#define STD_FILT_SFEC_PRIORITY (4 << 27) +#define STD_FILT_SFEC_PRIORITY_FIFO0 (5 << 27) +#define STD_FILT_SFEC_PRIORITY_FIFO1 (6 << 27) +#define STD_FILT_SFEC_BUFFER (7 << 27) +#define STD_FILT_SFID1_MASK (0x03FF << 16) +#define STD_FILT_SFID2_MASK (0x3FF << 0) +#define STD_FILT_SFID2_RX_BUFFER (0 << 9) +#define STD_FILT_SFID2_DEBUG_A (1 << 9) +#define STD_FILT_SFID2_DEBUG_B (2 << 9) +#define STD_FILT_SFID2_DEBUG_C (3 << 9) +#define STD_FILT_SFID2_BUFFER(nmbr) (nmbr & 0x3F) + +#define EXT_FILT_EFEC_MASK (7 << 29) +#define EXT_FILT_EFEC_DISABLE (0 << 29) +#define EXT_FILT_EFEC_FIFO0 (1 << 29) +#define EXT_FILT_EFEC_FIFO1 (2 << 29) +#define EXT_FILT_EFEC_REJECT (3 << 29) +#define EXT_FILT_EFEC_PRIORITY (4 << 29) +#define EXT_FILT_EFEC_PRIORITY_FIFO0 (5 << 29) +#define EXT_FILT_EFEC_PRIORITY_FIFO1 (6 << 29) +#define EXT_FILT_EFEC_BUFFER (7 << 29) +#define EXT_FILT_EFID1_MASK (0x1FFFFFFF) +#define EXT_FILT_EFT_MASK (3 << 30) +#define EXT_FILT_EFT_RANGE (0 << 30) +#define EXT_FILT_EFT_DUAL (1 << 30) +#define EXT_FILT_EFT_CLASSIC (2 << 30) +#define EXT_FILT_EFT_RANGE_NO_XIDAM (3 << 30) +#define EXT_FILT_EFID2_MASK (0x1FFFFFFF) +#define EXT_FILT_EFID2_RX_BUFFER (0 << 9) +#define EXT_FILT_EFID2_DEBUG_A (1 << 9) +#define EXT_FILT_EFID2_DEBUG_B (2 << 9) +#define EXT_FILT_EFID2_DEBUG_C (3 << 9) +#define EXT_FILT_EFID2_BUFFER(nmbr) (nmbr & 0x3F) + + +/*--------------------------------------------------------------------------- + * Internal variables + *---------------------------------------------------------------------------*/ + +static const Pin pinsMcan0[] = {PIN_MCAN0_TXD, PIN_MCAN0_RXD }; +static const Pin pinsMcan1[] = {PIN_MCAN1_TXD, PIN_MCAN1_RXD }; + +static uint32_t can0MsgRam[MCAN0_STD_FLTS_WRDS + + MCAN0_EXT_FLTS_WRDS + + MCAN0_RX_FIFO0_WRDS + + MCAN0_RX_FIFO1_WRDS + + MCAN0_RX_DED_BUFS_WRDS + + MCAN0_TX_EVT_FIFO_WRDS + + MCAN0_TX_DED_BUF_WRDS + + MCAN0_TX_FIFO_Q_WRDS]; + +static uint32_t can1MsgRam[MCAN1_STD_FLTS_WRDS + + MCAN1_EXT_FLTS_WRDS + + MCAN1_RX_FIFO0_WRDS + + MCAN1_RX_FIFO1_WRDS + + MCAN1_RX_DED_BUFS_WRDS + + MCAN1_TX_EVT_FIFO_WRDS + + MCAN1_TX_DED_BUF_WRDS + + MCAN1_TX_FIFO_Q_WRDS]; + +const MCan_ConfigType mcan0Config = +{ + MCAN0, + MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) | + MCAN_BTP_TSEG2(MCAN0_TSEG2) | MCAN_BTP_SJW(MCAN0_SJW), + MCAN_FBTP_FBRP(MCAN0_FBRP) | MCAN_FBTP_FTSEG1(MCAN0_FTSEG1) | + MCAN_FBTP_FTSEG2(MCAN0_FTSEG2) | MCAN_FBTP_FSJW(MCAN0_FSJW), + MCAN0_NMBR_STD_FLTS, + MCAN0_NMBR_EXT_FLTS, + MCAN0_NMBR_RX_FIFO0_ELMTS, + MCAN0_NMBR_RX_FIFO1_ELMTS, + MCAN0_NMBR_RX_DED_BUF_ELMTS, + MCAN0_NMBR_TX_EVT_FIFO_ELMTS, + MCAN0_NMBR_TX_DED_BUF_ELMTS, + MCAN0_NMBR_TX_FIFO_Q_ELMTS, + (MCAN0_RX_FIFO0_DATA_SIZE << 29) | ((MCAN0_RX_FIFO0_ELMT_SZ/4)+2), + /* element size in WORDS */ + (MCAN0_RX_FIFO1_DATA_SIZE << 29) | ((MCAN0_RX_FIFO1_ELMT_SZ/4)+2), + /* element size in WORDS */ + (MCAN0_RX_BUF_DATA_SIZE << 29) | ((MCAN0_RX_BUF_ELMT_SZ/4)+2), + /* element size in WORDS */ + (MCAN0_TX_BUF_DATA_SIZE << 29) | ((MCAN0_TX_BUF_ELMT_SZ/4)+2), + /* element size in WORDS */ + { + &can0MsgRam[0], + &can0MsgRam[MCAN0_STD_FLTS_WRDS], + &can0MsgRam[MCAN0_STD_FLTS_WRDS + MCAN0_EXT_FLTS_WRDS], + &can0MsgRam[MCAN0_STD_FLTS_WRDS + MCAN0_EXT_FLTS_WRDS + MCAN0_RX_FIFO0_WRDS], + &can0MsgRam[MCAN0_STD_FLTS_WRDS + MCAN0_EXT_FLTS_WRDS + MCAN0_RX_FIFO0_WRDS + + MCAN0_RX_FIFO1_WRDS], + &can0MsgRam[MCAN0_STD_FLTS_WRDS + MCAN0_EXT_FLTS_WRDS + MCAN0_RX_FIFO0_WRDS + + MCAN0_RX_FIFO1_WRDS + MCAN0_RX_DED_BUFS_WRDS], + &can0MsgRam[MCAN0_STD_FLTS_WRDS + MCAN0_EXT_FLTS_WRDS + MCAN0_RX_FIFO0_WRDS + + MCAN0_RX_FIFO1_WRDS + MCAN0_RX_DED_BUFS_WRDS + MCAN0_TX_EVT_FIFO_WRDS], + &can0MsgRam[MCAN0_STD_FLTS_WRDS + MCAN0_EXT_FLTS_WRDS + MCAN0_RX_FIFO0_WRDS + + MCAN0_RX_FIFO1_WRDS + MCAN0_RX_DED_BUFS_WRDS + MCAN0_TX_EVT_FIFO_WRDS + + MCAN0_TX_DED_BUF_WRDS] + }, +}; + +const MCan_ConfigType mcan1Config = +{ + MCAN1, + MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) | + MCAN_BTP_TSEG2(MCAN1_TSEG2) | MCAN_BTP_SJW(MCAN1_SJW), + MCAN_FBTP_FBRP(MCAN1_FBRP) | MCAN_FBTP_FTSEG1(MCAN1_FTSEG1) | + MCAN_FBTP_FTSEG2(MCAN1_FTSEG2) | MCAN_FBTP_FSJW(MCAN1_FSJW), + MCAN1_NMBR_STD_FLTS, + MCAN1_NMBR_EXT_FLTS, + MCAN1_NMBR_RX_FIFO0_ELMTS, + MCAN1_NMBR_RX_FIFO1_ELMTS, + MCAN0_NMBR_RX_DED_BUF_ELMTS, + MCAN1_NMBR_TX_EVT_FIFO_ELMTS, + MCAN1_NMBR_TX_DED_BUF_ELMTS, + MCAN1_NMBR_TX_FIFO_Q_ELMTS, + (MCAN1_RX_FIFO0_DATA_SIZE << 29) | ((MCAN1_RX_FIFO0_ELMT_SZ/4)+2), + /* element size in WORDS */ + (MCAN1_RX_FIFO1_DATA_SIZE << 29) | ((MCAN1_RX_FIFO1_ELMT_SZ/4)+2), + /* element size in WORDS */ + (MCAN1_RX_BUF_DATA_SIZE << 29) | ((MCAN1_RX_BUF_ELMT_SZ/4)+2), + /* element size in WORDS */ + (MCAN1_TX_BUF_DATA_SIZE << 29) | ((MCAN1_TX_BUF_ELMT_SZ/4)+2), + /* element size in WORDS */ + { + &can1MsgRam[0], + &can1MsgRam[MCAN1_STD_FLTS_WRDS], + &can1MsgRam[MCAN1_STD_FLTS_WRDS + MCAN1_EXT_FLTS_WRDS], + &can1MsgRam[MCAN1_STD_FLTS_WRDS + MCAN1_EXT_FLTS_WRDS + MCAN1_RX_FIFO0_WRDS], + &can1MsgRam[MCAN1_STD_FLTS_WRDS + MCAN1_EXT_FLTS_WRDS + MCAN1_RX_FIFO0_WRDS + + MCAN1_RX_FIFO1_WRDS], + &can1MsgRam[MCAN1_STD_FLTS_WRDS + MCAN1_EXT_FLTS_WRDS + MCAN1_RX_FIFO0_WRDS + + MCAN1_RX_FIFO1_WRDS + MCAN1_RX_DED_BUFS_WRDS], + &can1MsgRam[MCAN1_STD_FLTS_WRDS + MCAN1_EXT_FLTS_WRDS + MCAN1_RX_FIFO0_WRDS + + MCAN1_RX_FIFO1_WRDS + MCAN1_RX_DED_BUFS_WRDS + MCAN1_TX_EVT_FIFO_WRDS], + &can1MsgRam[MCAN1_STD_FLTS_WRDS + MCAN1_EXT_FLTS_WRDS + MCAN1_RX_FIFO0_WRDS + + MCAN1_RX_FIFO1_WRDS + MCAN1_RX_DED_BUFS_WRDS + MCAN1_TX_EVT_FIFO_WRDS + + MCAN1_TX_DED_BUF_WRDS] + }, +}; + + +/*--------------------------------------------------------------------------- + * Exported Functions + *---------------------------------------------------------------------------*/ + /** + * \brief Initializes the MCAN hardware for giving peripheral. + * Default: Mixed mode TX Buffer + FIFO. + * + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_Init( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t regVal32; + uint32_t * pMsgRam; + uint32_t cntr; + IRQn_Type mCanLine0Irq; + + /* Both MCAN controllers use programmable clock 5 to derive bit rate */ + // select MCK divided by 1 as programmable clock 5 output + PMC->PMC_PCK[5] = PMC_PCK_PRES(MCAN_PROG_CLK_PRESCALER - 1) | MCAN_PROG_CLK_SELECT; + PMC->PMC_SCER = PMC_SCER_PCK5; + + if( MCAN0 == mcan ) { + PIO_Configure(pinsMcan0, PIO_LISTSIZE(pinsMcan0)); + // Enable MCAN peripheral clock + PMC_EnablePeripheral( ID_MCAN0 ); + // Configure Message RAM Base Address + regVal32 = MATRIX->CCFG_CAN0 & 0x000001FF; + MATRIX->CCFG_CAN0 = regVal32 | + ( (uint32_t) mcanConfig->msgRam.pStdFilts & 0xFFFF0000 ); + mCanLine0Irq = MCAN0_IRQn; + } else if ( MCAN1 == mcan ) { + PIO_Configure(pinsMcan1, PIO_LISTSIZE(pinsMcan1)); + // Enable MCAN peripheral clock + PMC_EnablePeripheral( ID_MCAN1 ); + // Configure Message RAM Base Address + regVal32 = MATRIX->CCFG_SYSIO & 0x0000FFFF; + MATRIX->CCFG_SYSIO = regVal32 | ( (uint32_t) mcanConfig->msgRam.pStdFilts & 0xFFFF0000 ); + mCanLine0Irq = MCAN1_IRQn; + } else { + return; + } + + /* Indicates Initialization state */ + mcan->MCAN_CCCR = MCAN_CCCR_INIT_ENABLED; + do { regVal32 = mcan->MCAN_CCCR; } + while(0u == (regVal32 & MCAN_CCCR_INIT_ENABLED)); + + /* Enable writing to configuration registers */ + mcan->MCAN_CCCR = MCAN_CCCR_INIT_ENABLED | MCAN_CCCR_CCE_CONFIGURABLE; + + /* Global Filter Configuration: Reject remote frames, reject non-matching frames */ + mcan->MCAN_GFC = MCAN_GFC_RRFE_REJECT | MCAN_GFC_RRFS_REJECT + | MCAN_GFC_ANFE(2) | MCAN_GFC_ANFS(2); + + // Extended ID Filter AND mask + mcan->MCAN_XIDAM = 0x1FFFFFFF; + + /* Interrupt configuration - leave initialization with all interrupts off */ + // Disable all interrupts + mcan->MCAN_IE = 0; + mcan->MCAN_TXBTIE = 0x00000000; + // All interrupts directed to Line 0 + mcan->MCAN_ILS = 0x00000000; + // Disable both interrupt LINE 0 & LINE 1 + mcan->MCAN_ILE = 0x00; + // Clear all interrupt flags + mcan->MCAN_IR = 0xFFCFFFFF; + /* Enable NVIC - but no interrupts will happen since all sources are + disabled in MCAN_IE */ + NVIC_ClearPendingIRQ(mCanLine0Irq); + NVIC_EnableIRQ(mCanLine0Irq); + NVIC_ClearPendingIRQ((IRQn_Type) (mCanLine0Irq+1)); + NVIC_EnableIRQ((IRQn_Type) (mCanLine0Irq+1)); + + /* Configure CAN bit timing */ + mcan->MCAN_BTP = mcanConfig->bitTiming; + mcan->MCAN_FBTP = mcanConfig->fastBitTiming; + + /* Configure message RAM starting addresses & sizes */ + mcan->MCAN_SIDFC = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pStdFilts ) + | MCAN_SIDFC_LSS(mcanConfig->nmbrStdFilts); + mcan->MCAN_XIDFC = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pExtFilts ) + | MCAN_XIDFC_LSE(mcanConfig->nmbrExtFilts); + mcan->MCAN_RXF0C = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pRxFifo0 ) + | MCAN_RXF0C_F0S(mcanConfig->nmbrFifo0Elmts); + // watermark interrupt off, blocking mode + mcan->MCAN_RXF1C = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pRxFifo1 ) + | MCAN_RXF1C_F1S(mcanConfig->nmbrFifo1Elmts); + // watermark interrupt off, blocking mode + mcan->MCAN_RXBC = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pRxDedBuf ); + mcan->MCAN_TXEFC = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pTxEvtFifo ) + | MCAN_TXEFC_EFS(mcanConfig->nmbrTxEvtFifoElmts); + // watermark interrupt off + mcan->MCAN_TXBC = MAILBOX_ADDRESS( (uint32_t) mcanConfig->msgRam.pTxDedBuf ) + | MCAN_TXBC_NDTB(mcanConfig->nmbrTxDedBufElmts) + | MCAN_TXBC_TFQS(mcanConfig->nmbrTxFifoQElmts); + mcan->MCAN_RXESC = ((mcanConfig->rxBufElmtSize >> (29-MCAN_RXESC_RBDS_Pos)) & + MCAN_RXESC_RBDS_Msk) | + ((mcanConfig->rxFifo1ElmtSize >> (29-MCAN_RXESC_F1DS_Pos)) & + MCAN_RXESC_F1DS_Msk) | + ((mcanConfig->rxFifo0ElmtSize >> (29-MCAN_RXESC_F0DS_Pos)) & + MCAN_RXESC_F0DS_Msk); + mcan->MCAN_TXESC = ((mcanConfig->txBufElmtSize >> (29-MCAN_TXESC_TBDS_Pos)) & + MCAN_TXESC_TBDS_Msk); + + /* Configure Message Filters */ + // ...Disable all standard filters + pMsgRam = mcanConfig->msgRam.pStdFilts; + cntr = mcanConfig->nmbrStdFilts; + while ( cntr > 0 ) { + *pMsgRam++ = STD_FILT_SFEC_DISABLE; + cntr--; + } + // ...Disable all extended filters + pMsgRam = mcanConfig->msgRam.pExtFilts; + cntr = mcanConfig->nmbrExtFilts; + while ( cntr > 0 ) { + *pMsgRam = EXT_FILT_EFEC_DISABLE; + pMsgRam = pMsgRam + 2; + cntr--; + } + + mcan->MCAN_NDAT1 = 0xFFFFFFFF; // clear new (rx) data flags + mcan->MCAN_NDAT2 = 0xFFFFFFFF; // clear new (rx) data flags + + regVal32 = mcan->MCAN_CCCR & ~(MCAN_CCCR_CME_Msk | MCAN_CCCR_CMR_Msk); + mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CME_ISO11898_1; + mcan->MCAN_CCCR = regVal32 | (MCAN_CCCR_CMR_ISO11898_1 | MCAN_CCCR_CME_ISO11898_1); + + __DSB(); + __ISB(); +} + +/** + * \brief Enables a FUTURE switch to FD mode (tx & rx payloads up to 64 bytes) + * but transmits WITHOUT bit rate switching + * INIT must be set - so this should be called between MCAN_Init() and + * MCAN_Enable() + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_InitFdEnable( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t regVal32; + + regVal32 = mcan->MCAN_CCCR & ~MCAN_CCCR_CME_Msk; + mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CME(1); +} + +/** + * \brief Enables a FUTURE switch to FD mode (tx & rx payloads up to 64 bytes) and transmits + * WITH bit rate switching + * INIT must be set - so this should be called between MCAN_Init() and MCAN_Enable() + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_InitFdBitRateSwitchEnable( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t regVal32; + + regVal32 = mcan->MCAN_CCCR & ~MCAN_CCCR_CME_Msk; + mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CME(2); +} + +/** + * \brief Initializes the MCAN in loop back mode. + * INIT must be set - so this should be called between MCAN_Init() and + * MCAN_Enable() + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_InitLoopback( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + + mcan->MCAN_CCCR |= MCAN_CCCR_TEST_ENABLED; + //mcan->MCAN_CCCR |= MCAN_CCCR_MON_ENABLED; // for internal loop back + mcan->MCAN_TEST |= MCAN_TEST_LBCK_ENABLED; +} + +/** + * \brief Initializes MCAN queue for TX + * INIT must be set - so this should be called between MCAN_Init() and + * MCAN_Enable() + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_InitTxQueue( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_TXBC |= MCAN_TXBC_TFQM; +} + +/** + * \brief Enable MCAN peripheral. + * INIT must be set - so this should be called between MCAN_Init() + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_Enable( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_CCCR &= ~MCAN_CCCR_INIT_ENABLED; +} + +/** + * \brief Requests switch to Iso11898-1 (standard / classic) mode (tx & rx + * payloads up to 8 bytes). + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_RequestIso11898_1( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t regVal32; + + regVal32 = mcan->MCAN_CCCR & ~MCAN_CCCR_CMR_Msk; + mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CMR_ISO11898_1; + while ( (mcan->MCAN_CCCR & ( MCAN_CCCR_FDBS | MCAN_CCCR_FDO )) != 0 ) + { /* wait */ } +} + +/** + * \brief Requests switch to FD mode (tx & rx payloads up to 64 bytes) but + * transmits WITHOUT bit + * rate switching. requested mode should have been enabled at initialization + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_RequestFd( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t regVal32; + + if (( mcan->MCAN_CCCR & MCAN_CCCR_CME_Msk ) == MCAN_CCCR_CME(1) ) { + regVal32 = mcan->MCAN_CCCR & ~MCAN_CCCR_CMR_Msk; + mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CMR_FD; + while ( (mcan->MCAN_CCCR & MCAN_CCCR_FDO) == 0 ) { /* wait */ } + } +} + +/** + * \brief Request switch to FD mode (tx & rx payloads up to 64 bytes) and + * transmits WITH bit rate switching. + * requested mode should have been enabled at initialization + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_RequestFdBitRateSwitch( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t regVal32; + + if (( mcan->MCAN_CCCR & MCAN_CCCR_CME_Msk ) == MCAN_CCCR_CME(2) ) { + regVal32 = mcan->MCAN_CCCR & ~MCAN_CCCR_CMR_Msk; + mcan->MCAN_CCCR = regVal32 | MCAN_CCCR_CMR_FD_BITRATE_SWITCH; + while ( (mcan->MCAN_CCCR & ( MCAN_CCCR_FDBS | MCAN_CCCR_FDO )) != + ( MCAN_CCCR_FDBS | MCAN_CCCR_FDO ) ) { /* wait */ } + } +} + +/** + * \brief Switch on loop back mode. + * TEST must be set in MCAN_CCCR - e.g. by a prior call to MCAN_InitLoopback() + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_LoopbackOn( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_TEST |= MCAN_TEST_LBCK_ENABLED; +} + +/** + * \brief Switch off loop back mode. + * \param mcanConfig Pointer to a MCAN instance. + */ +void MCAN_LoopbackOff( const MCan_ConfigType * mcanConfig ) +{ + Mcan * mcan = mcanConfig->pMCan; + mcan->MCAN_TEST &= ~MCAN_TEST_LBCK_ENABLED; +} + +/** + * \brief Enable message line and message stored to Dedicated Receive Buffer + * Interrupt Line. + * \param mcanConfig Pointer to a MCAN instance. + * \param line Message line. + */ +void MCAN_IEnableMessageStoredToRxDedBuffer( const MCan_ConfigType * mcanConfig, + MCan_IntrLineType line ) +{ + Mcan * mcan = mcanConfig->pMCan; + if ( line == CAN_INTR_LINE_0 ) { + mcan->MCAN_ILS &= ~MCAN_ILS_DRXL; + mcan->MCAN_ILE |= MCAN_ILE_EINT0; + } else { + // Interrupt Line 1 + mcan->MCAN_ILS |= MCAN_ILS_DRXL; + mcan->MCAN_ILE |= MCAN_ILE_EINT1; + } + mcan->MCAN_IR = MCAN_IR_DRX; // clear previous flag + mcan->MCAN_IE |= MCAN_IE_DRXE; // enable it +} + +/** + * \brief Configures a Dedicated TX Buffer. + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to buffer. + * \param id Message ID. + * \param idType Type of ID + * \param dlc Type of dlc. + */ +uint8_t * MCAN_ConfigTxDedBuffer( const MCan_ConfigType * mcanConfig, + uint8_t buffer, uint32_t id, MCan_IdType idType, MCan_DlcType dlc ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t * pThisTxBuf = 0; + + if ( buffer < mcanConfig->nmbrTxDedBufElmts ) { + pThisTxBuf = mcanConfig->msgRam.pTxDedBuf + (buffer * + (mcanConfig->txBufElmtSize & ELMT_SIZE_MASK)); + if ( idType == CAN_STD_ID ) + *pThisTxBuf++ = (( id << 18 ) & ( CAN_11_BIT_ID_MASK << 18 )); + else + *pThisTxBuf++ = BUFFER_XTD_MASK | ( id & CAN_29_BIT_ID_MASK ); + *pThisTxBuf++ = (uint32_t) dlc << 16; + /* enable transmit from buffer to set TC interrupt bit in IR, but + interrupt will not happen unless TC interrupt is enabled*/ + mcan->MCAN_TXBTIE = ( 1 << buffer) ; + } + SCB_CleanInvalidateDCache(); + return (uint8_t *) pThisTxBuf; // now it points to the data field +} + +/** + * \brief Send Tx buffer. + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to buffer. + */ +void MCAN_SendTxDedBuffer( const MCan_ConfigType * mcanConfig, uint8_t buffer ) +{ + Mcan * mcan = mcanConfig->pMCan; + + if ( buffer < mcanConfig->nmbrTxDedBufElmts ) { + mcan->MCAN_TXBAR = ( 1 << buffer ); + } +} + +/** + * \brief Adds Message to TX Fifo / Queue + * \param mcanConfig Pointer to a MCAN instance. + * \param id Message ID. + * \param idType Type of ID + * \param dlc Type of dlc. + * \param data Pointer to data. + */ +uint32_t MCAN_AddToTxFifoQ( const MCan_ConfigType * mcanConfig, + uint32_t id, MCan_IdType idType, MCan_DlcType dlc, uint8_t * data ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t putIdx = 255; + uint32_t * pThisTxBuf = 0; + uint8_t * pTxData; + uint8_t cnt; + + // Configured for FifoQ and FifoQ not full? + if (( mcanConfig->nmbrTxFifoQElmts > 0 ) && + (( mcan->MCAN_TXFQS & MCAN_TXFQS_TFQF ) == 0 )) { + putIdx = ( mcan->MCAN_TXFQS & MCAN_TXFQS_TFQPI_Msk ) >> MCAN_TXFQS_TFQPI_Pos; + pThisTxBuf = mcanConfig->msgRam.pTxDedBuf + (putIdx * + (mcanConfig->txBufElmtSize & ELMT_SIZE_MASK)); + if ( idType == CAN_STD_ID ) + *pThisTxBuf++ = (( id << 18 ) & ( CAN_11_BIT_ID_MASK << 18 )); + else + *pThisTxBuf++ = BUFFER_XTD_MASK | ( id & CAN_29_BIT_ID_MASK ); + *pThisTxBuf++ = (uint32_t) dlc << 16; + pTxData = (uint8_t *) pThisTxBuf; + for ( cnt = 0; cnt < dlc ; cnt++ ) { + *pTxData++ = *data++; + } + /* enable transmit from buffer to set TC interrupt bit in IR, but + interrupt will not happen unless TC interrupt is enabled */ + mcan->MCAN_TXBTIE = ( 1 << putIdx); + // request to send + mcan->MCAN_TXBAR = ( 1 << putIdx ); + } + SCB_CleanInvalidateDCache(); + return putIdx; // now it points to the data field +} + +/** + * \brief Check if data transmitted from buffer/fifo/queue + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to data buffer. + */ +uint8_t MCAN_IsBufferTxd( const MCan_ConfigType * mcanConfig, uint8_t buffer ) +{ + Mcan * mcan = mcanConfig->pMCan; + + return ( mcan->MCAN_TXBTO & ( 1 << buffer ) ); +} + +/** + * \brief Configure RX Buffer Filter + * ID must match exactly for a RX Buffer Filter + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to data buffer. + * \param filter data of filter. + * \param idType Type of ID + */ +void MCAN_ConfigRxBufferFilter( const MCan_ConfigType * mcanConfig, + uint32_t buffer, uint32_t filter, uint32_t id, MCan_IdType idType) +{ + uint32_t * pThisRxFilt = 0; + + if ( buffer < mcanConfig->nmbrRxDedBufElmts ) { + if ( idType == CAN_STD_ID ) { + if (( filter < mcanConfig->nmbrStdFilts ) + && ( id <= CAN_11_BIT_ID_MASK )) { + pThisRxFilt = mcanConfig->msgRam.pStdFilts + filter; + // 1 word per filter + *pThisRxFilt = STD_FILT_SFEC_BUFFER | (id << 16) | + STD_FILT_SFID2_RX_BUFFER | buffer; + } + } else { + // extended ID + if (( filter < mcanConfig->nmbrExtFilts ) && + ( id <= CAN_29_BIT_ID_MASK )) { + pThisRxFilt = mcanConfig->msgRam.pExtFilts + (2 * filter); + // 2 words per filter + *pThisRxFilt++ = (uint32_t) EXT_FILT_EFEC_BUFFER | id; + *pThisRxFilt = EXT_FILT_EFID2_RX_BUFFER | buffer; + } + } + } + SCB_CleanInvalidateDCache(); +} + +/** + * \brief Configure Classic Filter + * Classic Filters direct accepted messages to a FIFO & include both a ID and + * a ID mask + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to data buffer. + * \param fifo fifo Number. + * \param filter data of filter. + * \param idType Type of ID + * \param mask Mask to be match + */ +void MCAN_ConfigRxClassicFilter( const MCan_ConfigType * mcanConfig, + MCan_FifoType fifo, uint8_t filter, uint32_t id, + MCan_IdType idType, uint32_t mask ) +{ + uint32_t * pThisRxFilt = 0; + uint32_t filterTemp; + + if ( idType == CAN_STD_ID ) { + if (( filter < mcanConfig->nmbrStdFilts ) && ( id <= CAN_11_BIT_ID_MASK ) + && ( mask <= CAN_11_BIT_ID_MASK )) { + pThisRxFilt = mcanConfig->msgRam.pStdFilts + filter; + // 1 word per filter + filterTemp = (uint32_t) STD_FILT_SFT_CLASSIC | (id << 16) | mask; + if ( fifo == CAN_FIFO_0 ) { + *pThisRxFilt = STD_FILT_SFEC_FIFO0 | filterTemp; + } else if ( fifo == CAN_FIFO_1 ) { + *pThisRxFilt = STD_FILT_SFEC_FIFO1 | filterTemp; + } + } else { + // extended ID + if (( filter < mcanConfig->nmbrExtFilts ) + && ( id <= CAN_29_BIT_ID_MASK ) + && ( mask <= CAN_29_BIT_ID_MASK )) { + pThisRxFilt = mcanConfig->msgRam.pExtFilts + (2 * filter); + // 2 words per filter + if ( fifo == CAN_FIFO_0 ) { + *pThisRxFilt++ = EXT_FILT_EFEC_FIFO0 | id; + } else if ( fifo == CAN_FIFO_0 ) { + *pThisRxFilt++ = EXT_FILT_EFEC_FIFO1 | id; + } + *pThisRxFilt = (uint32_t) EXT_FILT_EFT_CLASSIC | mask; + } + } + } + SCB_CleanInvalidateDCache(); +} + +/** + * \brief check if data received into buffer + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to data buffer. + */ +uint8_t MCAN_IsNewDataInRxDedBuffer( const MCan_ConfigType * mcanConfig, + uint8_t buffer ) +{ + Mcan * mcan = mcanConfig->pMCan; + + SCB_CleanInvalidateDCache(); + + if ( buffer < 32 ) { + return ( mcan->MCAN_NDAT1 & ( 1 << buffer )); + } else if ( buffer < 64 ) { + return ( mcan->MCAN_NDAT1 & ( 1 << (buffer - 32 ))); + } + else + return 0; +} + +/** + * \brief Get Rx buffer + * \param mcanConfig Pointer to a MCAN instance. + * \param buffer Pointer to data buffer. + * \param pRxMailbox Pointer to rx Mailbox. + */ +void MCAN_GetRxDedBuffer( const MCan_ConfigType * mcanConfig, + uint8_t buffer, Mailbox64Type * pRxMailbox ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t * pThisRxBuf = 0; + uint32_t tempRy; // temp copy of RX buffer word + uint8_t * pRxData; + uint8_t idx; + + SCB_CleanInvalidateDCache(); + + if ( buffer < mcanConfig->nmbrRxDedBufElmts ) { + pThisRxBuf = mcanConfig->msgRam.pRxDedBuf + + (buffer * (mcanConfig->rxBufElmtSize & ELMT_SIZE_MASK)); + tempRy = *pThisRxBuf++; // word R0 contains ID + if ( tempRy & BUFFER_XTD_MASK ) { + // extended ID? + pRxMailbox->info.id = tempRy & BUFFER_EXT_ID_MASK; + } else { + // standard ID + pRxMailbox->info.id = ( tempRy & BUFFER_STD_ID_MASK) >> 18; + } + tempRy = *pThisRxBuf++; // word R1 contains DLC & time stamp + pRxMailbox->info.length = (tempRy & BUFFER_DLC_MASK) >> 16; + pRxMailbox->info.timestamp = tempRy & BUFFER_RXTS_MASK; + // copy the data from the buffer to the mailbox + pRxData = (uint8_t *) pThisRxBuf; + for ( idx = 0; idx < pRxMailbox->info.length; idx++ ) + pRxMailbox->data[idx] = *pRxData++; + /* clear the new data flag for the buffer */ + if ( buffer < 32 ) { + mcan->MCAN_NDAT1 = ( 1 << buffer ); + } else { + mcan->MCAN_NDAT1 = ( 1 << (buffer - 32 )); + } + } +} + +/** + * \brief Get from the receive FIFO and place in a application mailbox + * \param mcanConfig Pointer to a MCAN instance. + * \param fifo Fifo Number + * \param pRxMailbox Pointer to rx Mailbox. + * \return: # of fifo entries at the start of the function + * 0 -> FIFO was empty at start + * 1 -> FIFO had 1 entry at start, but is empty at finish + * 2 -> FIFO had 2 entries at start, has 1 entry at finish + */ +uint32_t MCAN_GetRxFifoBuffer( const MCan_ConfigType * mcanConfig, + MCan_FifoType fifo, Mailbox64Type * pRxMailbox ) +{ + Mcan * mcan = mcanConfig->pMCan; + uint32_t * pThisRxBuf = 0; + uint32_t tempRy; // temp copy of RX buffer word + uint8_t * pRxData; + uint8_t idx; + uint32_t * fifo_ack_reg; + uint32_t get_index; + uint32_t fill_level; + uint32_t element_size; + + SCB_CleanInvalidateDCache(); + + // default: fifo empty + fill_level = 0; + + if ( fifo == CAN_FIFO_0 ) { + get_index = ( mcan->MCAN_RXF0S & MCAN_RXF0S_F0GI_Msk ) >> MCAN_RXF0S_F0GI_Pos; + fill_level = ( mcan->MCAN_RXF0S & MCAN_RXF0S_F0FL_Msk ) >> MCAN_RXF0S_F0FL_Pos; + pThisRxBuf = mcanConfig->msgRam.pRxFifo0; + element_size = mcanConfig->rxFifo0ElmtSize & ELMT_SIZE_MASK; + fifo_ack_reg = (uint32_t *) &mcan->MCAN_RXF0A; + } else if ( fifo == CAN_FIFO_1 ) { + get_index = ( mcan->MCAN_RXF1S & MCAN_RXF1S_F1GI_Msk ) >> MCAN_RXF1S_F1GI_Pos; + fill_level = ( mcan->MCAN_RXF1S & MCAN_RXF1S_F1FL_Msk ) >> MCAN_RXF1S_F1FL_Pos; + pThisRxBuf = mcanConfig->msgRam.pRxFifo1; + element_size = mcanConfig->rxFifo1ElmtSize & ELMT_SIZE_MASK; + fifo_ack_reg = (uint32_t *) &mcan->MCAN_RXF1A; + } + + if ( fill_level > 0 ) { + pThisRxBuf = pThisRxBuf + (get_index * element_size); + tempRy = *pThisRxBuf++; // word R0 contains ID + if ( tempRy & BUFFER_XTD_MASK ) { + // extended ID? + pRxMailbox->info.id = tempRy & BUFFER_EXT_ID_MASK; + } else { + // standard ID + pRxMailbox->info.id = ( tempRy & BUFFER_STD_ID_MASK) >> 18; + } + tempRy = *pThisRxBuf++; // word R1 contains DLC & timestamps + pRxMailbox->info.length = (tempRy & BUFFER_DLC_MASK) >> 16; + pRxMailbox->info.timestamp = tempRy & BUFFER_RXTS_MASK; + /* copy the data from the buffer to the mailbox */ + pRxData = (uint8_t *) pThisRxBuf; + for ( idx = 0; idx < pRxMailbox->info.length; idx++ ) + pRxMailbox->data[idx] = *pRxData++; + // acknowledge reading the fifo entry + *fifo_ack_reg = get_index; + /* return entries remaining in FIFO */ + } + return ( fill_level ); +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mcid_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mcid_dma.c new file mode 100644 index 000000000..08c38f70b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mcid_dma.c @@ -0,0 +1,906 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file + * + * Implement for SD/MMC low level commands. + * + * \sa \ref hsmci_module, \ref sdmmc_module + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include "sdmmc.h" + +#include + +/*---------------------------------------------------------------------------- + * Local constants + *----------------------------------------------------------------------------*/ +/** \addtorgoup mcid_defines + * @{*/ + +/** Enable MCI */ +#define MCI_ENABLE(pMciHw) HSMCI_Enable(pMciHw) +/** Disable MCI */ +#define MCI_DISABLE(pMciHw) HSMCI_Disable(pMciHw) +/** Reset MCI */ +#define MCI_RESET(pMciHw) HSMCI_Reset(pMciHw, 0) + +/** Return halfword(16-bit) count from byte count */ +#define toHWCOUNT(byteCnt) (((byteCnt)&0x1) ? (((byteCnt)/2)+1) : ((byteCnt)/2)) +/** Return word(32-bit) count from byte count */ +#define toWCOUNT(byteCnt) (((byteCnt)&0x3) ? (((byteCnt)/4)+1) : ((byteCnt)/4)) + + +/** Bit mask for status register errors. */ +#define STATUS_ERRORS ((uint32_t)(HSMCI_SR_UNRE \ + | HSMCI_SR_OVRE \ + | HSMCI_SR_ACKRCVE \ + | HSMCI_SR_CSTOE \ + | HSMCI_SR_DTOE \ + | HSMCI_SR_DCRCE \ + | HSMCI_SR_RTOE \ + | HSMCI_SR_RENDE \ + | HSMCI_SR_RCRCE \ + | HSMCI_SR_RDIRE \ + | HSMCI_SR_RINDE)) + +/** Bit mask for response errors */ +#define STATUS_ERRORS_RESP ((uint32_t)(HSMCI_SR_CSTOE \ + | HSMCI_SR_RTOE \ + | HSMCI_SR_RENDE \ + | HSMCI_SR_RCRCE \ + | HSMCI_SR_RDIRE \ + | HSMCI_SR_RINDE)) + +/** Bit mask for data errors */ +#define STATUS_ERRORS_DATA ((uint32_t)(HSMCI_SR_UNRE \ + | HSMCI_SR_OVRE \ + | HSMCI_SR_DTOE \ + | HSMCI_SR_DCRCE)) + +/** Max DMA size in a single transfer */ +#define MAX_DMA_SIZE (XDMAC_MAX_BT_SIZE & 0xFFFFFF00) + +/** SD/MMC memory Single block */ +#define _CMDR_SDMEM_SINGLE \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_SINGLE) +/** SD/MMC memory Multi block */ +#define _CMDR_SDMEM_MULTI \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_MULTIPLE) +/** SDIO byte transfer */ +#define _CMDR_SDIO_BYTE \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BYTE) +/** SDIO block transfer */ +#define _CMDR_SDIO_BLOCK \ + (HSMCI_CMDR_TRCMD_START_DATA | HSMCI_CMDR_TRTYP_BLOCK) + +/** @}*/ +/*--------------------------------------------------------------------------- + * Local types + *---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Local variable + *----------------------------------------------------------------------------*/ + +//#define MCID_DBG 0 +//static uint8_t bMcidDBG = 0; + +/** HAL for SD/MMC bus mode (MCI interface) */ +static sSdHalFunctions sdHal = { + (fSdmmcLock)MCID_Lock, + (fSdmmcRelease)MCID_Release, + (fSdmmcSendCommand)MCID_SendCmd, + (fSdmmcIOCtrl)MCID_IOCtrl +}; + +/*--------------------------------------------------------------------------- + * Internal functions + *---------------------------------------------------------------------------*/ + +/** \addtogroup mcid_functions + *@{ + */ + +/** + * Enable MCI peripheral access clock + */ +static uint8_t _PeripheralEnable(uint32_t id) +{ + if (PMC_IsPeriphEnabled(id)) return 0; + PMC_EnablePeripheral(id); + return 1; +} + +/** + * HSMCI DMA R/W prepare + */ +static uint32_t _MciDMAPrepare(sMcid *pMcid, uint8_t bRd) +{ + sXdmad *pXdmad = pMcid->pXdmad; + /* Allocate a channel */ + if (bRd) { + pMcid->dwDmaCh = XDMAD_AllocateChannel + (pXdmad, pMcid->bID, XDMAD_TRANSFER_MEMORY); + } else { + pMcid->dwDmaCh = XDMAD_AllocateChannel + (pXdmad, XDMAD_TRANSFER_MEMORY, pMcid->bID); + } + if (pMcid->dwDmaCh == XDMAD_ALLOC_FAILED) { + return SDMMC_ERROR_BUSY; + } + XDMAD_SetCallback(pXdmad, pMcid->dwDmaCh, NULL, NULL); + XDMAD_PrepareChannel( pXdmad, pMcid->dwDmaCh ); + return SDMMC_SUCCESS; +} + +/** + * HSMCI DMA R/W + * \return 1 if DMA started. + */ + +/* Linked lists for multi transfer buffer chaining structure instance. */ +static LinkedListDescriporView1 dmaLinkList[256]; + +static uint32_t _MciDMA(sMcid *pMcid, uint32_t bFByte, uint8_t bRd) +{ + Hsmci *pHw = pMcid->pMciHw; + sXdmad *pXdmad = pMcid->pXdmad; + sSdmmcCommand *pCmd = pMcid->pCmd; + sXdmadCfg xdmadRxCfg,xdmadTxCfg; + uint32_t xdmaCndc, xdmaInt; + uint32_t hsmciId; + uint8_t i; + uint32_t totalSize = pCmd->wNbBlocks * pCmd->wBlockSize; + uint32_t maxXSize; + uint32_t memAddress; + uint8_t bMByte; + + if (pMcid->dwXfrNdx >= totalSize) return 0; + /* Prepare DMA transfer */ + if(pCmd->wBlockSize != 1) { + pMcid->dwXSize = totalSize - pMcid->dwXfrNdx; + hsmciId = ID_HSMCI; + if (bRd) { + for ( i = 0; i < pCmd->wNbBlocks; i++) { + dmaLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 + | (( i == pCmd->wNbBlocks - 1) ? 0: XDMA_UBC_NDE_FETCH_EN) + | XDMA_UBC_NDEN_UPDATED + | pCmd->wBlockSize /4 ; + dmaLinkList[i].mbr_sa = (uint32_t)&(pHw->HSMCI_FIFO[i]); + dmaLinkList[i].mbr_da = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize]; + if ( i == pCmd->wNbBlocks - 1) + dmaLinkList[i].mbr_nda = 0; + else + dmaLinkList[i].mbr_nda = (uint32_t)&dmaLinkList[ i + 1 ]; + } + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_PER2MEM + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_WORD + | XDMAC_CC_SIF_AHB_IF1 + | XDMAC_CC_DIF_AHB_IF0 + | XDMAC_CC_SAM_FIXED_AM + | XDMAC_CC_DAM_INCREMENTED_AM + | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + (hsmciId, XDMAD_TRANSFER_RX )); + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 + | XDMAC_CNDC_NDE_DSCR_FETCH_EN + | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED + | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + + + if (XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, + &xdmadRxCfg, xdmaCndc, (uint32_t)&dmaLinkList[0], + XDMAC_CIE_LIE)) { + return 0; + } + // cache maintenance + SCB_CleanInvalidateDCache(); + + if (XDMAD_StartTransfer(pXdmad,pMcid->dwDmaCh)) { + return 0; + } + //Write + } else { + for ( i = 0; i < pCmd->wNbBlocks; i++){ + dmaLinkList[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 + |(( i == pCmd->wNbBlocks - 1) ? 0: XDMA_UBC_NDE_FETCH_EN) + | XDMA_UBC_NDEN_UPDATED + | pCmd->wBlockSize /4 ; + dmaLinkList[i].mbr_sa = (uint32_t)&pCmd->pData[i * pCmd->wBlockSize]; + dmaLinkList[i].mbr_da = (uint32_t)&(pHw->HSMCI_FIFO[i]); + if ( i == pCmd->wNbBlocks - 1) dmaLinkList[i].mbr_nda = 0; + else dmaLinkList[i].mbr_nda = (uint32_t)&dmaLinkList[ i + 1 ]; + } + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN + | XDMAC_CC_MBSIZE_SINGLE + | XDMAC_CC_DSYNC_MEM2PER + | XDMAC_CC_CSIZE_CHK_1 + | XDMAC_CC_DWIDTH_WORD + | XDMAC_CC_SIF_AHB_IF0 + | XDMAC_CC_DIF_AHB_IF1 + | XDMAC_CC_SAM_INCREMENTED_AM + | XDMAC_CC_DAM_FIXED_AM + | XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber(hsmciId, XDMAD_TRANSFER_TX )); + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 + | XDMAC_CNDC_NDE_DSCR_FETCH_EN + | XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED + | XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + if(XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, + &xdmadTxCfg, xdmaCndc, (uint32_t)&dmaLinkList[0], + XDMAC_CIE_LIE)){ + return 0; + } + // cache maintenance + SCB_CleanInvalidateDCache(); + + if (XDMAD_StartTransfer(pXdmad,pMcid->dwDmaCh)) { + return 0; + } + } + } else { + /* Memory address and alignment */ + memAddress = (uint32_t)&pCmd->pData[pMcid->dwXfrNdx]; + bMByte = bFByte ? 1 : (((memAddress & 0x3) || (totalSize & 0x3))); + /* P to M: Max size is P size */ + if (bRd) { + maxXSize = bFByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4); + } else { + /* M to P: Max size is M size */ + maxXSize = bMByte ? MAX_DMA_SIZE : (MAX_DMA_SIZE * 4); + } + /* Update index */ + pMcid->dwXSize = totalSize - pMcid->dwXfrNdx; + if (pMcid->dwXSize > maxXSize) { + pMcid->dwXSize = maxXSize; + } + /* Prepare DMA transfer */ + if (bRd) { + xdmadRxCfg.mbr_ubc = bFByte ? pMcid->dwXSize : toWCOUNT(pMcid->dwXSize); + xdmadRxCfg.mbr_sa = (uint32_t)&(pHw->HSMCI_RDR); + xdmadRxCfg.mbr_da = (uint32_t)memAddress; + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_PER2MEM| + XDMAC_CC_CSIZE_CHK_1 | + (bFByte ? XDMAC_CC_DWIDTH_BYTE : XDMAC_CC_DWIDTH_WORD) | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM; + xdmadRxCfg.mbr_bc = 0; + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadRxCfg, + 0, 0, xdmaInt); + } else { + xdmadTxCfg.mbr_ubc = toWCOUNT(pMcid->dwXSize); + xdmadTxCfg.mbr_sa = (uint32_t)memAddress; + xdmadTxCfg.mbr_da = (uint32_t)&(pHw->HSMCI_TDR); + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + (bFByte ? XDMAC_CC_DWIDTH_BYTE : XDMAC_CC_DWIDTH_WORD) | + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM; + xdmadTxCfg.mbr_bc = 0; + + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + XDMAD_ConfigureTransfer( pXdmad, pMcid->dwDmaCh, &xdmadTxCfg, + 0, 0, xdmaInt); + } + SCB_CleanInvalidateDCache(); + XDMAD_StartTransfer(pXdmad, pMcid->dwDmaCh); + } + return 1; +} + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * Reset MCI HW interface and disable it. + * \param keepSettings Keep old register settings, including + * _MR, _SDCR, _DTOR, _CSTOR, _DMA and _CFG. + */ +static void MCI_Reset(sMcid *pMci, uint8_t keepSettings) +{ + Hsmci *pMciHw = pMci->pMciHw; + + assert(pMci); + assert(pMci->pMciHw); + + HSMCI_Reset( pMciHw, keepSettings ); +} + +/** + * Configure the MCI CLKDIV in the MCI_MR register. The max. for MCI clock is + * MCK/2 and corresponds to CLKDIV = 0 + * \param pMci Pointer to the low level MCI driver. + * \param mciSpeed MCI clock speed in Hz, 0 will not change current speed. + * \param mck MCK to generate MCI Clock, in Hz + * \return The actual speed used, 0 for fail. + */ +static uint32_t MCI_SetSpeed( sMcid* pMci, uint32_t mciSpeed, uint32_t mck ) +{ + Hsmci *pMciHw = pMci->pMciHw; + uint32_t clkdiv; + assert(pMci); + assert(pMciHw); + + if((mck % mciSpeed) == 0) { + clkdiv = mck /mciSpeed; + } else { + clkdiv = ((mck + mciSpeed)/mciSpeed); + } + mciSpeed = mck / clkdiv; + + /* Modify MR */ + HSMCI_DivCtrl( pMciHw, clkdiv, 0x7); + return (mciSpeed); +} + +/** +*/ +static void _FinishCmd( sMcid* pMcid, uint8_t bStatus ) +{ + sSdmmcCommand *pCmd = pMcid->pCmd; + sXdmad *pXdmad = pMcid->pXdmad; + //uint32_t memAddress; + /* Release DMA channel (if used) */ + if (pMcid->dwDmaCh != XDMAD_ALLOC_FAILED) { + if (XDMAD_FreeChannel(pXdmad, pMcid->dwDmaCh)) { + TRACE_ERROR(" Can't free channel \n\r" ); + TRACE_DEBUG(" Channel is in %d state\n\r", + pXdmad->XdmaChannels[pMcid->dwDmaCh].state ); + } + pMcid->dwDmaCh = XDMAD_ALLOC_FAILED; + } + /* Release command */ + pMcid->pCmd = NULL; + pMcid->bState = MCID_LOCKED; + pCmd->bStatus = bStatus; + /* Invoke callback */ + if (pCmd->fCallback) { + (pCmd->fCallback)(pCmd->bStatus, pCmd->pArg); + } +} + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * Select MCI slot. + */ +void MCID_SetSlot(Hsmci *pMci, uint8_t slot) + +{ + HSMCI_SetSlot(pMci, slot); +} + +/** + * Initialize MCI driver. + */ +void MCID_Init(sMcid *pMcid, + Hsmci *pMci, uint8_t bID, uint32_t dwMck, + sXdmad *pXdmad, + uint8_t bPolling) +{ + uint16_t clkDiv; + + assert(pMcid); + assert(pMci); + + /* Initialize driver struct */ + pMcid->pMciHw = pMci; + pMcid->pCmd = NULL; + + pMcid->pXdmad = pXdmad; + pMcid->dwDmaCh = XDMAD_ALLOC_FAILED; + pMcid->dwXfrNdx = 0; + + pMcid->dwMck = dwMck; + + pMcid->bID = bID; + pMcid->bPolling = bPolling; + pMcid->bState = MCID_IDLE; + + _PeripheralEnable( bID ); + + MCI_RESET( pMci ); + MCI_DISABLE ( pMci ); + HSMCI_DisableIt( pMci, 0xFFFFFFFF ); + HSMCI_ConfigureDataTO( pMci, HSMCI_DTOR_DTOCYC(0xFF) + |HSMCI_DTOR_DTOMUL_1048576 ); + HSMCI_ConfigureCompletionTO( pMci , HSMCI_CSTOR_CSTOCYC(0xFF) + |HSMCI_CSTOR_CSTOMUL_1048576 ); + /* Set the Mode Register: 400KHz */ + clkDiv = (dwMck / (MCI_INITIAL_SPEED << 1)) - 1; + HSMCI_ConfigureMode( pMci, (clkDiv | HSMCI_MR_PWSDIV(0x7)) ); + + HSMCI_Enable( pMci ); + HSMCI_Configure( pMci, HSMCI_CFG_FIFOMODE | HSMCI_CFG_FERRCTRL ); + /* Enable DMA */ + HSMCI_EnableDma( pMci, 1 ); + //_PeripheralDisable( bID ); +} + +/** + * Lock the MCI driver for slot N access + */ +uint32_t MCID_Lock(sMcid *pMcid, uint8_t bSlot) +{ + Hsmci *pHw = pMcid->pMciHw; + uint32_t sdcr; + + assert(pMcid); + assert(pMcid->pMciHw); + + if (bSlot > 0) { + return SDMMC_ERROR_PARAM; + } + if (pMcid->bState >= MCID_LOCKED) { + return SDMMC_ERROR_LOCKED; + } + pMcid->bState = MCID_LOCKED; + sdcr = pHw->HSMCI_SDCR & ~(uint32_t)HSMCI_SDCR_SDCSEL_Msk; + pHw->HSMCI_SDCR = sdcr | (bSlot << HSMCI_SDCR_SDCSEL_Pos); + return SDMMC_OK; +} + +/** + * Release the driver. + */ +uint32_t MCID_Release(sMcid *pMcid) +{ + assert(pMcid); + + if (pMcid->bState >= MCID_CMD) { + return SDMMC_ERROR_BUSY; + } + pMcid->bState = MCID_IDLE; + return SDMMC_OK; +} + +/** + * SD/MMC command. + */ +uint32_t MCID_SendCmd(sMcid *pMcid, void *pCommand) +{ + Hsmci *pHw = pMcid->pMciHw; + sSdmmcCommand *pCmd = pCommand; + uint32_t mr, ier; + uint32_t cmdr; + + assert(pMcid); + assert(pMcid->pMciHw); + assert(pCmd); + //printf("cmd = %d \n\r",pCmd->bCmd); + if (!MCID_IsCmdCompleted(pMcid)) + { + return SDMMC_ERROR_BUSY; + } + pMcid->bState = MCID_CMD; + pMcid->pCmd = pCmd; + + //_PeripheralEnable(pMcid->bID); + MCI_DISABLE(pHw); + mr = HSMCI_GetMode(pHw) & (~(uint32_t)(HSMCI_MR_WRPROOF | + HSMCI_MR_RDPROOF |HSMCI_MR_FBYTE)); + /* Special: PowerON Init */ + if (pCmd->cmdOp.wVal == SDMMC_CMD_POWERONINIT){ + HSMCI_ConfigureMode(pHw, mr); + ier = HSMCI_IER_XFRDONE; + } else if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR) { + /* Normal command: idle the bus */ + HSMCI_ConfigureMode(pHw, mr); + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP; + } + /* No data transfer */ + else if ((pCmd->cmdOp.wVal & SDMMC_CMD_CNODATA(0xF)) == SDMMC_CMD_CNODATA(0)) { + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_RESP; + /* R3 response, no CRC */ + if (pCmd->cmdOp.bmBits.respType == 3) { + ier &= ~(uint32_t)HSMCI_IER_RCRCE; + } + } else if (pCmd->wNbBlocks == 0 || pCmd->pData == 0) { + /* Data command but no following */ + HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF + | HSMCI_MR_RDPROOF); + HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks); + ier = HSMCI_IER_CMDRDY | STATUS_ERRORS_RESP; + } else { + /* Command with data */ + /* Setup block size */ + if (pCmd->cmdOp.bmBits.sendCmd) { + HSMCI_ConfigureTransfer(pHw, pCmd->wBlockSize, pCmd->wNbBlocks); + } + /* Block size is 0, force byte */ + if (pCmd->wBlockSize == 0) + pCmd->wBlockSize = 1; + + /* Force byte transfer */ + if (pCmd->wBlockSize & 0x3) { + mr |= HSMCI_MR_FBYTE; + } + /* Set block size & MR */ + HSMCI_ConfigureMode(pHw, mr | HSMCI_MR_WRPROOF + | HSMCI_MR_RDPROOF + | (pCmd->wBlockSize << 16)); + SCB_CleanInvalidateDCache(); + /* DMA write */ + if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_TX) { + if (_MciDMAPrepare(pMcid, 0)) { + _FinishCmd(pMcid, SDMMC_ERROR_BUSY); + return SDMMC_ERROR_BUSY; + } + _MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),0); + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA; + if( pCmd->wNbBlocks > 1 ) ier |= HSMCI_IER_FIFOEMPTY; + } else { + if (_MciDMAPrepare(pMcid, 1)) { + _FinishCmd(pMcid, SDMMC_ERROR_BUSY); + return SDMMC_ERROR_BUSY; + } + _MciDMA(pMcid, (mr & HSMCI_MR_FBYTE),1); + ier = HSMCI_IER_XFRDONE | STATUS_ERRORS_DATA; + if( pCmd->wNbBlocks > 1 ) ier |= HSMCI_IER_FIFOEMPTY; + } + } + MCI_ENABLE(pHw); + if (pCmd->cmdOp.wVal & (SDMMC_CMD_bmPOWERON | SDMMC_CMD_bmCOMMAND)) { + cmdr = pCmd->bCmd; + + if (pCmd->cmdOp.bmBits.powerON) { + cmdr |= (HSMCI_CMDR_OPDCMD | HSMCI_CMDR_SPCMD_INIT); + } + if (pCmd->cmdOp.bmBits.odON) { + cmdr |= HSMCI_CMDR_OPDCMD; + } + if (pCmd->cmdOp.bmBits.sendCmd) { + cmdr |= HSMCI_CMDR_MAXLAT; + } + switch(pCmd->cmdOp.bmBits.xfrData) { + case SDMMC_CMD_TX: + if (pCmd->cmdOp.bmBits.ioCmd) { + cmdr |= (pCmd->wBlockSize == 1) ? + _CMDR_SDIO_BYTE : + _CMDR_SDIO_BLOCK; + } else { + cmdr |= (pCmd->wNbBlocks == 1) ? + _CMDR_SDMEM_SINGLE : + _CMDR_SDMEM_MULTI; + } + break; + + case SDMMC_CMD_RX: + if (pCmd->cmdOp.bmBits.ioCmd) { + cmdr |= HSMCI_CMDR_TRDIR_READ + |((pCmd->wBlockSize == 1) ? + _CMDR_SDIO_BYTE : + _CMDR_SDIO_BLOCK) ; + } else { + cmdr |= HSMCI_CMDR_TRDIR_READ + |((pCmd->wNbBlocks == 1) ? + _CMDR_SDMEM_SINGLE : + _CMDR_SDMEM_MULTI) ; + } + break; + + case SDMMC_CMD_STOPXFR: + cmdr |= HSMCI_CMDR_TRCMD_STOP_DATA; + break; + } + + switch(pCmd->cmdOp.bmBits.respType) { + case 3: case 4: + /* ignore CRC error */ + ier &= ~(uint32_t)HSMCI_IER_RCRCE; + case 1: case 5: case 6: case 7: + cmdr |= HSMCI_CMDR_RSPTYP_48_BIT; + break; + case 2: + cmdr |= HSMCI_CMDR_RSPTYP_136_BIT; + break; + /* No response, ignore RTOE */ + default: + ier &= ~(uint32_t)HSMCI_IER_RTOE; + } + + pHw->HSMCI_ARGR = pCmd->dwArg; + pHw->HSMCI_CMDR = cmdr; + } + + /* Ignore CRC error for R3 & R4 */ + if (pCmd->cmdOp.bmBits.xfrData == SDMMC_CMD_STOPXFR) { + ier &= ~STATUS_ERRORS_DATA; + } + /* Enable status flags */ + HSMCI_EnableIt(pHw, ier); + return SDMMC_OK; +} + +static uint32_t dwMsk; +/** + * Process pending events on the given MCI driver. + */ +void MCID_Handler(sMcid *pMcid) +{ + Hsmci *pHw = pMcid->pMciHw; + sSdmmcCommand *pCmd = pMcid->pCmd; + //uint32_t dwSr, dwMsk, dwMaskedSr; + uint32_t dwSr, dwMaskedSr; + assert(pMcid); + assert(pMcid->pMciHw); + + /* Do nothing if no pending command */ + if (pCmd == NULL) { + if (pMcid->bState >= MCID_CMD) { + pMcid->bState = MCID_LOCKED; + } + return; + } + + /* Read status */ + dwSr = HSMCI_GetStatus(pHw); + dwMsk = HSMCI_GetItMask(pHw); + dwMaskedSr = dwSr & dwMsk; + /* Check errors */ + if (dwMaskedSr & STATUS_ERRORS) { + if (dwMaskedSr & HSMCI_SR_RTOE) { + pCmd->bStatus = SDMMC_ERROR_NORESPONSE; + } + if (pCmd->bCmd != 12) pMcid->bState = MCID_ERROR; + //pMcid->bState = MCID_ERROR; + } + dwMsk &= ~STATUS_ERRORS; + + /* Check command complete */ + if (dwMaskedSr & HSMCI_SR_CMDRDY) { + TRACE_DEBUG("HSMCI_SR_CMDRDY \n\r"); + HSMCI_DisableIt(pHw, HSMCI_IDR_CMDRDY); + dwMsk &= ~(uint32_t)HSMCI_IMR_CMDRDY; + } + + /* Check if not busy */ + if (dwMaskedSr & HSMCI_SR_NOTBUSY) { + TRACE_DEBUG("NOTBUSY "); + HSMCI_DisableIt(pHw, HSMCI_IDR_NOTBUSY); + dwMsk &= ~(uint32_t)HSMCI_IMR_NOTBUSY; + } + /* Check if TX ready */ + if (dwMaskedSr & HSMCI_SR_TXRDY) { + TRACE_DEBUG("TXRDY "); + dwMsk &= ~(uint32_t)HSMCI_IMR_TXRDY; + } + /* Check if FIFO empty (all data sent) */ + if (dwMaskedSr & HSMCI_SR_FIFOEMPTY) { + /* Disable FIFO empty */ + HSMCI_DisableIt(pHw, HSMCI_IDR_FIFOEMPTY); + dwMsk &= ~(uint32_t)HSMCI_IMR_FIFOEMPTY; + TRACE_DEBUG("FIFOEMPTY %x \n\r",dwMsk); + } + + /* Check if DMA finished */ + if (dwMaskedSr & HSMCI_SR_XFRDONE) { + HSMCI_DisableIt(pHw, HSMCI_IDR_XFRDONE); + dwMsk &= ~(uint32_t)HSMCI_IMR_XFRDONE; + TRACE_DEBUG("HSMCI_SR_XFRDONE %x \n\r",dwMsk); + } + + /* All none error mask done, complete the command */ + if (0 == dwMsk || pMcid->bState == MCID_ERROR) { + /* Error reset */ + if (pMcid->bState == MCID_ERROR) { + MCI_Reset(pMcid, 1); + } else { + pCmd->bStatus = SDMMC_SUCCESS; + + if (pCmd->pResp) { + uint8_t bRspSize, i; + switch(pCmd->cmdOp.bmBits.respType) { + case 1: case 3: case 4: case 5: case 6: case 7: + bRspSize = 1; + break; + + case 2: + bRspSize = 4; + break; + + default: + bRspSize = 0; + } + for (i = 0; i < bRspSize; i ++) { + pCmd->pResp[i] = HSMCI_GetResponse(pHw); + } + } + } + /* Disable interrupts */ + HSMCI_DisableIt(pHw, HSMCI_GetItMask(pHw)); + /* Disable peripheral */ + //_PeripheralDisable(pMcid->bID); + /* Command is finished */ + _FinishCmd(pMcid, pCmd->bStatus); + } +} + +/** + * Cancel pending SD/MMC command. + */ +uint32_t MCID_CancelCmd(sMcid *pMcid) +{ + if (pMcid->bState == MCID_IDLE) { + return SDMMC_ERROR_STATE; + } + if (pMcid->bState == MCID_CMD) { + /* Cancel ... */ + MCI_Reset(pMcid, 1); + /* Command is finished */ + _FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL); + } + return SDMMC_OK; +} + +/** + * Reset MCID and disable HW + */ +void MCID_Reset(sMcid * pMcid) +{ + Hsmci *pHw = pMcid->pMciHw; + + MCID_CancelCmd(pMcid); + + //_PeripheralEnable(pMcid->bID); + + /* Disable */ + MCI_DISABLE(pHw); + /* MR reset */ + HSMCI_ConfigureMode(pHw, HSMCI_GetMode(pHw) & (HSMCI_MR_CLKDIV_Msk + | HSMCI_MR_PWSDIV_Msk)); + /* BLKR reset */ + HSMCI_ConfigureTransfer(pHw, 0, 0); + + /* Cancel ... */ + MCI_Reset(pMcid, 1); + //_PeripheralDisable(pMcid->bID); + + if (pMcid->bState == MCID_CMD) { + /* Command is finished */ + _FinishCmd(pMcid, SDMMC_ERROR_USER_CANCEL); + } +} + +/** + * Check if the command is finished + */ +uint32_t MCID_IsCmdCompleted(sMcid *pMcid) +{ + sSdmmcCommand *pCmd = pMcid->pCmd; + + if (pMcid->bPolling) { + MCID_Handler(pMcid); + } + if (pMcid->bState == MCID_CMD) { + return 0; + } + if (pCmd) { + return 0; + } + return 1; +} + +/** + * IO control functions + */ +uint32_t MCID_IOCtrl(sMcid *pMcid, uint32_t bCtl, uint32_t param) +{ + Hsmci *pMciHw = pMcid->pMciHw; + assert(pMcid); + assert(pMcid->pMciHw); + + //mciDis = _PeripheralEnable(pMcid->bID); + + switch (bCtl) { + case SDMMC_IOCTL_BUSY_CHECK: + *(uint32_t*)param = !MCID_IsCmdCompleted(pMcid); + break; + + case SDMMC_IOCTL_POWER: + return SDMMC_ERROR_NOT_SUPPORT; + + case SDMMC_IOCTL_RESET: + MCID_Reset(pMcid); + return SDMMC_SUCCESS; + + case SDMMC_IOCTL_CANCEL_CMD: + return MCID_CancelCmd(pMcid); + + case SDMMC_IOCTL_SET_CLOCK: + *(uint32_t*)param = MCI_SetSpeed(pMcid, + *(uint32_t*)param, + pMcid->dwMck); + break; + + case SDMMC_IOCTL_SET_HSMODE: + HSMCI_HsEnable( pMciHw, *(uint32_t*)param ); + *(uint32_t*)param = HSMCI_IsHsEnabled( pMciHw ); + + break; + + case SDMMC_IOCTL_SET_BUSMODE: + HSMCI_SetBusWidth( pMciHw, *(uint32_t*)param ); + break; + + case SDMMC_IOCTL_GET_BUSMODE: + //*(uint32_t*)param = 8; /* Max 4-bit bus */ + break; + + case SDMMC_IOCTL_GET_HSMODE: + *(uint32_t*)param = 1; /* Supported */ + break; + + default: + return SDMMC_ERROR_NOT_SUPPORT; + } + return SDMMC_OK; +} + +/** + * Initialize the SD/MMC card driver structure for SD/MMC bus mode + * \note defined in SD/MMC bus mode low level (Here uses MCI interface) + */ +void SDD_InitializeSdmmcMode(sSdCard * pSd,void * pDrv,uint8_t bSlot) +{ + SDD_Initialize(pSd, pDrv, bSlot, &sdHal); +} + +/**@}*/ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mediaLB.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mediaLB.c new file mode 100644 index 000000000..d9f1852a2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mediaLB.c @@ -0,0 +1,58 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup mediaLB Working with MediaLB + * \ingroup peripherals_module + * The mediaLB driver provides the interface to configure and use the peripheral. + * + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of mediaLB controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mpu.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mpu.c new file mode 100644 index 000000000..290602650 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/mpu.c @@ -0,0 +1,168 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/** + * \addtogroup mmu MMU Initialization + * + * \section Usage + * + * Translation Look-aside Buffers (TLBs) are an implementation technique that + * caches translations or translation table entries. TLBs avoid the requirement + * for every memory access to perform a translation table lookup. + * The ARM architecture does not specify the exact form of the TLB structures + * for any design. In a similar way to the requirements for caches, the + * architecture only defines certain principles for TLBs: + * + * The MMU supports memory accesses based on memory sections or pages: + * Super-sections Consist of 16MB blocks of memory. Support for Super sections + * is optional. + * -# Sections Consist of 1MB blocks of memory. + * -# Large pages Consist of 64KB blocks of memory. + * -# Small pages Consist of 4KB blocks of memory. + * + * Access to a memory region is controlled by the access permission bits and + * the domain field in the TLB entry. + * Memory region attributes + * Each TLB entry has an associated set of memory region attributes. These + * control accesses to the caches, + * how the write buffer is used, and if the memory region is Shareable and + * therefore must be kept coherent. + * + * Related files:\n + * \ref mmu.c\n + * \ref mmu.h \n + */ + +/*-------------------------------------------------------------------------- */ +/* Headers */ +/*-------------------------------------------------------------------------- */ +#include + +/*---------------------------------------------------------------------------- + * Exported functions + + *----------------------------------------------------------------------------*/ +/** + * \brief Enables the MPU module. + * + * \param dwMPUEnable Enable/Disable the memory region. + */ +void MPU_Enable( uint32_t dwMPUEnable ) +{ + MPU->CTRL = dwMPUEnable ; +} + +/** + * \brief Set active memory region. + * + * \param dwRegionNum The memory region to be active. + */ +void MPU_SetRegionNum( uint32_t dwRegionNum ) +{ + MPU->RNR = dwRegionNum; +} + +/** + * \brief Disable the current active region. + */ +extern void MPU_DisableRegion( void ) +{ + MPU->RASR &= 0xfffffffe; +} + +/** + * \brief Setup a memory region. + * + * \param dwRegionBaseAddr Memory region base address. + * \param dwRegionAttr Memory region attributes. + */ +void MPU_SetRegion( uint32_t dwRegionBaseAddr, uint32_t dwRegionAttr ) +{ + MPU->RBAR = dwRegionBaseAddr; + MPU->RASR = dwRegionAttr; +} + + +/** + * \brief Calculate region size for the RASR. + */ +uint32_t MPU_CalMPURegionSize( uint32_t dwActualSizeInBytes ) +{ + uint32_t dwRegionSize = 32; + uint32_t dwReturnValue = 4; + + while( dwReturnValue < 31 ) { + if( dwActualSizeInBytes <= dwRegionSize ) { + break; + } else { + dwReturnValue++; + } + dwRegionSize <<= 1; + } + + return ( dwReturnValue << 1 ); +} + + +/** + * \brief Update MPU regions. + * + * \return Unused (ANSI-C compatibility). + */ +void MPU_UpdateRegions( uint32_t dwRegionNum, uint32_t dwRegionBaseAddr, + uint32_t dwRegionAttr) +{ + + /* Disable interrupt */ + __disable_irq(); + + /* Clean up data and instruction buffer */ + __DSB(); + __ISB(); + + /* Set active region */ + MPU_SetRegionNum(dwRegionNum); + + /* Disable region */ + MPU_DisableRegion(); + + /* Update region attribute */ + MPU_SetRegion( dwRegionBaseAddr, dwRegionAttr); + + /* Clean up data and instruction buffer to make the new region taking + effect at once */ + __DSB(); + __ISB(); + + /* Enable the interrupt */ + __enable_irq(); +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio.c new file mode 100644 index 000000000..fe91ef07e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio.c @@ -0,0 +1,468 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled by + * peripheral A. Optionally, the corresponding internal pull-up(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralA( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PUER = mask; + } else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] &= (~mask & abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] &= (~mask & abcdsr); + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled + * by peripheral B. Optionally, the corresponding internal pull-up(s) can be + * enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralB( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PUER = mask; + } else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] = (mask | abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] &= (~mask & abcdsr); + + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled + * by peripheral C. Optionally, the corresponding internal pull-up(s) can be + * enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralC( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PUER = mask; + } else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] &= (~mask & abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] = (mask | abcdsr); + + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as being controlled + * by peripheral D. Optionally, the corresponding internal pull-up(s) can be + * enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask of one or more pin(s) to configure. + * \param enablePullUp Indicates if the pin(s) internal pull-up shall be + * configured. + */ +static void PIO_SetPeripheralD( + Pio *pio, + unsigned int mask, + unsigned char enablePullUp) +{ + unsigned int abcdsr; + /* Disable interrupts on the pin(s) */ + pio->PIO_IDR = mask; + + /* Enable the pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PUER = mask; + } else { + pio->PIO_PUDR = mask; + } + + abcdsr = pio->PIO_ABCDSR[0]; + pio->PIO_ABCDSR[0] = (mask | abcdsr); + abcdsr = pio->PIO_ABCDSR[1]; + pio->PIO_ABCDSR[1] = (mask | abcdsr); + + pio->PIO_PDR = mask; +} + +/** + * \brief Configures one or more pin(s) or a PIO controller as inputs. Optionally, + * the corresponding internal pull-up(s) and glitch filter(s) can be enabled. + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask indicating which pin(s) to configure as input(s). + * \param enablePullUp Indicates if the internal pull-up(s) must be enabled. + * \param enableFilter Indicates if the glitch filter(s) must be enabled. + */ +static void PIO_SetInput( + Pio *pio, + unsigned int mask, + unsigned char attribute) +{ + /* Disable interrupts */ + pio->PIO_IDR = mask; + + /* Enable pull-up(s) if necessary */ + if (attribute & PIO_PULLUP) + pio->PIO_PUER = mask; + else + pio->PIO_PUDR = mask; + + /* Enable Input Filter if necessary */ + if (attribute & (PIO_DEGLITCH | PIO_DEBOUNCE)) + pio->PIO_IFER = mask; + else + pio->PIO_IFDR = mask; + + /* Enable de-glitch or de-bounce if necessary */ + if (attribute & PIO_DEGLITCH) { + pio->PIO_IFSCDR = mask; + } else { + if (attribute & PIO_DEBOUNCE) { + pio->PIO_IFSCER = mask; + } + } + /* Configure pin as input */ + pio->PIO_ODR = mask; + pio->PIO_PER = mask; +} + +/** + * \brief Configures one or more pin(s) of a PIO controller as outputs, with the + * given default value. Optionally, the multi-drive feature can be enabled + * on the pin(s). + * + * \param pio Pointer to a PIO controller. + * \param mask Bitmask indicating which pin(s) to configure. + * \param defaultValue Default level on the pin(s). + * \param enableMultiDrive Indicates if the pin(s) shall be configured as + * open-drain. + * \param enablePullUp Indicates if the pin shall have its pull-up activated. + */ +static void PIO_SetOutput( + Pio *pio, + unsigned int mask, + unsigned char defaultValue, + unsigned char enableMultiDrive, + unsigned char enablePullUp) +{ + /* Disable interrupts */ + pio->PIO_IDR = mask; + + /* Enable pull-up(s) if necessary */ + if (enablePullUp) { + pio->PIO_PUER = mask; + } else { + pio->PIO_PUDR = mask; + } + + /* Enable multi-drive if necessary */ + if (enableMultiDrive) { + pio->PIO_MDER = mask; + } else { + pio->PIO_MDDR = mask; + } + + /* Set default value */ + if (defaultValue) { + pio->PIO_SODR = mask; + } else { + pio->PIO_CODR = mask; + } + /* Configure pin(s) as output(s) */ + pio->PIO_OER = mask; + pio->PIO_PER = mask; +} + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a list of Pin instances, each of which can either hold a + * single pin or a group of pins, depending on the mask value; all pins are + * configured by this function. The size of the array must also be provided and + * is easily computed using PIO_LISTSIZE whenever its length is not known in + * advance. + * + * \param list Pointer to a list of Pin instances. + * \param size Size of the Pin list (calculated using PIO_LISTSIZE). + * + * \return 1 if the pins have been configured properly; otherwise 0. + */ +uint8_t PIO_Configure( const Pin *list, uint32_t size ) +{ + /* Configure pins */ + while ( size > 0 ) { + switch ( list->type ) { + case PIO_PERIPH_A: + PIO_SetPeripheralA(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_B: + PIO_SetPeripheralB(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_C: + PIO_SetPeripheralC(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + case PIO_PERIPH_D: + PIO_SetPeripheralD(list->pio, + list->mask, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + case PIO_INPUT: +#ifndef __FPGA + PMC_EnablePeripheral(list->id); +#endif + PIO_SetInput(list->pio, + list->mask, + list->attribute); + break; + + case PIO_OUTPUT_0: + case PIO_OUTPUT_1: + PIO_SetOutput(list->pio, + list->mask, + (list->type == PIO_OUTPUT_1), + (list->attribute & PIO_OPENDRAIN) ? 1 : 0, + (list->attribute & PIO_PULLUP) ? 1 : 0); + break; + + default: return 0; + } + list++; + size--; + } + return 1; +} + +/** + * \brief Sets a high output level on all the PIOs defined in the given Pin + * instance. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will memorize the value they are changed to outputs. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ +void PIO_Set(const Pin *pin) +{ + pin->pio->PIO_SODR = pin->mask; +} + +/** + * \brief Sets a low output level on all the PIOs defined in the given Pin + * instance. + * This has no immediate effects on PIOs that are not output, but the PIO + * controller will memorize the value they are changed to outputs. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ +void PIO_Clear(const Pin *pin) +{ + pin->pio->PIO_CODR = pin->mask; +} + +/** + * \brief Returns 1 if one or more PIO of the given Pin instance currently have + * a high level; otherwise returns 0. This method returns the actual value that + * is being read on the pin. To return the supposed output value of a pin, use + * PIO_GetOutputDataStatus() instead. + * + * \param pin Pointer to a Pin instance describing one or more pins. + * + * \return 1 if the Pin instance contains at least one PIO that currently has + * a high level; otherwise 0. + */ +unsigned char PIO_Get( const Pin *pin ) +{ + unsigned int reg ; + + if ( (pin->type == PIO_OUTPUT_0) || (pin->type == PIO_OUTPUT_1) ) { + reg = pin->pio->PIO_ODSR ; + } else { + reg = pin->pio->PIO_PDSR ; + } + + if ( (reg & pin->mask) == 0 ) { + return 0 ; + } else { + return 1 ; + } +} + +/** + * \brief Returns 1 if one or more PIO of the given Pin are configured to output + * a high level (even if they are not output). + * To get the actual value of the pin, use PIO_Get() instead. + * + * \param pin Pointer to a Pin instance describing one or more pins. + * + * \return 1 if the Pin instance contains at least one PIO that is configured + * to output a high level; otherwise 0. + */ +unsigned char PIO_GetOutputDataStatus(const Pin *pin) +{ + if ((pin->pio->PIO_ODSR & pin->mask) == 0) { + return 0; + } else { + return 1; + } +} + +/** + * \brief Configures Glitch or Denouncing filter for input. + * + * \param pin Pointer to a Pin instance describing one or more pins. + * \param cuttoff Cut off frequency for denounce filter. + */ +void PIO_SetDebounceFilter( const Pin *pin, uint32_t cuttoff ) +{ + Pio *pio = pin->pio; + + pio->PIO_IFSCER = pin->mask; /* set Denouncing, 0 bit field no effect */ + pio->PIO_SCDR = ((32678/(2*(cuttoff))) - 1) & 0x3FFF; + /* the lowest 14 bits work */ +} + +/** + * \brief Enable write protect. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ +void PIO_EnableWriteProtect( const Pin *pin ) +{ + Pio *pio = pin->pio; + + pio->PIO_WPMR = ( PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_EN ); +} + +/** + * \brief Disable write protect. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ + +void PIO_DisableWriteProtect( const Pin *pin ) +{ + Pio *pio = pin->pio; + + pio->PIO_WPMR = ( PIO_WPMR_WPKEY_VALID | PIO_WPMR_WPEN_DIS ); +} + +/** + * \brief Get write protect violation information. + * + * \param pin Pointer to a Pin instance describing one or more pins. + */ +uint32_t PIO_GetWriteProtectViolationInfo( const Pin * pin ) +{ + Pio *pio = pin->pio; + return (pio->PIO_WPSR); +} + +/** + * \brief Set pin type + * the pin is controlled by the corresponding peripheral (A, B, C, D,E) + * \param pin Pointer to a Pin instance describing one or more pins. + * \param pinType PIO_PERIPH_A, PIO_PERIPH_B, ... + */ +void PIO_SetPinType( Pin * pin, uint8_t pinType) +{ + pin->type = pinType; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio_capture.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio_capture.c new file mode 100644 index 000000000..612ee1088 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio_capture.c @@ -0,0 +1,261 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup pio_capture_module Working with PIO Parallel Capture Mode + * \ingroup peripherals_module + * The PIO Parallel Capture Mode driver provides the interface to configure + * and use the PIO Parallel Capture Mode peripheral.\n + * + * The PIO Controller integrates an interface able to read data from a CMOS digital + * image sensor, a high-speed parallel ADC, a DSP synchronous port in synchronous + * mode, etc.... For better understanding and to ease reading, the following + * description uses an example with a CMOS digital image sensor + * + * To use the PIO Parallel Capture, the user has to follow these few steps: + *
      + *
    • Enable PIOA peripheral clock
      • + *
    • Configure the PDC
      • + *
    • Configure the PIO Capture interrupt
      • + *
    • Enable the PDC
      • + *
    • Enable the PIO Capture
      • + *
    • Wait for interrupt
      • + *
    • Disable the interrupt
      • + *
    • Read the DATA
      • + *
    + * + * For more accurate information, please look at the PIO Parallel Capture Mode + * section of the Datasheet. + * + * API Usage: + * + * -# Configurate the interrupt for PIOA, can be done by + * PIO_InitializeInterrupts() + * -# Initialize the PIO Parallel Capture API by filing the SpioCaptureInit + * structure + * options: + * - alwaysSampling: for sample data with or without take in account + * ENABLE pins. + * - halfSampling: for sample all data or only one time out of two + * -# Call PIO_CaptureInit() for init and enable the PDC, init the PIO capture. + * -# Call PIO_CaptureEnable() for enable the PIO Parallel Capture. + * -# When an interrupt is received, the PIO_CaptureHandler() is call and the + * respective callback is launch. + * -# When the transfer is complete, the user need to disable interrupt with + * PIO_CaptureDisableIt(). Otherwise, the PDC will send an interrupt. + * -# The data receive by the PIO Parallel Capture is inside the buffer passed + * in the PIO_CaptureInit(). + * + * Related files :\n + * \ref pio_capture.c\n + * \ref pio_capture.h\n + */ +/*@{*/ +/*@}*/ +/** + * \file + * + * Implementation of PIO Parallel Capture. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#define PIO_PCISR_RXBUFF (0x1u<<3) +#define PIO_PCISR_ENDRX (0x1u<<2) +/*---------------------------------------------------------------------------- + * Local Functions + *----------------------------------------------------------------------------*/ +/** Copy the API structure for interrupt handler */ +static SpioCaptureInit* _PioCaptureCopy; + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/** + * \brief The PIO_CaptureHandler must be called by the PIO Capture Interrupt + * Service Routine with the corresponding PIO Capture instance. + */ +/*----------------------------------------------------------------------------*/ +extern void PIO_CaptureHandler( void ) +{ + volatile uint32_t pio_captureSr; + uint32_t k; + + /* Read the status register*/ + pio_captureSr = PIOA->PIO_PCISR ; + k = pio_captureSr; + pio_captureSr = k & PIOA->PIO_PCIMR ; + + if (pio_captureSr & PIO_PCISR_DRDY) { + /* Parallel Capture Mode Data Ready */ + if ( _PioCaptureCopy->CbkDataReady != NULL ) { + _PioCaptureCopy->CbkDataReady( _PioCaptureCopy ); + } else { + TRACE_DEBUG("IT PIO Capture Data Ready received (no callback)\n\r"); + } + } + + if (pio_captureSr & PIO_PCISR_OVRE) { + /* Parallel Capture Mode Overrun Error */ + if ( _PioCaptureCopy->CbkOverrun != NULL ) { + _PioCaptureCopy->CbkOverrun( _PioCaptureCopy ); + } else { + TRACE_DEBUG("IT PIO Capture Overrun Error received (no callback)\n\r"); + } + } + + if (pio_captureSr & PIO_PCISR_RXBUFF) { + /* Reception Buffer Full */ + if ( _PioCaptureCopy->CbkBuffFull != NULL ) { + _PioCaptureCopy->CbkBuffFull( _PioCaptureCopy ); + } else { + TRACE_DEBUG("IT PIO Capture Reception Buffer Full received \ + (no callback)\n\r"); + } + } + + if (pio_captureSr & PIO_PCISR_ENDRX) { + /* End of Reception Transfer */ + if ( _PioCaptureCopy->CbkEndReception != NULL ) { + _PioCaptureCopy->CbkEndReception( _PioCaptureCopy ); + } else { + TRACE_DEBUG("IT PIO Capture End of Reception Transfer \ + received (no callback)\n\r"); + } + } +} + +/*----------------------------------------------------------------------------*/ +/** + * \brief Disable Interrupt of the PIO Capture + * \param itToDisable : Interrupt to disable + */ +/*----------------------------------------------------------------------------*/ +void PIO_CaptureDisableIt( uint32_t itToDisable ) +{ + /* Parallel capture mode is enabled */ + PIOA->PIO_PCIDR = itToDisable; +} + +/*----------------------------------------------------------------------------*/ +/** + * \brief Enable Interrupt of the PIO Capture + * \param itToEnable : Interrupt to enable + */ +/*----------------------------------------------------------------------------*/ +void PIO_CaptureEnableIt( uint32_t itToEnable ) +{ + /* Parallel capture mode is enabled */ + PIOA->PIO_PCIER = itToEnable; +} + +/*----------------------------------------------------------------------------*/ +/** + * \brief Enable the PIO Capture + */ +/*----------------------------------------------------------------------------*/ +void PIO_CaptureEnable( void ) +{ + /* PDC: Receive Pointer Register */ + // PIOA->PIO_RPR = (uint32_t)_PioCaptureCopy->pData ; + // /* PDC: Receive Counter Register */ + // /* Starts peripheral data transfer if corresponding channel is active */ + // PIOA->PIO_RCR = PIO_RCR_RXCTR(_PioCaptureCopy->dPDCsize) ; + + /* Parallel capture mode is enabled */ + PIOA->PIO_PCMR |= PIO_PCMR_PCEN ; +} + +/*----------------------------------------------------------------------------*/ +/** + * \brief Disable the PIO Capture + */ +/*----------------------------------------------------------------------------*/ +void PIO_CaptureDisable( void ) +{ + /* Parallel capture mode is disabled */ + PIOA->PIO_PCMR &= (uint32_t)(~PIO_PCMR_PCEN) ; +} + +/*----------------------------------------------------------------------------*/ +/** + * \brief Initialize the PIO Capture + * \param dsize : + * 0 = The reception data in the PIO_PCRHR register is a BYTE (8-bit). + * 1 = The reception data in the PIO_PCRHR register is a HALF-WORD (16-bit). + * 2/3 = The reception data in the PIO_PCRHR register is a WORD (32-bit). + * \param alwaysSampling: ALWYS: Parallel Capture Mode Always Sampling + * 0 = The parallel capture mode samples the data when both data enables are active. + * 1 = The parallel capture mode samples the data whatever the data enables are. + * \param halfSampling: HALFS: Parallel Capture Mode Half Sampling + * 0 = The parallel capture mode samples all the data. + * 1 = The parallel capture mode samples the data only one time out of two. + * \param modeFirstSample: FRSTS: Parallel Capture Mode First Sample + * This bit is useful only if the HALFS bit is set to 1. If data are numbered + * in the order that they are received with an index from 0 to n: + * 0 = Only data with an even index are sampled. + * 1 = Only data with an odd index are sampled. + */ +/*----------------------------------------------------------------------------*/ +void PIO_CaptureInit( SpioCaptureInit *pInit ) +{ + PMC_EnablePeripheral( ID_PIOA ); + + assert( (pInit->dsize < 0x4) ) ; + assert( (pInit->alwaysSampling < 2) ); + assert( (pInit->halfSampling < 2) ); + assert( (pInit->modeFirstSample < 2) ); + /* Copy the API structure for interrupt handler */ + _PioCaptureCopy = pInit; + + if ( pInit->CbkDataReady != NULL ) { + PIOA->PIO_PCIER = PIO_PCISR_DRDY; + } + + if ( pInit->CbkOverrun != NULL ) { + PIOA->PIO_PCIER = PIO_PCISR_OVRE; + } + + if ( pInit->CbkEndReception != NULL ) { + PIOA->PIO_PCIER = PIO_PCISR_ENDRX; + } + + if ( pInit->CbkBuffFull != NULL ) { + PIOA->PIO_PCIER = PIO_PCISR_RXBUFF; + } +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio_it.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio_it.c new file mode 100644 index 000000000..814041f08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pio_it.c @@ -0,0 +1,327 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/* + * \file + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +/* Maximum number of interrupt sources that can be defined. This + * constant can be increased, but the current value is the smallest possible + * that will be compatible with all existing projects. */ +#define MAX_INTERRUPT_SOURCES 7 + +/*---------------------------------------------------------------------------- + * Local types + *----------------------------------------------------------------------------*/ + +/** + * Describes a PIO interrupt source, including the PIO instance triggering the + * interrupt and the associated interrupt handler. + */ +typedef struct _InterruptSource +{ + /* Pointer to the source pin instance. */ + const Pin *pPin; + + /* Interrupt handler. */ + void (*handler)( const Pin* ) ; +} InterruptSource ; + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ + +/* List of interrupt sources. */ +static InterruptSource _aIntSources[MAX_INTERRUPT_SOURCES] ; + +/* Number of currently defined interrupt sources. */ +static uint32_t _dwNumSources = 0; + +/*---------------------------------------------------------------------------- + * Local Functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Handles all interrupts on the given PIO controller. + * \param id PIO controller ID. + * \param pPio PIO controller base address. + */ +extern void PioInterruptHandler( uint32_t id, Pio *pPio ) +{ + uint32_t status; + uint32_t i; + + /* Read PIO controller status */ + status = pPio->PIO_ISR; + status &= pPio->PIO_IMR; + + /* Check pending events */ + if ( status != 0 ) { + TRACE_DEBUG( "PIO interrupt on PIO controller #%d\n\r", id ) ; + + /* Find triggering source */ + i = 0; + while ( status != 0 ) { + /* There cannot be an un-configured source enabled. */ + assert(i < _dwNumSources); + + /* Source is configured on the same controller */ + if (_aIntSources[i].pPin->id == id) { + /* Source has PIOs whose statuses have changed */ + if ( (status & _aIntSources[i].pPin->mask) != 0 ) { + TRACE_DEBUG( "Interrupt source #%d triggered\n\r", i ) ; + _aIntSources[i].handler(_aIntSources[i].pPin); + status &= ~(_aIntSources[i].pPin->mask); + } + } + i++; + } + } +} + +/*---------------------------------------------------------------------------- + * Global Functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Parallel IO Controller A interrupt handler + * \Redefined PIOA interrupt handler for NVIC interrupt table. + */ +extern void PIOA_Handler( void ) +{ + PioInterruptHandler( ID_PIOA, PIOA ) ; +} + +/** + * \brief Parallel IO Controller B interrupt handler + * \Redefined PIOB interrupt handler for NVIC interrupt table. + */ +extern void PIOB_Handler( void ) +{ + PioInterruptHandler( ID_PIOB, PIOB ) ; +} + +/** + * \brief Parallel IO Controller C interrupt handler + * \Redefined PIOC interrupt handler for NVIC interrupt table. + */ +extern void PIOC_Handler( void ) +{ + PioInterruptHandler( ID_PIOC, PIOC ) ; +} + + +/** + * \brief Parallel IO Controller D interrupt handler + * \Redefined PIOD interrupt handler for NVIC interrupt table. + */ +extern void PIOD_Handler( void ) +{ + PioInterruptHandler( ID_PIOD, PIOD ) ; +} + +/** + * \brief Parallel IO Controller E interrupt handler + * \Redefined PIOE interrupt handler for NVIC interrupt table. + */ +extern void PIOE_Handler( void ) +{ + PioInterruptHandler( ID_PIOE, PIOE ) ; +} + +/** + * \brief Initializes the PIO interrupt management logic + * + * The desired priority of PIO interrupts must be provided. + * Calling this function multiple times result in the reset of currently + * configured interrupts. + * + * \param priority PIO controller interrupts priority. + */ +extern void PIO_InitializeInterrupts( uint32_t dwPriority ) +{ + TRACE_DEBUG( "PIO_Initialize()\n\r" ) ; + + /* Reset sources */ + _dwNumSources = 0 ; + + /* Configure PIO interrupt sources */ + TRACE_DEBUG( "PIO_Initialize: Configuring PIOA\n\r" ) ; + PMC_EnablePeripheral( ID_PIOA ) ; + PIOA->PIO_ISR ; + PIOA->PIO_IDR = 0xFFFFFFFF ; + NVIC_DisableIRQ( PIOA_IRQn ) ; + NVIC_ClearPendingIRQ( PIOA_IRQn ) ; + NVIC_SetPriority( PIOA_IRQn, dwPriority ) ; + NVIC_EnableIRQ( PIOA_IRQn ) ; + + TRACE_DEBUG( "PIO_Initialize: Configuring PIOB\n\r" ) ; + PMC_EnablePeripheral( ID_PIOB ) ; + PIOB->PIO_ISR ; + PIOB->PIO_IDR = 0xFFFFFFFF ; + NVIC_DisableIRQ( PIOB_IRQn ) ; + NVIC_ClearPendingIRQ( PIOB_IRQn ) ; + NVIC_SetPriority( PIOB_IRQn, dwPriority ) ; + NVIC_EnableIRQ( PIOB_IRQn ) ; + + TRACE_DEBUG( "PIO_Initialize: Configuring PIOC\n\r" ) ; + PMC_EnablePeripheral( ID_PIOC ) ; + PIOC->PIO_ISR ; + PIOC->PIO_IDR = 0xFFFFFFFF ; + NVIC_DisableIRQ( PIOC_IRQn ) ; + NVIC_ClearPendingIRQ( PIOC_IRQn ) ; + NVIC_SetPriority( PIOC_IRQn, dwPriority ) ; + NVIC_EnableIRQ( PIOC_IRQn ) ; + + TRACE_DEBUG( "PIO_Initialize: Configuring PIOD\n\r" ) ; + PMC_EnablePeripheral( ID_PIOD ) ; + PIOD->PIO_ISR ; + PIOD->PIO_IDR = 0xFFFFFFFF ; + NVIC_DisableIRQ( PIOD_IRQn ) ; + NVIC_ClearPendingIRQ( PIOD_IRQn ) ; + NVIC_SetPriority( PIOD_IRQn, dwPriority ) ; + NVIC_EnableIRQ( PIOD_IRQn ) ; + + TRACE_DEBUG( "PIO_Initialize: Configuring PIOE\n\r" ) ; + PMC_EnablePeripheral( ID_PIOE ) ; + PIOE->PIO_ISR ; + PIOE->PIO_IDR = 0xFFFFFFFF ; + NVIC_DisableIRQ( PIOE_IRQn ) ; + NVIC_ClearPendingIRQ( PIOE_IRQn ) ; + NVIC_SetPriority( PIOE_IRQn, dwPriority ) ; + NVIC_EnableIRQ( PIOE_IRQn ) ; +} + +/** + * Configures a PIO or a group of PIO to generate an interrupt on status + * change. The provided interrupt handler will be called with the triggering + * pin as its parameter (enabling different pin instances to share the same + * handler). + * \param pPin Pointer to a Pin instance. + * \param handler Interrupt handler function pointer. + */ +extern void PIO_ConfigureIt( const Pin *pPin, void (*handler)( const Pin* ) ) +{ + Pio* pio ; + InterruptSource* pSource ; + + TRACE_DEBUG( "PIO_ConfigureIt()\n\r" ) ; + + assert( pPin ) ; + pio = pPin->pio ; + assert( _dwNumSources < MAX_INTERRUPT_SOURCES ) ; + + /* Define new source */ + TRACE_DEBUG( "PIO_ConfigureIt: Defining new source #%d.\n\r", _dwNumSources ) ; + + pSource = &(_aIntSources[_dwNumSources]) ; + pSource->pPin = pPin ; + pSource->handler = handler ; + _dwNumSources++ ; + + /* PIO3 with additional interrupt support + * Configure additional interrupt mode registers */ + if ( pPin->attribute & PIO_IT_AIME ) { + // enable additional interrupt mode + pio->PIO_AIMER = pPin->mask ; + + // if bit field of selected pin is 1, set as Rising Edge/High level detection event + if ( pPin->attribute & PIO_IT_RE_OR_HL ) { + pio->PIO_REHLSR = pPin->mask ; + } else { + pio->PIO_FELLSR = pPin->mask; + } + + /* if bit field of selected pin is 1, set as edge detection source */ + if (pPin->attribute & PIO_IT_EDGE) + pio->PIO_ESR = pPin->mask; + else + pio->PIO_LSR = pPin->mask; + } else { + /* disable additional interrupt mode */ + pio->PIO_AIMDR = pPin->mask; + } +} + +/** + * Enables the given interrupt source if it has been configured. The status + * register of the corresponding PIO controller is cleared prior to enabling + * the interrupt. + * \param pPin Interrupt source to enable. + */ +extern void PIO_EnableIt( const Pin *pPin ) +{ + uint32_t i = 0; + uint32_t dwFound = 0; + + TRACE_DEBUG( "PIO_EnableIt()\n\r" ) ; + + assert( pPin != NULL ) ; + +#ifndef NOASSERT + + while ( (i < _dwNumSources) && !dwFound ) { + if ( _aIntSources[i].pPin == pPin ) { + dwFound = 1 ; + } + i++ ; + } + assert( dwFound != 0 ) ; +#endif + + pPin->pio->PIO_ISR; + pPin->pio->PIO_IER = pPin->mask ; +} + +/** + * Disables a given interrupt source, with no added side effects. + * + * \param pPin Interrupt source to disable. + */ +extern void PIO_DisableIt( const Pin *pPin ) +{ + assert( pPin != NULL ) ; + + TRACE_DEBUG( "PIO_DisableIt()\n\r" ) ; + + pPin->pio->PIO_IDR = pPin->mask; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pmc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pmc.c new file mode 100644 index 000000000..0b5c017da --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pmc.c @@ -0,0 +1,572 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup pmc_module Working with PMC + * The PMC driver provides the Interface to configure the Power Management + * Controller (PMC). + * + * \section Usage + *
      + *
    • Enables/Disable the clock of a peripheral by using + * PMC_EnablePeripheral() and PMC_DisablePeripheral().
      • + *
    • Enables/Disable the clock of all peripherals by using + * PMC_EnableAllPeripherals() and PMC_DisableAllPeripherals().
      • + *
    • Get status of a peripheral using PMC_IsPeriphEnabled().
      • + *
    • Manage the clocks using PMC_EnableExtOsc(), PMC_DisableExtOsc(), + * PMC_SelectExtOsc(), PMC_SelectExtBypassOsc(), PMC_EnableIntRC4_8_12MHz(), + * PMC_DisableIntRC4_8_12MHz(), PMC_SetPllaClock(), PMC_SetMckSelection(), + * PMC_DisableAllClocks(), PMC_ConfigureMckWithPlla(), + * PMC_EnableXT32KFME() and PMC_ConfigurePCK2().
      • + * + *
    + * For more accurate information, please look at the PMC section of the Datasheet. + * + * Related files :\n + * \ref pmc.c\n + * \ref pmc.h.\n +*/ + + /** + * \file + * + * \section Purpose + * + * Interface for configuring and using Power Management Controller (PMC) + * peripherals. + * + */ + +/** + * \file + * + * Implementation of Power Management Controller (PMC). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + +#define MASK_STATUS0 0xFFFFFFFC +#define MASK_STATUS1 0xFFFFFFFF + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ +/** + * \brief Switch MCK to PLLA clock. + */ +static void _PMC_SwitchMck2PllaClock(void) + +{ + /* Select PLLA as input clock for MCK */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_PLLA_CLK ; + + /* Wait until the master clock is established */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Switch MCK to main clock. + */ +static void _PMC_SwitchMck2MainClock(void) +{ + /* Select Main Oscillator as input clock for MCK */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_MAIN_CLK ; + + /* Wait until the master clock is established */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); + PMC->PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Switch MCK to slow clock. + */ +static void _PMC_SwitchMck2SlowClock(void) +{ + /* Select Slow Clock as input clock for MCK */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk) | PMC_MCKR_CSS_SLOW_CLK ; + + /* Wait until the master clock is established */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Set prescaler for MCK. + * + * \param prescaler Master Clock prescaler + */ +static void _PMC_SetMckPrescaler(uint32_t prescaler) +{ + /* Change MCK Prescaler divider in PMC_MCKR register */ + PMC->PMC_MCKR = (PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk) | prescaler; + + /* Wait until the master clock is established */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables the clock of a peripheral. The peripheral ID is used + * to identify which peripheral is targeted. + * + * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). + * + * \param id Peripheral ID (ID_xxx). + */ +void PMC_EnablePeripheral( uint32_t dwId ) +{ + assert( dwId < 63 ) ; + + if ( dwId < 32 ) { + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId) ) { + TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" \ + " %u is already enabled\n\r", (unsigned int)dwId ) ; + } else { + PMC->PMC_PCER0 = 1 << dwId ; + } + } else { + dwId -= 32; + if ((PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) == ((uint32_t)1 << dwId)) { + TRACE_DEBUG( "PMC_EnablePeripheral: clock of peripheral" \ + " %u is already enabled\n\r", (unsigned int)(dwId + 32) ) ; + } else { + PMC->PMC_PCER1 = 1 << dwId ; + } + } +} + +/** + * \brief Disables the clock of a peripheral. The peripheral ID is used + * to identify which peripheral is targeted. + * + * \note The ID must NOT be shifted (i.e. 1 << ID_xxx). + * + * \param id Peripheral ID (ID_xxx). + */ +void PMC_DisablePeripheral( uint32_t dwId ) +{ + assert( dwId < 63 ) ; + + if ( dwId < 32 ) { + if ( (PMC->PMC_PCSR0 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) { + TRACE_DEBUG("PMC_DisablePeripheral: clock of peripheral" \ + " %u is not enabled\n\r", (unsigned int)dwId ) ; + } else { + PMC->PMC_PCDR0 = 1 << dwId ; + } + } else { + dwId -= 32 ; + if ( (PMC->PMC_PCSR1 & ((uint32_t)1 << dwId)) != ((uint32_t)1 << dwId) ) { + TRACE_DEBUG( "PMC_DisablePeripheral: clock of peripheral" + " %u is not enabled\n\r", (unsigned int)(dwId + 32) ) ; + } else { + PMC->PMC_PCDR1 = 1 << dwId ; + } + } +} + +/** + * \brief Enable all the periph clock via PMC. + */ +void PMC_EnableAllPeripherals( void ) +{ + PMC->PMC_PCER0 = MASK_STATUS0 ; + while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != MASK_STATUS0 ) ; + + PMC->PMC_PCER1 = MASK_STATUS1 ; + while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != MASK_STATUS1 ) ; + + TRACE_DEBUG( "Enable all periph clocks\n\r" ) ; +} + +/** + * \brief Disable all the periph clock via PMC. + */ +void PMC_DisableAllPeripherals( void ) +{ + PMC->PMC_PCDR0 = MASK_STATUS0 ; + while ( (PMC->PMC_PCSR0 & MASK_STATUS0) != 0 ) ; + + PMC->PMC_PCDR1 = MASK_STATUS1 ; + while ( (PMC->PMC_PCSR1 & MASK_STATUS1) != 0 ) ; + + TRACE_DEBUG( "Disable all periph clocks\n\r" ) ; +} + +/** + * \brief Get Periph Status for the given peripheral ID. + * + * \param id Peripheral ID (ID_xxx). + */ +uint32_t PMC_IsPeriphEnabled( uint32_t dwId ) +{ + assert( dwId < ID_PERIPH_COUNT ) ; + + if ( dwId < 32 ) { + return ( PMC->PMC_PCSR0 & (1 << dwId) ) ; + } else { + return ( PMC->PMC_PCSR1 & (1 << (dwId - 32)) ) ; + } +} + + +/** + * \brief Enable external oscillator as main clock input. + */ +void PMC_EnableExtOsc(void) +{ + uint32_t read_MOR; + + /* Before switching MAIN OSC on external crystal : enable it and don't disable + * at the same time RC OSC in case of if MAIN OSC is still using RC OSC + */ + + read_MOR = PMC->CKGR_MOR; + read_MOR &= ~CKGR_MOR_MOSCRCF_Msk; + /* reset MOSCRCF field in MOR register before select RC 12MHz */ + read_MOR |= (CKGR_MOR_KEY_PASSWD + | CKGR_MOR_MOSCRCF_12_MHz + | CKGR_MOR_MOSCXTEN + | CKGR_MOR_MOSCRCEN + | CKGR_MOR_MOSCXTST(DEFAUTL_MAIN_OSC_COUNT)); + /* enable external crystal - enable RC OSC */ + + PMC->CKGR_MOR = read_MOR; + + while( !(PMC->PMC_SR & PMC_SR_MOSCRCS ) ); + /* wait end of RC oscillator stabilization */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); + + read_MOR |= CKGR_MOR_MOSCSEL; + /* select external crystal */ + + PMC->CKGR_MOR = read_MOR; + + while( !(PMC->PMC_SR & PMC_SR_MOSCSELS ) ); + /* Wait end of Main Oscillator Selection */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Disable external 12MHz oscillator. + */ +void PMC_DisableExtOsc(void) +{ + uint32_t read_MOR; + + read_MOR = PMC->CKGR_MOR; + read_MOR &= ~CKGR_MOR_MOSCXTEN; /* disable main xtal osc */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | read_MOR; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Select external OSC. + */ +void PMC_SelectExtOsc(void) +{ + /* switch from internal RC 12 MHz to external OSC 12 MHz */ + /* wait Main XTAL Oscillator stabilisation*/ + if ((PMC->CKGR_MOR & CKGR_MOR_MOSCSEL ) == CKGR_MOR_MOSCSEL) { + PMC_DisableIntRC4_8_12MHz(); + return; + } + /* enable external OSC 12 MHz */ + PMC->CKGR_MOR |= CKGR_MOR_MOSCXTEN | CKGR_MOR_KEY_PASSWD; + /* wait Main CLK Ready */ + while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY)); + /* switch MAIN clock to external OSC 12 MHz*/ + PMC->CKGR_MOR |= CKGR_MOR_MOSCSEL | CKGR_MOR_KEY_PASSWD; + /* wait MAIN clock status change for external OSC 12 MHz selection*/ + while(!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + /* in case where MCK is running on MAIN CLK */ + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + PMC_DisableIntRC4_8_12MHz(); +} + + +/** + * \brief Select external OSC. + */ +void PMC_SelectExtBypassOsc(void) +{ + volatile uint32_t timeout; + if((PMC->CKGR_MOR & CKGR_MOR_MOSCXTBY) != CKGR_MOR_MOSCXTBY){ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | + CKGR_MOR_MOSCRCEN | + CKGR_MOR_MOSCXTST(0xFF) | + CKGR_MOR_MOSCXTBY; + PMC->CKGR_MOR |= CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCSEL; + /* wait MAIN clock status change for external OSC 12 MHz selection*/ + while(!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + // Check if an external clock is provided + for(timeout = 0; timeout<0xffff;timeout++); + while(!(PMC->CKGR_MCFR & CKGR_MCFR_MAINFRDY)); + } +} + +/** + * \brief Enable internal 4/8/12MHz fast RC as main clock input. + * + * \param freqSelect fast RC frequency (FAST_RC_4MHZ, FAST_RC_8MHZ, + * FAST_RC_12MHZ). + */ +void PMC_EnableIntRC4_8_12MHz(uint32_t freqSelect) +{ + /* Enable Fast RC oscillator but DO NOT switch to RC now */ + PMC->CKGR_MOR |= (CKGR_MOR_KEY_PASSWD | CKGR_MOR_MOSCRCEN); + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Change Fast RC oscillator frequency */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCRCF_Msk) | + CKGR_MOR_KEY_PASSWD | freqSelect; + + /* Wait the Fast RC to stabilize */ + while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)); + + /* Switch to Fast RC */ + PMC->CKGR_MOR = (PMC->CKGR_MOR & ~CKGR_MOR_MOSCSEL) | + CKGR_MOR_KEY_PASSWD; + /* wait MAIN clock status change for Fast RC oscillator */ + while(!(PMC->PMC_SR & PMC_SR_MOSCSELS)); + + /* in case where MCK is running on MAIN CLK */ + while(!(PMC->PMC_SR & PMC_SR_MCKRDY)); + +} + +/** + * \brief Disable internal 4/8/12MHz fast RC. + */ +void PMC_DisableIntRC4_8_12MHz(void) +{ + uint32_t read_MOR; + + read_MOR = PMC->CKGR_MOR; + + read_MOR &= ~CKGR_MOR_MOSCRCF_Msk; /* reset MOSCRCF field in MOR register */ + read_MOR &= ~CKGR_MOR_MOSCRCEN; /* disable fast RC */ + PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD | read_MOR; + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); +} + +/** + * \brief Configure PLLA clock by giving MUL and DIV. + * Disable PLLA when 'mul' set to 0. + * + * \param mul PLL multiplier factor. + * \param div PLL divider factor. + */ +void PMC_SetPllaClock(uint32_t mul, uint32_t div) +{ + if (mul != 0) { + /* Init PLL speed */ + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE + | CKGR_PLLAR_PLLACOUNT(DEFAUTL_PLLA_COUNT) + | CKGR_PLLAR_MULA(mul - 1) + | CKGR_PLLAR_DIVA(div); + /* Wait for PLL stabilization */ + while( !(PMC->PMC_SR & PMC_SR_LOCKA) ); + } else { + PMC->CKGR_PLLAR = CKGR_PLLAR_ONE; /* disable PLL A */ + } +} + +/** + * \brief Selection of Master Clock. + * + * \param clockSource Master Clock source. + * \param prescaler Master Clock prescaler. + * + * \note + * The PMC_MCKR register must not be programmed in a single write + * operation (see. Product Data Sheet). + */ +void PMC_SetMckSelection(uint32_t clockSource, uint32_t prescaler) +{ + switch ( clockSource ) { + case PMC_MCKR_CSS_SLOW_CLK : + _PMC_SwitchMck2SlowClock(); + _PMC_SetMckPrescaler(prescaler); + break; + + case PMC_MCKR_CSS_MAIN_CLK : + _PMC_SwitchMck2MainClock(); + _PMC_SetMckPrescaler(prescaler); + break; + + case PMC_MCKR_CSS_PLLA_CLK : + _PMC_SetMckPrescaler(prescaler); + _PMC_SwitchMck2PllaClock(); + break ; + } +} + +/** + * \brief Disable all clocks. + */ +void PMC_DisableAllClocks(void) +{ + uint32_t read_reg; + + PMC->PMC_SCDR = PMC_SCDR_PCK0 | PMC_SCDR_PCK1 | PMC_SCDR_PCK2 | PMC_SCDR_PCK3 | + PMC_SCDR_PCK4 | PMC_SCDR_PCK5 | PMC_SCDR_PCK6; /* disable PCK */ + + _PMC_SwitchMck2MainClock(); + + PMC->CKGR_PLLAR = PMC->CKGR_PLLAR & ~CKGR_PLLAR_MULA_Msk; /* disable PLL A */ + + _PMC_SwitchMck2SlowClock(); + + read_reg = PMC->CKGR_MOR; + read_reg = (read_reg & ~CKGR_MOR_MOSCRCEN) | CKGR_MOR_KEY_PASSWD; + /* disable RC OSC */ + + PMC->CKGR_MOR = read_reg; + + PMC_DisableAllPeripherals(); /* disable all peripheral clocks */ +} + +/** + * \brief Configure PLLA as clock input for MCK. + * + * \param mul PLL multiplier factor (not shifted, don't minus 1). + * \param div PLL divider factor (not shifted). + * \param prescaler Master Clock prescaler (shifted as in register). + */ +void PMC_ConfigureMckWithPlla(uint32_t mul, uint32_t div, uint32_t prescaler) +{ + /* First, select Main OSC as input clock for MCK */ + _PMC_SwitchMck2MainClock(); + + /* Then, Set PLLA clock */ + PMC_SetPllaClock(mul, div); + + /* Wait until the master clock is established for the case we already + turn on the PLL */ + while( !(PMC->PMC_SR & PMC_SR_MCKRDY) ); + + /* Finally, select PllA as input clock for MCK */ + PMC_SetMckSelection(PMC_MCKR_CSS_PLLA_CLK, prescaler); +} + + +/** + * \brief Configure PLLA as clock input for MCK. + * + * \param mul PLL multiplier factor (not shifted, don't minus 1). + * \param div PLL divider factor (not shifted). + * \param prescaler Master Clock prescaler (shifted as in register). + */ +void PMC_EnableXT32KFME(void) +{ + + uint32_t read_MOR; + + /* Before switching MAIN OSC on external crystal : enable it and don't + disable at the same time RC OSC in case of if MAIN OSC is still using + RC OSC */ + + read_MOR = PMC->CKGR_MOR; + + read_MOR |= (CKGR_MOR_KEY_PASSWD |CKGR_MOR_XT32KFME); + /* enable external crystal - enable RC OSC */ + + PMC->CKGR_MOR = read_MOR; + +} + +/** + * \brief Configure PLLA as clock input for MCK. + * + * \param mul PLL multiplier factor (not shifted, don't minus 1). + * \param div PLL divider factor (not shifted). + * \param prescaler Master Clock prescaler (shifted as in register). + */ +void PMC_ConfigurePCK0(uint32_t MasterClk, uint32_t prescaler) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK0; /* disable PCK */ + + while((PMC->PMC_SCSR)& PMC_SCSR_PCK0); + PMC->PMC_PCK[0] = MasterClk | prescaler; + PMC->PMC_SCER = PMC_SCER_PCK0; + while(!((PMC->PMC_SR) & PMC_SR_PCKRDY0)); + +} + + +/** + * \brief Configure PLLA as clock input for MCK. + * + * \param mul PLL multiplier factor (not shifted, don't minus 1). + * \param div PLL divider factor (not shifted). + * \param prescaler Master Clock prescaler (shifted as in register). + */ +void PMC_ConfigurePCK1(uint32_t MasterClk, uint32_t prescaler) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK1; /* disable PCK */ + + while((PMC->PMC_SCSR)& PMC_SCSR_PCK1); + PMC->PMC_PCK[1] = MasterClk | prescaler; + PMC->PMC_SCER = PMC_SCER_PCK1; + while(!((PMC->PMC_SR) & PMC_SR_PCKRDY1)); + +} + +/** + * \brief Configure PLLA as clock input for MCK. + * + * \param mul PLL multiplier factor (not shifted, don't minus 1). + * \param div PLL divider factor (not shifted). + * \param prescaler Master Clock prescaler (shifted as in register). + */ +void PMC_ConfigurePCK2(uint32_t MasterClk, uint32_t prescaler) +{ + PMC->PMC_SCDR = PMC_SCDR_PCK2; /* disable PCK */ + + while((PMC->PMC_SCSR)& PMC_SCSR_PCK2); + PMC->PMC_PCK[2] = MasterClk | prescaler; + PMC->PMC_SCER = PMC_SCER_PCK2; + while(!((PMC->PMC_SR) & PMC_SR_PCKRDY2)); + +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pwmc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pwmc.c new file mode 100644 index 000000000..41faa8548 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/pwmc.c @@ -0,0 +1,578 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup pwm_module Working with PWM + * \ingroup peripherals_module + * The PWM driver provides the interface to configure and use the PWM + * peripheral. + * + * The PWM macrocell controls square output waveforms of 4 channels. + * Characteristics of output waveforms such as period, duty-cycle, + * dead-time can be configured.\n + * Some of PWM channels can be linked together as synchronous channel and + * duty-cycle of synchronous channels can be updated by PDC automatically. + * + * Before enabling the channels, they must have been configured first. + * The main settings include: + *
      + *
    • Configuration of the clock generator.
      • + *
    • Selection of the clock for each channel.
      • + *
    • Configuration of output waveform characteristics, such as period, + * duty-cycle etc.
      • + *
    • Configuration for synchronous channels if needed.
      • + * - Selection of the synchronous channels. + * - Selection of the moment when the WRDY flag and the corresponding PDC + * transfer request are set (PTRM and PTRCS in the PWM_SCM register). + * - Configuration of the update mode (UPDM in the PWM_SCM register). + * - Configuration of the update period (UPR in the PWM_SCUP register). + *
    + * + * After the channels is enabled, the user must use respective update registers + * to change the wave characteristics to prevent unexpected output waveform. + * i.e. PWM_CDTYUPDx register should be used if user want to change duty-cycle + * when the channel is enabled. + * + * For more accurate information, please look at the PWM section of the + * Datasheet. + * + * Related files :\n + * \ref pwmc.c\n + * \ref pwmc.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of the Pulse Width Modulation Controller (PWM) peripheral. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Finds a prescaler/divisor couple to generate the desired frequency + * from MCK. + * + * Returns the value to enter in PWM_CLK or 0 if the configuration cannot be + * met. + * + * \param frequency Desired frequency in Hz. + * \param mck Master clock frequency in Hz. + */ +static uint16_t FindClockConfiguration( + uint32_t frequency, + uint32_t mck) +{ + uint32_t divisors[11] = {1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024}; + uint8_t divisor = 0; + uint32_t prescaler; + + assert(frequency < mck); + + /* Find prescaler and divisor values */ + prescaler = (mck / divisors[divisor]) / frequency; + while ((prescaler > 255) && (divisor < 11)) { + divisor++; + prescaler = (mck / divisors[divisor]) / frequency; + } + + /* Return result */ + if ( divisor < 11 ) { + TRACE_DEBUG( "Found divisor=%u and prescaler=%u for freq=%uHz\n\r", + divisors[divisor], prescaler, frequency ) ; + + return prescaler | (divisor << 8) ; + } else { + return 0 ; + } +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures PWM a channel with the given parameters, basic configure + * function. + * + * The PWM controller must have been clocked in the PMC prior to calling this + * function. + * Beware: this function disables the channel. It waits until disable is effective. + * + * \param channel Channel number. + * \param prescaler Channel prescaler. + * \param alignment Channel alignment. + * \param polarity Channel polarity. + */ +void PWMC_ConfigureChannel( + Pwm* pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity) +{ + pPwm->PWM_CH_NUM[0].PWM_CMR = 1; + + // assert(prescaler < PWM_CMR0_CPRE_MCKB); + assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0); + assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0); + + /* Disable channel (effective at the end of the current period) */ + if ((pPwm->PWM_SR & (1 << channel)) != 0) { + pPwm->PWM_DIS = 1 << channel; + while ((pPwm->PWM_SR & (1 << channel)) != 0); + } + + /* Configure channel */ + pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity; +} + +/** + * \brief Configures PWM a channel with the given parameters, extend configure + * function. + * The PWM controller must have been clocked in the PMC prior to calling this + * function. + * Beware: this function disables the channel. It waits until disable is effective. + * + * \param channel Channel number. + * \param prescaler Channel prescaler. + * \param alignment Channel alignment. + * \param polarity Channel polarity. + * \param countEventSelect Channel counter event selection. + * \param DTEnable Channel dead time generator enable. + * \param DTHInverte Channel Dead-Time PWMHx output Inverted. + * \param DTLInverte Channel Dead-Time PWMHx output Inverted. + */ +void PWMC_ConfigureChannelExt( + Pwm* pPwm, + uint8_t channel, + uint32_t prescaler, + uint32_t alignment, + uint32_t polarity, + uint32_t countEventSelect, + uint32_t DTEnable, + uint32_t DTHInverte, + uint32_t DTLInverte) +{ + // assert(prescaler < PWM_CMR0_CPRE_MCKB); + assert((alignment & (uint32_t)~PWM_CMR_CALG) == 0); + assert((polarity & (uint32_t)~PWM_CMR_CPOL) == 0); + assert((countEventSelect & (uint32_t)~PWM_CMR_CES) == 0); + assert((DTEnable & (uint32_t)~PWM_CMR_DTE) == 0); + assert((DTHInverte & (uint32_t)~PWM_CMR_DTHI) == 0); + assert((DTLInverte & (uint32_t)~PWM_CMR_DTLI) == 0); + + /* Disable channel (effective at the end of the current period) */ + if ((pPwm->PWM_SR & (1 << channel)) != 0) { + pPwm->PWM_DIS = 1 << channel; + while ((pPwm->PWM_SR & (1 << channel)) != 0); + } + + /* Configure channel */ + pPwm->PWM_CH_NUM[channel].PWM_CMR = prescaler | alignment | polarity | + countEventSelect | DTEnable | DTHInverte | DTLInverte; +} + +/** + * \brief Configures PWM clocks A & B to run at the given frequencies. + * + * This function finds the best MCK divisor and prescaler values automatically. + * + * \param clka Desired clock A frequency (0 if not used). + * \param clkb Desired clock B frequency (0 if not used). + * \param mck Master clock frequency. + */ +void PWMC_ConfigureClocks(Pwm* pPwm, uint32_t clka, uint32_t clkb, uint32_t mck) +{ + uint32_t mode = 0; + uint32_t result; + + /* Clock A */ + if (clka != 0) { + result = FindClockConfiguration(clka, mck); + assert( result != 0 ) ; + mode |= result; + } + + /* Clock B */ + if (clkb != 0) { + result = FindClockConfiguration(clkb, mck); + assert( result != 0 ) ; + mode |= (result << 16); + } + + /* Configure clocks */ + TRACE_DEBUG( "Setting PWM_CLK = 0x%08X\n\r", mode ) ; + pPwm->PWM_CLK = mode; +} + +/** + * \brief Sets the period value used by a PWM channel. + * + * This function writes directly to the CPRD register if the channel is disabled; + * otherwise, it uses the update register CPRDUPD. + * + * \param channel Channel number. + * \param period Period value. + */ +void PWMC_SetPeriod( Pwm* pPwm, uint8_t channel, uint16_t period) +{ + /* If channel is disabled, write to CPRD */ + if ((pPwm->PWM_SR & (1 << channel)) == 0) { + + pPwm->PWM_CH_NUM[channel].PWM_CPRD = period; + } else { + /* Otherwise use update register */ + pPwm->PWM_CH_NUM[channel].PWM_CPRDUPD = period; + } +} + +/** + * \brief Sets the duty cycle used by a PWM channel. + * This function writes directly to the CDTY register if the channel is disabled; + * otherwise it uses the update register CDTYUPD. + * Note that the duty cycle must always be inferior or equal to the channel + * period. + * + * \param channel Channel number. + * \param duty Duty cycle value. + */ +void PWMC_SetDutyCycle( Pwm* pPwm, uint8_t channel, uint16_t duty) +{ + assert(duty <= pPwm->PWM_CH_NUM[channel].PWM_CPRD); + + /* If channel is disabled, write to CDTY */ + if ((pPwm->PWM_SR & (1 << channel)) == 0) { + pPwm->PWM_CH_NUM[channel].PWM_CDTY = duty; + } else { + /* Otherwise use update register */ + pPwm->PWM_CH_NUM[channel].PWM_CDTYUPD = duty; + } +} + +/** + * \brief Sets the dead time used by a PWM channel. + * This function writes directly to the DT register if the channel is disabled; + * otherwise it uses the update register DTUPD. + * Note that the dead time must always be inferior or equal to the channel + * period. + * + * \param channel Channel number. + * \param timeH Dead time value for PWMHx output. + * \param timeL Dead time value for PWMLx output. + */ +void PWMC_SetDeadTime( Pwm* pPwm, uint8_t channel, uint16_t timeH, uint16_t timeL) +{ + assert(timeH <= pPwm->PWM_CH_NUM[channel].PWM_CPRD); + assert(timeL <= pPwm->PWM_CH_NUM[channel].PWM_CPRD); + + /* If channel is disabled, write to DT */ + if ((pPwm->PWM_SR & (1 << channel)) == 0) { + pPwm->PWM_CH_NUM[channel].PWM_DT = timeH | (timeL << 16); + } else { + /* Otherwise use update register */ + pPwm->PWM_CH_NUM[channel].PWM_DTUPD = timeH | (timeL << 16); + } +} + +/** + * \brief Configures Synchronous channel with the given parameters. + * Beware: At this time, the channels should be disabled. + * + * \param channels Bitwise OR of Synchronous channels. + * \param updateMode Synchronous channel update mode. + * \param requestMode PDC transfer request mode. + * \param requestComparisonSelect PDC transfer request comparison selection. + */ +void PWMC_ConfigureSyncChannel( Pwm* pPwm, + uint32_t channels, + uint32_t updateMode, + uint32_t requestMode, + uint32_t requestComparisonSelect) +{ + pPwm->PWM_SCM = channels | updateMode | requestMode | requestComparisonSelect; +} + +/** + * \brief Sets the update period of the synchronous channels. + * This function writes directly to the SCUP register if the channel #0 is disabled; + * otherwise it uses the update register SCUPUPD. + * + * \param period update period. + */ +void PWMC_SetSyncChannelUpdatePeriod( Pwm* pPwm, uint8_t period) +{ + /* If channel is disabled, write to SCUP */ + if ((pPwm->PWM_SR & (1 << 0)) == 0) { + pPwm->PWM_SCUP = period; + } else { + /* Otherwise use update register */ + pPwm->PWM_SCUPUPD = period; + } +} + +/** + * \brief Sets synchronous channels update unlock. + * + * Note: If the UPDM field is set to 0, writing the UPDULOCK bit to 1 + * triggers the update of the period value, the duty-cycle and + * the dead-time values of synchronous channels at the beginning + * of the next PWM period. If the field UPDM is set to 1 or 2, + * writing the UPDULOCK bit to 1 triggers only the update of + * the period value and of the dead-time values of synchronous channels. + * This bit is automatically reset when the update is done. + */ +void PWMC_SetSyncChannelUpdateUnlock( Pwm* pPwm ) +{ + pPwm->PWM_SCUC = PWM_SCUC_UPDULOCK; +} + +/** + * \brief Enables the given PWM channel. + * + * This does NOT enable the corresponding pin;this must be done in the user code. + * + * \param channel Channel number. + */ +void PWMC_EnableChannel( Pwm* pPwm, uint8_t channel) +{ + pPwm->PWM_ENA = 1 << channel; +} + +/** + * \brief Disables the given PWM channel. + * + * Beware, channel will be effectively disabled at the end of the current period. + * Application can check channel is disabled using the following wait loop: + * while ((PWM->PWM_SR & (1 << channel)) != 0); + * + * \param channel Channel number. + */ +void PWMC_DisableChannel( Pwm* pPwm, uint8_t channel) +{ + pPwm->PWM_DIS = 1 << channel; +} + +/** + * \brief Enables the period interrupt for the given PWM channel. + * + * \param channel Channel number. + */ +void PWMC_EnableChannelIt( Pwm* pPwm, uint8_t channel) +{ + pPwm->PWM_IER1 = 1 << channel; +} + +/** + * \brief Return PWM Interrupt Status2 Register + * + */ +uint32_t PWMC_GetStatus2( Pwm* pPwm) +{ + return pPwm->PWM_ISR2; +} + +/** + * \brief Disables the period interrupt for the given PWM channel. + * + * \param channel Channel number. + */ +void PWMC_DisableChannelIt( Pwm* pPwm, uint8_t channel) +{ + pPwm->PWM_IDR1 = 1 << channel; +} + +/** + * \brief Enables the selected interrupts sources on a PWMC peripheral. + * + * \param sources1 Bitwise OR of selected interrupt sources of PWM_IER1. + * \param sources2 Bitwise OR of selected interrupt sources of PWM_IER2. + */ +void PWMC_EnableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2) +{ + pPwm->PWM_IER1 = sources1; + pPwm->PWM_IER2 = sources2; +} + +/** + * \brief Disables the selected interrupts sources on a PWMC peripheral. + * + * \param sources1 Bitwise OR of selected interrupt sources of PWM_IDR1. + * \param sources2 Bitwise OR of selected interrupt sources of PWM_IDR2. + */ +void PWMC_DisableIt( Pwm* pPwm, uint32_t sources1, uint32_t sources2) +{ + pPwm->PWM_IDR1 = sources1; + pPwm->PWM_IDR2 = sources2; +} + +/** + * \brief Set PWM output override value. + * + * \param value Bitwise OR of output override value. + */ +void PWMC_SetOverrideValue( Pwm* pPwm, uint32_t value) +{ + pPwm->PWM_OOV = value; +} + +/** + * \brief Enable override output. + * + * \param value Bitwise OR of output selection. + * \param sync 0: enable the output asynchronously, 1: enable it synchronously + */ +void PWMC_EnableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync) +{ + if (sync) { + pPwm->PWM_OSSUPD = value; + } else { + pPwm->PWM_OSS = value; + } +} + +/** + * \brief Output Selection for override PWM output. + * + * \param value Bitwise OR of output override value. + */ +void PWMC_OutputOverrideSelection( Pwm* pPwm, uint32_t value ) +{ + pPwm->PWM_OS = value; +} + + +/** + * \brief Disable override output. + * + * \param value Bitwise OR of output selection. + * \param sync 0: enable the output asynchronously, 1: enable it synchronously + */ +void PWMC_DisableOverrideOutput( Pwm* pPwm, uint32_t value, uint32_t sync) +{ + if (sync) { + + pPwm->PWM_OSCUPD = value; + } else { + + pPwm->PWM_OSC = value; + } +} + +/** + * \brief Set PWM fault mode. + * + * \param mode Bitwise OR of fault mode. + */ +void PWMC_SetFaultMode( Pwm* pPwm, uint32_t mode) +{ + pPwm->PWM_FMR = mode; +} + +/** + * \brief PWM fault clear. + * + * \param fault Bitwise OR of fault to clear. + */ +void PWMC_FaultClear( Pwm* pPwm, uint32_t fault) +{ + pPwm->PWM_FCR = fault; +} + +/** + * \brief Set PWM fault protection value. + * + * \param value Bitwise OR of fault protection value. + */ +void PWMC_SetFaultProtectionValue( Pwm* pPwm, uint32_t value) +{ + pPwm->PWM_FPV1 = value; +} + +/** + * \brief Enable PWM fault protection. + * + * \param value Bitwise OR of FPEx[y]. + */ +void PWMC_EnableFaultProtection( Pwm* pPwm, uint32_t value) +{ + pPwm->PWM_FPE = value; +} + +/** + * \brief Configure comparison unit. + * + * \param x comparison x index + * \param value comparison x value. + * \param mode comparison x mode + */ +void PWMC_ConfigureComparisonUnit( Pwm* pPwm, uint32_t x, uint32_t value, uint32_t mode) +{ + assert(x < 8); + + /* If channel is disabled, write to CMPxM & CMPxV */ + if ((pPwm->PWM_SR & (1 << 0)) == 0) { + pPwm->PWM_CMP[x].PWM_CMPM = mode; + pPwm->PWM_CMP[x].PWM_CMPV = value; + } else { + /* Otherwise use update register */ + pPwm->PWM_CMP[x].PWM_CMPMUPD = mode; + pPwm->PWM_CMP[x].PWM_CMPVUPD = value; + } +} + +/** + * \brief Configure event line mode. + * + * \param x Line x + * \param mode Bitwise OR of line mode selection + */ +void PWMC_ConfigureEventLineMode( Pwm* pPwm, uint32_t x, uint32_t mode) +{ + assert(x < 2); + + if (x == 0) { + pPwm->PWM_ELMR[0] = mode; + } else if (x == 1) { + pPwm->PWM_ELMR[1] = mode; + } +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/qspi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/qspi.c new file mode 100644 index 000000000..3916982d4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/qspi.c @@ -0,0 +1,709 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup qspi_module Working with QSPI + * \ingroup peripherals_module + * The QSPI driver provides the interface to configure and use the QSPI + * peripheral. + * + * The Serial Peripheral Interface (QSPI) circuit is a synchronous serial + * data link that provides communication with external devices in Master + * or Slave Mode. + * + * To use the QSPI, the user has to follow these few steps: + * -# Enable the QSPI pins required by the application (see pio.h). + * -# Configure the QSPI using the \ref QSPI_Configure(). This enables the + * peripheral clock. The mode register is loaded with the given value. + * -# Configure all the necessary chip selects with \ref QSPI_ConfigureNPCS(). + * -# Enable the QSPI by calling \ref QSPI_Enable(). + * -# Send/receive data using \ref QSPI_Write() and \ref QSPI_Read(). Note that +* \ref QSPI_Read() + * must be called after \ref QSPI_Write() to retrieve the last value read. + * -# Send/receive data using the PDC with the \ref QSPI_WriteBuffer() and + * \ref QSPI_ReadBuffer() functions. + * -# Disable the QSPI by calling \ref QSPI_Disable(). + * + * For more accurate information, please look at the QSPI section of the + * Datasheet. + * + * Related files :\n + * \ref qspi.c\n + * \ref qspi.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of Serial Peripheral Interface (QSPI) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include "stdlib.h" +#include "string.h" + +#include + + +#define SCRAMBLE_KEY 0x0BADDEAD +/*---------------------------------------------------------------------------- + * Internal functions + *----------------------------------------------------------------------------*/ + + + +/** + * \brief Configure QSPI/SPI mode + * + * \param pQspi Pointer to a Qspi instance. + */ +__STATIC_INLINE void QSPI_ConfigureMode( Qspi *pQspi, uint8_t dMode ) +{ + assert(pQspi); + pQspi->QSPI_MR = dMode ; +} + +/** + * \brief Configure mode register of QSPI + * + * \param pQspi Pointer to a Qspi instance. + */ +__STATIC_INLINE void QSPI_Configure( Qspi *pQspi, uint32_t dwConfiguration ) +{ + assert(pQspi); + pQspi->QSPI_MR |= dwConfiguration ; +} + + +/** + * \brief Configures a instruction address for QSPI in QSPI mode + * + * \param pQspi Pointer to a Qspi instance. + * \param dwAddr Instruction Address + */ +__STATIC_INLINE void QSPI_SetInstAddr( Qspi *pQspi,uint32_t dwAddr ) +{ + assert(pQspi); + pQspi->QSPI_IAR = dwAddr ; +} + + +/** + * \brief Configures instruction register with a given command for QSPI + * + * \param pQspi Pointer to a Qspi instance. + * \param dwInst Instruction Code + * \param dwOpt Instruction Code option + */ +__STATIC_INLINE void QSPI_SetInst( Qspi *pQspi, uint8_t dwInst, uint8_t dwOpt ) +{ + assert(pQspi); + pQspi->QSPI_ICR = (dwInst | QSPI_ICR_OPT(dwOpt) ); +} + +/** + * \brief Configures instruction frame register of QSPI + * + * \param pQspi Pointer to a Qspi instance. + * \param pInstFrame Instruction Frame configuration + */ +__STATIC_INLINE void QSPI_SetInstFrame( Qspi *pQspi, QspiInstFrame_t *pInstFrame) +{ + assert(pQspi); + pQspi->QSPI_IFR = pInstFrame->InstFrame.val; +} + +/** + * \brief Reads the Instruction frame of QSPI + * + * \param pQspi Pointer to an Qspi instance. + */ +__STATIC_INLINE uint32_t QSPI_GetInstFrame( Qspi *pQspi ) +{ + assert(pQspi); + return pQspi->QSPI_IFR; +} + +/** + * \brief Read QSPI RDR register for SPI mode + * + * \param pQspi Pointer to an Qspi instance. + */ +__STATIC_INLINE uint16_t QSPI_ReadSPI( Qspi *pQspi ) +{ + assert(pQspi); + while(!QSPI_GetStatus(pQspi, IsReceived)); + return pQspi->QSPI_RDR; +} + + +/** + * \brief Write to QSPI Tx register in SPI mode + * + * \param pQspi Pointer to an Qspi instance. + * \param wData Data to transmit + */ +__STATIC_INLINE void QSPI_WriteSPI( Qspi *pQspi, uint16_t wData ) +{ + assert(pQspi); + /* Send data */ + while(!QSPI_GetStatus(pQspi, IsTxEmpty)); + pQspi->QSPI_TDR = wData ; + while(!QSPI_GetStatus(pQspi, IsTxSent)); +} + +/** + * \brief Configures QSPI scrambling with a given Key + * + * \param pQspi Pointer to an Qspi instance. + * \param wKey Key for scramble/unscramble + * \param EnableFlag Enable/disable scramble + * \param Random Add random value with given key + */ +__STATIC_INLINE void QSPI_ScrambleData( Qspi *pQspi, uint32_t wKey, + uint8_t EnableFlag, uint8_t Random ) +{ + assert(pQspi); + assert(EnableFlag < 2); + assert(Random < 2 ); + + if(EnableFlag) { + pQspi->QSPI_SKR = wKey; + } + pQspi->QSPI_SMR = ( EnableFlag | (Random << 1)); +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables a QSPI peripheral. + * + * \param pQspi Pointer to a Qspi instance. + */ +void QSPI_Enable( Qspi *pQspi ) +{ + assert(pQspi); + pQspi->QSPI_CR = QSPI_CR_QSPIEN ; + while(!(pQspi->QSPI_SR & QSPI_SR_QSPIENS)); +} + +/** + * \brief Disables a QSPI peripheral. + * + * \param pQspi Pointer to a Qspi instance. + */ +void QSPI_Disable( Qspi *pQspi ) +{ + assert(pQspi); + pQspi->QSPI_CR = QSPI_CR_QSPIDIS ; + while(pQspi->QSPI_SR & QSPI_SR_QSPIENS); +} + +/** + * \brief Resets a QSPI peripheral. + * + * \param pQspi Pointer to a Qspi instance. + */ +void QSPI_SwReset( Qspi *pQspi ) +{ + assert(pQspi); + pQspi->QSPI_CR = QSPI_CR_SWRST ; +} + +/** + * \brief Enables one or more interrupt sources of a QSPI peripheral. + * + * \param pQspi Pointer to a Qspi instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +QspidStatus_t QSPI_EnableIt( Qspi *pQspi, uint32_t dwSources ) +{ + assert(pQspi); + pQspi->QSPI_IER = dwSources ; + return QSPI_SUCCESS; +} + +/** + * \brief Disables one or more interrupt sources of a QSPI peripheral. + * + * \param pQspi Pointer to a Qspi instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +QspidStatus_t QSPI_DisableIt( Qspi *pQspi, uint32_t dwSources ) +{ + assert(pQspi); + pQspi->QSPI_IDR = dwSources ; + return QSPI_SUCCESS; +} + +/** + * \brief Return the interrupt mask register. + * + * \return Qspi interrupt mask register. + */ +uint32_t QSPI_GetItMask( Qspi *pQspi ) +{ + assert(pQspi); + return (pQspi->QSPI_IMR) ; +} + +/** + * \brief Returns enabled interrupt status + * + * \return Qspi interrupt mask register. + */ +uint32_t QSPI_GetEnabledItStatus( Qspi *pQspi ) +{ + assert(pQspi); + return (pQspi->QSPI_IMR & QSPI_GetStatus(pQspi, 0xFFFFFFFF) ) ; +} + +/** + * \brief Get the current status register of the given QSPI peripheral. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param pQspi Pointer to a Qspi instance. + * \param rStatus Compare status with given status bit + * \return QSPI status register. + */ +uint32_t QSPI_GetStatus( Qspi *pQspi, const QspiStatus_t rStatus ) +{ + assert(pQspi); + return (pQspi->QSPI_SR & rStatus) ; +} + +/** + * \brief Configures peripheral clock of a QSPI/SPI peripheral. + * + * \param pQspi Pointer to an Qspi instance. + * \param dwConfiguration Desired clock configuration. + */ +void QSPI_ConfigureClock( Qspi *pQspi, QspiClockMode_t ClockMode, uint32_t dwClockCfg ) +{ + assert(pQspi); + pQspi->QSPI_SCR = ClockMode ; + pQspi->QSPI_SCR |= dwClockCfg ; +} + +/** + * \brief Configures QSPI/SPI + * + * \param pQspi Pointer to an Qspi instance. + * \param Mode Mode for QSPI or SPI + * \param dwConfiguration Config of SPI or QSPI mode + */ +QspidStatus_t QSPI_ConfigureInterface( Qspid_t *pQspid, QspiMode_t Mode, + uint32_t dwConfiguration) +{ + pQspid->pQspiHw = QSPI; + pQspid->qspiId = ID_QSPI; + + QSPI_Disable(pQspid->pQspiHw); + QSPI_SwReset(pQspid->pQspiHw); + + QSPI_ConfigureMode(pQspid->pQspiHw, Mode); + QSPI_Configure(pQspid->pQspiHw, dwConfiguration); + + return QSPI_SUCCESS; +} + + +/** + * \brief Ends ongoing transfer by releasing CS of QSPI peripheral. + * + * \param pQspi Pointer to an Qspi instance. + */ +QspidStatus_t QSPI_EndTransfer( Qspi *pQspi ) +{ + assert(pQspi); + while(!QSPI_GetStatus(pQspi, IsTxEmpty)); + pQspi->QSPI_CR = QSPI_CR_LASTXFER ; + + return QSPI_SUCCESS; +} + + +/*---------------------------------------------------------------------------- + * SPI functions + *----------------------------------------------------------------------------*/ +/** + * \brief Reads the data received by a SPI peripheral. This + * method must be called after a successful SPI_Write call. + * + * \param pQspid Pointer to a Qspi instance. + * \param pData Buffer to put read value + * \return Qspi status + */ +QspidStatus_t QSPI_SingleReadSPI( Qspid_t *pQspid, uint16_t* const pData ) +{ + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + Qspi *pQspi = pQspid->pQspiHw; + uint32_t NumOfAttempt = 0; + uint16_t Dummy= 0xFF; + + for(; ;) { + if( QSPI_GetStatus(pQspi, IsReceived)) { + *pData = QSPI_ReadSPI(pQspi) ; + QSPI_WriteSPI(pQspi, Dummy); + *pData = QSPI_ReadSPI(pQspi) ; + NumOfAttempt = 0; + Status = QSPI_SUCCESS; + } else { + if(NumOfAttempt > 0xFFFF) { + Status = QSPI_READ_ERROR; + TRACE_ERROR(" SPI Read Error \n\r"); + break; + } else { + Status = QSPI_READ_ERROR; + NumOfAttempt++; + } + } + } + return Status; +} + +/** + * \brief Reads multiple data received by a SPI peripheral. This + * method must be called after a successful SPI_Write call. + * + * \param pQspid Pointer to a Qspi instance. + * \param pData Pointer to read buffer + * \param NumOfBytes Num of bytes to read + * + * \return Qspi status + */ +QspidStatus_t QSPI_MultiReadSPI( Qspid_t *pQspid, uint16_t* const pData, + uint32_t NumOfBytes ) +{ + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + Qspi *pQspi = pQspid->pQspiHw; + uint32_t NumOfBytesRead = 0; + uint32_t NumOfAttempt = 0; + uint8_t *pwData = (uint8_t *)pData; + uint16_t Dummy=0xFF; + + /* Dummy read and write to discard first bytes recvd and start + receiving new data*/ + Dummy = QSPI_ReadSPI(pQspi) ; + QSPI_WriteSPI(pQspi, Dummy); + for(; NumOfBytesRead < NumOfBytes;) { + if( QSPI_GetStatus(pQspi, IsTxSent)) { + *pwData= QSPI_ReadSPI(pQspi) ; + if(pQspi->QSPI_MR & QSPI_MR_NBBITS_Msk) { + pwData += sizeof(uint16_t); + } else { + pwData += sizeof(uint8_t); + } + NumOfBytesRead++; + NumOfAttempt = 0; + Status = QSPI_SUCCESS; + QSPI_WriteSPI(pQspi, Dummy); + } else { + if(NumOfAttempt > 0xFFFF) { + Status = QSPI_READ_ERROR; + TRACE_ERROR(" SPI MultiRead Error \n\r"); + break; + } else { + Status = QSPI_READ_ERROR; + NumOfAttempt++; + } + } + } + return Status; +} + +/** + * \brief Sends a single data through a SPI peripheral. + * + * \param pQspid Pointer to a Qspi instance. + * \param pData Pointer to Tx data + * + * \return Qspi status + */ +QspidStatus_t QSPI_SingleWriteSPI( Qspid_t *pQspid, uint16_t const *pData ) +{ + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + Qspi *pQspi = pQspid->pQspiHw; + uint32_t NumOfAttempt = 0; + + for(;;) { + if( QSPI_GetStatus(pQspi, IsTxSent)) { + QSPI_WriteSPI(pQspi, *pData); + NumOfAttempt = 0; + Status = QSPI_SUCCESS; + break; + } else { + Status = QSPI_BUSY_SENDING; + NumOfAttempt++; + if(NumOfAttempt > 0xFFFF) { + Status = QSPI_WRITE_ERROR; + TRACE_ERROR(" SPI Write Error \n\r"); + break; + } + } + } + return Status; + +} + +/** + * \brief Sends multiple data through a SPI peripheral. + * + * \param pQspid Pointer to a Qspi instance. + * \param pData Pointer to a Tx buffer + * \param NumOfBytes Num of data to send. + */ +QspidStatus_t QSPI_MultiWriteSPI( Qspid_t *pQspid, uint16_t const *pData, + uint32_t NumOfBytes ) +{ + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + Qspi *pQspi = pQspid->pQspiHw; + uint32_t NumOfBytesWrite = 0; + uint32_t NumOfAttempt = 0; + uint8_t *pwData = (uint8_t *)pData; + uint8_t Addr_Inc = 0; + + if(pQspi->QSPI_MR & QSPI_MR_NBBITS_Msk) { + Addr_Inc = sizeof(uint16_t); + } else { + Addr_Inc = sizeof(uint8_t); + } + + for(; NumOfBytesWrite < NumOfBytes; NumOfBytesWrite++) { + if( QSPI_GetStatus(pQspi, IsTxEmpty)) { + QSPI_WriteSPI(pQspi, (uint16_t )*pwData); + pwData += Addr_Inc; + NumOfAttempt = 0; + Status = QSPI_SUCCESS; + } else { + Status = QSPI_BUSY_SENDING; + NumOfAttempt++; + if(NumOfAttempt > 0xFFFF) { + Status = QSPI_WRITE_ERROR; + TRACE_ERROR(" SPI Multi Write Error \n\r"); + break; + } + } + } + return Status; + +} + +/*---------------------------------------------------------------------------- + * QSPI functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Send an instruction over QSPI (oly a flash command no data) + * + * \param pQspi Pointer to an Qspi instance. + * \param KeepCfg To keep Instruction fram value or restes to zero + * + * \return Returns 1 if At least one instruction end has been detected since + * the last read of QSPI_SR.; otherwise + * returns 0. + */ +QspidStatus_t QSPI_SendCommand( Qspid_t *pQspid, uint8_t const KeepCfg) +{ + QspiInstFrame_t* const pFrame = pQspid->pQspiFrame; + QspiMemCmd_t pCommand = pQspid->qspiCommand; + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + + if( pFrame->InstFrame.bm.bAddrEn) + { + QSPI_SetInstAddr(pQspid->pQspiHw, pFrame->Addr); + } + QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), + ( (pCommand.Option >> QSPI_ICR_OPT_Pos) & 0xFF)); + QSPI_SetInstFrame(pQspid->pQspiHw, pFrame ); + + memory_sync(); + while(!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); + // poll CR reg to know status if instruction has end + if(!KeepCfg) { + pFrame->InstFrame.val = 0; + } + return Status; +} + + + +/** + * \brief Send instruction over QSPI with data + * + * \param pQspi Pointer to an Qspi instance. + * \param KeepCfg To keep Instruction fram value or restes to zero + * + * \return Returns 1 if At least one instruction end has been detected + * since the last read of QSPI_SR.; otherwise returns 0. + */ +QspidStatus_t QSPI_SendCommandWithData( Qspid_t *pQspid, uint8_t const KeepCfg) +{ + QspiInstFrame_t* const pFrame = pQspid->pQspiFrame; + QspiMemCmd_t pCommand = pQspid->qspiCommand; + QspiBuffer_t pBuffer = pQspid->qspiBuffer; + uint32_t *pQspiBuffer = (uint32_t *)QSPIMEM_ADDR; + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + + //assert(pBuffer.pDataRx); + assert(pBuffer.pDataTx); + + QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), (pCommand.Option & 0xFF) ); + QSPI_SetInstFrame(pQspid->pQspiHw, pFrame ); + + QSPI_GetInstFrame(pQspid->pQspiHw); + // to synchronize system bus accesses + if(!KeepCfg) { + pFrame->InstFrame.val = 0; + } + + memcpy(pQspiBuffer ,pBuffer.pDataTx , pBuffer.TxDataSize ); + memory_sync(); + QSPI_EndTransfer(pQspid->pQspiHw ) ; + // End transmission after all data has been sent + while(!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); + // poll CR reg to know status if instruction has end + + return Status; +} + +/** + * \brief Send instruction over QSPI to read data + * + * \param pQspi Pointer to an Qspi instance. + * \param KeepCfg To keep Instruction from value or resets to zero + * + * \return Returns 1 if At least one instruction end has been detected + * since the last read of QSPI_SR.; otherwise returns 0. + */ +QspidStatus_t QSPI_ReadCommand( Qspid_t *pQspid, uint8_t const KeepCfg) +{ + QspiInstFrame_t* const pFrame = pQspid->pQspiFrame; + QspiMemCmd_t pCommand = pQspid->qspiCommand; + QspiBuffer_t pBuffer = pQspid->qspiBuffer; + uint32_t *pQspiBuffer = (uint32_t *)QSPIMEM_ADDR; + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + + assert(pBuffer.pDataRx); + + QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), + (pCommand.Option & 0xFF) ); + QSPI_SetInstFrame(pQspid->pQspiHw, pFrame ); + + QSPI_GetInstFrame(pQspid->pQspiHw); + // to synchronize system bus accesses + if(!KeepCfg) { + pFrame->InstFrame.val = 0; + } + memcpy(pBuffer.pDataRx , pQspiBuffer, pBuffer.RxDataSize ); + memory_sync(); + QSPI_EndTransfer(pQspid->pQspiHw ) ; + // End transmission after all data has been sent + while(!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); + // poll CR reg to know status if instruction has end + + return Status; +} + +/** + * \brief Sends an instruction over QSPI and configures other related address +* like Addr , Frame and synchronise bus access before data read or write + * + * \param pQspi Pointer to an Qspi instance. + * \param KeepCfg To keep Instruction from value or resets to zero + * \param ScrambleFlag Enable or disable scramble on QSPI + * + * \return Returns 1 if At least one instruction end has been detected since + * the last read of QSPI_SR.; otherwise returns 0. + */ +QspidStatus_t QSPI_EnableMemAccess( Qspid_t *pQspid, uint8_t const KeepCfg, + uint8_t ScrambleFlag) +{ + QspiInstFrame_t* const pFrame = pQspid->pQspiFrame; + QspiMemCmd_t pCommand = pQspid->qspiCommand; + + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + + QSPI_SetInst(pQspid->pQspiHw, (pCommand.Instruction & 0xFF), + (pCommand.Option & 0xFF) ); + + if(ScrambleFlag) { + QSPI_ScrambleData(pQspid->pQspiHw, SCRAMBLE_KEY, ScrambleFlag, 1); + } + + QSPI_SetInstFrame(pQspid->pQspiHw, pFrame ); + + QSPI_GetInstFrame(pQspid->pQspiHw); + // to synchronize system bus accesses + if(!KeepCfg) { + pFrame->InstFrame.val = 0; + } + Status = QSPI_SUCCESS; + return Status; +} + +/** + * \brief Writes or reads the QSPI memory (0x80000000) to transmit or + * receive data from Flash memory + * \param pQspi Pointer to an Qspi instance. + * \param ReadWrite Flag to indicate read/write QSPI memory access + * + * \return Returns 1 if At least one instruction end has been detected since + * the last read of QSPI_SR.; otherwise returns 0. + */ +QspidStatus_t QSPI_ReadWriteMem( Qspid_t *pQspid, Access_t const ReadWrite) +{ + QspidStatus_t Status = QSPI_UNKNOWN_ERROR; + QspiInstFrame_t* const pFrame = pQspid->pQspiFrame; + uint32_t *pQspiMem = (uint32_t *)( QSPIMEM_ADDR | pFrame->Addr); + QspiBuffer_t pBuffer = pQspid->qspiBuffer; + + assert( ( (ReadWrite > CmdAccess) && (ReadWrite <= WriteAccess) ) ? true: false ); + if (ReadWrite == WriteAccess) { + memcpy(pQspiMem, pBuffer.pDataTx , pBuffer.TxDataSize ); + } else { + memcpy(pBuffer.pDataRx, pQspiMem, pBuffer.RxDataSize ); + } + memory_sync(); + QSPI_EndTransfer(pQspid->pQspiHw ) ; + // End transmission after all data has been sent + while(!(pQspid->pQspiHw->QSPI_SR & QSPI_SR_INSTRE)); + // poll CR reg to know status if instruction has end + + Status = QSPI_SUCCESS; + return Status; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/qspi_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/qspi_dma.c new file mode 100644 index 000000000..6c5f1f152 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/qspi_dma.c @@ -0,0 +1,604 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \addtogroup qspi_dma_module QSPI xDMA driver + * \ingroup peripherals_module + * + * + */ + +/** + * \file + * + * Implementation for the SPI Flash with xDMA driver. + * + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** xDMA support */ + +/** xDMA Link List size for SPI transmission*/ +#define DMA_QSPI_LLI 2 + +/*----------------------------------------------------------------------------- + * QSPI DMA Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief SPI xDMA Rx callback + * Invoked on SPi DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to Spid instance. + */ +static void QSPID_Spi_Cb(uint32_t channel, QspiDma_t* pArg) +{ + Qspi *pQspiHw = pArg->Qspid.pQspiHw; + if (channel != pArg->RxChNum) + return; + /* Release the semaphore */ + ReleaseMutex(pArg->progress); + QSPI_EndTransfer(pQspiHw); + memory_sync(); +} + + +/** + * \brief QSPI xDMA Tx callback + * Invoked on QSPi DMA Write done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to Spid instance. + */ +static void QSPID_qspiTx_Cb(uint32_t channel, QspiDma_t* pArg) +{ + Qspi *pQspiHw = pArg->Qspid.pQspiHw; + if (channel != pArg->TxChNum) + return; + /* Release the semaphore */ + ReleaseMutex(pArg->progress); + QSPI_EndTransfer(pQspiHw); + while(!QSPI_GetStatus(pArg->Qspid.pQspiHw, IsEofInst )); + memory_sync(); +} + + +/** + * \brief QSPI xDMA Rx callback + * Invoked on SPi DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to Spid instance. + */ +static void QSPID_qspiRx_Cb(uint32_t channel, QspiDma_t* pArg) +{ + Qspi *pQspiHw = pArg->Qspid.pQspiHw; + if (channel != pArg->RxChNum) + return; + /* Release the semaphore */ + ReleaseMutex(pArg->progress); + QSPI_EndTransfer(pQspiHw); + while(!QSPI_GetStatus(pArg->Qspid.pQspiHw, IsEofInst )); + memory_sync(); +} + +/** + * \brief Configures the DMA for QSPI + * + * \param pQspidma Pointer to QSPI DMA structure + * \param Addr Address to Read or write of QSPI flash memory + * \param pBuffer Pointer input/output buffer + * \param ReadWrite Read or write memory flag + * \returns 0 if the dma multibuffer configuration successfully; otherwise returns + * QSPID_ERROR_XXX. + */ +static uint8_t QSPID_configureQpsiDma(QspiDma_t *pQspidma, uint32_t Addr, + QspiBuffer_t *pBuffer, Access_t const ReadWrite) +{ + sXdmadCfg xdmadCfg, xdmadRxCfg,xdmadTxCfg; + uint8_t chanNum; + uint8_t qspi_id = pQspidma->Qspid.qspiId; + Qspi *pQspiHw = pQspidma->Qspid.pQspiHw; + uint32_t xdmaCndc, xdmaInt, BurstSize, ChannelWidth; + + + /* Setup DMA for QSPI */ + + if(pQspidma->Qspid.qspiMode == QSPI_MR_SMM_SPI) { + // SPI mode + /* SPI TX DMA config */ + xdmadTxCfg.mbr_sa = (uint32_t)pBuffer->pDataTx; + xdmadTxCfg.mbr_da = (uint32_t)&pQspiHw->QSPI_TDR; + xdmadTxCfg.mbr_ubc = (pBuffer->TxDataSize); + + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( qspi_id, XDMAD_TRANSFER_TX )); + + xdmadTxCfg.mbr_bc = 0; + xdmadTxCfg.mbr_sus = 0; + xdmadTxCfg.mbr_dus =0; + + /* SPI RX DMA config */ + + xdmadRxCfg.mbr_da = (uint32_t)pBuffer->pDataRx; + xdmadRxCfg.mbr_sa = (uint32_t)&pQspiHw->QSPI_RDR; + xdmadRxCfg.mbr_ubc = (pBuffer->RxDataSize); + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( qspi_id, XDMAD_TRANSFER_RX )); + + xdmadRxCfg.mbr_bc = 0; + xdmadRxCfg.mbr_sus = 0; + xdmadRxCfg.mbr_dus =0; + xdmaCndc = 0; + /* Put all interrupts on for non LLI list setup of DMA */ + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + memory_barrier(); + if (XDMAD_ConfigureTransfer + ( pQspidma->pXdmad, pQspidma->RxChNum, &xdmadRxCfg, xdmaCndc, 0, xdmaInt)) + return QSPID_ERROR; + + if (XDMAD_ConfigureTransfer + ( pQspidma->pXdmad, pQspidma->TxChNum, &xdmadTxCfg, xdmaCndc, 0, xdmaInt)) + return QSPID_ERROR; + return 0; + + } else { + if(ReadWrite == WriteAccess) { + xdmadCfg.mbr_sa = (uint32_t)pBuffer->pDataTx; + xdmadCfg.mbr_da = (uint32_t)( QSPIMEM_ADDR | Addr); + xdmadCfg.mbr_ubc = (pBuffer->TxDataSize); + chanNum = pQspidma->TxChNum; + ChannelWidth = XDMAC_CC_DWIDTH_BYTE; + BurstSize = XDMAC_CC_MBSIZE_SIXTEEN; + } else if(ReadWrite == ReadAccess) { + xdmadCfg.mbr_da = (uint32_t)pBuffer->pDataRx; + xdmadCfg.mbr_sa = (uint32_t)( QSPIMEM_ADDR | Addr); + xdmadCfg.mbr_ubc = ((pBuffer->RxDataSize>>2) + 1); + chanNum = pQspidma->RxChNum; + ChannelWidth = XDMAC_CC_DWIDTH_WORD; + BurstSize = XDMAC_CC_MBSIZE_SIXTEEN; + } else { + TRACE_ERROR(" QSPI error \n\r"); + return 1; + } + + xdmadCfg.mbr_cfg = XDMAC_CC_TYPE_MEM_TRAN | + XDMAC_CC_MEMSET_NORMAL_MODE | + BurstSize | + ChannelWidth | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_INCREMENTED_AM ; + + xdmadCfg.mbr_bc = 0; + xdmadCfg.mbr_sus = 0; + xdmadCfg.mbr_dus =0; + + xdmaCndc = 0; + + + /* Put all interrupts on for non LLI list setup of DMA */ + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + memory_barrier(); + if (XDMAD_ConfigureTransfer( pQspidma->pXdmad, chanNum, &xdmadCfg, xdmaCndc, 0, xdmaInt)) + return QSPID_ERROR; + return 0; + } +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes the pQspidma structure and the corresponding QSPI & DMA . + * hardware select value. + * + * \param pQspidma Pointer to a QspiDma_t instance. + * \param Mode Associated SPI peripheral. + * \param dwConf QSPI peripheral configuration. + * \param pXdmad Pointer to a Xdmad instance. + */ +uint32_t QSPID_Configure( QspiDma_t *pQspidma, QspiMode_t Mode, + uint32_t dwConf, sXdmad* pXdmad) +{ + /* Initialize the QSPI structure */ + + QSPI_ConfigureInterface(&pQspidma->Qspid, Mode, dwConf); + + pQspidma->Qspid.qspiCommand.Instruction = 0; + pQspidma->Qspid.qspiCommand.Option = 0; + + pQspidma->RxChNum = QSPID_CH_NOT_ENABLED; + pQspidma->TxChNum = QSPID_CH_NOT_ENABLED; + + pQspidma->pXdmad = pXdmad; + + /* XDMA Driver initialize */ + XDMAD_Initialize( pQspidma->pXdmad, 0 ); + + /* Configure and enable interrupt */ + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority( XDMAC_IRQn ,1); + NVIC_EnableIRQ(XDMAC_IRQn); + + + return QSPI_SUCCESS; +} + + + +/** + * \brief Enables a QSPI Rx channel. This function will allocate a dma Rx + * channel for QSPI + * + * \param pQspidma Pointer to a Spid instance. + + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is not + * valid. + */ +uint32_t QSPID_EnableQspiRxChannel(QspiDma_t *pQspidma) +{ + static uint16_t DmaChannel; + + /* Try to get the semaphore */ + if (pQspidma->RxChNum != QSPID_CH_NOT_ENABLED) { + return QSPID_ERROR_LOCK; + } + + /* Allocate a DMA channel */ + DmaChannel = XDMAD_AllocateChannel( + pQspidma->pXdmad, XDMAD_TRANSFER_MEMORY, XDMAD_TRANSFER_MEMORY); + if ( DmaChannel == XDMAD_ALLOC_FAILED ){ + return QSPID_ERROR; + } + + pQspidma->RxChNum = DmaChannel; + /* Setup callbacks*/ + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, + (XdmadTransferCallback)QSPID_qspiRx_Cb, pQspidma); + + if (XDMAD_PrepareChannel( pQspidma->pXdmad, pQspidma->RxChNum )) + return QSPID_ERROR; + return 0; +} + + +/** + * \brief Enables a QSPI Tx channel. This function will allocate a dma Tx + * channel for QSPI + * + * \param pQspidma Pointer to a Spid instance. + + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is + * not valid. + */ +uint32_t QSPID_EnableQspiTxChannel(QspiDma_t *pQspidma) +{ + static uint16_t DmaChannel; + + /* Try to get the semaphore */ + if (pQspidma->TxChNum != QSPID_CH_NOT_ENABLED) { + return QSPID_ERROR_LOCK; + } + /* Allocate a DMA channel */ + DmaChannel = XDMAD_AllocateChannel( pQspidma->pXdmad, + XDMAD_TRANSFER_MEMORY, XDMAD_TRANSFER_MEMORY); + if ( DmaChannel == XDMAD_ALLOC_FAILED ) { + return QSPID_ERROR; + } + + pQspidma->TxChNum = DmaChannel; + /* Setup callbacks */ + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, + (XdmadTransferCallback)QSPID_qspiTx_Cb, pQspidma); + + if (XDMAD_PrepareChannel( pQspidma->pXdmad, pQspidma->TxChNum )) + return QSPID_ERROR; + + return 0; +} + + +/** + * \brief Enables a QSPI SPI Rx channel. This function will allocate a dma + * Rx channel for QSPI SPI mode + * + * \param pQspidma Pointer to a Spid instance. + + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is + * not valid. + */ +uint32_t QSPID_EnableSpiChannel(QspiDma_t *pQspidma) +{ + static uint16_t DmaChannel; + + /* Try to get the semaphore */ + if (pQspidma->RxChNum != QSPID_CH_NOT_ENABLED) { + return QSPID_ERROR_LOCK; + } + + /* Try to get the semaphore */ + if (pQspidma->TxChNum != QSPID_CH_NOT_ENABLED) { + return QSPID_ERROR_LOCK; + } + + /* Allocate a DMA channel */ + DmaChannel = XDMAD_AllocateChannel + ( pQspidma->pXdmad, pQspidma->Qspid.qspiId, XDMAD_TRANSFER_MEMORY); + if ( DmaChannel == XDMAD_ALLOC_FAILED ) { + return QSPID_ERROR; + } + + pQspidma->RxChNum = DmaChannel; + + /* Allocate a DMA channel */ + DmaChannel = XDMAD_AllocateChannel( pQspidma->pXdmad, + XDMAD_TRANSFER_MEMORY, pQspidma->Qspid.qspiId); + if ( DmaChannel == XDMAD_ALLOC_FAILED ) { + return QSPID_ERROR; + } + + pQspidma->TxChNum = DmaChannel; + + /* Setup callbacks*/ + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, + (XdmadTransferCallback)QSPID_Spi_Cb, pQspidma); + if (XDMAD_PrepareChannel( pQspidma->pXdmad, pQspidma->RxChNum )) + return QSPID_ERROR; + + /* Setup callbacks for SPI0/1 TX (ignored) */ + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, NULL, NULL); + if ( XDMAD_PrepareChannel( pQspidma->pXdmad, pQspidma->TxChNum )) + return QSPID_ERROR; + + return 0; +} + + +/** + * \brief Disables a QSPI Rx channel. This function will de-allocate previous + * allocated dma Rx channel for QSPI + * + * \param pQspidma Pointer to a Spid instance. + + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is + * not valid. + */ +uint32_t QSPID_DisableQspiRxChannel(QspiDma_t *pQspidma) +{ + + XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->RxChNum); + XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->RxChNum); + + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, NULL, NULL); + + + /* Free allocated DMA channel for QSPI RX. */ + XDMAD_FreeChannel( pQspidma->pXdmad, pQspidma->RxChNum); + + pQspidma->RxChNum = QSPID_CH_NOT_ENABLED; + + return 0; +} + + + +/** + * \brief Disables a QSPI Tx channel. This function will de-allocate previous + * allocated dma Tx channel for QSPI + * + * \param pQspidma Pointer to a Spid instance. + + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is + * not valid. + */ +uint32_t QSPID_DisableQspiTxChannel(QspiDma_t *pQspidma) +{ + + XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->TxChNum); + XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->TxChNum); + + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->TxChNum, NULL, NULL); + + /* Free allocated DMA channel for QSPI TX. */ + XDMAD_FreeChannel( pQspidma->pXdmad, pQspidma->TxChNum); + + pQspidma->TxChNum = QSPID_CH_NOT_ENABLED; + + return 0; +} + + +/** + * \brief Disables a QSPI SPI Rx and Tx channels. This function will + * de-allocate privious allocated dma Rx, Txchannel for QSPI in SPI mode + * + * \param pQspidma Pointer to a Spid instance. + + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is + * not valid. + */ +uint32_t QSPID_DisableSpiChannel(QspiDma_t *pQspidma) +{ + + XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->RxChNum); + //XDMAC_SoftwareFlushReq(pQspidma->pXdmad->pXdmacs, pQspidma->TxChNum); + XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->RxChNum); + XDMAD_StopTransfer(pQspidma->pXdmad, pQspidma->TxChNum); + + XDMAD_SetCallback(pQspidma->pXdmad, pQspidma->RxChNum, NULL, NULL); + + /* Free allocated DMA channel for QSPI RX. */ + XDMAD_FreeChannel( pQspidma->pXdmad, pQspidma->RxChNum); + + XDMAD_FreeChannel( pQspidma->pXdmad, pQspidma->TxChNum); + + pQspidma->RxChNum = QSPID_CH_NOT_ENABLED; + pQspidma->TxChNum = QSPID_CH_NOT_ENABLED; + + return 0; +} + + +/** + * \brief Starts a QSPI read or write operation. + * + * \param pQspidma Pointer to a Qspid instance. + * \param ReadWrite Defines the memory access type + * \returns 0 if the transfer has been started successfully; otherwise returns + * QSPID_ERROR_LOCK is the driver is in use, or QSPID_ERROR if the command is + * not valid. + */ +uint32_t QSPID_ReadWriteQSPI(QspiDma_t *pQspidma, Access_t const ReadWrite) +{ + QspiBuffer_t *pBuffer = &pQspidma->Qspid.qspiBuffer; + uint8_t chanNum; + uint32_t semTimer = 0x7FF; + + //assert(pBuffer->pDataTx); + + if (pQspidma->progress) { + return QSPID_ERROR_LOCK; + } + LockMutex(pQspidma->progress, semTimer); + if(ReadWrite == WriteAccess) { + chanNum = pQspidma->TxChNum; + } else if(ReadWrite == ReadAccess) { + chanNum = pQspidma->RxChNum; + } else { + TRACE_ERROR("%s QSPI Access Error\n\r", __FUNCTION__); + } + + if (QSPID_configureQpsiDma + ( pQspidma, pQspidma->Qspid.pQspiFrame->Addr, pBuffer, ReadWrite) ) + return QSPID_ERROR_LOCK; + + SCB_CleanInvalidateDCache(); + /* Start DMA 0(RX) && 1(TX) */ + if (XDMAD_StartTransfer( pQspidma->pXdmad,chanNum )) + return QSPID_ERROR_LOCK; + return 0; +} + +/** + * \brief Starts a SPI master transfer. This is a non blocking function. It will + * return as soon as the transfer is started. + * + * \param pSpid Pointer to a Spid instance. + * \param pCommand Pointer to the SPI command to execute. + * \returns 0 if the transfer has been started successfully; otherwise returns + * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not + * valid. + */ +uint32_t QSPID_ReadWriteSPI(QspiDma_t *pQspidma, Access_t const ReadWrite) +{ + QspiBuffer_t *pBuffer = &pQspidma->Qspid.qspiBuffer; + uint32_t semTimer = 0x7FF; + + assert(pBuffer->pDataRx); + assert(pBuffer->pDataTx); + + /* Try to get the dataflash semaphore */ + if (pQspidma->progress) { + + return QSPID_ERROR_LOCK; + } + + LockMutex(pQspidma->progress, semTimer); + + + if (QSPID_configureQpsiDma + ( pQspidma, pQspidma->Qspid.pQspiFrame->Addr, pBuffer, ReadWrite) ) + return QSPID_ERROR_LOCK; + + SCB_CleanInvalidateDCache(); + + /* Start DMA 0(RX) && 1(TX) */ + if (XDMAD_StartTransfer( pQspidma->pXdmad, pQspidma->RxChNum )) + return QSPID_ERROR_LOCK; + if (XDMAD_StartTransfer( pQspidma->pXdmad, pQspidma->TxChNum )) + return QSPID_ERROR_LOCK; + return 0; +} + +/** + * \brief Check if the QSPI driver is busy. + * + * \param pSpid Pointer to a Spid instance. + * \returns 1 if the SPI driver is currently busy executing a command; otherwise + */ +uint32_t QSPID_IsBusy(volatile uint8_t *QspiSemaphore) +{ + if( Is_LockFree(QspiSemaphore) ) { + return 1; + } else { + return 0; + } +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rstc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rstc.c new file mode 100644 index 000000000..8ad5418ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rstc.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \file */ +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include + + +/*--------------------------------------------------------------------------- + * Exported functions + *---------------------------------------------------------------------------*/ + +/** + * Configure the mode of the RSTC peripheral. + * The configuration is computed by the lib (RSTC_RMR_*). + * \param mr Desired mode configuration. + */ +void RSTC_ConfigureMode(uint32_t mr) +{ + Rstc *pHw = RSTC; + mr &= ~RSTC_MR_KEY_Msk; + pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; +} + +/** + * Enable/Disable the detection of a low level on the pin NRST as User Reset + * \param enable 1 to enable & 0 to disable. + */ +void RSTC_SetUserResetEnable(uint8_t enable) +{ + Rstc *pHw = RSTC; + uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk); + if (enable) { + mr |= RSTC_MR_URSTEN; + } else { + mr &= ~RSTC_MR_URSTEN; + } + pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; +} + +/** + * Enable/Disable the interrupt of a User Reset (USRTS bit in RSTC_RST). + * \param enable 1 to enable & 0 to disable. + */ +void RSTC_SetUserResetInterruptEnable(uint8_t enable) +{ + Rstc *pHw = RSTC; + uint32_t mr = pHw->RSTC_MR & (~RSTC_MR_KEY_Msk); + if (enable) { + mr |= RSTC_MR_URSTIEN; + } else { + mr &= ~RSTC_MR_URSTIEN; + } + pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; +} + +/** + * Setup the external reset length. The length is asserted during a time of + * pow(2, powl+1) Slow Clock(32KHz). The duration is between 60us and 2s. + * \param powl Power length defined. + */ +void RSTC_SetExtResetLength(uint8_t powl) +{ + Rstc *pHw = RSTC; + uint32_t mr = pHw->RSTC_MR; + mr &= ~(RSTC_MR_KEY_Msk | RSTC_MR_ERSTL_Msk); + mr |= RSTC_MR_ERSTL(powl); + pHw->RSTC_MR = mr | RSTC_MR_KEY_PASSWD; +} + + +/** + * Resets the processor. + */ +void RSTC_ProcessorReset(void) +{ + Rstc *pHw = RSTC; + pHw->RSTC_CR = RSTC_CR_PROCRST | RSTC_CR_KEY_PASSWD; +} + + +/** + * Asserts the NRST pin for external resets. + */ +void RSTC_ExtReset(void) +{ + Rstc *pHw = RSTC; + pHw->RSTC_CR = RSTC_CR_EXTRST | RSTC_CR_KEY_PASSWD; +} + +/** + * Return NRST pin level ( 1 or 0 ). + */ +uint8_t RSTC_GetNrstLevel(void) +{ + Rstc *pHw = RSTC; + return ((pHw->RSTC_SR & RSTC_SR_NRSTL) > 0); +} + +/** + * Returns 1 if at least one high-to-low transition of NRST (User Reset) has + * been detected since the last read of RSTC_RSR. + */ +uint8_t RSTC_IsUserResetDetected(void) +{ + Rstc *pHw = RSTC; + if (pHw->RSTC_SR & RSTC_SR_URSTS) { + return 1; + } + return 0; +} + +/** + * Return 1 if a software reset command is being performed by the reset + * controller. The reset controller is busy. + */ +uint8_t RSTC_IsBusy(void) +{ + Rstc *pHw = RSTC; + if (pHw->RSTC_SR & RSTC_SR_SRCMP) { + return 1; + } + return 0; +} + +/** + * Get the status + */ +uint32_t RSTC_GetStatus(void) +{ + Rstc *pHw = RSTC; + return (pHw->RSTC_SR); +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rtc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rtc.c new file mode 100644 index 000000000..546782e2d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rtc.c @@ -0,0 +1,455 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup rtc_module Working with RTC + * \ingroup peripherals_module + * The RTC driver provides the interface to configure and use the RTC + * peripheral. + * + * It manages date, time, and alarms.\n + * This timer is clocked by the 32kHz system clock, and is not impacted by + * power management settings (PMC). To be accurate, it is better to use an + * external 32kHz crystal instead of the internal 32kHz RC.\n + * + * It uses BCD format, and time can be set in AM/PM or 24h mode through a + * configuration bit in the mode register.\n + * + * To update date or time, the user has to follow these few steps : + *
      + *
    • Set UPDTIM and/or UPDCAL bit(s) in RTC_CR,
      • + *
    • Polling or IRQ on the ACKUPD bit of RTC_CR,
      • + *
    • Clear ACKUPD bit in RTC_SCCR,
      • + *
    • Update Time and/or Calendar values in RTC_TIMR/RTC_CALR (BCD format),
      • + *
    • Clear UPDTIM and/or UPDCAL bit in RTC_CR.
      • + *
    + * An alarm can be set to happen on month, date, hours, minutes or seconds, + * by setting the proper "Enable" bit of each of these fields in the Time and + * Calendar registers. + * This allows a large number of configurations to be available for the user. + * Alarm occurrence can be detected even by polling or interrupt. + * + * A check of the validity of the date and time format and values written by + * the user is automatically done. + * Errors are reported through the Valid Entry Register. + * + * For more accurate information, please look at the RTC section of the + * Datasheet. + * + * Related files :\n + * \ref rtc.c\n + * \ref rtc.h.\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Real Time Clock (RTC) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Sets the RTC in either 12 or 24 hour mode. + * + * \param mode Hour mode. + */ +extern void RTC_SetHourMode( Rtc* pRtc, uint32_t dwMode ) +{ + assert((dwMode & 0xFFFFFFFE) == 0); + + pRtc->RTC_MR = dwMode ; +} + +/** + * \brief Gets the RTC mode. + * + * \return Hour mode. + */ +extern uint32_t RTC_GetHourMode( Rtc* pRtc ) +{ + uint32_t dwMode ; + + TRACE_DEBUG( "RTC_SetHourMode()\n\r" ) ; + + dwMode = pRtc->RTC_MR; + dwMode &= 0xFFFFFFFE; + + return dwMode ; +} + +/** + * \brief Enables the selected interrupt sources of the RTC. + * + * \param sources Interrupt sources to enable. + */ +extern void RTC_EnableIt( Rtc* pRtc, uint32_t dwSources ) +{ + assert((dwSources & (uint32_t)(~0x1F)) == 0); + + TRACE_DEBUG( "RTC_EnableIt()\n\r" ) ; + + pRtc->RTC_IER = dwSources ; +} + +/** + * \brief Disables the selected interrupt sources of the RTC. + * + * \param sources Interrupt sources to disable. + */ +extern void RTC_DisableIt( Rtc* pRtc, uint32_t dwSources ) +{ + assert((dwSources & (uint32_t)(~0x1F)) == 0); + + TRACE_DEBUG( "RTC_DisableIt()\n\r" ) ; + + pRtc->RTC_IDR = dwSources ; +} + +/** + * \brief Sets the current time in the RTC. + * + * \note In successive update operations, the user must wait at least one second + * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these + * bits again. Please look at the RTC section of the datasheet for detail. + * + * \param ucHour Current hour in 12 or 24 hour mode. + * \param ucMinute Current minute. + * \param ucSecond Current second. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetTime( Rtc* pRtc, uint8_t ucHour, uint8_t ucMinute, uint8_t ucSecond ) +{ + uint32_t dwTime=0 ; + uint8_t ucHour_bcd ; + uint8_t ucMin_bcd ; + uint8_t ucSec_bcd ; + + TRACE_DEBUG( "RTC_SetTime(%02d:%02d:%02d)\n\r", ucHour, ucMinute, ucSecond ) ; + + /* if 12-hour mode, set AMPM bit */ + if ( (pRtc->RTC_MR & RTC_MR_HRMOD) == RTC_MR_HRMOD ) { + if ( ucHour > 12 ) { + ucHour -= 12 ; + dwTime |= RTC_TIMR_AMPM ; + } + } + ucHour_bcd = (ucHour%10) | ((ucHour/10)<<4) ; + ucMin_bcd = (ucMinute%10) | ((ucMinute/10)<<4) ; + ucSec_bcd = (ucSecond%10) | ((ucSecond/10)<<4) ; + + /* value overflow */ + if ( (ucHour_bcd & (uint8_t)(~RTC_HOUR_BIT_LEN_MASK)) | + (ucMin_bcd & (uint8_t)(~RTC_MIN_BIT_LEN_MASK)) | + (ucSec_bcd & (uint8_t)(~RTC_SEC_BIT_LEN_MASK))) { + return 1 ; + } + + dwTime = ucSec_bcd | (ucMin_bcd << 8) | (ucHour_bcd<<16) ; + + pRtc->RTC_CR |= RTC_CR_UPDTIM ; + while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ; + pRtc->RTC_SCCR = RTC_SCCR_ACKCLR ; + pRtc->RTC_TIMR = dwTime ; + pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDTIM) ; + pRtc->RTC_SCCR |= RTC_SCCR_SECCLR ; + + return (int)(pRtc->RTC_VER & RTC_VER_NVTIM) ; +} + +/** + * \brief Retrieves the current time as stored in the RTC in several variables. + * + * \param pucHour If not null, current hour is stored in this variable. + * \param pucMinute If not null, current minute is stored in this variable. + * \param pucSecond If not null, current second is stored in this variable. + */ +extern void RTC_GetTime( Rtc* pRtc, uint8_t *pucHour, + uint8_t *pucMinute, uint8_t *pucSecond ) +{ + uint32_t dwTime ; + + TRACE_DEBUG( "RTC_GetTime()\n\r" ) ; + + /* Get current RTC time */ + dwTime = pRtc->RTC_TIMR ; + while ( dwTime != pRtc->RTC_TIMR ) { + dwTime = pRtc->RTC_TIMR ; + } + + /* Hour */ + if ( pucHour ) { + *pucHour = ((dwTime & 0x00300000) >> 20) * 10 + + ((dwTime & 0x000F0000) >> 16); + + if ( (dwTime & RTC_TIMR_AMPM) == RTC_TIMR_AMPM ) { + *pucHour += 12 ; + } + } + + /* Minute */ + if ( pucMinute ) { + *pucMinute = ((dwTime & 0x00007000) >> 12) * 10 + + ((dwTime & 0x00000F00) >> 8); + } + + /* Second */ + if ( pucSecond ) { + *pucSecond = ((dwTime & 0x00000070) >> 4) * 10 + + (dwTime & 0x0000000F); + } +} + +/** + * \brief Sets a time alarm on the RTC. + * The match is performed only on the provided variables; + * Setting all pointers to 0 disables the time alarm. + * + * \note In AM/PM mode, the hour value must have bit #7 set for PM, cleared for + * AM (as expected in the time registers). + * + * \param pucHour If not null, the time alarm will hour-match this value. + * \param pucMinute If not null, the time alarm will minute-match this value. + * \param pucSecond If not null, the time alarm will second-match this value. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetTimeAlarm( Rtc* pRtc, uint8_t *pucHour, + uint8_t *pucMinute, uint8_t *pucSecond ) +{ + uint32_t dwAlarm=0 ; + + TRACE_DEBUG( "RTC_SetTimeAlarm()\n\r" ) ; + + /* Hour */ + if ( pucHour ) { + dwAlarm |= RTC_TIMALR_HOUREN | ((*pucHour / 10) << 20) | ((*pucHour % 10) << 16); + } + + /* Minute */ + if ( pucMinute ) { + dwAlarm |= RTC_TIMALR_MINEN | ((*pucMinute / 10) << 12) + | ((*pucMinute % 10) << 8); + } + + /* Second */ + if ( pucSecond ) { + dwAlarm |= RTC_TIMALR_SECEN | ((*pucSecond / 10) << 4) | (*pucSecond % 10); + } + + pRtc->RTC_TIMALR = dwAlarm ; + + return (int)(pRtc->RTC_VER & RTC_VER_NVTIMALR) ; +} + +/** + * \brief Retrieves the current year, month and day from the RTC. + * Month, day and week values are numbered starting at 1. + * + * \param pYwear Current year (optional). + * \param pucMonth Current month (optional). + * \param pucDay Current day (optional). + * \param pucWeek Current day in current week (optional). + */ +extern void RTC_GetDate( Rtc* pRtc, uint16_t *pwYear, uint8_t *pucMonth, + uint8_t *pucDay, uint8_t *pucWeek ) +{ + uint32_t dwDate ; + + /* Get current date (multiple reads are necessary to insure a stable value) */ + do { + dwDate = pRtc->RTC_CALR ; + } + while ( dwDate != pRtc->RTC_CALR ) ; + + /* Retrieve year */ + if ( pwYear ) { + *pwYear = (((dwDate >> 4) & 0x7) * 1000) + + ((dwDate & 0xF) * 100) + + (((dwDate >> 12) & 0xF) * 10) + + ((dwDate >> 8) & 0xF); + } + + /* Retrieve month */ + if ( pucMonth ) { + *pucMonth = (((dwDate >> 20) & 1) * 10) + ((dwDate >> 16) & 0xF); + } + + /* Retrieve day */ + if ( pucDay ) { + *pucDay = (((dwDate >> 28) & 0x3) * 10) + ((dwDate >> 24) & 0xF); + } + + /* Retrieve week */ + if ( pucWeek ) { + *pucWeek = ((dwDate >> 21) & 0x7); + } +} + +/** + * \brief Sets the current year, month and day in the RTC. + * Month, day and week values must be numbered starting from 1. + * + * \note In successive update operations, the user must wait at least one second + * after resetting the UPDTIM/UPDCAL bit in the RTC_CR before setting these + * bits again. Please look at the RTC section of the datasheet for detail. + * + * \param wYear Current year. + * \param ucMonth Current month. + * \param ucDay Current day. + * \param ucWeek Day number in current week. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetDate( Rtc* pRtc, uint16_t wYear, uint8_t ucMonth, + uint8_t ucDay, uint8_t ucWeek ) +{ + uint32_t wDate ; + uint8_t ucCent_bcd ; + uint8_t ucYear_bcd ; + uint8_t ucMonth_bcd ; + uint8_t ucDay_bcd ; + uint8_t ucWeek_bcd ; + + ucCent_bcd = ((wYear/100)%10) | ((wYear/1000)<<4); + ucYear_bcd = (wYear%10) | (((wYear/10)%10)<<4); + ucMonth_bcd = ((ucMonth%10) | (ucMonth/10)<<4); + ucDay_bcd = ((ucDay%10) | (ucDay/10)<<4); + ucWeek_bcd = ((ucWeek%10) | (ucWeek/10)<<4); + + /* value over flow */ + if ( (ucCent_bcd & (uint8_t)(~RTC_CENT_BIT_LEN_MASK)) | + (ucYear_bcd & (uint8_t)(~RTC_YEAR_BIT_LEN_MASK)) | + (ucMonth_bcd & (uint8_t)(~RTC_MONTH_BIT_LEN_MASK)) | + (ucWeek_bcd & (uint8_t)(~RTC_WEEK_BIT_LEN_MASK)) | + (ucDay_bcd & (uint8_t)(~RTC_DATE_BIT_LEN_MASK)) + ) { + return 1 ; + } + + + /* Convert values to date register value */ + wDate = ucCent_bcd | + (ucYear_bcd << 8) | + (ucMonth_bcd << 16) | + (ucWeek_bcd << 21) | + (ucDay_bcd << 24); + + /* Update calendar register */ + pRtc->RTC_CR |= RTC_CR_UPDCAL ; + while ((pRtc->RTC_SR & RTC_SR_ACKUPD) != RTC_SR_ACKUPD) ; + + pRtc->RTC_SCCR = RTC_SCCR_ACKCLR; + pRtc->RTC_CALR = wDate ; + pRtc->RTC_CR &= (uint32_t)(~RTC_CR_UPDCAL) ; + pRtc->RTC_SCCR |= RTC_SCCR_SECCLR; /* clear SECENV in SCCR */ + + return (int)(pRtc->RTC_VER & RTC_VER_NVCAL) ; +} + +/** + * \brief Sets a date alarm in the RTC. + * The alarm will match only the provided values; + * Passing a null-pointer disables the corresponding field match. + * + * \param pucMonth If not null, the RTC alarm will month-match this value. + * \param pucDay If not null, the RTC alarm will day-match this value. + * + * \return 0 success, 1 fail to set + */ +extern int RTC_SetDateAlarm( Rtc* pRtc, uint8_t *pucMonth, uint8_t *pucDay ) +{ + uint32_t dwAlarm ; + + dwAlarm = ((pucMonth) || (pucDay)) ? (0) : (0x01010000); + + TRACE_DEBUG( "RTC_SetDateAlarm()\n\r" ) ; + + /* Compute alarm field value */ + if ( pucMonth ) { + dwAlarm |= RTC_CALALR_MTHEN | ((*pucMonth / 10) << 20) + | ((*pucMonth % 10) << 16); + } + + if ( pucDay ) { + dwAlarm |= RTC_CALALR_DATEEN | ((*pucDay / 10) << 28) + | ((*pucDay % 10) << 24); + } + + /* Set alarm */ + pRtc->RTC_CALALR = dwAlarm ; + + return (int)(pRtc->RTC_VER & RTC_VER_NVCALALR) ; +} + +/** + * \brief Clear flag bits of status clear command register in the RTC. + * + * \param mask Bits mask of cleared events + */ +extern void RTC_ClearSCCR( Rtc* pRtc, uint32_t dwMask ) +{ + /* Clear all flag bits in status clear command register */ + dwMask &= RTC_SCCR_ACKCLR | RTC_SCCR_ALRCLR | RTC_SCCR_SECCLR + | RTC_SCCR_TIMCLR | RTC_SCCR_CALCLR ; + + pRtc->RTC_SCCR = dwMask ; +} + +/** + * \brief Get flag bits of status register in the RTC. + * + * \param mask Bits mask of Status Register + * + * \return Status register & mask + */ +extern uint32_t RTC_GetSR( Rtc* pRtc, uint32_t dwMask ) +{ + uint32_t dwEvent ; + + dwEvent = pRtc->RTC_SR ; + + return (dwEvent & dwMask) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rtt.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rtt.c new file mode 100644 index 000000000..1a4d3b416 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/rtt.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup rtt_module Working with RTT + * \ingroup peripherals_module + * The RTT driver provides the interface to configure and use the RTT + * peripheral. + * + * The Real-time Timer is used to count elapsed seconds.\n + * This timer is clocked by the 32kHz system clock divided by a programmable + * 16-bit value. To be accurate, it is better to use an + * external 32kHz crystal instead of the internal 32kHz RC.\n + * + * To count elapsed seconds, the user could follow these few steps: + *
      + *
    • Programming PTPRES in RTT_MR to feeding the timer with a 1Hz signal.
      • + *
    • Writing the bit RTTRST in RTT_MR to restart the timer with new settings.
      • + *
    + * + * An alarm can be set to happen on second by setting alarm value in RTT_AR. + * Alarm occurrence can be detected by polling or interrupt. + * + * For more accurate information, please look at the RTT section of the + * Datasheet. + * + * Related files :\n + * \ref rtt.c\n + * \ref rtt.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of Real Time Timer (RTT) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Changes the prescaler value of the given RTT and restarts it. + * + * \note This function disables RTT interrupt sources. + * + * \param rtt Pointer to a Rtt instance. + * \param prescaler Prescaler value for the RTT. + */ +void RTT_SetPrescaler(Rtt *rtt, uint16_t prescaler) +{ + rtt->RTT_MR = (prescaler | RTT_MR_RTTRST); +} + +/** + * \brief Returns the current value of the RTT timer value. + * + * \param rtt Pointer to a Rtt instance. + */ +uint32_t RTT_GetTime(Rtt *rtt) +{ + return rtt->RTT_VR; +} + +/** + * \brief Enables the specified RTT interrupt sources. + * + * \param rtt Pointer to a Rtt instance. + * \param sources Bitmask of interrupts to enable. + */ +void RTT_EnableIT(Rtt *rtt, uint32_t sources) +{ + assert( (sources & 0x0004FFFF) == 0 ) ; + rtt->RTT_MR |= sources; +} + +/** + * \brief Returns the status register value of the given RTT. + * + * \param rtt Pointer to an Rtt instance. + */ +uint32_t RTT_GetStatus(Rtt *rtt) +{ + return rtt->RTT_SR; +} + +/** + * \brief Configures the RTT to generate an alarm at the given time. + * + * \param pRtt Pointer to an Rtt instance. + * \param time Alarm time. + */ +void RTT_SetAlarm(Rtt *pRtt, uint32_t time) +{ + assert(time > 0); + + pRtt->RTT_AR = time - 1; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/sdramc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/sdramc.c new file mode 100644 index 000000000..d2f13a6a1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/sdramc.c @@ -0,0 +1,210 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup sdram_module + * The SDRAMC driver provides the Interface to configure the SDRAM Controller + * (SDRAMC). + * \section Usage + *
      + *
    • Configure SDRAM using SDRAMC_Configure().
      • + + *
    + * For more accurate information, please look at the SDRAMC section of the + * Datasheet. + * Related files :\n + * \ref sdramc.c\n + * \ref sdramc.h.\n +*/ + + /** + * \file + * + * \section Purpose + * + * Interface for configuring and using SDRAM Controller (SDRAMC). + * + */ + +/** + * \file + * + * Implementation of memories configuration on board. + * + */ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ +/** + * \brief Calculate the sdram controller config register value. + * \param pMemory Pointer to the sdram structure. + * \return Configure register value. + */ +static uint32_t SDRAMC_compute_CR_value( SSdramc_Memory* pMemory ) +{ + uint32_t dw=0 ; + + dw |= pMemory->cfg.dwColumnBits ; + dw |= pMemory->cfg.dwRowBits ; + dw |= pMemory->cfg.dwBanks ; //NB, number of banks + dw |= pMemory->cfg.dwCAS ; //CAS, CAS latency + dw |= pMemory->cfg.dwDataBusWidth ; //DBW, data bus width + dw |= SDRAMC_CR_TWR( pMemory->cfg.dwWriteRecoveryDelay ) ; + //TWR, Write Recovery Delay + dw |= SDRAMC_CR_TRC_TRFC( pMemory->cfg.dwRowCycleDelay_RowRefreshCycle ) ; + //TRC_TRFC,Row Cycle Delay and Row Refresh Cycle + dw |= SDRAMC_CR_TRP( pMemory->cfg.dwRowPrechargeDelay ) ; + //TRP, Row Precharge Delay + dw |= SDRAMC_CR_TRCD( pMemory->cfg.dwRowColumnDelay ) ; + //TRCD, Row to Column Delay + dw |= SDRAMC_CR_TRAS( pMemory->cfg.dwActivePrechargeDelay ) ; + //TRAS, Active to Precharge Delay + dw |= SDRAMC_CR_TXSR( pMemory->cfg.dwExitSelfRefreshActiveDelay ) ; + //TXSR, Exit Self Refresh to Active Delay + return dw ; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Configure and initialize the SDRAM controller. + * \param pMemory Pointer to the sdram structure. + * \param dwClockFrequency SDRAM clock frequency. + */ +extern void SDRAMC_Configure( SSdramc_Memory* pMemory, uint32_t dwClockFrequency ) +{ + volatile uint32_t dw ; + + /* SDRAM hardware init */ + /* Enable peripheral clock */ + PMC_EnablePeripheral( ID_SMC ) ; + + /* SDRAM device configure */ + /* Step 1. */ + /* Program the features of SDRAM device into the Configuration Register.*/ + SDRAMC->SDRAMC_CR = SDRAMC_compute_CR_value( pMemory ) ; + + /* Step 2. */ + /* For low-power SDRAM, temperature-compensated self refresh (TCSR), + drive strength (DS) and partial array self refresh (PASR) must be set + in the Low-power Register.*/ + SDRAMC->SDRAMC_LPR = 0; + + /* Step 3. */ + /* Program the memory device type into the Memory Device Register */ + SDRAMC->SDRAMC_MDR = SDRAMC_MDR_MD_SDRAM; + + /* Step 4 */ + /* A minimum pause of 200 ¦Ìs is provided to precede any signal toggle. + (6 core cycles per iteration) */ + for ( dw = 0; dw < ((dwClockFrequency/1000000)*200/6) ; dw++ ) ; + + /* Step 5. */ + /* A NOP command is issued to the SDR-SDRAM. Program NOP command into + Mode Register, the application must set Mode to 1 in the Mode Register. + Perform a write access to any SDR-SDRAM address to acknowledge this command. + Now the clock which drives SDR-SDRAM device is enabled.*/ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NOP; + *(uint16_t *)(EBI_SDRAMC_ADDR) = 0; + + /* Step 6. */ + /* An all banks precharge command is issued to the SDR-SDRAM. Program all + banks precharge command into Mode Register, the application must set Mode to + 2 in the Mode Register . Perform a write access to any SDRSDRAM address to + acknowledge this command. */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_ALLBANKS_PRECHARGE; + *(uint16_t *)(EBI_SDRAMC_ADDR) = 0x0; + + /* add some delays after precharge */ + for ( dw = 0; dw < ((dwClockFrequency/1000000)*200/6) ; dw++ ); + + /* Step 7. */ + /* Eight auto-refresh (CBR) cycles are provided. Program the auto refresh + command (CBR) into Mode Register, the application must set Mode to 4 in + the Mode Register. Once in the idle state, eight AUTO REFRESH cycles must + be performed. */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x1; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x2; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x3; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x4; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x5; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x6; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0 ) = 0x7; + + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_AUTO_REFRESH; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0) = 0x8; + + /* Step 8. */ + /* A Mode Register set (MRS) cycle is issued to program the parameters of + the SDRAM devices, in particular CAS latency and burst length. */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_LOAD_MODEREG; + *(uint16_t *)(EBI_SDRAMC_ADDR + 0x22) = 0xcafe; + + /* Step 9. */ + /* For low-power SDR-SDRAM initialization, an Extended Mode Register set + (EMRS) cycle is issued to program the SDR-SDRAM parameters (TCSR, PASR, DS). + The write address must be chosen so that BA[1] is set to 1 and BA[0] is set + to 0 */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_EXT_LOAD_MODEREG; + *((uint16_t *)(EBI_SDRAMC_ADDR + (1 << pMemory->cfg.dwBK1))) = 0; + + /* Step 10. */ + /* The application must go into Normal Mode, setting Mode to 0 in the Mode + Register and perform a write access at any location in the SDRAM to + acknowledge this command. */ + SDRAMC->SDRAMC_MR = SDRAMC_MR_MODE_NORMAL; + *(uint16_t *)(EBI_SDRAMC_ADDR ) = 0x0; + + /* Step 11. */ + /* Write the refresh rate into the count field in the SDRAMC Refresh + Timer register. Set Refresh timer 15.625 us*/ + dw=dwClockFrequency/1000u ; + dw*=15625u ; + dw/=1000000u ; + SDRAMC->SDRAMC_TR = SDRAMC_TR_COUNT( dw ) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/smc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/smc.c new file mode 100644 index 000000000..ce2edb384 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/smc.c @@ -0,0 +1,741 @@ +/* ---------------------------------------------------------------------------- + * ATMEL Microcontroller Software Support + * ---------------------------------------------------------------------------- + * Copyright (c) 2010, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ +/** + * \file + * + * Implementation of NFC functions. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +static SmcStatus smcStatus; +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Counts and return the number of bits set to '1' in the given hsiao code . + * \param code Hsizo code. + */ +static unsigned char CountBitsInByte(unsigned char byte) +{ + unsigned char count = 0; + while (byte > 0) { + if (byte & 1) { + count++; + } + byte >>= 1; + } + + return count; +} + +/** + * \brief Counts and return the number of bits set to '1' in the given hsiao code. + * \param code Hsizo code. + */ +static unsigned char CountBitsInCode(unsigned char *code) +{ + return CountBitsInByte(code[0]) + + CountBitsInByte(code[1]) + + CountBitsInByte(code[2]); +} + +/** + * \brief Clear the corresponding interrupt flag. + */ +static void SMC_Clear_Status (void) +{ + smcStatus.BStatus = 0; +} + +/** + * \brief Check the STATUS and set the corresponding interrupt flag. + */ +static void SMC_Handler(void) +{ + uint32_t status; + status = SMC->SMC_SR; +#if 0 + if ((status & SMC_SR_SMCSTS) == SMC_SR_SMCSTS) + /* NAND Flash Controller is enabled */ + smcStatus.bStatus.smcSts = 1; +#endif + if ((status & SMC_SR_XFRDONE) == SMC_SR_XFRDONE) + /* When set to one, this flag indicates that the NFC has terminated the + Data Transfer. This flag is reset after a status read operation. */ + smcStatus.bStatus.xfrDone = 1; + if ((status & SMC_SR_CMDDONE) == SMC_SR_CMDDONE) + /* When set to one, this flag indicates that the NFC has terminated the + Command. This flag is reset after a status read operation.*/ + smcStatus.bStatus.cmdDone = 1; + if ((status & (1<<24)) == (1<<24)) + /* If set to one, this flag indicates that an edge has been detected on + the Ready/Busy Line x. Depending on the EDGE CTRL field located in + the SMC_CFG register, only rising or falling edge is detected. + This flag is reset after a status read operation. */ + smcStatus.bStatus.rbEdge = 1; + if ((status & SMC_SR_ECCRDY) == SMC_SR_ECCRDY) + /* When set to one, this flag indicates that the Hamming ECC + computation is completed. This flag is reset after a status read + operation.*/ + smcStatus.bStatus.hammingReady = 1; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Sets NFC configuration. + * \param cfg NFC configuration. + */ +void SMC_NFC_Configure(uint32_t cfg) +{ + SMC->SMC_CFG = cfg; +} + +/** + * \brief Reset NFC controller. + */ +void SMC_NFC_Reset(void) +{ + /* Disable all the SMC NFC interrupts */ + SMC->SMC_IDR = 0xFFFFFFFF; + SMC->SMC_CTRL = 0; +} + +/** + * \brief Enable NFC controller. + */ +void SMC_NFC_EnableNfc(void) +{ + SMC->SMC_CTRL |= SMC_CTRL_NFCEN; +} + +/** + * \brief Enable NFC controller reads both main and spare area in read mode. + */ +void SMC_NFC_EnableSpareRead(void) +{ + SMC->SMC_CFG |= SMC_CFG_RSPARE; +} + +/** + * \brief The NFC controller skips spare area in read mode. + */ +void SMC_NFC_DisableSpareRead(void) +{ + SMC->SMC_CFG &= (~SMC_CFG_RSPARE); +} + +/** + * \brief Enables the NFC controller writes both main and spare area in write + */ +void SMC_NFC_EnableSpareWrite(void) +{ + SMC->SMC_CFG |= SMC_CFG_WSPARE; +} + +/** + * \brief The NFC controller skips spare area in write mode. + */ +void SMC_NFC_DisableSpareWrite(void) +{ + SMC->SMC_CFG &= (~SMC_CFG_WSPARE); +} + +/** + * \brief Check if spare area be read in read mode. + * + * \return Returns 1 if NFC controller reads both main and spare area in + * read mode, otherwise returns 0. + */ +uint8_t SMC_NFC_isSpareRead(void) +{ + return (((SMC->SMC_CFG) >> 9) & 0x1); +} + +/** + * \brief Check if spare area be written in write mode. + * + * \return Returns 1 if NFC controller writes both main and spare area in + * write mode, otherwise returns 0. + */ +uint8_t SMC_NFC_isSpareWrite(void) +{ + return (((SMC->SMC_CFG) >> 8) & 0x1); +} + +/** + * \brief Check if NFC transfer complete. + * \return Returns 1 if NFC controller has terminated the data transmission, + * otherwise returns 0. + */ +uint8_t SMC_NFC_isTransferComplete(void) +{ + return ((SMC->SMC_SR & SMC_SR_XFRDONE) == SMC_SR_XFRDONE); +} + +/** + * \brief Check Ready/Busy line. + * + * \return Returns 1 if edge has been detected on the Ready/Busy line, + * otherwise returns 0. + */ +uint8_t SMC_NFC_isReadyBusy(void) +{ + return ((SMC->SMC_SR & SMC_SR_RB_EDGE0) == SMC_SR_RB_EDGE0); +} + +/** + * \brief Check if NFC Controller is busy. + * + * \return Returns 1 if NFC Controller is activated and accesses the memory device, + * otherwise returns 0. + */ +uint8_t SMC_NFC_isNfcBusy(void) +{ + return ((SMC->SMC_SR & SMC_SR_NFCBUSY) == SMC_SR_NFCBUSY); +} + +/** + * \brief Get NFC Status. + * + * \return Returns the current status register of SMC NFC Status Register. + * This resets the internal value of the status register, so further + * read may yield different values. + */ +uint32_t SMC_NFC_GetStatus(void) +{ + return SMC->SMC_SR; +} + +/* + * HOST command functions + */ + +/** + * \brief Check if the host controller is busy. + * \return Returns 1 if the host controller is busy, otherwise returns 0. + */ +static uint8_t SMC_NFC_isHostBusy(void) +{ + return (((*((volatile uint32_t *) (NFC_CMD_BASE_ADDR + NFCADDR_CMD_NFCCMD))) + & 0x8000000) == 0x8000000); +} + +/** + * \brief Wait for NFC command has done. + */ +void SMC_NFC_Wait_CommandDone(void) +{ + while (smcStatus.bStatus.cmdDone == 0) + { + SMC_Handler(); + } +} + +/** + * \brief Wait for NFC Data Transfer Terminated. + */ +void SMC_NFC_Wait_XfrDone(void) +{ + while (smcStatus.bStatus.xfrDone == 0) + { + SMC_Handler(); + } +} + +/** + * \brief Wait for NFC Data Transfer Terminated. + */ +void SMC_NFC_Wait_HammingReady(void) +{ + while (smcStatus.bStatus.hammingReady ==0) + { + SMC_Handler(); + } +} + +/** + * \brief Wait for NFC Ready/Busy Line 3 Edge Detected. + */ +void SMC_NFC_Wait_RBbusy(void) +{ + while (smcStatus.bStatus.rbEdge == 0) + { + SMC_Handler(); + } +} + +/** + * \brief Uses the HOST nandflash controller to send a command to the NFC. + * \param cmd command to send. + * \param addressCycle address cycle when command access id decoded. + * \param cycle0 address at first cycle. + */ +void SMC_NFC_SendCommand(uint32_t cmd, uint32_t addressCycle, uint32_t cycle0) +{ + volatile uint32_t *pCommandAddress; + SMC_Clear_Status(); + /* Wait until host controller is not busy. */ + while(SMC_NFC_isHostBusy()); + /* Send the command plus the ADDR_CYCLE */ + pCommandAddress = (volatile uint32_t *) (cmd + NFC_CMD_BASE_ADDR); + SMC->SMC_ADDR = cycle0; + *pCommandAddress = addressCycle; + SMC_NFC_Wait_CommandDone(); +} + +/* ECC function */ + +/** + * \brief Get 24-bit ECC code for 8-bit data path NAND flash. + * 24-bit ECC is generated in order to perform one bit correction + * for 512 byte in page 512/1024/2048/4096 for 8-bit words + * + * \param size Data size in bytes. + * \param code Codes buffer. + */ +static void _smc_ecc_GetW9BitPer512Ecc(uint32_t pageDataSize, uint8_t *code) +{ + uint8_t i; + uint8_t numEcc; + uint32_t eccParity; + uint32_t ecc[16]; + + SMC_ECC_GetValue(ecc); + numEcc = pageDataSize / 512; + /* P2048' P1024' P512' P256' P128' P64' P32' P16' --- 3rd. Ecc Byte to store */ + /* P8' P4' P2' P1' P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */ + /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */ + for (i = 0; i < numEcc; i++) { + /* Get Parity and NParity value. */ + eccParity = ecc[i]; + eccParity = ~eccParity; + code[i * 3] = eccParity & 0xff; + code[i * 3 + 1] = (eccParity >> 8) & 0xff; + code[i * 3 + 2] = (eccParity >> 16) & 0xff; + } +} + +/** + * \brief Get 24-bit ECC code for 8-bit data path NAND flash. + * 24-bit ECC is generated in order to perform one bit correction + * for 256 byte in page 512/1024/2048/4096 for 8-bit words + * + * \param size Data size in bytes. + * \param code Codes buffer. + */ +static void _smc_ecc_GetW8BitPer256Ecc(uint32_t pageDataSize, uint8_t *code) +{ + uint8_t i; + uint8_t numEcc; + uint32_t eccParity; + uint32_t ecc[16]; + + SMC_ECC_GetValue(ecc); + numEcc = pageDataSize / 256; + + /* P2048' P1024' P512' P256' P128' P64' P32' P16' --- 3rd. Ecc Byte to store */ + /* P8' P4' P2' P1' P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */ + /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */ + for (i = 0; i < numEcc; i++) { + /* Get Parity and NParity value. */ + eccParity = ecc[i]; + eccParity = ~eccParity; + TRACE_DEBUG("ecc Parity%d is 0x%08x \n\r", (int)i, (uint32_t)eccParity); + code[i * 3] = eccParity & 0xff; + code[i * 3 + 1] = (eccParity >> 8) & 0xff; + code[i * 3 + 2] = (eccParity >> 16) & 0xff; + } +} + +/** + * \breif Get 32-bit ECC code for 16-bit data path NAND flash. + * 32-bit ECC is generated in order to perform one bit correction + * for a page in page 512/1024/2048/4096 for 16-bit words + * + * \param size Data size in bytes. + * \param code Codes buffer. + */ +static void _smc_ecc_GetW12BitPerPageEcc(uint32_t pageDataSize, uint8_t *code) +{ + uint32_t eccParity; + uint32_t eccNparity; + uint32_t ecc[16]; + + pageDataSize = pageDataSize; /* stop warning */ + /* Get Parity value. */ + SMC_ECC_GetValue(ecc); + + /* ---- P16384'P8192'P4096'P2048' P1024'P512'P256' --- 4th. Ecc Byte to store */ + /* P128' P64' P32' P16' P8' P4' P2' P1' --- 3rd. Ecc Byte to store */ + /* ---- P16384 P8192 P4096 P2048 P1024 P512 P256 --- 2nd. Ecc Byte to store */ + /* P128 P64 P32 P16 P8 P4 P2 P1 --- 1st. Ecc Byte to store */ + + /* Invert codes (linux compatibility) */ + eccParity = ecc[0]; + eccNparity = ecc[1]; + code[0] = eccParity & 0xff; + code[1] = (eccParity >> 8 )& 0xff; + code[2] = eccNparity & 0xff; + code[3] = (eccNparity >> 8 )& 0xff; +} + + +/** + * \brief Configures ECC mode. + * \param type Type of correction. + * \param pageSize Page size of NAND flash device. + */ +void SMC_ECC_Configure(uint32_t type, uint32_t pageSize) +{ + /* Software Reset ECC. */ + SMC->SMC_ECC_CTRL = (0x1 << 1) ; + SMC->SMC_ECC_MD = type | pageSize; +} + +/** + * \brief Get ECC correction type. + * + * \return Returns type of ECC correction setting. + */ +uint32_t SMC_ECC_GetCorrectoinType(void) +{ + return ((SMC->SMC_ECC_MD)& SMC_ECC_MD_TYPCORREC_Msk); +} + +/** + * \brief Get ECC status. + * \param eccNumber ecc parity number from 0 to 15. + * + * \return Returns ECC status by giving ecc number. + */ +uint8_t SMC_ECC_GetStatus(uint8_t eccNumber) +{ + uint32_t status; + + if (eccNumber < 8){ + status = SMC->SMC_ECC_SR1; + } else { + status = SMC->SMC_ECC_SR2; + eccNumber -=8; + } + return ((status >> (eccNumber * 4)) & 0x07); +} + +/** + * \brief Get all ECC parity and Nparity value. + */ +void SMC_ECC_GetValue(uint32_t *ecc) +{ + ecc[0] = SMC->SMC_ECC_PR0; + ecc[1] = SMC->SMC_ECC_PR1; + ecc[2] = SMC->SMC_ECC_PR2; + ecc[3] = SMC->SMC_ECC_PR3; + ecc[4] = SMC->SMC_ECC_PR4; + ecc[5] = SMC->SMC_ECC_PR5; + ecc[6] = SMC->SMC_ECC_PR6; + ecc[7] = SMC->SMC_ECC_PR7; + ecc[8] = SMC->SMC_ECC_PR8; + ecc[9] = SMC->SMC_ECC_PR9; + ecc[10] = SMC->SMC_ECC_PR10; + ecc[11] = SMC->SMC_ECC_PR11; + ecc[12] = SMC->SMC_ECC_PR12; + ecc[13] = SMC->SMC_ECC_PR13; + ecc[14] = SMC->SMC_ECC_PR14; + ecc[15] = SMC->SMC_ECC_PR15; +} + +/** + * \brief verifies 4-bytes hsiao codes for a data block whose size is a page Size + * word. Page words block is verified between the given HSIAO code + * generated by hardware and original HSIAO codes store has been previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + */ +static uint8_t _smc_ecc_VerifyW12BitPerPageEcc( + uint8_t *data, + const uint8_t *originalCode, + const uint8_t *verifyCode) +{ + uint8_t correctionCode[4]; + uint8_t bitCount; + // Xor both codes together + correctionCode[0] = verifyCode[0] ^ originalCode[0]; + correctionCode[1] = verifyCode[1] ^ originalCode[1]; + correctionCode[2] = verifyCode[2] ^ originalCode[2]; + correctionCode[3] = verifyCode[3] ^ originalCode[3]; + TRACE_DEBUG("Correction code = %02X %02X %02X %02X\n\r", + correctionCode[0], correctionCode[1], correctionCode[2], correctionCode[3]); + /* If all bytes are 0, there is no error */ + if ((correctionCode[0] == 0) + && (correctionCode[1] == 0) + && (correctionCode[2] == 0) + && (correctionCode[3] == 0)) { + + return 0; + } + /* If there is a single bit error, there are 15 bits set to 1 */ + bitCount = CountBitsInByte(correctionCode[0]) + + CountBitsInByte(correctionCode[1]) + + CountBitsInByte(correctionCode[2]) + + CountBitsInByte(correctionCode[3]); + if (bitCount == 15) { + /* Get byte and bit indexes */ + uint16_t byte = (correctionCode[0] & 0xf0) >> 4; + byte |= (correctionCode[1] & 0xff) << 4; + uint8_t bit = correctionCode[0] & 0x0f; + /* Correct bit */ + printf("Correcting byte #%d at bit %d\n\r", byte, bit); + data[byte] ^= (1 << bit); + + return Hsiao_ERROR_SINGLEBIT; + } + + /* Check if ECC has been corrupted */ + if (bitCount == 1) { + return Hsiao_ERROR_ECC; + } + /* Otherwise, this is a multi-bit error */ + else { + return Hsiao_ERROR_MULTIPLEBITS; + } +} + +/** + * \brief verifies 3-bytes hsiao codes for a data block whose size is a page Size + * word. Page words block is verified between the given HSIAO code + * generated by hardware and original HSIAO codes store has been previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + */ +static uint8_t _smc_ecc_VerifyW8BitPer256Ecc( + uint8_t *data, + uint32_t size, + const uint8_t *originalCode, + const uint8_t *verifyCode) +{ + uint8_t correctionCode[3]; + uint32_t position = 0; + uint8_t byte; + uint8_t bit; + uint8_t error = 0; + + TRACE_DEBUG("_smc_ecc_VerifyW8BitPer256Ecc()\n\r"); + while (position < size) { + /* Xor both codes together */ + correctionCode[0] = verifyCode[0] ^ originalCode[0]; + correctionCode[1] = verifyCode[1] ^ originalCode[1]; + correctionCode[2] = verifyCode[2] ^ originalCode[2]; + TRACE_DEBUG("Correction code = %02X %02X %02X\n\r", + correctionCode[0], correctionCode[1], correctionCode[2]); + + /* If all bytes are 0, there is no error */ + if ( correctionCode[0] || correctionCode[1] || correctionCode[2]) { + /* If there is a single bit error, there are 11 bits set to 1 */ + if (CountBitsInCode(correctionCode) == 11) { + /* Get byte and bit indexes */ + byte = (correctionCode[0] & 0xf8) >> 3; + byte |= (correctionCode[1] & 0x07) << 5; + bit = correctionCode[0] & 0x07; + /* Correct bit */ + printf("Correcting byte #%u at bit %u\n\r", (unsigned int)(position + byte), (unsigned int)bit); + data[byte] ^= (1 << bit); + error = Hsiao_ERROR_SINGLEBIT; + } + /* Check if ECC has been corrupted */ + else if (CountBitsInCode(correctionCode) == 1) { + return Hsiao_ERROR_ECC; + } else { + /* Otherwise, this is a multi-bit error */ + return Hsiao_ERROR_MULTIPLEBITS; + } + } + data += 256; + originalCode += 3; + verifyCode += 3; + position += 256; + } + return error; +} + +/** + * \brief 3-bytes hsiao codes for a data block whose size is multiple of + * 512 bytes. Each 512-bytes block is verified between the given HSIAO code + * generated by hardware and original HSIAO codes store has been previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + */ +static uint8_t _smc_ecc_VerifyW9BitPer512Ecc( + uint8_t *data, + uint32_t size, + const uint8_t *originalCode, + const uint8_t *verifyCode) +{ + uint8_t correctionCode[3]; + uint32_t position = 0; + uint16_t byte; + uint8_t bit; + uint8_t error = 0; + + TRACE_DEBUG("_smc_ecc_VerifyW9BitPer512Ecc()\n\r"); + while (position < size) { + /* Xor both codes together */ + correctionCode[0] = verifyCode[0] ^ originalCode[0]; + correctionCode[1] = verifyCode[1] ^ originalCode[1]; + correctionCode[2] = verifyCode[2] ^ originalCode[2]; + TRACE_DEBUG("Correction code = %02X %02X %02X\n\r", + correctionCode[0], correctionCode[1], correctionCode[2]); + + /* If all bytes are 0, there is no error */ + if ( correctionCode[0] || correctionCode[1] || correctionCode[2]) { + // If there is a single bit error, there are 11 bits set to 1 + if (CountBitsInCode(correctionCode) == 12) { + /* Get byte and bit indexes */ + byte = (correctionCode[0] & 0xf8) >> 3; + byte |= (correctionCode[1] & 0x0f) << 5; + bit = correctionCode[0] & 0x07; + /* Correct bit */ + printf("Correcting byte #%u at bit %u\n\r", + (unsigned int)(position + byte), (unsigned int)bit); + data[byte] ^= (1 << bit); + error = Hsiao_ERROR_SINGLEBIT; + } + /* Check if ECC has been corrupted */ + else if (CountBitsInCode(correctionCode) == 1) { + return Hsiao_ERROR_ECC; + } else { + /* Otherwise, this is a multi-bit error */ + return Hsiao_ERROR_MULTIPLEBITS; + } + } + data += 512; + originalCode += 3; + verifyCode += 3; + position += 512; + } + return error; +} + +/** + * Get ECC code for 8bit/16-bit data path NAND flash by giving data path. + * 24-bit or 32-bit ECC is generated in order to perform one bit correction + * for a page in page 512/1024/2048/4096. + * + * \param size Data size in bytes. + * \param code Codes buffer. + * \param busWidth 8bit/16bit data path. + */ +void SMC_ECC_GetEccParity(uint32_t pageDataSize, uint8_t *code, uint8_t busWidth) +{ + uint8_t correctionType; + + correctionType = SMC_ECC_GetCorrectoinType(); + /* For 16-bit data path */ + if (busWidth == 16 && correctionType == SMC_ECC_MD_TYPCORREC_CPAGE ) + _smc_ecc_GetW12BitPerPageEcc(pageDataSize, code); + /* For 8-bit data path */ + else { + switch (correctionType){ + case SMC_ECC_MD_TYPCORREC_CPAGE: + _smc_ecc_GetW12BitPerPageEcc(pageDataSize, code); + break; + case SMC_ECC_MD_TYPCORREC_C256B: + _smc_ecc_GetW8BitPer256Ecc(pageDataSize, code); + break; + case SMC_ECC_MD_TYPCORREC_C512B: + _smc_ecc_GetW9BitPer512Ecc(pageDataSize, code); + break; + } + } +} + + +/** + * Verifies hsiao codes for a data block. The block is verified between the given + * HSIAO code generated by hardware and original HSIAO codes store has been + * previously stored. + * Returns 0 if the data is correct, Hsiao_ERROR_SINGLEBIT if one or more + * block(s) have had a single bit corrected, or either Hsiao_ERROR_ECC + * or Hsiao_ERROR_MULTIPLEBITS. + * \param data Data buffer to verify. + * \param size Size of the data in words. + * \param originalCode Original codes. + * \param verifyCode codes to be verified. + * \param dataPath 8bit/16bit data path. + */ +uint8_t SMC_ECC_VerifyHsiao( + uint8_t *data, + uint32_t size, + const uint8_t *originalCode, + const uint8_t *verifyCode, + uint8_t busWidth) +{ + uint8_t correctionType; + uint8_t error = 0; + correctionType = SMC_ECC_GetCorrectoinType(); + /* For 16-bit data path */ + if (busWidth == 16 && (correctionType == SMC_ECC_MD_TYPCORREC_CPAGE) ) { + error = _smc_ecc_VerifyW12BitPerPageEcc((uint8_t*)data, originalCode, verifyCode); + } + /* For 8-bit data path */ + else { + switch (correctionType){ + case SMC_ECC_MD_TYPCORREC_CPAGE: + error = _smc_ecc_VerifyW12BitPerPageEcc(data, originalCode, verifyCode); + break; + case SMC_ECC_MD_TYPCORREC_C256B: + error = _smc_ecc_VerifyW8BitPer256Ecc(data, size, originalCode, verifyCode); + break; + case SMC_ECC_MD_TYPCORREC_C512B: + error = _smc_ecc_VerifyW9BitPer512Ecc(data, size, originalCode, verifyCode); + break; + } + } + return error; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/spi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/spi.c new file mode 100644 index 000000000..13408fe08 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/spi.c @@ -0,0 +1,279 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup spi_module Working with SPI + * The SPI driver provides the interface to configure and use the SPI + * peripheral. + * + * The Serial Peripheral Interface (SPI) circuit is a synchronous serial + * data link that provides communication with external devices in Master + * or Slave Mode. + * + * To use the SPI, the user has to follow these few steps: + * -# Enable the SPI pins required by the application (see pio.h). + * -# Configure the SPI using the \ref SPI_Configure(). This enables the + * peripheral clock. The mode register is loaded with the given value. + * -# Configure all the necessary chip selects with \ref SPI_ConfigureNPCS(). + * -# Enable the SPI by calling \ref SPI_Enable(). + * -# Send/receive data using \ref SPI_Write() and \ref SPI_Read(). Note that + * \ref SPI_Read() + * must be called after \ref SPI_Write() to retrieve the last value read. + * -# Disable the SPI by calling \ref SPI_Disable(). + * + * For more accurate information, please look at the SPI section of the + * Datasheet. + * + * Related files :\n + * \ref spi.c\n + * \ref spi.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of Serial Peripheral Interface (SPI) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables a SPI peripheral. + * + * \param spi Pointer to an SPI instance. + */ +extern void SPI_Enable( Spi* spi ) +{ + spi->SPI_CR = SPI_CR_SPIEN ; +} + +/** + * \brief Disables a SPI peripheral. + * + * \param spi Pointer to an SPI instance. + */ +extern void SPI_Disable( Spi* spi ) +{ + spi->SPI_CR = SPI_CR_SPIDIS ; +} + +/** + * \brief Enables one or more interrupt sources of a SPI peripheral. + * + * \param spi Pointer to an SPI instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void SPI_EnableIt( Spi* spi, uint32_t dwSources ) +{ + spi->SPI_IER = dwSources ; +} + +/** + * \brief Disables one or more interrupt sources of a SPI peripheral. + * + * \param spi Pointer to an SPI instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +extern void SPI_DisableIt( Spi* spi, uint32_t dwSources ) +{ + spi->SPI_IDR = dwSources ; +} + +/** + * \brief Configures a SPI peripheral as specified. The configuration can be + * computed using several macros (see \ref spi_configuration_macros). + * + * \param spi Pointer to an SPI instance. + * \param id Peripheral ID of the SPI. + * \param configuration Value of the SPI configuration register. + */ +extern void SPI_Configure( Spi* spi, uint32_t dwId, uint32_t dwConfiguration ) +{ + PMC_EnablePeripheral( dwId ) ; + + spi->SPI_CR = SPI_CR_SPIDIS ; + + /* Execute a software reset of the SPI twice */ + spi->SPI_CR = SPI_CR_SWRST ; + spi->SPI_CR = SPI_CR_SWRST ; + spi->SPI_MR = dwConfiguration ; +} + +/** + * \brief Configures SPI chip select. + * + * \param spi Pointer to an SPI instance. + * \param cS Chip select of NPSCx. + */ +extern void SPI_ChipSelect( Spi* spi, uint8_t cS) +{ + spi->SPI_MR |= SPI_MR_PCS_Msk ; + spi->SPI_MR &= ~(SPI_MR_PCS ( cS )) ; +} + +/** + * \brief Configures SPI Mode Register. + * + * \param spi Pointer to an SPI instance. + * \param configuration Value of the SPI mode register. + */ +extern void SPI_SetMode( Spi* spi, + uint32_t dwConfiguration ) +{ + spi->SPI_MR = dwConfiguration ; +} + +/** + * \brief Configures SPI to release last used CS line. + * + * \param spi Pointer to an SPI instance. + */ +extern void SPI_ReleaseCS( Spi* spi ) +{ + spi->SPI_CR = SPI_CR_LASTXFER ; +} + + +/** + * \brief Configures a chip select of a SPI peripheral. The chip select + * configuration is computed using several macros + * (see \ref spi_configuration_macros). + * + * \param spi Pointer to an SPI instance. + * \param npcs Chip select to configure (0, 1, 2 or 3). + * \param configuration Desired chip select configuration. + */ +void SPI_ConfigureNPCS( Spi* spi, uint32_t dwNpcs, uint32_t dwConfiguration ) +{ + spi->SPI_CSR[dwNpcs] = dwConfiguration ; +} + +/** + * \brief Configures a chip select active mode of a SPI peripheral. + * + * \param spi Pointer to an SPI instance. + * \param dwNpcs Chip select to configure (0, 1, 2 or 3). + * \param bReleaseOnLast CS controlled by last transfer. + * SPI_ReleaseCS() is used to release CS. + */ +void SPI_ConfigureCSMode( Spi* spi, uint32_t dwNpcs, uint32_t bReleaseOnLast ) +{ + if (bReleaseOnLast) { + spi->SPI_CSR[dwNpcs] |= SPI_CSR_CSAAT; + } else { + spi->SPI_CSR[dwNpcs] &= ~SPI_CSR_CSAAT; + } +} + +/** + * \brief Get the current status register of the given SPI peripheral. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param spi Pointer to a Spi instance. + * \return SPI status register. + */ +extern uint32_t SPI_GetStatus( Spi* spi ) +{ + return spi->SPI_SR ; +} + +/** + * \brief Reads and returns the last word of data received by a SPI peripheral. + * This method must be called after a successful SPI_Write call. + * + * \param spi Pointer to an Spi instance. + * + * \return read data. + */ +extern uint32_t SPI_Read( Spi* spi ) +{ + while ( (spi->SPI_SR & SPI_SR_RDRF) == 0 ) ; + + return spi->SPI_RDR & 0xFFFF ; +} + +/** + * \brief Sends data through a SPI peripheral. If the SPI is configured to use a + * fixed peripheral select, the npcs value is meaningless. Otherwise, + * it identifies the component which shall be addressed. + * + * \param spi Pointer to an SPI instance. + * \param npcs Chip select of the component to address (0, 1, 2 or 3). + * \param data Word of data to send. + */ +extern void SPI_Write( Spi* spi, uint32_t dwNpcs, uint16_t wData ) +{ + /* Send data */ + while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ; + spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) ; + while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ; +} + +/** + * \brief Sends last data through a SPI peripheral. + * If the SPI is configured to use a fixed peripheral select, the npcs value is + * meaningless. Otherwise, it identifies the component which shall be addressed. + * + * \param spi Pointer to an SPI instance. + * \param npcs Chip select of the component to address (0, 1, 2 or 3). + * \param data Word of data to send. + */ +extern void SPI_WriteLast( Spi* spi, uint32_t dwNpcs, uint16_t wData ) +{ + /* Send data */ + while ( (spi->SPI_SR & SPI_SR_TXEMPTY) == 0 ) ; + spi->SPI_TDR = wData | SPI_PCS( dwNpcs ) | SPI_TDR_LASTXFER ; + while ( (spi->SPI_SR & SPI_SR_TDRE) == 0 ) ; +} + +/** + * \brief Check if SPI transfer finish. + * + * \param spi Pointer to an SPI instance. + * + * \return Returns 1 if there is no pending write operation on the SPI; + * otherwise returns 0. + */ +extern uint32_t SPI_IsFinished( Spi* spi ) +{ + return ((spi->SPI_SR & SPI_SR_TXEMPTY) != 0) ; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/spi_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/spi_dma.c new file mode 100644 index 000000000..fbe8fb6b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/spi_dma.c @@ -0,0 +1,380 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \addtogroup spi_dma_module SPI xDMA driver + * \ingroup lib_spiflash + * \section Usage + * + *
      + *
    • SPID_Configure() initializes and configures the SPI peripheral and xDMA + * for data transfer.
      • + *
    • Configures the parameters for the device corresponding to the cs value + * by SPID_ConfigureCS().
      • + *
    • Starts a SPI master transfer. This is a non blocking function + * SPID_SendCommand(). It will + * return as soon as the transfer is started..
      • + *
    + * + */ + +/** + * \file + * + * Implementation for the SPI Flash with xDMA driver. + * + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Definitions + *----------------------------------------------------------------------------*/ + +/** xDMA support */ +#define USE_SPI_DMA + +/** xDMA Link List size for SPI transmission*/ +#define DMA_SPI_LLI 2 + +/*---------------------------------------------------------------------------- + * Macros + *----------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------- + * Local Variables + *----------------------------------------------------------------------------*/ + + +/* DMA driver instance */ +static uint32_t spiDmaTxChannel; +static uint32_t spiDmaRxChannel; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief SPI xDMA Rx callback + * Invoked on SPi DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to Spid instance. + */ +static void SPID_Rx_Cb(uint32_t channel, Spid* pArg) +{ + SpidCmd *pSpidCmd = pArg->pCurrentCommand; + Spi *pSpiHw = pArg->pSpiHw; + if (channel != spiDmaRxChannel) + return; + + /* Disable the SPI TX & RX */ + SPI_Disable ( pSpiHw ); + TRACE_INFO("SPI Rx DMA Callback has been called %d bytes received\n\r", + pArg->pCurrentCommand->RxSize); + /* Configure and enable interrupt on RC compare */ + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_DisableIRQ(XDMAC_IRQn); + + /* Disable the SPI Peripheral */ + PMC_DisablePeripheral ( pArg->spiId ); + + /* Release CS */ + SPI_ReleaseCS(pSpiHw); + + /* Release the DMA channels */ + XDMAD_FreeChannel(pArg->pXdmad, spiDmaRxChannel); + XDMAD_FreeChannel(pArg->pXdmad, spiDmaTxChannel); + SCB_CleanInvalidateDCache(); + /* Release the dataflash semaphore */ + pArg->semaphore++; + + printf(" %s\n\r",pArg->pCurrentCommand->pRxBuff); + + /* Invoke the callback associated with the current command */ + if (pSpidCmd && pSpidCmd->callback) { + //printf("p %d", pArg->semaphore); + pSpidCmd->callback(0, pSpidCmd->pArgument); + } +} + +/** + * \brief Configure the DMA Channels: 0 RX, 1 TX. + * Channels are disabled after configure. + * \returns 0 if the dma channel configuration successfully; otherwise returns + * SPID_ERROR_XXX. + */ +static uint8_t _spid_configureDmaChannels( Spid* pSpid ) +{ + /* Driver initialize */ + XDMAD_Initialize( pSpid->pXdmad, 0 ); + + XDMAD_FreeChannel( pSpid->pXdmad, spiDmaTxChannel); + XDMAD_FreeChannel( pSpid->pXdmad, spiDmaRxChannel); + + /* Allocate a DMA channel for SPI0/1 TX. */ + spiDmaTxChannel = XDMAD_AllocateChannel( pSpid->pXdmad, + XDMAD_TRANSFER_MEMORY, pSpid->spiId); + if ( spiDmaTxChannel == XDMAD_ALLOC_FAILED ) { + return SPID_ERROR; + } + /* Allocate a DMA channel for SPI0/1 RX. */ + spiDmaRxChannel = + XDMAD_AllocateChannel( pSpid->pXdmad, pSpid->spiId, XDMAD_TRANSFER_MEMORY); + if ( spiDmaRxChannel == XDMAD_ALLOC_FAILED ) { + return SPID_ERROR; + } + + /* Setup callbacks for SPI0/1 RX */ + XDMAD_SetCallback(pSpid->pXdmad, spiDmaRxChannel, + (XdmadTransferCallback)SPID_Rx_Cb, pSpid); + if (XDMAD_PrepareChannel( pSpid->pXdmad, spiDmaRxChannel )) + return SPID_ERROR; + + /* Setup callbacks for SPI0/1 TX (ignored) */ + XDMAD_SetCallback(pSpid->pXdmad, spiDmaTxChannel, NULL, NULL); + if ( XDMAD_PrepareChannel( pSpid->pXdmad, spiDmaTxChannel )) + return SPID_ERROR; + return 0; +} + +/** + * \brief Configure the DMA source and destination with Linker List mode. + * + * \param pCommand Pointer to command + * \returns 0 if the dma multibuffer configuration successfully; otherwise + * returns SPID_ERROR_XXX. + */ +static uint8_t _spid_configureLinkList(Spi *pSpiHw, void *pXdmad, SpidCmd *pCommand) +{ + sXdmadCfg xdmadRxCfg,xdmadTxCfg; + uint32_t xdmaCndc, xdmaInt; + uint32_t spiId; + if ((unsigned int)pSpiHw == (unsigned int)SPI0 ) spiId = ID_SPI0; + if ((unsigned int)pSpiHw == (unsigned int)SPI1 ) spiId = ID_SPI1; + + /* Setup TX */ + + xdmadTxCfg.mbr_sa = (uint32_t)pCommand->pTxBuff; + + xdmadTxCfg.mbr_da = (uint32_t)&pSpiHw->SPI_TDR; + + xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | + XDMA_UBC_NDE_FETCH_DIS| + XDMA_UBC_NSEN_UPDATED | pCommand->TxSize; + + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( spiId, XDMAD_TRANSFER_TX )); + + + xdmadTxCfg.mbr_bc = 0; + xdmadTxCfg.mbr_sus = 0; + xdmadTxCfg.mbr_dus =0; + + /* Setup RX Link List */ + + xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | + XDMA_UBC_NDE_FETCH_DIS| + XDMA_UBC_NDEN_UPDATED | pCommand->RxSize; + + xdmadRxCfg.mbr_da = (uint32_t)pCommand->pRxBuff; + + xdmadRxCfg.mbr_sa = (uint32_t)&pSpiHw->SPI_RDR; + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( spiId, XDMAD_TRANSFER_RX )); + + + xdmadRxCfg.mbr_bc = 0; + xdmadRxCfg.mbr_sus = 0; + xdmadRxCfg.mbr_dus =0; + + xdmaCndc = 0; + + /* Put all interrupts on for non LLI list setup of DMA */ + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + if (XDMAD_ConfigureTransfer( pXdmad, spiDmaRxChannel, &xdmadRxCfg, xdmaCndc, 0, xdmaInt)) + return SPID_ERROR; + + if (XDMAD_ConfigureTransfer( pXdmad, spiDmaTxChannel, &xdmadTxCfg, xdmaCndc, 0, xdmaInt)) + return SPID_ERROR; + return 0; +} + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes the Spid structure and the corresponding SPI & DMA hardware. + * select value. + * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX. + * The DMA channels are freed automatically when no SPI command processing. + * + * \param pSpid Pointer to a Spid instance. + * \param pSpiHw Associated SPI peripheral. + * \param spiId SPI peripheral identifier. + * \param pDmad Pointer to a Dmad instance. + */ +uint32_t SPID_Configure( Spid *pSpid , + Spi *pSpiHw , + uint8_t spiId, + uint32_t spiMode, + sXdmad *pXdmad ) +{ + /* Initialize the SPI structure */ + pSpid->pSpiHw = pSpiHw; + pSpid->spiId = spiId; + pSpid->semaphore = 1; + pSpid->pCurrentCommand = 0; + pSpid->pXdmad = pXdmad; + + /* Enable the SPI Peripheral ,Execute a software reset of the SPI, + Configure SPI in Master Mode*/ + SPI_Configure ( pSpiHw, pSpid->spiId, spiMode ); + + return 0; +} + +/** + * \brief Configures the parameters for the device corresponding to the cs value. + * + * \param pSpid Pointer to a Spid instance. + * \param cs number corresponding to the SPI chip select. + * \param csr SPI_CSR value to setup. + */ +void SPID_ConfigureCS( Spid *pSpid, + uint32_t dwCS, + uint32_t dwCsr) +{ + Spi *pSpiHw = pSpid->pSpiHw; + + /* Enable the SPI Peripheral */ + PMC_EnablePeripheral (pSpid->spiId ); + /* Configure SPI Chip Select Register */ + SPI_ConfigureNPCS( pSpiHw, dwCS, dwCsr ); + + /* Disable the SPI Peripheral */ + PMC_DisablePeripheral (pSpid->spiId ); + +} + +/** + * \brief Starts a SPI master transfer. This is a non blocking function. It will + * return as soon as the transfer is started. + * + * \param pSpid Pointer to a Spid instance. + * \param pCommand Pointer to the SPI command to execute. + * \returns 0 if the transfer has been started successfully; otherwise returns + * SPID_ERROR_LOCK is the driver is in use, or SPID_ERROR if the command is not + * valid. + */ +uint32_t SPID_SendCommand( Spid *pSpid, SpidCmd *pCommand) +{ + Spi *pSpiHw = pSpid->pSpiHw; + + /* Try to get the dataflash semaphore */ + if (pSpid->semaphore == 0) { + return SPID_ERROR_LOCK; + } + pSpid->semaphore--; + + /* Enable the SPI Peripheral */ + PMC_EnablePeripheral (pSpid->spiId ); + + /* SPI chip select */ + SPI_ChipSelect (pSpiHw, 1 << pCommand->spiCs); + + // Initialize the callback + pSpid->pCurrentCommand = pCommand; + + /* Initialize DMA controller using channel 0 for RX, 1 for TX. */ + if (_spid_configureDmaChannels(pSpid) ) + return SPID_ERROR_LOCK; + + /* Configure and enable interrupt on RC compare */ + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority( XDMAC_IRQn ,1); + NVIC_EnableIRQ(XDMAC_IRQn); + + + if (_spid_configureLinkList(pSpiHw, pSpid->pXdmad, pCommand)) + return SPID_ERROR_LOCK; + + /* Enables the SPI to transfer and receive data. */ + SPI_Enable (pSpiHw ); + SCB_CleanInvalidateDCache(); + /* Start DMA 0(RX) && 1(TX) */ + if (XDMAD_StartTransfer( pSpid->pXdmad, spiDmaRxChannel )) + return SPID_ERROR_LOCK; + if (XDMAD_StartTransfer( pSpid->pXdmad, spiDmaTxChannel )) + return SPID_ERROR_LOCK; + + return 0; +} + +/** + * \brief Check if the SPI driver is busy. + * + * \param pSpid Pointer to a Spid instance. + * \returns 1 if the SPI driver is currently busy executing a command; otherwise + */ +uint32_t SPID_IsBusy(const Spid *pSpid) +{ + if (pSpid->semaphore == 0) { + return 1; + } else { + return 0; + } +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/ssc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/ssc.c new file mode 100644 index 000000000..8091b3c6b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/ssc.c @@ -0,0 +1,216 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup ssc_module Working with SSC + * The SSC driver provides the interface to configure and use the SSC + * peripheral. + * + * !Usage + * + * -# Enable the SSC interface pins. + * -# Configure the SSC to operate at a specific frequency by calling + * SSC_Configure(). This function enables the peripheral clock of the SSC, + * but not its PIOs. + * -# Configure the transmitter and/or the receiver using the + * SSC_ConfigureTransmitter() and SSC_ConfigureEmitter() functions. + * -# Enable the PIOs or the transmitter and/or the received. + * -# Enable the transmitter and/or the receiver using SSC_EnableTransmitter() + * and SSC_EnableReceiver() + * -# Send data through the transmitter using SSC_Write() + * -# Receive data from the receiver using SSC_Read() + * -# Disable the transmitter and/or the receiver using SSC_DisableTransmitter() + * and SSC_DisableReceiver() + * + * For more accurate information, please look at the SSC section of the + * Datasheet. + * + * Related files :\n + * \ref ssc.c\n + * \ref ssc.h.\n + */ +/*@{*/ +/*@}*/ + + +/** + * \file + * + * Implementation of Synchronous Serial (SSC) controller. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a SSC peripheral.If the divided clock is not used, the + * master clock frequency can be set to 0. + * \note The emitter and transmitter are disabled by this function. + * \param ssc Pointer to an SSC instance. + * \param bitRate bit rate. + * \param masterClock master clock. + */ +void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock) +{ + uint32_t id; + // uint32_t maxClock; + id = ID_SSC ; + // maxClock = PMC_SetPeriMaxClock(id, masterClock); + + /* Reset, disable receiver & transmitter */ + ssc->SSC_CR = SSC_CR_RXDIS | SSC_CR_TXDIS | SSC_CR_SWRST; + + /* Configure clock frequency */ + if (bitRate != 0) { + ssc->SSC_CMR = masterClock / (2 * bitRate); + } else { + ssc->SSC_CMR = 0; + } + /* Enable SSC peripheral clock */ + PMC_EnablePeripheral(id); +} + +/** + * \brief Configures the transmitter of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param tcmr Transmit Clock Mode Register value. + * \param tfmr Transmit Frame Mode Register value. + */ +void SSC_ConfigureTransmitter(Ssc *ssc,uint32_t tcmr, uint32_t tfmr) +{ + ssc->SSC_TCMR = tcmr; + ssc->SSC_TFMR = tfmr; +} + +/** + * \brief Configures the receiver of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param rcmr Receive Clock Mode Register value. + * \param rfmr Receive Frame Mode Register value. + */ +void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr) +{ + ssc->SSC_RCMR = rcmr; + ssc->SSC_RFMR = rfmr; +} + +/** + * \brief Enables the transmitter of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_EnableTransmitter(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_TXEN; +} + +/** + * \brief Disables the transmitter of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_DisableTransmitter(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_TXDIS; +} + +/** + * \brief Enables the receiver of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_EnableReceiver(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_RXEN; +} + +/** + * \brief Disables the receiver of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + */ +void SSC_DisableReceiver(Ssc *ssc) +{ + ssc->SSC_CR = SSC_CR_RXDIS; +} + +/** + * \brief Enables one or more interrupt sources of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources) +{ + ssc->SSC_IER = sources; +} + +/** + * \brief Disables one or more interrupt sources of a SSC peripheral. + * \param ssc Pointer to an SSC instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources) +{ + ssc->SSC_IDR = sources; +} + +/** + * \brief Sends one data frame through a SSC peripheral. If another frame is currently + * being sent, this function waits for the previous transfer to complete. + * \param ssc Pointer to an SSC instance. + * \param frame Data frame to send. + */ +void SSC_Write(Ssc *ssc, uint32_t frame) +{ + while ((ssc->SSC_SR & SSC_SR_TXRDY) == 0); + ssc->SSC_THR = frame; +} + +/** + * \brief Waits until one frame is received on a SSC peripheral, and returns it. + * \param ssc Pointer to an SSC instance. + */ +uint32_t SSC_Read(Ssc *ssc) +{ + while ((ssc->SSC_SR & SSC_SR_RXRDY) == 0); + return ssc->SSC_RHR; +} + +/** + * \brief Return 1 if one frame is received, 0 otherwise. + * \param ssc Pointer to an SSC instance. + */ +uint8_t SSC_IsRxReady(Ssc *ssc) +{ + return ((ssc->SSC_SR & SSC_SR_RXRDY) > 0); +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/supc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/supc.c new file mode 100644 index 000000000..fabf9031c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/supc.c @@ -0,0 +1,195 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Select external 32K Crystal. + * + */ + +void SUPC_SelectExtCrystal32K(void) +{ + PMC_EnableXT32KFME(); + /* Select XTAL 32k instead of internal slow RC 32k for slow clock */ + if ( (SUPC->SUPC_SR & SUPC_SR_OSCSEL) != SUPC_SR_OSCSEL_CRYST ) { + SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL_CRYSTAL_SEL; + while( !(SUPC->SUPC_SR & SUPC_SR_OSCSEL) ); + } +} + +/** + * \brief VROFF asserts the vddcore_nreset and stops the voltage regulator + * + */ +void SUPC_DisableVoltageReg(void) +{ + SUPC->SUPC_CR |= SUPC_CR_KEY_PASSWD | SUPC_CR_VROFF; +} + +/** + * \brief Configures supply monitor + * + */ +void SUPC_ConfigSupplyMonitor(uint32_t Config) +{ + SUPC->SUPC_SMMR = Config; +} + + +/** + * \brief Disables supply monitor + * + */ +void SUPC_DisableSupplyMonitor(void) +{ + SUPC->SUPC_SMMR = SUPC_SMMR_SMSMPL_SMD; +} + + +/** + * \brief Enables/Disables Brownout detector + * + */ +void SUPC_BrownoutDetectEnable(uint8_t enable) +{ + if(enable) { + SUPC->SUPC_MR = ( SUPC_MR_BODDIS_ENABLE | SUPC_MR_KEY_PASSWD); + } else { + SUPC->SUPC_MR = ( SUPC_MR_BODDIS_DISABLE | SUPC_MR_KEY_PASSWD); + } +} + +/** + * \brief Enables Brownout Detector Reset + * + */ +void SUPC_BrownoutResetEnable(void) +{ + SUPC->SUPC_MR = ( SUPC_MR_BODRSTEN_ENABLE | SUPC_MR_KEY_PASSWD); +} + + +/** + * \brief Enables/Disables Sram in backup mode + * + */ +void SUPC_SramBackupMode(uint8_t enable) +{ + if(enable) { + SUPC->SUPC_MR = ((1 << 17) | SUPC_MR_KEY_PASSWD); + } else { + SUPC->SUPC_MR = ( (0 << 17) | SUPC_MR_KEY_PASSWD); + } +} + +/** + * \brief Bypass external 32.768KHz oscillator + * + */ +void SUPC_BypassXtal32KOsc(void) +{ + SUPC->SUPC_MR = ( SUPC_MR_OSCBYPASS_BYPASS | SUPC_MR_KEY_PASSWD); +} + + +/** + * \brief Enables/Disables Wakeup mode + * + */ +void SUPC_EnablesWakeupMode(uint32_t Regs, uint8_t enable) +{ + if(enable) { + SUPC->SUPC_WUMR |= Regs; + } else { + SUPC->SUPC_WUMR &= ~(uint32_t)Regs; + } +} + +/** + * \brief Configure Wakeup denounce period + * + */ +void SUPC_SetWakeupDebounce(uint8_t period) +{ + SUPC->SUPC_WUMR |= ( (period << SUPC_WUMR_WKUPDBC_Pos) & SUPC_WUMR_WKUPDBC_Msk); +} + +/** + * \brief Configure Low-power denounce period + * + */ +void SUPC_SetLowPowerDebounce(uint8_t period) +{ + SUPC->SUPC_WUMR |= ( (period << SUPC_WUMR_LPDBC_Pos) & SUPC_WUMR_LPDBC_Msk); +} + + +/** + * \brief Enables/Disables Wakeup Inputs + * + */ +void SUPC_EnablesWakeupInput(uint32_t Input, uint8_t enable) +{ + if(enable) { + SUPC->SUPC_WUIR |= Input; + } else { + SUPC->SUPC_WUIR &= ~(uint32_t)Input; + } +} + +/** + * \brief Checks if Crystal oscillator is selected as a slow clock + */ + +uint8_t SUPC_IsSlowClkExtCrystal32K(void) +{ + return ((SUPC->SUPC_SR & SUPC_SR_OSCSEL) >> 7); +} + +/** + * \brief Checks if Crystal oscillator is selected as a slow clock + */ + +uint8_t SUPC_Read_Status(uint32_t status) +{ + return (SUPC->SUPC_SR & status); +} + + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/tc.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/tc.c new file mode 100644 index 000000000..940efe9e9 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/tc.c @@ -0,0 +1,200 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup tc_module + * The TC driver provides the Interface to configure the Timer Counter (TC). + * + * \section Usage + *
      + *
    • Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically.
      • + *
    • Configure a Timer Counter in the desired mode using TC_Configure().
      • + *
    • Start or stop the timer clock using TC_Start() and TC_Stop().
      • + * + *
    + * For more accurate information, please look at the TC section of the Datasheet. + * + * Related files :\n + * \ref tc.c\n + * \ref tc.h.\n +*/ + + /** + * \file + * + * \section Purpose + * + * Interface for configuring and using Timer Counter (TC) peripherals. + * + * \section Usage + * -# Optionally, use TC_FindMckDivisor() to let the program find the best + * TCCLKS field value automatically. + * -# Configure a Timer Counter in the desired mode using TC_Configure(). + * -# Start or stop the timer clock using TC_Start() and TC_Stop(). + */ + +/** + * \file + * + * Implementation of Timer Counter (TC). + * + */ + +/*------------------------------------------------------------------------------ + * Headers + *-----------------------------------------------------------------------------*/ + +#include "board.h" + +#include + +/*------------------------------------------------------------------------------ + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a Timer Counter Channel + * + * Configures a Timer Counter to operate in the given mode. Timer is stopped + * after configuration and must be restarted with TC_Start(). All the + * interrupts of the timer are also disabled. + * + * \param pTc Pointer to a Tc instance. + * \param channel Channel number. + * \param mode Operating mode (TC_CMR value). + */ +extern void TC_Configure( Tc *pTc, uint32_t dwChannel, uint32_t dwMode ) +{ + TcChannel* pTcCh ; + + assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ; + pTcCh = pTc->TC_CHANNEL+dwChannel ; + + /* Disable TC clock */ + pTcCh->TC_CCR = TC_CCR_CLKDIS ; + + /* Disable interrupts */ + pTcCh->TC_IDR = 0xFFFFFFFF ; + + /* Clear status register */ + pTcCh->TC_SR ; + + /* Set mode */ + pTcCh->TC_CMR = dwMode ; +} + +/** + * \brief Reset and Start the TC Channel + * + * Enables the timer clock and performs a software reset to start the counting. + * + * \param pTc Pointer to a Tc instance. + * \param dwChannel Channel number. + */ +extern void TC_Start( Tc *pTc, uint32_t dwChannel ) +{ + TcChannel* pTcCh ; + + assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ; + + pTcCh = pTc->TC_CHANNEL+dwChannel ; + pTcCh->TC_CCR = TC_CCR_CLKEN | TC_CCR_SWTRG ; +} + +/** + * \brief Stop TC Channel + * + * Disables the timer clock, stopping the counting. + * + * \param pTc Pointer to a Tc instance. + * \param dwChannel Channel number. + */ +extern void TC_Stop(Tc *pTc, uint32_t dwChannel ) +{ + TcChannel* pTcCh ; + + assert( dwChannel < (sizeof( pTc->TC_CHANNEL )/sizeof( pTc->TC_CHANNEL[0] )) ) ; + + pTcCh = pTc->TC_CHANNEL+dwChannel ; + pTcCh->TC_CCR = TC_CCR_CLKDIS ; +} + +/** + * \brief Find best MCK divisor + * + * Finds the best MCK divisor given the timer frequency and MCK. The result + * is guaranteed to satisfy the following equation: + * \code + * (MCK / (DIV * 65536)) <= freq <= (MCK / DIV) + * \endcode + * with DIV being the highest possible value. + * + * \param dwFreq Desired timer frequency. + * \param dwMCk Master clock frequency. + * \param dwDiv Divisor value. + * \param dwTcClks TCCLKS field value for divisor. + * \param dwBoardMCK Board clock frequency. + * + * \return 1 if a proper divisor has been found, otherwise 0. + */ +extern uint32_t TC_FindMckDivisor( uint32_t dwFreq, uint32_t dwMCk, + uint32_t *dwDiv, uint32_t *dwTcClks, uint32_t dwBoardMCK ) +{ + const uint32_t adwDivisors[5] = { 2, 8, 32, 128, BOARD_MCK / 32768 } ; + + uint32_t dwIndex = 0 ; + dwBoardMCK = dwBoardMCK; + /* Satisfy lower bound */ + while ( dwFreq < ((dwMCk / adwDivisors[dwIndex]) / 65536) ) { + dwIndex++ ; + + /* If no divisor can be found, return 0 */ + if ( dwIndex == (sizeof( adwDivisors )/sizeof( adwDivisors[0] )) ) { + return 0 ; + } + } + + /* Try to maximize DIV while satisfying upper bound */ + while ( dwIndex < 4 ) { + if ( dwFreq > (dwMCk / adwDivisors[dwIndex + 1]) ) { + break ; + } + dwIndex++ ; + } + + /* Store results */ + if ( dwDiv ) { + *dwDiv = adwDivisors[dwIndex] ; + } + if ( dwTcClks ) { + *dwTcClks = dwIndex ; + } + return 1 ; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/timetick.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/timetick.c new file mode 100644 index 000000000..0b1865be6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/timetick.c @@ -0,0 +1,187 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * Implement the System Timer. + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "board.h" +#include +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ +#define MAX_TIMER 4 +/** Tick Counter united by ms */ +static volatile uint32_t _dwTickCount = 0 ; +static uint8_t SysTickConfigured = 0 ; + +static volatile uint32_t _dwTickTimer = 0 ; +static TimeEvent *pTimeEventList = 0; + +SyTickDelayCounter_t DelayTimer; + +/*---------------------------------------------------------------------------- + * Exported Functions + *----------------------------------------------------------------------------*/ + + +/** + * \brief Handler for System Tick interrupt. + * + * Process System Tick Event + * Increments the time-stamp counter. + */ +void SysTick_Handler( void ) +{ + TimeEvent *pEvent; + pEvent = pTimeEventList; + _dwTickCount ++; + if(_dwTickTimer) + _dwTickTimer --; + while(pEvent) { + if(pEvent->time_start && pEvent->occur == 0) { + pEvent->time_tick--; + if(pEvent->time_tick == 0) { + pEvent->time_start = 0; + pEvent->occur = 1; + } + } + pEvent = pEvent->pNextEvent; + } +} + +void SetTimeEvent(TimeEvent* pEvent) +{ + pTimeEventList = pEvent; +} + +/** + * \brief Configures the System Timer. + * Systick interrupt handler will generates 1ms interrupt and increase a + * tickCount. + * \note IRQ handler must be configured before invoking this function. + */ +uint32_t TimeTick_Configure( void ) +{ + uint8_t Mdiv_Val; + uint32_t Pck; + _dwTickCount = 0 ; + + TRACE_INFO( "Configure system tick to get 1ms tick period.\n\r" ) ; + /* check if there is MDIV value */ + Mdiv_Val = ( (PMC->PMC_MCKR & PMC_MCKR_MDIV_Msk) >> PMC_MCKR_MDIV_Pos); + + if(Mdiv_Val == 0) { + Pck = BOARD_MCK; + } else if(Mdiv_Val == 3 ) { + Pck = BOARD_MCK * Mdiv_Val; + } else { + Pck = BOARD_MCK * (Mdiv_Val*2); + } + + DelayTimer.pTimer1 = NULL; DelayTimer.pTimer1=NULL; + /* Configure SysTick for 1 ms. */ + if ( SysTick_Config( Pck/1000 ) ) { + TRACE_ERROR("SysTick configuration error\n\r" ) ; + SysTickConfigured = 0; + return 1; + } + SysTickConfigured = 1; + return 0; +} + +/** + * \brief Get Delayed number of tick + * \param startTick Start tick point. + * \param endTick End tick point. + */ +uint32_t GetDelayInTicks(uint32_t startTick, uint32_t endTick) +{ + assert(SysTickConfigured); + + if (endTick >= startTick) return (endTick - startTick); + return (endTick + (0xFFFFFFFF - startTick) + 1); + +} + +/** + * \brief Get Delayed number of tick + * \param startTick Start tick point. + * \param endTick End tick point. + */ +uint32_t GetTicks(void) +{ + assert(SysTickConfigured); + + return _dwTickCount; +} + +/** + * \brief Sync Wait for several ms + * \param dwMs Waiting time in ms. + */ +void Wait( volatile uint32_t dwMs ) +{ + uint32_t dwStart , dwEnd; + + assert(SysTickConfigured); + + dwStart = _dwTickCount ; + dwEnd = _dwTickCount; + while(GetDelayInTicks(dwStart, dwEnd) < dwMs ){ + dwEnd = _dwTickCount; + } +} + +/** + * \brief Sync Sleep for several ms + * \param dwMs Sleeping time in ms. + */ +void Sleep( volatile uint32_t dwMs ) +{ + uint32_t dwStart , dwEnd; + + assert(SysTickConfigured); + + __ASM("CPSIE I"); + dwStart = _dwTickCount ; + dwEnd = _dwTickCount; + do { + if (GetDelayInTicks(dwStart, dwEnd) < dwMs ) { + break ; + } + dwEnd = _dwTickCount; + __ASM("WFI"); + } while( 1 ) ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/trng.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/trng.c new file mode 100644 index 000000000..5a4237d17 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/trng.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup rtng_module Working with RTNG + * \ingroup peripherals_module + * The TRNG driver provides the interface to configure and use the TRNG peripheral. + * \n + * + * The True Random Number Generator (TRNG) passes the American NIST Special Publication + * 800-22 and Diehard Random Tests Suites. As soon as the TRNG is enabled (TRNG_Enable()), + * the generator provides one 32-bit value every 84 clock cycles. + * Interrupt trng_int can be enabled through TRNG_EnableIt()(respectively disabled in TRNG_IDR). + * This interrupt is set when a new random value is available and is cleared when the status + * register is read (TRNG_SR register). The flag DATRDY of the status register (TRNG_ISR) is set + * when the random data is ready to be read out on the 32-bit output data through TRNG_GetRandData(). + * + * For more accurate information, please look at the SHA section of the + * Datasheet. + * + * Related files :\n + * \ref trng.c\n + * \ref trng.h\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of True Random Number Generator (TRNG) + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enables the TRNG to provide Random Values. + * \param key This key is to be written when the ENABLE bit is set. + */ +void TRNG_Enable(void) +{ + TRNG->TRNG_CR = TRNG_CR_ENABLE | TRNG_CR_KEY_PASSWD; +} + +/** + * \brief Disables the TRNG to provide Random Values. + * \param key This key is to be written when the DISABLE bit is set. + */ +void TRNG_Disable(void) +{ + TRNG->TRNG_CR = TRNG_CR_KEY_PASSWD; +} + +/** + * \brief Data Ready Interrupt enable. + */ +void TRNG_EnableIt(void) +{ + TRNG->TRNG_IER = TRNG_IER_DATRDY; +} + +/** + * \brief Data Ready Interrupt Disable. + */ +void TRNG_DisableIt(void) +{ + TRNG->TRNG_IDR = TRNG_IDR_DATRDY; +} + +/** + * \brief Get the current status register of the given TRNG peripheral. + * \return TRNG status register. + */ +uint32_t TRNG_GetStatus(void) +{ + return TRNG->TRNG_ISR; +} + +/** + * \brief Get the 32-bit Output Data from TRNG peripheral. + * \return TRNG output data. + */ +uint32_t TRNG_GetRandData(void) +{ + return TRNG->TRNG_ODATA; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/twi.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/twi.c new file mode 100644 index 000000000..7b63306cf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/twi.c @@ -0,0 +1,386 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup twi_module Working with TWI + * \ingroup peripherals_module + * The TWI driver provides the interface to configure and use the TWI + * peripheral. + * + * \section Usage + *
      + *
    • Configures a TWI peripheral to operate in master mode, at the given + * frequency (in Hz) using TWI_Configure().
      • + *
    • Sends a STOP condition on the TWI using TWI_Stop().
      • + *
    • Starts a read operation on the TWI bus with the specified slave using + * TWI_StartRead(). Data must then be read using TWI_ReadByte() whenever + * a byte is available (poll using TWI_ByteReceived()).
      • + *
    • Starts a write operation on the TWI to access the selected slave using + * TWI_StartWrite(). A byte of data must be provided to start the write; + * other bytes are written next.
      • + *
    • Sends a byte of data to one of the TWI slaves on the bus using + * TWI_WriteByte(). + * This function must be called once before TWI_StartWrite() with the first + * byte of data + * to send, then it shall be called repeatedly after that to send the + * remaining bytes.
      • + *
    • Check if a byte has been received and can be read on the given TWI + * peripheral using TWI_ByteReceived().< + * Check if a byte has been sent using TWI_ByteSent().
      • + *
    • Check if the current transmission is complete (the STOP has been sent) + * using TWI_TransferComplete().
      • + *
    • Enables & disable the selected interrupts sources on a TWI peripheral + * using TWI_EnableIt() and TWI_DisableIt().
      • + *
    • Get current status register of the given TWI peripheral using + * TWI_GetStatus(). Get current status register of the given TWI peripheral, but + * masking interrupt sources which are not currently enabled using + * TWI_GetMaskedStatus().
      • + *
    + * For more accurate information, please look at the TWI section of the + * Datasheet. + * + * Related files :\n + * \ref twi.c\n + * \ref twi.h.\n + */ +/*@{*/ +/*@}*/ + +/** + * \file + * + * Implementation of Two Wire Interface (TWI). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +#define TWIHS_IT ( TWIHS_IER_TXCOMP | TWIHS_IER_TXCOMP | TWIHS_IER_RXRDY \ + | TWIHS_IER_TXRDY | TWIHS_IER_SVACC | TWIHS_IER_GACC | \ + TWIHS_IER_OVRE | TWIHS_IER_UNRE | TWIHS_IER_NACK | \ + TWIHS_IER_ARBLST | TWIHS_IER_SCL_WS | TWIHS_IER_EOSACC | \ + TWIHS_IER_MCACK | TWIHS_IER_TOUT | TWIHS_IER_PECERR |\ + TWIHS_IER_SMBDAM | TWIHS_IER_SMBHHM) + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures a TWI peripheral to operate in master mode, at the given + * frequency (in Hz). The duty cycle of the TWI clock is set to 50%. + * \param pTwi Pointer to an Twihs instance. + * \param twck Desired TWI clock frequency. + * \param mck Master clock frequency. + */ +void TWI_ConfigureMaster( Twihs *pTwi, uint32_t dwTwCk, uint32_t dwMCk ) +{ + uint32_t dwCkDiv = 0 ; + uint32_t dwClDiv ; + uint32_t dwOk = 0 ; + + TRACE_DEBUG( "TWI_ConfigureMaster()\n\r" ) ; + assert( pTwi ) ; + + /* SVEN: TWI Slave Mode Enabled */ + pTwi->TWIHS_CR = TWIHS_CR_SVEN ; + /* Reset the TWI */ + pTwi->TWIHS_CR = TWIHS_CR_SWRST ; + pTwi->TWIHS_RHR ; + + /* TWI Slave Mode Disabled, TWI Master Mode Disabled. */ + pTwi->TWIHS_CR = TWIHS_CR_SVDIS ; + pTwi->TWIHS_CR = TWIHS_CR_MSDIS ; + + /* Set master mode */ + pTwi->TWIHS_CR = TWIHS_CR_MSEN ; + + /* Configure clock */ + while ( !dwOk ) { + dwClDiv = ((dwMCk / (2 * dwTwCk)) - 4) / (1<TWIHS_CWGR = 0 ; + pTwi->TWIHS_CWGR = (dwCkDiv << 16) | (dwClDiv << 8) | dwClDiv ; +} + +/** + * \brief Configures a TWI peripheral to operate in slave mode. + * \param pTwi Pointer to an Twihs instance. + * \param slaveAddress Slave address. + */ +void TWI_ConfigureSlave(Twihs *pTwi, uint8_t slaveAddress) +{ + uint32_t i; + + /* TWI software reset */ + pTwi->TWIHS_CR = TWIHS_CR_SWRST; + pTwi->TWIHS_RHR; + + /* Wait at least 10 ms */ + for (i=0; i < 1000000; i++); + + /* TWI Slave Mode Disabled, TWI Master Mode Disabled*/ + pTwi->TWIHS_CR = TWIHS_CR_SVDIS | TWIHS_CR_MSDIS; + + /* Configure slave address. */ + pTwi->TWIHS_SMR = 0; + pTwi->TWIHS_SMR = TWIHS_SMR_SADR(slaveAddress); + + /* SVEN: TWI Slave Mode Enabled */ + pTwi->TWIHS_CR = TWIHS_CR_SVEN; + + /* Wait at least 10 ms */ + for (i=0; i < 1000000; i++); + assert( (pTwi->TWIHS_CR & TWIHS_CR_SVDIS)!= TWIHS_CR_SVDIS ) ; +} + +/** + * \brief Sends a STOP condition on the TWI. + * \param pTwi Pointer to an Twihs instance. + */ +void TWI_Stop( Twihs *pTwi ) +{ + assert( pTwi != NULL ) ; + + pTwi->TWIHS_CR = TWIHS_CR_STOP; +} + +/** + * \brief Starts a read operation on the TWI bus with the specified slave, it + * returns immediately. Data must then be read using TWI_ReadByte() whenever a + * byte is available (poll using TWI_ByteReceived()). + * \param pTwi Pointer to an Twihs instance. + * \param address Slave address on the bus. + * \param iaddress Optional internal address bytes. + * \param isize Number of internal address bytes. + */ +void TWI_StartRead( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize) +{ + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Set slave address and number of internal address bytes. */ + pTwi->TWIHS_MMR = 0; + pTwi->TWIHS_MMR = (isize << 8) | TWIHS_MMR_MREAD | (address << 16); + + /* Set internal address bytes */ + pTwi->TWIHS_IADR = 0; + pTwi->TWIHS_IADR = iaddress; + + /* Send START condition */ + pTwi->TWIHS_CR = TWIHS_CR_START; +} + +/** + * \brief Reads a byte from the TWI bus. The read operation must have been started + * using TWI_StartRead() and a byte must be available (check with TWI_ByteReceived()). + * \param pTwi Pointer to an Twihs instance. + * \return byte read. + */ +uint8_t TWI_ReadByte(Twihs *pTwi) +{ + assert( pTwi != NULL ) ; + + return pTwi->TWIHS_RHR; +} + +/** + * \brief Sends a byte of data to one of the TWI slaves on the bus. + * \note This function must be called once before TWI_StartWrite() with + * the first byte of data to send, then it shall be called repeatedly + * after that to send the remaining bytes. + * \param pTwi Pointer to an Twihs instance. + * \param byte Byte to send. + */ +void TWI_WriteByte(Twihs *pTwi, uint8_t byte) +{ + assert( pTwi != NULL ) ; + + pTwi->TWIHS_THR = byte; +} + +/** + * \brief Starts a write operation on the TWI to access the selected slave, then + * returns immediately. A byte of data must be provided to start the write; + * other bytes are written next. + * after that to send the remaining bytes. + * \param pTwi Pointer to an Twihs instance. + * \param address Address of slave to acccess on the bus. + * \param iaddress Optional slave internal address. + * \param isize Number of internal address bytes. + * \param byte First byte to send. + */ +void TWI_StartWrite( + Twihs *pTwi, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t byte) +{ + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Set slave address and number of internal address bytes. */ + pTwi->TWIHS_MMR = 0; + pTwi->TWIHS_MMR = (isize << 8) | (address << 16); + + /* Set internal address bytes. */ + pTwi->TWIHS_IADR = 0; + pTwi->TWIHS_IADR = iaddress; + + /* Write first byte to send.*/ + TWI_WriteByte(pTwi, byte); +} + +/** + * \brief Check if a byte have been received from TWI. + * \param pTwi Pointer to an Twihs instance. + * \return 1 if a byte has been received and can be read on the given TWI + * peripheral; otherwise, returns 0. This function resets the status register. + */ +uint8_t TWI_ByteReceived(Twihs *pTwi) +{ + return ((pTwi->TWIHS_SR & TWIHS_SR_RXRDY) == TWIHS_SR_RXRDY); +} + +/** + * \brief Check if a byte have been sent to TWI. + * \param pTwi Pointer to an Twihs instance. + * \return 1 if a byte has been sent so another one can be stored for + * transmission; otherwise returns 0. This function clears the status register. + */ +uint8_t TWI_ByteSent(Twihs *pTwi) +{ + return ((pTwi->TWIHS_SR & TWIHS_SR_TXRDY) == TWIHS_SR_TXRDY); +} + +/** + * \brief Check if current transmission is completed. + * \param pTwi Pointer to an Twihs instance. + * \return 1 if the current transmission is complete (the STOP has been sent); + * otherwise returns 0. + */ +uint8_t TWI_TransferComplete(Twihs *pTwi) +{ + return ((pTwi->TWIHS_SR & TWIHS_SR_TXCOMP) == TWIHS_SR_TXCOMP); +} + +/** + * \brief Enables the selected interrupts sources on a TWI peripheral. + * \param pTwi Pointer to an Twihs instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void TWI_EnableIt(Twihs *pTwi, uint32_t sources) +{ + assert( pTwi != NULL ) ; + assert( (sources & TWIHS_IT) ) ; + + pTwi->TWIHS_IER = sources; +} + +/** + * \brief Disables the selected interrupts sources on a TWI peripheral. + * \param pTwi Pointer to an Twihs instance. + * \param sources Bitwise OR of selected interrupt sources. + */ +void TWI_DisableIt(Twihs *pTwi, uint32_t sources) +{ + assert( pTwi != NULL ) ; + assert(sources & TWIHS_IT ) ; + + pTwi->TWIHS_IDR = sources; +} + +/** + * \brief Get the current status register of the given TWI peripheral. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param pTwi Pointer to an Twihs instance. + * \return TWI status register. + */ +uint32_t TWI_GetStatus(Twihs *pTwi) +{ + assert( pTwi != NULL ) ; + + return pTwi->TWIHS_SR; +} + +/** + * \brief Returns the current status register of the given TWI peripheral, but + * masking interrupt sources which are not currently enabled. + * \note This resets the internal value of the status register, so further + * read may yield different values. + * \param pTwi Pointer to an Twihs instance. + */ +uint32_t TWI_GetMaskedStatus(Twihs *pTwi) +{ + uint32_t status; + + assert( pTwi != NULL ) ; + + status = pTwi->TWIHS_SR; + status &= pTwi->TWIHS_IMR; + + return status; +} + +/** + * \brief Sends a STOP condition. STOP Condition is sent just after completing + * the current byte transmission in master read mode. + * \param pTwi Pointer to an Twihs instance. + */ +void TWI_SendSTOPCondition(Twihs *pTwi) +{ + assert( pTwi != NULL ) ; + + pTwi->TWIHS_CR |= TWIHS_CR_STOP; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/twid.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/twid.c new file mode 100644 index 000000000..e111a26a7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/twid.c @@ -0,0 +1,724 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Definition + *----------------------------------------------------------------------------*/ +#define TWITIMEOUTMAX 400 +static uint32_t dmaWriteChannel,dmaReadChannel; + +/*---------------------------------------------------------------------------- + * Types + *----------------------------------------------------------------------------*/ + +/** TWI driver callback function.*/ +typedef void (*TwiCallback)(Async *); + +/** \brief TWI asynchronous transfer descriptor.*/ +typedef struct _AsyncTwi { + + /** Asynchronous transfer status. */ + volatile uint8_t status; + /** Callback function to invoke when transfer completes or fails.*/ + TwiCallback callback; + /** Pointer to the data buffer.*/ + uint8_t *pData; + /** Total number of bytes to transfer.*/ + uint32_t num; + /** Number of already transferred bytes.*/ + uint32_t transferred; + +} AsyncTwi; + +/** + * \brief Initializes a TWI DMA Read channel. + */ +static void TWID_DmaInitializeRead(TwihsDma *pTwiXdma) +{ + /* Allocate a XDMA channel, Read accesses into TWI_THR */ + dmaReadChannel = XDMAD_AllocateChannel( pTwiXdma->pTwiDma, pTwiXdma->Twi_id, + XDMAD_TRANSFER_MEMORY); + if ( dmaReadChannel == XDMAD_ALLOC_FAILED ) { + printf("-E- Can't allocate XDMA channel\n\r"); + } + XDMAD_PrepareChannel(pTwiXdma->pTwiDma, dmaReadChannel ); +} + +/** + * \brief Initializes a TWI DMA write channel. + */ +static void TWID_DmaInitializeWrite(TwihsDma *pTwiXdma) +{ + /* Allocate a XDMA channel, Write accesses into TWI_THR */ + dmaWriteChannel = XDMAD_AllocateChannel( pTwiXdma->pTwiDma, XDMAD_TRANSFER_MEMORY, + pTwiXdma->Twi_id); + if ( dmaWriteChannel == XDMAD_ALLOC_FAILED ) { + printf("-E- Can't allocate XDMA channel\n\r"); + } + XDMAD_PrepareChannel(pTwiXdma->pTwiDma, dmaWriteChannel ); +} + +/** + * \brief Configure xDMA write linker list for TWI transfer. + */ +static uint8_t TWID_XdmaConfigureWrite(TwihsDma *pTwiXdma, uint8_t *buf, uint32_t len) +{ + uint32_t xdmaCndc, Thr, xdmaInt; + sXdmadCfg xdmadTxCfg; + + Thr = (uint32_t)&(TWIHS0->TWIHS_THR); + if(pTwiXdma->Twi_id==ID_TWIHS1) { + Thr = (uint32_t)&(TWIHS1->TWIHS_THR); + } + if(pTwiXdma->Twi_id==ID_TWIHS2) { + Thr = (uint32_t)&(TWIHS2->TWIHS_THR); + } + xdmadTxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | + XDMA_UBC_NDE_FETCH_DIS| + XDMA_UBC_NSEN_UPDATED | len; + + xdmadTxCfg.mbr_sa = (uint32_t)buf; + xdmadTxCfg.mbr_da = Thr; + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( + pTwiXdma->Twi_id, XDMAD_TRANSFER_TX )); + + xdmadTxCfg.mbr_bc = 0; + xdmadTxCfg.mbr_sus = 0; + xdmadTxCfg.mbr_dus =0; + xdmaCndc = 0; + + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE ); + if (XDMAD_ConfigureTransfer( pTwiXdma->pTwiDma, dmaWriteChannel, + &xdmadTxCfg, xdmaCndc, 0, xdmaInt) ) + return USARTD_ERROR; + + return 0; +} + + +/** + * \brief Configure xDMA read linker list for TWI transfer. + */ +static uint8_t TWID_XdmaConfigureRead(TwihsDma *pTwiXdma, uint8_t *buf, uint32_t len) +{ + uint32_t xdmaCndc, Rhr, xdmaInt; + sXdmadCfg xdmadRxCfg; + + Rhr = (uint32_t)&(TWIHS0->TWIHS_RHR); + if(pTwiXdma->Twi_id==ID_TWIHS1) { + Rhr = (uint32_t)&(TWIHS1->TWIHS_RHR); + } + if(pTwiXdma->Twi_id==ID_TWIHS2) { + Rhr = (uint32_t)&(TWIHS2->TWIHS_RHR); + } + xdmadRxCfg.mbr_ubc = XDMA_UBC_NVIEW_NDV0 | + XDMA_UBC_NDE_FETCH_DIS| + XDMA_UBC_NDEN_UPDATED | + len; + + xdmadRxCfg.mbr_da = (uint32_t)buf; + xdmadRxCfg.mbr_sa = Rhr; + + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SINGLE | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( + pTwiXdma->Twi_id , XDMAD_TRANSFER_RX )); + + xdmadRxCfg.mbr_bc = 0; + xdmadRxCfg.mbr_sus = 0; + xdmadRxCfg.mbr_dus =0; + xdmaCndc = 0; + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE ); + + if (XDMAD_ConfigureTransfer( pTwiXdma->pTwiDma, dmaReadChannel, + &xdmadRxCfg, xdmaCndc, 0, xdmaInt)) + return 1; + return 0; +} + +/*---------------------------------------------------------------------------- + * Global functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Returns 1 if the given transfer has ended; otherwise returns 0. + * \param pAsync Pointer to an Async instance. + */ +uint32_t ASYNC_IsFinished( Async* pAsync ) +{ + return (pAsync->status != ASYNC_STATUS_PENDING) ; +} + +/** + * \brief Initializes a TWI driver instance, using the given TWI peripheral. + * \note The peripheral must have been initialized properly before calling this + * function. + * \param pTwid Pointer to the Twid instance to initialize. + * \param pTwi Pointer to the TWI peripheral to use. + */ +void TWID_Initialize(Twid *pTwid, Twihs *pTwi) +{ + TRACE_DEBUG( "TWID_Initialize()\n\r" ) ; + assert( pTwid != NULL ) ; + assert( pTwi != NULL ) ; + + /* Initialize driver. */ + pTwid->pTwi = pTwi; + pTwid->pTransfer = 0; +} + +/** + * \brief Interrupt handler for a TWI peripheral. Manages asynchronous transfer + * occurring on the bus. This function MUST be called by the interrupt service + * routine of the TWI peripheral if asynchronous read/write are needed. + * \param pTwid Pointer to a Twid instance. + */ +void TWID_Handler( Twid *pTwid ) +{ + uint8_t status; + AsyncTwi *pTransfer ; + Twihs *pTwi ; + + assert( pTwid != NULL ) ; + + pTransfer = (AsyncTwi*)pTwid->pTransfer ; + assert( pTransfer != NULL ) ; + pTwi = pTwid->pTwi ; + assert( pTwi != NULL ) ; + + /* Retrieve interrupt status */ + status = TWI_GetMaskedStatus(pTwi); + + /* Byte received */ + if (TWI_STATUS_RXRDY(status)) { + + pTransfer->pData[pTransfer->transferred] = TWI_ReadByte(pTwi); + pTransfer->transferred++; + + /* check for transfer finish */ + if (pTransfer->transferred == pTransfer->num) { + + TWI_DisableIt(pTwi, TWIHS_IDR_RXRDY); + TWI_EnableIt(pTwi, TWIHS_IER_TXCOMP); + } + /* Last byte? */ + else if (pTransfer->transferred == (pTransfer->num - 1)) { + + TWI_Stop(pTwi); + } + } + /* Byte sent*/ + else if (TWI_STATUS_TXRDY(status)) { + + /* Transfer finished ? */ + if (pTransfer->transferred == pTransfer->num) { + + TWI_DisableIt(pTwi, TWIHS_IDR_TXRDY); + TWI_EnableIt(pTwi, TWIHS_IER_TXCOMP); + TWI_SendSTOPCondition(pTwi); + } + /* Bytes remaining */ + else { + + TWI_WriteByte(pTwi, pTransfer->pData[pTransfer->transferred]); + pTransfer->transferred++; + } + } + /* Transfer complete*/ + else if (TWI_STATUS_TXCOMP(status)) { + + TWI_DisableIt(pTwi, TWIHS_IDR_TXCOMP); + pTransfer->status = 0; + if (pTransfer->callback) { + pTransfer->callback((Async *) pTransfer); + } + pTwid->pTransfer = 0; + } +} + +/** + * \brief Asynchronously reads data from a slave on the TWI bus. An optional + * callback function is triggered when the transfer is complete. + * \param pTwid Pointer to a Twid instance. + * \param address TWI slave address. + * \param iaddress Optional slave internal address. + * \param isize Internal address size in bytes. + * \param pData Data buffer for storing received bytes. + * \param num Number of bytes to read. + * \param pAsync Asynchronous transfer descriptor. + * \return 0 if the transfer has been started; otherwise returns a TWI error code. + */ +uint8_t TWID_Read( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync) +{ + Twihs *pTwi; + AsyncTwi *pTransfer; + uint32_t startTime; + assert( pTwid != NULL ) ; + pTwi = pTwid->pTwi; + pTransfer = (AsyncTwi *) pTwid->pTransfer; + + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Check that no transfer is already pending*/ + if (pTransfer) { + + TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); + return TWID_ERROR_BUSY; + } + + /* Set STOP signal if only one byte is sent*/ + if (num == 1) { + + TWI_Stop(pTwi); + } + + /* Asynchronous transfer*/ + if (pAsync) { + + /* Update the transfer descriptor */ + pTwid->pTransfer = pAsync; + pTransfer = (AsyncTwi *) pAsync; + pTransfer->status = ASYNC_STATUS_PENDING; + pTransfer->pData = pData; + pTransfer->num = num; + pTransfer->transferred = 0; + + /* Enable read interrupt and start the transfer */ + TWI_EnableIt(pTwi, TWIHS_IER_RXRDY); + TWI_StartRead(pTwi, address, iaddress, isize); + } + /* Synchronous transfer*/ + else { + + /* Start read*/ + TWI_StartRead(pTwi, address, iaddress, isize); + + /* Read all bytes, setting STOP before the last byte*/ + while (num > 0) { + + /* Last byte ?*/ + if (num == 1) { + TWI_Stop(pTwi); + } + /* Wait for byte then read and store it*/ + startTime = GetTicks(); + while( !TWI_ByteReceived(pTwi)) { + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout BR\n\r"); + break; + } + } + + *pData++ = TWI_ReadByte(pTwi); + num--; + } + + /* Wait for transfer to be complete */ + startTime = GetTicks(); + while( !TWI_TransferComplete(pTwi) ) { + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout TC\n\r"); + break; + } + } + } + return 0; +} + +/** + * \brief Asynchronously sends data to a slave on the TWI bus. An optional + * callback function is invoked whenever the transfer is complete. + * \param pTwid Pointer to a Twid instance. + * \param address TWI slave address. + * \param iaddress Optional slave internal address. + * \param isize Number of internal address bytes. + * \param pData Data buffer for storing received bytes. + * \param num Data buffer to send. + * \param pAsync Asynchronous transfer descriptor. + * \return 0 if the transfer has been started; otherwise returns a TWI error code. + */ +uint8_t TWID_Write( + Twid *pTwid, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync) +{ + Twihs *pTwi = pTwid->pTwi; + uint32_t startTime; + AsyncTwi *pTransfer = (AsyncTwi *) pTwid->pTransfer; + + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Check that no transfer is already pending */ + if (pTransfer) { + TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); + return TWID_ERROR_BUSY; + } + + /* Asynchronous transfer */ + if (pAsync) { + /* Update the transfer descriptor */ + pTwid->pTransfer = pAsync; + pTransfer = (AsyncTwi *) pAsync; + pTransfer->status = ASYNC_STATUS_PENDING; + pTransfer->pData = pData; + pTransfer->num = num; + pTransfer->transferred = 1; + + /* Enable write interrupt and start the transfer */ + TWI_StartWrite(pTwi, address, iaddress, isize, *pData); + TWI_EnableIt(pTwi, TWIHS_IER_TXRDY); + + } else { + /* Synchronous transfer*/ + // Start write + TWI_StartWrite(pTwi, address, iaddress, isize, *pData++); + num--; + /* Send all bytes */ + while (num > 0) { + /* Wait before sending the next byte */ + startTime = GetTicks(); + while( !TWI_ByteSent(pTwi) ) { + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout BS\n\r"); + break; + } + } + TWI_WriteByte(pTwi, *pData++); + num--; + } + /* Wait for actual end of transfer */ + startTime = GetTicks(); + /* Send a STOP condition */ + TWI_SendSTOPCondition(pTwi); + while( !TWI_TransferComplete(pTwi) ) { + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout TC2\n\r"); + break; + } + } + } + return 0; +} + +/** + * \brief Initializes a TWI driver instance, using the given TWI peripheral. + * \note The peripheral must have been initialized properly before calling this + * function. + * \param pTwid Pointer to the Twid instance to initialize. + * \param pTwi Pointer to the TWI peripheral to use. + */ +void TWID_DmaInitialize(TwihsDma *pTwidma, Twihs *pTwi, uint8_t bPolling) +{ + TRACE_DEBUG( "TWID_Initialize()\n\r" ) ; + assert( pTwidma != NULL ) ; + + if ((unsigned int)pTwi == (unsigned int)TWIHS0 ) pTwidma->Twi_id = ID_TWIHS0; + if ((unsigned int)pTwi == (unsigned int)TWIHS1 ) pTwidma->Twi_id = ID_TWIHS1; + if ((unsigned int)pTwi == (unsigned int)TWIHS2 ) pTwidma->Twi_id = ID_TWIHS2; + + /* Initialize driver. */ + pTwidma->pTwid->pTwi = pTwi; + pTwidma->pTwid->pTransfer = 0; + + if(!bPolling) { + /* Enable XDMA interrupt and give it priority over any other peripheral + interrupt */ + NVIC_ClearPendingIRQ(XDMAC_IRQn); + NVIC_SetPriority(XDMAC_IRQn, 1); + NVIC_EnableIRQ( XDMAC_IRQn ); + } + /* Initialize XDMA driver instance with polling mode */ + XDMAD_Initialize( pTwidma->pTwiDma, bPolling ); +} + +/** + * \brief Asynchronously reads data from a slave on the TWI bus. An optional + * callback function is triggered when the transfer is complete. + * \param pTwid Pointer to a Twid instance. + * \param address TWI slave address. + * \param iaddress Optional slave internal address. + * \param isize Internal address size in bytes. + * \param pData Data buffer for storing received bytes. + * \param num Number of bytes to read. + * \param pAsync Asynchronous transfer descriptor. + * \param TWI_ID TWI ID for TWI0, TWIHS1, TWIHS2. + * \return 0 if the transfer has been started; otherwise returns a TWI error code. + */ +uint8_t TWID_DmaRead( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync) +{ + Twihs *pTwi; + AsyncTwi *pTransfer; + uint32_t status, startTime; + + assert( pTwiXdma->pTwid != NULL ) ; + pTwi = pTwiXdma->pTwid->pTwi; + pTransfer = (AsyncTwi *) pTwiXdma->pTwid->pTransfer; + + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + /* Check that no transfer is already pending*/ + if (pTransfer) { + + TRACE_ERROR("TWID_Read: A transfer is already pending\n\r"); + return TWID_ERROR_BUSY; + } + /* Asynchronous transfer*/ + if (pAsync) { + /* Update the transfer descriptor */ + pTwiXdma->pTwid->pTransfer = pAsync; + pTransfer = (AsyncTwi *) pAsync; + pTransfer->status = ASYNC_STATUS_PENDING; + pTransfer->pData = pData; + pTransfer->num = num; + pTransfer->transferred = 0; + + /* Enable read interrupt and start the transfer */ + TWI_EnableIt(pTwi, TWIHS_IER_RXRDY); + TWI_StartRead(pTwi, address, iaddress, isize); + } else { + /* Synchronous transfer*/ + TWID_DmaInitializeRead(pTwiXdma); + TWID_XdmaConfigureRead(pTwiXdma, pData, (num - 2)); + + // cache maintenance before starting DMA Xfr + SCB_CleanInvalidateDCache(); + /* Start read*/ + XDMAD_StartTransfer( pTwiXdma->pTwiDma, dmaReadChannel ); + TWI_StartRead(pTwi, address, iaddress, isize); + + startTime = GetTicks(); + while( XDMAD_IsTransferDone(pTwiXdma->pTwiDma, dmaReadChannel) ) { + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID DMA not done\n\r"); + break; + } + } + + status = TWI_GetStatus(pTwi); + startTime = GetTicks(); + + while( !(status & TWIHS_SR_RXRDY)) { + status = TWI_GetStatus(pTwi); + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID DMA not done\n\r"); + break; + } + } + TWI_Stop(pTwi); + + pData[num - 2] = TWI_ReadByte(pTwi); + status = TWI_GetStatus(pTwi); + startTime = GetTicks(); + + while( !(status & TWIHS_SR_RXRDY)) { + status = TWI_GetStatus(pTwi); + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout Read\n\r"); + break; + } + } + pData[num-1] = TWI_ReadByte(pTwi); + status = TWI_GetStatus(pTwi); + startTime = GetTicks(); + while( !(status & TWIHS_SR_TXCOMP)) { + status = TWI_GetStatus(pTwi); + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout Read\n\r"); + break; + } + } + + XDMAD_StopTransfer( pTwiXdma->pTwiDma, dmaReadChannel ); + XDMAD_FreeChannel(pTwiXdma->pTwiDma, dmaWriteChannel); + } + return 0; +} + +/** + * \brief Asynchronously sends data to a slave on the TWI bus. An optional + * callback function is invoked whenever the transfer is complete. + * \param pTwid Pointer to a Twid instance. + * \param address TWI slave address. + * \param iaddress Optional slave internal address. + * \param isize Number of internal address bytes. + * \param pData Data buffer for storing received bytes. + * \param num Data buffer to send. + * \param pAsync Asynchronous transfer descriptor. + * \param TWI_ID TWIHS ID for TWIHS0, TWIHS1, TWIHS2. + * \return 0 if the transfer has been started; otherwise returns a TWI error code. + */ +uint8_t TWID_DmaWrite( + TwihsDma *pTwiXdma, + uint8_t address, + uint32_t iaddress, + uint8_t isize, + uint8_t *pData, + uint32_t num, + Async *pAsync) +{ + Twihs *pTwi = pTwiXdma->pTwid->pTwi; + AsyncTwi *pTransfer = (AsyncTwi *) pTwiXdma->pTwid->pTransfer; + uint32_t status, startTime; + //uint8_t singleTransfer = 0; + assert( pTwi != NULL ) ; + assert( (address & 0x80) == 0 ) ; + assert( (iaddress & 0xFF000000) == 0 ) ; + assert( isize < 4 ) ; + + // if(num == 1) singleTransfer = 1; + /* Check that no transfer is already pending */ + if (pTransfer) { + + TRACE_ERROR("TWI_Write: A transfer is already pending\n\r"); + return TWID_ERROR_BUSY; + } + + /* Asynchronous transfer */ + if (pAsync) { + + /* Update the transfer descriptor */ + pTwiXdma->pTwid->pTransfer = pAsync; + pTransfer = (AsyncTwi *) pAsync; + pTransfer->status = ASYNC_STATUS_PENDING; + pTransfer->pData = pData; + pTransfer->num = num; + pTransfer->transferred = 1; + + /* Enable write interrupt and start the transfer */ + TWI_StartWrite(pTwi, address, iaddress, isize, *pData); + TWI_EnableIt(pTwi, TWIHS_IER_TXRDY); + } else { + /* Synchronous transfer*/ + TWID_DmaInitializeWrite(pTwiXdma); + TWID_XdmaConfigureWrite(pTwiXdma, pData, (num - 1) ); + /* Set slave address and number of internal address bytes. */ + pTwi->TWIHS_MMR = 0; + pTwi->TWIHS_MMR = (isize << 8) | (address << 16); + + /* Set internal address bytes. */ + pTwi->TWIHS_IADR = 0; + pTwi->TWIHS_IADR = iaddress; + + // cache maintenance before starting DMA Xfr + SCB_CleanInvalidateDCache(); + + startTime = GetTicks(); + + XDMAD_StartTransfer( pTwiXdma->pTwiDma, dmaWriteChannel ); + + while( (XDMAD_IsTransferDone(pTwiXdma->pTwiDma, dmaWriteChannel)) ) { + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID DMA not done, Channel State is %d\n\r", + pTwiXdma->pTwiDma->XdmaChannels[dmaWriteChannel].state); + break; + } + } + status = TWI_GetStatus(pTwi); + startTime = GetTicks(); + + while( !(status & TWIHS_SR_TXRDY)) { + status = TWI_GetStatus(pTwi); + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout TXRDY\n\r"); + break; + } + } + /* Send a STOP condition */ + TWI_Stop(pTwi); + + TWI_WriteByte(pTwi, pData[num-1]); + status = TWI_GetStatus(pTwi); + startTime = GetTicks(); + + while( !(status & TWIHS_SR_TXCOMP)) { + status = TWI_GetStatus(pTwi); + if ( (GetDelayInTicks(startTime, GetTicks() ) ) > TWITIMEOUTMAX) { + TRACE_ERROR("TWID Timeout Write\n\r"); + break; + } + } + XDMAD_StopTransfer(pTwiXdma->pTwiDma, dmaWriteChannel ); + XDMAD_FreeChannel(pTwiXdma->pTwiDma, dmaWriteChannel); + + } + return 0; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/uart.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/uart.c new file mode 100644 index 000000000..3f2bdc6b7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/uart.c @@ -0,0 +1,233 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2011, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of UART (Universal Asynchronous Receiver Transmitter) + * controller. + * + */ +/*------------------------------------------------------------------------------ + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*------------------------------------------------------------------------------ + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Configures an UART peripheral with the specified parameters. + * + * + * \param uart Pointer to the UART peripheral to configure. + * \param mode Desired value for the UART mode register (see the datasheet). + * \param baudrate Baudrate at which the UART should operate (in Hz). + * \param masterClock Frequency of the system master clock (in Hz). + */ +void UART_Configure(Uart *uart, + uint32_t mode, + uint32_t baudrate, + uint32_t masterClock) +{ + /* Reset and disable receiver & transmitter*/ + uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX + | UART_CR_RXDIS | UART_CR_TXDIS | UART_CR_RSTSTA; + + uart->UART_IDR = 0xFFFFFFFF; + + /* Configure mode*/ + uart->UART_MR = mode; + + /* Configure baudrate*/ + uart->UART_BRGR = (masterClock / baudrate) / 16; + + uart->UART_CR = UART_CR_TXEN | UART_CR_RXEN; + +} +/** + * \brief Enables or disables the transmitter of an UART peripheral. + * + * + * \param uart Pointer to an UART peripheral + * \param enabled If true, the transmitter is enabled; otherwise it is + * disabled. + */ +void UART_SetTransmitterEnabled(Uart *uart, uint8_t enabled) +{ + if (enabled) { + uart->UART_CR = UART_CR_TXEN; + } else { + uart->UART_CR = UART_CR_TXDIS; + } +} + +/** + * \brief Enables or disables the receiver of an UART peripheral + * + * + * \param uart Pointer to an UART peripheral + * \param enabled If true, the receiver is enabled; otherwise it is disabled. + */ +void UART_SetReceiverEnabled(Uart *uart, uint8_t enabled) +{ + if (enabled) { + uart->UART_CR = UART_CR_RXEN; + } else { + uart->UART_CR = UART_CR_RXDIS; + } +} + +/** + * \brief Return 1 if a character can be read in UART + * \param uart Pointer to an UART peripheral. + */ +uint32_t UART_IsRxReady(Uart *uart) +{ + return (uart->UART_SR & UART_SR_RXRDY); +} + +/** + * \brief Reads and returns a character from the UART. + * + * \note This function is synchronous (i.e. uses polling). + * \param uart Pointer to an UART peripheral. + * \return Character received. + */ +uint8_t UART_GetChar(Uart *uart) +{ + while (!UART_IsRxReady(uart)); + return uart->UART_RHR; +} + +/** + * \brief Return 1 if a character can be send to UART + * \param uart Pointer to an UART peripheral. + */ +uint32_t UART_IsTxReady(Uart *uart) +{ + return (uart->UART_SR & UART_SR_TXRDY); +} + +/** + * \brief Return 1 if a character can be send to UART + * \param uart Pointer to an UART peripheral. + */ +static uint32_t UART_IsTxSent(Uart *uart) +{ + return (uart->UART_SR & UART_SR_TXEMPTY); +} + +/** + * \brief Sends one packet of data through the specified UART peripheral. This + * function operates synchronously, so it only returns when the data has been + * actually sent. + * + * \param uart Pointer to an UART peripheral. + * \param c Character to send + */ +void UART_PutChar( Uart *uart, uint8_t c) +{ + /* Wait for the transmitter to be ready*/ + while (!UART_IsRxReady(uart) && !UART_IsTxSent(uart)); + + /* Send character*/ + uart->UART_THR = c; + + /* Wait for the transfer to complete*/ + while (!UART_IsTxSent(uart)); +} + +/** + * \brief Get present status + * \param uart Pointer to an UART peripheral. + */ +uint32_t UART_GetStatus(Uart *uart) +{ + return uart->UART_SR; +} + +/** + * \brief Enable interrupt + * \param uart Pointer to an UART peripheral. + * \param mode Interrupt mode. + */ +void UART_EnableIt(Uart *uart,uint32_t mode) +{ + uart->UART_IER = mode; +} + +/** + * \brief Disable interrupt + * \param uart Pointer to an UART peripheral. + * \param mode Interrupt mode. + */ +void UART_DisableIt(Uart *uart,uint32_t mode) +{ + uart->UART_IDR = mode; +} + +/** + * \brief Return interrupt mask + * \param uart Pointer to an UART peripheral. + */ +uint32_t UART_GetItMask(Uart *uart) +{ + return uart->UART_IMR; +} + +void UART_SendBuffer(Uart *uart, uint8_t *pBuffer, uint32_t BuffLen) +{ + uint8_t *pData = pBuffer; + uint32_t Len =0; + + for(Len =0; LenUART_CMPR = (UART_CMPR_VAL1(Val1) | UART_CMPR_VAL2(Val2)); +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/uart_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/uart_dma.c new file mode 100644 index 000000000..b519bc28f --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/uart_dma.c @@ -0,0 +1,595 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \addtogroup uart_dma_module UART xDMA driver + * \ingroup lib_uart + * \section Usage + * + *
      + *
    • UARTD_Configure() initializes and configures the UART peripheral and + * xDMA for data transfer.
      • + *
    • Configures the parameters for the device corresponding to the cs value + * by UARTD_ConfigureCS().
      • + *
    • Starts a UART master transfer. This is a non blocking function + * UARTD_SendData(). It will + * return as soon as the transfer is started..
      • + *
    + * + */ + +/** + * \file + * + * Implementation for the UART with xDMA driver. + * + */ + + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include "string.h" +#include "stdlib.h" + + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + + /** + * \brief UART xDMA Rx callback + * Invoked on UART DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to UARTDma instance. + */ +static void UARTD_Rx_Cb(uint32_t channel, UartDma* pArg) +{ + + UartChannel *pUartdCh = pArg->pRxChannel; + if (channel != pUartdCh->ChNum) + return; + + /* Release the DMA channels */ + XDMAD_FreeChannel(pArg->pXdmad, pUartdCh->ChNum); + pUartdCh->sempaphore = 1; + memory_barrier(); +} + +/** + * \brief USART xDMA Rx callback + * Invoked on USART DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to USARTDma instance. + */ +static void UARTD_Tx_Cb(uint32_t channel, UartDma* pArg) +{ + UartChannel *pUartdCh = pArg->pTxChannel; + if (channel != pUartdCh->ChNum) + return; + + /* Release the DMA channels */ + XDMAD_FreeChannel(pArg->pXdmad, pUartdCh->ChNum); + pUartdCh->sempaphore = 1; + memory_barrier(); +} + +/** + * \brief Configure the UART Rx DMA mode. + * + * \param pUartHw Pointer to UART instance + * \param pXdmad Pointer to XDMA instance + * \param pUsartRx Pointer to Usart Rx channel + * \returns 0 if the dma multibuffer configuration successfully; otherwise + * returns USARTD_ERROR_XXX. + */ +static uint8_t _configureUartRxDma(UartDma *pUartd , UartChannel *pUartRx) +{ + sXdmadCfg xdmadRxCfg; + uint32_t xdmaCndc, xdmaInt; + uint32_t i, LLI_Size; + Uart *pUartHwRx = pUartd->pUartHw; + sXdmad* pXdmadRx = pUartd->pXdmad; + uint8_t *pBuff = 0; + + /* Setup RX Single block */ + if(pUartRx->dmaProgrammingMode < XDMAD_LLI) { + xdmadRxCfg.mbr_ubc = pUartRx->BuffSize; + xdmadRxCfg.mbr_da = (uint32_t)pUartRx->pBuff; + + xdmadRxCfg.mbr_sa = (uint32_t)&pUartHwRx->UART_RHR; + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( pUartd->uartId, XDMAD_TRANSFER_RX )); + + xdmadRxCfg.mbr_bc = 0; + if(pUartRx->dmaProgrammingMode == XDMAD_MULTI) { + xdmadRxCfg.mbr_bc = pUartRx->dmaBlockSize; + } + xdmadRxCfg.mbr_sus = 0; + xdmadRxCfg.mbr_dus =0; + xdmaCndc = 0; + + /* Put all interrupts on for non LLI list setup of DMA */ + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + } else if(pUartRx->dmaProgrammingMode == XDMAD_LLI) { + /* Setup RX Link List */ + LLI_Size = pUartRx->dmaBlockSize; + pBuff = pUartRx->pBuff; + if(pUartRx->pLLIview != NULL) { + free(pUartRx->pLLIview); + pUartRx->pLLIview = NULL; + } + + pUartRx->pLLIview = malloc(sizeof(LinkedListDescriporView1)*LLI_Size); + if( pUartRx->pLLIview == NULL) { + TRACE_ERROR(" Can not allocate memory to Rx LLI"); + return USARTD_ERROR; + } + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( + pUartd->uartId, XDMAD_TRANSFER_RX )); + xdmadRxCfg.mbr_bc = 0; + for (i = 0; i < LLI_Size; i++) { + pUartRx->pLLIview[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | + XDMA_UBC_NSEN_UNCHANGED | + XDMA_UBC_NDEN_UPDATED | + ((i== LLI_Size- 1)? ( (pUartRx->dmaRingBuffer)? + XDMA_UBC_NDE_FETCH_EN : 0): + XDMA_UBC_NDE_FETCH_EN) | pUartRx->BuffSize; + pUartRx->pLLIview[i].mbr_sa = (uint32_t)&pUartHwRx->UART_RHR; + pUartRx->pLLIview[i].mbr_da = (uint32_t)pBuff; + pUartRx->pLLIview[i].mbr_nda = (i == ( LLI_Size - 1))? + ( (pUartRx->dmaRingBuffer)? (uint32_t)pUartRx->pLLIview : 0 ): + (uint32_t)&pUartRx->pLLIview[ i + 1 ]; + pBuff += pUartRx->BuffSize; + } + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED| + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + + xdmaInt = ((pUartRx->dmaRingBuffer)? XDMAC_CIE_BIE : XDMAC_CIE_LIE); + + } else { + return 1; + } + memory_barrier(); + if (XDMAD_ConfigureTransfer( pXdmadRx, pUartRx->ChNum, &xdmadRxCfg, + xdmaCndc, (uint32_t)pUartRx->pLLIview, xdmaInt)) + return USARTD_ERROR; + return 0; +} + +/** + * \brief Configure the UART Tx DMA mode. + * + * \param pUartHw Pointer to UART instance + * \param pXdmad Pointer to XDMA instance + * \param pUsartTx Pointer to Usart Tx channel + * \returns 0 if the dma multibuffer configuration successfully; otherwise + * returns USARTD_ERROR_XXX. + */ +static uint8_t _configureUartTxDma(UartDma *pUartd, UartChannel *pUartTx) +{ + sXdmadCfg xdmadTxCfg; + uint32_t xdmaCndc, xdmaInt, LLI_Size, i; + uint8_t *pBuff = 0; + Uart *pUartHwTx = pUartd->pUartHw; + sXdmad* pXdmadTx = pUartd->pXdmad; + + + /* Setup TX */ + if(pUartTx->dmaProgrammingMode < XDMAD_LLI) { + xdmadTxCfg.mbr_ubc = pUartTx->BuffSize; + + xdmadTxCfg.mbr_sa = (uint32_t)pUartTx->pBuff; + xdmadTxCfg.mbr_da = (uint32_t)&pUartHwTx->UART_THR; + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( + pUartd->uartId, XDMAD_TRANSFER_TX )); + + xdmadTxCfg.mbr_bc = 0; + if(pUartTx->dmaProgrammingMode == XDMAD_MULTI) { + xdmadTxCfg.mbr_bc = pUartTx->dmaBlockSize; + } + xdmadTxCfg.mbr_sus = 0; + xdmadTxCfg.mbr_dus =0; + xdmadTxCfg.mbr_ds= 0; + xdmaCndc = 0; + /* Enable End of Block; Read Bus error; Write Bus Error; + Overflow Error interrupt */ + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + + } else if(pUartTx->dmaProgrammingMode == XDMAD_LLI) { + LLI_Size = pUartTx->dmaBlockSize; + pBuff = pUartTx->pBuff; + if(pUartTx->pLLIview != NULL) { + free(pUartTx->pLLIview); + pUartTx->pLLIview = NULL; + } + + pUartTx->pLLIview = malloc(sizeof(LinkedListDescriporView1)*LLI_Size); + if( pUartTx->pLLIview == NULL) { + TRACE_ERROR(" Can not allocate memory to Tx LLI"); + return USARTD_ERROR; + } + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber( + pUartd->uartId, XDMAD_TRANSFER_TX )); + xdmadTxCfg.mbr_bc = 0; + for (i = 0; i < LLI_Size; i++) { + pUartTx->pLLIview[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | + XDMA_UBC_NSEN_UPDATED | + XDMA_UBC_NDEN_UNCHANGED | + ((i== LLI_Size- 1)? ( (pUartTx->dmaRingBuffer)? + XDMA_UBC_NDE_FETCH_EN : 0): + XDMA_UBC_NDE_FETCH_EN) | pUartTx->BuffSize; + pUartTx->pLLIview[i].mbr_da = (uint32_t)&pUartHwTx->UART_THR; + pUartTx->pLLIview[i].mbr_sa = (uint32_t)pBuff; + pUartTx->pLLIview[i].mbr_nda = (i == ( LLI_Size - 1))? + ( (pUartTx->dmaRingBuffer)? (uint32_t)pUartTx->pLLIview : 0 ): + (uint32_t)&pUartTx->pLLIview[ i + 1 ]; + pBuff += pUartTx->BuffSize; + } + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED| + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + xdmaInt = ((pUartTx->dmaRingBuffer)? XDMAC_CIE_BIE : XDMAC_CIE_LIE); + + } else { + TRACE_ERROR("DmaProgState is incorrect \n\r"); + return 1; + } + memory_barrier(); + if (XDMAD_ConfigureTransfer( pXdmadTx, pUartTx->ChNum, &xdmadTxCfg, xdmaCndc, + (uint32_t)pUartTx->pLLIview, xdmaInt)) + return USARTD_ERROR; + return 0; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes the UartDma structure and the corresponding UART & DMA . + * hardware select value. + * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX. + * The DMA channels are freed automatically when no UART command processing. + * + * \param pUartd Pointer to a UartDma instance. + * \param pUartHw Associated UART peripheral. + * \param uartId UART peripheral identifier. + * \param uartMode UART peripheral identifier.* + * \param baud UART baud rate + * \param clk UART ref clock + * \param pXdmad Pointer to a Dmad instance. + */ +uint32_t UARTD_Configure( UartDma *pUartd , + uint8_t uartId, + uint32_t uartMode, + uint32_t baud, + uint32_t clk) +{ + /* Enable the peripheral clock in the PMC*/ + PMC_EnablePeripheral( uartId ); + + /* Initialize the UART structure */ + pUartd->uartId = uartId; + + if (uartId == ID_UART0) + pUartd->pUartHw = UART0; + if (uartId == ID_UART1) + pUartd->pUartHw = UART1; + if (uartId == ID_UART2) + pUartd->pUartHw = UART2; + if (uartId == ID_UART3) + pUartd->pUartHw = UART3; + if (uartId == ID_UART4) + pUartd->pUartHw = UART4; + + pUartd->pXdmad->pXdmacs = XDMAC; + + /* Enable the UART Peripheral ,Execute a software reset of the UART, + Configure UART in Master Mode*/ + UART_Configure ( pUartd->pUartHw, uartMode, baud, clk); + + /* Driver initialize */ + XDMAD_Initialize( pUartd->pXdmad, 0 ); + + /* Check if DMA IRQ is enable; if not clear pending IRQs in init it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) { + NVIC_ClearPendingIRQ(XDMAC_IRQn); + } + return 0; +} + +/** + * \brief This function initialize the appropriate DMA channel for Rx channel of + * UART + * \param pUartd Pointer to a UartDma instance. + * \param pRxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR + * if the command is not valid. + */ +uint32_t UARTD_EnableRxChannels( UartDma *pUartd, UartChannel *pRxCh) +{ + Uart *pUartHw = pUartd->pUartHw; + uint32_t Channel; + + assert(pRxCh); + /* Init USART Rx Channel. */ + pUartd->pRxChannel = pRxCh; + + /* Enables the USART to receive data. */ + UART_SetReceiverEnabled ( pUartHw , ENABLE); + + + /* Allocate a DMA channel for UART RX. */ + Channel = XDMAD_AllocateChannel( pUartd->pXdmad, pUartd->uartId, + XDMAD_TRANSFER_MEMORY); + if ( Channel == XDMAD_ALLOC_FAILED ) { + return UARTD_ERROR; + } + pRxCh->ChNum = Channel ; + + /* Setup callbacks for UART RX */ + if(pRxCh->callback) { + XDMAD_SetCallback(pUartd->pXdmad, pRxCh->ChNum, + (XdmadTransferCallback)pRxCh->callback, pRxCh->pArgument); + } else { + XDMAD_SetCallback(pUartd->pXdmad, pRxCh->ChNum, + (XdmadTransferCallback)UARTD_Rx_Cb, pUartd); + } + + if (XDMAD_PrepareChannel( pUartd->pXdmad, pRxCh->ChNum )) + return UARTD_ERROR; + if (_configureUartRxDma(pUartd, pRxCh)) + return UARTD_ERROR_LOCK; + /* Check if DMA IRQ is enable; if not Enable it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) { + /* Enable interrupt */ + NVIC_EnableIRQ(XDMAC_IRQn); + } + return 0; +} + +/** + * \brief This function initialize the appropriate DMA channel for Tx channel of + * UART + * \param pUartd Pointer to a UartDma instance. + * \param pTxCh Pointer to RxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR + * if the command is not valid. + */ +uint32_t UARTD_EnableTxChannels( UartDma *pUartd, UartChannel *pTxCh) +{ + Uart *pUartHw = pUartd->pUartHw; + uint32_t Channel; + + /* Init USART Tx Channel. */ + pUartd->pTxChannel = pTxCh; + + /* Enables the USART to transfer data. */ + UART_SetTransmitterEnabled ( pUartHw , ENABLE); + + /* Allocate a DMA channel for UART TX. */ + Channel = XDMAD_AllocateChannel( pUartd->pXdmad, + XDMAD_TRANSFER_MEMORY, pUartd->uartId); + if ( pTxCh->ChNum == XDMAD_ALLOC_FAILED ) { + return USARTD_ERROR; + } + + pTxCh->ChNum = Channel ; + + /* Setup callbacks for UART TX */ + if(pUartd->pTxChannel->callback) { + XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, + (XdmadTransferCallback)pTxCh->callback, pTxCh->pArgument); + } else { + XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)UARTD_Tx_Cb, pUartd); + } + + if ( XDMAD_PrepareChannel( pUartd->pXdmad, pTxCh->ChNum )) + return USARTD_ERROR; + + if (_configureUartTxDma(pUartd, pTxCh)) + return USARTD_ERROR_LOCK; + + /* Check if DMA IRQ is enable; if not Enable it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) { + /* Enable interrupt */ + NVIC_EnableIRQ(XDMAC_IRQn); + } + + return 0; +} + +/** + * \brief This function disables the appropriate DMA channel for Rx channel of + * USART + * \param pUsartd Pointer to a UsartDma instance. + * \param pRxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR + * if the command is not valid. + */ + +uint32_t UARTD_DisableRxChannels( UartDma *pUartd, UartChannel *pRxCh) +{ + assert(pRxCh); + + /* Enables the USART to transfer data. */ + UART_SetReceiverEnabled ( pUartd->pUartHw , DISABLE); + + XDMAD_StopTransfer(pUartd->pXdmad, pRxCh->ChNum); + + XDMAD_SetCallback(pUartd->pXdmad, pRxCh->ChNum, NULL, NULL); + + /* Free allocated DMA channel for USART TX. */ + if(XDMAD_FreeChannel( pUartd->pXdmad, pRxCh->ChNum) != XDMAD_OK) { + return USARTD_ERROR; + } + + if (pRxCh->dmaProgrammingMode == XDMAD_LLI) { + free(pRxCh->pLLIview); + pRxCh->pLLIview = NULL; + } + + pRxCh->sempaphore = 1; + memory_barrier(); + return 0; +} + + +/** + * \brief This function disables the appropriate DMA channel for Tx channel of + * USART + * \param pUsartd Pointer to a USARTDma instance. + * \param pTxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR + * if the command is not valid. + */ + +uint32_t UARTD_DisableTxChannels( UartDma *pUartd, UartChannel *pTxCh) +{ + assert(pTxCh); + + /* Enables the USART to transfer data. */ + UART_SetTransmitterEnabled ( pUartd->pUartHw , DISABLE); + + XDMAD_StopTransfer(pUartd->pXdmad, pTxCh->ChNum); + + XDMAD_SetCallback(pUartd->pXdmad, pTxCh->ChNum, NULL, NULL); + + /* Free allocated DMA channel for USART TX. */ + if(XDMAD_FreeChannel( pUartd->pXdmad, pTxCh->ChNum) != XDMAD_OK) { + return USARTD_ERROR; + } + + if (pTxCh->dmaProgrammingMode == XDMAD_LLI) { + free(pTxCh->pLLIview); + pTxCh->pLLIview = NULL; + } + + pTxCh->sempaphore = 1; + memory_barrier(); + return 0; +} + +/** + * \brief Starts a UART master transfer. This is a non blocking function. It + * will return as soon as the transfer is started. + * + * \param pUartd Pointer to a UartDma instance. + * \returns 0 if the transfer has been started successfully; otherwise returns + * UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR if the command is + * not valid. + */ +uint32_t UARTD_SendData( UartDma *pUartd) +{ + /* Start DMA 0(RX) && 1(TX) */ + SCB_CleanInvalidateDCache(); + pUartd->pTxChannel->sempaphore=0; + memory_barrier(); + if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pTxChannel->ChNum )) + return USARTD_ERROR_LOCK; + + return 0; +} + +/** + * \brief Starts a UART master transfer. This is a non blocking function. It + * will return as soon as the transfer is started. + * + * \param pUartd Pointer to a UartDma instance. + * \returns 0 if the transfer has been started successfully; otherwise returns + * UARTD_ERROR_LOCK is the driver is in use, or UARTD_ERROR if the command is + * not valid. + */ +uint32_t UARTD_RcvData( UartDma *pUartd) +{ + SCB_CleanInvalidateDCache(); + pUartd->pRxChannel->sempaphore=0; + memory_barrier(); + /* Start DMA 0(RX) && 1(TX) */ + if (XDMAD_StartTransfer( pUartd->pXdmad, pUartd->pRxChannel->ChNum )) + return USARTD_ERROR_LOCK; + + return 0; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/usart.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/usart.c new file mode 100644 index 000000000..d7b66eadc --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/usart.c @@ -0,0 +1,467 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of USART (Universal Synchronous Asynchronous Receiver + * Transmitter) controller. + * + */ +/*------------------------------------------------------------------------------ + * Headers + *-----------------------------------------------------------------------------*/ +#include "chip.h" + +#include +#include + +/*---------------------------------------------------------------------------- + * Local definitions + *----------------------------------------------------------------------------*/ + + +/*------------------------------------------------------------------------------ + * Exported functions + *-----------------------------------------------------------------------------*/ + +/** + * \brief Configures an USART baudrate. + * + * + * \param pUsart Pointer to the USART peripheral to configure. + * \param baudrate Baudrate at which the USART should operate (in Hz). + * \param masterClock Frequency of the system master clock (in Hz). + */ +void USART_SetBaudrate(Usart *pUsart, + uint8_t OverSamp, + uint32_t baudrate, + uint32_t masterClock) +{ + unsigned int CD, FP, BaudError, ActualBaudRate; + /* Configure baudrate*/ + BaudError = 10; + OverSamp = 0; + + /*Asynchronous*/ + if ((pUsart->US_MR & US_MR_SYNC) == 0) + { + /* 7816 mode */ + if( ((pUsart->US_MR & US_MR_USART_MODE_IS07816_T_0) + == US_MR_USART_MODE_IS07816_T_0 ) + || ((pUsart->US_MR & US_MR_USART_MODE_IS07816_T_1) + == US_MR_USART_MODE_IS07816_T_1 )) + { + /* Define the baud rate divisor register */ + /* CD = MCK / SCK */ + /* SCK = FIDI x BAUD = 372 x 9600 */ + /* BOARD_MCK */ + /* CD = MCK/(FIDI x BAUD) = 150000000 / (372x9600) = 42 */ + CD = masterClock / (pUsart->US_FIDI * baudrate); + FP = 0; + } + else{ + while (BaudError > 5) { + CD = (masterClock / (baudrate * 8 *( 2 - OverSamp))); + FP = ((masterClock / (baudrate * ( 2 - OverSamp)) ) - CD * 8); + ActualBaudRate = (masterClock/(CD * 8 + FP)) / ( 2 - OverSamp); + BaudError = (100 - ((baudrate * 100 / ActualBaudRate))); + + if (BaudError > 5) + { + OverSamp++; + if(OverSamp >= 2) + { + TRACE_ERROR("Canont set this baudrate \n\r"); + break; + } + } + } + } + } + /*Synchronous SPI */ + if((pUsart->US_MR & US_MR_USART_MODE_SPI_MASTER) + == US_MR_USART_MODE_SPI_MASTER + || ((pUsart->US_MR & US_MR_SYNC) == US_MR_SYNC) ) + { + if( (pUsart->US_MR & US_MR_USCLKS_Msk) == US_MR_USCLKS_MCK) + { + CD = masterClock / baudrate; + FP = ((masterClock / baudrate) - CD); + } + } + + pUsart->US_BRGR = ( US_BRGR_CD(CD) | US_BRGR_FP(FP)); + + /* Configure OverSamp*/ + pUsart->US_MR |= (OverSamp << 19); +} + +/** + * \brief Configures an USART peripheral with the specified parameters. + * + * + * \param pUsart Pointer to the USART peripheral to configure. + * \param mode Desired value for the USART mode register (see the datasheet). + * \param baudrate Baudrate at which the USART should operate (in Hz). + * \param masterClock Frequency of the system master clock (in Hz). + */ +void USART_Configure(Usart *pUsart, + uint32_t mode, + uint32_t baudrate, + uint32_t masterClock) +{ + + /* Reset and disable receiver & transmitter*/ + pUsart->US_CR = US_CR_RSTRX | US_CR_RSTTX + | US_CR_RXDIS | US_CR_TXDIS | US_CR_RSTSTA; + pUsart->US_IDR = 0xFFFFFFFF; + + pUsart->US_MR = mode; + /* Configure baudrate*/ + USART_SetBaudrate(pUsart, 0, baudrate, masterClock); + + /* Enable receiver and transmitter */ + pUsart->US_CR = US_CR_RXEN | US_CR_TXEN; + + /* Disable buffering for printf(). */ +#if ( defined (__GNUC__) && !defined (__SAMBA__) ) + setvbuf(stdout, (char *)NULL, _IONBF, 0); +#endif + +} +/** + * \brief Enables or disables the transmitter of an USART peripheral. + * + * + * \param pUsart Pointer to an USART peripheral + * \param enabled If true, the transmitter is enabled; otherwise it is + * disabled. + */ +void USART_SetTransmitterEnabled(Usart *pUsart, uint8_t enabled) +{ + if (enabled) { + pUsart->US_CR = US_CR_TXEN; + } else { + pUsart->US_CR = US_CR_TXDIS; + } +} + +/** + * \brief Disables the Receiver of an USART peripheral. + * + * \param pUsart Pointer to an USART peripheral + */ +void USART_DisableRx(Usart *pUsart) +{ + + pUsart->US_CR = US_CR_RXDIS; +} + +/** + * \brief Disables the transmitter of an USART peripheral. + * + * \param pUsart Pointer to an USART peripheral + */ +void USART_DisableTx(Usart *pUsart) +{ + pUsart->US_CR = US_CR_TXDIS; +} + +/** + * \brief Enables the Receiver of an USART peripheral. + * + * \param pUsart Pointer to an USART peripheral + */ +void USART_EnableRx(Usart *pUsart) +{ + + pUsart->US_CR = US_CR_RXEN; +} + +/** + * \brief Enables the transmitter of an USART peripheral + * + * \param pUsart Pointer to an USART peripheral + */ +void USART_EnableTx(Usart *pUsart) +{ + pUsart->US_CR = US_CR_TXEN; +} +/** + * \brief Resets or disables the Receiver of an USART peripheral. + * + * + * \param pUsart Pointer to an USART peripheral + */ +void USART_ResetRx(Usart *pUsart) +{ + + pUsart->US_CR = US_CR_RSTRX | US_CR_RXDIS; +} + +/** + * \brief resets and disables the transmitter of an USART peripheral. + * + * + * \param pUsart Pointer to an USART peripheral + */ +void USART_ResetTx(Usart *pUsart) +{ + pUsart->US_CR = US_CR_RSTTX | US_CR_TXDIS; +} +/** + * \brief Enables or disables the receiver of an USART peripheral + * + * + * \param pUsart Pointer to an USART peripheral + * \param enabled If true, the receiver is enabled; otherwise it is disabled. + */ +void USART_SetReceiverEnabled(Usart *pUsart, uint8_t enabled) +{ + if (enabled) { + pUsart->US_CR = US_CR_RXEN; + } else { + pUsart->US_CR = US_CR_RXDIS; + } +} + +/** + * \brief Enables or disables the Request To Send (RTS) of an USART peripheral + * + * + * \param pUsart Pointer to an USART peripheral + * \param enabled If true, the RTS is enabled (0); otherwise it is disabled. + */ +void USART_SetRTSEnabled( Usart *pUsart, uint8_t enabled) +{ + if (enabled) { + pUsart->US_CR = US_CR_RTSEN; + } else { + pUsart->US_CR = US_CR_RTSDIS; + } +} + +/** + * \brief Sends one packet of data through the specified USART peripheral. This + * function operates synchronously, so it only returns when the data has been + * actually sent. + * + * + * \param pUsart Pointer to an USART peripheral. + * \param data Data to send including 9nth bit and sync field if necessary (in + * the same format as the US_THR register in the datasheet). + * \param timeOut Time out value (0 = no timeout). + */ +void USART_Write( Usart *pUsart, uint16_t data, volatile uint32_t timeOut) +{ + if (timeOut == 0) { + while ((pUsart->US_CSR & US_CSR_TXEMPTY) == 0); + } else { + while ((pUsart->US_CSR & US_CSR_TXEMPTY) == 0) { + if (timeOut == 0) { + TRACE_ERROR("USART_Write: Timed out.\n\r"); + return; + } + timeOut--; + } + } + pUsart->US_THR = data; +} + +/** + * \brief Reads and return a packet of data on the specified USART peripheral. + * This function operates asynchronously, so it waits until some data has been + * received. + * + * \param pUsart Pointer to an USART peripheral. + * \param timeOut Time out value (0 -> no timeout). + */ +uint16_t USART_Read( Usart *pUsart, volatile uint32_t timeOut) +{ + if (timeOut == 0) { + while ((pUsart->US_CSR & US_CSR_RXRDY) == 0); + } else { + while ((pUsart->US_CSR & US_CSR_RXRDY) == 0) { + if (timeOut == 0) { + TRACE_ERROR( "USART_Read: Timed out.\n\r" ) ; + return 0; + } + timeOut--; + } + } + return pUsart->US_RHR; +} + +/** + * \brief Returns 1 if some data has been received and can be read from an + * USART; otherwise returns 0. + * + * \param pUsart Pointer to an USART instance. + */ +uint8_t USART_IsDataAvailable(Usart *pUsart) +{ + if ((pUsart->US_CSR & US_CSR_RXRDY) != 0) { + return 1; + } else { + return 0; + } +} + +/** + * \brief Sends one packet of data through the specified USART peripheral. This + * function operates synchronously, so it only returns when the data has been + * actually sent. + * + * \param pUsart Pointer to an USART peripheral. + * \param c Character to send + */ +void USART_PutChar( Usart *pUsart, uint8_t c) +{ + /* Wait for the transmitter to be ready*/ + while ((pUsart->US_CSR & US_CSR_TXEMPTY) == 0); + + /* Send character*/ + pUsart->US_THR = c; + + /* Wait for the transfer to complete*/ + while ((pUsart->US_CSR & US_CSR_TXEMPTY) == 0); +} + +/** + * \brief Return 1 if a character can be read in USART + * \param pUsart Pointer to an USART peripheral. + */ +uint32_t USART_IsRxReady(Usart *pUsart) +{ + return (pUsart->US_CSR & US_CSR_RXRDY); +} + +/** + * \brief Get present status + * \param pUsart Pointer to an USART peripheral. + */ +uint32_t USART_GetStatus(Usart *pUsart) +{ + return pUsart->US_CSR; +} + +/** + * \brief Enable interrupt + * \param pUsart Pointer to an USART peripheral. + * \param mode Interrupt mode. + */ +void USART_EnableIt(Usart *pUsart,uint32_t mode) +{ + pUsart->US_IER = mode; +} + +/** + * \brief Disable interrupt + * \param pUsart Pointer to an USART peripheral. + * \param mode Interrupt mode. + */ +void USART_DisableIt(Usart *pUsart,uint32_t mode) +{ + pUsart->US_IDR = mode; +} + +/** + * \brief Return interrupt mask + * \param pUsart Pointer to an USART peripheral. + */ +uint32_t USART_GetItMask(Usart *pUsart) +{ + return pUsart->US_IMR; +} + +/** + * \brief Reads and returns a character from the USART. + * + * \note This function is synchronous (i.e. uses polling). + * \param pUsart Pointer to an USART peripheral. + * \return Character received. + */ +uint8_t USART_GetChar(Usart *pUsart) +{ + while ((pUsart->US_CSR & US_CSR_RXRDY) == 0); + return pUsart->US_RHR; +} + +/** + * \brief Enable Rx Timeout for USART. + * + * \param pUsart Pointer to an USART peripheral. + * \param Timeout Timeout value + * \return None + */ +void USART_EnableRecvTimeOut(Usart *pUsart, uint32_t Timeout) +{ + if( Timeout <= MAX_RX_TIMEOUT ) { + pUsart->US_RTOR = Timeout; + } else if( Timeout == 0) { + TRACE_DEBUG("Timeout is disabled\n\r"); + } else { + TRACE_INFO_WP("\n\r"); + TRACE_FATAL("Timeout value is out of range\n\r"); + } +} + +/** + * \brief Enable Tx Timeout for USART. + * + * \param pUsart Pointer to an USART peripheral. + * \param TimeGaurd TimeGaurd value + * \return None + */ +void USART_EnableTxTimeGaurd(Usart *pUsart, uint32_t TimeGaurd) +{ + if( ( (pUsart->US_MR & US_MR_USART_MODE_LON ) && TimeGaurd <= 16777215) || + ((pUsart->US_MR & US_MR_USART_MODE_LON ) && TimeGaurd <= 255) ) { + pUsart->US_TTGR = TimeGaurd; + } else { + TRACE_ERROR(" TimeGaurd Value is too big for mode"); + } +} +/** + * \brief Acknowledge Rx timeout and sets to Idle or periodic repetitive state. + * + * \param pUsart Pointer to an USART peripheral. + * \param Periodic If timeout is periodic or should wait for new char + * \return None + */ +void USART_AcknowledgeRxTimeOut(Usart *pUsart, uint8_t Periodic) +{ + if(Periodic) { + pUsart->US_CR = US_CR_RETTO; // Restart timeout timer + } else { + // Puts USARt in Idle mode and waits for a char after timeout + pUsart->US_CR = US_CR_STTTO; + } +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/usart_dma.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/usart_dma.c new file mode 100644 index 000000000..e10d8548d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/usart_dma.c @@ -0,0 +1,580 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + /** + * \addtogroup usart_dma_module USART xDMA driver + * \section Usage + * + *
      + *
    • USARTD_Configure() initializes and configures the USART peripheral + * and xDMA for data transfer.
      • + *
    • Configures the parameters for the device corresponding to the cs + * value by USARTD_ConfigureCS().
      • + *
    + * + */ + +/** + * \file + * + * Implementation for the USART with xDMA driver. + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include "string.h" +#include "stdlib.h" + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ + +/** + * \brief USART xDMA Rx callback + * Invoked on USART DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to USARTDma instance. + */ +static void USARTD_Rx_Cb(uint32_t channel, UsartDma* pArg) +{ + + UsartChannel *pUsartdCh = pArg->pRxChannel; + if (channel != pUsartdCh->ChNum) + return; + + /* Release the DMA channels */ + XDMAD_FreeChannel(pArg->pXdmad, pUsartdCh->ChNum); + pUsartdCh->dmaProgress = 1; + memory_barrier(); +} + +/** + * \brief USART xDMA Rx callback + * Invoked on USART DMA reception done. + * \param channel DMA channel. + * \param pArg Pointer to callback argument - Pointer to USARTDma instance. + */ +static void USARTD_Tx_Cb(uint32_t channel, UsartDma* pArg) +{ + UsartChannel *pUsartdCh = pArg->pTxChannel; + if (channel != pUsartdCh->ChNum) + return; + /* Release the DMA channels */ + XDMAD_FreeChannel(pArg->pXdmad, pUsartdCh->ChNum); + + pUsartdCh->dmaProgress = 1; + memory_barrier(); +} + +/** + * \brief Configure the USART Rx DMA Destination with Linker List mode. + * + * \param UsartChannel Pointer to USART dma channel + * \returns 0 if the dma multibuffer configuration successfully; otherwise + * returnsUSARTD_ERROR_XXX. + */ +static uint8_t _configureRxDma(UsartDma *pUsart, UsartChannel *pUsartRx) +{ + sXdmadCfg xdmadRxCfg; + uint32_t xdmaCndc, xdmaInt; + uint32_t i, LLI_Size; + Usart *pUsartHwRx = pUsart->pUsartHw; + sXdmad* pXdmadRx = pUsart->pXdmad; + uint8_t *pBuff = 0; + + + /* Setup RX Single block */ + if(pUsartRx->dmaProgrammingMode < XDMAD_LLI) { + xdmadRxCfg.mbr_ubc = pUsartRx->BuffSize; + xdmadRxCfg.mbr_da = (uint32_t)pUsartRx->pBuff; + + xdmadRxCfg.mbr_sa = (uint32_t)&pUsartHwRx->US_RHR; + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( pUsart->usartId, XDMAD_TRANSFER_RX )); + + xdmadRxCfg.mbr_bc = 0; + if(pUsartRx->dmaProgrammingMode == XDMAD_MULTI) + { + xdmadRxCfg.mbr_bc = pUsartRx->dmaBlockSize; + } + xdmadRxCfg.mbr_sus = 0; + xdmadRxCfg.mbr_dus =0; + xdmaCndc = 0; + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_DIE | + XDMAC_CIE_FIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + } else if(pUsartRx->dmaProgrammingMode == XDMAD_LLI) { + + /* Setup RX Link List */ + LLI_Size = pUsartRx->dmaBlockSize; + pBuff = pUsartRx->pBuff; + if(pUsartRx->pLLIview != NULL) + { + free(pUsartRx->pLLIview); + pUsartRx->pLLIview = NULL; + } + + pUsartRx->pLLIview = malloc(sizeof(LinkedListDescriporView1)*LLI_Size); + if( pUsartRx->pLLIview == NULL) { + TRACE_ERROR(" Can not allocate memory to Rx LLI"); + return USARTD_ERROR; + } + xdmadRxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_PER2MEM | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF1 | + XDMAC_CC_DIF_AHB_IF0 | + XDMAC_CC_SAM_FIXED_AM | + XDMAC_CC_DAM_INCREMENTED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( pUsart->usartId, XDMAD_TRANSFER_RX )); + xdmadRxCfg.mbr_bc = 0; + for (i = 0; i < LLI_Size; i++) { + pUsartRx->pLLIview[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | + XDMA_UBC_NSEN_UNCHANGED | + XDMA_UBC_NDEN_UPDATED | + ((i== LLI_Size- 1)? ( + (pUsartRx->dmaRingBuffer)? + XDMA_UBC_NDE_FETCH_EN : 0): + XDMA_UBC_NDE_FETCH_EN) | + pUsartRx->BuffSize; + pUsartRx->pLLIview[i].mbr_sa = (uint32_t)&pUsartHwRx->US_RHR; + pUsartRx->pLLIview[i].mbr_da = (uint32_t)pBuff; + pUsartRx->pLLIview[i].mbr_nda = (i == ( LLI_Size - 1))? + ( (pUsartRx->dmaRingBuffer)? (uint32_t)pUsartRx->pLLIview : 0 ) + :(uint32_t)&pUsartRx->pLLIview[ i + 1 ]; + pBuff += pUsartRx->BuffSize; + } + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED| + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + xdmaInt = ((pUsartRx->dmaRingBuffer)? XDMAC_CIE_BIE : XDMAC_CIE_LIE); + } else { + return 1; + } + memory_barrier(); + if (XDMAD_ConfigureTransfer( + pXdmadRx, pUsartRx->ChNum, &xdmadRxCfg, xdmaCndc, + (uint32_t)pUsartRx->pLLIview, xdmaInt)) + return USARTD_ERROR; + return 0; +} + +/** + * \brief Configure the USART tx DMA source with Linker List mode. + * + * \param UsartChannel Pointer to USART dma channel + * \returns 0 if the dma multibuffer configuration successfully; otherwise returns + * USARTD_ERROR_XXX. + */ +static uint8_t _configureTxDma(UsartDma *pUsart, UsartChannel *pUsartTx) +{ + sXdmadCfg xdmadTxCfg; + uint32_t xdmaCndc, xdmaInt, LLI_Size, i; + uint8_t *pBuff = 0; + Usart *pUsartHwTx = pUsart->pUsartHw; + sXdmad* pXdmadTx = pUsart->pXdmad; + + /* Setup TX Link List */ + + if(pUsartTx->dmaProgrammingMode < XDMAD_LLI) { + /* Number of Data */ + xdmadTxCfg.mbr_ubc = pUsartTx->BuffSize; + /* Source and Destination address of DMA */ + xdmadTxCfg.mbr_sa = (uint32_t)pUsartTx->pBuff; + xdmadTxCfg.mbr_da = (uint32_t)&pUsartHwTx->US_THR; + /* DMA Channel configuration */ + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE| + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( pUsart->usartId, XDMAD_TRANSFER_TX )); + + xdmadTxCfg.mbr_bc = 0; + if(pUsartTx->dmaProgrammingMode == XDMAD_MULTI) + { + xdmadTxCfg.mbr_bc = pUsartTx->dmaBlockSize; + } + xdmadTxCfg.mbr_sus = 0; + xdmadTxCfg.mbr_dus =0; + xdmadTxCfg.mbr_ds= 0; + xdmaCndc = 0; + /* Enable End of Block; Read Bus error; Write Bus Error; + Overflow Error interrupt */ + xdmaInt = (XDMAC_CIE_BIE | + XDMAC_CIE_RBIE | + XDMAC_CIE_WBIE | + XDMAC_CIE_ROIE); + } else if(pUsartTx->dmaProgrammingMode == XDMAD_LLI) { + LLI_Size = pUsartTx->dmaBlockSize; + pBuff = pUsartTx->pBuff; + /* If channel's LLI is already configured and application + want to reconfigured it, free before re-allocating memory */ + if(pUsartTx->pLLIview != NULL) { + free(pUsartTx->pLLIview); + pUsartTx->pLLIview = NULL; + } + pUsartTx->pLLIview = malloc(sizeof(LinkedListDescriporView1)*LLI_Size); + + if( pUsartTx->pLLIview == NULL) { + TRACE_ERROR(" Can not allocate memory to Tx LLI"); + return USARTD_ERROR; + } + + xdmadTxCfg.mbr_cfg = XDMAC_CC_TYPE_PER_TRAN | + XDMAC_CC_MBSIZE_SIXTEEN | + XDMAC_CC_DSYNC_MEM2PER | + XDMAC_CC_MEMSET_NORMAL_MODE | + XDMAC_CC_CSIZE_CHK_1 | + XDMAC_CC_DWIDTH_BYTE | + XDMAC_CC_SIF_AHB_IF0 | + XDMAC_CC_DIF_AHB_IF1 | + XDMAC_CC_SAM_INCREMENTED_AM | + XDMAC_CC_DAM_FIXED_AM | + XDMAC_CC_PERID(XDMAIF_Get_ChannelNumber + ( pUsart->usartId, XDMAD_TRANSFER_TX )); + xdmadTxCfg.mbr_bc = 0; + for (i = 0; i < LLI_Size; i++) { + pUsartTx->pLLIview[i].mbr_ubc = XDMA_UBC_NVIEW_NDV1 | + XDMA_UBC_NSEN_UPDATED | + XDMA_UBC_NDEN_UNCHANGED | + ((i== LLI_Size- 1)? ( (pUsartTx->dmaRingBuffer) + ? XDMA_UBC_NDE_FETCH_EN : 0): + XDMA_UBC_NDE_FETCH_EN) | pUsartTx->BuffSize; + pUsartTx->pLLIview[i].mbr_sa = (uint32_t)pBuff; + pUsartTx->pLLIview[i].mbr_da = (uint32_t)&pUsartHwTx->US_THR; + pUsartTx->pLLIview[i].mbr_nda = (i == ( LLI_Size - 1))? + ( (pUsartTx->dmaRingBuffer)? (uint32_t)pUsartTx->pLLIview : 0 ) + :(uint32_t)&pUsartTx->pLLIview[ i + 1 ]; + pBuff += pUsartTx->BuffSize; + } + xdmaCndc = XDMAC_CNDC_NDVIEW_NDV1 | + XDMAC_CNDC_NDE_DSCR_FETCH_EN | + XDMAC_CNDC_NDSUP_SRC_PARAMS_UPDATED| + XDMAC_CNDC_NDDUP_DST_PARAMS_UPDATED ; + xdmaInt = ((pUsartTx->dmaRingBuffer)? XDMAC_CIE_BIE : XDMAC_CIE_LIE); + } else { + TRACE_ERROR("DmaProgState is incorrect \n\r"); + return 1; + } + memory_barrier(); + if (XDMAD_ConfigureTransfer( pXdmadTx, pUsartTx->ChNum, + &xdmadTxCfg, xdmaCndc, (uint32_t)pUsartTx->pLLIview, xdmaInt)) + return USARTD_ERROR; + return 0; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ +/** + * \brief Initializes the USARTDma structure and the corresponding USART & DMA . + * hardware select value. + * The driver will uses DMA channel 0 for RX and DMA channel 1 for TX. + * The DMA channels are freed automatically when no USART command processing. + * + * \param pUSARTD Pointer to a UsartDma instance. + * \param pUsartHw Associated USART peripheral. + * \param usartId USART peripheral identifier. + * \param UsartClk USART clock. + * \param pXdmad Pointer to a Dmad instance. + */ +uint32_t USARTD_Configure( UsartDma *pUsartd , + uint8_t usartId, + uint32_t UsartMode, + uint32_t BaudRate, + uint32_t UsartClk) +{ + /* Enable the peripheral clock in the PMC*/ + PMC_EnablePeripheral( usartId ); + + /* Initialize the USART structure */ + pUsartd->usartId = usartId; + + if (usartId == ID_USART0) + pUsartd->pUsartHw = USART0; + if (usartId == ID_USART1) + pUsartd->pUsartHw = USART1; + if (usartId == ID_USART2) + pUsartd->pUsartHw = USART2; + + + pUsartd->pXdmad->pXdmacs = XDMAC; + /* Enable the USART Peripheral ,Execute a software reset of the USART, + Configure USART in Master Mode*/ + USART_Configure ( pUsartd->pUsartHw, UsartMode, BaudRate, UsartClk); + + /* Driver initialize */ + XDMAD_Initialize( pUsartd->pXdmad, 0 ); + + /* Check if DMA IRQ is enable; if not clear pending IRQs in init it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) { + NVIC_ClearPendingIRQ(XDMAC_IRQn); + } + return 0; +} + +/** + * \brief This function initialize the appropriate DMA channel for Rx channel + * of USART + * \param pUsartd Pointer to a UsartDma instance. + * \param pRxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns USARTD_ERROR_LOCK is the driver is in use, or + * USARTD_ERROR if the command is not valid. + */ +uint32_t USARTD_EnableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh) +{ + uint32_t Channel; + + assert(pRxCh); + /* Init USART Rx Channel. */ + pUsartd->pRxChannel = pRxCh; + + /* Enables the USART to receive data. */ + USART_SetReceiverEnabled ( pUsartd->pUsartHw , ENABLE); + + + /* Allocate a DMA channel for USART0/1 RX. */ + Channel = XDMAD_AllocateChannel( pUsartd->pXdmad, pUsartd->usartId, + XDMAD_TRANSFER_MEMORY); + if ( Channel == XDMAD_ALLOC_FAILED ) { + return USARTD_ERROR; + } + + pRxCh->ChNum = Channel; + + /* Setup callbacks for USART RX */ + if(pUsartd->pRxChannel->callback) { + XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum, + (XdmadTransferCallback)pRxCh->callback, pRxCh->pArgument); + } else { + XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum, + (XdmadTransferCallback)USARTD_Rx_Cb, pUsartd); + } + + + if (XDMAD_PrepareChannel( pUsartd->pXdmad, pRxCh->ChNum )) + return USARTD_ERROR; + + if (_configureRxDma(pUsartd , pUsartd->pRxChannel)) + return USARTD_ERROR_LOCK; + + /* Check if DMA IRQ is enable; if not Enable it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) { + /* Enable interrupt */ + NVIC_EnableIRQ(XDMAC_IRQn); + } + return 0; +} + +/** + * \brief This function initialize the appropriate DMA channel for Tx channel + * of USART + * \param pUsartd Pointer to a USARTDma instance. + * \param pTxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns USARTD_ERROR_LOCK is the driver is in use, or + * USARTD_ERROR if the command is not valid. + */ +uint32_t USARTD_EnableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh) +{ + + uint32_t Channel; + + assert(pTxCh); + + /* Init USART Tx Channel. */ + pUsartd->pTxChannel = pTxCh; + + /* Enables the USART to transfer data. */ + USART_SetTransmitterEnabled ( pUsartd->pUsartHw , ENABLE); + + /* Allocate a DMA channel for USART0/1 TX. */ + Channel = XDMAD_AllocateChannel( pUsartd->pXdmad, XDMAD_TRANSFER_MEMORY, + pUsartd->usartId); + if ( Channel == XDMAD_ALLOC_FAILED ) { + return USARTD_ERROR; + } + pTxCh->ChNum = Channel; + /* Setup callbacks for USART0/1 TX */ + if(pUsartd->pTxChannel->callback) { + XDMAD_SetCallback(pUsartd->pXdmad, pTxCh->ChNum, + (XdmadTransferCallback)pTxCh->callback, pTxCh->pArgument); + } else { + XDMAD_SetCallback(pUsartd->pXdmad, pTxCh->ChNum, (XdmadTransferCallback)USARTD_Tx_Cb, pUsartd); + } + + if ( XDMAD_PrepareChannel( pUsartd->pXdmad, pTxCh->ChNum )) + return USARTD_ERROR; + + if (_configureTxDma(pUsartd , pUsartd->pTxChannel)) + return USARTD_ERROR_LOCK; + + /* Check if DMA IRQ is enable; if not Enable it */ + if(!(NVIC_GetActive(XDMAC_IRQn))) { + /* Enable interrupt */ + NVIC_EnableIRQ(XDMAC_IRQn); + } + return 0; +} + +/** + * \brief This function disables the appropriate DMA channel for Rx channel of + * USART + * \param pUsartd Pointer to a UsartDma instance. + * \param pRxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns USARTD_ERROR_LOCK is the driver is in use, or + * USARTD_ERROR if the command is not valid. + */ +uint32_t USARTD_DisableRxChannels( UsartDma *pUsartd, UsartChannel *pRxCh) +{ + assert(pRxCh); + + /* Enables the USART to transfer data. */ + USART_SetReceiverEnabled ( pUsartd->pUsartHw , DISABLE); + + XDMAD_StopTransfer(pUsartd->pXdmad, pRxCh->ChNum); + + XDMAD_SetCallback(pUsartd->pXdmad, pRxCh->ChNum, NULL, NULL); + /* Free allocated DMA channel for USART TX. */ + if(XDMAD_FreeChannel( pUsartd->pXdmad, pRxCh->ChNum) != XDMAD_OK) { + return USARTD_ERROR; + } + + if (pRxCh->dmaProgrammingMode == XDMAD_LLI) { + free(pRxCh->pLLIview); + pRxCh->pLLIview = NULL; + } + pRxCh->dmaProgress = 1; + memory_barrier(); + return 0; +} + +/** + * \brief This function disables the appropriate DMA channel for Tx channel of + * USART + * \param pUsartd Pointer to a USARTDma instance. + * \param pTxCh Pointer to TxChannel configuration + * \returns 0 if the transfer has been started successfully; + * otherwise returns USARTD_ERROR_LOCK is the driver is in use, or + * USARTD_ERROR if the command is not valid. + */ + +uint32_t USARTD_DisableTxChannels( UsartDma *pUsartd, UsartChannel *pTxCh) +{ + assert(pTxCh); + + /* Enables the USART to transfer data. */ + USART_SetTransmitterEnabled ( pUsartd->pUsartHw , DISABLE); + + XDMAD_StopTransfer(pUsartd->pXdmad, pTxCh->ChNum); + + XDMAD_SetCallback(pUsartd->pXdmad, pTxCh->ChNum, NULL, NULL); + /* Free allocated DMA channel for USART TX. */ + if(XDMAD_FreeChannel( pUsartd->pXdmad, pTxCh->ChNum) != XDMAD_OK) { + return USARTD_ERROR; + } + + if (pTxCh->dmaProgrammingMode == XDMAD_LLI) { + free(pTxCh->pLLIview); + pTxCh->pLLIview = NULL; + } + pTxCh->dmaProgress = 1; + memory_barrier(); + return 0; +} + +/** + * \brief Starts a USART master transfer. This is a non blocking function. It + * will return as soon as the transfer is started. + * + * \param pUSARTD Pointer to a USARTDma instance. + * \returns 0 if the transfer has been started successfully; otherwise returns + * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is + * not valid. + */ +uint32_t USARTD_SendData( UsartDma *pUsartd) +{ + /* Start DMA 0(RX) && 1(TX) */ + SCB_CleanInvalidateDCache(); + pUsartd->pTxChannel->dmaProgress=0; + memory_barrier(); + if (XDMAD_StartTransfer( pUsartd->pXdmad, pUsartd->pTxChannel->ChNum )) + return USARTD_ERROR_LOCK; + return 0; +} + +/** + * \brief Starts a USART master transfer. This is a non blocking function. It will + * return as soon as the transfer is started. + * + * \param pUSARTD Pointer to a USARTDma instance. + * \returns 0 if the transfer has been started successfully; otherwise returns + * USARTD_ERROR_LOCK is the driver is in use, or USARTD_ERROR if the command is not + * valid. + */ +uint32_t USARTD_RcvData( UsartDma *pUsartd) +{ + /* Start DMA 0(RX) && 1(TX) */ + SCB_CleanInvalidateDCache(); + pUsartd->pRxChannel->dmaProgress=0; + memory_barrier(); + if (XDMAD_StartTransfer( pUsartd->pXdmad, pUsartd->pRxChannel->ChNum )) + return USARTD_ERROR_LOCK; + return 0; +} + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/wdt.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/wdt.c new file mode 100644 index 000000000..2d97a6b9e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/wdt.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2012, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** + * \file + * + * Implementation of Watchdog Timer (WDT) controller. + * + */ + +/** \addtogroup wdt_module Working with WDT + * \ingroup peripherals_module + * The WDT driver provides the interface to configure and use the WDT + * peripheral. + * + * The WDT can be used to prevent system lock-up if the software becomes + * trapped in a deadlock. It can generate a general reset or a processor + * reset only. It is clocked by slow clock divided by 128. + * + * The WDT is running at reset with 16 seconds watchdog period (slow clock at + * 32.768 kHz) + * and external reset generation enabled. The user must either disable it or + * reprogram it to meet the application requires. + * + * To use the WDT, the user could follow these few steps: + *
      + *
    • Enable watchdog with given mode using \ref WDT_Enable(). + *
    • Restart the watchdog using \ref WDT_Restart() within the watchdog period. + *
    + * + * For more accurate information, please look at the WDT section of the + * Datasheet. + * + * \note + * The Watchdog Mode Register (WDT_MR) can be written only once.\n + * + * Related files :\n + * \ref wdt.c\n + * \ref wdt.h.\n + */ +/*@{*/ +/*@}*/ + +/*--------------------------------------------------------------------------- + * Headers + *---------------------------------------------------------------------------*/ + +#include "chip.h" + +#include + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Enable watchdog with given mode. + * + * \note The Watchdog Mode Register (WDT_MR) can be written only once. + * Only a processor reset resets it. + * + * \param dwMode WDT mode to be set + */ +extern void WDT_Enable( Wdt* pWDT, uint32_t dwMode ) +{ + pWDT->WDT_MR = dwMode ; +} + +/** + * \brief Disable watchdog. + * + * \note The Watchdog Mode Register (WDT_MR) can be written only once. + * Only a processor reset resets it. + */ +extern void WDT_Disable( Wdt* pWDT ) +{ + pWDT->WDT_MR = WDT_MR_WDDIS; +} + +/** + * \brief Watchdog restart. + */ +extern void WDT_Restart( Wdt* pWDT ) +{ + pWDT->WDT_CR = 0xA5000001; +} + +/** + * \brief Watchdog get status. + */ +extern uint32_t WDT_GetStatus( Wdt* pWDT ) +{ + return (pWDT->WDT_SR & 0x3) ; +} + +/** + * \brief Watchdog get period. + * + * \param dwMs desired watchdog period in millisecond. + */ +extern uint32_t WDT_GetPeriod( uint32_t dwMs ) +{ + if ( (dwMs < 4) || (dwMs > 16000) ) { + return 0 ; + } + return ((dwMs << 8) / 1000) ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdma_hardware_interface.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdma_hardware_interface.c new file mode 100644 index 000000000..052ba71ee --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdma_hardware_interface.c @@ -0,0 +1,158 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2013, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup dmad_module + * + * \section DmaHw Dma Hardware Interface Usage + *
      + *
    • The DMA controller can handle the transfer between peripherals and memory + * and so receives the triggers from the peripherals. The hardware interface + * number are getting from DMAIF_Get_ChannelNumber().
      • + + *
    • DMAIF_IsValidatedPeripherOnDma() helps to check if the given DMAC has + * associated peripheral identifier coded by the given peripheral.
      • + * + *
    + */ +/*@{*/ +/*@}*/ + +/** \file */ +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ +#include "chip.h" + +/*---------------------------------------------------------------------------- + * Local variables + *----------------------------------------------------------------------------*/ +/** Array of DMA Channel definition for SAMv7 chip*/ +static const XdmaHardwareInterface xdmaHwIf[] = { +/* xdmac, peripheral, T/R, HW interface number*/ + {0, ID_HSMCI, 0, 0}, + {0, ID_HSMCI, 1, 0}, + {0, ID_SPI0, 0, 1}, + {0, ID_SPI0, 1, 2}, + {0, ID_SPI1, 0, 3}, + {0, ID_SPI1, 1, 4}, + {0, ID_QSPI, 0, 5}, + {0, ID_QSPI, 1, 6}, + {0, ID_USART0, 0, 7}, + {0, ID_USART0, 1, 8}, + {0, ID_USART1, 0, 9}, + {0, ID_USART1, 1, 10}, + {0, ID_USART2, 0, 11}, + {0, ID_USART2, 1, 12}, + {0, ID_PWM0, 0, 13}, + {0, ID_TWIHS0, 0, 14}, + {0, ID_TWIHS0, 1, 15}, + {0, ID_TWIHS1, 0, 16}, + {0, ID_TWIHS1, 1, 17}, + {0, ID_TWIHS2, 0, 18}, + {0, ID_TWIHS2, 1, 19}, + {0, ID_UART0, 0, 20}, + {0, ID_UART0, 1, 21}, + {0, ID_UART1, 0, 22}, + {0, ID_UART1, 1, 23}, + {0, ID_UART2, 0, 24}, + {0, ID_UART2, 1, 25}, + {0, ID_UART3, 0, 26}, + {0, ID_UART3, 1, 27}, + {0, ID_UART4, 0, 28}, + {0, ID_UART4, 1, 29}, + {0, ID_DACC, 0, 30}, + {0, ID_DACC, 0, 31}, + {0, ID_SSC, 0, 32}, + {0, ID_SSC, 1, 33}, + {0, ID_PIOA, 1, 34}, + {0, ID_AFEC0, 1, 35}, + {0, ID_AFEC1, 1, 36}, + {0, ID_AES, 0, 37}, + {0, ID_AES, 1, 38}, + {0, ID_PWM1, 0, 39}, + {0, ID_TC0, 1, 40}, + {0, ID_TC1, 1, 41}, + {0, ID_TC2, 1, 42}, + {0, ID_TC3, 1, 43}, +}; + + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Get peripheral identifier coded for hardware handshaking interface + * + * \param bDmac DMA Controller number. + * \param bPeriphID Peripheral ID. + * \param bTransfer Transfer type 0: Tx, 1 :Rx. + * \return 0-15 peripheral identifier coded. + * 0xff : no associated peripheral identifier coded. + */ +uint8_t XDMAIF_Get_ChannelNumber (uint8_t bPeriphID, + uint8_t bTransfer) +{ + uint8_t i; + uint8_t NumOfPeripheral = ((XDMAC_GetType(XDMAC) & 0x00FF0000) >> 16); + for (i = 0; i <=NumOfPeripheral; i++) + { + if ( (xdmaHwIf[i].bPeriphID == bPeriphID) && + (xdmaHwIf[i].bTransfer == bTransfer)) { + return xdmaHwIf[i].bIfID; + } + } + return 0xff; +} + +/** + * \brief Check if the given DMAC has associated peripheral identifier coded by + * the given peripheral. + * + * \param bDmac DMA Controller number. + * \param bPeriphID Peripheral ID (0xff : memory only). + * \return 1: Is a validated peripheral. 0: no associated peripheral identifier + * coded. + */ +uint8_t XDMAIF_IsValidatedPeripherOnDma( uint8_t bPeriphID) +{ + uint8_t i; + uint8_t NumOfPeripheral = ((XDMAC_GetType(XDMAC) & 0x00FF0000) >> 16); + /* It is always validated when transfer to memory */ + if (bPeriphID == 0xFF) { + return 1; + } + + for (i = 0; i <=NumOfPeripheral; i++) { + if ((xdmaHwIf[i].bPeriphID == bPeriphID)) { + return 1; + } + } + return 0; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdmac.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdmac.c new file mode 100644 index 000000000..edc4d35ed --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdmac.c @@ -0,0 +1,547 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + + +/** + * \file + * + * Implementation of xDMA controller (XDMAC). + * + */ + +/*---------------------------------------------------------------------------- + * Headers + *----------------------------------------------------------------------------*/ + +#include "chip.h" + +#include +#include +/** \addtogroup dmac_functions XDMAC Functions + *@{ + */ + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Get XDMAC global type. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetType( Xdmac *pXdmac) +{ + assert(pXdmac); + return pXdmac->XDMAC_GTYPE; +} + +/** + * \brief Get XDMAC global configuration. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetConfig( Xdmac *pXdmac) +{ + assert(pXdmac); + return pXdmac->XDMAC_GCFG; +} + +/** + * \brief Get XDMAC global weighted arbiter configuration. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetArbiter( Xdmac *pXdmac) +{ + assert(pXdmac); + return pXdmac->XDMAC_GWAC; +} + +/** + * \brief Enables XDMAC global interrupt. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param dwInteruptMask IT to be enabled. + */ +void XDMAC_EnableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask ) +{ + assert(pXdmac); + pXdmac->XDMAC_GIE = ( XDMAC_GIE_IE0 << dwInteruptMask) ; +} + +/** + * \brief Disables XDMAC global interrupt + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param dwInteruptMask IT to be enabled + */ +void XDMAC_DisableGIt (Xdmac *pXdmac, uint8_t dwInteruptMask ) +{ + assert(pXdmac); + pXdmac->XDMAC_GID = (XDMAC_GID_ID0 << dwInteruptMask); +} + +/** + * \brief Get XDMAC global interrupt mask. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetGItMask( Xdmac *pXdmac ) +{ + assert(pXdmac); + return (pXdmac->XDMAC_GIM); +} + +/** + * \brief Get XDMAC global interrupt status. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetGIsr( Xdmac *pXdmac ) +{ + assert(pXdmac); + return (pXdmac->XDMAC_GIS); +} + +/** + * \brief Get XDMAC masked global interrupt. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetMaskedGIsr( Xdmac *pXdmac ) +{ + uint32_t _dwStatus; + assert(pXdmac); + _dwStatus = pXdmac->XDMAC_GIS; + _dwStatus &= pXdmac->XDMAC_GIM; + return _dwStatus; +} + +/** + * \brief enables the relevant channel of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_EnableChannel( Xdmac *pXdmac, uint8_t channel ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GE = (XDMAC_GE_EN0 << channel); +} + +/** + * \brief enables the relevant channels of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param bmChannels Channels bitmap. + */ +void XDMAC_EnableChannels( Xdmac *pXdmac, uint32_t bmChannels ) +{ + assert(pXdmac); + pXdmac->XDMAC_GE = bmChannels; +} + +/** + * \brief Disables the relevant channel of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_DisableChannel( Xdmac *pXdmac, uint8_t channel ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GD =( XDMAC_GD_DI0 << channel); +} + +/** + * \brief Disables the relevant channels of given XDMAC. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param bmChannels Channels bitmap. + */ +void XDMAC_DisableChannels( Xdmac *pXdmac, uint32_t bmChannels ) +{ + assert(pXdmac); + pXdmac->XDMAC_GD = bmChannels; +} + + +/** + * \brief Get Global channel status of given XDMAC. + * \note: When set to 1, this bit indicates that the channel x is enabled. + If a channel disable request is issued, this bit remains asserted + until pending transaction is completed. + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetGlobalChStatus(Xdmac *pXdmac) +{ + assert(pXdmac); + return pXdmac->XDMAC_GS; +} + +/** + * \brief Suspend the relevant channel's read. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_SuspendReadChannel( Xdmac *pXdmac, uint8_t channel ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRS |= XDMAC_GRS_RS0 << channel; +} + +/** + * \brief Suspend the relevant channel's write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_SuspendWriteChannel( Xdmac *pXdmac, uint8_t channel ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GWS |= XDMAC_GWS_WS0 << channel; +} + +/** + * \brief Suspend the relevant channel's read & write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_SuspendReadWriteChannel( Xdmac *pXdmac, uint8_t channel ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRWS = (XDMAC_GRWS_RWS0 << channel); +} + +/** + * \brief Resume the relevant channel's read & write. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_ResumeReadWriteChannel( Xdmac *pXdmac, uint8_t channel ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GRWR = (XDMAC_GRWR_RWR0 << channel); +} + +/** + * \brief Set software transfer request on the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_SoftwareTransferReq(Xdmac *pXdmac, uint8_t channel) +{ + + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GSWR = (XDMAC_GSWR_SWREQ0 << channel); +} + +/** + * \brief Get software transfer status of the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + */ +uint32_t XDMAC_GetSoftwareTransferStatus(Xdmac *pXdmac) +{ + + assert(pXdmac); + return pXdmac->XDMAC_GSWS; +} + +/** + * \brief Set software flush request on the relevant channel. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +void XDMAC_SoftwareFlushReq(Xdmac *pXdmac, uint8_t channel) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_GSWF = (XDMAC_GSWF_SWF0 << channel); + while( !(XDMAC_GetChannelIsr(pXdmac, channel) & XDMAC_CIS_FIS) ); +} + +/** + * \brief Disable interrupt with mask on the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dwInteruptMask Interrupt mask. + */ +void XDMAC_EnableChannelIt (Xdmac *pXdmac, uint8_t channel, uint8_t dwInteruptMask ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CIE = dwInteruptMask; +} + +/** + * \brief Enable interrupt with mask on the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dwInteruptMask Interrupt mask. + */ +void XDMAC_DisableChannelIt (Xdmac *pXdmac, uint8_t channel, uint8_t dwInteruptMask ) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CID = dwInteruptMask; +} + +/** + * \brief Get interrupt mask for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t XDMAC_GetChannelItMask (Xdmac *pXdmac, uint8_t channel) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CIM; +} + +/** + * \brief Get interrupt status for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t XDMAC_GetChannelIsr (Xdmac *pXdmac, uint8_t channel) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CIS; +} + +/** + * \brief Get masked interrupt status for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t XDMAC_GetMaskChannelIsr (Xdmac *pXdmac, uint8_t channel) +{ + uint32_t status; + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + status = pXdmac->XDMAC_CHID[channel].XDMAC_CIS; + status &= pXdmac->XDMAC_CHID[channel].XDMAC_CIM; + + return status; +} + +/** + * \brief Set source address for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Source address. + */ +void XDMAC_SetSourceAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CSA = addr; +} + +/** + * \brief Set destination address for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Destination address. + */ +void XDMAC_SetDestinationAddr(Xdmac *pXdmac, uint8_t channel, uint32_t addr) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDA = addr; +} + +/** + * \brief Set next descriptor's address & interface for the relevant channel of + * given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param addr Address of next descriptor. + * \param ndaif Interface of next descriptor. + */ +void XDMAC_SetDescriptorAddr(Xdmac *pXdmac, uint8_t channel, + uint32_t addr, uint8_t ndaif) +{ + assert(pXdmac); + assert(ndaif<2); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CNDA = ( addr & 0xFFFFFFFC ) | ndaif; +} + +/** + * \brief Set next descriptor's configuration for the relevant channel of + * given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param config Configuration of next descriptor. + */ +void XDMAC_SetDescriptorControl(Xdmac *pXdmac, uint8_t channel, uint8_t config) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CNDC = config; +} + +/** + * \brief Set microblock length for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param ublen Microblock length. + */ +void XDMAC_SetMicroblockControl(Xdmac *pXdmac, uint8_t channel, uint32_t ublen) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CUBC = XDMAC_CUBC_UBLEN(ublen); +} + +/** + * \brief Set block length for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param blen Block length. + */ +void XDMAC_SetBlockControl(Xdmac *pXdmac, uint8_t channel, uint16_t blen) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CBC = XDMAC_CBC_BLEN(blen); +} + +/** + * \brief Set configuration for the relevant channel of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param config Channel configuration. + */ +void XDMAC_SetChannelConfig(Xdmac *pXdmac, uint8_t channel, uint32_t config) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CC = config; +} + +/** + * \brief Get the relevant channel's configuration of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t XDMAC_GetChannelConfig(Xdmac *pXdmac, uint8_t channel) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CC; +} + +/** + * \brief Set the relevant channel's data stride memory pattern of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dds_msp Data stride memory pattern. + */ +void XDMAC_SetDataStride_MemPattern(Xdmac *pXdmac, uint8_t channel, uint32_t dds_msp) +{ + + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDS_MSP = dds_msp; +} + +/** + * \brief Set the relevant channel's source microblock stride of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param subs Source microblock stride. + */ +void XDMAC_SetSourceMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t subs) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CSUS = XDMAC_CSUS_SUBS(subs); +} + +/** + * \brief Set the relevant channel's destination microblock stride of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + * \param dubs Destination microblock stride. + */ +void XDMAC_SetDestinationMicroBlockStride(Xdmac *pXdmac, uint8_t channel, uint32_t dubs) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + pXdmac->XDMAC_CHID[channel].XDMAC_CDUS = XDMAC_CDUS_DUBS(dubs); +} + +/** + * \brief Get the relevant channel's destination address of given XDMA. + * + * \param pXdmac Pointer to the XDMAC peripheral. + * \param channel Particular channel number. + */ +uint32_t XDMAC_GetChDestinationAddr(Xdmac *pXdmac, uint8_t channel) +{ + assert(pXdmac); + assert(channel < XDMAC_CHANNEL_NUM); + return pXdmac->XDMAC_CHID[channel].XDMAC_CDA; +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdmad.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdmad.c new file mode 100644 index 000000000..2c70a996e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/libchip_samv7/source/xdmad.c @@ -0,0 +1,494 @@ +/* ---------------------------------------------------------------------------- + * SAM Software Package License + * ---------------------------------------------------------------------------- + * Copyright (c) 2014, Atmel Corporation + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * - Redistributions of source code must retain the above copyright notice, + * this list of conditions and the disclaimer below. + * + * Atmel's name may not be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE + * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * ---------------------------------------------------------------------------- + */ + +/** \addtogroup xdmad_module + * + * \section Xdma xDma Configuration Usage + * + * To configure a XDMA channel, the user has to follow these few steps : + *
      + *
    • Initialize a XDMA driver instance by XDMAD_Initialize().
      • + *
    • choose an available (disabled) channel using XDMAD_AllocateChannel().
      • + *
    • After the XDMAC selected channel has been programmed, + * XDMAD_PrepareChannel() is to enable clock and dma peripheral of the DMA, and + * set Configuration register to set up the transfer type (memory or non-memory + * peripheral for source and destination) and flow control device.
      • + *
    • Invoke XDMAD_StartTransfer() to start DMA transfer or + * XDMAD_StopTransfer() to force stop DMA transfer.
      • + *
    • Once the buffer of data is transferred, XDMAD_IsTransferDone() + * checks if DMA transfer is finished.
      • + *
    • XDMAD_Handler() handles XDMA interrupt, and invoking XDMAD_SetCallback() + * if provided.
      • + *
    + * + * Related files:\n + * \ref xdmad.h\n + * \ref xdmad.c.\n + */ + +/** \file */ + +/** \addtogroup dmad_functions + @{*/ + +/*---------------------------------------------------------------------------- + * Includes + *----------------------------------------------------------------------------*/ + +#include "chip.h" +#include +static uint8_t xDmad_Initialized = 0; + +/*---------------------------------------------------------------------------- + * Local functions + *----------------------------------------------------------------------------*/ +/** + * \brief Try to allocate a DMA channel for on given controller. + * \param pDmad Pointer to DMA driver instance. + * \param bSrcID Source peripheral ID, 0xFF for memory. + * \param bDstID Destination peripheral ID, 0xFF for memory. + * \return Channel number if allocation successful, return + * DMAD_ALLOC_FAILED if allocation failed. + */ +static uint32_t XDMAD_AllocateXdmacChannel( sXdmad *pXdmad, + uint8_t bSrcID, + uint8_t bDstID) +{ + uint32_t i; + /* Can't support peripheral to peripheral */ + if ((( bSrcID != XDMAD_TRANSFER_MEMORY ) + && ( bDstID != XDMAD_TRANSFER_MEMORY ))) { + return XDMAD_ALLOC_FAILED; + } + /* dma transfer from peripheral to memory */ + if ( bDstID == XDMAD_TRANSFER_MEMORY) { + if( (!XDMAIF_IsValidatedPeripherOnDma(bSrcID)) ) { + TRACE_ERROR("%s:: Allocation failed", __FUNCTION__); + return XDMAD_ALLOC_FAILED; + } + } + /* dma transfer from memory to peripheral */ + if ( bSrcID == XDMAD_TRANSFER_MEMORY ) { + if( (!XDMAIF_IsValidatedPeripherOnDma(bDstID)) ) { + TRACE_ERROR("%s:: Allocation failed", __FUNCTION__); + return XDMAD_ALLOC_FAILED; + } + } + + for (i = 0; i < pXdmad->numChannels; i ++) { + if ( pXdmad->XdmaChannels[i].state == XDMAD_STATE_FREE ) { + /* Allocate the channel */ + pXdmad->XdmaChannels[i].state = XDMAD_STATE_ALLOCATED; + /* Get general informations */ + pXdmad->XdmaChannels[i].bSrcPeriphID = bSrcID; + pXdmad->XdmaChannels[i].bDstPeriphID = bDstID; + pXdmad->XdmaChannels[i].bSrcTxIfID = + XDMAIF_Get_ChannelNumber(bSrcID, 0); + pXdmad->XdmaChannels[i].bSrcRxIfID = + XDMAIF_Get_ChannelNumber(bSrcID, 1); + pXdmad->XdmaChannels[i].bDstTxIfID = + XDMAIF_Get_ChannelNumber(bDstID, 0); + pXdmad->XdmaChannels[i].bDstRxIfID = + XDMAIF_Get_ChannelNumber(bDstID, 1); + return ((i) & 0xFF); + } + } + TRACE_ERROR("%s:: Allocation failed, all channels are occupied", __FUNCTION__); + return XDMAD_ALLOC_FAILED; +} + +/*---------------------------------------------------------------------------- + * Exported functions + *----------------------------------------------------------------------------*/ + +/** + * \brief Initialize xDMA driver instance. + * \param pXdmad Pointer to xDMA driver instance. + * \param bPollingMode Polling DMA transfer: + * 1. Via XDMAD_IsTransferDone(); or + * 2. Via XDMAD_Handler(). + */ +void XDMAD_Initialize( sXdmad *pXdmad, uint8_t bPollingMode ) +{ + uint32_t j; + uint32_t volatile timer=0x7FF; + + assert( pXdmad) ; + LockMutex(pXdmad->xdmaMutex, timer); + if (xDmad_Initialized) { + ReleaseMutex(pXdmad->xdmaMutex); + return; + } + pXdmad->pXdmacs = XDMAC; + pXdmad->pollingMode = bPollingMode; + pXdmad->numControllers = XDMAC_CONTROLLER_NUM; + pXdmad->numChannels = (XDMAC_GTYPE_NB_CH( XDMAC_GetType(XDMAC) ) + 1); + + for (j = 0; j < pXdmad->numChannels; j ++) { + pXdmad->XdmaChannels[j].fCallback = 0; + pXdmad->XdmaChannels[j].pArg = 0; + pXdmad->XdmaChannels[j].bIrqOwner = 0; + pXdmad->XdmaChannels[j].bSrcPeriphID = 0; + pXdmad->XdmaChannels[j].bDstPeriphID = 0; + pXdmad->XdmaChannels[j].bSrcTxIfID = 0; + pXdmad->XdmaChannels[j].bSrcRxIfID = 0; + pXdmad->XdmaChannels[j].bDstTxIfID = 0; + pXdmad->XdmaChannels[j].bDstRxIfID = 0; + pXdmad->XdmaChannels[j].state = XDMAD_STATE_FREE; + } + xDmad_Initialized = 1; + ReleaseMutex(pXdmad->xdmaMutex); +} + + +/** + * \brief Allocate a XDMA channel for upper layer. + * \param pXdmad Pointer to xDMA driver instance. + * \param bSrcID Source peripheral ID, 0xFF for memory. + * \param bDstID Destination peripheral ID, 0xFF for memory. + * \return Channel number if allocation successful, return + * XDMAD_ALLOC_FAILED if allocation failed. + */ +uint32_t XDMAD_AllocateChannel( sXdmad *pXdmad, + uint8_t bSrcID, + uint8_t bDstID) +{ + uint32_t dwChannel = XDMAD_ALLOC_FAILED; + uint32_t volatile timer=0x7FF; + + LockMutex(pXdmad->xdmaMutex, timer); + dwChannel = XDMAD_AllocateXdmacChannel( pXdmad, bSrcID, bDstID ); + ReleaseMutex(pXdmad->xdmaMutex); + + return dwChannel; +} + +/** + * \brief Free the specified xDMA channel. + * \param pXdmad Pointer to xDMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eXdmadRC XDMAD_FreeChannel( sXdmad *pXdmad, + uint32_t dwChannel ) +{ + uint8_t iChannel = (dwChannel) & 0xFF; + assert( pXdmad != NULL ) ; + if (iChannel >= pXdmad->numChannels) return XDMAD_ERROR; + switch ( pXdmad->XdmaChannels[iChannel].state ) { + case XDMAD_STATE_ALLOCATED: + case XDMAD_STATE_START: + case XDMAD_STATE_IN_XFR: + return XDMAD_BUSY; + case XDMAD_STATE_DONE: + case XDMAD_STATE_HALTED: + pXdmad->XdmaChannels[iChannel].state = XDMAD_STATE_FREE; + break; + } + return XDMAD_OK; +} + +/** + * \brief Set the callback function for xDMA channel transfer. + * \param pXdmad Pointer to xDMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + * \param fCallback Pointer to callback function. + * \param pArg Pointer to optional argument for callback. + */ +eXdmadRC XDMAD_SetCallback( sXdmad *pXdmad, + uint32_t dwChannel, + XdmadTransferCallback fCallback, + void* pArg ) +{ + + uint8_t iChannel = (dwChannel) & 0xFF; + assert( pXdmad != NULL ) ; + if (iChannel >= pXdmad->numChannels) return XDMAD_ERROR; + if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE ) + return XDMAD_ERROR; + else if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START ) + return XDMAD_BUSY; + + pXdmad->XdmaChannels[iChannel].fCallback = fCallback; + pXdmad->XdmaChannels[iChannel].pArg = pArg; + + return XDMAD_OK; +} + + +/** + * \brief Enable clock of the xDMA peripheral, Enable the dma peripheral, + * configure configuration register for xDMA transfer. + * \param pXdmad Pointer to xDMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + * \param dwCfg Configuration value. + */ +eXdmadRC XDMAD_PrepareChannel( sXdmad *pXdmad, uint32_t dwChannel) +{ + + uint8_t iChannel = (dwChannel) & 0xFF; + Xdmac *pXdmac = pXdmad->pXdmacs; + + assert( pXdmad != NULL ) ; + if (iChannel >= pXdmad->numChannels) return XDMAD_ERROR; + + if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE ) + return XDMAD_ERROR; + else if ( ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START ) + || ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_IN_XFR ) ) + return XDMAD_BUSY; + + + /* Enable clock of the DMA peripheral */ + if (!PMC_IsPeriphEnabled( ID_XDMAC )) { + PMC_EnablePeripheral( ID_XDMAC ); + } + /* Clear dummy status */ + XDMAC_GetChannelIsr( pXdmac,iChannel ); + /* Disables XDMAC interrupt for the given channel. */ + XDMAC_DisableGIt (pXdmac, iChannel); + XDMAC_DisableChannelIt (pXdmac, iChannel, 0xFF); + /* Disable the given dma channel. */ + XDMAC_DisableChannel( pXdmac, iChannel ); + XDMAC_SetSourceAddr(pXdmac, iChannel, 0); + XDMAC_SetDestinationAddr(pXdmac, iChannel, 0); + XDMAC_SetBlockControl(pXdmac, iChannel, 0); + XDMAC_SetChannelConfig( pXdmac, iChannel, 0x20); + XDMAC_SetDescriptorAddr(pXdmac, iChannel, 0, 0); + XDMAC_SetDescriptorControl(pXdmac, iChannel, 0); + return XDMAD_OK; +} + +/** + * \brief xDMA interrupt handler + * \param pxDmad Pointer to DMA driver instance. + */ +void XDMAD_Handler( sXdmad *pDmad) +{ + Xdmac *pXdmac; + sXdmadChannel *pCh; + uint32_t xdmaChannelIntStatus, xdmaGlobaIntStatus,xdmaGlobalChStatus; + uint8_t bExec = 0; + uint8_t _iChannel; + assert( pDmad != NULL ) ; + + pXdmac = pDmad->pXdmacs; + xdmaGlobaIntStatus = XDMAC_GetGIsr(pXdmac); + if ((xdmaGlobaIntStatus & 0xFFFFFF) != 0) { + xdmaGlobalChStatus = XDMAC_GetGlobalChStatus(pXdmac); + for (_iChannel = 0; _iChannel < pDmad->numChannels; _iChannel ++) { + if (!(xdmaGlobaIntStatus & (1<<_iChannel))) continue; + pCh = &pDmad->XdmaChannels[_iChannel]; + if ( pCh->state == XDMAD_STATE_FREE) return ; + if ((xdmaGlobalChStatus & ( XDMAC_GS_ST0 << _iChannel)) == 0) { + bExec = 0; + xdmaChannelIntStatus = XDMAC_GetMaskChannelIsr( pXdmac, _iChannel); + if (xdmaChannelIntStatus & XDMAC_CIS_BIS) { + if((XDMAC_GetChannelItMask(pXdmac, _iChannel) & XDMAC_CIM_LIM) + == 0 ) { + pCh->state = XDMAD_STATE_DONE ; + bExec = 1; + } + TRACE_DEBUG("XDMAC_CIS_BIS\n\r"); + } + if (xdmaChannelIntStatus & XDMAC_CIS_FIS) { + TRACE_DEBUG("XDMAC_CIS_FIS\n\r"); + } + if (xdmaChannelIntStatus & XDMAC_CIS_RBEIS) { + TRACE_DEBUG("XDMAC_CIS_RBEIS\n\r"); + } + if (xdmaChannelIntStatus & XDMAC_CIS_WBEIS) { + TRACE_DEBUG("XDMAC_CIS_WBEIS\n\r"); + } + if (xdmaChannelIntStatus & XDMAC_CIS_ROIS) { + TRACE_DEBUG("XDMAC_CIS_ROIS\n\r"); + } + if (xdmaChannelIntStatus & XDMAC_CIS_LIS) { + TRACE_DEBUG("XDMAC_CIS_LIS\n\r"); + pCh->state = XDMAD_STATE_DONE ; + bExec = 1; + } + if (xdmaChannelIntStatus & XDMAC_CIS_DIS ) + { + pCh->state = XDMAD_STATE_DONE ; + bExec = 1; + } + SCB_CleanInvalidateDCache(); + } else { + SCB_CleanInvalidateDCache(); + /* Block end interrupt for LLI dma mode */ + if( XDMAC_GetChannelIsr( pXdmac, _iChannel) & XDMAC_CIS_BIS) { + /* Execute callback */ + pCh->fCallback(_iChannel, pCh->pArg); + } + } + /* Execute callback */ + if (bExec && pCh->fCallback) { + pCh->fCallback(_iChannel, pCh->pArg); + } + } + } +} + +/** + * \brief Check if DMA transfer is finished. + * In polling mode XDMAD_Handler() is polled. + * \param pDmad Pointer to DMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eXdmadRC XDMAD_IsTransferDone( sXdmad *pXdmad, uint32_t dwChannel ) +{ + uint8_t iChannel = (dwChannel) & 0xFF; + uint8_t state; + assert( pXdmad != NULL ) ; + if (iChannel >= pXdmad->numChannels) + return XDMAD_ERROR; + + SCB_CleanInvalidateDCache(); + state = pXdmad->XdmaChannels[iChannel].state; + if ( state == XDMAD_STATE_ALLOCATED ) return XDMAD_OK; + if ( state == XDMAD_STATE_FREE ) return XDMAD_ERROR; + else if ( state != XDMAD_STATE_DONE ) { + if(pXdmad->pollingMode) XDMAD_Handler( pXdmad); + return XDMAD_BUSY; + } + return XDMAD_OK; +} + + +/** + * \brief Configure DMA for a single transfer. + * \param pXdmad Pointer to xDMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eXdmadRC XDMAD_ConfigureTransfer( sXdmad *pXdmad, + uint32_t dwChannel, + sXdmadCfg *pXdmaParam, + uint32_t dwXdmaDescCfg, + uint32_t dwXdmaDescAddr, + uint32_t dwXdmaIntEn) +{ + uint8_t iChannel = (dwChannel) & 0xFF; + + assert( pXdmad != NULL ) ; + if (iChannel >= pXdmad->numChannels) + return XDMAD_ERROR; + + Xdmac *pXdmac = pXdmad->pXdmacs; + XDMAC_GetChannelIsr( pXdmac, iChannel); + + if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE ) + return XDMAD_ERROR; + if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START ) + return XDMAD_BUSY; + /* Linked List is enabled */ + if ((dwXdmaDescCfg & XDMAC_CNDC_NDE) == XDMAC_CNDC_NDE_DSCR_FETCH_EN) { + if ((dwXdmaDescCfg & XDMAC_CNDC_NDVIEW_Msk) == XDMAC_CNDC_NDVIEW_NDV0) { + XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg ); + XDMAC_SetSourceAddr(pXdmac, iChannel, pXdmaParam->mbr_sa); + XDMAC_SetDestinationAddr(pXdmac, iChannel, pXdmaParam->mbr_da); + } + if ((dwXdmaDescCfg & XDMAC_CNDC_NDVIEW_Msk) == XDMAC_CNDC_NDVIEW_NDV1) { + XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg ); + } + XDMAC_SetDescriptorAddr(pXdmac, iChannel, dwXdmaDescAddr, 0); + XDMAC_SetDescriptorControl(pXdmac, iChannel, dwXdmaDescCfg); + XDMAC_DisableChannelIt (pXdmac, iChannel, 0xFF); + XDMAC_EnableChannelIt (pXdmac,iChannel, dwXdmaIntEn ); + } else { + /* LLI is disabled. */ + XDMAC_SetSourceAddr(pXdmac, iChannel, pXdmaParam->mbr_sa); + XDMAC_SetDestinationAddr(pXdmac, iChannel, pXdmaParam->mbr_da); + XDMAC_SetMicroblockControl(pXdmac, iChannel, pXdmaParam->mbr_ubc); + XDMAC_SetBlockControl(pXdmac, iChannel, pXdmaParam->mbr_bc); + XDMAC_SetDataStride_MemPattern(pXdmac, iChannel, pXdmaParam->mbr_ds); + XDMAC_SetSourceMicroBlockStride(pXdmac, iChannel, pXdmaParam->mbr_sus); + XDMAC_SetDestinationMicroBlockStride(pXdmac, iChannel, pXdmaParam->mbr_dus); + XDMAC_SetChannelConfig( pXdmac, iChannel, pXdmaParam->mbr_cfg ); + XDMAC_SetDescriptorAddr(pXdmac, iChannel, 0, 0); + XDMAC_SetDescriptorControl(pXdmac, iChannel, 0); + XDMAC_EnableChannelIt (pXdmac,iChannel,dwXdmaIntEn); + } + return XDMAD_OK; +} + +/** + * \brief Start xDMA transfer. + * \param pXdmad Pointer to XDMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eXdmadRC XDMAD_StartTransfer( sXdmad *pXdmad, uint32_t dwChannel ) +{ + uint8_t iChannel = (dwChannel) & 0xFF; + + assert( pXdmad != NULL ) ; + if (iChannel >= pXdmad->numChannels) return XDMAD_ERROR; + + Xdmac *pXdmac = pXdmad->pXdmacs; + if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_FREE ) { + TRACE_ERROR("%s:: XDMAD_STATE_FREE \n\r", __FUNCTION__); + return XDMAD_ERROR; + } else if ( pXdmad->XdmaChannels[iChannel].state == XDMAD_STATE_START ) { + TRACE_ERROR("%s:: XDMAD_STATE_START \n\r", __FUNCTION__) + return XDMAD_BUSY; + } + /* Change state to transferring */ + pXdmad->XdmaChannels[iChannel].state = XDMAD_STATE_START; + XDMAC_EnableChannel(pXdmac, iChannel); + if ( pXdmad->pollingMode == 0 ) { + XDMAC_EnableGIt( pXdmac, iChannel); + } + return XDMAD_OK; +} + + +/** + * \brief Stop DMA transfer. + * \param pDmad Pointer to DMA driver instance. + * \param dwChannel ControllerNumber << 8 | ChannelNumber. + */ +eXdmadRC XDMAD_StopTransfer( sXdmad *pXdmad, uint32_t dwChannel ) +{ + uint8_t _iChannel = (dwChannel) & 0xFF; + assert( pXdmad != NULL ) ; + if (_iChannel >= pXdmad->numChannels) return XDMAD_ERROR; + Xdmac *pXdmac = pXdmad->pXdmacs; + + pXdmad->XdmaChannels[_iChannel].state = XDMAD_STATE_HALTED; + /* Disable channel */ + XDMAC_DisableChannel(pXdmac, _iChannel); + /* Disable interrupts */ + XDMAC_DisableChannelIt(pXdmac, _iChannel, 0xFF); + /* Clear pending status */ + XDMAC_GetChannelIsr( pXdmac, _iChannel); + XDMAC_GetGlobalChStatus(pXdmac); + return XDMAD_OK; +} + +/**@}*/ + diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c new file mode 100644 index 000000000..6ccbcc75a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/main.c @@ -0,0 +1,241 @@ +/* + FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * This project provides two demo applications. A simple blinky style project, + * and a more comprehensive test and demo application. The + * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting (defined in this file) is used to + * select between the two. The simply blinky demo is implemented and described + * in main_blinky.c. The more comprehensive test and demo application is + * implemented and described in main_full.c. + * + * This file implements the code that is not demo specific, including the + * hardware setup and standard FreeRTOS hook functions. + * + * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON + * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO + * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * + */ + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Standard demo includes. */ +#include "TimerDemo.h" +#include "QueueOverwrite.h" +#include "EventGroupsDemo.h" +#include "IntSemTest.h" +#include "TaskNotify.h" + +/* Library includes. */ +#include "board.h" + +/* Set mainCREATE_SIMPLE_BLINKY_DEMO_ONLY to one to run the simple blinky demo, +or 0 to run the more comprehensive test and demo application. */ +#define mainCREATE_SIMPLE_BLINKY_DEMO_ONLY 1 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * main_blinky() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1. + * main_full() is used when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 0. + */ +#if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 + extern void main_blinky( void ); +#else + extern void main_full( void ); +#endif /* #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 */ + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting is described at the top + of this file. */ + #if( mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 1 ) + { + main_blinky(); + } + #else + { + main_full(); + } + #endif + + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ + /* Disable watchdog. */ + WDT_Disable( WDT ); + WDT_Disable( ( Wdt * ) RSWDT ); + + SCB_EnableICache(); + SCB_EnableDCache(); + + LED_Configure( 0 ); + LED_Configure( 1 ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + + /* Force an assert. */ + configASSERT( ( volatile void * ) NULL ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if mainCREATE_SIMPLE_BLINKY_DEMO_ONLY == 0 + { + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Call the code that uses a mutex from an ISR. */ + vInterruptSemaphorePeriodicTest(); + + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* Just to keep the linker happy. */ +int __write( int x ); +int __write( int x ) +{ + return x; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/sam_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/sam_flash.ld new file mode 100644 index 000000000..21f8553db --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/sam_flash.ld @@ -0,0 +1,139 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + /* heap section */ + .heap (NOLOAD): + { + . = ALIGN(8); + _sheap = .; + . = . + HEAP_SIZE; + . = ALIGN(8); + _eheap = .; + } > ram + + . = ALIGN(4); + _end = . ; + _ram_end_ = ORIGIN(ram) + LENGTH(ram) -1 ; +} diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/samv71q21_flash.ld b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/samv71q21_flash.ld new file mode 100644 index 000000000..b5b32a1ef --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_AtmelStudio/samv71q21_flash.ld @@ -0,0 +1,53 @@ +/* ---------------------------------------------------------------------------- */ +/* Atmel Microcontroller Software Support */ +/* SAM Software Package License */ +/* ---------------------------------------------------------------------------- */ +/* Copyright (c) 2014, Atmel Corporation */ +/* */ +/* All rights reserved. */ +/* */ +/* Redistribution and use in source and binary forms, with or without */ +/* modification, are permitted provided that the following condition is met: */ +/* */ +/* - Redistributions of source code must retain the above copyright notice, */ +/* this list of conditions and the disclaimer below. */ +/* */ +/* Atmel's name may not be used to endorse or promote products derived from */ +/* this software without specific prior written permission. */ +/* */ +/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ +/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ +/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ +/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ +/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ +/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ +/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ +/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ +/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ +/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/* ---------------------------------------------------------------------------- */ + +/*------------------------------------------------------------------------------ + * Linker script for running in internal FLASH on the ATSAMV71Q21 + *----------------------------------------------------------------------------*/ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00400000, LENGTH = 0x00200000 + ram (rwx) : ORIGIN = 0x20400000, LENGTH = 0x00060000 + sdram(rwx): ORIGIN = 0x70000000, LENGTH = 0x00200000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : 0x2000; + +/* The heapsize used by the application. NOTE: you need to adjust according to your application. */ +HEAP_SIZE = DEFINED(HEAP_SIZE) ? HEAP_SIZE : 0x1000; + +INCLUDE sam_flash.ld +INCLUDE sam_sdram.ld \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c index caf151531..92d02d91f 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/Full_Demo/IntQueueTimer.c @@ -196,5 +196,9 @@ volatile uint32_t ulDummy; /* Keep a count of the number of interrupts to use as a time base for the run-time stats. */ ulHighFrequencyTimerCounts++; + + /* Prevent compiler warnings about the variable being set but then + unused. */ + ( void ) ulDummy; } diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx index 39c48192f..ce0173f72 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvoptx @@ -142,12 +142,11 @@ 0 DLGUARM - 0 CMSIS_AGDI - -X"EDBG CMSIS-DAP" -UFFFFFFFFFFFFFFFFFFFF -O239 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -FO7 -FD20400000 -FC1000 -FN0 + -X"EDBG CMSIS-DAP" -UATML2407080200001813 -O239 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BD11477) -L00(0) -FO7 -FD20400000 -FC1000 -FN0 0 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx index 404fee89c..25ddcf2e1 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/RTOSDemo.uvprojx @@ -346,7 +346,7 @@ 1 - 0 + 1 0 0 1 diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h deleted file mode 100644 index 919611602..000000000 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/arm_math.h +++ /dev/null @@ -1,7390 +0,0 @@ -/* ---------------------------------------------------------------------- -* Copyright (C) 2010-2014 ARM Limited. All rights reserved. -* -* $Date: 12. March 2014 -* $Revision: V1.4.3 -* -* Project: CMSIS DSP Library -* Title: arm_math.h -* -* Description: Public header file for CMSIS DSP Library -* -* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* - Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* - Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in -* the documentation and/or other materials provided with the -* distribution. -* - Neither the name of ARM LIMITED nor the names of its contributors -* may be used to endorse or promote products derived from this -* software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE -* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, -* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, -* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT -* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN -* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -* POSSIBILITY OF SUCH DAMAGE. - * -------------------------------------------------------------------- */ - -/** - \mainpage CMSIS DSP Software Library - * - * Introduction - * ------------ - * - * This user manual describes the CMSIS DSP software library, - * a suite of common signal processing functions for use on Cortex-M processor based devices. - * - * The library is divided into a number of functions each covering a specific category: - * - Basic math functions - * - Fast math functions - * - Complex math functions - * - Filters - * - Matrix functions - * - Transforms - * - Motor control functions - * - Statistical functions - * - Support functions - * - Interpolation functions - * - * The library has separate functions for operating on 8-bit integers, 16-bit integers, - * 32-bit integer and 32-bit floating-point values. - * - * Using the Library - * ------------ - * - * The library installer contains prebuilt versions of the libraries in the Lib folder. - * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) - * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) - * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) - * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) - * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) - * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) - * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) - * - * The library functions are declared in the public file arm_math.h which is placed in the Include folder. - * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single - * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. - * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or - * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. - * - * Examples - * -------- - * - * The library ships with a number of examples which demonstrate how to use the library functions. - * - * Toolchain Support - * ------------ - * - * The library has been developed and tested with MDK-ARM version 4.60. - * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. - * - * Building the Library - * ------------ - * - * The library installer contains a project file to re build libraries on MDK-ARM Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. - * - arm_cortexM_math.uvproj - * - * - * The libraries can be built by opening the arm_cortexM_math.uvproj project in MDK-ARM, selecting a specific target, and defining the optional pre processor MACROs detailed above. - * - * Pre-processor Macros - * ------------ - * - * Each library project have differant pre-processor macros. - * - * - UNALIGNED_SUPPORT_DISABLE: - * - * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access - * - * - ARM_MATH_BIG_ENDIAN: - * - * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. - * - * - ARM_MATH_MATRIX_CHECK: - * - * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices - * - * - ARM_MATH_ROUNDING: - * - * Define macro ARM_MATH_ROUNDING for rounding on support functions - * - * - ARM_MATH_CMx: - * - * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target - * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. - * - * - __FPU_PRESENT: - * - * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries - * - *
    - * CMSIS-DSP in ARM::CMSIS Pack - * ----------------------------- - * - * The following files relevant to CMSIS-DSP are present in the ARM::CMSIS Pack directories: - * |File/Folder |Content | - * |------------------------------|------------------------------------------------------------------------| - * |\b CMSIS\\Documentation\\DSP | This documentation | - * |\b CMSIS\\DSP_Lib | Software license agreement (license.txt) | - * |\b CMSIS\\DSP_Lib\\Examples | Example projects demonstrating the usage of the library functions | - * |\b CMSIS\\DSP_Lib\\Source | Source files for rebuilding the library | - * - *
    - * Revision History of CMSIS-DSP - * ------------ - * Please refer to \ref ChangeLog_pg. - * - * Copyright Notice - * ------------ - * - * Copyright (C) 2010-2014 ARM Limited. All rights reserved. - */ - - -/** - * @defgroup groupMath Basic Math Functions - */ - -/** - * @defgroup groupFastMath Fast Math Functions - * This set of functions provides a fast approximation to sine, cosine, and square root. - * As compared to most of the other functions in the CMSIS math library, the fast math functions - * operate on individual values and not arrays. - * There are separate functions for Q15, Q31, and floating-point data. - * - */ - -/** - * @defgroup groupCmplxMath Complex Math Functions - * This set of functions operates on complex data vectors. - * The data in the complex arrays is stored in an interleaved fashion - * (real, imag, real, imag, ...). - * In the API functions, the number of samples in a complex array refers - * to the number of complex values; the array contains twice this number of - * real values. - */ - -/** - * @defgroup groupFilters Filtering Functions - */ - -/** - * @defgroup groupMatrix Matrix Functions - * - * This set of functions provides basic matrix math operations. - * The functions operate on matrix data structures. For example, - * the type - * definition for the floating-point matrix structure is shown - * below: - * 
    - *     typedef struct
- *     {
- *       uint16_t numRows;     // number of rows of the matrix.
- *       uint16_t numCols;     // number of columns of the matrix.
- *       float32_t *pData;     // points to the data of the matrix.
- *     } arm_matrix_instance_f32;
- *
    - * There are similar definitions for Q15 and Q31 data types. - * - * The structure specifies the size of the matrix and then points to - * an array of data. The array is of size numRows X numCols - * and the values are arranged in row order. That is, the - * matrix element (i, j) is stored at: - * 
    - *     pData[i*numCols + j]
- *
    - * - * \par Init Functions - * There is an associated initialization function for each type of matrix - * data structure. - * The initialization function sets the values of the internal structure fields. - * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() - * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. - * - * \par - * Use of the initialization function is optional. However, if initialization function is used - * then the instance structure cannot be placed into a const data section. - * To place the instance structure in a const data - * section, manually initialize the data structure. For example: - * 
    - * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
- * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
- *
    - * where nRows specifies the number of rows, nColumns - * specifies the number of columns, and pData points to the - * data array. - * - * \par Size Checking - * By default all of the matrix functions perform size checking on the input and - * output matrices. For example, the matrix addition function verifies that the - * two input matrices and the output matrix all have the same number of rows and - * columns. If the size check fails the functions return: - * 
    - *     ARM_MATH_SIZE_MISMATCH
- *
    - * Otherwise the functions return - * 
    - *     ARM_MATH_SUCCESS
- *
    - * There is some overhead associated with this matrix size checking. - * The matrix size checking is enabled via the \#define - * 
    - *     ARM_MATH_MATRIX_CHECK
- *
    - * within the library project settings. By default this macro is defined - * and size checking is enabled. By changing the project settings and - * undefining this macro size checking is eliminated and the functions - * run a bit faster. With size checking disabled the functions always - * return ARM_MATH_SUCCESS. - */ - -/** - * @defgroup groupTransforms Transform Functions - */ - -/** - * @defgroup groupController Controller Functions - */ - -/** - * @defgroup groupStats Statistics Functions - */ -/** - * @defgroup groupSupport Support Functions - */ - -/** - * @defgroup groupInterpolation Interpolation Functions - * These functions perform 1- and 2-dimensional interpolation of data. - * Linear interpolation is used for 1-dimensional data and - * bilinear interpolation is used for 2-dimensional data. - */ - -/** - * @defgroup groupExamples Examples - */ -#ifndef _ARM_MATH_H -#define _ARM_MATH_H - -#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ - -#if defined (ARM_MATH_CM4) -#include "core_cm4.h" -#elif defined (ARM_MATH_CM3) -#include "core_cm3.h" -#elif defined (ARM_MATH_CM0) -#include "core_cm0.h" -#define ARM_MATH_CM0_FAMILY -#elif defined (ARM_MATH_CM0PLUS) -#include "core_cm0plus.h" -#define ARM_MATH_CM0_FAMILY -#else -#include "ARMCM4.h" -#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." -#endif - -#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ -#include "string.h" -#include "math.h" -#ifdef __cplusplus -extern "C" -{ -#endif - - - /** - * @brief Macros required for reciprocal calculation in Normalized LMS - */ - -#define DELTA_Q31 (0x100) -#define DELTA_Q15 0x5 -#define INDEX_MASK 0x0000003F -#ifndef PI -#define PI 3.14159265358979f -#endif - - /** - * @brief Macros required for SINE and COSINE Fast math approximations - */ - -#define FAST_MATH_TABLE_SIZE 512 -#define FAST_MATH_Q31_SHIFT (32 - 10) -#define FAST_MATH_Q15_SHIFT (16 - 10) -#define CONTROLLER_Q31_SHIFT (32 - 9) -#define TABLE_SIZE 256 -#define TABLE_SPACING_Q31 0x400000 -#define TABLE_SPACING_Q15 0x80 - - /** - * @brief Macros required for SINE and COSINE Controller functions - */ - /* 1.31(q31) Fixed value of 2/360 */ - /* -1 to +1 is divided into 360 values so total spacing is (2/360) */ -#define INPUT_SPACING 0xB60B61 - - /** - * @brief Macro for Unaligned Support - */ -#ifndef UNALIGNED_SUPPORT_DISABLE - #define ALIGN4 -#else - #if defined (__GNUC__) - #define ALIGN4 __attribute__((aligned(4))) - #else - #define ALIGN4 __align(4) - #endif -#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ - - /** - * @brief Error status returned by some functions in the library. - */ - - typedef enum - { - ARM_MATH_SUCCESS = 0, /**< No error */ - ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ - ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ - ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ - ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ - ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ - ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ - } arm_status; - - /** - * @brief 8-bit fractional data type in 1.7 format. - */ - typedef int8_t q7_t; - - /** - * @brief 16-bit fractional data type in 1.15 format. - */ - typedef int16_t q15_t; - - /** - * @brief 32-bit fractional data type in 1.31 format. - */ - typedef int32_t q31_t; - - /** - * @brief 64-bit fractional data type in 1.63 format. - */ - typedef int64_t q63_t; - - /** - * @brief 32-bit floating-point type definition. - */ - typedef float float32_t; - - /** - * @brief 64-bit floating-point type definition. - */ - typedef double float64_t; - - /** - * @brief definition to read/write two 16 bit values. - */ -#if defined __CC_ARM -#define __SIMD32_TYPE int32_t __packed -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __ICCARM__ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t __packed -#elif defined __GNUC__ -#define __SIMD32_TYPE int32_t -#define CMSIS_UNUSED __attribute__((unused)) -#elif defined __CSMC__ /* Cosmic */ -#define CMSIS_UNUSED -#define __SIMD32_TYPE int32_t -#else -#error Unknown compiler -#endif - -#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr)) -#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) - -#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr)) - -#define __SIMD64(addr) (*(int64_t **) & (addr)) - -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - /** - * @brief definition to pack two 16 bit values. - */ -#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ - (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) ) -#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ - (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) ) - -#endif - - - /** - * @brief definition to pack four 8 bit values. - */ -#ifndef ARM_MATH_BIG_ENDIAN - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v3) << 24) & (int32_t)0xFF000000) ) -#else - -#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \ - (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ - (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ - (((int32_t)(v0) << 24) & (int32_t)0xFF000000) ) - -#endif - - - /** - * @brief Clips Q63 to Q31 values. - */ - static __INLINE q31_t clip_q63_to_q31( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x; - } - - /** - * @brief Clips Q63 to Q15 values. - */ - static __INLINE q15_t clip_q63_to_q15( - q63_t x) - { - return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ? - ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15); - } - - /** - * @brief Clips Q31 to Q7 values. - */ - static __INLINE q7_t clip_q31_to_q7( - q31_t x) - { - return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ? - ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x; - } - - /** - * @brief Clips Q31 to Q15 values. - */ - static __INLINE q15_t clip_q31_to_q15( - q31_t x) - { - return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ? - ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x; - } - - /** - * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. - */ - - static __INLINE q63_t mult32x64( - q63_t x, - q31_t y) - { - return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) + - (((q63_t) (x >> 32) * y))); - } - - -#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM ) -#define __CLZ __clz -#endif - -#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) ) - - static __INLINE uint32_t __CLZ( - q31_t data); - - - static __INLINE uint32_t __CLZ( - q31_t data) - { - uint32_t count = 0; - uint32_t mask = 0x80000000; - - while((data & mask) == 0) - { - count += 1u; - mask = mask >> 1u; - } - - return (count); - - } - -#endif - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. - */ - - static __INLINE uint32_t arm_recip_q31( - q31_t in, - q31_t * dst, - q31_t * pRecipTable) - { - - uint32_t out, tempVal; - uint32_t index, i; - uint32_t signBits; - - if(in > 0) - { - signBits = __CLZ(in) - 1; - } - else - { - signBits = __CLZ(-in) - 1; - } - - /* Convert input sample to 1.31 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = (uint32_t) (in >> 24u); - index = (index & INDEX_MASK); - - /* 1.31 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0u; i < 2u; i++) - { - tempVal = (q31_t) (((q63_t) in * out) >> 31u); - tempVal = 0x7FFFFFFF - tempVal; - /* 1.31 with exp 1 */ - //out = (q31_t) (((q63_t) out * tempVal) >> 30u); - out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1u); - - } - - /** - * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. - */ - static __INLINE uint32_t arm_recip_q15( - q15_t in, - q15_t * dst, - q15_t * pRecipTable) - { - - uint32_t out = 0, tempVal = 0; - uint32_t index = 0, i = 0; - uint32_t signBits = 0; - - if(in > 0) - { - signBits = __CLZ(in) - 17; - } - else - { - signBits = __CLZ(-in) - 17; - } - - /* Convert input sample to 1.15 format */ - in = in << signBits; - - /* calculation of index for initial approximated Val */ - index = in >> 8; - index = (index & INDEX_MASK); - - /* 1.15 with exp 1 */ - out = pRecipTable[index]; - - /* calculation of reciprocal value */ - /* running approximation for two iterations */ - for (i = 0; i < 2; i++) - { - tempVal = (q15_t) (((q31_t) in * out) >> 15); - tempVal = 0x7FFF - tempVal; - /* 1.15 with exp 1 */ - out = (q15_t) (((q31_t) out * tempVal) >> 14); - } - - /* write output */ - *dst = out; - - /* return num of signbits of out = 1/in value */ - return (signBits + 1); - - } - - - /* - * @brief C custom defined intrinisic function for only M0 processors - */ -#if defined(ARM_MATH_CM0_FAMILY) - - static __INLINE q31_t __SSAT( - q31_t x, - uint32_t y) - { - int32_t posMax, negMin; - uint32_t i; - - posMax = 1; - for (i = 0; i < (y - 1); i++) - { - posMax = posMax * 2; - } - - if(x > 0) - { - posMax = (posMax - 1); - - if(x > posMax) - { - x = posMax; - } - } - else - { - negMin = -posMax; - - if(x < negMin) - { - x = negMin; - } - } - return (x); - - - } - -#endif /* end of ARM_MATH_CM0_FAMILY */ - - - - /* - * @brief C custom defined intrinsic function for M3 and M0 processors - */ -#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) - - /* - * @brief C custom defined QADD8 for M3 and M0 processors - */ - static __INLINE q31_t __QADD8( - q31_t x, - q31_t y) - { - - q31_t sum; - q7_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((q31_t) (r + s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8); - t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8); - u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8); - - sum = - (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) | - (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF); - - return sum; - - } - - /* - * @brief C custom defined QSUB8 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB8( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s, t, u; - - r = (q7_t) x; - s = (q7_t) y; - - r = __SSAT((r - s), 8); - s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; - t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; - u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24; - - sum = - (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & - 0x000000FF); - - return sum; - } - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - - /* - * @brief C custom defined QADD16 for M3 and M0 processors - */ - static __INLINE q31_t __QADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r + s, 16); - s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined SHADD16 for M3 and M0 processors - */ - static __INLINE q31_t __SHADD16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (s >> 1)); - s = ((q31_t) ((x >> 17) + (y >> 17))) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - - } - - /* - * @brief C custom defined QSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __QSUB16( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = __SSAT(r - s, 16); - s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16; - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SHSUB16 for M3 and M0 processors - */ - static __INLINE q31_t __SHSUB16( - q31_t x, - q31_t y) - { - - q31_t diff; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (s >> 1)); - s = (((x >> 17) - (y >> 17)) << 16); - - diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return diff; - } - - /* - * @brief C custom defined QASX for M3 and M0 processors - */ - static __INLINE q31_t __QASX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) + (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x - (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHASX for M3 and M0 processors - */ - static __INLINE q31_t __SHASX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) - (y >> 17)); - s = (((x >> 17) + (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - - /* - * @brief C custom defined QSAX for M3 and M0 processors - */ - static __INLINE q31_t __QSAX( - q31_t x, - q31_t y) - { - - q31_t sum = 0; - - sum = - ((sum + - clip_q31_to_q15((q31_t) ((q15_t) (x >> 16) - (q15_t) y))) << 16) + - clip_q31_to_q15((q31_t) ((q15_t) x + (q15_t) (y >> 16))); - - return sum; - } - - /* - * @brief C custom defined SHSAX for M3 and M0 processors - */ - static __INLINE q31_t __SHSAX( - q31_t x, - q31_t y) - { - - q31_t sum; - q31_t r, s; - - r = (q15_t) x; - s = (q15_t) y; - - r = ((r >> 1) + (y >> 17)); - s = (((x >> 17) - (s >> 1)) << 16); - - sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); - - return sum; - } - - /* - * @brief C custom defined SMUSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMUSDX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) - - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined SMUADX for M3 and M0 processors - */ - static __INLINE q31_t __SMUADX( - q31_t x, - q31_t y) - { - - return ((q31_t) (((q15_t) x * (q15_t) (y >> 16)) + - ((q15_t) (x >> 16) * (q15_t) y))); - } - - /* - * @brief C custom defined QADD for M3 and M0 processors - */ - static __INLINE q31_t __QADD( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x + y); - } - - /* - * @brief C custom defined QSUB for M3 and M0 processors - */ - static __INLINE q31_t __QSUB( - q31_t x, - q31_t y) - { - return clip_q63_to_q31((q63_t) x - y); - } - - /* - * @brief C custom defined SMLAD for M3 and M0 processors - */ - static __INLINE q31_t __SMLAD( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLADX for M3 and M0 processors - */ - static __INLINE q31_t __SMLADX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLSDX for M3 and M0 processors - */ - static __INLINE q31_t __SMLSDX( - q31_t x, - q31_t y, - q31_t sum) - { - - return (sum - ((q15_t) (x >> 16) * (q15_t) (y)) + - ((q15_t) x * (q15_t) (y >> 16))); - } - - /* - * @brief C custom defined SMLALD for M3 and M0 processors - */ - static __INLINE q63_t __SMLALD( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) (y >> 16)) + - ((q15_t) x * (q15_t) y)); - } - - /* - * @brief C custom defined SMLALDX for M3 and M0 processors - */ - static __INLINE q63_t __SMLALDX( - q31_t x, - q31_t y, - q63_t sum) - { - - return (sum + ((q15_t) (x >> 16) * (q15_t) y)) + - ((q15_t) x * (q15_t) (y >> 16)); - } - - /* - * @brief C custom defined SMUAD for M3 and M0 processors - */ - static __INLINE q31_t __SMUAD( - q31_t x, - q31_t y) - { - - return (((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - /* - * @brief C custom defined SMUSD for M3 and M0 processors - */ - static __INLINE q31_t __SMUSD( - q31_t x, - q31_t y) - { - - return (-((x >> 16) * (y >> 16)) + - (((x << 16) >> 16) * ((y << 16) >> 16))); - } - - - /* - * @brief C custom defined SXTB16 for M3 and M0 processors - */ - static __INLINE q31_t __SXTB16( - q31_t x) - { - - return ((((x << 24) >> 24) & 0x0000FFFF) | - (((x << 8) >> 8) & 0xFFFF0000)); - } - - -#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ - - - /** - * @brief Instance structure for the Q7 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q7; - - /** - * @brief Instance structure for the Q15 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - } arm_fir_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of filter coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - } arm_fir_instance_f32; - - - /** - * @brief Processing function for the Q7 FIR filter. - * @param[in] *S points to an instance of the Q7 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q7( - const arm_fir_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q7 FIR filter. - * @param[in,out] *S points to an instance of the Q7 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed. - * @return none - */ - void arm_fir_init_q7( - arm_fir_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 FIR filter. - * @param[in] *S points to an instance of the Q15 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q15( - const arm_fir_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 FIR filter. - * @param[in,out] *S points to an instance of the Q15 FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if - * numTaps is not a supported value. - */ - - arm_status arm_fir_init_q15( - arm_fir_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR filter. - * @param[in] *S points to an instance of the Q31 FIR filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_fast_q31( - const arm_fir_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR filter. - * @param[in,out] *S points to an instance of the Q31 FIR structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_q31( - arm_fir_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the floating-point FIR filter. - * @param[in] *S points to an instance of the floating-point FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_f32( - const arm_fir_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR filter. - * @param[in,out] *S points to an instance of the floating-point FIR filter structure. - * @param[in] numTaps Number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of samples that are processed at a time. - * @return none. - */ - void arm_fir_init_f32( - arm_fir_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q15 Biquad cascade filter. - */ - typedef struct - { - int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q15; - - - /** - * @brief Instance structure for the Q31 Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ - - } arm_biquad_casd_df1_inst_q31; - - /** - * @brief Instance structure for the floating-point Biquad cascade filter. - */ - typedef struct - { - uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ - float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ - - - } arm_biquad_casd_df1_inst_f32; - - - - /** - * @brief Processing function for the Q15 Biquad cascade filter. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q15 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q15( - arm_biquad_casd_df1_inst_q15 * S, - uint8_t numStages, - q15_t * pCoeffs, - q15_t * pState, - int8_t postShift); - - - /** - * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q15( - const arm_biquad_casd_df1_inst_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 Biquad cascade filter - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_fast_q31( - const arm_biquad_casd_df1_inst_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 Biquad cascade filter. - * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cascade_df1_init_q31( - arm_biquad_casd_df1_inst_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q31_t * pState, - int8_t postShift); - - /** - * @brief Processing function for the floating-point Biquad cascade filter. - * @param[in] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df1_f32( - const arm_biquad_casd_df1_inst_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point Biquad cascade filter. - * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df1_init_f32( - arm_biquad_casd_df1_inst_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - /** - * @brief Instance structure for the floating-point matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - float32_t *pData; /**< points to the data of the matrix. */ - } arm_matrix_instance_f32; - - /** - * @brief Instance structure for the Q15 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q15_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q15; - - /** - * @brief Instance structure for the Q31 matrix structure. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows of the matrix. */ - uint16_t numCols; /**< number of columns of the matrix. */ - q31_t *pData; /**< points to the data of the matrix. */ - - } arm_matrix_instance_q31; - - - - /** - * @brief Floating-point matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix addition. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_add_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pScratch); - - /** - * @brief Q31, complex, matrix multiplication. - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_cmplx_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_f32( - const arm_matrix_instance_f32 * pSrc, - arm_matrix_instance_f32 * pDst); - - - /** - * @brief Q15 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q15( - const arm_matrix_instance_q15 * pSrc, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix transpose. - * @param[in] *pSrc points to the input matrix - * @param[out] *pDst points to the output matrix - * @return The function returns either ARM_MATH_SIZE_MISMATCH - * or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_trans_q31( - const arm_matrix_instance_q31 * pSrc, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @param[in] *pState points to the array for storing intermediate results - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst, - q15_t * pState); - - /** - * @brief Q31 matrix multiplication - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_mult_fast_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Floating-point matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_f32( - const arm_matrix_instance_f32 * pSrcA, - const arm_matrix_instance_f32 * pSrcB, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q15( - const arm_matrix_instance_q15 * pSrcA, - const arm_matrix_instance_q15 * pSrcB, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix subtraction - * @param[in] *pSrcA points to the first input matrix structure - * @param[in] *pSrcB points to the second input matrix structure - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_sub_q31( - const arm_matrix_instance_q31 * pSrcA, - const arm_matrix_instance_q31 * pSrcB, - arm_matrix_instance_q31 * pDst); - - /** - * @brief Floating-point matrix scaling. - * @param[in] *pSrc points to the input matrix - * @param[in] scale scale factor - * @param[out] *pDst points to the output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_f32( - const arm_matrix_instance_f32 * pSrc, - float32_t scale, - arm_matrix_instance_f32 * pDst); - - /** - * @brief Q15 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q15( - const arm_matrix_instance_q15 * pSrc, - q15_t scaleFract, - int32_t shift, - arm_matrix_instance_q15 * pDst); - - /** - * @brief Q31 matrix scaling. - * @param[in] *pSrc points to input matrix - * @param[in] scaleFract fractional portion of the scale factor - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to output matrix structure - * @return The function returns either - * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. - */ - - arm_status arm_mat_scale_q31( - const arm_matrix_instance_q31 * pSrc, - q31_t scaleFract, - int32_t shift, - arm_matrix_instance_q31 * pDst); - - - /** - * @brief Q31 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q31( - arm_matrix_instance_q31 * S, - uint16_t nRows, - uint16_t nColumns, - q31_t * pData); - - /** - * @brief Q15 matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_q15( - arm_matrix_instance_q15 * S, - uint16_t nRows, - uint16_t nColumns, - q15_t * pData); - - /** - * @brief Floating-point matrix initialization. - * @param[in,out] *S points to an instance of the floating-point matrix structure. - * @param[in] nRows number of rows in the matrix. - * @param[in] nColumns number of columns in the matrix. - * @param[in] *pData points to the matrix data array. - * @return none - */ - - void arm_mat_init_f32( - arm_matrix_instance_f32 * S, - uint16_t nRows, - uint16_t nColumns, - float32_t * pData); - - - - /** - * @brief Instance structure for the Q15 PID Control. - */ - typedef struct - { - q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ -#ifdef ARM_MATH_CM0_FAMILY - q15_t A1; - q15_t A2; -#else - q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ -#endif - q15_t state[3]; /**< The state array of length 3. */ - q15_t Kp; /**< The proportional gain. */ - q15_t Ki; /**< The integral gain. */ - q15_t Kd; /**< The derivative gain. */ - } arm_pid_instance_q15; - - /** - * @brief Instance structure for the Q31 PID Control. - */ - typedef struct - { - q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - q31_t A2; /**< The derived gain, A2 = Kd . */ - q31_t state[3]; /**< The state array of length 3. */ - q31_t Kp; /**< The proportional gain. */ - q31_t Ki; /**< The integral gain. */ - q31_t Kd; /**< The derivative gain. */ - - } arm_pid_instance_q31; - - /** - * @brief Instance structure for the floating-point PID Control. - */ - typedef struct - { - float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ - float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ - float32_t A2; /**< The derived gain, A2 = Kd . */ - float32_t state[3]; /**< The state array of length 3. */ - float32_t Kp; /**< The proportional gain. */ - float32_t Ki; /**< The integral gain. */ - float32_t Kd; /**< The derivative gain. */ - } arm_pid_instance_f32; - - - - /** - * @brief Initialization function for the floating-point PID Control. - * @param[in,out] *S points to an instance of the PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_f32( - arm_pid_instance_f32 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @return none - */ - void arm_pid_reset_f32( - arm_pid_instance_f32 * S); - - - /** - * @brief Initialization function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q31( - arm_pid_instance_q31 * S, - int32_t resetStateFlag); - - - /** - * @brief Reset function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @return none - */ - - void arm_pid_reset_q31( - arm_pid_instance_q31 * S); - - /** - * @brief Initialization function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID structure. - * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. - * @return none. - */ - void arm_pid_init_q15( - arm_pid_instance_q15 * S, - int32_t resetStateFlag); - - /** - * @brief Reset function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the q15 PID Control structure - * @return none - */ - void arm_pid_reset_q15( - arm_pid_instance_q15 * S); - - - /** - * @brief Instance structure for the floating-point Linear Interpolate function. - */ - typedef struct - { - uint32_t nValues; /**< nValues */ - float32_t x1; /**< x1 */ - float32_t xSpacing; /**< xSpacing */ - float32_t *pYData; /**< pointer to the table of Y values */ - } arm_linear_interp_instance_f32; - - /** - * @brief Instance structure for the floating-point bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - float32_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_f32; - - /** - * @brief Instance structure for the Q31 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q31_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q31; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q15_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q15; - - /** - * @brief Instance structure for the Q15 bilinear interpolation function. - */ - - typedef struct - { - uint16_t numRows; /**< number of rows in the data table. */ - uint16_t numCols; /**< number of columns in the data table. */ - q7_t *pData; /**< points to the data table. */ - } arm_bilinear_interp_instance_q7; - - - /** - * @brief Q7 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector multiplication. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_mult_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - - - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q15; - - arm_status arm_cfft_radix2_init_q15( - arm_cfft_radix2_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q15( - const arm_cfft_radix2_instance_q15 * S, - q15_t * pSrc); - - - - /** - * @brief Instance structure for the Q15 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q15; - - arm_status arm_cfft_radix4_init_q15( - arm_cfft_radix4_instance_q15 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix4_q15( - const arm_cfft_radix4_instance_q15 * S, - q15_t * pSrc); - - /** - * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix2_instance_q31; - - arm_status arm_cfft_radix2_init_q31( - arm_cfft_radix2_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - void arm_cfft_radix2_q31( - const arm_cfft_radix2_instance_q31 * S, - q31_t * pSrc); - - /** - * @brief Instance structure for the Q31 CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - } arm_cfft_radix4_instance_q31; - - void arm_cfft_radix4_q31( - const arm_cfft_radix4_instance_q31 * S, - q31_t * pSrc); - - arm_status arm_cfft_radix4_init_q31( - arm_cfft_radix4_instance_q31 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix2_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix2_init_f32( - arm_cfft_radix2_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix2_f32( - const arm_cfft_radix2_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ - uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ - float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ - float32_t onebyfftLen; /**< value of 1/fftLen. */ - } arm_cfft_radix4_instance_f32; - -/* Deprecated */ - arm_status arm_cfft_radix4_init_f32( - arm_cfft_radix4_instance_f32 * S, - uint16_t fftLen, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - -/* Deprecated */ - void arm_cfft_radix4_f32( - const arm_cfft_radix4_instance_f32 * S, - float32_t * pSrc); - - /** - * @brief Instance structure for the floating-point CFFT/CIFFT function. - */ - - typedef struct - { - uint16_t fftLen; /**< length of the FFT. */ - const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ - const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ - uint16_t bitRevLength; /**< bit reversal table length. */ - } arm_cfft_instance_f32; - - void arm_cfft_f32( - const arm_cfft_instance_f32 * S, - float32_t * p1, - uint8_t ifftFlag, - uint8_t bitReverseFlag); - - /** - * @brief Instance structure for the Q15 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q15; - - arm_status arm_rfft_init_q15( - arm_rfft_instance_q15 * S, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q15( - const arm_rfft_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst); - - /** - * @brief Instance structure for the Q31 RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint32_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_q31; - - arm_status arm_rfft_init_q31( - arm_rfft_instance_q31 * S, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_q31( - const arm_rfft_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - - typedef struct - { - uint32_t fftLenReal; /**< length of the real FFT. */ - uint16_t fftLenBy2; /**< length of the complex FFT. */ - uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ - uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ - uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ - float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ - float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_rfft_instance_f32; - - arm_status arm_rfft_init_f32( - arm_rfft_instance_f32 * S, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint32_t fftLenReal, - uint32_t ifftFlagR, - uint32_t bitReverseFlag); - - void arm_rfft_f32( - const arm_rfft_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst); - - /** - * @brief Instance structure for the floating-point RFFT/RIFFT function. - */ - -typedef struct - { - arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ - uint16_t fftLenRFFT; /**< length of the real sequence */ - float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */ - } arm_rfft_fast_instance_f32 ; - -arm_status arm_rfft_fast_init_f32 ( - arm_rfft_fast_instance_f32 * S, - uint16_t fftLen); - -void arm_rfft_fast_f32( - arm_rfft_fast_instance_f32 * S, - float32_t * p, float32_t * pOut, - uint8_t ifftFlag); - - /** - * @brief Instance structure for the floating-point DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - float32_t normalize; /**< normalizing factor. */ - float32_t *pTwiddle; /**< points to the twiddle factor table. */ - float32_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_f32; - - /** - * @brief Initialization function for the floating-point DCT4/IDCT4. - * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. - */ - - arm_status arm_dct4_init_f32( - arm_dct4_instance_f32 * S, - arm_rfft_instance_f32 * S_RFFT, - arm_cfft_radix4_instance_f32 * S_CFFT, - uint16_t N, - uint16_t Nby2, - float32_t normalize); - - /** - * @brief Processing function for the floating-point DCT4/IDCT4. - * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_f32( - const arm_dct4_instance_f32 * S, - float32_t * pState, - float32_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q31 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q31_t normalize; /**< normalizing factor. */ - q31_t *pTwiddle; /**< points to the twiddle factor table. */ - q31_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q31; - - /** - * @brief Initialization function for the Q31 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure - * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q31( - arm_dct4_instance_q31 * S, - arm_rfft_instance_q31 * S_RFFT, - arm_cfft_radix4_instance_q31 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q31_t normalize); - - /** - * @brief Processing function for the Q31 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q31 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q31( - const arm_dct4_instance_q31 * S, - q31_t * pState, - q31_t * pInlineBuffer); - - /** - * @brief Instance structure for the Q15 DCT4/IDCT4 function. - */ - - typedef struct - { - uint16_t N; /**< length of the DCT4. */ - uint16_t Nby2; /**< half of the length of the DCT4. */ - q15_t normalize; /**< normalizing factor. */ - q15_t *pTwiddle; /**< points to the twiddle factor table. */ - q15_t *pCosFactor; /**< points to the cosFactor table. */ - arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ - arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ - } arm_dct4_instance_q15; - - /** - * @brief Initialization function for the Q15 DCT4/IDCT4. - * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. - * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. - * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. - * @param[in] N length of the DCT4. - * @param[in] Nby2 half of the length of the DCT4. - * @param[in] normalize normalizing factor. - * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. - */ - - arm_status arm_dct4_init_q15( - arm_dct4_instance_q15 * S, - arm_rfft_instance_q15 * S_RFFT, - arm_cfft_radix4_instance_q15 * S_CFFT, - uint16_t N, - uint16_t Nby2, - q15_t normalize); - - /** - * @brief Processing function for the Q15 DCT4/IDCT4. - * @param[in] *S points to an instance of the Q15 DCT4 structure. - * @param[in] *pState points to state buffer. - * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. - * @return none. - */ - - void arm_dct4_q15( - const arm_dct4_instance_q15 * S, - q15_t * pState, - q15_t * pInlineBuffer); - - /** - * @brief Floating-point vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector addition. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_add_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q7( - q7_t * pSrcA, - q7_t * pSrcB, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector subtraction. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_sub_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a floating-point vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scale scale factor to be applied - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_f32( - float32_t * pSrc, - float32_t scale, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q7 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q7( - q7_t * pSrc, - q7_t scaleFract, - int8_t shift, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q15 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q15( - q15_t * pSrc, - q15_t scaleFract, - int8_t shift, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Multiplies a Q31 vector by a scalar. - * @param[in] *pSrc points to the input vector - * @param[in] scaleFract fractional portion of the scale value - * @param[in] shift number of bits to shift the result by - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_scale_q31( - q31_t * pSrc, - q31_t scaleFract, - int8_t shift, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Q7 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Floating-point vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Q15 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Q31 vector absolute value. - * @param[in] *pSrc points to the input buffer - * @param[out] *pDst points to the output buffer - * @param[in] blockSize number of samples in each vector - * @return none. - */ - - void arm_abs_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Dot product of floating-point vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t blockSize, - float32_t * result); - - /** - * @brief Dot product of Q7 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q7( - q7_t * pSrcA, - q7_t * pSrcB, - uint32_t blockSize, - q31_t * result); - - /** - * @brief Dot product of Q15 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Dot product of Q31 vectors. - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] blockSize number of samples in each vector - * @param[out] *result output result returned here - * @return none. - */ - - void arm_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t blockSize, - q63_t * result); - - /** - * @brief Shifts the elements of a Q7 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q7( - q7_t * pSrc, - int8_t shiftBits, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q15 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q15( - q15_t * pSrc, - int8_t shiftBits, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Shifts the elements of a Q31 vector a specified number of bits. - * @param[in] *pSrc points to the input vector - * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_shift_q31( - q31_t * pSrc, - int8_t shiftBits, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_f32( - float32_t * pSrc, - float32_t offset, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q7( - q7_t * pSrc, - q7_t offset, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q15( - q15_t * pSrc, - q15_t offset, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Adds a constant offset to a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[in] offset is the offset to be added - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_offset_q31( - q31_t * pSrc, - q31_t offset, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a floating-point vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q7 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q15 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Negates the elements of a Q31 vector. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] blockSize number of samples in the vector - * @return none. - */ - - void arm_negate_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Copies the elements of a floating-point vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q7 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q7( - q7_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Copies the elements of a Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_copy_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - /** - * @brief Fills a constant value into a floating-point vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_f32( - float32_t value, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q7 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q7( - q7_t value, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q15 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q15( - q15_t value, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Fills a constant value into a Q31 vector. - * @param[in] value input value to be filled - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_fill_q31( - q31_t value, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - - void arm_conv_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_conv_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - - /** - * @brief Convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. - * @return none. - */ - - void arm_conv_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Partial convolution of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Partial convolution of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - /** - * @brief Partial convolution of Q7 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints, - q15_t * pScratch1, - q15_t * pScratch2); - - -/** - * @brief Partial convolution of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data - * @param[in] firstIndex is the first output sample to start with. - * @param[in] numPoints is the number of output points to be computed. - * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. - */ - - arm_status arm_conv_partial_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - uint32_t firstIndex, - uint32_t numPoints); - - - - /** - * @brief Instance structure for the Q15 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - } arm_fir_decimate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR decimator. - */ - - typedef struct - { - uint8_t M; /**< decimation factor. */ - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - - } arm_fir_decimate_instance_f32; - - - - /** - * @brief Processing function for the floating-point FIR decimator. - * @param[in] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_f32( - const arm_fir_decimate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point FIR decimator. - * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_f32( - arm_fir_decimate_instance_f32 * S, - uint16_t numTaps, - uint8_t M, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q15( - const arm_fir_decimate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @brief Initialization function for the Q15 FIR decimator. - * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q15( - arm_fir_decimate_instance_q15 * S, - uint16_t numTaps, - uint8_t M, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_q31( - const arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. - * @param[in] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of input samples to process per call. - * @return none - */ - - void arm_fir_decimate_fast_q31( - arm_fir_decimate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 FIR decimator. - * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. - * @param[in] numTaps number of coefficients in the filter. - * @param[in] M decimation factor. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * blockSize is not a multiple of M. - */ - - arm_status arm_fir_decimate_init_q31( - arm_fir_decimate_instance_q31 * S, - uint16_t numTaps, - uint8_t M, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - - /** - * @brief Instance structure for the Q15 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ - } arm_fir_interpolate_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR interpolator. - */ - - typedef struct - { - uint8_t L; /**< upsample factor. */ - uint16_t phaseLength; /**< length of each polyphase filter component. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ - float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ - } arm_fir_interpolate_instance_f32; - - - /** - * @brief Processing function for the Q15 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q15( - const arm_fir_interpolate_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 FIR interpolator. - * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q15( - arm_fir_interpolate_instance_q15 * S, - uint8_t L, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 FIR interpolator. - * @param[in] *S points to an instance of the Q15 FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_q31( - const arm_fir_interpolate_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR interpolator. - * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_q31( - arm_fir_interpolate_instance_q31 * S, - uint8_t L, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the floating-point FIR interpolator. - * @param[in] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_interpolate_f32( - const arm_fir_interpolate_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point FIR interpolator. - * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. - * @param[in] L upsample factor. - * @param[in] numTaps number of filter coefficients in the filter. - * @param[in] *pCoeffs points to the filter coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] blockSize number of input samples to process per call. - * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if - * the filter length numTaps is not a multiple of the interpolation factor L. - */ - - arm_status arm_fir_interpolate_init_f32( - arm_fir_interpolate_instance_f32 * S, - uint8_t L, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the high precision Q31 Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ - q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ - - } arm_biquad_cas_df1_32x64_ins_q31; - - - /** - * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cas_df1_32x64_q31( - const arm_biquad_cas_df1_32x64_ins_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format - * @return none - */ - - void arm_biquad_cas_df1_32x64_init_q31( - arm_biquad_cas_df1_32x64_ins_q31 * S, - uint8_t numStages, - q31_t * pCoeffs, - q63_t * pState, - uint8_t postShift); - - - - /** - * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. - */ - - typedef struct - { - uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ - float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ - float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ - } arm_biquad_cascade_df2T_instance_f32; - - - /** - * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in] *S points to an instance of the filter data structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_biquad_cascade_df2T_f32( - const arm_biquad_cascade_df2T_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. - * @param[in,out] *S points to an instance of the filter data structure. - * @param[in] numStages number of 2nd order stages in the filter. - * @param[in] *pCoeffs points to the filter coefficients. - * @param[in] *pState points to the state buffer. - * @return none - */ - - void arm_biquad_cascade_df2T_init_f32( - arm_biquad_cascade_df2T_instance_f32 * S, - uint8_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - - - /** - * @brief Instance structure for the Q15 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point FIR lattice filter. - */ - - typedef struct - { - uint16_t numStages; /**< number of filter stages. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ - } arm_fir_lattice_instance_f32; - - /** - * @brief Initialization function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q15( - arm_fir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pCoeffs, - q15_t * pState); - - - /** - * @brief Processing function for the Q15 FIR lattice filter. - * @param[in] *S points to an instance of the Q15 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - void arm_fir_lattice_q15( - const arm_fir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_q31( - arm_fir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pCoeffs, - q31_t * pState); - - - /** - * @brief Processing function for the Q31 FIR lattice filter. - * @param[in] *S points to an instance of the Q31 FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_q31( - const arm_fir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - -/** - * @brief Initialization function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] numStages number of filter stages. - * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. - * @param[in] *pState points to the state buffer. The array is of length numStages. - * @return none. - */ - - void arm_fir_lattice_init_f32( - arm_fir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pCoeffs, - float32_t * pState); - - /** - * @brief Processing function for the floating-point FIR lattice filter. - * @param[in] *S points to an instance of the floating-point FIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_fir_lattice_f32( - const arm_fir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q15; - - /** - * @brief Instance structure for the Q31 IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_q31; - - /** - * @brief Instance structure for the floating-point IIR lattice filter. - */ - typedef struct - { - uint16_t numStages; /**< number of stages in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ - float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ - float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ - } arm_iir_lattice_instance_f32; - - /** - * @brief Processing function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_f32( - const arm_iir_lattice_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point IIR lattice filter. - * @param[in] *S points to an instance of the floating-point IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_f32( - arm_iir_lattice_instance_f32 * S, - uint16_t numStages, - float32_t * pkCoeffs, - float32_t * pvCoeffs, - float32_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q31( - const arm_iir_lattice_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q31 IIR lattice filter. - * @param[in] *S points to an instance of the Q31 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_init_q31( - arm_iir_lattice_instance_q31 * S, - uint16_t numStages, - q31_t * pkCoeffs, - q31_t * pvCoeffs, - q31_t * pState, - uint32_t blockSize); - - - /** - * @brief Processing function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the Q15 IIR lattice structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_iir_lattice_q15( - const arm_iir_lattice_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - -/** - * @brief Initialization function for the Q15 IIR lattice filter. - * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. - * @param[in] numStages number of stages in the filter. - * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. - * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. - * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. - * @param[in] blockSize number of samples to process per call. - * @return none. - */ - - void arm_iir_lattice_init_q15( - arm_iir_lattice_instance_q15 * S, - uint16_t numStages, - q15_t * pkCoeffs, - q15_t * pvCoeffs, - q15_t * pState, - uint32_t blockSize); - - /** - * @brief Instance structure for the floating-point LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that controls filter coefficient updates. */ - } arm_lms_instance_f32; - - /** - * @brief Processing function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_f32( - const arm_lms_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_init_f32( - arm_lms_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - /** - * @brief Instance structure for the Q15 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - } arm_lms_instance_q15; - - - /** - * @brief Initialization function for the Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to the coefficient buffer. - * @param[in] *pState points to the state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q15( - arm_lms_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Processing function for Q15 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q15( - const arm_lms_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint32_t postShift; /**< bit shift applied to coefficients. */ - - } arm_lms_instance_q31; - - /** - * @brief Processing function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q15 LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_q31( - const arm_lms_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 LMS filter. - * @param[in] *S points to an instance of the Q31 LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_init_q31( - arm_lms_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint32_t postShift); - - /** - * @brief Instance structure for the floating-point normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - float32_t mu; /**< step size that control filter coefficient updates. */ - float32_t energy; /**< saves previous frame energy. */ - float32_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_f32; - - /** - * @brief Processing function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_f32( - arm_lms_norm_instance_f32 * S, - float32_t * pSrc, - float32_t * pRef, - float32_t * pOut, - float32_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for floating-point normalized LMS filter. - * @param[in] *S points to an instance of the floating-point LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_init_f32( - arm_lms_norm_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - float32_t mu, - uint32_t blockSize); - - - /** - * @brief Instance structure for the Q31 normalized LMS filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q31_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q31_t *recipTable; /**< points to the reciprocal initial value table. */ - q31_t energy; /**< saves previous frame energy. */ - q31_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q31; - - /** - * @brief Processing function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q31( - arm_lms_norm_instance_q31 * S, - q31_t * pSrc, - q31_t * pRef, - q31_t * pOut, - q31_t * pErr, - uint32_t blockSize); - - /** - * @brief Initialization function for Q31 normalized LMS filter. - * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q31( - arm_lms_norm_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - q31_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Instance structure for the Q15 normalized LMS filter. - */ - - typedef struct - { - uint16_t numTaps; /**< Number of coefficients in the filter. */ - q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ - q15_t mu; /**< step size that controls filter coefficient updates. */ - uint8_t postShift; /**< bit shift applied to coefficients. */ - q15_t *recipTable; /**< Points to the reciprocal initial value table. */ - q15_t energy; /**< saves previous frame energy. */ - q15_t x0; /**< saves previous input sample. */ - } arm_lms_norm_instance_q15; - - /** - * @brief Processing function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] *pSrc points to the block of input data. - * @param[in] *pRef points to the block of reference data. - * @param[out] *pOut points to the block of output data. - * @param[out] *pErr points to the block of error data. - * @param[in] blockSize number of samples to process. - * @return none. - */ - - void arm_lms_norm_q15( - arm_lms_norm_instance_q15 * S, - q15_t * pSrc, - q15_t * pRef, - q15_t * pOut, - q15_t * pErr, - uint32_t blockSize); - - - /** - * @brief Initialization function for Q15 normalized LMS filter. - * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. - * @param[in] numTaps number of filter coefficients. - * @param[in] *pCoeffs points to coefficient buffer. - * @param[in] *pState points to state buffer. - * @param[in] mu step size that controls filter coefficient updates. - * @param[in] blockSize number of samples to process. - * @param[in] postShift bit shift applied to coefficients. - * @return none. - */ - - void arm_lms_norm_init_q15( - arm_lms_norm_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - q15_t mu, - uint32_t blockSize, - uint8_t postShift); - - /** - * @brief Correlation of floating-point sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_f32( - float32_t * pSrcA, - uint32_t srcALen, - float32_t * pSrcB, - uint32_t srcBLen, - float32_t * pDst); - - - /** - * @brief Correlation of Q15 sequences - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - void arm_correlate_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - - /** - * @brief Correlation of Q15 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst); - - - - /** - * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @return none. - */ - - void arm_correlate_fast_opt_q15( - q15_t * pSrcA, - uint32_t srcALen, - q15_t * pSrcB, - uint32_t srcBLen, - q15_t * pDst, - q15_t * pScratch); - - /** - * @brief Correlation of Q31 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - /** - * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_fast_q31( - q31_t * pSrcA, - uint32_t srcALen, - q31_t * pSrcB, - uint32_t srcBLen, - q31_t * pDst); - - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. - * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). - * @return none. - */ - - void arm_correlate_opt_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst, - q15_t * pScratch1, - q15_t * pScratch2); - - - /** - * @brief Correlation of Q7 sequences. - * @param[in] *pSrcA points to the first input sequence. - * @param[in] srcALen length of the first input sequence. - * @param[in] *pSrcB points to the second input sequence. - * @param[in] srcBLen length of the second input sequence. - * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. - * @return none. - */ - - void arm_correlate_q7( - q7_t * pSrcA, - uint32_t srcALen, - q7_t * pSrcB, - uint32_t srcBLen, - q7_t * pDst); - - - /** - * @brief Instance structure for the floating-point sparse FIR filter. - */ - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_f32; - - /** - * @brief Instance structure for the Q31 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q31; - - /** - * @brief Instance structure for the Q15 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q15; - - /** - * @brief Instance structure for the Q7 sparse FIR filter. - */ - - typedef struct - { - uint16_t numTaps; /**< number of coefficients in the filter. */ - uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ - q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ - q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ - uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ - int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ - } arm_fir_sparse_instance_q7; - - /** - * @brief Processing function for the floating-point sparse FIR filter. - * @param[in] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_f32( - arm_fir_sparse_instance_f32 * S, - float32_t * pSrc, - float32_t * pDst, - float32_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the floating-point sparse FIR filter. - * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_f32( - arm_fir_sparse_instance_f32 * S, - uint16_t numTaps, - float32_t * pCoeffs, - float32_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q31 sparse FIR filter. - * @param[in] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q31( - arm_fir_sparse_instance_q31 * S, - q31_t * pSrc, - q31_t * pDst, - q31_t * pScratchIn, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q31 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q31( - arm_fir_sparse_instance_q31 * S, - uint16_t numTaps, - q31_t * pCoeffs, - q31_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q15 sparse FIR filter. - * @param[in] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q15( - arm_fir_sparse_instance_q15 * S, - q15_t * pSrc, - q15_t * pDst, - q15_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - - /** - * @brief Initialization function for the Q15 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q15( - arm_fir_sparse_instance_q15 * S, - uint16_t numTaps, - q15_t * pCoeffs, - q15_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - /** - * @brief Processing function for the Q7 sparse FIR filter. - * @param[in] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] *pSrc points to the block of input data. - * @param[out] *pDst points to the block of output data - * @param[in] *pScratchIn points to a temporary buffer of size blockSize. - * @param[in] *pScratchOut points to a temporary buffer of size blockSize. - * @param[in] blockSize number of input samples to process per call. - * @return none. - */ - - void arm_fir_sparse_q7( - arm_fir_sparse_instance_q7 * S, - q7_t * pSrc, - q7_t * pDst, - q7_t * pScratchIn, - q31_t * pScratchOut, - uint32_t blockSize); - - /** - * @brief Initialization function for the Q7 sparse FIR filter. - * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. - * @param[in] numTaps number of nonzero coefficients in the filter. - * @param[in] *pCoeffs points to the array of filter coefficients. - * @param[in] *pState points to the state buffer. - * @param[in] *pTapDelay points to the array of offset times. - * @param[in] maxDelay maximum offset time supported. - * @param[in] blockSize number of samples that will be processed per block. - * @return none - */ - - void arm_fir_sparse_init_q7( - arm_fir_sparse_instance_q7 * S, - uint16_t numTaps, - q7_t * pCoeffs, - q7_t * pState, - int32_t * pTapDelay, - uint16_t maxDelay, - uint32_t blockSize); - - - /* - * @brief Floating-point sin_cos function. - * @param[in] theta input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cos output. - * @return none. - */ - - void arm_sin_cos_f32( - float32_t theta, - float32_t * pSinVal, - float32_t * pCcosVal); - - /* - * @brief Q31 sin_cos function. - * @param[in] theta scaled input value in degrees - * @param[out] *pSinVal points to the processed sine output. - * @param[out] *pCosVal points to the processed cosine output. - * @return none. - */ - - void arm_sin_cos_q31( - q31_t theta, - q31_t * pSinVal, - q31_t * pCosVal); - - - /** - * @brief Floating-point complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex conjugate. - * @param[in] *pSrc points to the input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_conj_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - - /** - * @brief Floating-point complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude squared - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_squared_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup PID PID Motor Control - * - * A Proportional Integral Derivative (PID) controller is a generic feedback control - * loop mechanism widely used in industrial control systems. - * A PID controller is the most commonly used type of feedback controller. - * - * This set of functions implements (PID) controllers - * for Q15, Q31, and floating-point data types. The functions operate on a single sample - * of data and each call to the function returns a single processed value. - * S points to an instance of the PID control data structure. in - * is the input sample value. The functions return the output value. - * - * \par Algorithm: - * 
    -   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
-   *    A0 = Kp + Ki + Kd
-   *    A1 = (-Kp ) - (2 * Kd )
-   *    A2 = Kd
    - * - * \par - * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant - * - * \par - * \image html PID.gif "Proportional Integral Derivative Controller" - * - * \par - * The PID controller calculates an "error" value as the difference between - * the measured output and the reference input. - * The controller attempts to minimize the error by adjusting the process control inputs. - * The proportional value determines the reaction to the current error, - * the integral value determines the reaction based on the sum of recent errors, - * and the derivative value determines the reaction based on the rate at which the error has been changing. - * - * \par Instance Structure - * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. - * A separate instance structure must be defined for each PID Controller. - * There are separate instance structure declarations for each of the 3 supported data types. - * - * \par Reset Functions - * There is also an associated reset function for each data type which clears the state array. - * - * \par Initialization Functions - * There is also an associated initialization function for each data type. - * The initialization function performs the following operations: - * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. - * - Zeros out the values in the state buffer. - * - * \par - * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. - * - * \par Fixed-Point Behavior - * Care must be taken when using the fixed-point versions of the PID Controller functions. - * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup PID - * @{ - */ - - /** - * @brief Process function for the floating-point PID Control. - * @param[in,out] *S is an instance of the floating-point PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - */ - - - static __INLINE float32_t arm_pid_f32( - arm_pid_instance_f32 * S, - float32_t in) - { - float32_t out; - - /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ - out = (S->A0 * in) + - (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q31 PID Control. - * @param[in,out] *S points to an instance of the Q31 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 64-bit accumulator. - * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. - * Thus, if the accumulator result overflows it wraps around rather than clip. - * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. - * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. - */ - - static __INLINE q31_t arm_pid_q31( - arm_pid_instance_q31 * S, - q31_t in) - { - q63_t acc; - q31_t out; - - /* acc = A0 * x[n] */ - acc = (q63_t) S->A0 * in; - - /* acc += A1 * x[n-1] */ - acc += (q63_t) S->A1 * S->state[0]; - - /* acc += A2 * x[n-2] */ - acc += (q63_t) S->A2 * S->state[1]; - - /* convert output to 1.31 format to add y[n-1] */ - out = (q31_t) (acc >> 31u); - - /* out += y[n-1] */ - out += S->state[2]; - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @brief Process function for the Q15 PID Control. - * @param[in,out] *S points to an instance of the Q15 PID Control structure - * @param[in] in input sample to process - * @return out processed output sample. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using a 64-bit internal accumulator. - * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. - * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. - * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. - * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. - * Lastly, the accumulator is saturated to yield a result in 1.15 format. - */ - - static __INLINE q15_t arm_pid_q15( - arm_pid_instance_q15 * S, - q15_t in) - { - q63_t acc; - q15_t out; - -#ifndef ARM_MATH_CM0_FAMILY - __SIMD32_TYPE *vstate; - - /* Implementation of PID controller */ - - /* acc = A0 * x[n] */ - acc = (q31_t) __SMUAD(S->A0, in); - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - vstate = __SIMD32_CONST(S->state); - acc = __SMLALD(S->A1, (q31_t) *vstate, acc); - -#else - /* acc = A0 * x[n] */ - acc = ((q31_t) S->A0) * in; - - /* acc += A1 * x[n-1] + A2 * x[n-2] */ - acc += (q31_t) S->A1 * S->state[0]; - acc += (q31_t) S->A2 * S->state[1]; - -#endif - - /* acc += y[n-1] */ - acc += (q31_t) S->state[2] << 15; - - /* saturate the output */ - out = (q15_t) (__SSAT((acc >> 15), 16)); - - /* Update state */ - S->state[1] = S->state[0]; - S->state[0] = in; - S->state[2] = out; - - /* return to application */ - return (out); - - } - - /** - * @} end of PID group - */ - - - /** - * @brief Floating-point matrix inverse. - * @param[in] *src points to the instance of the input floating-point matrix structure. - * @param[out] *dst points to the instance of the output floating-point matrix structure. - * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. - * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. - */ - - arm_status arm_mat_inverse_f32( - const arm_matrix_instance_f32 * src, - arm_matrix_instance_f32 * dst); - - - - /** - * @ingroup groupController - */ - - - /** - * @defgroup clarke Vector Clarke Transform - * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. - * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents - * in the two-phase orthogonal stator axis Ialpha and Ibeta. - * When Ialpha is superposed with Ia as shown in the figure below - * \image html clarke.gif Stator current space vector and its components in (a,b). - * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta - * can be calculated using only Ia and Ib. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeFormula.gif - * where Ia and Ib are the instantaneous stator phases and - * pIalpha and pIbeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup clarke - * @{ - */ - - /** - * - * @brief Floating-point Clarke transform - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - */ - - static __INLINE void arm_clarke_f32( - float32_t Ia, - float32_t Ib, - float32_t * pIalpha, - float32_t * pIbeta) - { - /* Calculate pIalpha using the equation, pIalpha = Ia */ - *pIalpha = Ia; - - /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ - *pIbeta = - ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib); - - } - - /** - * @brief Clarke transform for Q31 version - * @param[in] Ia input three-phase coordinate a - * @param[in] Ib input three-phase coordinate b - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - static __INLINE void arm_clarke_q31( - q31_t Ia, - q31_t Ib, - q31_t * pIalpha, - q31_t * pIbeta) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIalpha from Ia by equation pIalpha = Ia */ - *pIalpha = Ia; - - /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30); - - /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ - product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30); - - /* pIbeta is calculated by adding the intermediate products */ - *pIbeta = __QADD(product1, product2); - } - - /** - * @} end of clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q31 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q31( - q7_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_clarke Vector Inverse Clarke Transform - * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html clarkeInvFormula.gif - * where pIa and pIb are the instantaneous stator phases and - * Ialpha and Ibeta are the two coordinates of time invariant vector. - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Clarke transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_clarke - * @{ - */ - - /** - * @brief Floating-point Inverse Clarke transform - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - */ - - - static __INLINE void arm_inv_clarke_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pIa, - float32_t * pIb) - { - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ - *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta; - - } - - /** - * @brief Inverse Clarke transform for Q31 version - * @param[in] Ialpha input two-phase orthogonal vector axis alpha - * @param[in] Ibeta input two-phase orthogonal vector axis beta - * @param[out] *pIa points to output three-phase coordinate a - * @param[out] *pIb points to output three-phase coordinate b - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the subtraction, hence there is no risk of overflow. - */ - - static __INLINE void arm_inv_clarke_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pIa, - q31_t * pIb) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - - /* Calculating pIa from Ialpha by equation pIa = Ialpha */ - *pIa = Ialpha; - - /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31); - - /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31); - - /* pIb is calculated by subtracting the products */ - *pIb = __QSUB(product2, product1); - - } - - /** - * @} end of inv_clarke group - */ - - /** - * @brief Converts the elements of the Q7 vector to Q15 vector. - * @param[in] *pSrc input pointer - * @param[out] *pDst output pointer - * @param[in] blockSize number of samples to process - * @return none. - */ - void arm_q7_to_q15( - q7_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - - - /** - * @ingroup groupController - */ - - /** - * @defgroup park Vector Park Transform - * - * Forward Park transform converts the input two-coordinate vector to flux and torque components. - * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents - * from the stationary to the moving reference frame and control the spatial relationship between - * the stator vector current and rotor flux vector. - * If we consider the d axis aligned with the rotor flux, the diagram below shows the - * current vector and the relationship from the two reference frames: - * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkFormula.gif - * where Ialpha and Ibeta are the stator vector components, - * pId and pIq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup park - * @{ - */ - - /** - * @brief Floating-point Park transform - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * The function implements the forward Park transform. - * - */ - - static __INLINE void arm_park_f32( - float32_t Ialpha, - float32_t Ibeta, - float32_t * pId, - float32_t * pIq, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ - *pId = Ialpha * cosVal + Ibeta * sinVal; - - /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ - *pIq = -Ialpha * sinVal + Ibeta * cosVal; - - } - - /** - * @brief Park transform for Q31 version - * @param[in] Ialpha input two-phase vector coordinate alpha - * @param[in] Ibeta input two-phase vector coordinate beta - * @param[out] *pId points to output rotor reference frame d - * @param[out] *pIq points to output rotor reference frame q - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition and subtraction, hence there is no risk of overflow. - */ - - - static __INLINE void arm_park_q31( - q31_t Ialpha, - q31_t Ibeta, - q31_t * pId, - q31_t * pIq, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Ialpha * cosVal) */ - product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * sinVal) */ - product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Ialpha * sinVal) */ - product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Ibeta * cosVal) */ - product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31); - - /* Calculate pId by adding the two intermediate products 1 and 2 */ - *pId = __QADD(product1, product2); - - /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ - *pIq = __QSUB(product4, product3); - } - - /** - * @} end of park group - */ - - /** - * @brief Converts the elements of the Q7 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q7_to_float( - q7_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupController - */ - - /** - * @defgroup inv_park Vector Inverse Park transform - * Inverse Park transform converts the input flux and torque components to two-coordinate vector. - * - * The function operates on a single sample of data and each call to the function returns the processed output. - * The library provides separate functions for Q31 and floating-point data types. - * \par Algorithm - * \image html parkInvFormula.gif - * where pIalpha and pIbeta are the stator vector components, - * Id and Iq are rotor vector components and cosVal and sinVal are the - * cosine and sine values of theta (rotor flux position). - * \par Fixed-Point Behavior - * Care must be taken when using the Q31 version of the Park transform. - * In particular, the overflow and saturation behavior of the accumulator used must be considered. - * Refer to the function specific documentation below for usage guidelines. - */ - - /** - * @addtogroup inv_park - * @{ - */ - - /** - * @brief Floating-point Inverse Park transform - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - */ - - static __INLINE void arm_inv_park_f32( - float32_t Id, - float32_t Iq, - float32_t * pIalpha, - float32_t * pIbeta, - float32_t sinVal, - float32_t cosVal) - { - /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ - *pIalpha = Id * cosVal - Iq * sinVal; - - /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ - *pIbeta = Id * sinVal + Iq * cosVal; - - } - - - /** - * @brief Inverse Park transform for Q31 version - * @param[in] Id input coordinate of rotor reference frame d - * @param[in] Iq input coordinate of rotor reference frame q - * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha - * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta - * @param[in] sinVal sine value of rotation angle theta - * @param[in] cosVal cosine value of rotation angle theta - * @return none. - * - * Scaling and Overflow Behavior: - * \par - * The function is implemented using an internal 32-bit accumulator. - * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. - * There is saturation on the addition, hence there is no risk of overflow. - */ - - - static __INLINE void arm_inv_park_q31( - q31_t Id, - q31_t Iq, - q31_t * pIalpha, - q31_t * pIbeta, - q31_t sinVal, - q31_t cosVal) - { - q31_t product1, product2; /* Temporary variables used to store intermediate results */ - q31_t product3, product4; /* Temporary variables used to store intermediate results */ - - /* Intermediate product is calculated by (Id * cosVal) */ - product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31); - - /* Intermediate product is calculated by (Iq * sinVal) */ - product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31); - - - /* Intermediate product is calculated by (Id * sinVal) */ - product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31); - - /* Intermediate product is calculated by (Iq * cosVal) */ - product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31); - - /* Calculate pIalpha by using the two intermediate products 1 and 2 */ - *pIalpha = __QSUB(product1, product2); - - /* Calculate pIbeta by using the two intermediate products 3 and 4 */ - *pIbeta = __QADD(product4, product3); - - } - - /** - * @} end of Inverse park group - */ - - - /** - * @brief Converts the elements of the Q31 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_float( - q31_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup LinearInterpolate Linear Interpolation - * - * Linear interpolation is a method of curve fitting using linear polynomials. - * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line - * - * \par - * \image html LinearInterp.gif "Linear interpolation" - * - * \par - * A Linear Interpolate function calculates an output value(y), for the input(x) - * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) - * - * \par Algorithm: - * 
    -   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
-   *       where x0, x1 are nearest values of input x
-   *             y0, y1 are nearest values to output y
-   *
    - * - * \par - * This set of functions implements Linear interpolation process - * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single - * sample of data and each call to the function returns a single processed value. - * S points to an instance of the Linear Interpolate function data structure. - * x is the input sample value. The functions returns the output value. - * - * \par - * if x is outside of the table boundary, Linear interpolation returns first value of the table - * if x is below input range and returns last value of table if x is above range. - */ - - /** - * @addtogroup LinearInterpolate - * @{ - */ - - /** - * @brief Process function for the floating-point Linear Interpolation Function. - * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure - * @param[in] x input sample to process - * @return y processed output sample. - * - */ - - static __INLINE float32_t arm_linear_interp_f32( - arm_linear_interp_instance_f32 * S, - float32_t x) - { - - float32_t y; - float32_t x0, x1; /* Nearest input values */ - float32_t y0, y1; /* Nearest output values */ - float32_t xSpacing = S->xSpacing; /* spacing between input values */ - int32_t i; /* Index variable */ - float32_t *pYData = S->pYData; /* pointer to output table */ - - /* Calculation of index */ - i = (int32_t) ((x - S->x1) / xSpacing); - - if(i < 0) - { - /* Iniatilize output for below specified range as least output value of table */ - y = pYData[0]; - } - else if((uint32_t)i >= S->nValues) - { - /* Iniatilize output for above specified range as last output value of table */ - y = pYData[S->nValues - 1]; - } - else - { - /* Calculation of nearest input values */ - x0 = S->x1 + i * xSpacing; - x1 = S->x1 + (i + 1) * xSpacing; - - /* Read of nearest output values */ - y0 = pYData[i]; - y1 = pYData[i + 1]; - - /* Calculation of output */ - y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); - - } - - /* returns output value */ - return (y); - } - - /** - * - * @brief Process function for the Q31 Linear Interpolation Function. - * @param[in] *pYData pointer to Q31 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q31_t arm_linear_interp_q31( - q31_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q31_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - - /* 20 bits for the fractional part */ - /* shift left by 11 to keep fract in 1.31 format */ - fract = (x & 0x000FFFFF) << 11; - - /* Read two nearest output values from the index in 1.31(q31) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 2.30 format */ - y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32)); - - /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ - y += ((q31_t) (((q63_t) y1 * fract) >> 32)); - - /* Convert y to 1.31 format */ - return (y << 1u); - - } - - } - - /** - * - * @brief Process function for the Q15 Linear Interpolation Function. - * @param[in] *pYData pointer to Q15 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - * - */ - - - static __INLINE q15_t arm_linear_interp_q15( - q15_t * pYData, - q31_t x, - uint32_t nValues) - { - q63_t y; /* output */ - q15_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - int32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - index = ((x & 0xFFF00000) >> 20u); - - if(index >= (int32_t)(nValues - 1)) - { - return (pYData[nValues - 1]); - } - else if(index < 0) - { - return (pYData[0]); - } - else - { - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract) and y is in 13.35 format */ - y = ((q63_t) y0 * (0xFFFFF - fract)); - - /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ - y += ((q63_t) y1 * (fract)); - - /* convert y to 1.15 format */ - return (y >> 20); - } - - - } - - /** - * - * @brief Process function for the Q7 Linear Interpolation Function. - * @param[in] *pYData pointer to Q7 Linear Interpolation table - * @param[in] x input sample to process - * @param[in] nValues number of table values - * @return y processed output sample. - * - * \par - * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. - * This function can support maximum of table size 2^12. - */ - - - static __INLINE q7_t arm_linear_interp_q7( - q7_t * pYData, - q31_t x, - uint32_t nValues) - { - q31_t y; /* output */ - q7_t y0, y1; /* Nearest output values */ - q31_t fract; /* fractional part */ - uint32_t index; /* Index to read nearest output values */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - if (x < 0) - { - return (pYData[0]); - } - index = (x >> 20) & 0xfff; - - - if(index >= (nValues - 1)) - { - return (pYData[nValues - 1]); - } - else - { - - /* 20 bits for the fractional part */ - /* fract is in 12.20 format */ - fract = (x & 0x000FFFFF); - - /* Read two nearest output values from the index and are in 1.7(q7) format */ - y0 = pYData[index]; - y1 = pYData[index + 1u]; - - /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ - y = ((y0 * (0xFFFFF - fract))); - - /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ - y += (y1 * fract); - - /* convert y to 1.7(q7) format */ - return (y >> 20u); - - } - - } - /** - * @} end of LinearInterpolate group - */ - - /** - * @brief Fast approximation to the trigonometric sine function for floating-point data. - * @param[in] x input value in radians. - * @return sin(x). - */ - - float32_t arm_sin_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q31_t arm_sin_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric sine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return sin(x). - */ - - q15_t arm_sin_q15( - q15_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for floating-point data. - * @param[in] x input value in radians. - * @return cos(x). - */ - - float32_t arm_cos_f32( - float32_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q31 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q31_t arm_cos_q31( - q31_t x); - - /** - * @brief Fast approximation to the trigonometric cosine function for Q15 data. - * @param[in] x Scaled input value in radians. - * @return cos(x). - */ - - q15_t arm_cos_q15( - q15_t x); - - - /** - * @ingroup groupFastMath - */ - - - /** - * @defgroup SQRT Square Root - * - * Computes the square root of a number. - * There are separate functions for Q15, Q31, and floating-point data types. - * The square root function is computed using the Newton-Raphson algorithm. - * This is an iterative algorithm of the form: - * 
    -   *      x1 = x0 - f(x0)/f'(x0)
-   *
    - * where x1 is the current estimate, - * x0 is the previous estimate, and - * f'(x0) is the derivative of f() evaluated at x0. - * For the square root function, the algorithm reduces to: - * 
    -   *     x0 = in/2                         [initial guess]
-   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
-   *
    - */ - - - /** - * @addtogroup SQRT - * @{ - */ - - /** - * @brief Floating-point square root function. - * @param[in] in input value. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - - static __INLINE arm_status arm_sqrt_f32( - float32_t in, - float32_t * pOut) - { - if(in > 0) - { - -// #if __FPU_USED -#if (__FPU_USED == 1) && defined ( __CC_ARM ) - *pOut = __sqrtf(in); -#else - *pOut = sqrtf(in); -#endif - - return (ARM_MATH_SUCCESS); - } - else - { - *pOut = 0.0f; - return (ARM_MATH_ARGUMENT_ERROR); - } - - } - - - /** - * @brief Q31 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q31( - q31_t in, - q31_t * pOut); - - /** - * @brief Q15 square root function. - * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. - * @param[out] *pOut square root of input value. - * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if - * in is negative value and returns zero output for negative values. - */ - arm_status arm_sqrt_q15( - q15_t in, - q15_t * pOut); - - /** - * @} end of SQRT group - */ - - - - - - - /** - * @brief floating-point Circular write function. - */ - - static __INLINE void arm_circularWrite_f32( - int32_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const int32_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief floating-point Circular Read function. - */ - static __INLINE void arm_circularRead_f32( - int32_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - int32_t * dst, - int32_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (int32_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - /** - * @brief Q15 Circular write function. - */ - - static __INLINE void arm_circularWrite_q15( - q15_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q15_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q15 Circular Read function. - */ - static __INLINE void arm_circularRead_q15( - q15_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q15_t * dst, - q15_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q15_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update wOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Q7 Circular write function. - */ - - static __INLINE void arm_circularWrite_q7( - q7_t * circBuffer, - int32_t L, - uint16_t * writeOffset, - int32_t bufferInc, - const q7_t * src, - int32_t srcInc, - uint32_t blockSize) - { - uint32_t i = 0u; - int32_t wOffset; - - /* Copy the value of Index pointer that points - * to the current location where the input samples to be copied */ - wOffset = *writeOffset; - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the input sample to the circular buffer */ - circBuffer[wOffset] = *src; - - /* Update the input pointer */ - src += srcInc; - - /* Circularly update wOffset. Watch out for positive and negative value */ - wOffset += bufferInc; - if(wOffset >= L) - wOffset -= L; - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *writeOffset = wOffset; - } - - - - /** - * @brief Q7 Circular Read function. - */ - static __INLINE void arm_circularRead_q7( - q7_t * circBuffer, - int32_t L, - int32_t * readOffset, - int32_t bufferInc, - q7_t * dst, - q7_t * dst_base, - int32_t dst_length, - int32_t dstInc, - uint32_t blockSize) - { - uint32_t i = 0; - int32_t rOffset, dst_end; - - /* Copy the value of Index pointer that points - * to the current location from where the input samples to be read */ - rOffset = *readOffset; - - dst_end = (int32_t) (dst_base + dst_length); - - /* Loop over the blockSize */ - i = blockSize; - - while(i > 0u) - { - /* copy the sample from the circular buffer to the destination buffer */ - *dst = circBuffer[rOffset]; - - /* Update the input pointer */ - dst += dstInc; - - if(dst == (q7_t *) dst_end) - { - dst = dst_base; - } - - /* Circularly update rOffset. Watch out for positive and negative value */ - rOffset += bufferInc; - - if(rOffset >= L) - { - rOffset -= L; - } - - /* Decrement the loop counter */ - i--; - } - - /* Update the index pointer */ - *readOffset = rOffset; - } - - - /** - * @brief Sum of the squares of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q31( - q31_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q15( - q15_t * pSrc, - uint32_t blockSize, - q63_t * pResult); - - /** - * @brief Sum of the squares of the elements of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_power_q7( - q7_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_mean_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult); - - /** - * @brief Mean value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Mean value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Mean value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - void arm_mean_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Variance of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Variance of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_var_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Root Mean Square of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Root Mean Square of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_rms_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Standard deviation of the elements of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult); - - /** - * @brief Standard deviation of the elements of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output value. - * @return none. - */ - - void arm_std_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult); - - /** - * @brief Floating-point complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_f32( - float32_t * pSrc, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q31( - q31_t * pSrc, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex magnitude - * @param[in] *pSrc points to the complex input vector - * @param[out] *pDst points to the real output vector - * @param[in] numSamples number of complex samples in the input vector - * @return none. - */ - - void arm_cmplx_mag_q15( - q15_t * pSrc, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q15 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q15( - q15_t * pSrcA, - q15_t * pSrcB, - uint32_t numSamples, - q31_t * realResult, - q31_t * imagResult); - - /** - * @brief Q31 complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_q31( - q31_t * pSrcA, - q31_t * pSrcB, - uint32_t numSamples, - q63_t * realResult, - q63_t * imagResult); - - /** - * @brief Floating-point complex dot product - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[in] numSamples number of complex samples in each vector - * @param[out] *realResult real part of the result returned here - * @param[out] *imagResult imaginary part of the result returned here - * @return none. - */ - - void arm_cmplx_dot_prod_f32( - float32_t * pSrcA, - float32_t * pSrcB, - uint32_t numSamples, - float32_t * realResult, - float32_t * imagResult); - - /** - * @brief Q15 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q15( - q15_t * pSrcCmplx, - q15_t * pSrcReal, - q15_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_q31( - q31_t * pSrcCmplx, - q31_t * pSrcReal, - q31_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-real multiplication - * @param[in] *pSrcCmplx points to the complex input vector - * @param[in] *pSrcReal points to the real input vector - * @param[out] *pCmplxDst points to the complex output vector - * @param[in] numSamples number of samples in each vector - * @return none. - */ - - void arm_cmplx_mult_real_f32( - float32_t * pSrcCmplx, - float32_t * pSrcReal, - float32_t * pCmplxDst, - uint32_t numSamples); - - /** - * @brief Minimum value of a Q7 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *result is output pointer - * @param[in] index is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * result, - uint32_t * index); - - /** - * @brief Minimum value of a Q15 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[in] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a Q31 vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - void arm_min_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - - /** - * @brief Minimum value of a floating-point vector. - * @param[in] *pSrc is input pointer - * @param[in] blockSize is the number of samples to process - * @param[out] *pResult is output pointer - * @param[out] *pIndex is the array index of the minimum value in the input buffer. - * @return none. - */ - - void arm_min_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q7 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q7( - q7_t * pSrc, - uint32_t blockSize, - q7_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q15 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q15( - q15_t * pSrc, - uint32_t blockSize, - q15_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a Q31 vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_q31( - q31_t * pSrc, - uint32_t blockSize, - q31_t * pResult, - uint32_t * pIndex); - -/** - * @brief Maximum value of a floating-point vector. - * @param[in] *pSrc points to the input buffer - * @param[in] blockSize length of the input vector - * @param[out] *pResult maximum value returned here - * @param[out] *pIndex index of maximum value returned here - * @return none. - */ - - void arm_max_f32( - float32_t * pSrc, - uint32_t blockSize, - float32_t * pResult, - uint32_t * pIndex); - - /** - * @brief Q15 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q15( - q15_t * pSrcA, - q15_t * pSrcB, - q15_t * pDst, - uint32_t numSamples); - - /** - * @brief Q31 complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_q31( - q31_t * pSrcA, - q31_t * pSrcB, - q31_t * pDst, - uint32_t numSamples); - - /** - * @brief Floating-point complex-by-complex multiplication - * @param[in] *pSrcA points to the first input vector - * @param[in] *pSrcB points to the second input vector - * @param[out] *pDst points to the output vector - * @param[in] numSamples number of complex samples in each vector - * @return none. - */ - - void arm_cmplx_mult_cmplx_f32( - float32_t * pSrcA, - float32_t * pSrcB, - float32_t * pDst, - uint32_t numSamples); - - /** - * @brief Converts the elements of the floating-point vector to Q31 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q31 output vector - * @param[in] blockSize length of the input vector - * @return none. - */ - void arm_float_to_q31( - float32_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q15 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q15 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q15( - float32_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the floating-point vector to Q7 vector. - * @param[in] *pSrc points to the floating-point input vector - * @param[out] *pDst points to the Q7 output vector - * @param[in] blockSize length of the input vector - * @return none - */ - void arm_float_to_q7( - float32_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q31 vector to Q15 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q15( - q31_t * pSrc, - q15_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q31 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q31_to_q7( - q31_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - /** - * @brief Converts the elements of the Q15 vector to floating-point vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_float( - q15_t * pSrc, - float32_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q31 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q31( - q15_t * pSrc, - q31_t * pDst, - uint32_t blockSize); - - - /** - * @brief Converts the elements of the Q15 vector to Q7 vector. - * @param[in] *pSrc is input pointer - * @param[out] *pDst is output pointer - * @param[in] blockSize is the number of samples to process - * @return none. - */ - void arm_q15_to_q7( - q15_t * pSrc, - q7_t * pDst, - uint32_t blockSize); - - - /** - * @ingroup groupInterpolation - */ - - /** - * @defgroup BilinearInterpolate Bilinear Interpolation - * - * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. - * The underlying function f(x, y) is sampled on a regular grid and the interpolation process - * determines values between the grid points. - * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. - * Bilinear interpolation is often used in image processing to rescale images. - * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. - * - * Algorithm - * \par - * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. - * For floating-point, the instance structure is defined as: - * 
    -   *   typedef struct
-   *   {
-   *     uint16_t numRows;
-   *     uint16_t numCols;
-   *     float32_t *pData;
-   * } arm_bilinear_interp_instance_f32;
-   *
    - * - * \par - * where numRows specifies the number of rows in the table; - * numCols specifies the number of columns in the table; - * and pData points to an array of size numRows*numCols values. - * The data table pTable is organized in row order and the supplied data values fall on integer indexes. - * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. - * - * \par - * Let (x, y) specify the desired interpolation point. Then define: - * 
    -   *     XF = floor(x)
-   *     YF = floor(y)
-   *
    - * \par - * The interpolated output point is computed as: - * 
    -   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
-   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
-   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
-   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
-   *
    - * Note that the coordinates (x, y) contain integer and fractional components. - * The integer components specify which portion of the table to use while the - * fractional components control the interpolation processor. - * - * \par - * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. - */ - - /** - * @addtogroup BilinearInterpolate - * @{ - */ - - /** - * - * @brief Floating-point bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate. - * @param[in] Y interpolation coordinate. - * @return out interpolated value. - */ - - - static __INLINE float32_t arm_bilinear_interp_f32( - const arm_bilinear_interp_instance_f32 * S, - float32_t X, - float32_t Y) - { - float32_t out; - float32_t f00, f01, f10, f11; - float32_t *pData = S->pData; - int32_t xIndex, yIndex, index; - float32_t xdiff, ydiff; - float32_t b1, b2, b3, b4; - - xIndex = (int32_t) X; - yIndex = (int32_t) Y; - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 - || yIndex > (S->numCols - 1)) - { - return (0); - } - - /* Calculation of index for two nearest points in X-direction */ - index = (xIndex - 1) + (yIndex - 1) * S->numCols; - - - /* Read two nearest points in X-direction */ - f00 = pData[index]; - f01 = pData[index + 1]; - - /* Calculation of index for two nearest points in Y-direction */ - index = (xIndex - 1) + (yIndex) * S->numCols; - - - /* Read two nearest points in Y-direction */ - f10 = pData[index]; - f11 = pData[index + 1]; - - /* Calculation of intermediate values */ - b1 = f00; - b2 = f01 - f00; - b3 = f10 - f00; - b4 = f00 - f01 - f10 + f11; - - /* Calculation of fractional part in X */ - xdiff = X - xIndex; - - /* Calculation of fractional part in Y */ - ydiff = Y - yIndex; - - /* Calculation of bi-linear interpolated output */ - out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; - - /* return to application */ - return (out); - - } - - /** - * - * @brief Q31 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q31_t arm_bilinear_interp_q31( - arm_bilinear_interp_instance_q31 * S, - q31_t X, - q31_t Y) - { - q31_t out; /* Temporary output */ - q31_t acc = 0; /* output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q31_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q31_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20u); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20u); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* shift left xfract by 11 to keep 1.31 format */ - xfract = (X & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - /* 20 bits for the fractional part */ - /* shift left yfract by 11 to keep 1.31 format */ - yfract = (Y & 0x000FFFFF) << 11u; - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ - out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32)); - acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32)); - - /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (xfract) >> 32)); - - /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ - out = ((q31_t) ((q63_t) y2 * (xfract) >> 32)); - acc += ((q31_t) ((q63_t) out * (yfract) >> 32)); - - /* Convert acc to 1.31(q31) format */ - return (acc << 2u); - - } - - /** - * @brief Q15 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q15_t arm_bilinear_interp_q15( - arm_bilinear_interp_instance_q15 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q15_t x1, x2, y1, y2; /* Nearest output values */ - q31_t xfract, yfract; /* X, Y fractional parts */ - int32_t rI, cI; /* Row and column indices */ - q15_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ - - /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ - /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ - out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u); - acc = ((q63_t) out * (0xFFFFF - yfract)); - - /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u); - acc += ((q63_t) out * (xfract)); - - /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ - out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u); - acc += ((q63_t) out * (yfract)); - - /* acc is in 13.51 format and down shift acc by 36 times */ - /* Convert out to 1.15 format */ - return (acc >> 36); - - } - - /** - * @brief Q7 bilinear interpolation. - * @param[in,out] *S points to an instance of the interpolation structure. - * @param[in] X interpolation coordinate in 12.20 format. - * @param[in] Y interpolation coordinate in 12.20 format. - * @return out interpolated value. - */ - - static __INLINE q7_t arm_bilinear_interp_q7( - arm_bilinear_interp_instance_q7 * S, - q31_t X, - q31_t Y) - { - q63_t acc = 0; /* output */ - q31_t out; /* Temporary output */ - q31_t xfract, yfract; /* X, Y fractional parts */ - q7_t x1, x2, y1, y2; /* Nearest output values */ - int32_t rI, cI; /* Row and column indices */ - q7_t *pYData = S->pData; /* pointer to output table values */ - uint32_t nCols = S->numCols; /* num of rows */ - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - rI = ((X & 0xFFF00000) >> 20); - - /* Input is in 12.20 format */ - /* 12 bits for the table index */ - /* Index value calculation */ - cI = ((Y & 0xFFF00000) >> 20); - - /* Care taken for table outside boundary */ - /* Returns zero output when values are outside table boundary */ - if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) - { - return (0); - } - - /* 20 bits for the fractional part */ - /* xfract should be in 12.20 format */ - xfract = (X & 0x000FFFFF); - - /* Read two nearest output values from the index */ - x1 = pYData[(rI) + nCols * (cI)]; - x2 = pYData[(rI) + nCols * (cI) + 1u]; - - - /* 20 bits for the fractional part */ - /* yfract should be in 12.20 format */ - yfract = (Y & 0x000FFFFF); - - /* Read two nearest output values from the index */ - y1 = pYData[(rI) + nCols * (cI + 1)]; - y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; - - /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ - out = ((x1 * (0xFFFFF - xfract))); - acc = (((q63_t) out * (0xFFFFF - yfract))); - - /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ - out = ((x2 * (0xFFFFF - yfract))); - acc += (((q63_t) out * (xfract))); - - /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y1 * (0xFFFFF - xfract))); - acc += (((q63_t) out * (yfract))); - - /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ - out = ((y2 * (yfract))); - acc += (((q63_t) out * (xfract))); - - /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ - return (acc >> 40); - - } - - /** - * @} end of BilinearInterpolate group - */ - - -#if defined ( __CC_ARM ) //Keil -//SMMLAR - #define multAcc_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMLSR - #define multSub_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32) - -//SMMULR - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("push") \ - _Pragma ("O1") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT \ - _Pragma ("pop") - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__ICCARM__) //IAR - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - -//Enter low optimization region - place directly above function definition - #define LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define LOW_OPTIMIZATION_EXIT - -//Enter low optimization region - place directly above function definition - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \ - _Pragma ("optimize=low") - -//Exit low optimization region - place directly after end of function definition - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__GNUC__) - //SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - - #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") )) - - #define LOW_OPTIMIZATION_EXIT - - #define IAR_ONLY_LOW_OPTIMIZATION_ENTER - - #define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#elif defined(__CSMC__) // Cosmic -//SMMLA - #define multAcc_32x32_keep32_R(a, x, y) \ - a += (q31_t) (((q63_t) x * y) >> 32) - - //SMMLS - #define multSub_32x32_keep32_R(a, x, y) \ - a -= (q31_t) (((q63_t) x * y) >> 32) - -//SMMUL - #define mult_32x32_keep32_R(a, x, y) \ - a = (q31_t) (((q63_t) x * y ) >> 32) - -#define LOW_OPTIMIZATION_ENTER -#define LOW_OPTIMIZATION_EXIT -#define IAR_ONLY_LOW_OPTIMIZATION_ENTER -#define IAR_ONLY_LOW_OPTIMIZATION_EXIT - -#endif - - - - - -#ifdef __cplusplus -} -#endif - - -#endif /* _ARM_MATH_H */ - - -/** - * - * End of file. - */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h deleted file mode 100644 index 36f637ee7..000000000 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/libchip_samv7/include/cmsis/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,1790 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V3.30 - * @date 06. May 2014 - * - * @note - * - ******************************************************************************/ -/* Copyright (c) 2009 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#ifdef __cplusplus - extern "C" { -#endif - -/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
    - Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    - Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
    - Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** \ingroup Cortex_M4 - @{ - */ - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (0x30) /*!< [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ - -#define __CORTEX_M (0x04) /*!< Cortex-M Core */ - - -#if defined ( __CC_ARM ) - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #define __STATIC_INLINE static __inline - -#elif defined ( __GNUC__ ) - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __ICCARM__ ) - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #define __STATIC_INLINE static inline - -#elif defined ( __TMS470__ ) - #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __TASKING__ ) - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #define __STATIC_INLINE static inline - -#elif defined ( __CSMC__ ) /* Cosmic */ - #define __packed - #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ - #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ - #define __STATIC_INLINE static inline - -#endif - -/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TMS470__ ) - #if defined __TI_VFP_SUPPORT__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif - -#elif defined ( __CSMC__ ) /* Cosmic */ - #if ( __CSMC__ & 0x400) // FPU present for parser - #if (__FPU_PRESENT == 1) - #define __FPU_USED 1 - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0 - #endif - #else - #define __FPU_USED 0 - #endif -#endif - -#include /* standard types definitions */ -#include /* Core Instruction Access */ -#include /* Core Function Access */ -#include /* Compiler specific SIMD Intrinsics */ - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000 - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0 - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0 - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 4 - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0 - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ -#else - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ -#endif - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - - -/** \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - - -/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ -#if (__CORTEX_M != 0x04) - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ -#else - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ -#endif - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - - -/** \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/*@} end of group CMSIS_CORE */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24]; - __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[24]; - __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24]; - __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24]; - __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56]; - __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644]; - __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5]; - __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Registers Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* SCB Hard Fault Status Registers Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_CALIB_TENMS_Pos) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __O union - { - __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864]; - __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15]; - __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15]; - __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[29]; - __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ - __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ - __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ - uint32_t RESERVED4[43]; - __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6]; - __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Integration Write Register Definitions */ -#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ -#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ - -/* ITM Integration Read Register Definitions */ -#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ -#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ - -/* ITM Integration Mode Control Register Definitions */ -#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ -#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1]; - __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1]; - __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1]; - __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2]; - __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55]; - __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131]; - __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759]; - __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ - __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1]; - __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39]; - __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8]; - __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ -#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ -#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if (__MPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register */ -#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register */ -#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register */ -#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register */ -#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register */ -#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if (__FPU_PRESENT == 1) -/** \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1]; - __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ -} FPU_Type; - -/* Floating-Point Context Control Register */ -#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register */ -#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register */ -#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ - -/*@} end of group CMSIS_FPU */ -#endif - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register */ -#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Cortex-M4 Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if (__MPU_PRESENT == 1) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#if (__FPU_PRESENT == 1) - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -/** \brief Set Priority Grouping - - The function sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ - SCB->AIRCR = reg_value; -} - - -/** \brief Get Priority Grouping - - The function reads the priority grouping field from the NVIC Interrupt Controller. - - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) -{ - return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ -} - - -/** \brief Enable External Interrupt - - The function enables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) -{ -/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ - NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ -} - - -/** \brief Disable External Interrupt - - The function disables a device-specific interrupt in the NVIC interrupt controller. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) -{ - NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ -} - - -/** \brief Get Pending Interrupt - - The function reads the pending register in the NVIC and returns the pending bit - for the specified interrupt. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - */ -__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ -} - - -/** \brief Set Pending Interrupt - - The function sets the pending bit of an external interrupt. - - \param [in] IRQn Interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ -} - - -/** \brief Clear Pending Interrupt - - The function clears the pending bit of an external interrupt. - - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ -} - - -/** \brief Get Active Interrupt - - The function reads the active register in NVIC and returns the active bit. - - \param [in] IRQn Interrupt number. - - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - */ -__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) -{ - return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ -} - - -/** \brief Set Interrupt Priority - - The function sets the priority of an interrupt. - - \note The priority cannot be set for every core interrupt. - - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - */ -__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if(IRQn < 0) { - SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ - else { - NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ -} - - -/** \brief Get Interrupt Priority - - The function reads the priority of an interrupt. The interrupt - number can be positive to specify an external (device specific) - interrupt, or negative to specify an internal (core) interrupt. - - - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented - priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) -{ - - if(IRQn < 0) { - return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ - else { - return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ -} - - -/** \brief Encode Priority - - The function encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - return ( - ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | - ((SubPriority & ((1 << (SubPriorityBits )) - 1))) - ); -} - - -/** \brief Decode Priority - - The function decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; - SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; - - *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); - *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); -} - - -/** \brief System Reset - - The function initiates a system reset request to reset the MCU. - */ -__STATIC_INLINE void NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - while(1); /* wait until reset */ -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if (__Vendor_SysTickConfig == 0) - -/** \brief System Tick Configuration - - The function initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - - \param [in] ticks Number of ticks between two interrupts. - - \return 0 Function succeeded. - \return 1 Function failed. - - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ - - SysTick->LOAD = ticks - 1; /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** \brief ITM Send Character - - The function transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - - \param [in] ch Character to transmit. - - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ - (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0].u32 == 0); - ITM->PORT[0].u8 = (uint8_t) ch; - } - return (ch); -} - - -/** \brief ITM Receive Character - - The function inputs a character via the external variable \ref ITM_RxBuffer. - - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) { - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** \brief ITM Check Character - - The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) { - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { - return (0); /* no character available */ - } else { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __CMSIS_GENERIC */ diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat index 3f1fe57d2..031884d9e 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.Debug.cspy.bat @@ -25,7 +25,7 @@ if not "%1" == "" goto debugFile @echo on -"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" @echo off goto end @@ -34,7 +34,7 @@ goto end @echo on -"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\temp\FreeRTOSv8.2.1\clean\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" +"C:\DevTools\IAR Systems\Embedded Workbench 7.2\common\bin\cspybat" -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.general.xcl" "--debug_file=%1" --backend -f "C:\E\Dev\FreeRTOS\WorkingCopy\FreeRTOS\Demo\CORTEX_M7_SAMV71_Xplained_IAR_Keil\settings\RTOSDemo.Debug.driver.xcl" @echo off :end \ No newline at end of file diff --git a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt index a92c77bbe..3646f8897 100644 --- a/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt +++ b/FreeRTOS/Demo/CORTEX_M7_SAMV71_Xplained_IAR_Keil/settings/RTOSDemo.wsdt @@ -28,7 +28,7 @@ - + TabID-23288-9694 @@ -40,7 +40,7 @@ - 0 + 0 TabID-13649-20313 @@ -56,7 +56,7 @@ TabID-30315-19856Find in FilesFind-in-Files - 0 + 0 @@ -69,7 +69,7 @@ - iaridepm.enu1-2-2770272-2-2200174119048176829163095784553-2-21701682-2-216841721002381174797119048176829 + iaridepm.enu1-2-2770272-2-2200174119048176829163095784553-2-21701682-2-216841721002381174797119048176829