From: Lad, Prabhakar Date: Sun, 24 Jun 2012 21:35:21 +0000 (+0000) Subject: da850/omap-l138: Fix NAND flash timings X-Git-Tag: v2012.10-rc1~345 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=de94b80d3c8ea4d3b52c9c33d85a9a93c7c4182d;p=u-boot da850/omap-l138: Fix NAND flash timings Though Commit id a3f88293ddd13facd734769c1664d35ab4ed681f (da850evm: setup the NAND flash timings) has configured the AEMIF timings, they are not exactly in sync with the timings used in Linux. Linux is configuring the timing register as 0x08222204, where as currently it configured to 0x00100084 in U-Boot. This issue was found out when support for NAND SPL is added in U-Boot. Without this patch U-Boot does not come up with SPL. Tested-by: Christian Riesch Signed-off-by: Lad, Prabhakar Signed-off-by: Rajashekhara, Sudhakar Signed-off-by: Hadli, Manjunath --- diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 152a524959..0c7aabb134 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -348,11 +348,11 @@ int board_init(void) * NAND CS setup - cycle counts based on da850evm NAND timings in the * Linux kernel @ 25MHz EMIFA */ - writel((DAVINCI_ABCR_WSETUP(0) | - DAVINCI_ABCR_WSTROBE(1) | - DAVINCI_ABCR_WHOLD(0) | - DAVINCI_ABCR_RSETUP(0) | - DAVINCI_ABCR_RSTROBE(1) | + writel((DAVINCI_ABCR_WSETUP(2) | + DAVINCI_ABCR_WSTROBE(2) | + DAVINCI_ABCR_WHOLD(1) | + DAVINCI_ABCR_RSETUP(1) | + DAVINCI_ABCR_RSTROBE(4) | DAVINCI_ABCR_RHOLD(0) | DAVINCI_ABCR_TA(1) | DAVINCI_ABCR_ASIZE_8BIT),