From: Stefan Roese Date: Mon, 16 Jul 2007 08:00:43 +0000 (+0200) Subject: ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c X-Git-Tag: v1.3.0-rc1~38 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=df3f17422aeb03fb81a7ac8c78d2b05d05aa4cf9;p=u-boot ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.c The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese --- diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 7316c34b4a..d08fcf3565 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -562,6 +562,40 @@ int checkboard (void) return 0; } +/* + * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with + * board specific values. + */ +static int ppc440spe_rev_a(void) +{ + if ((get_pvr() == PVR_440SPe_6_RA) || (get_pvr() == PVR_440SPe_RA)) + return 1; + else + return 0; +} + +u32 ddr_wrdtr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_WRDTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_270_DEG_ADV); + + return default_val; +} + +u32 ddr_clktr(u32 default_val) { + /* + * Yucca boards with 440SPe rev. A need a slightly different setup + * for the MCIF0_CLKTR register. + */ + if (ppc440spe_rev_a()) + return (SDRAM_CLKTR_CLKP_180_DEG_ADV); + + return default_val; +} + #if defined(CFG_DRAM_TEST) int testdram (void) {