From: richardbarry Date: Sun, 5 Jul 2009 13:48:46 +0000 (+0000) Subject: Update header files to include CMSIS files. X-Git-Tag: V5.4.1~27 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=e092e6b2944b01512f6aba993e256b3e22bd38cb;p=freertos Update header files to include CMSIS files. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@798 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev.h b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev.h new file mode 100644 index 000000000..1e1743870 --- /dev/null +++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev.h @@ -0,0 +1,109 @@ +/* + * @file: EthDev.h + * @purpose: Ethernet Device Definitions + * @version: V1.10 + * @date: 24. Feb. 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + */ + +#ifndef _ETHDEV__H +#define _ETHDEV__H + +#ifndef NULL + #define NULL 0 +#endif + +/*---------------------------------------------------------------------------- + Ethernet Device Defines + *----------------------------------------------------------------------------*/ +#define EthDev_ADDR_SIZE 6 /*!< Ethernet Address size in bytes */ +#define EthDev_MTU_SIZE 1514 /*!< Maximum Transmission Unit */ + + +/*---------------------------------------------------------------------------- + Ethernet Device Configuration and Control Command Defines + *----------------------------------------------------------------------------*/ +typedef enum { + EthDev_LINK_DOWN = 0, /*!< Ethernet link not established */ + EthDev_LINK_UP = 1, /*!< Ethernet link established */ +} EthDev_LINK; + +typedef enum { + EthDev_SPEED_10M = 0, /*!< 10.0 Mbps link speed */ + EthDev_SPEED_100M = 1, /*!< 100.0 Mbps link speed */ + EthDev_SPEED_1000M = 2, /*!< 1.0 Gbps link speed */ +} EthDev_SPEED; + +typedef enum { + EthDev_DUPLEX_HALF = 0, /*!< Link half duplex */ + EthDev_DUPLEX_FULL = 1, /*!< Link full duplex */ +} EthDev_DUPLEX; + +typedef enum { + EthDev_MODE_AUTO = 0, + EthDev_MODE_10M_FULL = 1, + EthDev_MODE_10M_HALF = 2, + EthDev_MODE_100M_FULL = 3, + EthDev_MODE_100M_HALF = 4, + EthDev_MODE_1000M_FULL = 5, + EthDev_MODE_1000M_HALF = 6, +} EthDev_MODE; + +typedef struct { + EthDev_LINK Link : 1; + EthDev_DUPLEX Duplex : 1; + EthDev_SPEED Speed : 2; +} EthDev_STATUS; + + +/*---------------------------------------------------------------------------- + Ethernet Device IO Block Structure + *----------------------------------------------------------------------------*/ +typedef struct { + + /* Initialized by the user application before call to Init. */ + EthDev_MODE Mode; + unsigned char HwAddr[EthDev_ADDR_SIZE]; + void *(*RxFrame) (int size); + void (*RxFrameReady) (int size); + + /* Initialized by Ethernet driver. */ + int (*Init) (void); + int (*UnInit) (void); + int (*SetMCFilter)(int NumHwAddr, unsigned char *pHwAddr); + int (*TxFrame) (void *pData, int size); + void (*Lock) (void); + void (*UnLock) (void); + EthDev_STATUS (*LinkChk) (void); +} EthDev_IOB; + +// prototypes +portBASE_TYPE Init_EMAC(void); +unsigned short ReadFrameBE_EMAC(void); +void CopyToFrame_EMAC(void *Source, unsigned int Size); +void CopyFromFrame_EMAC(void *Dest, unsigned short Size); +void DummyReadFrame_EMAC(unsigned short Size); +unsigned short StartReadFrame(void); +void EndReadFrame(void); +unsigned int CheckFrameReceived(void); +void RequestSend(void); +unsigned int Rdy4Tx(void); +void DoSend_EMAC(unsigned short FrameSize); +void vEMACWaitForInput( void ); +unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); + + +#endif diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev_LPC17xx.h b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev_LPC17xx.h new file mode 100644 index 000000000..352f57e65 --- /dev/null +++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/EthDev_LPC17xx.h @@ -0,0 +1,332 @@ +/* + * @file: EthDev_LPC17xx.h + * @purpose: Ethernet Device Definitions for NXP LPC17xx + * @version: V0.01 + * @date: 14. May 2009 + *---------------------------------------------------------------------------- + * + * Copyright (C) 2009 ARM Limited. All rights reserved. + * + * ARM Limited (ARM) is supplying this software for use with Cortex-M3 + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + */ + +#ifndef __ETHDEV_LPC17XX_H +#define __ETHDEV_LPC17XX_H + +#include + +/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ +#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ +#define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */ +#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ + +#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ + +typedef struct { /* RX Descriptor struct */ + uint32_t Packet; + uint32_t Ctrl; +} RX_DESC_TypeDef; + +typedef struct { /* RX Status struct */ + uint32_t Info; + uint32_t HashCRC; +} RX_STAT_TypeDef; + +typedef struct { /* TX Descriptor struct */ + uint32_t Packet; + uint32_t Ctrl; +} TX_DESC_TypeDef; + +typedef struct { /* TX Status struct */ + uint32_t Info; +} TX_STAT_TypeDef; + + +/* EMAC variables located in AHB SRAM bank 1*/ +#define AHB_SRAM_BANK1_BASE 0x2007c000UL +#define RX_DESC_BASE (AHB_SRAM_BANK1_BASE ) +#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_DESC_TypeDef */ +#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*(2*4)) /* 2 * uint32_t, see RX_STAT_TypeDef */ +#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*(2*4)) /* 2 * uint32_t, see TX_DESC_TypeDef */ +#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*(1*4)) /* 1 * uint32_t, see TX_STAT_TypeDef */ +#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) + +/* RX and TX descriptor and status definitions. */ +#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) +#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) +#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) +#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) +#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) +#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) +#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) +#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) +#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) + + + +/* MAC Configuration Register 1 */ +#define MAC1_REC_EN 0x00000001 /* Receive Enable */ +#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ +#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ +#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ +#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ +#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ +#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ +#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ +#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ +#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ +#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ + +/* MAC Configuration Register 2 */ +#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ +#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ +#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ +#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ +#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ +#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ +#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ +#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ +#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ +#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ +#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ +#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ +#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ + +/* Back-to-Back Inter-Packet-Gap Register */ +#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ +#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ + +/* Non Back-to-Back Inter-Packet-Gap Register */ +#define IPGR_DEF 0x00000012 /* Recommended value */ + +/* Collision Window/Retry Register */ +#define CLRT_DEF 0x0000370F /* Default value */ + +/* PHY Support Register */ +#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ +#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ + +/* Test Register */ +#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ +#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ +#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ + +/* MII Management Configuration Register */ +#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ +#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ +#define MCFG_CLK_SEL 0x0000003C /* Clock Select Mask */ +#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ + +/* MII Management Command Register */ +#define MCMD_READ 0x00000001 /* MII Read */ +#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ + +#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ +#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ + +/* MII Management Address Register */ +#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ +#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ + +/* MII Management Indicators Register */ +#define MIND_BUSY 0x00000001 /* MII is Busy */ +#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ +#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ +#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ + +/* Command Register */ +#define CR_RX_EN 0x00000001 /* Enable Receive */ +#define CR_TX_EN 0x00000002 /* Enable Transmit */ +#define CR_REG_RES 0x00000008 /* Reset Host Registers */ +#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ +#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ +#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ +#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ +#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ +#define CR_RMII 0x00000200 /* Reduced MII Interface */ +#define CR_FULL_DUP 0x00000400 /* Full Duplex */ + +/* Status Register */ +#define SR_RX_EN 0x00000001 /* Enable Receive */ +#define SR_TX_EN 0x00000002 /* Enable Transmit */ + +/* Transmit Status Vector 0 Register */ +#define TSV0_CRC_ERR 0x00000001 /* CRC error */ +#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ +#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ +#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ +#define TSV0_MCAST 0x00000010 /* Multicast Destination */ +#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ +#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ +#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ +#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ +#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ +#define TSV0_GIANT 0x00000400 /* Giant Frame */ +#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ +#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ +#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ +#define TSV0_PAUSE 0x20000000 /* Pause Frame */ +#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ +#define TSV0_VLAN 0x80000000 /* VLAN Frame */ + +/* Transmit Status Vector 1 Register */ +#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ +#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ + +/* Receive Status Vector Register */ +#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ +#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ +#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ +#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ +#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ +#define RSV_CRC_ERR 0x00100000 /* CRC Error */ +#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ +#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ +#define RSV_REC_OK 0x00800000 /* Frame Received OK */ +#define RSV_MCAST 0x01000000 /* Multicast Frame */ +#define RSV_BCAST 0x02000000 /* Broadcast Frame */ +#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ +#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ +#define RSV_PAUSE 0x10000000 /* Pause Frame */ +#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ +#define RSV_VLAN 0x40000000 /* VLAN Frame */ + +/* Flow Control Counter Register */ +#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ +#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ + +/* Flow Control Status Register */ +#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ + +/* Receive Filter Control Register */ +#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ +#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ +#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ +#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ +#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ +#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ +#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ +#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ + +/* Receive Filter WoL Status/Clear Registers */ +#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ +#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ +#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ +#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ +#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ +#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ +#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ +#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ + +/* Interrupt Status/Enable/Clear/Set Registers */ +#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ +#define INT_RX_ERR 0x00000002 /* Receive Error */ +#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ +#define INT_RX_DONE 0x00000008 /* Receive Done */ +#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ +#define INT_TX_ERR 0x00000020 /* Transmit Error */ +#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ +#define INT_TX_DONE 0x00000080 /* Transmit Done */ +#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ +#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ + +/* Power Down Register */ +#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ + +/* RX Descriptor Control Word */ +#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ +#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ + +/* RX Status Hash CRC Word */ +#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ +#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ + +/* RX Status Information Word */ +#define RINFO_SIZE 0x000007FF /* Data size in bytes */ +#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ +#define RINFO_VLAN 0x00080000 /* VLAN Frame */ +#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ +#define RINFO_MCAST 0x00200000 /* Multicast Frame */ +#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ +#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ +#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ +#define RINFO_LEN_ERR 0x02000000 /* Length Error */ +#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ +#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ +#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ +#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ +#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ +#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ + RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) + +/* TX Descriptor Control Word */ +#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ +#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ +#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ +#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ +#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ +#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ +#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ + +/* TX Status Information Word */ +#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ +#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ +#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ +#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ +#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ +#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ +#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ +#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ + +/* ENET Device Revision ID */ +#define OLD_EMAC_MODULE_ID 0x39022000 /* Rev. ID for first rev '-' */ + +/* DP83848C PHY Registers */ +#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ +#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ +#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ +#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ +#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ +#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ +#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ +#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ + +/* PHY Extended Registers */ +#define PHY_REG_STS 0x10 /* Status Register */ +#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ +#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ +#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ +#define PHY_REG_RECR 0x15 /* Receive Error Counter */ +#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ +#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ +#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ +#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ +#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ +#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ +#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ + +#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ +#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ +#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ +#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ +#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ + +#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ +#define DP83848C_ID 0x20005C90 /* PHY Identifier */ + +#endif + +/*---------------------------------------------------------------------------- + * end of file + *---------------------------------------------------------------------------*/ diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c deleted file mode 100644 index 1368c2157..000000000 --- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.c +++ /dev/null @@ -1,465 +0,0 @@ -/****************************************************************** - ***** ***** - ***** Ver.: 1.0 ***** - ***** Date: 07/05/2001 ***** - ***** Auth: Andreas Dannenberg ***** - ***** HTWK Leipzig ***** - ***** university of applied sciences ***** - ***** Germany ***** - ***** Func: ethernet packet-driver for use with LAN- ***** - ***** controller CS8900 from Crystal/Cirrus Logic ***** - ***** ***** - ***** Keil: Module modified for use with Philips ***** - ***** LPC2378 EMAC Ethernet controller ***** - ***** ***** - ******************************************************************/ - -/* Adapted from file originally written by Andreas Dannenberg. Supplied with permission. */ -#include "FreeRTOS.h" -#include "semphr.h" -#include "task.h" -#include "emac.h" -#include "LPC17xx_defs.h" - -#define configPINSEL2_VALUE 0x50150105 - -/* The semaphore used to wake the uIP task when data arives. */ -xSemaphoreHandle xEMACSemaphore = NULL; - -static unsigned short *rptr; -static unsigned short *tptr; - -static unsigned short SwapBytes( unsigned short Data ) -{ - return( Data >> 8 ) | ( Data << 8 ); -} - -// Keil: function added to write PHY -int write_PHY( int PhyReg, int Value ) -{ - unsigned int tout; - const unsigned int uiMaxTime = 10; - - MAC_MADR = DP83848C_DEF_ADR | PhyReg; - MAC_MWTD = Value; - - /* Wait utill operation completed */ - tout = 0; - for( tout = 0; tout < uiMaxTime; tout++ ) - { - if( (MAC_MIND & MIND_BUSY) == 0 ) - { - break; - } - - vTaskDelay( 2 ); - } - - if( tout < uiMaxTime ) - { - return pdPASS; - } - else - { - return pdFAIL; - } -} - -// Keil: function added to read PHY -unsigned short read_PHY( unsigned char PhyReg, portBASE_TYPE *pxStatus ) -{ - unsigned int tout; - const unsigned int uiMaxTime = 10; - - MAC_MADR = DP83848C_DEF_ADR | PhyReg; - MAC_MCMD = MCMD_READ; - - /* Wait until operation completed */ - tout = 0; - for( tout = 0; tout < uiMaxTime; tout++ ) - { - if( (MAC_MIND & MIND_BUSY) == 0 ) - { - break; - } - - vTaskDelay( 2 ); - } - - MAC_MCMD = 0; - - if( tout >= uiMaxTime ) - { - *pxStatus = pdFAIL; - } - - return( MAC_MRDD ); -} - -// Keil: function added to initialize Rx Descriptors -void rx_descr_init( void ) -{ - unsigned int i; - - for( i = 0; i < NUM_RX_FRAG; i++ ) - { - RX_DESC_PACKET( i ) = RX_BUF( i ); - RX_DESC_CTRL( i ) = RCTRL_INT | ( ETH_FRAG_SIZE - 1 ); - RX_STAT_INFO( i ) = 0; - RX_STAT_HASHCRC( i ) = 0; - } - - /* Set EMAC Receive Descriptor Registers. */ - MAC_RXDESCRIPTOR = RX_DESC_BASE; - MAC_RXSTATUS = RX_STAT_BASE; - MAC_RXDESCRIPTORNUM = NUM_RX_FRAG - 1; - - /* Rx Descriptors Point to 0 */ - MAC_RXCONSUMEINDEX = 0; -} - -// Keil: function added to initialize Tx Descriptors -void tx_descr_init( void ) -{ - unsigned int i; - - for( i = 0; i < NUM_TX_FRAG; i++ ) - { - TX_DESC_PACKET( i ) = TX_BUF( i ); - TX_DESC_CTRL( i ) = 0; - TX_STAT_INFO( i ) = 0; - } - - /* Set EMAC Transmit Descriptor Registers. */ - MAC_TXDESCRIPTOR = TX_DESC_BASE; - MAC_TXSTATUS = TX_STAT_BASE; - MAC_TXDESCRIPTORNUM = NUM_TX_FRAG - 1; - - /* Tx Descriptors Point to 0 */ - MAC_TXPRODUCEINDEX = 0; -} - -// configure port-pins for use with LAN-controller, -// reset it and send the configuration-sequence -portBASE_TYPE Init_EMAC( void ) -{ - portBASE_TYPE xReturn = pdPASS; - - // Keil: function modified to access the EMAC - // Initializes the EMAC ethernet controller - volatile unsigned int regv, tout, id1, id2; - - /* Enable P1 Ethernet Pins. */ - PINSEL2 = configPINSEL2_VALUE; - PINSEL3 = ( PINSEL3 &~0x0000000F ) | 0x00000005; - - /* Power Up the EMAC controller. */ - PCONP |= PCONP_PCENET; - vTaskDelay( 2 ); - - /* Reset all EMAC internal modules. */ - MAC_MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX | MAC1_SIM_RES | MAC1_SOFT_RES; - MAC_COMMAND = CR_REG_RES | CR_TX_RES | CR_RX_RES | CR_PASS_RUNT_FRM; - - /* A short delay after reset. */ - vTaskDelay( 2 ); - - /* Initialize MAC control registers. */ - MAC_MAC1 = MAC1_PASS_ALL; - MAC_MAC2 = MAC2_CRC_EN | MAC2_PAD_EN; - MAC_MAXF = ETH_MAX_FLEN; - MAC_CLRT = CLRT_DEF; - MAC_IPGR = IPGR_DEF; - - /* Enable Reduced MII interface. */ - MAC_COMMAND = CR_RMII | CR_PASS_RUNT_FRM; - - /* Reset Reduced MII Logic. */ - MAC_SUPP = SUPP_RES_RMII; - vTaskDelay( 2 ); - MAC_SUPP = 0; - - /* Put the PHY in reset mode */ - write_PHY( PHY_REG_BMCR, 0x8000 ); - xReturn = write_PHY( PHY_REG_BMCR, 0x8000 ); - - /* Wait for hardware reset to end. */ - for( tout = 0; tout < 100; tout++ ) - { - vTaskDelay( 10 ); - regv = read_PHY( PHY_REG_BMCR, &xReturn ); - if( !(regv & 0x8000) ) - { - /* Reset complete */ - break; - } - } - - /* Check if this is a DP83848C PHY. */ - id1 = read_PHY( PHY_REG_IDR1, &xReturn ); - id2 = read_PHY( PHY_REG_IDR2, &xReturn ); - if( ((id1 << 16) | (id2 & 0xFFF0)) == DP83848C_ID ) - { - /* Set the Ethernet MAC Address registers */ - MAC_SA0 = ( emacETHADDR0 << 8 ) | emacETHADDR1; - MAC_SA1 = ( emacETHADDR2 << 8 ) | emacETHADDR3; - MAC_SA2 = ( emacETHADDR4 << 8 ) | emacETHADDR5; - - /* Initialize Tx and Rx DMA Descriptors */ - rx_descr_init(); - tx_descr_init(); - - /* Receive Broadcast and Perfect Match Packets */ - MAC_RXFILTERCTRL = RFC_UCAST_EN | RFC_BCAST_EN | RFC_PERFECT_EN; - - /* Create the semaphore used ot wake the uIP task. */ - vSemaphoreCreateBinary( xEMACSemaphore ); - - /* Configure the PHY device */ - - /* Use autonegotiation about the link speed. */ - if( write_PHY(PHY_REG_BMCR, PHY_AUTO_NEG) ) - { - /* Wait to complete Auto_Negotiation. */ - for( tout = 0; tout < 10; tout++ ) - { - vTaskDelay( 100 ); - regv = read_PHY( PHY_REG_BMSR, &xReturn ); - if( regv & 0x0020 ) - { - /* Autonegotiation Complete. */ - break; - } - } - } - } - else - { - xReturn = pdFAIL; - } - - /* Check the link status. */ - if( xReturn == pdPASS ) - { - xReturn = pdFAIL; - for( tout = 0; tout < 10; tout++ ) - { - vTaskDelay( 100 ); - regv = read_PHY( PHY_REG_STS, &xReturn ); - if( regv & 0x0001 ) - { - /* Link is on. */ - xReturn = pdPASS; - break; - } - } - } - - if( xReturn == pdPASS ) - { - /* Configure Full/Half Duplex mode. */ - if( regv & 0x0004 ) - { - /* Full duplex is enabled. */ - MAC_MAC2 |= MAC2_FULL_DUP; - MAC_COMMAND |= CR_FULL_DUP; - MAC_IPGT = IPGT_FULL_DUP; - } - else - { - /* Half duplex mode. */ - MAC_IPGT = IPGT_HALF_DUP; - } - - /* Configure 100MBit/10MBit mode. */ - if( regv & 0x0002 ) - { - /* 10MBit mode. */ - MAC_SUPP = 0; - } - else - { - /* 100MBit mode. */ - MAC_SUPP = SUPP_SPEED; - } - - /* Reset all interrupts */ - MAC_INTCLEAR = 0xFFFF; - - /* Enable receive and transmit mode of MAC Ethernet core */ - MAC_COMMAND |= ( CR_RX_EN | CR_TX_EN ); - MAC_MAC1 |= MAC1_REC_EN; - } - - return xReturn; -} - -// reads a word in little-endian byte order from RX_BUFFER -unsigned short ReadFrame_EMAC( void ) -{ - return( *rptr++ ); -} - -// reads a word in big-endian byte order from RX_FRAME_PORT -// (useful to avoid permanent byte-swapping while reading -// TCP/IP-data) -unsigned short ReadFrameBE_EMAC( void ) -{ - unsigned short ReturnValue; - - ReturnValue = SwapBytes( *rptr++ ); - return( ReturnValue ); -} - -// copies bytes from frame port to MCU-memory -// NOTES: * an odd number of byte may only be transfered -// if the frame is read to the end! -// * MCU-memory MUST start at word-boundary -void CopyFromFrame_EMAC( void *Dest, unsigned short Size ) -{ - unsigned short *piDest; // Keil: Pointer added to correct expression - piDest = Dest; // Keil: Line added - while( Size > 1 ) - { - *piDest++ = ReadFrame_EMAC(); - Size -= 2; - } - - if( Size ) - { // check for leftover byte... - *( unsigned char * ) piDest = ( char ) ReadFrame_EMAC(); // the LAN-Controller will return 0 - } // for the highbyte -} - -// does a dummy read on frame-I/O-port -// NOTE: only an even number of bytes is read! -void DummyReadFrame_EMAC( unsigned short Size ) // discards an EVEN number of bytes -{ // from RX-fifo - while( Size > 1 ) - { - ReadFrame_EMAC(); - Size -= 2; - } -} - -// Reads the length of the received ethernet frame and checks if the -// destination address is a broadcast message or not -// returns the frame length -unsigned short StartReadFrame( void ) -{ - unsigned short RxLen; - unsigned int idx; - - idx = MAC_RXCONSUMEINDEX; - RxLen = ( RX_STAT_INFO(idx) & RINFO_SIZE ) - 3; - rptr = ( unsigned short * ) RX_DESC_PACKET( idx ); - return( RxLen ); -} - -void EndReadFrame( void ) -{ - unsigned int idx; - - /* DMA free packet. */ - idx = MAC_RXCONSUMEINDEX; - - if( ++idx == NUM_RX_FRAG ) - { - idx = 0; - } - - MAC_RXCONSUMEINDEX = idx; -} - -unsigned int CheckFrameReceived( void ) -{ - // Packet received ? - if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX ) - { // more packets received ? - return( 1 ); - } - else - { - return( 0 ); - } -} - -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ) -{ - unsigned int uiLen = 0; - - if( MAC_RXPRODUCEINDEX != MAC_RXCONSUMEINDEX ) - { - uiLen = StartReadFrame(); - CopyFromFrame_EMAC( ucBuffer, uiLen ); - EndReadFrame(); - } - - return uiLen; -} - -// requests space in EMAC memory for storing an outgoing frame -void RequestSend( void ) -{ - unsigned int idx; - - idx = MAC_TXPRODUCEINDEX; - tptr = ( unsigned short * ) TX_DESC_PACKET( idx ); -} - -// check if ethernet controller is ready to accept the -// frame we want to send -unsigned int Rdy4Tx( void ) -{ - return( 1 ); // the ethernet controller transmits much faster -} // than the CPU can load its buffers - -// writes a word in little-endian byte order to TX_BUFFER -void WriteFrame_EMAC( unsigned short Data ) -{ - *tptr++ = Data; -} - -// copies bytes from MCU-memory to frame port -// NOTES: * an odd number of byte may only be transfered -// if the frame is written to the end! -// * MCU-memory MUST start at word-boundary -void CopyToFrame_EMAC( void *Source, unsigned int Size ) -{ - unsigned short *piSource; - - piSource = Source; - Size = ( Size + 1 ) & 0xFFFE; // round Size up to next even number - while( Size > 0 ) - { - WriteFrame_EMAC( *piSource++ ); - Size -= 2; - } -} - -void DoSend_EMAC( unsigned short FrameSize ) -{ - unsigned int idx; - - idx = MAC_TXPRODUCEINDEX; - TX_DESC_CTRL( idx ) = FrameSize | TCTRL_LAST; - if( ++idx == NUM_TX_FRAG ) - { - idx = 0; - } - - MAC_TXPRODUCEINDEX = idx; -} - -void vEMAC_ISR( void ) -{ - portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE; - - /* Clear the interrupt. */ - MAC_INTCLEAR = 0xffff; - - /* Ensure the uIP task is not blocked as data has arrived. */ - xSemaphoreGiveFromISR( xEMACSemaphore, &xHigherPriorityTaskWoken ); - - portEND_SWITCHING_ISR( xHigherPriorityTaskWoken ); -} diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.h b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.h deleted file mode 100644 index 6aa5249e2..000000000 --- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/emac.h +++ /dev/null @@ -1,324 +0,0 @@ -/*---------------------------------------------------------------------------- - * LPC2378 Ethernet Definitions - *---------------------------------------------------------------------------- - * Name: EMAC.H - * Purpose: Philips LPC2378 EMAC hardware definitions - *---------------------------------------------------------------------------- - * Copyright (c) 2006 KEIL - An ARM Company. All rights reserved. - *---------------------------------------------------------------------------*/ -#ifndef __EMAC_H -#define __EMAC_H - -/* MAC address definition. The MAC address must be unique on the network. */ -#define emacETHADDR0 0 -#define emacETHADDR1 0xbd -#define emacETHADDR2 0x33 -#define emacETHADDR3 0x02 -#define emacETHADDR4 0x64 -#define emacETHADDR5 0x24 - - -/* EMAC Memory Buffer configuration for 16K Ethernet RAM. */ -#define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */ -#define NUM_TX_FRAG 2 /* Num.of TX Fragments 2*1536= 3.0kB */ -#define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */ - -#define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */ - -/* EMAC variables located in 16K Ethernet SRAM */ -//extern unsigned char xEthDescriptors[]; -#define RX_DESC_BASE (0x2007c000UL) -#define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8) -#define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8) -#define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8) -#define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4) -#define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE) -#define TX_BUF_END (TX_BUF_BASE + NUM_TX_FRAG*ETH_FRAG_SIZE) - -/* RX and TX descriptor and status definitions. */ -#define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i)) -#define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i)) -#define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i)) -#define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i)) -#define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i)) -#define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i)) -#define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i)) -#define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i) -#define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i) - -/* MAC Configuration Register 1 */ -#define MAC1_REC_EN 0x00000001 /* Receive Enable */ -#define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */ -#define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */ -#define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */ -#define MAC1_LOOPB 0x00000010 /* Loop Back Mode */ -#define MAC1_RES_TX 0x00000100 /* Reset TX Logic */ -#define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */ -#define MAC1_RES_RX 0x00000400 /* Reset RX Logic */ -#define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */ -#define MAC1_SIM_RES 0x00004000 /* Simulation Reset */ -#define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */ - -/* MAC Configuration Register 2 */ -#define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */ -#define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */ -#define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */ -#define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */ -#define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */ -#define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */ -#define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */ -#define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */ -#define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */ -#define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */ -#undef MAC2_NO_BACKOFF /* Remove compiler warning. */ -#define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */ -#define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */ -#define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */ - -/* Back-to-Back Inter-Packet-Gap Register */ -#define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */ -#define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */ - -/* Non Back-to-Back Inter-Packet-Gap Register */ -#define IPGR_DEF 0x00000012 /* Recommended value */ - -/* Collision Window/Retry Register */ -#define CLRT_DEF 0x0000370F /* Default value */ - -/* PHY Support Register */ -#undef SUPP_SPEED /* Remove compiler warning. */ -#define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */ -#define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */ - -/* Test Register */ -#define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */ -#define TEST_TST_PAUSE 0x00000002 /* Test Pause */ -#define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */ - -/* MII Management Configuration Register */ -#define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */ -#define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */ -#define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */ -#define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */ - -/* MII Management Command Register */ -#undef MCMD_READ /* Remove compiler warning. */ -#define MCMD_READ 0x00000001 /* MII Read */ -#undef MCMD_SCAN /* Remove compiler warning. */ -#define MCMD_SCAN 0x00000002 /* MII Scan continuously */ - -#define MII_WR_TOUT 0x00050000 /* MII Write timeout count */ -#define MII_RD_TOUT 0x00050000 /* MII Read timeout count */ - -/* MII Management Address Register */ -#define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */ -#define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */ - -/* MII Management Indicators Register */ -#undef MIND_BUSY /* Remove compiler warning. */ -#define MIND_BUSY 0x00000001 /* MII is Busy */ -#define MIND_SCAN 0x00000002 /* MII Scanning in Progress */ -#define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */ -#define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */ - -/* Command Register */ -#define CR_RX_EN 0x00000001 /* Enable Receive */ -#define CR_TX_EN 0x00000002 /* Enable Transmit */ -#define CR_REG_RES 0x00000008 /* Reset Host Registers */ -#define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */ -#define CR_RX_RES 0x00000020 /* Reset Receive Datapath */ -#define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */ -#define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */ -#define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */ -#define CR_RMII 0x00000200 /* Reduced MII Interface */ -#define CR_FULL_DUP 0x00000400 /* Full Duplex */ - -/* Status Register */ -#define SR_RX_EN 0x00000001 /* Enable Receive */ -#define SR_TX_EN 0x00000002 /* Enable Transmit */ - -/* Transmit Status Vector 0 Register */ -#define TSV0_CRC_ERR 0x00000001 /* CRC error */ -#define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */ -#define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */ -#define TSV0_DONE 0x00000008 /* Tramsmission Completed */ -#define TSV0_MCAST 0x00000010 /* Multicast Destination */ -#define TSV0_BCAST 0x00000020 /* Broadcast Destination */ -#define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */ -#define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */ -#define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */ -#define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */ -#define TSV0_GIANT 0x00000400 /* Giant Frame */ -#define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */ -#define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */ -#define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */ -#define TSV0_PAUSE 0x20000000 /* Pause Frame */ -#define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */ -#define TSV0_VLAN 0x80000000 /* VLAN Frame */ - -/* Transmit Status Vector 1 Register */ -#define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */ -#define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */ - -/* Receive Status Vector Register */ -#define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */ -#define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */ -#define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */ -#define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */ -#define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */ -#define RSV_CRC_ERR 0x00100000 /* CRC Error */ -#define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */ -#define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */ -#define RSV_REC_OK 0x00800000 /* Frame Received OK */ -#define RSV_MCAST 0x01000000 /* Multicast Frame */ -#define RSV_BCAST 0x02000000 /* Broadcast Frame */ -#define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */ -#define RSV_CTRL_FRAME 0x08000000 /* Control Frame */ -#define RSV_PAUSE 0x10000000 /* Pause Frame */ -#define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */ -#define RSV_VLAN 0x40000000 /* VLAN Frame */ - -/* Flow Control Counter Register */ -#define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */ -#define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */ - -/* Flow Control Status Register */ -#define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */ - -/* Receive Filter Control Register */ -#define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */ -#define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */ -#define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */ -#define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */ -#define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/ -#define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */ -#define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */ -#define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */ - -/* Receive Filter WoL Status/Clear Registers */ -#define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */ -#define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */ -#define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */ -#define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */ -#define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */ -#define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */ -#define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */ -#define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */ - -/* Interrupt Status/Enable/Clear/Set Registers */ -#define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */ -#define INT_RX_ERR 0x00000002 /* Receive Error */ -#define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */ -#define INT_RX_DONE 0x00000008 /* Receive Done */ -#define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */ -#define INT_TX_ERR 0x00000020 /* Transmit Error */ -#define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */ -#define INT_TX_DONE 0x00000080 /* Transmit Done */ -#define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */ -#define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */ - -/* Power Down Register */ -#define PD_POWER_DOWN 0x80000000 /* Power Down MAC */ - -/* RX Descriptor Control Word */ -#define RCTRL_SIZE 0x000007FF /* Buffer size mask */ -#define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */ - -/* RX Status Hash CRC Word */ -#define RHASH_SA 0x000001FF /* Hash CRC for Source Address */ -#define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */ - -/* RX Status Information Word */ -#define RINFO_SIZE 0x000007FF /* Data size in bytes */ -#define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */ -#define RINFO_VLAN 0x00080000 /* VLAN Frame */ -#define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */ -#define RINFO_MCAST 0x00200000 /* Multicast Frame */ -#define RINFO_BCAST 0x00400000 /* Broadcast Frame */ -#define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */ -#define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */ -#define RINFO_LEN_ERR 0x02000000 /* Length Error */ -#define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */ -#define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */ -#define RINFO_OVERRUN 0x10000000 /* Receive overrun */ -#define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */ -#define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */ -#define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -#define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \ - RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN) - -/* TX Descriptor Control Word */ -#define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */ -#define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */ -#define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */ -#define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */ -#define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */ -#define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */ -#define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */ - -/* TX Status Information Word */ -#define TINFO_COL_CNT 0x01E00000 /* Collision Count */ -#define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */ -#define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */ -#define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */ -#define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */ -#define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */ -#define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */ -#define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */ - -/* DP83848C PHY Registers */ -#define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */ -#define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */ -#define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */ -#define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */ -#define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */ -#define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */ -#define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */ -#define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */ - -/* PHY Extended Registers */ -#define PHY_REG_STS 0x10 /* Status Register */ -#define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */ -#define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */ -#define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */ -#define PHY_REG_RECR 0x15 /* Receive Error Counter */ -#define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */ -#define PHY_REG_RBR 0x17 /* RMII and Bypass Register */ -#define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */ -#define PHY_REG_PHYCR 0x19 /* PHY Control Register */ -#define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */ -#define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */ -#define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */ - -#define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */ -#define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */ -#define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */ -#define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */ -#define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */ - -#define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */ -#define DP83848C_ID 0x20005C90 /* PHY Identifier */ - -// prototypes -portBASE_TYPE Init_EMAC(void); -unsigned short ReadFrameBE_EMAC(void); -void CopyToFrame_EMAC(void *Source, unsigned int Size); -void CopyFromFrame_EMAC(void *Dest, unsigned short Size); -void DummyReadFrame_EMAC(unsigned short Size); -unsigned short StartReadFrame(void); -void EndReadFrame(void); -unsigned int CheckFrameReceived(void); -void RequestSend(void); -unsigned int Rdy4Tx(void); -void DoSend_EMAC(unsigned short FrameSize); -void vEMACWaitForInput( void ); -unsigned int uiGetEMACRxData( unsigned char *ucBuffer ); - - -#endif - -/*---------------------------------------------------------------------------- - * end of file - *---------------------------------------------------------------------------*/ - diff --git a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c index da81da5ce..9cfe47471 100644 --- a/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c +++ b/Demo/CORTEX_LPC1768_GCC_Rowley/webserver/uIP_Task.c @@ -66,6 +66,7 @@ /* Demo includes. */ #include "emac.h" +#include "EthDev_LPC17xx.h" #include "LED.h" #include "LPC17xx.h" @@ -81,7 +82,6 @@ /* Standard constant. */ #define uipTOTAL_FRAME_HEADER_SIZE 54 - /*-----------------------------------------------------------*/ /*