From: Dave Gerlach Date: Sat, 17 Mar 2018 07:54:30 +0000 (+0530) Subject: am43xx: Do not allow EMIF to control DDR_RESET in rtconly config X-Git-Tag: v2018.05-rc2~102 X-Git-Url: https://git.sur5r.net/?a=commitdiff_plain;h=e18945ad22eb2a8baad1a2dbc8c541411ac9528b;p=u-boot am43xx: Do not allow EMIF to control DDR_RESET in rtconly config Prevent EMIF control of DDR_RESET line on DDR3 am43xx platforms for am43xx_evm_rtconly_config. Without this DDR is unstable and can become corrupted after multiple iterations of RTC+DDR mode. Signed-off-by: Dave Gerlach [j-keerthy@ti.com Ported to latest master branch] Signed-off-by: Keerthy Reviewed-by: Tom Rini --- diff --git a/arch/arm/mach-omap2/am33xx/emif4.c b/arch/arm/mach-omap2/am33xx/emif4.c index 68c7705178..9b429c9262 100644 --- a/arch/arm/mach-omap2/am33xx/emif4.c +++ b/arch/arm/mach-omap2/am33xx/emif4.c @@ -95,8 +95,13 @@ void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, writel(DDR_CKE_CTRL_NORMAL, &ddrctrl->ddrckectrl); if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) +#ifndef CONFIG_SPL_RTC_DDR_SUPPORT /* Allow EMIF to control DDR_RESET */ writel(0x00000000, &ddrctrl->ddrioctrl); +#else + /* Override EMIF DDR_RESET control */ + writel(0x80000000, &ddrctrl->ddrioctrl); +#endif /* CONFIG_SPL_RTC_DDR_SUPPORT */ #endif /* Program EMIF instance */